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// megafunction wizard: %FIFO%CBX% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: dcfifo // ============================================================ // File Name: fifo_2k.v // Megafunction Name(s): // dcfifo // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition // ************************************************************ //Copyright (C) 1991-2005 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. //dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=11 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END //a_gray2bin device_family="Cyclone" WIDTH=11 bin gray //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END //synthesis_resources = //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_a_gray2bin_8m4 ( bin, gray) /* synthesis synthesis_clearbox=1 */; output [10:0] bin; input [10:0] gray; wire xor0; wire xor1; wire xor2; wire xor3; wire xor4; wire xor5; wire xor6; wire xor7; wire xor8; wire xor9; assign bin = {gray[10], xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0}, xor0 = (gray[0] ^ xor1), xor1 = (gray[1] ^ xor2), xor2 = (gray[2] ^ xor3), xor3 = (gray[3] ^ xor4), xor4 = (gray[4] ^ xor5), xor5 = (gray[5] ^ xor6), xor6 = (gray[6] ^ xor7), xor7 = (gray[7] ^ xor8), xor8 = (gray[8] ^ xor9), xor9 = (gray[10] ^ gray[9]); endmodule //fifo_2k_a_gray2bin_8m4 //a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=11 aclr clock cnt_en q //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END //synthesis_resources = lut 12 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_a_graycounter_726 ( aclr, clock, cnt_en, q) /* synthesis synthesis_clearbox=1 */; input aclr; input clock; input cnt_en; output [10:0] q; wire [0:0] wire_countera_0cout; wire [0:0] wire_countera_1cout; wire [0:0] wire_countera_2cout; wire [0:0] wire_countera_3cout; wire [0:0] wire_countera_4cout; wire [0:0] wire_countera_5cout; wire [0:0] wire_countera_6cout; wire [0:0] wire_countera_7cout; wire [0:0] wire_countera_8cout; wire [0:0] wire_countera_9cout; wire [10:0] wire_countera_regout; wire wire_parity_cout; wire wire_parity_regout; wire [10:0] power_modified_counter_values; wire sclr; wire updown; cyclone_lcell countera_0 ( .aclr(aclr), .cin(wire_parity_cout), .clk(clock), .combout(), .cout(wire_countera_0cout[0:0]), .dataa(cnt_en), .datab(wire_countera_regout[0:0]), .ena(1'b1), .regout(wire_countera_regout[0:0]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_0.cin_used = "true", countera_0.lut_mask = "c6a0", countera_0.operation_mode = "arithmetic", countera_0.sum_lutc_input = "cin", countera_0.synch_mode = "on", countera_0.lpm_type = "cyclone_lcell"; cyclone_lcell countera_1 ( .aclr(aclr), .cin(wire_countera_0cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_1cout[0:0]), .dataa(power_modified_counter_values[0]), .datab(power_modified_counter_values[1]), .ena(1'b1), .regout(wire_countera_regout[1:1]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_1.cin_used = "true", countera_1.lut_mask = "6c50", countera_1.operation_mode = "arithmetic", countera_1.sum_lutc_input = "cin", countera_1.synch_mode = "on", countera_1.lpm_type = "cyclone_lcell"; cyclone_lcell countera_2 ( .aclr(aclr), .cin(wire_countera_1cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_2cout[0:0]), .dataa(power_modified_counter_values[1]), .datab(power_modified_counter_values[2]), .ena(1'b1), .regout(wire_countera_regout[2:2]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_2.cin_used = "true", countera_2.lut_mask = "6c50", countera_2.operation_mode = "arithmetic", countera_2.sum_lutc_input = "cin", countera_2.synch_mode = "on", countera_2.lpm_type = "cyclone_lcell"; cyclone_lcell countera_3 ( .aclr(aclr), .cin(wire_countera_2cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_3cout[0:0]), .dataa(power_modified_counter_values[2]), .datab(power_modified_counter_values[3]), .ena(1'b1), .regout(wire_countera_regout[3:3]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_3.cin_used = "true", countera_3.lut_mask = "6c50", countera_3.operation_mode = "arithmetic", countera_3.sum_lutc_input = "cin", countera_3.synch_mode = "on", countera_3.lpm_type = "cyclone_lcell"; cyclone_lcell countera_4 ( .aclr(aclr), .cin(wire_countera_3cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_4cout[0:0]), .dataa(power_modified_counter_values[3]), .datab(power_modified_counter_values[4]), .ena(1'b1), .regout(wire_countera_regout[4:4]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_4.cin_used = "true", countera_4.lut_mask = "6c50", countera_4.operation_mode = "arithmetic", countera_4.sum_lutc_input = "cin", countera_4.synch_mode = "on", countera_4.lpm_type = "cyclone_lcell"; cyclone_lcell countera_5 ( .aclr(aclr), .cin(wire_countera_4cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_5cout[0:0]), .dataa(power_modified_counter_values[4]), .datab(power_modified_counter_values[5]), .ena(1'b1), .regout(wire_countera_regout[5:5]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_5.cin_used = "true", countera_5.lut_mask = "6c50", countera_5.operation_mode = "arithmetic", countera_5.sum_lutc_input = "cin", countera_5.synch_mode = "on", countera_5.lpm_type = "cyclone_lcell"; cyclone_lcell countera_6 ( .aclr(aclr), .cin(wire_countera_5cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_6cout[0:0]), .dataa(power_modified_counter_values[5]), .datab(power_modified_counter_values[6]), .ena(1'b1), .regout(wire_countera_regout[6:6]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_6.cin_used = "true", countera_6.lut_mask = "6c50", countera_6.operation_mode = "arithmetic", countera_6.sum_lutc_input = "cin", countera_6.synch_mode = "on", countera_6.lpm_type = "cyclone_lcell"; cyclone_lcell countera_7 ( .aclr(aclr), .cin(wire_countera_6cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_7cout[0:0]), .dataa(power_modified_counter_values[6]), .datab(power_modified_counter_values[7]), .ena(1'b1), .regout(wire_countera_regout[7:7]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_7.cin_used = "true", countera_7.lut_mask = "6c50", countera_7.operation_mode = "arithmetic", countera_7.sum_lutc_input = "cin", countera_7.synch_mode = "on", countera_7.lpm_type = "cyclone_lcell"; cyclone_lcell countera_8 ( .aclr(aclr), .cin(wire_countera_7cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_8cout[0:0]), .dataa(power_modified_counter_values[7]), .datab(power_modified_counter_values[8]), .ena(1'b1), .regout(wire_countera_regout[8:8]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_8.cin_used = "true", countera_8.lut_mask = "6c50", countera_8.operation_mode = "arithmetic", countera_8.sum_lutc_input = "cin", countera_8.synch_mode = "on", countera_8.lpm_type = "cyclone_lcell"; cyclone_lcell countera_9 ( .aclr(aclr), .cin(wire_countera_8cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_9cout[0:0]), .dataa(power_modified_counter_values[8]), .datab(power_modified_counter_values[9]), .ena(1'b1), .regout(wire_countera_regout[9:9]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_9.cin_used = "true", countera_9.lut_mask = "6c50", countera_9.operation_mode = "arithmetic", countera_9.sum_lutc_input = "cin", countera_9.synch_mode = "on", countera_9.lpm_type = "cyclone_lcell"; cyclone_lcell countera_10 ( .aclr(aclr), .cin(wire_countera_9cout[0:0]), .clk(clock), .combout(), .cout(), .dataa(power_modified_counter_values[10]), .ena(1'b1), .regout(wire_countera_regout[10:10]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datab(1'b1), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_10.cin_used = "true", countera_10.lut_mask = "5a5a", countera_10.operation_mode = "normal", countera_10.sum_lutc_input = "cin", countera_10.synch_mode = "on", countera_10.lpm_type = "cyclone_lcell"; cyclone_lcell parity ( .aclr(aclr), .cin(updown), .clk(clock), .combout(), .cout(wire_parity_cout), .dataa(cnt_en), .datab(wire_parity_regout), .ena(1'b1), .regout(wire_parity_regout), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam parity.cin_used = "true", parity.lut_mask = "6682", parity.operation_mode = "arithmetic", parity.synch_mode = "on", parity.lpm_type = "cyclone_lcell"; assign power_modified_counter_values = {wire_countera_regout[10:0]}, q = power_modified_counter_values, sclr = 1'b0, updown = 1'b1; endmodule //fifo_2k_a_graycounter_726 //a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=11 aclr clock cnt_en q //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END //synthesis_resources = lut 12 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_a_graycounter_2r6 ( aclr, clock, cnt_en, q) /* synthesis synthesis_clearbox=1 */; input aclr; input clock; input cnt_en; output [10:0] q; wire [0:0] wire_countera_0cout; wire [0:0] wire_countera_1cout; wire [0:0] wire_countera_2cout; wire [0:0] wire_countera_3cout; wire [0:0] wire_countera_4cout; wire [0:0] wire_countera_5cout; wire [0:0] wire_countera_6cout; wire [0:0] wire_countera_7cout; wire [0:0] wire_countera_8cout; wire [0:0] wire_countera_9cout; wire [10:0] wire_countera_regout; wire wire_parity_cout; wire wire_parity_regout; wire [10:0] power_modified_counter_values; wire sclr; wire updown; cyclone_lcell countera_0 ( .aclr(aclr), .cin(wire_parity_cout), .clk(clock), .combout(), .cout(wire_countera_0cout[0:0]), .dataa(cnt_en), .datab(wire_countera_regout[0:0]), .ena(1'b1), .regout(wire_countera_regout[0:0]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_0.cin_used = "true", countera_0.lut_mask = "c6a0", countera_0.operation_mode = "arithmetic", countera_0.sum_lutc_input = "cin", countera_0.synch_mode = "on", countera_0.lpm_type = "cyclone_lcell"; cyclone_lcell countera_1 ( .aclr(aclr), .cin(wire_countera_0cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_1cout[0:0]), .dataa(power_modified_counter_values[0]), .datab(power_modified_counter_values[1]), .ena(1'b1), .regout(wire_countera_regout[1:1]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_1.cin_used = "true", countera_1.lut_mask = "6c50", countera_1.operation_mode = "arithmetic", countera_1.sum_lutc_input = "cin", countera_1.synch_mode = "on", countera_1.lpm_type = "cyclone_lcell"; cyclone_lcell countera_2 ( .aclr(aclr), .cin(wire_countera_1cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_2cout[0:0]), .dataa(power_modified_counter_values[1]), .datab(power_modified_counter_values[2]), .ena(1'b1), .regout(wire_countera_regout[2:2]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_2.cin_used = "true", countera_2.lut_mask = "6c50", countera_2.operation_mode = "arithmetic", countera_2.sum_lutc_input = "cin", countera_2.synch_mode = "on", countera_2.lpm_type = "cyclone_lcell"; cyclone_lcell countera_3 ( .aclr(aclr), .cin(wire_countera_2cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_3cout[0:0]), .dataa(power_modified_counter_values[2]), .datab(power_modified_counter_values[3]), .ena(1'b1), .regout(wire_countera_regout[3:3]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_3.cin_used = "true", countera_3.lut_mask = "6c50", countera_3.operation_mode = "arithmetic", countera_3.sum_lutc_input = "cin", countera_3.synch_mode = "on", countera_3.lpm_type = "cyclone_lcell"; cyclone_lcell countera_4 ( .aclr(aclr), .cin(wire_countera_3cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_4cout[0:0]), .dataa(power_modified_counter_values[3]), .datab(power_modified_counter_values[4]), .ena(1'b1), .regout(wire_countera_regout[4:4]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_4.cin_used = "true", countera_4.lut_mask = "6c50", countera_4.operation_mode = "arithmetic", countera_4.sum_lutc_input = "cin", countera_4.synch_mode = "on", countera_4.lpm_type = "cyclone_lcell"; cyclone_lcell countera_5 ( .aclr(aclr), .cin(wire_countera_4cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_5cout[0:0]), .dataa(power_modified_counter_values[4]), .datab(power_modified_counter_values[5]), .ena(1'b1), .regout(wire_countera_regout[5:5]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_5.cin_used = "true", countera_5.lut_mask = "6c50", countera_5.operation_mode = "arithmetic", countera_5.sum_lutc_input = "cin", countera_5.synch_mode = "on", countera_5.lpm_type = "cyclone_lcell"; cyclone_lcell countera_6 ( .aclr(aclr), .cin(wire_countera_5cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_6cout[0:0]), .dataa(power_modified_counter_values[5]), .datab(power_modified_counter_values[6]), .ena(1'b1), .regout(wire_countera_regout[6:6]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_6.cin_used = "true", countera_6.lut_mask = "6c50", countera_6.operation_mode = "arithmetic", countera_6.sum_lutc_input = "cin", countera_6.synch_mode = "on", countera_6.lpm_type = "cyclone_lcell"; cyclone_lcell countera_7 ( .aclr(aclr), .cin(wire_countera_6cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_7cout[0:0]), .dataa(power_modified_counter_values[6]), .datab(power_modified_counter_values[7]), .ena(1'b1), .regout(wire_countera_regout[7:7]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_7.cin_used = "true", countera_7.lut_mask = "6c50", countera_7.operation_mode = "arithmetic", countera_7.sum_lutc_input = "cin", countera_7.synch_mode = "on", countera_7.lpm_type = "cyclone_lcell"; cyclone_lcell countera_8 ( .aclr(aclr), .cin(wire_countera_7cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_8cout[0:0]), .dataa(power_modified_counter_values[7]), .datab(power_modified_counter_values[8]), .ena(1'b1), .regout(wire_countera_regout[8:8]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_8.cin_used = "true", countera_8.lut_mask = "6c50", countera_8.operation_mode = "arithmetic", countera_8.sum_lutc_input = "cin", countera_8.synch_mode = "on", countera_8.lpm_type = "cyclone_lcell"; cyclone_lcell countera_9 ( .aclr(aclr), .cin(wire_countera_8cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_9cout[0:0]), .dataa(power_modified_counter_values[8]), .datab(power_modified_counter_values[9]), .ena(1'b1), .regout(wire_countera_regout[9:9]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_9.cin_used = "true", countera_9.lut_mask = "6c50", countera_9.operation_mode = "arithmetic", countera_9.sum_lutc_input = "cin", countera_9.synch_mode = "on", countera_9.lpm_type = "cyclone_lcell"; cyclone_lcell countera_10 ( .aclr(aclr), .cin(wire_countera_9cout[0:0]), .clk(clock), .combout(), .cout(), .dataa(power_modified_counter_values[10]), .ena(1'b1), .regout(wire_countera_regout[10:10]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datab(1'b1), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_10.cin_used = "true", countera_10.lut_mask = "5a5a", countera_10.operation_mode = "normal", countera_10.sum_lutc_input = "cin", countera_10.synch_mode = "on", countera_10.lpm_type = "cyclone_lcell"; cyclone_lcell parity ( .aclr(aclr), .cin(updown), .clk(clock), .combout(), .cout(wire_parity_cout), .dataa(cnt_en), .datab((~ wire_parity_regout)), .ena(1'b1), .regout(wire_parity_regout), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam parity.cin_used = "true", parity.lut_mask = "9982", parity.operation_mode = "arithmetic", parity.synch_mode = "on", parity.lpm_type = "cyclone_lcell"; assign power_modified_counter_values = {wire_countera_regout[10:1], (~ wire_countera_regout[0])}, q = power_modified_counter_values, sclr = 1'b0, updown = 1'b1; endmodule //fifo_2k_a_graycounter_2r6 //altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a //VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END //synthesis_resources = M4K 8 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_altsyncram_6pl ( address_a, address_b, clock0, clock1, clocken1, data_a, q_b, wren_a) /* synthesis synthesis_clearbox=1 */; input [10:0] address_a; input [10:0] address_b; input clock0; input clock1; input clocken1; input [15:0] data_a; output [15:0] q_b; input wren_a; wire [0:0] wire_ram_block3a_0portbdataout; wire [0:0] wire_ram_block3a_1portbdataout; wire [0:0] wire_ram_block3a_2portbdataout; wire [0:0] wire_ram_block3a_3portbdataout; wire [0:0] wire_ram_block3a_4portbdataout; wire [0:0] wire_ram_block3a_5portbdataout; wire [0:0] wire_ram_block3a_6portbdataout; wire [0:0] wire_ram_block3a_7portbdataout; wire [0:0] wire_ram_block3a_8portbdataout; wire [0:0] wire_ram_block3a_9portbdataout; wire [0:0] wire_ram_block3a_10portbdataout; wire [0:0] wire_ram_block3a_11portbdataout; wire [0:0] wire_ram_block3a_12portbdataout; wire [0:0] wire_ram_block3a_13portbdataout; wire [0:0] wire_ram_block3a_14portbdataout; wire [0:0] wire_ram_block3a_15portbdataout; wire [10:0] address_a_wire; wire [10:0] address_b_wire; cyclone_ram_block ram_block3a_0 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[0]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_0portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_0.connectivity_checking = "OFF", ram_block3a_0.logical_ram_name = "ALTSYNCRAM", ram_block3a_0.mixed_port_feed_through_mode = "dont_care", ram_block3a_0.operation_mode = "dual_port", ram_block3a_0.port_a_address_width = 11, ram_block3a_0.port_a_data_width = 1, ram_block3a_0.port_a_first_address = 0, ram_block3a_0.port_a_first_bit_number = 0, ram_block3a_0.port_a_last_address = 2047, ram_block3a_0.port_a_logical_ram_depth = 2048, ram_block3a_0.port_a_logical_ram_width = 16, ram_block3a_0.port_b_address_clear = "none", ram_block3a_0.port_b_address_clock = "clock1", ram_block3a_0.port_b_address_width = 11, ram_block3a_0.port_b_data_out_clear = "none", ram_block3a_0.port_b_data_out_clock = "none", ram_block3a_0.port_b_data_width = 1, ram_block3a_0.port_b_first_address = 0, ram_block3a_0.port_b_first_bit_number = 0, ram_block3a_0.port_b_last_address = 2047, ram_block3a_0.port_b_logical_ram_depth = 2048, ram_block3a_0.port_b_logical_ram_width = 16, ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_0.ram_block_type = "auto", ram_block3a_0.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_1 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[1]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_1portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_1.connectivity_checking = "OFF", ram_block3a_1.logical_ram_name = "ALTSYNCRAM", ram_block3a_1.mixed_port_feed_through_mode = "dont_care", ram_block3a_1.operation_mode = "dual_port", ram_block3a_1.port_a_address_width = 11, ram_block3a_1.port_a_data_width = 1, ram_block3a_1.port_a_first_address = 0, ram_block3a_1.port_a_first_bit_number = 1, ram_block3a_1.port_a_last_address = 2047, ram_block3a_1.port_a_logical_ram_depth = 2048, ram_block3a_1.port_a_logical_ram_width = 16, ram_block3a_1.port_b_address_clear = "none", ram_block3a_1.port_b_address_clock = "clock1", ram_block3a_1.port_b_address_width = 11, ram_block3a_1.port_b_data_out_clear = "none", ram_block3a_1.port_b_data_out_clock = "none", ram_block3a_1.port_b_data_width = 1, ram_block3a_1.port_b_first_address = 0, ram_block3a_1.port_b_first_bit_number = 1, ram_block3a_1.port_b_last_address = 2047, ram_block3a_1.port_b_logical_ram_depth = 2048, ram_block3a_1.port_b_logical_ram_width = 16, ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_1.ram_block_type = "auto", ram_block3a_1.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_2 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[2]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_2portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_2.connectivity_checking = "OFF", ram_block3a_2.logical_ram_name = "ALTSYNCRAM", ram_block3a_2.mixed_port_feed_through_mode = "dont_care", ram_block3a_2.operation_mode = "dual_port", ram_block3a_2.port_a_address_width = 11, ram_block3a_2.port_a_data_width = 1, ram_block3a_2.port_a_first_address = 0, ram_block3a_2.port_a_first_bit_number = 2, ram_block3a_2.port_a_last_address = 2047, ram_block3a_2.port_a_logical_ram_depth = 2048, ram_block3a_2.port_a_logical_ram_width = 16, ram_block3a_2.port_b_address_clear = "none", ram_block3a_2.port_b_address_clock = "clock1", ram_block3a_2.port_b_address_width = 11, ram_block3a_2.port_b_data_out_clear = "none", ram_block3a_2.port_b_data_out_clock = "none", ram_block3a_2.port_b_data_width = 1, ram_block3a_2.port_b_first_address = 0, ram_block3a_2.port_b_first_bit_number = 2, ram_block3a_2.port_b_last_address = 2047, ram_block3a_2.port_b_logical_ram_depth = 2048, ram_block3a_2.port_b_logical_ram_width = 16, ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_2.ram_block_type = "auto", ram_block3a_2.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_3 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[3]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_3portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_3.connectivity_checking = "OFF", ram_block3a_3.logical_ram_name = "ALTSYNCRAM", ram_block3a_3.mixed_port_feed_through_mode = "dont_care", ram_block3a_3.operation_mode = "dual_port", ram_block3a_3.port_a_address_width = 11, ram_block3a_3.port_a_data_width = 1, ram_block3a_3.port_a_first_address = 0, ram_block3a_3.port_a_first_bit_number = 3, ram_block3a_3.port_a_last_address = 2047, ram_block3a_3.port_a_logical_ram_depth = 2048, ram_block3a_3.port_a_logical_ram_width = 16, ram_block3a_3.port_b_address_clear = "none", ram_block3a_3.port_b_address_clock = "clock1", ram_block3a_3.port_b_address_width = 11, ram_block3a_3.port_b_data_out_clear = "none", ram_block3a_3.port_b_data_out_clock = "none", ram_block3a_3.port_b_data_width = 1, ram_block3a_3.port_b_first_address = 0, ram_block3a_3.port_b_first_bit_number = 3, ram_block3a_3.port_b_last_address = 2047, ram_block3a_3.port_b_logical_ram_depth = 2048, ram_block3a_3.port_b_logical_ram_width = 16, ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_3.ram_block_type = "auto", ram_block3a_3.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_4 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[4]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_4portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_4.connectivity_checking = "OFF", ram_block3a_4.logical_ram_name = "ALTSYNCRAM", ram_block3a_4.mixed_port_feed_through_mode = "dont_care", ram_block3a_4.operation_mode = "dual_port", ram_block3a_4.port_a_address_width = 11, ram_block3a_4.port_a_data_width = 1, ram_block3a_4.port_a_first_address = 0, ram_block3a_4.port_a_first_bit_number = 4, ram_block3a_4.port_a_last_address = 2047, ram_block3a_4.port_a_logical_ram_depth = 2048, ram_block3a_4.port_a_logical_ram_width = 16, ram_block3a_4.port_b_address_clear = "none", ram_block3a_4.port_b_address_clock = "clock1", ram_block3a_4.port_b_address_width = 11, ram_block3a_4.port_b_data_out_clear = "none", ram_block3a_4.port_b_data_out_clock = "none", ram_block3a_4.port_b_data_width = 1, ram_block3a_4.port_b_first_address = 0, ram_block3a_4.port_b_first_bit_number = 4, ram_block3a_4.port_b_last_address = 2047, ram_block3a_4.port_b_logical_ram_depth = 2048, ram_block3a_4.port_b_logical_ram_width = 16, ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_4.ram_block_type = "auto", ram_block3a_4.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_5 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[5]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_5portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_5.connectivity_checking = "OFF", ram_block3a_5.logical_ram_name = "ALTSYNCRAM", ram_block3a_5.mixed_port_feed_through_mode = "dont_care", ram_block3a_5.operation_mode = "dual_port", ram_block3a_5.port_a_address_width = 11, ram_block3a_5.port_a_data_width = 1, ram_block3a_5.port_a_first_address = 0, ram_block3a_5.port_a_first_bit_number = 5, ram_block3a_5.port_a_last_address = 2047, ram_block3a_5.port_a_logical_ram_depth = 2048, ram_block3a_5.port_a_logical_ram_width = 16, ram_block3a_5.port_b_address_clear = "none", ram_block3a_5.port_b_address_clock = "clock1", ram_block3a_5.port_b_address_width = 11, ram_block3a_5.port_b_data_out_clear = "none", ram_block3a_5.port_b_data_out_clock = "none", ram_block3a_5.port_b_data_width = 1, ram_block3a_5.port_b_first_address = 0, ram_block3a_5.port_b_first_bit_number = 5, ram_block3a_5.port_b_last_address = 2047, ram_block3a_5.port_b_logical_ram_depth = 2048, ram_block3a_5.port_b_logical_ram_width = 16, ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_5.ram_block_type = "auto", ram_block3a_5.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_6 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[6]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_6portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_6.connectivity_checking = "OFF", ram_block3a_6.logical_ram_name = "ALTSYNCRAM", ram_block3a_6.mixed_port_feed_through_mode = "dont_care", ram_block3a_6.operation_mode = "dual_port", ram_block3a_6.port_a_address_width = 11, ram_block3a_6.port_a_data_width = 1, ram_block3a_6.port_a_first_address = 0, ram_block3a_6.port_a_first_bit_number = 6, ram_block3a_6.port_a_last_address = 2047, ram_block3a_6.port_a_logical_ram_depth = 2048, ram_block3a_6.port_a_logical_ram_width = 16, ram_block3a_6.port_b_address_clear = "none", ram_block3a_6.port_b_address_clock = "clock1", ram_block3a_6.port_b_address_width = 11, ram_block3a_6.port_b_data_out_clear = "none", ram_block3a_6.port_b_data_out_clock = "none", ram_block3a_6.port_b_data_width = 1, ram_block3a_6.port_b_first_address = 0, ram_block3a_6.port_b_first_bit_number = 6, ram_block3a_6.port_b_last_address = 2047, ram_block3a_6.port_b_logical_ram_depth = 2048, ram_block3a_6.port_b_logical_ram_width = 16, ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_6.ram_block_type = "auto", ram_block3a_6.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_7 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[7]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_7portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_7.connectivity_checking = "OFF", ram_block3a_7.logical_ram_name = "ALTSYNCRAM", ram_block3a_7.mixed_port_feed_through_mode = "dont_care", ram_block3a_7.operation_mode = "dual_port", ram_block3a_7.port_a_address_width = 11, ram_block3a_7.port_a_data_width = 1, ram_block3a_7.port_a_first_address = 0, ram_block3a_7.port_a_first_bit_number = 7, ram_block3a_7.port_a_last_address = 2047, ram_block3a_7.port_a_logical_ram_depth = 2048, ram_block3a_7.port_a_logical_ram_width = 16, ram_block3a_7.port_b_address_clear = "none", ram_block3a_7.port_b_address_clock = "clock1", ram_block3a_7.port_b_address_width = 11, ram_block3a_7.port_b_data_out_clear = "none", ram_block3a_7.port_b_data_out_clock = "none", ram_block3a_7.port_b_data_width = 1, ram_block3a_7.port_b_first_address = 0, ram_block3a_7.port_b_first_bit_number = 7, ram_block3a_7.port_b_last_address = 2047, ram_block3a_7.port_b_logical_ram_depth = 2048, ram_block3a_7.port_b_logical_ram_width = 16, ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_7.ram_block_type = "auto", ram_block3a_7.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_8 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[8]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_8portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_8.connectivity_checking = "OFF", ram_block3a_8.logical_ram_name = "ALTSYNCRAM", ram_block3a_8.mixed_port_feed_through_mode = "dont_care", ram_block3a_8.operation_mode = "dual_port", ram_block3a_8.port_a_address_width = 11, ram_block3a_8.port_a_data_width = 1, ram_block3a_8.port_a_first_address = 0, ram_block3a_8.port_a_first_bit_number = 8, ram_block3a_8.port_a_last_address = 2047, ram_block3a_8.port_a_logical_ram_depth = 2048, ram_block3a_8.port_a_logical_ram_width = 16, ram_block3a_8.port_b_address_clear = "none", ram_block3a_8.port_b_address_clock = "clock1", ram_block3a_8.port_b_address_width = 11, ram_block3a_8.port_b_data_out_clear = "none", ram_block3a_8.port_b_data_out_clock = "none", ram_block3a_8.port_b_data_width = 1, ram_block3a_8.port_b_first_address = 0, ram_block3a_8.port_b_first_bit_number = 8, ram_block3a_8.port_b_last_address = 2047, ram_block3a_8.port_b_logical_ram_depth = 2048, ram_block3a_8.port_b_logical_ram_width = 16, ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_8.ram_block_type = "auto", ram_block3a_8.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_9 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[9]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_9portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_9.connectivity_checking = "OFF", ram_block3a_9.logical_ram_name = "ALTSYNCRAM", ram_block3a_9.mixed_port_feed_through_mode = "dont_care", ram_block3a_9.operation_mode = "dual_port", ram_block3a_9.port_a_address_width = 11, ram_block3a_9.port_a_data_width = 1, ram_block3a_9.port_a_first_address = 0, ram_block3a_9.port_a_first_bit_number = 9, ram_block3a_9.port_a_last_address = 2047, ram_block3a_9.port_a_logical_ram_depth = 2048, ram_block3a_9.port_a_logical_ram_width = 16, ram_block3a_9.port_b_address_clear = "none", ram_block3a_9.port_b_address_clock = "clock1", ram_block3a_9.port_b_address_width = 11, ram_block3a_9.port_b_data_out_clear = "none", ram_block3a_9.port_b_data_out_clock = "none", ram_block3a_9.port_b_data_width = 1, ram_block3a_9.port_b_first_address = 0, ram_block3a_9.port_b_first_bit_number = 9, ram_block3a_9.port_b_last_address = 2047, ram_block3a_9.port_b_logical_ram_depth = 2048, ram_block3a_9.port_b_logical_ram_width = 16, ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_9.ram_block_type = "auto", ram_block3a_9.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_10 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[10]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_10portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_10.connectivity_checking = "OFF", ram_block3a_10.logical_ram_name = "ALTSYNCRAM", ram_block3a_10.mixed_port_feed_through_mode = "dont_care", ram_block3a_10.operation_mode = "dual_port", ram_block3a_10.port_a_address_width = 11, ram_block3a_10.port_a_data_width = 1, ram_block3a_10.port_a_first_address = 0, ram_block3a_10.port_a_first_bit_number = 10, ram_block3a_10.port_a_last_address = 2047, ram_block3a_10.port_a_logical_ram_depth = 2048, ram_block3a_10.port_a_logical_ram_width = 16, ram_block3a_10.port_b_address_clear = "none", ram_block3a_10.port_b_address_clock = "clock1", ram_block3a_10.port_b_address_width = 11, ram_block3a_10.port_b_data_out_clear = "none", ram_block3a_10.port_b_data_out_clock = "none", ram_block3a_10.port_b_data_width = 1, ram_block3a_10.port_b_first_address = 0, ram_block3a_10.port_b_first_bit_number = 10, ram_block3a_10.port_b_last_address = 2047, ram_block3a_10.port_b_logical_ram_depth = 2048, ram_block3a_10.port_b_logical_ram_width = 16, ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_10.ram_block_type = "auto", ram_block3a_10.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_11 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[11]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_11portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_11.connectivity_checking = "OFF", ram_block3a_11.logical_ram_name = "ALTSYNCRAM", ram_block3a_11.mixed_port_feed_through_mode = "dont_care", ram_block3a_11.operation_mode = "dual_port", ram_block3a_11.port_a_address_width = 11, ram_block3a_11.port_a_data_width = 1, ram_block3a_11.port_a_first_address = 0, ram_block3a_11.port_a_first_bit_number = 11, ram_block3a_11.port_a_last_address = 2047, ram_block3a_11.port_a_logical_ram_depth = 2048, ram_block3a_11.port_a_logical_ram_width = 16, ram_block3a_11.port_b_address_clear = "none", ram_block3a_11.port_b_address_clock = "clock1", ram_block3a_11.port_b_address_width = 11, ram_block3a_11.port_b_data_out_clear = "none", ram_block3a_11.port_b_data_out_clock = "none", ram_block3a_11.port_b_data_width = 1, ram_block3a_11.port_b_first_address = 0, ram_block3a_11.port_b_first_bit_number = 11, ram_block3a_11.port_b_last_address = 2047, ram_block3a_11.port_b_logical_ram_depth = 2048, ram_block3a_11.port_b_logical_ram_width = 16, ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_11.ram_block_type = "auto", ram_block3a_11.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_12 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[12]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_12portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_12.connectivity_checking = "OFF", ram_block3a_12.logical_ram_name = "ALTSYNCRAM", ram_block3a_12.mixed_port_feed_through_mode = "dont_care", ram_block3a_12.operation_mode = "dual_port", ram_block3a_12.port_a_address_width = 11, ram_block3a_12.port_a_data_width = 1, ram_block3a_12.port_a_first_address = 0, ram_block3a_12.port_a_first_bit_number = 12, ram_block3a_12.port_a_last_address = 2047, ram_block3a_12.port_a_logical_ram_depth = 2048, ram_block3a_12.port_a_logical_ram_width = 16, ram_block3a_12.port_b_address_clear = "none", ram_block3a_12.port_b_address_clock = "clock1", ram_block3a_12.port_b_address_width = 11, ram_block3a_12.port_b_data_out_clear = "none", ram_block3a_12.port_b_data_out_clock = "none", ram_block3a_12.port_b_data_width = 1, ram_block3a_12.port_b_first_address = 0, ram_block3a_12.port_b_first_bit_number = 12, ram_block3a_12.port_b_last_address = 2047, ram_block3a_12.port_b_logical_ram_depth = 2048, ram_block3a_12.port_b_logical_ram_width = 16, ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_12.ram_block_type = "auto", ram_block3a_12.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_13 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[13]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_13portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_13.connectivity_checking = "OFF", ram_block3a_13.logical_ram_name = "ALTSYNCRAM", ram_block3a_13.mixed_port_feed_through_mode = "dont_care", ram_block3a_13.operation_mode = "dual_port", ram_block3a_13.port_a_address_width = 11, ram_block3a_13.port_a_data_width = 1, ram_block3a_13.port_a_first_address = 0, ram_block3a_13.port_a_first_bit_number = 13, ram_block3a_13.port_a_last_address = 2047, ram_block3a_13.port_a_logical_ram_depth = 2048, ram_block3a_13.port_a_logical_ram_width = 16, ram_block3a_13.port_b_address_clear = "none", ram_block3a_13.port_b_address_clock = "clock1", ram_block3a_13.port_b_address_width = 11, ram_block3a_13.port_b_data_out_clear = "none", ram_block3a_13.port_b_data_out_clock = "none", ram_block3a_13.port_b_data_width = 1, ram_block3a_13.port_b_first_address = 0, ram_block3a_13.port_b_first_bit_number = 13, ram_block3a_13.port_b_last_address = 2047, ram_block3a_13.port_b_logical_ram_depth = 2048, ram_block3a_13.port_b_logical_ram_width = 16, ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_13.ram_block_type = "auto", ram_block3a_13.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_14 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[14]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_14portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_14.connectivity_checking = "OFF", ram_block3a_14.logical_ram_name = "ALTSYNCRAM", ram_block3a_14.mixed_port_feed_through_mode = "dont_care", ram_block3a_14.operation_mode = "dual_port", ram_block3a_14.port_a_address_width = 11, ram_block3a_14.port_a_data_width = 1, ram_block3a_14.port_a_first_address = 0, ram_block3a_14.port_a_first_bit_number = 14, ram_block3a_14.port_a_last_address = 2047, ram_block3a_14.port_a_logical_ram_depth = 2048, ram_block3a_14.port_a_logical_ram_width = 16, ram_block3a_14.port_b_address_clear = "none", ram_block3a_14.port_b_address_clock = "clock1", ram_block3a_14.port_b_address_width = 11, ram_block3a_14.port_b_data_out_clear = "none", ram_block3a_14.port_b_data_out_clock = "none", ram_block3a_14.port_b_data_width = 1, ram_block3a_14.port_b_first_address = 0, ram_block3a_14.port_b_first_bit_number = 14, ram_block3a_14.port_b_last_address = 2047, ram_block3a_14.port_b_logical_ram_depth = 2048, ram_block3a_14.port_b_logical_ram_width = 16, ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_14.ram_block_type = "auto", ram_block3a_14.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_15 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[15]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_15portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_15.connectivity_checking = "OFF", ram_block3a_15.logical_ram_name = "ALTSYNCRAM", ram_block3a_15.mixed_port_feed_through_mode = "dont_care", ram_block3a_15.operation_mode = "dual_port", ram_block3a_15.port_a_address_width = 11, ram_block3a_15.port_a_data_width = 1, ram_block3a_15.port_a_first_address = 0, ram_block3a_15.port_a_first_bit_number = 15, ram_block3a_15.port_a_last_address = 2047, ram_block3a_15.port_a_logical_ram_depth = 2048, ram_block3a_15.port_a_logical_ram_width = 16, ram_block3a_15.port_b_address_clear = "none", ram_block3a_15.port_b_address_clock = "clock1", ram_block3a_15.port_b_address_width = 11, ram_block3a_15.port_b_data_out_clear = "none", ram_block3a_15.port_b_data_out_clock = "none", ram_block3a_15.port_b_data_width = 1, ram_block3a_15.port_b_first_address = 0, ram_block3a_15.port_b_first_bit_number = 15, ram_block3a_15.port_b_last_address = 2047, ram_block3a_15.port_b_logical_ram_depth = 2048, ram_block3a_15.port_b_logical_ram_width = 16, ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_15.ram_block_type = "auto", ram_block3a_15.lpm_type = "cyclone_ram_block"; assign address_a_wire = address_a, address_b_wire = address_b, q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]}; endmodule //fifo_2k_altsyncram_6pl //dffpipe DELAY=1 WIDTH=11 clock clrn d q //VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END //synthesis_resources = lut 11 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_dffpipe_ab3 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 */ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; input clock; input clrn; input [10:0] d; output [10:0] q; wire [10:0] wire_dffe4a_D; reg [10:0] dffe4a; wire ena; wire prn; wire sclr; // synopsys translate_off initial dffe4a[0:0] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[0:0] <= 1'b1; else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0; else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0]; // synopsys translate_off initial dffe4a[1:1] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[1:1] <= 1'b1; else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0; else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1]; // synopsys translate_off initial dffe4a[2:2] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[2:2] <= 1'b1; else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0; else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2]; // synopsys translate_off initial dffe4a[3:3] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[3:3] <= 1'b1; else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0; else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3]; // synopsys translate_off initial dffe4a[4:4] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[4:4] <= 1'b1; else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0; else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4]; // synopsys translate_off initial dffe4a[5:5] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[5:5] <= 1'b1; else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0; else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5]; // synopsys translate_off initial dffe4a[6:6] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[6:6] <= 1'b1; else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0; else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6]; // synopsys translate_off initial dffe4a[7:7] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[7:7] <= 1'b1; else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0; else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7]; // synopsys translate_off initial dffe4a[8:8] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[8:8] <= 1'b1; else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0; else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8]; // synopsys translate_off initial dffe4a[9:9] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[9:9] <= 1'b1; else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0; else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9]; // synopsys translate_off initial dffe4a[10:10] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[10:10] <= 1'b1; else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0; else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10]; assign wire_dffe4a_D = (d & {11{(~ sclr)}}); assign ena = 1'b1, prn = 1'b1, q = dffe4a, sclr = 1'b0; endmodule //fifo_2k_dffpipe_ab3 //dffpipe WIDTH=11 clock clrn d q //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END //dffpipe WIDTH=11 clock clrn d q //VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END //synthesis_resources = lut 11 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_dffpipe_dm2 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 */ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; input clock; input clrn; input [10:0] d; output [10:0] q; wire [10:0] wire_dffe6a_D; reg [10:0] dffe6a; wire ena; wire prn; wire sclr; // synopsys translate_off initial dffe6a[0:0] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[0:0] <= 1'b1; else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0; else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0]; // synopsys translate_off initial dffe6a[1:1] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[1:1] <= 1'b1; else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0; else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1]; // synopsys translate_off initial dffe6a[2:2] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[2:2] <= 1'b1; else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0; else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2]; // synopsys translate_off initial dffe6a[3:3] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[3:3] <= 1'b1; else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0; else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3]; // synopsys translate_off initial dffe6a[4:4] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[4:4] <= 1'b1; else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0; else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4]; // synopsys translate_off initial dffe6a[5:5] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[5:5] <= 1'b1; else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0; else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5]; // synopsys translate_off initial dffe6a[6:6] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[6:6] <= 1'b1; else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0; else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6]; // synopsys translate_off initial dffe6a[7:7] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[7:7] <= 1'b1; else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0; else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7]; // synopsys translate_off initial dffe6a[8:8] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[8:8] <= 1'b1; else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0; else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8]; // synopsys translate_off initial dffe6a[9:9] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[9:9] <= 1'b1; else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0; else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9]; // synopsys translate_off initial dffe6a[10:10] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[10:10] <= 1'b1; else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0; else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10]; assign wire_dffe6a_D = (d & {11{(~ sclr)}}); assign ena = 1'b1, prn = 1'b1, q = dffe6a, sclr = 1'b0; endmodule //fifo_2k_dffpipe_dm2 //synthesis_resources = lut 11 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_alt_synch_pipe_dm2 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 */ /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */; input clock; input clrn; input [10:0] d; output [10:0] q; wire [10:0] wire_dffpipe5_q; fifo_2k_dffpipe_dm2 dffpipe5 ( .clock(clock), .clrn(clrn), .d(d), .q(wire_dffpipe5_q)); assign q = wire_dffpipe5_q; endmodule //fifo_2k_alt_synch_pipe_dm2 //lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=11 dataa datab result //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END //synthesis_resources = lut 11 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_add_sub_a18 ( dataa, datab, result) /* synthesis synthesis_clearbox=1 */; input [10:0] dataa; input [10:0] datab; output [10:0] result; wire [10:0] wire_add_sub_cella_combout; wire [0:0] wire_add_sub_cella_0cout; wire [0:0] wire_add_sub_cella_1cout; wire [0:0] wire_add_sub_cella_2cout; wire [0:0] wire_add_sub_cella_3cout; wire [0:0] wire_add_sub_cella_4cout; wire [0:0] wire_add_sub_cella_5cout; wire [0:0] wire_add_sub_cella_6cout; wire [0:0] wire_add_sub_cella_7cout; wire [0:0] wire_add_sub_cella_8cout; wire [0:0] wire_add_sub_cella_9cout; wire [10:0] wire_add_sub_cella_dataa; wire [10:0] wire_add_sub_cella_datab; cyclone_lcell add_sub_cella_0 ( .cin(1'b1), .combout(wire_add_sub_cella_combout[0:0]), .cout(wire_add_sub_cella_0cout[0:0]), .dataa(wire_add_sub_cella_dataa[0:0]), .datab(wire_add_sub_cella_datab[0:0]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_0.cin_used = "true", add_sub_cella_0.lut_mask = "69b2", add_sub_cella_0.operation_mode = "arithmetic", add_sub_cella_0.sum_lutc_input = "cin", add_sub_cella_0.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_1 ( .cin(wire_add_sub_cella_0cout[0:0]), .combout(wire_add_sub_cella_combout[1:1]), .cout(wire_add_sub_cella_1cout[0:0]), .dataa(wire_add_sub_cella_dataa[1:1]), .datab(wire_add_sub_cella_datab[1:1]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_1.cin_used = "true", add_sub_cella_1.lut_mask = "69b2", add_sub_cella_1.operation_mode = "arithmetic", add_sub_cella_1.sum_lutc_input = "cin", add_sub_cella_1.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_2 ( .cin(wire_add_sub_cella_1cout[0:0]), .combout(wire_add_sub_cella_combout[2:2]), .cout(wire_add_sub_cella_2cout[0:0]), .dataa(wire_add_sub_cella_dataa[2:2]), .datab(wire_add_sub_cella_datab[2:2]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_2.cin_used = "true", add_sub_cella_2.lut_mask = "69b2", add_sub_cella_2.operation_mode = "arithmetic", add_sub_cella_2.sum_lutc_input = "cin", add_sub_cella_2.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_3 ( .cin(wire_add_sub_cella_2cout[0:0]), .combout(wire_add_sub_cella_combout[3:3]), .cout(wire_add_sub_cella_3cout[0:0]), .dataa(wire_add_sub_cella_dataa[3:3]), .datab(wire_add_sub_cella_datab[3:3]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_3.cin_used = "true", add_sub_cella_3.lut_mask = "69b2", add_sub_cella_3.operation_mode = "arithmetic", add_sub_cella_3.sum_lutc_input = "cin", add_sub_cella_3.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_4 ( .cin(wire_add_sub_cella_3cout[0:0]), .combout(wire_add_sub_cella_combout[4:4]), .cout(wire_add_sub_cella_4cout[0:0]), .dataa(wire_add_sub_cella_dataa[4:4]), .datab(wire_add_sub_cella_datab[4:4]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_4.cin_used = "true", add_sub_cella_4.lut_mask = "69b2", add_sub_cella_4.operation_mode = "arithmetic", add_sub_cella_4.sum_lutc_input = "cin", add_sub_cella_4.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_5 ( .cin(wire_add_sub_cella_4cout[0:0]), .combout(wire_add_sub_cella_combout[5:5]), .cout(wire_add_sub_cella_5cout[0:0]), .dataa(wire_add_sub_cella_dataa[5:5]), .datab(wire_add_sub_cella_datab[5:5]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_5.cin_used = "true", add_sub_cella_5.lut_mask = "69b2", add_sub_cella_5.operation_mode = "arithmetic", add_sub_cella_5.sum_lutc_input = "cin", add_sub_cella_5.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_6 ( .cin(wire_add_sub_cella_5cout[0:0]), .combout(wire_add_sub_cella_combout[6:6]), .cout(wire_add_sub_cella_6cout[0:0]), .dataa(wire_add_sub_cella_dataa[6:6]), .datab(wire_add_sub_cella_datab[6:6]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_6.cin_used = "true", add_sub_cella_6.lut_mask = "69b2", add_sub_cella_6.operation_mode = "arithmetic", add_sub_cella_6.sum_lutc_input = "cin", add_sub_cella_6.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_7 ( .cin(wire_add_sub_cella_6cout[0:0]), .combout(wire_add_sub_cella_combout[7:7]), .cout(wire_add_sub_cella_7cout[0:0]), .dataa(wire_add_sub_cella_dataa[7:7]), .datab(wire_add_sub_cella_datab[7:7]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_7.cin_used = "true", add_sub_cella_7.lut_mask = "69b2", add_sub_cella_7.operation_mode = "arithmetic", add_sub_cella_7.sum_lutc_input = "cin", add_sub_cella_7.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_8 ( .cin(wire_add_sub_cella_7cout[0:0]), .combout(wire_add_sub_cella_combout[8:8]), .cout(wire_add_sub_cella_8cout[0:0]), .dataa(wire_add_sub_cella_dataa[8:8]), .datab(wire_add_sub_cella_datab[8:8]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_8.cin_used = "true", add_sub_cella_8.lut_mask = "69b2", add_sub_cella_8.operation_mode = "arithmetic", add_sub_cella_8.sum_lutc_input = "cin", add_sub_cella_8.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_9 ( .cin(wire_add_sub_cella_8cout[0:0]), .combout(wire_add_sub_cella_combout[9:9]), .cout(wire_add_sub_cella_9cout[0:0]), .dataa(wire_add_sub_cella_dataa[9:9]), .datab(wire_add_sub_cella_datab[9:9]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_9.cin_used = "true", add_sub_cella_9.lut_mask = "69b2", add_sub_cella_9.operation_mode = "arithmetic", add_sub_cella_9.sum_lutc_input = "cin", add_sub_cella_9.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_10 ( .cin(wire_add_sub_cella_9cout[0:0]), .combout(wire_add_sub_cella_combout[10:10]), .cout(), .dataa(wire_add_sub_cella_dataa[10:10]), .datab(wire_add_sub_cella_datab[10:10]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_10.cin_used = "true", add_sub_cella_10.lut_mask = "6969", add_sub_cella_10.operation_mode = "normal", add_sub_cella_10.sum_lutc_input = "cin", add_sub_cella_10.lpm_type = "cyclone_lcell"; assign wire_add_sub_cella_dataa = dataa, wire_add_sub_cella_datab = datab; assign result = wire_add_sub_cella_combout; endmodule //fifo_2k_add_sub_a18 //lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END //lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END //synthesis_resources = lut 97 M4K 8 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_dcfifo_0cq ( aclr, data, q, rdclk, rdempty, rdreq, rdusedw, wrclk, wrfull, wrreq, wrusedw) /* synthesis synthesis_clearbox=1 */ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */; input aclr; input [15:0] data; output [15:0] q; input rdclk; output rdempty; input rdreq; output [10:0] rdusedw; input wrclk; output wrfull; input wrreq; output [10:0] wrusedw; wire [10:0] wire_rdptr_g_gray2bin_bin; wire [10:0] wire_rs_dgwp_gray2bin_bin; wire [10:0] wire_wrptr_g_gray2bin_bin; wire [10:0] wire_ws_dgrp_gray2bin_bin; wire [10:0] wire_rdptr_g_q; wire [10:0] wire_rdptr_g1p_q; wire [10:0] wire_wrptr_g1p_q; wire [15:0] wire_fifo_ram_q_b; reg [10:0] delayed_wrptr_g; reg [10:0] wrptr_g; wire [10:0] wire_rs_brp_q; wire [10:0] wire_rs_bwp_q; wire [10:0] wire_rs_dgwp_q; wire [10:0] wire_ws_brp_q; wire [10:0] wire_ws_bwp_q; wire [10:0] wire_ws_dgrp_q; wire [10:0] wire_rdusedw_sub_result; wire [10:0] wire_wrusedw_sub_result; reg wire_rdempty_eq_comp_aeb_int; wire wire_rdempty_eq_comp_aeb; wire [10:0] wire_rdempty_eq_comp_dataa; wire [10:0] wire_rdempty_eq_comp_datab; reg wire_wrfull_eq_comp_aeb_int; wire wire_wrfull_eq_comp_aeb; wire [10:0] wire_wrfull_eq_comp_dataa; wire [10:0] wire_wrfull_eq_comp_datab; wire int_rdempty; wire int_wrfull; wire valid_rdreq; wire valid_wrreq; fifo_2k_a_gray2bin_8m4 rdptr_g_gray2bin ( .bin(wire_rdptr_g_gray2bin_bin), .gray(wire_rdptr_g_q)); fifo_2k_a_gray2bin_8m4 rs_dgwp_gray2bin ( .bin(wire_rs_dgwp_gray2bin_bin), .gray(wire_rs_dgwp_q)); fifo_2k_a_gray2bin_8m4 wrptr_g_gray2bin ( .bin(wire_wrptr_g_gray2bin_bin), .gray(wrptr_g)); fifo_2k_a_gray2bin_8m4 ws_dgrp_gray2bin ( .bin(wire_ws_dgrp_gray2bin_bin), .gray(wire_ws_dgrp_q)); fifo_2k_a_graycounter_726 rdptr_g ( .aclr(aclr), .clock(rdclk), .cnt_en(valid_rdreq), .q(wire_rdptr_g_q)); fifo_2k_a_graycounter_2r6 rdptr_g1p ( .aclr(aclr), .clock(rdclk), .cnt_en(valid_rdreq), .q(wire_rdptr_g1p_q)); fifo_2k_a_graycounter_2r6 wrptr_g1p ( .aclr(aclr), .clock(wrclk), .cnt_en(valid_wrreq), .q(wire_wrptr_g1p_q)); fifo_2k_altsyncram_6pl fifo_ram ( .address_a(wrptr_g), .address_b(((wire_rdptr_g_q & {11{int_rdempty}}) | (wire_rdptr_g1p_q & {11{(~ int_rdempty)}}))), .clock0(wrclk), .clock1(rdclk), .clocken1((valid_rdreq | int_rdempty)), .data_a(data), .q_b(wire_fifo_ram_q_b), .wren_a(valid_wrreq)); // synopsys translate_off initial delayed_wrptr_g = 0; // synopsys translate_on always @ ( posedge wrclk or posedge aclr) if (aclr == 1'b1) delayed_wrptr_g <= 11'b0; else delayed_wrptr_g <= wrptr_g; // synopsys translate_off initial wrptr_g = 0; // synopsys translate_on always @ ( posedge wrclk or posedge aclr) if (aclr == 1'b1) wrptr_g <= 11'b0; else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q; fifo_2k_dffpipe_ab3 rs_brp ( .clock(rdclk), .clrn((~ aclr)), .d(wire_rdptr_g_gray2bin_bin), .q(wire_rs_brp_q)); fifo_2k_dffpipe_ab3 rs_bwp ( .clock(rdclk), .clrn((~ aclr)), .d(wire_rs_dgwp_gray2bin_bin), .q(wire_rs_bwp_q)); fifo_2k_alt_synch_pipe_dm2 rs_dgwp ( .clock(rdclk), .clrn((~ aclr)), .d(delayed_wrptr_g), .q(wire_rs_dgwp_q)); fifo_2k_dffpipe_ab3 ws_brp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_ws_dgrp_gray2bin_bin), .q(wire_ws_brp_q)); fifo_2k_dffpipe_ab3 ws_bwp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_wrptr_g_gray2bin_bin), .q(wire_ws_bwp_q)); fifo_2k_alt_synch_pipe_dm2 ws_dgrp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_rdptr_g_q), .q(wire_ws_dgrp_q)); fifo_2k_add_sub_a18 rdusedw_sub ( .dataa(wire_rs_bwp_q), .datab(wire_rs_brp_q), .result(wire_rdusedw_sub_result)); fifo_2k_add_sub_a18 wrusedw_sub ( .dataa(wire_ws_bwp_q), .datab(wire_ws_brp_q), .result(wire_wrusedw_sub_result)); always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab) if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) begin wire_rdempty_eq_comp_aeb_int = 1'b1; end else begin wire_rdempty_eq_comp_aeb_int = 1'b0; end assign wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int; assign wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q, wire_rdempty_eq_comp_datab = wire_rdptr_g_q; always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab) if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) begin wire_wrfull_eq_comp_aeb_int = 1'b1; end else begin wire_wrfull_eq_comp_aeb_int = 1'b0; end assign wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int; assign wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q, wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q; assign int_rdempty = wire_rdempty_eq_comp_aeb, int_wrfull = wire_wrfull_eq_comp_aeb, q = wire_fifo_ram_q_b, rdempty = int_rdempty, rdusedw = wire_rdusedw_sub_result, valid_rdreq = rdreq, valid_wrreq = wrreq, wrfull = int_wrfull, wrusedw = wire_wrusedw_sub_result; endmodule //fifo_2k_dcfifo_0cq //VALID FILE // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module fifo_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdempty, rdusedw, wrfull, wrusedw)/* synthesis synthesis_clearbox = 1 */; input [15:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [15:0] q; output rdempty; output [10:0] rdusedw; output wrfull; output [10:0] wrusedw; wire sub_wire0; wire [10:0] sub_wire1; wire sub_wire2; wire [15:0] sub_wire3; wire [10:0] sub_wire4; wire rdempty = sub_wire0; wire [10:0] wrusedw = sub_wire1[10:0]; wire wrfull = sub_wire2; wire [15:0] q = sub_wire3[15:0]; wire [10:0] rdusedw = sub_wire4[10:0]; fifo_2k_dcfifo_0cq fifo_2k_dcfifo_0cq_component ( .wrclk (wrclk), .rdreq (rdreq), .aclr (aclr), .rdclk (rdclk), .wrreq (wrreq), .data (data), .rdempty (sub_wire0), .wrusedw (sub_wire1), .wrfull (sub_wire2), .q (sub_wire3), .rdusedw (sub_wire4)); endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: Width NUMERIC "16" // Retrieval info: PRIVATE: Depth NUMERIC "2048" // Retrieval info: PRIVATE: Clock NUMERIC "4" // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" // Retrieval info: PRIVATE: Full NUMERIC "1" // Retrieval info: PRIVATE: Empty NUMERIC "1" // Retrieval info: PRIVATE: UsedW NUMERIC "1" // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" // Retrieval info: PRIVATE: rsFull NUMERIC "0" // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" // Retrieval info: PRIVATE: rsUsedW NUMERIC "1" // Retrieval info: PRIVATE: wsFull NUMERIC "1" // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" // Retrieval info: PRIVATE: wsUsedW NUMERIC "1" // Retrieval info: PRIVATE: dc_aclr NUMERIC "1" // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" // Retrieval info: PRIVATE: Optimize NUMERIC "2" // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" // Retrieval info: CONSTANT: USE_EAB STRING "ON" // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty // Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0] // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull // Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0] // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr // Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 // Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 // Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0 // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 // Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0 // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE

// megafunction wizard: %FIFO%CBX% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: dcfifo // ============================================================ // File Name: fifo_2k.v // Megafunction Name(s): // dcfifo // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition // ************************************************************ //Copyright (C) 1991-2005 Altera Corporation //Your use of Altera Corporation's design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. //dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=11 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END //a_gray2bin device_family="Cyclone" WIDTH=11 bin gray //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END //synthesis_resources = //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_a_gray2bin_8m4 ( bin, gray) /* synthesis synthesis_clearbox=1 */; output [10:0] bin; input [10:0] gray; wire xor0; wire xor1; wire xor2; wire xor3; wire xor4; wire xor5; wire xor6; wire xor7; wire xor8; wire xor9; assign bin = {gray[10], xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0}, xor0 = (gray[0] ^ xor1), xor1 = (gray[1] ^ xor2), xor2 = (gray[2] ^ xor3), xor3 = (gray[3] ^ xor4), xor4 = (gray[4] ^ xor5), xor5 = (gray[5] ^ xor6), xor6 = (gray[6] ^ xor7), xor7 = (gray[7] ^ xor8), xor8 = (gray[8] ^ xor9), xor9 = (gray[10] ^ gray[9]); endmodule //fifo_2k_a_gray2bin_8m4 //a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=11 aclr clock cnt_en q //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END //synthesis_resources = lut 12 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_a_graycounter_726 ( aclr, clock, cnt_en, q) /* synthesis synthesis_clearbox=1 */; input aclr; input clock; input cnt_en; output [10:0] q; wire [0:0] wire_countera_0cout; wire [0:0] wire_countera_1cout; wire [0:0] wire_countera_2cout; wire [0:0] wire_countera_3cout; wire [0:0] wire_countera_4cout; wire [0:0] wire_countera_5cout; wire [0:0] wire_countera_6cout; wire [0:0] wire_countera_7cout; wire [0:0] wire_countera_8cout; wire [0:0] wire_countera_9cout; wire [10:0] wire_countera_regout; wire wire_parity_cout; wire wire_parity_regout; wire [10:0] power_modified_counter_values; wire sclr; wire updown; cyclone_lcell countera_0 ( .aclr(aclr), .cin(wire_parity_cout), .clk(clock), .combout(), .cout(wire_countera_0cout[0:0]), .dataa(cnt_en), .datab(wire_countera_regout[0:0]), .ena(1'b1), .regout(wire_countera_regout[0:0]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_0.cin_used = "true", countera_0.lut_mask = "c6a0", countera_0.operation_mode = "arithmetic", countera_0.sum_lutc_input = "cin", countera_0.synch_mode = "on", countera_0.lpm_type = "cyclone_lcell"; cyclone_lcell countera_1 ( .aclr(aclr), .cin(wire_countera_0cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_1cout[0:0]), .dataa(power_modified_counter_values[0]), .datab(power_modified_counter_values[1]), .ena(1'b1), .regout(wire_countera_regout[1:1]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_1.cin_used = "true", countera_1.lut_mask = "6c50", countera_1.operation_mode = "arithmetic", countera_1.sum_lutc_input = "cin", countera_1.synch_mode = "on", countera_1.lpm_type = "cyclone_lcell"; cyclone_lcell countera_2 ( .aclr(aclr), .cin(wire_countera_1cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_2cout[0:0]), .dataa(power_modified_counter_values[1]), .datab(power_modified_counter_values[2]), .ena(1'b1), .regout(wire_countera_regout[2:2]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_2.cin_used = "true", countera_2.lut_mask = "6c50", countera_2.operation_mode = "arithmetic", countera_2.sum_lutc_input = "cin", countera_2.synch_mode = "on", countera_2.lpm_type = "cyclone_lcell"; cyclone_lcell countera_3 ( .aclr(aclr), .cin(wire_countera_2cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_3cout[0:0]), .dataa(power_modified_counter_values[2]), .datab(power_modified_counter_values[3]), .ena(1'b1), .regout(wire_countera_regout[3:3]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_3.cin_used = "true", countera_3.lut_mask = "6c50", countera_3.operation_mode = "arithmetic", countera_3.sum_lutc_input = "cin", countera_3.synch_mode = "on", countera_3.lpm_type = "cyclone_lcell"; cyclone_lcell countera_4 ( .aclr(aclr), .cin(wire_countera_3cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_4cout[0:0]), .dataa(power_modified_counter_values[3]), .datab(power_modified_counter_values[4]), .ena(1'b1), .regout(wire_countera_regout[4:4]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_4.cin_used = "true", countera_4.lut_mask = "6c50", countera_4.operation_mode = "arithmetic", countera_4.sum_lutc_input = "cin", countera_4.synch_mode = "on", countera_4.lpm_type = "cyclone_lcell"; cyclone_lcell countera_5 ( .aclr(aclr), .cin(wire_countera_4cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_5cout[0:0]), .dataa(power_modified_counter_values[4]), .datab(power_modified_counter_values[5]), .ena(1'b1), .regout(wire_countera_regout[5:5]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_5.cin_used = "true", countera_5.lut_mask = "6c50", countera_5.operation_mode = "arithmetic", countera_5.sum_lutc_input = "cin", countera_5.synch_mode = "on", countera_5.lpm_type = "cyclone_lcell"; cyclone_lcell countera_6 ( .aclr(aclr), .cin(wire_countera_5cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_6cout[0:0]), .dataa(power_modified_counter_values[5]), .datab(power_modified_counter_values[6]), .ena(1'b1), .regout(wire_countera_regout[6:6]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_6.cin_used = "true", countera_6.lut_mask = "6c50", countera_6.operation_mode = "arithmetic", countera_6.sum_lutc_input = "cin", countera_6.synch_mode = "on", countera_6.lpm_type = "cyclone_lcell"; cyclone_lcell countera_7 ( .aclr(aclr), .cin(wire_countera_6cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_7cout[0:0]), .dataa(power_modified_counter_values[6]), .datab(power_modified_counter_values[7]), .ena(1'b1), .regout(wire_countera_regout[7:7]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_7.cin_used = "true", countera_7.lut_mask = "6c50", countera_7.operation_mode = "arithmetic", countera_7.sum_lutc_input = "cin", countera_7.synch_mode = "on", countera_7.lpm_type = "cyclone_lcell"; cyclone_lcell countera_8 ( .aclr(aclr), .cin(wire_countera_7cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_8cout[0:0]), .dataa(power_modified_counter_values[7]), .datab(power_modified_counter_values[8]), .ena(1'b1), .regout(wire_countera_regout[8:8]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_8.cin_used = "true", countera_8.lut_mask = "6c50", countera_8.operation_mode = "arithmetic", countera_8.sum_lutc_input = "cin", countera_8.synch_mode = "on", countera_8.lpm_type = "cyclone_lcell"; cyclone_lcell countera_9 ( .aclr(aclr), .cin(wire_countera_8cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_9cout[0:0]), .dataa(power_modified_counter_values[8]), .datab(power_modified_counter_values[9]), .ena(1'b1), .regout(wire_countera_regout[9:9]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_9.cin_used = "true", countera_9.lut_mask = "6c50", countera_9.operation_mode = "arithmetic", countera_9.sum_lutc_input = "cin", countera_9.synch_mode = "on", countera_9.lpm_type = "cyclone_lcell"; cyclone_lcell countera_10 ( .aclr(aclr), .cin(wire_countera_9cout[0:0]), .clk(clock), .combout(), .cout(), .dataa(power_modified_counter_values[10]), .ena(1'b1), .regout(wire_countera_regout[10:10]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datab(1'b1), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_10.cin_used = "true", countera_10.lut_mask = "5a5a", countera_10.operation_mode = "normal", countera_10.sum_lutc_input = "cin", countera_10.synch_mode = "on", countera_10.lpm_type = "cyclone_lcell"; cyclone_lcell parity ( .aclr(aclr), .cin(updown), .clk(clock), .combout(), .cout(wire_parity_cout), .dataa(cnt_en), .datab(wire_parity_regout), .ena(1'b1), .regout(wire_parity_regout), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam parity.cin_used = "true", parity.lut_mask = "6682", parity.operation_mode = "arithmetic", parity.synch_mode = "on", parity.lpm_type = "cyclone_lcell"; assign power_modified_counter_values = {wire_countera_regout[10:0]}, q = power_modified_counter_values, sclr = 1'b0, updown = 1'b1; endmodule //fifo_2k_a_graycounter_726 //a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=11 aclr clock cnt_en q //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END //synthesis_resources = lut 12 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_a_graycounter_2r6 ( aclr, clock, cnt_en, q) /* synthesis synthesis_clearbox=1 */; input aclr; input clock; input cnt_en; output [10:0] q; wire [0:0] wire_countera_0cout; wire [0:0] wire_countera_1cout; wire [0:0] wire_countera_2cout; wire [0:0] wire_countera_3cout; wire [0:0] wire_countera_4cout; wire [0:0] wire_countera_5cout; wire [0:0] wire_countera_6cout; wire [0:0] wire_countera_7cout; wire [0:0] wire_countera_8cout; wire [0:0] wire_countera_9cout; wire [10:0] wire_countera_regout; wire wire_parity_cout; wire wire_parity_regout; wire [10:0] power_modified_counter_values; wire sclr; wire updown; cyclone_lcell countera_0 ( .aclr(aclr), .cin(wire_parity_cout), .clk(clock), .combout(), .cout(wire_countera_0cout[0:0]), .dataa(cnt_en), .datab(wire_countera_regout[0:0]), .ena(1'b1), .regout(wire_countera_regout[0:0]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_0.cin_used = "true", countera_0.lut_mask = "c6a0", countera_0.operation_mode = "arithmetic", countera_0.sum_lutc_input = "cin", countera_0.synch_mode = "on", countera_0.lpm_type = "cyclone_lcell"; cyclone_lcell countera_1 ( .aclr(aclr), .cin(wire_countera_0cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_1cout[0:0]), .dataa(power_modified_counter_values[0]), .datab(power_modified_counter_values[1]), .ena(1'b1), .regout(wire_countera_regout[1:1]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_1.cin_used = "true", countera_1.lut_mask = "6c50", countera_1.operation_mode = "arithmetic", countera_1.sum_lutc_input = "cin", countera_1.synch_mode = "on", countera_1.lpm_type = "cyclone_lcell"; cyclone_lcell countera_2 ( .aclr(aclr), .cin(wire_countera_1cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_2cout[0:0]), .dataa(power_modified_counter_values[1]), .datab(power_modified_counter_values[2]), .ena(1'b1), .regout(wire_countera_regout[2:2]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_2.cin_used = "true", countera_2.lut_mask = "6c50", countera_2.operation_mode = "arithmetic", countera_2.sum_lutc_input = "cin", countera_2.synch_mode = "on", countera_2.lpm_type = "cyclone_lcell"; cyclone_lcell countera_3 ( .aclr(aclr), .cin(wire_countera_2cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_3cout[0:0]), .dataa(power_modified_counter_values[2]), .datab(power_modified_counter_values[3]), .ena(1'b1), .regout(wire_countera_regout[3:3]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_3.cin_used = "true", countera_3.lut_mask = "6c50", countera_3.operation_mode = "arithmetic", countera_3.sum_lutc_input = "cin", countera_3.synch_mode = "on", countera_3.lpm_type = "cyclone_lcell"; cyclone_lcell countera_4 ( .aclr(aclr), .cin(wire_countera_3cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_4cout[0:0]), .dataa(power_modified_counter_values[3]), .datab(power_modified_counter_values[4]), .ena(1'b1), .regout(wire_countera_regout[4:4]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_4.cin_used = "true", countera_4.lut_mask = "6c50", countera_4.operation_mode = "arithmetic", countera_4.sum_lutc_input = "cin", countera_4.synch_mode = "on", countera_4.lpm_type = "cyclone_lcell"; cyclone_lcell countera_5 ( .aclr(aclr), .cin(wire_countera_4cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_5cout[0:0]), .dataa(power_modified_counter_values[4]), .datab(power_modified_counter_values[5]), .ena(1'b1), .regout(wire_countera_regout[5:5]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_5.cin_used = "true", countera_5.lut_mask = "6c50", countera_5.operation_mode = "arithmetic", countera_5.sum_lutc_input = "cin", countera_5.synch_mode = "on", countera_5.lpm_type = "cyclone_lcell"; cyclone_lcell countera_6 ( .aclr(aclr), .cin(wire_countera_5cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_6cout[0:0]), .dataa(power_modified_counter_values[5]), .datab(power_modified_counter_values[6]), .ena(1'b1), .regout(wire_countera_regout[6:6]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_6.cin_used = "true", countera_6.lut_mask = "6c50", countera_6.operation_mode = "arithmetic", countera_6.sum_lutc_input = "cin", countera_6.synch_mode = "on", countera_6.lpm_type = "cyclone_lcell"; cyclone_lcell countera_7 ( .aclr(aclr), .cin(wire_countera_6cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_7cout[0:0]), .dataa(power_modified_counter_values[6]), .datab(power_modified_counter_values[7]), .ena(1'b1), .regout(wire_countera_regout[7:7]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_7.cin_used = "true", countera_7.lut_mask = "6c50", countera_7.operation_mode = "arithmetic", countera_7.sum_lutc_input = "cin", countera_7.synch_mode = "on", countera_7.lpm_type = "cyclone_lcell"; cyclone_lcell countera_8 ( .aclr(aclr), .cin(wire_countera_7cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_8cout[0:0]), .dataa(power_modified_counter_values[7]), .datab(power_modified_counter_values[8]), .ena(1'b1), .regout(wire_countera_regout[8:8]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_8.cin_used = "true", countera_8.lut_mask = "6c50", countera_8.operation_mode = "arithmetic", countera_8.sum_lutc_input = "cin", countera_8.synch_mode = "on", countera_8.lpm_type = "cyclone_lcell"; cyclone_lcell countera_9 ( .aclr(aclr), .cin(wire_countera_8cout[0:0]), .clk(clock), .combout(), .cout(wire_countera_9cout[0:0]), .dataa(power_modified_counter_values[8]), .datab(power_modified_counter_values[9]), .ena(1'b1), .regout(wire_countera_regout[9:9]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_9.cin_used = "true", countera_9.lut_mask = "6c50", countera_9.operation_mode = "arithmetic", countera_9.sum_lutc_input = "cin", countera_9.synch_mode = "on", countera_9.lpm_type = "cyclone_lcell"; cyclone_lcell countera_10 ( .aclr(aclr), .cin(wire_countera_9cout[0:0]), .clk(clock), .combout(), .cout(), .dataa(power_modified_counter_values[10]), .ena(1'b1), .regout(wire_countera_regout[10:10]), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datab(1'b1), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam countera_10.cin_used = "true", countera_10.lut_mask = "5a5a", countera_10.operation_mode = "normal", countera_10.sum_lutc_input = "cin", countera_10.synch_mode = "on", countera_10.lpm_type = "cyclone_lcell"; cyclone_lcell parity ( .aclr(aclr), .cin(updown), .clk(clock), .combout(), .cout(wire_parity_cout), .dataa(cnt_en), .datab((~ wire_parity_regout)), .ena(1'b1), .regout(wire_parity_regout), .sclr(sclr) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aload(1'b0), .datac(1'b1), .datad(1'b1), .inverta(1'b0), .regcascin(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam parity.cin_used = "true", parity.lut_mask = "9982", parity.operation_mode = "arithmetic", parity.synch_mode = "on", parity.lpm_type = "cyclone_lcell"; assign power_modified_counter_values = {wire_countera_regout[10:1], (~ wire_countera_regout[0])}, q = power_modified_counter_values, sclr = 1'b0, updown = 1'b1; endmodule //fifo_2k_a_graycounter_2r6 //altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a //VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END //synthesis_resources = M4K 8 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_altsyncram_6pl ( address_a, address_b, clock0, clock1, clocken1, data_a, q_b, wren_a) /* synthesis synthesis_clearbox=1 */; input [10:0] address_a; input [10:0] address_b; input clock0; input clock1; input clocken1; input [15:0] data_a; output [15:0] q_b; input wren_a; wire [0:0] wire_ram_block3a_0portbdataout; wire [0:0] wire_ram_block3a_1portbdataout; wire [0:0] wire_ram_block3a_2portbdataout; wire [0:0] wire_ram_block3a_3portbdataout; wire [0:0] wire_ram_block3a_4portbdataout; wire [0:0] wire_ram_block3a_5portbdataout; wire [0:0] wire_ram_block3a_6portbdataout; wire [0:0] wire_ram_block3a_7portbdataout; wire [0:0] wire_ram_block3a_8portbdataout; wire [0:0] wire_ram_block3a_9portbdataout; wire [0:0] wire_ram_block3a_10portbdataout; wire [0:0] wire_ram_block3a_11portbdataout; wire [0:0] wire_ram_block3a_12portbdataout; wire [0:0] wire_ram_block3a_13portbdataout; wire [0:0] wire_ram_block3a_14portbdataout; wire [0:0] wire_ram_block3a_15portbdataout; wire [10:0] address_a_wire; wire [10:0] address_b_wire; cyclone_ram_block ram_block3a_0 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[0]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_0portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_0.connectivity_checking = "OFF", ram_block3a_0.logical_ram_name = "ALTSYNCRAM", ram_block3a_0.mixed_port_feed_through_mode = "dont_care", ram_block3a_0.operation_mode = "dual_port", ram_block3a_0.port_a_address_width = 11, ram_block3a_0.port_a_data_width = 1, ram_block3a_0.port_a_first_address = 0, ram_block3a_0.port_a_first_bit_number = 0, ram_block3a_0.port_a_last_address = 2047, ram_block3a_0.port_a_logical_ram_depth = 2048, ram_block3a_0.port_a_logical_ram_width = 16, ram_block3a_0.port_b_address_clear = "none", ram_block3a_0.port_b_address_clock = "clock1", ram_block3a_0.port_b_address_width = 11, ram_block3a_0.port_b_data_out_clear = "none", ram_block3a_0.port_b_data_out_clock = "none", ram_block3a_0.port_b_data_width = 1, ram_block3a_0.port_b_first_address = 0, ram_block3a_0.port_b_first_bit_number = 0, ram_block3a_0.port_b_last_address = 2047, ram_block3a_0.port_b_logical_ram_depth = 2048, ram_block3a_0.port_b_logical_ram_width = 16, ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_0.ram_block_type = "auto", ram_block3a_0.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_1 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[1]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_1portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_1.connectivity_checking = "OFF", ram_block3a_1.logical_ram_name = "ALTSYNCRAM", ram_block3a_1.mixed_port_feed_through_mode = "dont_care", ram_block3a_1.operation_mode = "dual_port", ram_block3a_1.port_a_address_width = 11, ram_block3a_1.port_a_data_width = 1, ram_block3a_1.port_a_first_address = 0, ram_block3a_1.port_a_first_bit_number = 1, ram_block3a_1.port_a_last_address = 2047, ram_block3a_1.port_a_logical_ram_depth = 2048, ram_block3a_1.port_a_logical_ram_width = 16, ram_block3a_1.port_b_address_clear = "none", ram_block3a_1.port_b_address_clock = "clock1", ram_block3a_1.port_b_address_width = 11, ram_block3a_1.port_b_data_out_clear = "none", ram_block3a_1.port_b_data_out_clock = "none", ram_block3a_1.port_b_data_width = 1, ram_block3a_1.port_b_first_address = 0, ram_block3a_1.port_b_first_bit_number = 1, ram_block3a_1.port_b_last_address = 2047, ram_block3a_1.port_b_logical_ram_depth = 2048, ram_block3a_1.port_b_logical_ram_width = 16, ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_1.ram_block_type = "auto", ram_block3a_1.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_2 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[2]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_2portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_2.connectivity_checking = "OFF", ram_block3a_2.logical_ram_name = "ALTSYNCRAM", ram_block3a_2.mixed_port_feed_through_mode = "dont_care", ram_block3a_2.operation_mode = "dual_port", ram_block3a_2.port_a_address_width = 11, ram_block3a_2.port_a_data_width = 1, ram_block3a_2.port_a_first_address = 0, ram_block3a_2.port_a_first_bit_number = 2, ram_block3a_2.port_a_last_address = 2047, ram_block3a_2.port_a_logical_ram_depth = 2048, ram_block3a_2.port_a_logical_ram_width = 16, ram_block3a_2.port_b_address_clear = "none", ram_block3a_2.port_b_address_clock = "clock1", ram_block3a_2.port_b_address_width = 11, ram_block3a_2.port_b_data_out_clear = "none", ram_block3a_2.port_b_data_out_clock = "none", ram_block3a_2.port_b_data_width = 1, ram_block3a_2.port_b_first_address = 0, ram_block3a_2.port_b_first_bit_number = 2, ram_block3a_2.port_b_last_address = 2047, ram_block3a_2.port_b_logical_ram_depth = 2048, ram_block3a_2.port_b_logical_ram_width = 16, ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_2.ram_block_type = "auto", ram_block3a_2.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_3 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[3]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_3portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_3.connectivity_checking = "OFF", ram_block3a_3.logical_ram_name = "ALTSYNCRAM", ram_block3a_3.mixed_port_feed_through_mode = "dont_care", ram_block3a_3.operation_mode = "dual_port", ram_block3a_3.port_a_address_width = 11, ram_block3a_3.port_a_data_width = 1, ram_block3a_3.port_a_first_address = 0, ram_block3a_3.port_a_first_bit_number = 3, ram_block3a_3.port_a_last_address = 2047, ram_block3a_3.port_a_logical_ram_depth = 2048, ram_block3a_3.port_a_logical_ram_width = 16, ram_block3a_3.port_b_address_clear = "none", ram_block3a_3.port_b_address_clock = "clock1", ram_block3a_3.port_b_address_width = 11, ram_block3a_3.port_b_data_out_clear = "none", ram_block3a_3.port_b_data_out_clock = "none", ram_block3a_3.port_b_data_width = 1, ram_block3a_3.port_b_first_address = 0, ram_block3a_3.port_b_first_bit_number = 3, ram_block3a_3.port_b_last_address = 2047, ram_block3a_3.port_b_logical_ram_depth = 2048, ram_block3a_3.port_b_logical_ram_width = 16, ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_3.ram_block_type = "auto", ram_block3a_3.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_4 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[4]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_4portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_4.connectivity_checking = "OFF", ram_block3a_4.logical_ram_name = "ALTSYNCRAM", ram_block3a_4.mixed_port_feed_through_mode = "dont_care", ram_block3a_4.operation_mode = "dual_port", ram_block3a_4.port_a_address_width = 11, ram_block3a_4.port_a_data_width = 1, ram_block3a_4.port_a_first_address = 0, ram_block3a_4.port_a_first_bit_number = 4, ram_block3a_4.port_a_last_address = 2047, ram_block3a_4.port_a_logical_ram_depth = 2048, ram_block3a_4.port_a_logical_ram_width = 16, ram_block3a_4.port_b_address_clear = "none", ram_block3a_4.port_b_address_clock = "clock1", ram_block3a_4.port_b_address_width = 11, ram_block3a_4.port_b_data_out_clear = "none", ram_block3a_4.port_b_data_out_clock = "none", ram_block3a_4.port_b_data_width = 1, ram_block3a_4.port_b_first_address = 0, ram_block3a_4.port_b_first_bit_number = 4, ram_block3a_4.port_b_last_address = 2047, ram_block3a_4.port_b_logical_ram_depth = 2048, ram_block3a_4.port_b_logical_ram_width = 16, ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_4.ram_block_type = "auto", ram_block3a_4.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_5 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[5]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_5portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_5.connectivity_checking = "OFF", ram_block3a_5.logical_ram_name = "ALTSYNCRAM", ram_block3a_5.mixed_port_feed_through_mode = "dont_care", ram_block3a_5.operation_mode = "dual_port", ram_block3a_5.port_a_address_width = 11, ram_block3a_5.port_a_data_width = 1, ram_block3a_5.port_a_first_address = 0, ram_block3a_5.port_a_first_bit_number = 5, ram_block3a_5.port_a_last_address = 2047, ram_block3a_5.port_a_logical_ram_depth = 2048, ram_block3a_5.port_a_logical_ram_width = 16, ram_block3a_5.port_b_address_clear = "none", ram_block3a_5.port_b_address_clock = "clock1", ram_block3a_5.port_b_address_width = 11, ram_block3a_5.port_b_data_out_clear = "none", ram_block3a_5.port_b_data_out_clock = "none", ram_block3a_5.port_b_data_width = 1, ram_block3a_5.port_b_first_address = 0, ram_block3a_5.port_b_first_bit_number = 5, ram_block3a_5.port_b_last_address = 2047, ram_block3a_5.port_b_logical_ram_depth = 2048, ram_block3a_5.port_b_logical_ram_width = 16, ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_5.ram_block_type = "auto", ram_block3a_5.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_6 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[6]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_6portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_6.connectivity_checking = "OFF", ram_block3a_6.logical_ram_name = "ALTSYNCRAM", ram_block3a_6.mixed_port_feed_through_mode = "dont_care", ram_block3a_6.operation_mode = "dual_port", ram_block3a_6.port_a_address_width = 11, ram_block3a_6.port_a_data_width = 1, ram_block3a_6.port_a_first_address = 0, ram_block3a_6.port_a_first_bit_number = 6, ram_block3a_6.port_a_last_address = 2047, ram_block3a_6.port_a_logical_ram_depth = 2048, ram_block3a_6.port_a_logical_ram_width = 16, ram_block3a_6.port_b_address_clear = "none", ram_block3a_6.port_b_address_clock = "clock1", ram_block3a_6.port_b_address_width = 11, ram_block3a_6.port_b_data_out_clear = "none", ram_block3a_6.port_b_data_out_clock = "none", ram_block3a_6.port_b_data_width = 1, ram_block3a_6.port_b_first_address = 0, ram_block3a_6.port_b_first_bit_number = 6, ram_block3a_6.port_b_last_address = 2047, ram_block3a_6.port_b_logical_ram_depth = 2048, ram_block3a_6.port_b_logical_ram_width = 16, ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_6.ram_block_type = "auto", ram_block3a_6.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_7 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[7]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_7portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_7.connectivity_checking = "OFF", ram_block3a_7.logical_ram_name = "ALTSYNCRAM", ram_block3a_7.mixed_port_feed_through_mode = "dont_care", ram_block3a_7.operation_mode = "dual_port", ram_block3a_7.port_a_address_width = 11, ram_block3a_7.port_a_data_width = 1, ram_block3a_7.port_a_first_address = 0, ram_block3a_7.port_a_first_bit_number = 7, ram_block3a_7.port_a_last_address = 2047, ram_block3a_7.port_a_logical_ram_depth = 2048, ram_block3a_7.port_a_logical_ram_width = 16, ram_block3a_7.port_b_address_clear = "none", ram_block3a_7.port_b_address_clock = "clock1", ram_block3a_7.port_b_address_width = 11, ram_block3a_7.port_b_data_out_clear = "none", ram_block3a_7.port_b_data_out_clock = "none", ram_block3a_7.port_b_data_width = 1, ram_block3a_7.port_b_first_address = 0, ram_block3a_7.port_b_first_bit_number = 7, ram_block3a_7.port_b_last_address = 2047, ram_block3a_7.port_b_logical_ram_depth = 2048, ram_block3a_7.port_b_logical_ram_width = 16, ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_7.ram_block_type = "auto", ram_block3a_7.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_8 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[8]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_8portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_8.connectivity_checking = "OFF", ram_block3a_8.logical_ram_name = "ALTSYNCRAM", ram_block3a_8.mixed_port_feed_through_mode = "dont_care", ram_block3a_8.operation_mode = "dual_port", ram_block3a_8.port_a_address_width = 11, ram_block3a_8.port_a_data_width = 1, ram_block3a_8.port_a_first_address = 0, ram_block3a_8.port_a_first_bit_number = 8, ram_block3a_8.port_a_last_address = 2047, ram_block3a_8.port_a_logical_ram_depth = 2048, ram_block3a_8.port_a_logical_ram_width = 16, ram_block3a_8.port_b_address_clear = "none", ram_block3a_8.port_b_address_clock = "clock1", ram_block3a_8.port_b_address_width = 11, ram_block3a_8.port_b_data_out_clear = "none", ram_block3a_8.port_b_data_out_clock = "none", ram_block3a_8.port_b_data_width = 1, ram_block3a_8.port_b_first_address = 0, ram_block3a_8.port_b_first_bit_number = 8, ram_block3a_8.port_b_last_address = 2047, ram_block3a_8.port_b_logical_ram_depth = 2048, ram_block3a_8.port_b_logical_ram_width = 16, ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_8.ram_block_type = "auto", ram_block3a_8.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_9 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[9]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_9portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_9.connectivity_checking = "OFF", ram_block3a_9.logical_ram_name = "ALTSYNCRAM", ram_block3a_9.mixed_port_feed_through_mode = "dont_care", ram_block3a_9.operation_mode = "dual_port", ram_block3a_9.port_a_address_width = 11, ram_block3a_9.port_a_data_width = 1, ram_block3a_9.port_a_first_address = 0, ram_block3a_9.port_a_first_bit_number = 9, ram_block3a_9.port_a_last_address = 2047, ram_block3a_9.port_a_logical_ram_depth = 2048, ram_block3a_9.port_a_logical_ram_width = 16, ram_block3a_9.port_b_address_clear = "none", ram_block3a_9.port_b_address_clock = "clock1", ram_block3a_9.port_b_address_width = 11, ram_block3a_9.port_b_data_out_clear = "none", ram_block3a_9.port_b_data_out_clock = "none", ram_block3a_9.port_b_data_width = 1, ram_block3a_9.port_b_first_address = 0, ram_block3a_9.port_b_first_bit_number = 9, ram_block3a_9.port_b_last_address = 2047, ram_block3a_9.port_b_logical_ram_depth = 2048, ram_block3a_9.port_b_logical_ram_width = 16, ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_9.ram_block_type = "auto", ram_block3a_9.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_10 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[10]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_10portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_10.connectivity_checking = "OFF", ram_block3a_10.logical_ram_name = "ALTSYNCRAM", ram_block3a_10.mixed_port_feed_through_mode = "dont_care", ram_block3a_10.operation_mode = "dual_port", ram_block3a_10.port_a_address_width = 11, ram_block3a_10.port_a_data_width = 1, ram_block3a_10.port_a_first_address = 0, ram_block3a_10.port_a_first_bit_number = 10, ram_block3a_10.port_a_last_address = 2047, ram_block3a_10.port_a_logical_ram_depth = 2048, ram_block3a_10.port_a_logical_ram_width = 16, ram_block3a_10.port_b_address_clear = "none", ram_block3a_10.port_b_address_clock = "clock1", ram_block3a_10.port_b_address_width = 11, ram_block3a_10.port_b_data_out_clear = "none", ram_block3a_10.port_b_data_out_clock = "none", ram_block3a_10.port_b_data_width = 1, ram_block3a_10.port_b_first_address = 0, ram_block3a_10.port_b_first_bit_number = 10, ram_block3a_10.port_b_last_address = 2047, ram_block3a_10.port_b_logical_ram_depth = 2048, ram_block3a_10.port_b_logical_ram_width = 16, ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_10.ram_block_type = "auto", ram_block3a_10.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_11 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[11]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_11portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_11.connectivity_checking = "OFF", ram_block3a_11.logical_ram_name = "ALTSYNCRAM", ram_block3a_11.mixed_port_feed_through_mode = "dont_care", ram_block3a_11.operation_mode = "dual_port", ram_block3a_11.port_a_address_width = 11, ram_block3a_11.port_a_data_width = 1, ram_block3a_11.port_a_first_address = 0, ram_block3a_11.port_a_first_bit_number = 11, ram_block3a_11.port_a_last_address = 2047, ram_block3a_11.port_a_logical_ram_depth = 2048, ram_block3a_11.port_a_logical_ram_width = 16, ram_block3a_11.port_b_address_clear = "none", ram_block3a_11.port_b_address_clock = "clock1", ram_block3a_11.port_b_address_width = 11, ram_block3a_11.port_b_data_out_clear = "none", ram_block3a_11.port_b_data_out_clock = "none", ram_block3a_11.port_b_data_width = 1, ram_block3a_11.port_b_first_address = 0, ram_block3a_11.port_b_first_bit_number = 11, ram_block3a_11.port_b_last_address = 2047, ram_block3a_11.port_b_logical_ram_depth = 2048, ram_block3a_11.port_b_logical_ram_width = 16, ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_11.ram_block_type = "auto", ram_block3a_11.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_12 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[12]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_12portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_12.connectivity_checking = "OFF", ram_block3a_12.logical_ram_name = "ALTSYNCRAM", ram_block3a_12.mixed_port_feed_through_mode = "dont_care", ram_block3a_12.operation_mode = "dual_port", ram_block3a_12.port_a_address_width = 11, ram_block3a_12.port_a_data_width = 1, ram_block3a_12.port_a_first_address = 0, ram_block3a_12.port_a_first_bit_number = 12, ram_block3a_12.port_a_last_address = 2047, ram_block3a_12.port_a_logical_ram_depth = 2048, ram_block3a_12.port_a_logical_ram_width = 16, ram_block3a_12.port_b_address_clear = "none", ram_block3a_12.port_b_address_clock = "clock1", ram_block3a_12.port_b_address_width = 11, ram_block3a_12.port_b_data_out_clear = "none", ram_block3a_12.port_b_data_out_clock = "none", ram_block3a_12.port_b_data_width = 1, ram_block3a_12.port_b_first_address = 0, ram_block3a_12.port_b_first_bit_number = 12, ram_block3a_12.port_b_last_address = 2047, ram_block3a_12.port_b_logical_ram_depth = 2048, ram_block3a_12.port_b_logical_ram_width = 16, ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_12.ram_block_type = "auto", ram_block3a_12.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_13 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[13]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_13portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_13.connectivity_checking = "OFF", ram_block3a_13.logical_ram_name = "ALTSYNCRAM", ram_block3a_13.mixed_port_feed_through_mode = "dont_care", ram_block3a_13.operation_mode = "dual_port", ram_block3a_13.port_a_address_width = 11, ram_block3a_13.port_a_data_width = 1, ram_block3a_13.port_a_first_address = 0, ram_block3a_13.port_a_first_bit_number = 13, ram_block3a_13.port_a_last_address = 2047, ram_block3a_13.port_a_logical_ram_depth = 2048, ram_block3a_13.port_a_logical_ram_width = 16, ram_block3a_13.port_b_address_clear = "none", ram_block3a_13.port_b_address_clock = "clock1", ram_block3a_13.port_b_address_width = 11, ram_block3a_13.port_b_data_out_clear = "none", ram_block3a_13.port_b_data_out_clock = "none", ram_block3a_13.port_b_data_width = 1, ram_block3a_13.port_b_first_address = 0, ram_block3a_13.port_b_first_bit_number = 13, ram_block3a_13.port_b_last_address = 2047, ram_block3a_13.port_b_logical_ram_depth = 2048, ram_block3a_13.port_b_logical_ram_width = 16, ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_13.ram_block_type = "auto", ram_block3a_13.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_14 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[14]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_14portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_14.connectivity_checking = "OFF", ram_block3a_14.logical_ram_name = "ALTSYNCRAM", ram_block3a_14.mixed_port_feed_through_mode = "dont_care", ram_block3a_14.operation_mode = "dual_port", ram_block3a_14.port_a_address_width = 11, ram_block3a_14.port_a_data_width = 1, ram_block3a_14.port_a_first_address = 0, ram_block3a_14.port_a_first_bit_number = 14, ram_block3a_14.port_a_last_address = 2047, ram_block3a_14.port_a_logical_ram_depth = 2048, ram_block3a_14.port_a_logical_ram_width = 16, ram_block3a_14.port_b_address_clear = "none", ram_block3a_14.port_b_address_clock = "clock1", ram_block3a_14.port_b_address_width = 11, ram_block3a_14.port_b_data_out_clear = "none", ram_block3a_14.port_b_data_out_clock = "none", ram_block3a_14.port_b_data_width = 1, ram_block3a_14.port_b_first_address = 0, ram_block3a_14.port_b_first_bit_number = 14, ram_block3a_14.port_b_last_address = 2047, ram_block3a_14.port_b_logical_ram_depth = 2048, ram_block3a_14.port_b_logical_ram_width = 16, ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_14.ram_block_type = "auto", ram_block3a_14.lpm_type = "cyclone_ram_block"; cyclone_ram_block ram_block3a_15 ( .clk0(clock0), .clk1(clock1), .ena0(wren_a), .ena1(clocken1), .portaaddr({address_a_wire[10:0]}), .portadatain({data_a[15]}), .portadataout(), .portawe(1'b1), .portbaddr({address_b_wire[10:0]}), .portbdataout(wire_ram_block3a_15portbdataout[0:0]), .portbrewe(1'b1) `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .clr0(1'b0), .clr1(1'b0), .portabyteenamasks(1'b1), .portbbyteenamasks(1'b1), .portbdatain(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .devclrn(), .devpor() // synopsys translate_on ); defparam ram_block3a_15.connectivity_checking = "OFF", ram_block3a_15.logical_ram_name = "ALTSYNCRAM", ram_block3a_15.mixed_port_feed_through_mode = "dont_care", ram_block3a_15.operation_mode = "dual_port", ram_block3a_15.port_a_address_width = 11, ram_block3a_15.port_a_data_width = 1, ram_block3a_15.port_a_first_address = 0, ram_block3a_15.port_a_first_bit_number = 15, ram_block3a_15.port_a_last_address = 2047, ram_block3a_15.port_a_logical_ram_depth = 2048, ram_block3a_15.port_a_logical_ram_width = 16, ram_block3a_15.port_b_address_clear = "none", ram_block3a_15.port_b_address_clock = "clock1", ram_block3a_15.port_b_address_width = 11, ram_block3a_15.port_b_data_out_clear = "none", ram_block3a_15.port_b_data_out_clock = "none", ram_block3a_15.port_b_data_width = 1, ram_block3a_15.port_b_first_address = 0, ram_block3a_15.port_b_first_bit_number = 15, ram_block3a_15.port_b_last_address = 2047, ram_block3a_15.port_b_logical_ram_depth = 2048, ram_block3a_15.port_b_logical_ram_width = 16, ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1", ram_block3a_15.ram_block_type = "auto", ram_block3a_15.lpm_type = "cyclone_ram_block"; assign address_a_wire = address_a, address_b_wire = address_b, q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]}; endmodule //fifo_2k_altsyncram_6pl //dffpipe DELAY=1 WIDTH=11 clock clrn d q //VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END //synthesis_resources = lut 11 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_dffpipe_ab3 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 */ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; input clock; input clrn; input [10:0] d; output [10:0] q; wire [10:0] wire_dffe4a_D; reg [10:0] dffe4a; wire ena; wire prn; wire sclr; // synopsys translate_off initial dffe4a[0:0] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[0:0] <= 1'b1; else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0; else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0]; // synopsys translate_off initial dffe4a[1:1] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[1:1] <= 1'b1; else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0; else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1]; // synopsys translate_off initial dffe4a[2:2] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[2:2] <= 1'b1; else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0; else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2]; // synopsys translate_off initial dffe4a[3:3] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[3:3] <= 1'b1; else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0; else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3]; // synopsys translate_off initial dffe4a[4:4] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[4:4] <= 1'b1; else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0; else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4]; // synopsys translate_off initial dffe4a[5:5] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[5:5] <= 1'b1; else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0; else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5]; // synopsys translate_off initial dffe4a[6:6] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[6:6] <= 1'b1; else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0; else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6]; // synopsys translate_off initial dffe4a[7:7] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[7:7] <= 1'b1; else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0; else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7]; // synopsys translate_off initial dffe4a[8:8] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[8:8] <= 1'b1; else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0; else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8]; // synopsys translate_off initial dffe4a[9:9] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[9:9] <= 1'b1; else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0; else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9]; // synopsys translate_off initial dffe4a[10:10] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe4a[10:10] <= 1'b1; else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0; else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10]; assign wire_dffe4a_D = (d & {11{(~ sclr)}}); assign ena = 1'b1, prn = 1'b1, q = dffe4a, sclr = 1'b0; endmodule //fifo_2k_dffpipe_ab3 //dffpipe WIDTH=11 clock clrn d q //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END //dffpipe WIDTH=11 clock clrn d q //VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END //synthesis_resources = lut 11 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_dffpipe_dm2 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 */ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */; input clock; input clrn; input [10:0] d; output [10:0] q; wire [10:0] wire_dffe6a_D; reg [10:0] dffe6a; wire ena; wire prn; wire sclr; // synopsys translate_off initial dffe6a[0:0] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[0:0] <= 1'b1; else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0; else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0]; // synopsys translate_off initial dffe6a[1:1] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[1:1] <= 1'b1; else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0; else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1]; // synopsys translate_off initial dffe6a[2:2] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[2:2] <= 1'b1; else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0; else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2]; // synopsys translate_off initial dffe6a[3:3] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[3:3] <= 1'b1; else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0; else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3]; // synopsys translate_off initial dffe6a[4:4] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[4:4] <= 1'b1; else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0; else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4]; // synopsys translate_off initial dffe6a[5:5] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[5:5] <= 1'b1; else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0; else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5]; // synopsys translate_off initial dffe6a[6:6] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[6:6] <= 1'b1; else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0; else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6]; // synopsys translate_off initial dffe6a[7:7] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[7:7] <= 1'b1; else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0; else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7]; // synopsys translate_off initial dffe6a[8:8] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[8:8] <= 1'b1; else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0; else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8]; // synopsys translate_off initial dffe6a[9:9] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[9:9] <= 1'b1; else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0; else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9]; // synopsys translate_off initial dffe6a[10:10] = 0; // synopsys translate_on always @ ( posedge clock or negedge prn or negedge clrn) if (prn == 1'b0) dffe6a[10:10] <= 1'b1; else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0; else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10]; assign wire_dffe6a_D = (d & {11{(~ sclr)}}); assign ena = 1'b1, prn = 1'b1, q = dffe6a, sclr = 1'b0; endmodule //fifo_2k_dffpipe_dm2 //synthesis_resources = lut 11 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_alt_synch_pipe_dm2 ( clock, clrn, d, q) /* synthesis synthesis_clearbox=1 */ /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */; input clock; input clrn; input [10:0] d; output [10:0] q; wire [10:0] wire_dffpipe5_q; fifo_2k_dffpipe_dm2 dffpipe5 ( .clock(clock), .clrn(clrn), .d(d), .q(wire_dffpipe5_q)); assign q = wire_dffpipe5_q; endmodule //fifo_2k_alt_synch_pipe_dm2 //lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=11 dataa datab result //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END //synthesis_resources = lut 11 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_add_sub_a18 ( dataa, datab, result) /* synthesis synthesis_clearbox=1 */; input [10:0] dataa; input [10:0] datab; output [10:0] result; wire [10:0] wire_add_sub_cella_combout; wire [0:0] wire_add_sub_cella_0cout; wire [0:0] wire_add_sub_cella_1cout; wire [0:0] wire_add_sub_cella_2cout; wire [0:0] wire_add_sub_cella_3cout; wire [0:0] wire_add_sub_cella_4cout; wire [0:0] wire_add_sub_cella_5cout; wire [0:0] wire_add_sub_cella_6cout; wire [0:0] wire_add_sub_cella_7cout; wire [0:0] wire_add_sub_cella_8cout; wire [0:0] wire_add_sub_cella_9cout; wire [10:0] wire_add_sub_cella_dataa; wire [10:0] wire_add_sub_cella_datab; cyclone_lcell add_sub_cella_0 ( .cin(1'b1), .combout(wire_add_sub_cella_combout[0:0]), .cout(wire_add_sub_cella_0cout[0:0]), .dataa(wire_add_sub_cella_dataa[0:0]), .datab(wire_add_sub_cella_datab[0:0]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_0.cin_used = "true", add_sub_cella_0.lut_mask = "69b2", add_sub_cella_0.operation_mode = "arithmetic", add_sub_cella_0.sum_lutc_input = "cin", add_sub_cella_0.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_1 ( .cin(wire_add_sub_cella_0cout[0:0]), .combout(wire_add_sub_cella_combout[1:1]), .cout(wire_add_sub_cella_1cout[0:0]), .dataa(wire_add_sub_cella_dataa[1:1]), .datab(wire_add_sub_cella_datab[1:1]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_1.cin_used = "true", add_sub_cella_1.lut_mask = "69b2", add_sub_cella_1.operation_mode = "arithmetic", add_sub_cella_1.sum_lutc_input = "cin", add_sub_cella_1.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_2 ( .cin(wire_add_sub_cella_1cout[0:0]), .combout(wire_add_sub_cella_combout[2:2]), .cout(wire_add_sub_cella_2cout[0:0]), .dataa(wire_add_sub_cella_dataa[2:2]), .datab(wire_add_sub_cella_datab[2:2]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_2.cin_used = "true", add_sub_cella_2.lut_mask = "69b2", add_sub_cella_2.operation_mode = "arithmetic", add_sub_cella_2.sum_lutc_input = "cin", add_sub_cella_2.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_3 ( .cin(wire_add_sub_cella_2cout[0:0]), .combout(wire_add_sub_cella_combout[3:3]), .cout(wire_add_sub_cella_3cout[0:0]), .dataa(wire_add_sub_cella_dataa[3:3]), .datab(wire_add_sub_cella_datab[3:3]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_3.cin_used = "true", add_sub_cella_3.lut_mask = "69b2", add_sub_cella_3.operation_mode = "arithmetic", add_sub_cella_3.sum_lutc_input = "cin", add_sub_cella_3.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_4 ( .cin(wire_add_sub_cella_3cout[0:0]), .combout(wire_add_sub_cella_combout[4:4]), .cout(wire_add_sub_cella_4cout[0:0]), .dataa(wire_add_sub_cella_dataa[4:4]), .datab(wire_add_sub_cella_datab[4:4]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_4.cin_used = "true", add_sub_cella_4.lut_mask = "69b2", add_sub_cella_4.operation_mode = "arithmetic", add_sub_cella_4.sum_lutc_input = "cin", add_sub_cella_4.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_5 ( .cin(wire_add_sub_cella_4cout[0:0]), .combout(wire_add_sub_cella_combout[5:5]), .cout(wire_add_sub_cella_5cout[0:0]), .dataa(wire_add_sub_cella_dataa[5:5]), .datab(wire_add_sub_cella_datab[5:5]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_5.cin_used = "true", add_sub_cella_5.lut_mask = "69b2", add_sub_cella_5.operation_mode = "arithmetic", add_sub_cella_5.sum_lutc_input = "cin", add_sub_cella_5.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_6 ( .cin(wire_add_sub_cella_5cout[0:0]), .combout(wire_add_sub_cella_combout[6:6]), .cout(wire_add_sub_cella_6cout[0:0]), .dataa(wire_add_sub_cella_dataa[6:6]), .datab(wire_add_sub_cella_datab[6:6]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_6.cin_used = "true", add_sub_cella_6.lut_mask = "69b2", add_sub_cella_6.operation_mode = "arithmetic", add_sub_cella_6.sum_lutc_input = "cin", add_sub_cella_6.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_7 ( .cin(wire_add_sub_cella_6cout[0:0]), .combout(wire_add_sub_cella_combout[7:7]), .cout(wire_add_sub_cella_7cout[0:0]), .dataa(wire_add_sub_cella_dataa[7:7]), .datab(wire_add_sub_cella_datab[7:7]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_7.cin_used = "true", add_sub_cella_7.lut_mask = "69b2", add_sub_cella_7.operation_mode = "arithmetic", add_sub_cella_7.sum_lutc_input = "cin", add_sub_cella_7.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_8 ( .cin(wire_add_sub_cella_7cout[0:0]), .combout(wire_add_sub_cella_combout[8:8]), .cout(wire_add_sub_cella_8cout[0:0]), .dataa(wire_add_sub_cella_dataa[8:8]), .datab(wire_add_sub_cella_datab[8:8]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_8.cin_used = "true", add_sub_cella_8.lut_mask = "69b2", add_sub_cella_8.operation_mode = "arithmetic", add_sub_cella_8.sum_lutc_input = "cin", add_sub_cella_8.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_9 ( .cin(wire_add_sub_cella_8cout[0:0]), .combout(wire_add_sub_cella_combout[9:9]), .cout(wire_add_sub_cella_9cout[0:0]), .dataa(wire_add_sub_cella_dataa[9:9]), .datab(wire_add_sub_cella_datab[9:9]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_9.cin_used = "true", add_sub_cella_9.lut_mask = "69b2", add_sub_cella_9.operation_mode = "arithmetic", add_sub_cella_9.sum_lutc_input = "cin", add_sub_cella_9.lpm_type = "cyclone_lcell"; cyclone_lcell add_sub_cella_10 ( .cin(wire_add_sub_cella_9cout[0:0]), .combout(wire_add_sub_cella_combout[10:10]), .cout(), .dataa(wire_add_sub_cella_dataa[10:10]), .datab(wire_add_sub_cella_datab[10:10]), .regout() `ifdef FORMAL_VERIFICATION `else // synopsys translate_off `endif , .aclr(1'b0), .aload(1'b0), .clk(1'b1), .datac(1'b1), .datad(1'b1), .ena(1'b1), .inverta(1'b0), .regcascin(1'b0), .sclr(1'b0), .sload(1'b0) `ifdef FORMAL_VERIFICATION `else // synopsys translate_on `endif // synopsys translate_off , .cin0(), .cin1(), .cout0(), .cout1(), .devclrn(), .devpor() // synopsys translate_on ); defparam add_sub_cella_10.cin_used = "true", add_sub_cella_10.lut_mask = "6969", add_sub_cella_10.operation_mode = "normal", add_sub_cella_10.sum_lutc_input = "cin", add_sub_cella_10.lpm_type = "cyclone_lcell"; assign wire_add_sub_cella_dataa = dataa, wire_add_sub_cella_datab = datab; assign result = wire_add_sub_cella_combout; endmodule //fifo_2k_add_sub_a18 //lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END //lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END //synthesis_resources = lut 97 M4K 8 //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module fifo_2k_dcfifo_0cq ( aclr, data, q, rdclk, rdempty, rdreq, rdusedw, wrclk, wrfull, wrreq, wrusedw) /* synthesis synthesis_clearbox=1 */ /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */; input aclr; input [15:0] data; output [15:0] q; input rdclk; output rdempty; input rdreq; output [10:0] rdusedw; input wrclk; output wrfull; input wrreq; output [10:0] wrusedw; wire [10:0] wire_rdptr_g_gray2bin_bin; wire [10:0] wire_rs_dgwp_gray2bin_bin; wire [10:0] wire_wrptr_g_gray2bin_bin; wire [10:0] wire_ws_dgrp_gray2bin_bin; wire [10:0] wire_rdptr_g_q; wire [10:0] wire_rdptr_g1p_q; wire [10:0] wire_wrptr_g1p_q; wire [15:0] wire_fifo_ram_q_b; reg [10:0] delayed_wrptr_g; reg [10:0] wrptr_g; wire [10:0] wire_rs_brp_q; wire [10:0] wire_rs_bwp_q; wire [10:0] wire_rs_dgwp_q; wire [10:0] wire_ws_brp_q; wire [10:0] wire_ws_bwp_q; wire [10:0] wire_ws_dgrp_q; wire [10:0] wire_rdusedw_sub_result; wire [10:0] wire_wrusedw_sub_result; reg wire_rdempty_eq_comp_aeb_int; wire wire_rdempty_eq_comp_aeb; wire [10:0] wire_rdempty_eq_comp_dataa; wire [10:0] wire_rdempty_eq_comp_datab; reg wire_wrfull_eq_comp_aeb_int; wire wire_wrfull_eq_comp_aeb; wire [10:0] wire_wrfull_eq_comp_dataa; wire [10:0] wire_wrfull_eq_comp_datab; wire int_rdempty; wire int_wrfull; wire valid_rdreq; wire valid_wrreq; fifo_2k_a_gray2bin_8m4 rdptr_g_gray2bin ( .bin(wire_rdptr_g_gray2bin_bin), .gray(wire_rdptr_g_q)); fifo_2k_a_gray2bin_8m4 rs_dgwp_gray2bin ( .bin(wire_rs_dgwp_gray2bin_bin), .gray(wire_rs_dgwp_q)); fifo_2k_a_gray2bin_8m4 wrptr_g_gray2bin ( .bin(wire_wrptr_g_gray2bin_bin), .gray(wrptr_g)); fifo_2k_a_gray2bin_8m4 ws_dgrp_gray2bin ( .bin(wire_ws_dgrp_gray2bin_bin), .gray(wire_ws_dgrp_q)); fifo_2k_a_graycounter_726 rdptr_g ( .aclr(aclr), .clock(rdclk), .cnt_en(valid_rdreq), .q(wire_rdptr_g_q)); fifo_2k_a_graycounter_2r6 rdptr_g1p ( .aclr(aclr), .clock(rdclk), .cnt_en(valid_rdreq), .q(wire_rdptr_g1p_q)); fifo_2k_a_graycounter_2r6 wrptr_g1p ( .aclr(aclr), .clock(wrclk), .cnt_en(valid_wrreq), .q(wire_wrptr_g1p_q)); fifo_2k_altsyncram_6pl fifo_ram ( .address_a(wrptr_g), .address_b(((wire_rdptr_g_q & {11{int_rdempty}}) | (wire_rdptr_g1p_q & {11{(~ int_rdempty)}}))), .clock0(wrclk), .clock1(rdclk), .clocken1((valid_rdreq | int_rdempty)), .data_a(data), .q_b(wire_fifo_ram_q_b), .wren_a(valid_wrreq)); // synopsys translate_off initial delayed_wrptr_g = 0; // synopsys translate_on always @ ( posedge wrclk or posedge aclr) if (aclr == 1'b1) delayed_wrptr_g <= 11'b0; else delayed_wrptr_g <= wrptr_g; // synopsys translate_off initial wrptr_g = 0; // synopsys translate_on always @ ( posedge wrclk or posedge aclr) if (aclr == 1'b1) wrptr_g <= 11'b0; else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q; fifo_2k_dffpipe_ab3 rs_brp ( .clock(rdclk), .clrn((~ aclr)), .d(wire_rdptr_g_gray2bin_bin), .q(wire_rs_brp_q)); fifo_2k_dffpipe_ab3 rs_bwp ( .clock(rdclk), .clrn((~ aclr)), .d(wire_rs_dgwp_gray2bin_bin), .q(wire_rs_bwp_q)); fifo_2k_alt_synch_pipe_dm2 rs_dgwp ( .clock(rdclk), .clrn((~ aclr)), .d(delayed_wrptr_g), .q(wire_rs_dgwp_q)); fifo_2k_dffpipe_ab3 ws_brp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_ws_dgrp_gray2bin_bin), .q(wire_ws_brp_q)); fifo_2k_dffpipe_ab3 ws_bwp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_wrptr_g_gray2bin_bin), .q(wire_ws_bwp_q)); fifo_2k_alt_synch_pipe_dm2 ws_dgrp ( .clock(wrclk), .clrn((~ aclr)), .d(wire_rdptr_g_q), .q(wire_ws_dgrp_q)); fifo_2k_add_sub_a18 rdusedw_sub ( .dataa(wire_rs_bwp_q), .datab(wire_rs_brp_q), .result(wire_rdusedw_sub_result)); fifo_2k_add_sub_a18 wrusedw_sub ( .dataa(wire_ws_bwp_q), .datab(wire_ws_brp_q), .result(wire_wrusedw_sub_result)); always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab) if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) begin wire_rdempty_eq_comp_aeb_int = 1'b1; end else begin wire_rdempty_eq_comp_aeb_int = 1'b0; end assign wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int; assign wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q, wire_rdempty_eq_comp_datab = wire_rdptr_g_q; always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab) if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) begin wire_wrfull_eq_comp_aeb_int = 1'b1; end else begin wire_wrfull_eq_comp_aeb_int = 1'b0; end assign wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int; assign wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q, wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q; assign int_rdempty = wire_rdempty_eq_comp_aeb, int_wrfull = wire_wrfull_eq_comp_aeb, q = wire_fifo_ram_q_b, rdempty = int_rdempty, rdusedw = wire_rdusedw_sub_result, valid_rdreq = rdreq, valid_wrreq = wrreq, wrfull = int_wrfull, wrusedw = wire_wrusedw_sub_result; endmodule //fifo_2k_dcfifo_0cq //VALID FILE // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module fifo_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, rdempty, rdusedw, wrfull, wrusedw)/* synthesis synthesis_clearbox = 1 */; input [15:0] data; input wrreq; input rdreq; input rdclk; input wrclk; input aclr; output [15:0] q; output rdempty; output [10:0] rdusedw; output wrfull; output [10:0] wrusedw; wire sub_wire0; wire [10:0] sub_wire1; wire sub_wire2; wire [15:0] sub_wire3; wire [10:0] sub_wire4; wire rdempty = sub_wire0; wire [10:0] wrusedw = sub_wire1[10:0]; wire wrfull = sub_wire2; wire [15:0] q = sub_wire3[15:0]; wire [10:0] rdusedw = sub_wire4[10:0]; fifo_2k_dcfifo_0cq fifo_2k_dcfifo_0cq_component ( .wrclk (wrclk), .rdreq (rdreq), .aclr (aclr), .rdclk (rdclk), .wrreq (wrreq), .data (data), .rdempty (sub_wire0), .wrusedw (sub_wire1), .wrfull (sub_wire2), .q (sub_wire3), .rdusedw (sub_wire4)); endmodule // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: Width NUMERIC "16" // Retrieval info: PRIVATE: Depth NUMERIC "2048" // Retrieval info: PRIVATE: Clock NUMERIC "4" // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" // Retrieval info: PRIVATE: Full NUMERIC "1" // Retrieval info: PRIVATE: Empty NUMERIC "1" // Retrieval info: PRIVATE: UsedW NUMERIC "1" // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" // Retrieval info: PRIVATE: sc_aclr NUMERIC "0" // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" // Retrieval info: PRIVATE: rsFull NUMERIC "0" // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" // Retrieval info: PRIVATE: rsUsedW NUMERIC "1" // Retrieval info: PRIVATE: wsFull NUMERIC "1" // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" // Retrieval info: PRIVATE: wsUsedW NUMERIC "1" // Retrieval info: PRIVATE: dc_aclr NUMERIC "1" // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" // Retrieval info: PRIVATE: Optimize NUMERIC "2" // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048" // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE" // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" // Retrieval info: CONSTANT: USE_EAB STRING "ON" // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty // Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0] // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull // Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0] // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr // Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 // Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 // Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0 // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0 // Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0 // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE

// (C) 2001-2016 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // (C) 2001-2013 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $ // $Revision: #1 $ // $Date: 2016/02/08 $ // $Author: swbranch $ // -------------------------------------- // Reset controller // // Combines all the input resets and synchronizes // the result to the clk. // ACDS13.1 - Added reset request as part of reset sequencing // -------------------------------------- `timescale 1 ns / 1 ns module altera_reset_controller #( parameter NUM_RESET_INPUTS = 6, parameter USE_RESET_REQUEST_IN0 = 0, parameter USE_RESET_REQUEST_IN1 = 0, parameter USE_RESET_REQUEST_IN2 = 0, parameter USE_RESET_REQUEST_IN3 = 0, parameter USE_RESET_REQUEST_IN4 = 0, parameter USE_RESET_REQUEST_IN5 = 0, parameter USE_RESET_REQUEST_IN6 = 0, parameter USE_RESET_REQUEST_IN7 = 0, parameter USE_RESET_REQUEST_IN8 = 0, parameter USE_RESET_REQUEST_IN9 = 0, parameter USE_RESET_REQUEST_IN10 = 0, parameter USE_RESET_REQUEST_IN11 = 0, parameter USE_RESET_REQUEST_IN12 = 0, parameter USE_RESET_REQUEST_IN13 = 0, parameter USE_RESET_REQUEST_IN14 = 0, parameter USE_RESET_REQUEST_IN15 = 0, parameter OUTPUT_RESET_SYNC_EDGES = "deassert", parameter SYNC_DEPTH = 2, parameter RESET_REQUEST_PRESENT = 0, parameter RESET_REQ_WAIT_TIME = 3, parameter MIN_RST_ASSERTION_TIME = 11, parameter RESET_REQ_EARLY_DSRT_TIME = 4, parameter ADAPT_RESET_REQUEST = 0 ) ( // -------------------------------------- // We support up to 16 reset inputs, for now // -------------------------------------- input reset_in0, input reset_in1, input reset_in2, input reset_in3, input reset_in4, input reset_in5, input reset_in6, input reset_in7, input reset_in8, input reset_in9, input reset_in10, input reset_in11, input reset_in12, input reset_in13, input reset_in14, input reset_in15, input reset_req_in0, input reset_req_in1, input reset_req_in2, input reset_req_in3, input reset_req_in4, input reset_req_in5, input reset_req_in6, input reset_req_in7, input reset_req_in8, input reset_req_in9, input reset_req_in10, input reset_req_in11, input reset_req_in12, input reset_req_in13, input reset_req_in14, input reset_req_in15, input clk, output reg reset_out, output reg reset_req ); // Always use async reset synchronizer if reset_req is used localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); // -------------------------------------- // Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1 // -------------------------------------- localparam MIN_METASTABLE = 3; localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME; localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME; localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ? MIN_RST_ASSERTION_TIME + 1 : ( (MIN_RST_ASSERTION_TIME > LARGER)? MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 : MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2 ); localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1; // -------------------------------------- wire merged_reset; wire merged_reset_req_in; wire reset_out_pre; wire reset_req_pre; // Registers and Interconnect (*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain; reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain; reg r_sync_rst; reg r_early_rst; // -------------------------------------- // "Or" all the input resets together // -------------------------------------- assign merged_reset = ( reset_in0 | reset_in1 | reset_in2 | reset_in3 | reset_in4 | reset_in5 | reset_in6 | reset_in7 | reset_in8 | reset_in9 | reset_in10 | reset_in11 | reset_in12 | reset_in13 | reset_in14 | reset_in15 ); assign merged_reset_req_in = ( ( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) | ( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) | ( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) | ( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) | ( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) | ( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) | ( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) | ( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) | ( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) | ( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) | ( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) | ( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) | ( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) | ( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) | ( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) | ( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0) ); // -------------------------------------- // And if required, synchronize it to the required clock domain, // with the correct synchronization type // -------------------------------------- generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin assign reset_out_pre = merged_reset; assign reset_req_pre = merged_reset_req_in; end else begin altera_reset_synchronizer #( .DEPTH (SYNC_DEPTH), .ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET) ) alt_rst_sync_uq1 ( .clk (clk), .reset_in (merged_reset), .reset_out (reset_out_pre) ); altera_reset_synchronizer #( .DEPTH (SYNC_DEPTH), .ASYNC_RESET(0) ) alt_rst_req_sync_uq1 ( .clk (clk), .reset_in (merged_reset_req_in), .reset_out (reset_req_pre) ); end endgenerate generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )| ( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin always @* begin reset_out = reset_out_pre; reset_req = reset_req_pre; end end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin wire reset_out_pre2; altera_reset_synchronizer #( .DEPTH (SYNC_DEPTH+1), .ASYNC_RESET(0) ) alt_rst_sync_uq2 ( .clk (clk), .reset_in (reset_out_pre), .reset_out (reset_out_pre2) ); always @* begin reset_out = reset_out_pre2; reset_req = reset_req_pre; end end else begin // 3-FF Metastability Synchronizer initial begin altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}}; end always @(posedge clk) begin altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <= {altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre}; end // Synchronous reset pipe initial begin r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}}; end always @(posedge clk) begin if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1) begin r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}}; end else begin r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]}; end end // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition // matches the early input. always @(posedge clk) begin case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst}) 3'b000: r_sync_rst <= 1'b0; // Not reset 3'b001: r_sync_rst <= 1'b0; 3'b010: r_sync_rst <= 1'b0; 3'b011: r_sync_rst <= 1'b1; 3'b100: r_sync_rst <= 1'b1; 3'b101: r_sync_rst <= 1'b1; 3'b110: r_sync_rst <= 1'b1; 3'b111: r_sync_rst <= 1'b1; // In Reset default: r_sync_rst <= 1'b1; endcase case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre}) 2'b00: r_early_rst <= 1'b0; // Not reset 2'b01: r_early_rst <= 1'b1; // Coming out of reset 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. 2'b11: r_early_rst <= 1'b1; // Held in reset default: r_early_rst <= 1'b1; endcase end always @* begin reset_out = r_sync_rst; reset_req = r_early_rst; end end endgenerate endmodule

// (C) 2001-2016 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // (C) 2001-2013 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $ // $Revision: #1 $ // $Date: 2016/02/08 $ // $Author: swbranch $ // -------------------------------------- // Reset controller // // Combines all the input resets and synchronizes // the result to the clk. // ACDS13.1 - Added reset request as part of reset sequencing // -------------------------------------- `timescale 1 ns / 1 ns module altera_reset_controller #( parameter NUM_RESET_INPUTS = 6, parameter USE_RESET_REQUEST_IN0 = 0, parameter USE_RESET_REQUEST_IN1 = 0, parameter USE_RESET_REQUEST_IN2 = 0, parameter USE_RESET_REQUEST_IN3 = 0, parameter USE_RESET_REQUEST_IN4 = 0, parameter USE_RESET_REQUEST_IN5 = 0, parameter USE_RESET_REQUEST_IN6 = 0, parameter USE_RESET_REQUEST_IN7 = 0, parameter USE_RESET_REQUEST_IN8 = 0, parameter USE_RESET_REQUEST_IN9 = 0, parameter USE_RESET_REQUEST_IN10 = 0, parameter USE_RESET_REQUEST_IN11 = 0, parameter USE_RESET_REQUEST_IN12 = 0, parameter USE_RESET_REQUEST_IN13 = 0, parameter USE_RESET_REQUEST_IN14 = 0, parameter USE_RESET_REQUEST_IN15 = 0, parameter OUTPUT_RESET_SYNC_EDGES = "deassert", parameter SYNC_DEPTH = 2, parameter RESET_REQUEST_PRESENT = 0, parameter RESET_REQ_WAIT_TIME = 3, parameter MIN_RST_ASSERTION_TIME = 11, parameter RESET_REQ_EARLY_DSRT_TIME = 4, parameter ADAPT_RESET_REQUEST = 0 ) ( // -------------------------------------- // We support up to 16 reset inputs, for now // -------------------------------------- input reset_in0, input reset_in1, input reset_in2, input reset_in3, input reset_in4, input reset_in5, input reset_in6, input reset_in7, input reset_in8, input reset_in9, input reset_in10, input reset_in11, input reset_in12, input reset_in13, input reset_in14, input reset_in15, input reset_req_in0, input reset_req_in1, input reset_req_in2, input reset_req_in3, input reset_req_in4, input reset_req_in5, input reset_req_in6, input reset_req_in7, input reset_req_in8, input reset_req_in9, input reset_req_in10, input reset_req_in11, input reset_req_in12, input reset_req_in13, input reset_req_in14, input reset_req_in15, input clk, output reg reset_out, output reg reset_req ); // Always use async reset synchronizer if reset_req is used localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); // -------------------------------------- // Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1 // -------------------------------------- localparam MIN_METASTABLE = 3; localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME; localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME; localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ? MIN_RST_ASSERTION_TIME + 1 : ( (MIN_RST_ASSERTION_TIME > LARGER)? MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 : MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2 ); localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1; // -------------------------------------- wire merged_reset; wire merged_reset_req_in; wire reset_out_pre; wire reset_req_pre; // Registers and Interconnect (*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain; reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain; reg r_sync_rst; reg r_early_rst; // -------------------------------------- // "Or" all the input resets together // -------------------------------------- assign merged_reset = ( reset_in0 | reset_in1 | reset_in2 | reset_in3 | reset_in4 | reset_in5 | reset_in6 | reset_in7 | reset_in8 | reset_in9 | reset_in10 | reset_in11 | reset_in12 | reset_in13 | reset_in14 | reset_in15 ); assign merged_reset_req_in = ( ( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) | ( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) | ( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) | ( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) | ( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) | ( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) | ( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) | ( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) | ( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) | ( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) | ( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) | ( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) | ( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) | ( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) | ( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) | ( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0) ); // -------------------------------------- // And if required, synchronize it to the required clock domain, // with the correct synchronization type // -------------------------------------- generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin assign reset_out_pre = merged_reset; assign reset_req_pre = merged_reset_req_in; end else begin altera_reset_synchronizer #( .DEPTH (SYNC_DEPTH), .ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET) ) alt_rst_sync_uq1 ( .clk (clk), .reset_in (merged_reset), .reset_out (reset_out_pre) ); altera_reset_synchronizer #( .DEPTH (SYNC_DEPTH), .ASYNC_RESET(0) ) alt_rst_req_sync_uq1 ( .clk (clk), .reset_in (merged_reset_req_in), .reset_out (reset_req_pre) ); end endgenerate generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )| ( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin always @* begin reset_out = reset_out_pre; reset_req = reset_req_pre; end end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin wire reset_out_pre2; altera_reset_synchronizer #( .DEPTH (SYNC_DEPTH+1), .ASYNC_RESET(0) ) alt_rst_sync_uq2 ( .clk (clk), .reset_in (reset_out_pre), .reset_out (reset_out_pre2) ); always @* begin reset_out = reset_out_pre2; reset_req = reset_req_pre; end end else begin // 3-FF Metastability Synchronizer initial begin altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}}; end always @(posedge clk) begin altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <= {altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre}; end // Synchronous reset pipe initial begin r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}}; end always @(posedge clk) begin if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1) begin r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}}; end else begin r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]}; end end // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition // matches the early input. always @(posedge clk) begin case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst}) 3'b000: r_sync_rst <= 1'b0; // Not reset 3'b001: r_sync_rst <= 1'b0; 3'b010: r_sync_rst <= 1'b0; 3'b011: r_sync_rst <= 1'b1; 3'b100: r_sync_rst <= 1'b1; 3'b101: r_sync_rst <= 1'b1; 3'b110: r_sync_rst <= 1'b1; 3'b111: r_sync_rst <= 1'b1; // In Reset default: r_sync_rst <= 1'b1; endcase case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre}) 2'b00: r_early_rst <= 1'b0; // Not reset 2'b01: r_early_rst <= 1'b1; // Coming out of reset 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. 2'b11: r_early_rst <= 1'b1; // Held in reset default: r_early_rst <= 1'b1; endcase end always @* begin reset_out = r_sync_rst; reset_req = r_early_rst; end end endgenerate endmodule

// (C) 2001-2016 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // (C) 2001-2013 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $ // $Revision: #1 $ // $Date: 2016/02/08 $ // $Author: swbranch $ // -------------------------------------- // Reset controller // // Combines all the input resets and synchronizes // the result to the clk. // ACDS13.1 - Added reset request as part of reset sequencing // -------------------------------------- `timescale 1 ns / 1 ns module altera_reset_controller #( parameter NUM_RESET_INPUTS = 6, parameter USE_RESET_REQUEST_IN0 = 0, parameter USE_RESET_REQUEST_IN1 = 0, parameter USE_RESET_REQUEST_IN2 = 0, parameter USE_RESET_REQUEST_IN3 = 0, parameter USE_RESET_REQUEST_IN4 = 0, parameter USE_RESET_REQUEST_IN5 = 0, parameter USE_RESET_REQUEST_IN6 = 0, parameter USE_RESET_REQUEST_IN7 = 0, parameter USE_RESET_REQUEST_IN8 = 0, parameter USE_RESET_REQUEST_IN9 = 0, parameter USE_RESET_REQUEST_IN10 = 0, parameter USE_RESET_REQUEST_IN11 = 0, parameter USE_RESET_REQUEST_IN12 = 0, parameter USE_RESET_REQUEST_IN13 = 0, parameter USE_RESET_REQUEST_IN14 = 0, parameter USE_RESET_REQUEST_IN15 = 0, parameter OUTPUT_RESET_SYNC_EDGES = "deassert", parameter SYNC_DEPTH = 2, parameter RESET_REQUEST_PRESENT = 0, parameter RESET_REQ_WAIT_TIME = 3, parameter MIN_RST_ASSERTION_TIME = 11, parameter RESET_REQ_EARLY_DSRT_TIME = 4, parameter ADAPT_RESET_REQUEST = 0 ) ( // -------------------------------------- // We support up to 16 reset inputs, for now // -------------------------------------- input reset_in0, input reset_in1, input reset_in2, input reset_in3, input reset_in4, input reset_in5, input reset_in6, input reset_in7, input reset_in8, input reset_in9, input reset_in10, input reset_in11, input reset_in12, input reset_in13, input reset_in14, input reset_in15, input reset_req_in0, input reset_req_in1, input reset_req_in2, input reset_req_in3, input reset_req_in4, input reset_req_in5, input reset_req_in6, input reset_req_in7, input reset_req_in8, input reset_req_in9, input reset_req_in10, input reset_req_in11, input reset_req_in12, input reset_req_in13, input reset_req_in14, input reset_req_in15, input clk, output reg reset_out, output reg reset_req ); // Always use async reset synchronizer if reset_req is used localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); // -------------------------------------- // Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1 // -------------------------------------- localparam MIN_METASTABLE = 3; localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME; localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME; localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ? MIN_RST_ASSERTION_TIME + 1 : ( (MIN_RST_ASSERTION_TIME > LARGER)? MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 : MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2 ); localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1; // -------------------------------------- wire merged_reset; wire merged_reset_req_in; wire reset_out_pre; wire reset_req_pre; // Registers and Interconnect (*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain; reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain; reg r_sync_rst; reg r_early_rst; // -------------------------------------- // "Or" all the input resets together // -------------------------------------- assign merged_reset = ( reset_in0 | reset_in1 | reset_in2 | reset_in3 | reset_in4 | reset_in5 | reset_in6 | reset_in7 | reset_in8 | reset_in9 | reset_in10 | reset_in11 | reset_in12 | reset_in13 | reset_in14 | reset_in15 ); assign merged_reset_req_in = ( ( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) | ( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) | ( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) | ( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) | ( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) | ( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) | ( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) | ( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) | ( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) | ( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) | ( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) | ( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) | ( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) | ( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) | ( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) | ( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0) ); // -------------------------------------- // And if required, synchronize it to the required clock domain, // with the correct synchronization type // -------------------------------------- generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin assign reset_out_pre = merged_reset; assign reset_req_pre = merged_reset_req_in; end else begin altera_reset_synchronizer #( .DEPTH (SYNC_DEPTH), .ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET) ) alt_rst_sync_uq1 ( .clk (clk), .reset_in (merged_reset), .reset_out (reset_out_pre) ); altera_reset_synchronizer #( .DEPTH (SYNC_DEPTH), .ASYNC_RESET(0) ) alt_rst_req_sync_uq1 ( .clk (clk), .reset_in (merged_reset_req_in), .reset_out (reset_req_pre) ); end endgenerate generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )| ( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin always @* begin reset_out = reset_out_pre; reset_req = reset_req_pre; end end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin wire reset_out_pre2; altera_reset_synchronizer #( .DEPTH (SYNC_DEPTH+1), .ASYNC_RESET(0) ) alt_rst_sync_uq2 ( .clk (clk), .reset_in (reset_out_pre), .reset_out (reset_out_pre2) ); always @* begin reset_out = reset_out_pre2; reset_req = reset_req_pre; end end else begin // 3-FF Metastability Synchronizer initial begin altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}}; end always @(posedge clk) begin altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <= {altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre}; end // Synchronous reset pipe initial begin r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}}; end always @(posedge clk) begin if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1) begin r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}}; end else begin r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]}; end end // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition // matches the early input. always @(posedge clk) begin case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst}) 3'b000: r_sync_rst <= 1'b0; // Not reset 3'b001: r_sync_rst <= 1'b0; 3'b010: r_sync_rst <= 1'b0; 3'b011: r_sync_rst <= 1'b1; 3'b100: r_sync_rst <= 1'b1; 3'b101: r_sync_rst <= 1'b1; 3'b110: r_sync_rst <= 1'b1; 3'b111: r_sync_rst <= 1'b1; // In Reset default: r_sync_rst <= 1'b1; endcase case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre}) 2'b00: r_early_rst <= 1'b0; // Not reset 2'b01: r_early_rst <= 1'b1; // Coming out of reset 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. 2'b11: r_early_rst <= 1'b1; // Held in reset default: r_early_rst <= 1'b1; endcase end always @* begin reset_out = r_sync_rst; reset_req = r_early_rst; end end endgenerate endmodule

// (C) 2001-2016 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // (C) 2001-2013 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $ // $Revision: #1 $ // $Date: 2016/02/08 $ // $Author: swbranch $ // -------------------------------------- // Reset controller // // Combines all the input resets and synchronizes // the result to the clk. // ACDS13.1 - Added reset request as part of reset sequencing // -------------------------------------- `timescale 1 ns / 1 ns module altera_reset_controller #( parameter NUM_RESET_INPUTS = 6, parameter USE_RESET_REQUEST_IN0 = 0, parameter USE_RESET_REQUEST_IN1 = 0, parameter USE_RESET_REQUEST_IN2 = 0, parameter USE_RESET_REQUEST_IN3 = 0, parameter USE_RESET_REQUEST_IN4 = 0, parameter USE_RESET_REQUEST_IN5 = 0, parameter USE_RESET_REQUEST_IN6 = 0, parameter USE_RESET_REQUEST_IN7 = 0, parameter USE_RESET_REQUEST_IN8 = 0, parameter USE_RESET_REQUEST_IN9 = 0, parameter USE_RESET_REQUEST_IN10 = 0, parameter USE_RESET_REQUEST_IN11 = 0, parameter USE_RESET_REQUEST_IN12 = 0, parameter USE_RESET_REQUEST_IN13 = 0, parameter USE_RESET_REQUEST_IN14 = 0, parameter USE_RESET_REQUEST_IN15 = 0, parameter OUTPUT_RESET_SYNC_EDGES = "deassert", parameter SYNC_DEPTH = 2, parameter RESET_REQUEST_PRESENT = 0, parameter RESET_REQ_WAIT_TIME = 3, parameter MIN_RST_ASSERTION_TIME = 11, parameter RESET_REQ_EARLY_DSRT_TIME = 4, parameter ADAPT_RESET_REQUEST = 0 ) ( // -------------------------------------- // We support up to 16 reset inputs, for now // -------------------------------------- input reset_in0, input reset_in1, input reset_in2, input reset_in3, input reset_in4, input reset_in5, input reset_in6, input reset_in7, input reset_in8, input reset_in9, input reset_in10, input reset_in11, input reset_in12, input reset_in13, input reset_in14, input reset_in15, input reset_req_in0, input reset_req_in1, input reset_req_in2, input reset_req_in3, input reset_req_in4, input reset_req_in5, input reset_req_in6, input reset_req_in7, input reset_req_in8, input reset_req_in9, input reset_req_in10, input reset_req_in11, input reset_req_in12, input reset_req_in13, input reset_req_in14, input reset_req_in15, input clk, output reg reset_out, output reg reset_req ); // Always use async reset synchronizer if reset_req is used localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); // -------------------------------------- // Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1 // -------------------------------------- localparam MIN_METASTABLE = 3; localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME; localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME; localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ? MIN_RST_ASSERTION_TIME + 1 : ( (MIN_RST_ASSERTION_TIME > LARGER)? MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 : MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2 ); localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1; // -------------------------------------- wire merged_reset; wire merged_reset_req_in; wire reset_out_pre; wire reset_req_pre; // Registers and Interconnect (*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain; reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain; reg r_sync_rst; reg r_early_rst; // -------------------------------------- // "Or" all the input resets together // -------------------------------------- assign merged_reset = ( reset_in0 | reset_in1 | reset_in2 | reset_in3 | reset_in4 | reset_in5 | reset_in6 | reset_in7 | reset_in8 | reset_in9 | reset_in10 | reset_in11 | reset_in12 | reset_in13 | reset_in14 | reset_in15 ); assign merged_reset_req_in = ( ( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) | ( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) | ( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) | ( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) | ( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) | ( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) | ( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) | ( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) | ( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) | ( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) | ( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) | ( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) | ( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) | ( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) | ( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) | ( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0) ); // -------------------------------------- // And if required, synchronize it to the required clock domain, // with the correct synchronization type // -------------------------------------- generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin assign reset_out_pre = merged_reset; assign reset_req_pre = merged_reset_req_in; end else begin altera_reset_synchronizer #( .DEPTH (SYNC_DEPTH), .ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET) ) alt_rst_sync_uq1 ( .clk (clk), .reset_in (merged_reset), .reset_out (reset_out_pre) ); altera_reset_synchronizer #( .DEPTH (SYNC_DEPTH), .ASYNC_RESET(0) ) alt_rst_req_sync_uq1 ( .clk (clk), .reset_in (merged_reset_req_in), .reset_out (reset_req_pre) ); end endgenerate generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )| ( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin always @* begin reset_out = reset_out_pre; reset_req = reset_req_pre; end end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin wire reset_out_pre2; altera_reset_synchronizer #( .DEPTH (SYNC_DEPTH+1), .ASYNC_RESET(0) ) alt_rst_sync_uq2 ( .clk (clk), .reset_in (reset_out_pre), .reset_out (reset_out_pre2) ); always @* begin reset_out = reset_out_pre2; reset_req = reset_req_pre; end end else begin // 3-FF Metastability Synchronizer initial begin altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}}; end always @(posedge clk) begin altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <= {altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre}; end // Synchronous reset pipe initial begin r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}}; end always @(posedge clk) begin if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1) begin r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}}; end else begin r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]}; end end // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition // matches the early input. always @(posedge clk) begin case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst}) 3'b000: r_sync_rst <= 1'b0; // Not reset 3'b001: r_sync_rst <= 1'b0; 3'b010: r_sync_rst <= 1'b0; 3'b011: r_sync_rst <= 1'b1; 3'b100: r_sync_rst <= 1'b1; 3'b101: r_sync_rst <= 1'b1; 3'b110: r_sync_rst <= 1'b1; 3'b111: r_sync_rst <= 1'b1; // In Reset default: r_sync_rst <= 1'b1; endcase case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre}) 2'b00: r_early_rst <= 1'b0; // Not reset 2'b01: r_early_rst <= 1'b1; // Coming out of reset 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. 2'b11: r_early_rst <= 1'b1; // Held in reset default: r_early_rst <= 1'b1; endcase end always @* begin reset_out = r_sync_rst; reset_req = r_early_rst; end end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ddr_mc_phy_wrapper.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Oct 10 2010 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Wrapper file that encompasses the MC_PHY module // instantiation and handles the vector remapping between // the MC_PHY ports and the user's DDR3 ports. Vector // remapping affects DDR3 control, address, and DQ/DQS/DM. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_ddr_mc_phy_wrapper # ( parameter TCQ = 100, // Register delay (simulation only) parameter tCK = 2500, // ps parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank parameter BANK_WIDTH = 3, // # of bank address parameter CKE_WIDTH = 1, // # of clock enable outputs parameter CS_WIDTH = 1, // # of chip select parameter CK_WIDTH = 1, // # of CK parameter CWL = 5, // CAS Write latency parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter DM_WIDTH = 8, // # of data mask parameter DQ_WIDTH = 16, // # of data bits parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of strobe pairs parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3) parameter RANKS = 4, // # of ranks parameter ODT_WIDTH = 1, // # of ODT outputs parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter REG_CTRL = "OFF", // "ON" for registered DIMM parameter ROW_WIDTH = 16, // # of row/column address parameter USE_CS_PORT = 1, // Support chip select output parameter USE_DM_PORT = 1, // Support data mask output parameter USE_ODT_PORT = 1, // Support ODT output parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option parameter LP_DDR_CK_WIDTH = 2, // Hard PHY parameters parameter PHYCTL_CMD_FIFO = "FALSE", parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf, parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter PHY_0_BITLANES = 48'h0000_0000_0000, parameter PHY_1_BITLANES = 48'h0000_0000_0000, parameter PHY_2_BITLANES = 48'h0000_0000_0000, // Parameters calculated outside of this block parameter HIGHEST_BANK = 3, // Highest I/O bank index parameter HIGHEST_LANE = 12, // Highest byte lane index // ** Pin mapping parameters // Parameters for mapping between hard PHY and physical DDR3 signals // There are 2 classes of parameters: // - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of // 8-bit elements. Each element indicates the bank and byte lane // location of that particular signal. The bit lane in this case // doesn't need to be specified, either because there's only one // pin pair in each byte lane that the DQS or CK pair can be // located at, or in the case of CKE_ODT_BYTE_MAP, only the byte // lane needs to be specified in order to determine which byte // lane generates the RCLK (Note that CKE, and ODT must be located // in the same bank, thus only one element in CKE_ODT_BYTE_MAP) // [7:4] = bank # (0-4) // [3:0] = byte lane # (0-3) // - All other MAP parameters: These consist of 12-bit elements. Each // element indicates the bank, byte lane, and bit lane location of // that particular signal: // [11:8] = bank # (0-4) // [7:4] = byte lane # (0-3) // [3:0] = bit lane # (0-11) // Note that not all elements in all parameters will be used - it // depends on the actual widths of the DDR3 buses. The parameters are // structured to support a maximum of: // - DQS groups: 18 // - data mask bits: 18 // In addition, the default parameter size of some of the parameters will // support a certain number of bits, however, this can be expanded at // compile time by expanding the width of the vector passed into this // parameter // - chip selects: 10 // - bank bits: 3 // - address bits: 16 parameter CK_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter ADDR_MAP = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, parameter BANK_MAP = 36'h000_000_000, parameter CAS_MAP = 12'h000, parameter CKE_ODT_BYTE_MAP = 8'h00, parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000, parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000, parameter CKE_ODT_AUX = "FALSE", parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, parameter PARITY_MAP = 12'h000, parameter RAS_MAP = 12'h000, parameter WE_MAP = 12'h000, parameter DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, // DATAx_MAP parameter is used for byte lane X in the design parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, // MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9] parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, // Simulation options parameter SIM_CAL_OPTION = "NONE", // The PHY_CONTROL primitive in the bank where PLL exists is declared // as the Master PHY_CONTROL. parameter MASTER_PHY_CTL = 1, parameter DRAM_WIDTH = 8 ) ( input rst, input iddr_rst, input clk, input freq_refclk, input mem_refclk, input pll_lock, input sync_pulse, input mmcm_ps_clk, input idelayctrl_refclk, input phy_cmd_wr_en, input phy_data_wr_en, input [31:0] phy_ctl_wd, input phy_ctl_wr, input phy_if_empty_def, input phy_if_reset, input [5:0] data_offset_1, input [5:0] data_offset_2, input [3:0] aux_in_1, input [3:0] aux_in_2, output [4:0] idelaye2_init_val, output [5:0] oclkdelay_init_val, output if_empty, output phy_ctl_full, output phy_cmd_full, output phy_data_full, output phy_pre_data_a_full, output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk, output phy_mc_go, input phy_write_calib, input phy_read_calib, input calib_in_common, input [5:0] calib_sel, input [DQS_CNT_WIDTH:0] byte_sel_cnt, input [DRAM_WIDTH-1:0] fine_delay_incdec_pb, input fine_delay_sel, input [HIGHEST_BANK-1:0] calib_zero_inputs, input [HIGHEST_BANK-1:0] calib_zero_ctrl, input [2:0] po_fine_enable, input [2:0] po_coarse_enable, input [2:0] po_fine_inc, input [2:0] po_coarse_inc, input po_counter_load_en, input po_counter_read_en, input [2:0] po_sel_fine_oclk_delay, input [8:0] po_counter_load_val, output [8:0] po_counter_read_val, output [5:0] pi_counter_read_val, input [HIGHEST_BANK-1:0] pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input [5:0] pi_counter_load_val, input idelay_ce, input idelay_inc, input idelay_ld, input idle, output pi_phase_locked, output pi_phase_locked_all, output pi_dqs_found, output pi_dqs_found_all, output pi_dqs_out_of_range, // From/to calibration logic/soft PHY input phy_init_data_sel, input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address, input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank, input [nCK_PER_CLK-1:0] mux_cas_n, input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n, input [nCK_PER_CLK-1:0] mux_ras_n, input [1:0] mux_odt, input [nCK_PER_CLK-1:0] mux_cke, input [nCK_PER_CLK-1:0] mux_we_n, input [nCK_PER_CLK-1:0] parity_in, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata, input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask, input mux_reset_n, output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Memory I/F output [ROW_WIDTH-1:0] ddr_addr, output [BANK_WIDTH-1:0] ddr_ba, output ddr_cas_n, output [CKE_WIDTH-1:0] ddr_cke, output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, output [DM_WIDTH-1:0] ddr_dm, output [ODT_WIDTH-1:0] ddr_odt, output ddr_parity, output ddr_ras_n, output ddr_we_n, output ddr_reset_n, inout [DQ_WIDTH-1:0] ddr_dq, inout [DQS_WIDTH-1:0] ddr_dqs, inout [DQS_WIDTH-1:0] ddr_dqs_n, //output iodelay_ctrl_rdy, output pd_out ,input dbg_pi_counter_read_en ,output ref_dll_lock ,input rst_phaser_ref ,output [11:0] dbg_pi_phase_locked_phy4lanes ,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes ); function [71:0] generate_bytelanes_ddr_ck; input [143:0] ck_byte_map; integer v ; begin generate_bytelanes_ddr_ck = 'b0 ; for (v = 0; v < CK_WIDTH; v = v + 1) begin if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2) generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1) generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; else generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; end end endfunction function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map; input [143:0] ck_byte_map; integer g; begin generate_ddr_ck_map = 'b0 ; for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" : (ck_byte_map[(g*8)+:4] == 4'd1) ? "B" : (ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ; generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" : (ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location end end endfunction // Enable low power mode for input buffer localparam IBUF_LOW_PWR = (IBUF_LPWR_MODE == "OFF") ? "FALSE" : ((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL"); // Ratio of data to strobe localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH; // number of data phases per internal clock localparam PHASE_PER_CLK = 2*nCK_PER_CLK; // used to determine routing to OUT_FIFO for control/address for 2:1 // vs. 4:1 memory:internal clock ratio modes localparam PHASE_DIV = 4 / nCK_PER_CLK; localparam CLK_PERIOD = tCK * nCK_PER_CLK; // Create an aggregate parameters for data mapping to reduce # of generate // statements required in remapping code. Need to account for the case // when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP // parameter will have fewer than 8 elements used localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0], DATA16_MAP[12*DQ_PER_DQS-1:0], DATA15_MAP[12*DQ_PER_DQS-1:0], DATA14_MAP[12*DQ_PER_DQS-1:0], DATA13_MAP[12*DQ_PER_DQS-1:0], DATA12_MAP[12*DQ_PER_DQS-1:0], DATA11_MAP[12*DQ_PER_DQS-1:0], DATA10_MAP[12*DQ_PER_DQS-1:0], DATA9_MAP[12*DQ_PER_DQS-1:0], DATA8_MAP[12*DQ_PER_DQS-1:0], DATA7_MAP[12*DQ_PER_DQS-1:0], DATA6_MAP[12*DQ_PER_DQS-1:0], DATA5_MAP[12*DQ_PER_DQS-1:0], DATA4_MAP[12*DQ_PER_DQS-1:0], DATA3_MAP[12*DQ_PER_DQS-1:0], DATA2_MAP[12*DQ_PER_DQS-1:0], DATA1_MAP[12*DQ_PER_DQS-1:0], DATA0_MAP[12*DQ_PER_DQS-1:0]}; // Same deal, but for data mask mapping localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP}; localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ; localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ; // Temporary parameters to determine which bank is outputting the CK/CK# // Eventually there will be support for multiple CK/CK# output //localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]); //// Temporary method to force MC_PHY to generate ODDR associated with //// CK/CK# output only for a single byte lane in the design. All banks //// that won't be generating the CK/CK# will have "UNUSED" as their //// PHY_GENERATE_DDR_CK parameter //localparam TMP_PHY_0_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); //localparam TMP_PHY_1_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); //localparam TMP_PHY_2_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); // Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx // which indicates which bit lanes in data byte lanes are // output-only bitlanes (e.g. used specifically for data mask outputs) function [143:0] calc_phy_bitlanes_outonly; input [215:0] data_mask_in; integer z; begin calc_phy_bitlanes_outonly = 'b0; // Only enable BITLANES parameters for data masks if, well, if // the data masks are actually enabled if (USE_DM_PORT == 1) for (z = 0; z < DM_WIDTH; z = z + 1) calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] + 12*data_mask_in[(12*z+4)+:2] + data_mask_in[12*z+:4]] = 1'b1; end endfunction localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP); localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0]; localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48]; localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96]; // Determine which bank and byte lane generates the RCLK used to clock // out the auxilliary (ODT, CKE) outputs localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON = (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1)))); localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON = (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL"))); localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF = (CKE_MAP[11:8] == 4'h0) ? 0 : ((CKE_MAP[11:8] == 4'h1) ? 1 : ((CKE_MAP[11:8] == 4'h2) ? 2 : ((CKE_MAP[11:8] == 4'h3) ? 3 : ((CKE_MAP[11:8] == 4'h4) ? 4 : -1)))); localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF = (CKE_MAP[7:4] == 4'h0) ? "A" : ((CKE_MAP[7:4] == 4'h1) ? "B" : ((CKE_MAP[7:4] == 4'h2) ? "C" : ((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL"))); localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ; localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ; //*************************************************************************** // OCLKDELAYED tap setting calculation: // Parameters for calculating amount of phase shifting output clock to // achieve 90 degree offset between DQS and DQ on writes //*************************************************************************** //90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz // and 1.25 for Mem_RefClk > 300 MHz localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE"; //DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400, //DIV4: MemRefClk < 200 MHz localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" : tCK > 2500 ? "DIV2": "NONE"; localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 : PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1); // Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK; // Whether OCLK_DELAY output comes inverted or not localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0); // Phaser-Out Stage3 Tap delay for 90 deg shift. // Maximum tap delay is FreqRefClk period distributed over 64 taps // localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV; localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) - (INT_DELAY + HALF_CYCLE_DELAY)) * 63 * FREQ_REF_DIV; //localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY; localparam integer PHY_0_A_PO_OCLK_DELAY_HW = (tCK > 2273) ? 34 : (tCK > 2000) ? 33 : (tCK > 1724) ? 32 : (tCK > 1515) ? 31 : (tCK > 1315) ? 30 : (tCK > 1136) ? 29 : (tCK > 1021) ? 28 : 27; // Note that simulation requires a different value than in H/W because of the // difference in the way delays are modeled localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ? ((tCK > 2500) ? 8 : (DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) : MC_OCLK_DELAY; // Initial DQ IDELAY value localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 : (tCK < 1000) ? 0 : (tCK < 1330) ? 0 : (tCK < 2300) ? 0 : (tCK < 2500) ? 2 : 0; //localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0; // Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3? localparam PHY_0_RD_CMD_OFFSET_0 = 10; localparam PHY_0_RD_CMD_OFFSET_1 = 10; localparam PHY_0_RD_CMD_OFFSET_2 = 10; localparam PHY_0_RD_CMD_OFFSET_3 = 10; // 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4; // 4:1 and 2:1 have different values localparam PHY_0_WR_DURATION_0 = 7; localparam PHY_0_WR_DURATION_1 = 7; localparam PHY_0_WR_DURATION_2 = 7; localparam PHY_0_WR_DURATION_3 = 7; // Aux_out parameters for toggle mode (CKE) localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 : (CWL < 7) ? 4 + ((CWL_M % 2) ? 0 : 1) : 5 + ((CWL_M % 2) ? 0 : 1); // temporary parameter to enable/disable PHY PC counters. In both 4:1 and // 2:1 cases, this should be disabled. For now, enable for 4:1 mode to // avoid making too many changes at once. localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE"; wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out; wire [HIGHEST_LANE-1:0] mem_dqs_in; wire [HIGHEST_LANE-1:0] mem_dqs_out; wire [HIGHEST_LANE-1:0] mem_dqs_ts; wire [HIGHEST_LANE*10-1:0] mem_dq_in; wire [HIGHEST_LANE*12-1:0] mem_dq_out; wire [HIGHEST_LANE*12-1:0] mem_dq_ts; wire [DQ_WIDTH-1:0] in_dq; wire [DQS_WIDTH-1:0] in_dqs; wire [ROW_WIDTH-1:0] out_addr; wire [BANK_WIDTH-1:0] out_ba; wire out_cas_n; wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n; wire [DM_WIDTH-1:0] out_dm; wire [ODT_WIDTH -1:0] out_odt; wire [CKE_WIDTH -1 :0] out_cke ; wire [DQ_WIDTH-1:0] out_dq; wire [DQS_WIDTH-1:0] out_dqs; wire out_parity; wire out_ras_n; wire out_we_n; wire [HIGHEST_LANE*80-1:0] phy_din; wire [HIGHEST_LANE*80-1:0] phy_dout; wire phy_rd_en; wire [DM_WIDTH-1:0] ts_dm; wire [DQ_WIDTH-1:0] ts_dq; wire [DQS_WIDTH-1:0] ts_dqs; wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr; wire [DQS_WIDTH-1:0] pd_out_pre; //wire metaQ; reg [31:0] phy_ctl_wd_i1; reg [31:0] phy_ctl_wd_i2; reg phy_ctl_wr_i1; reg phy_ctl_wr_i2; reg [5:0] data_offset_1_i1; reg [5:0] data_offset_1_i2; reg [5:0] data_offset_2_i1; reg [5:0] data_offset_2_i2; wire [31:0] phy_ctl_wd_temp; wire phy_ctl_wr_temp; wire [5:0] data_offset_1_temp; wire [5:0] data_offset_2_temp; wire [5:0] data_offset_1_of; wire [5:0] data_offset_2_of; wire [31:0] phy_ctl_wd_of; wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */; wire [3:0] phy_ctl_full_temp; wire data_io_idle_pwrdwn; reg [29:0] fine_delay_mod; //3 bit per DQ reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb (* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1; // Always read from input data FIFOs when not empty assign phy_rd_en = !if_empty; // IDELAYE2 initial value assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE; assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY; // Idle powerdown when there are no pending reads in the MC assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0; //*************************************************************************** // Auxiliary output steering //*************************************************************************** // For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be // mapped to ddr_odt and the aux_out[7:4] from one of the data banks // will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the // addr/ctl bank would bank would map to both ddr_odt and ddr_cke. generate if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins if (CKE_WIDTH == 1) begin : gen_cke // Explicitly instantiate OBUF to ensure that these are present // in the netlist. Typically this is not required since NGDBUILD // at the top-level knows to infer an I/O/IOBUF and therefore a // top-level LOC constraint can be attached to that pin. This does // not work when a hierarchical flow is used and the LOC is applied // at the individual core-level UCF OBUF u_cke_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), .O (ddr_cke) ); end else begin: gen_2rank_cke OBUF u_cke0_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), .O (ddr_cke[0]) ); OBUF u_cke1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_cke[1]) ); end end endgenerate generate if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins if (USE_ODT_PORT == 1) begin : gen_use_odt // Explicitly instantiate OBUF to ensure that these are present // in the netlist. Typically this is not required since NGDBUILD // at the top-level knows to infer an I/O/IOBUF and therefore a // top-level LOC constraint can be attached to that pin. This does // not work when a hierarchical flow is used and the LOC is applied // at the individual core-level UCF OBUF u_odt_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]), .O (ddr_odt[0]) ); if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_odt[1]) ); end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), .O (ddr_odt[1]) ); end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_odt[1]) ); OBUF u_odt2_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), .O (ddr_odt[2]) ); end end else begin assign ddr_odt = 'b0; end end endgenerate //*************************************************************************** // Read data bit steering //*************************************************************************** // Transpose elements of rd_data_map to form final read data output: // phy_din elements are grouped according to "physical bit" - e.g. // for nCK_PER_CLK = 4, there are 8 data phases transfered per physical // bit per clock cycle: // = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2, // dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0} // whereas rd_data is are grouped according to "phase" - e.g. // = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0, // dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0} // therefore rd_data is formed by transposing phy_din - e.g. // for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY // bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then // the assignments for bits of rd_data corresponding to DQ[1:0] // would be: // {rd_data[112], rd_data[96], rd_data[80], rd_data[64], // rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0] // {rd_data[113], rd_data[97], rd_data[81], rd_data[65], // rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8] generate genvar i, j; for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1 for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2 assign rd_data[DQ_WIDTH*j + i] = phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+ 80*FULL_DATA_MAP[(12*i+4)+:2] + 8*FULL_DATA_MAP[12*i+:4]) + j]; end end endgenerate //generage idelay_inc per bits reg [11:0] cal_tmp; reg [95:0] byte_sel_data_map; assign byte_sel_cnt_w1 = byte_sel_cnt; always @ (posedge clk) begin byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96]; end always @ (posedge clk) begin fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00}; fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00}; fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00}; fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00}; fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00}; fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00}; fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00}; fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00}; fine_delay_sel_r <= #TCQ fine_delay_sel; end //*************************************************************************** // Control/address //*************************************************************************** assign out_cas_n = mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]]; generate // if signal placed on bit lanes [0-9] if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10 // Determine routing based on clock ratio mode. If running in 4:1 // mode, then all four bits from logic are used. If 2:1 mode, only // 2-bits are provided by logic, and each bit is repeated 2x to form // 4-bit input to IN_FIFO, e.g. // 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]} // 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]} assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + 8*CAS_MAP[3:0])+:4] = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; end else begin: gen_cas_ge10 // If signal is placed in bit lane [10] or [11], route to upper // nibble of phy_dout lane [5] or [6] respectively (in this case // phy_dout lane [5, 6] are multiplexed to take input for two // different SDR signals - this is how bits[10,11] need to be // provided to the OUT_FIFO assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + 8*(CAS_MAP[3:0]-5) + 4)+:4] = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; end endgenerate assign out_ras_n = mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]]; generate if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10 assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + 8*RAS_MAP[3:0])+:4] = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; end else begin: gen_ras_ge10 assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + 8*(RAS_MAP[3:0]-5) + 4)+:4] = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; end endgenerate assign out_we_n = mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]]; generate if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10 assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + 8*WE_MAP[3:0])+:4] = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], mux_we_n[1/PHASE_DIV], mux_we_n[0]}; end else begin: gen_we_ge10 assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + 8*(WE_MAP[3:0]-5) + 4)+:4] = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], mux_we_n[1/PHASE_DIV], mux_we_n[0]}; end endgenerate generate if (REG_CTRL == "ON") begin: gen_parity_out // Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs assign out_parity = mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] + PARITY_MAP[3:0]]; if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10 assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + 8*PARITY_MAP[3:0])+:4] = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], parity_in[1/PHASE_DIV], parity_in[0]}; end else begin: gen_ge10 assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + 8*(PARITY_MAP[3:0]-5) + 4)+:4] = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], parity_in[1/PHASE_DIV], parity_in[0]}; end end endgenerate //***************************************************************** generate genvar m, n,x; //***************************************************************** // Control/address (multi-bit) buses //***************************************************************** // Row/Column address for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out assign out_addr[m] = mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] + 12*ADDR_MAP[(12*m+4)+:2] + ADDR_MAP[12*m+:4]]; if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10 // For multi-bit buses, we also have to deal with transposition // when going from the logic-side control bus to phy_dout for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + 80*ADDR_MAP[(12*m+4)+:2] + 8*ADDR_MAP[12*m+:4] + n] = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + 80*ADDR_MAP[(12*m+4)+:2] + 8*(ADDR_MAP[12*m+:4]-5) + 4 + n] = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; end end end // Bank address for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out assign out_ba[m] = mem_dq_out[48*BANK_MAP[(12*m+8)+:3] + 12*BANK_MAP[(12*m+4)+:2] + BANK_MAP[12*m+:4]]; if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + 80*BANK_MAP[(12*m+4)+:2] + 8*BANK_MAP[12*m+:4] + n] = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + 80*BANK_MAP[(12*m+4)+:2] + 8*(BANK_MAP[12*m+:4]-5) + 4 + n] = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; end end end // Chip select if (USE_CS_PORT == 1) begin: gen_cs_n_out for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out assign out_cs_n[m] = mem_dq_out[48*CS_MAP[(12*m+8)+:3] + 12*CS_MAP[(12*m+4)+:2] + CS_MAP[12*m+:4]]; if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CS_MAP[(12*m+8)+:3] + 80*CS_MAP[(12*m+4)+:2] + 8*CS_MAP[12*m+:4] + n] = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CS_MAP[(12*m+8)+:3] + 80*CS_MAP[(12*m+4)+:2] + 8*(CS_MAP[12*m+:4]-5) + 4 + n] = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; end end end end if(CKE_ODT_AUX == "FALSE") begin // ODT_ports wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ; if(RANKS == 1) begin for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ; end end else begin for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ; assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ; end end if (USE_ODT_PORT == 1) begin: gen_odt_out for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1 assign out_odt[m] = mem_dq_out[48*ODT_MAP[(12*m+8)+:3] + 12*ODT_MAP[(12*m+4)+:2] + ODT_MAP[12*m+:4]]; if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + 80*ODT_MAP[(12*m+4)+:2] + 8*ODT_MAP[12*m+:4] + n] = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + 80*ODT_MAP[(12*m+4)+:2] + 8*(ODT_MAP[12*m+:4]-5) + 4 + n] = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; end end end end wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ; for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ; end for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out assign out_cke[m] = mem_dq_out[48*CKE_MAP[(12*m+8)+:3] + 12*CKE_MAP[(12*m+4)+:2] + CKE_MAP[12*m+:4]]; if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + 80*CKE_MAP[(12*m+4)+:2] + 8*CKE_MAP[12*m+:4] + n] = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + 80*CKE_MAP[(12*m+4)+:2] + 8*(CKE_MAP[12*m+:4]-5) + 4 + n] = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; end end end end //***************************************************************** // Data mask //***************************************************************** if (USE_DM_PORT == 1) begin: gen_dm_out for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out assign out_dm[m] = mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] + 12*FULL_MASK_MAP[(12*m+4)+:2] + FULL_MASK_MAP[12*m+:4]]; assign ts_dm[m] = mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] + 12*FULL_MASK_MAP[(12*m+4)+:2] + FULL_MASK_MAP[12*m+:4]]; for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] + 80*FULL_MASK_MAP[(12*m+4)+:2] + 8*FULL_MASK_MAP[12*m+:4] + n] = mux_wrdata_mask[DM_WIDTH*n + m]; end end end //***************************************************************** // Input and output DQ //***************************************************************** for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout // to MC_PHY assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] + 10*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]] = in_dq[m]; // to I/O buffers assign out_dq[m] = mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] + 12*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]]; assign ts_dq[m] = mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] + 12*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]]; for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] + 80*FULL_DATA_MAP[(12*m+4)+:2] + 8*FULL_DATA_MAP[12*m+:4] + n] = mux_wrdata[DQ_WIDTH*n + m]; end end //***************************************************************** // Input and output DQS //***************************************************************** for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout // to MC_PHY assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]] = in_dqs[m]; // to I/O buffers assign out_dqs[m] = mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; assign ts_dqs[m] = mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; end endgenerate assign pd_out = pd_out_pre[byte_sel_cnt_w1]; //*************************************************************************** // Memory I/F output and I/O buffer instantiation //*************************************************************************** // Note on instantiation - generally at the minimum, it's not required to // instantiate the output buffers - they can be inferred by the synthesis // tool, and there aren't any attributes that need to be associated with // them. Consider as a future option to take out the OBUF instantiations OBUF u_cas_n_obuf ( .I (out_cas_n), .O (ddr_cas_n) ); OBUF u_ras_n_obuf ( .I (out_ras_n), .O (ddr_ras_n) ); OBUF u_we_n_obuf ( .I (out_we_n), .O (ddr_we_n) ); generate genvar p; for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf OBUF u_addr_obuf ( .I (out_addr[p]), .O (ddr_addr[p]) ); end for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf OBUF u_bank_obuf ( .I (out_ba[p]), .O (ddr_ba[p]) ); end if (USE_CS_PORT == 1) begin: gen_cs_n_obuf for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf OBUF u_cs_n_obuf ( .I (out_cs_n[p]), .O (ddr_cs_n[p]) ); end end if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo if (USE_ODT_PORT== 1) begin: gen_odt_obuf for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf OBUF u_cs_n_obuf ( .I (out_odt[p]), .O (ddr_odt[p]) ); end end for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf OBUF u_cs_n_obuf ( .I (out_cke[p]), .O (ddr_cke[p]) ); end end if (REG_CTRL == "ON") begin: gen_parity_obuf // Generate addr/ctrl parity output only for DDR3 registered DIMMs OBUF u_parity_obuf ( .I (out_parity), .O (ddr_parity) ); end else begin: gen_parity_tieoff assign ddr_parity = 1'b0; end if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf // Generate reset output only for DDR3 and DDR2 RDIMMs OBUF u_reset_obuf ( .I (mux_reset_n), .O (ddr_reset_n) ); end else begin: gen_reset_tieoff assign ddr_reset_n = 1'b1; end if (USE_DM_PORT == 1) begin: gen_dm_obuf for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm OBUFT u_dm_obuf ( .I (out_dm[p]), .T (ts_dm[p]), .O (ddr_dm[p]) ); end end else begin: gen_dm_tieoff assign ddr_dm = 'b0; end if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end else begin: gen_dq_iobuf_default for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end //if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else if ((DRAM_TYPE == "DDR2") || (tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff IOBUFDS_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS_DIFF_OUT_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE"), .SIM_DEVICE ("7SERIES"), .USE_IBUFDISABLE ("FALSE") ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .TM (ts_dqs[p]), .TS (ts_dqs[p]), .OB (in_dqs_lpbk_to_iddr[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); mig_7series_v2_3_poc_pd # ( .TCQ (TCQ), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) ) u_iddr_edge_det ( .clk (clk), .iddr_rst (iddr_rst), .kclk (in_dqs_lpbk_to_iddr[p]), .mmcm_ps_clk (mmcm_ps_clk), .pd_out (pd_out_pre[p]) ); end end //end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else if ((DRAM_TYPE == "DDR2") || (tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff IOBUFDS_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS_DIFF_OUT_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE"), .SIM_DEVICE ("7SERIES"), .USE_IBUFDISABLE ("FALSE") ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), //.IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .TM (ts_dqs[p]), .TS (ts_dqs[p]), .OB (in_dqs_lpbk_to_iddr[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); mig_7series_v2_3_poc_pd # ( .TCQ (TCQ), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) ) u_iddr_edge_det ( .clk (clk), .iddr_rst (iddr_rst), .kclk (in_dqs_lpbk_to_iddr[p]), .mmcm_ps_clk (mmcm_ps_clk), .pd_out (pd_out_pre[p]) ); end end end else begin: gen_dqs_iobuf_default for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end end end endgenerate always @(posedge clk) begin phy_ctl_wd_i1 <= #TCQ phy_ctl_wd; phy_ctl_wr_i1 <= #TCQ phy_ctl_wr; phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1; phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1; data_offset_1_i1 <= #TCQ data_offset_1; data_offset_1_i2 <= #TCQ data_offset_1_i1; data_offset_2_i1 <= #TCQ data_offset_2; data_offset_2_i2 <= #TCQ data_offset_2_i1; end // 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it. // 2:1 mode the command goes through pre fifo assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of; assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of; assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of; assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of; generate begin mig_7series_v2_3_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (32) ) phy_ctl_pre_fifo_0 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[1]), .wr_en_in (phy_ctl_wr), .d_in (phy_ctl_wd), .wr_en_out (phy_ctl_wr_of), .d_out (phy_ctl_wd_of) ); mig_7series_v2_3_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (6) ) phy_ctl_pre_fifo_1 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[2]), .wr_en_in (phy_ctl_wr), .d_in (data_offset_1), .wr_en_out (), .d_out (data_offset_1_of) ); mig_7series_v2_3_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (6) ) phy_ctl_pre_fifo_2 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[3]), .wr_en_in (phy_ctl_wr), .d_in (data_offset_2), .wr_en_out (), .d_out (data_offset_2_of) ); end endgenerate //*************************************************************************** // Hard PHY instantiation //*************************************************************************** assign phy_ctl_full = phy_ctl_full_temp[0]; mig_7series_v2_3_ddr_mc_phy # ( .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .PHY_0_BITLANES (PHY_0_BITLANES), .PHY_1_BITLANES (PHY_1_BITLANES), .PHY_2_BITLANES (PHY_2_BITLANES), .PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY), .PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY), .PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY), .RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK), .RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE), //.CKE_ODT_AUX (CKE_ODT_AUX), .GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP), .BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK), .NUM_DDR_CK (CK_WIDTH), .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH), .PO_CTL_COARSE_BYPASS ("FALSE"), .PHYCTL_CMD_FIFO ("FALSE"), .PHY_CLK_RATIO (nCK_PER_CLK), .MASTER_PHY_CTL (MASTER_PHY_CTL), .PHY_FOUR_WINDOW_CLOCKS (63), .PHY_EVENTS_DELAY (18), .PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN .PHY_SYNC_MODE ("FALSE"), .SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"), .PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE" .PHY_0_GENERATE_IDELAYCTRL ("FALSE"), .PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV), .PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE .PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0), .PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1), .PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2), .PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3), .PHY_0_RD_DURATION_0 (6), .PHY_0_RD_DURATION_1 (6), .PHY_0_RD_DURATION_2 (6), .PHY_0_RD_DURATION_3 (6), .PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0), .PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1), .PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2), .PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3), .PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0), .PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1), .PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2), .PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3), .PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5), .PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV), .PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_GENERATE_IDELAYCTRL ("FALSE"), //.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK), //.PHY_1_NUM_DDR_CK (1), .PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_GENERATE_IDELAYCTRL ("FALSE"), //.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK), //.PHY_2_NUM_DDR_CK (1), .PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .TCK (tCK), .PHY_0_IODELAY_GRP (IODELAY_GRP), .PHY_1_IODELAY_GRP (IODELAY_GRP), .PHY_2_IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .CKE_ODT_AUX (CKE_ODT_AUX) ) u_ddr_mc_phy ( .rst (rst), // Don't use MC_PHY to generate DDR_RESET_N output. Instead // generate this output outside of MC_PHY (and synchronous to CLK) .ddr_rst_in_n (1'b1), .phy_clk (clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), // Remove later - always same connection as phy_clk port .mem_refclk_div4 (clk), .pll_lock (pll_lock), .auxout_clk (), .sync_pulse (sync_pulse), // IDELAYCTRL instantiated outside of mc_phy module .idelayctrl_refclk (), .phy_dout (phy_dout), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phy_ctl_wd (phy_ctl_wd_temp), .phy_ctl_wr (phy_ctl_wr_temp), .if_empty_def (phy_if_empty_def), .if_rst (phy_if_reset), .phyGo ('b1), .aux_in_1 (aux_in_1), .aux_in_2 (aux_in_2), // No support yet for different data offsets for different I/O banks // (possible use in supporting wider range of skew among bytes) .data_offset_1 (data_offset_1_temp), .data_offset_2 (data_offset_2_temp), .cke_in (), .if_a_empty (), .if_empty (if_empty), .if_empty_or (), .if_empty_and (), .of_ctl_a_full (), // .of_data_a_full (phy_data_full), .of_ctl_full (phy_cmd_full), .of_data_full (), .pre_data_a_full (phy_pre_data_a_full), .idelay_ld (idelay_ld), .idelay_ce (idelay_ce), .idelay_inc (idelay_inc), .input_sink (), .phy_din (phy_din), .phy_ctl_a_full (), .phy_ctl_full (phy_ctl_full_temp), .mem_dq_out (mem_dq_out), .mem_dq_ts (mem_dq_ts), .mem_dq_in (mem_dq_in), .mem_dqs_out (mem_dqs_out), .mem_dqs_ts (mem_dqs_ts), .mem_dqs_in (mem_dqs_in), .aux_out (aux_out), .phy_ctl_ready (), .rst_out (), .ddr_clk (ddr_clk), //.rclk (), .mcGo (phy_mc_go), .phy_write_calib (phy_write_calib), .phy_read_calib (phy_read_calib), .calib_sel (calib_sel), .calib_in_common (calib_in_common), .calib_zero_inputs (calib_zero_inputs), .calib_zero_ctrl (calib_zero_ctrl), .calib_zero_lanes ('b0), .po_fine_enable (po_fine_enable), .po_coarse_enable (po_coarse_enable), .po_fine_inc (po_fine_inc), .po_coarse_inc (po_coarse_inc), .po_counter_load_en (po_counter_load_en), .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay), .po_counter_load_val (po_counter_load_val), .po_counter_read_en (po_counter_read_en), .po_coarse_overflow (), .po_fine_overflow (), .po_counter_read_val (po_counter_read_val), .pi_rst_dqs_find (pi_rst_dqs_find), .pi_fine_enable (pi_fine_enable), .pi_fine_inc (pi_fine_inc), .pi_counter_load_en (pi_counter_load_en), .pi_counter_read_en (dbg_pi_counter_read_en), .pi_counter_load_val (pi_counter_load_val), .pi_fine_overflow (), .pi_counter_read_val (pi_counter_read_val), .pi_phase_locked (pi_phase_locked), .pi_phase_locked_all (pi_phase_locked_all), .pi_dqs_found (), .pi_dqs_found_any (pi_dqs_found), .pi_dqs_found_all (pi_dqs_found_all), .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes), // Currently not being used. May be used in future if periodic // reads become a requirement. This output could be used to signal // a catastrophic failure in read capture and the need for // re-calibration. .pi_dqs_out_of_range (pi_dqs_out_of_range) ,.ref_dll_lock (ref_dll_lock) ,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes) ,.fine_delay (fine_delay_mod) ,.fine_delay_sel (fine_delay_sel_r) // ,.rst_phaser_ref (rst_phaser_ref) ); endmodule

//***************************************************************************** // (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ddr_mc_phy_wrapper.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Oct 10 2010 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Wrapper file that encompasses the MC_PHY module // instantiation and handles the vector remapping between // the MC_PHY ports and the user's DDR3 ports. Vector // remapping affects DDR3 control, address, and DQ/DQS/DM. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_ddr_mc_phy_wrapper # ( parameter TCQ = 100, // Register delay (simulation only) parameter tCK = 2500, // ps parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank parameter BANK_WIDTH = 3, // # of bank address parameter CKE_WIDTH = 1, // # of clock enable outputs parameter CS_WIDTH = 1, // # of chip select parameter CK_WIDTH = 1, // # of CK parameter CWL = 5, // CAS Write latency parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter DM_WIDTH = 8, // # of data mask parameter DQ_WIDTH = 16, // # of data bits parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of strobe pairs parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3) parameter RANKS = 4, // # of ranks parameter ODT_WIDTH = 1, // # of ODT outputs parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter REG_CTRL = "OFF", // "ON" for registered DIMM parameter ROW_WIDTH = 16, // # of row/column address parameter USE_CS_PORT = 1, // Support chip select output parameter USE_DM_PORT = 1, // Support data mask output parameter USE_ODT_PORT = 1, // Support ODT output parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option parameter LP_DDR_CK_WIDTH = 2, // Hard PHY parameters parameter PHYCTL_CMD_FIFO = "FALSE", parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf, parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter PHY_0_BITLANES = 48'h0000_0000_0000, parameter PHY_1_BITLANES = 48'h0000_0000_0000, parameter PHY_2_BITLANES = 48'h0000_0000_0000, // Parameters calculated outside of this block parameter HIGHEST_BANK = 3, // Highest I/O bank index parameter HIGHEST_LANE = 12, // Highest byte lane index // ** Pin mapping parameters // Parameters for mapping between hard PHY and physical DDR3 signals // There are 2 classes of parameters: // - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of // 8-bit elements. Each element indicates the bank and byte lane // location of that particular signal. The bit lane in this case // doesn't need to be specified, either because there's only one // pin pair in each byte lane that the DQS or CK pair can be // located at, or in the case of CKE_ODT_BYTE_MAP, only the byte // lane needs to be specified in order to determine which byte // lane generates the RCLK (Note that CKE, and ODT must be located // in the same bank, thus only one element in CKE_ODT_BYTE_MAP) // [7:4] = bank # (0-4) // [3:0] = byte lane # (0-3) // - All other MAP parameters: These consist of 12-bit elements. Each // element indicates the bank, byte lane, and bit lane location of // that particular signal: // [11:8] = bank # (0-4) // [7:4] = byte lane # (0-3) // [3:0] = bit lane # (0-11) // Note that not all elements in all parameters will be used - it // depends on the actual widths of the DDR3 buses. The parameters are // structured to support a maximum of: // - DQS groups: 18 // - data mask bits: 18 // In addition, the default parameter size of some of the parameters will // support a certain number of bits, however, this can be expanded at // compile time by expanding the width of the vector passed into this // parameter // - chip selects: 10 // - bank bits: 3 // - address bits: 16 parameter CK_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter ADDR_MAP = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, parameter BANK_MAP = 36'h000_000_000, parameter CAS_MAP = 12'h000, parameter CKE_ODT_BYTE_MAP = 8'h00, parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000, parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000, parameter CKE_ODT_AUX = "FALSE", parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, parameter PARITY_MAP = 12'h000, parameter RAS_MAP = 12'h000, parameter WE_MAP = 12'h000, parameter DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, // DATAx_MAP parameter is used for byte lane X in the design parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, // MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9] parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, // Simulation options parameter SIM_CAL_OPTION = "NONE", // The PHY_CONTROL primitive in the bank where PLL exists is declared // as the Master PHY_CONTROL. parameter MASTER_PHY_CTL = 1, parameter DRAM_WIDTH = 8 ) ( input rst, input iddr_rst, input clk, input freq_refclk, input mem_refclk, input pll_lock, input sync_pulse, input mmcm_ps_clk, input idelayctrl_refclk, input phy_cmd_wr_en, input phy_data_wr_en, input [31:0] phy_ctl_wd, input phy_ctl_wr, input phy_if_empty_def, input phy_if_reset, input [5:0] data_offset_1, input [5:0] data_offset_2, input [3:0] aux_in_1, input [3:0] aux_in_2, output [4:0] idelaye2_init_val, output [5:0] oclkdelay_init_val, output if_empty, output phy_ctl_full, output phy_cmd_full, output phy_data_full, output phy_pre_data_a_full, output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk, output phy_mc_go, input phy_write_calib, input phy_read_calib, input calib_in_common, input [5:0] calib_sel, input [DQS_CNT_WIDTH:0] byte_sel_cnt, input [DRAM_WIDTH-1:0] fine_delay_incdec_pb, input fine_delay_sel, input [HIGHEST_BANK-1:0] calib_zero_inputs, input [HIGHEST_BANK-1:0] calib_zero_ctrl, input [2:0] po_fine_enable, input [2:0] po_coarse_enable, input [2:0] po_fine_inc, input [2:0] po_coarse_inc, input po_counter_load_en, input po_counter_read_en, input [2:0] po_sel_fine_oclk_delay, input [8:0] po_counter_load_val, output [8:0] po_counter_read_val, output [5:0] pi_counter_read_val, input [HIGHEST_BANK-1:0] pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input [5:0] pi_counter_load_val, input idelay_ce, input idelay_inc, input idelay_ld, input idle, output pi_phase_locked, output pi_phase_locked_all, output pi_dqs_found, output pi_dqs_found_all, output pi_dqs_out_of_range, // From/to calibration logic/soft PHY input phy_init_data_sel, input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address, input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank, input [nCK_PER_CLK-1:0] mux_cas_n, input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n, input [nCK_PER_CLK-1:0] mux_ras_n, input [1:0] mux_odt, input [nCK_PER_CLK-1:0] mux_cke, input [nCK_PER_CLK-1:0] mux_we_n, input [nCK_PER_CLK-1:0] parity_in, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata, input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask, input mux_reset_n, output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Memory I/F output [ROW_WIDTH-1:0] ddr_addr, output [BANK_WIDTH-1:0] ddr_ba, output ddr_cas_n, output [CKE_WIDTH-1:0] ddr_cke, output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, output [DM_WIDTH-1:0] ddr_dm, output [ODT_WIDTH-1:0] ddr_odt, output ddr_parity, output ddr_ras_n, output ddr_we_n, output ddr_reset_n, inout [DQ_WIDTH-1:0] ddr_dq, inout [DQS_WIDTH-1:0] ddr_dqs, inout [DQS_WIDTH-1:0] ddr_dqs_n, //output iodelay_ctrl_rdy, output pd_out ,input dbg_pi_counter_read_en ,output ref_dll_lock ,input rst_phaser_ref ,output [11:0] dbg_pi_phase_locked_phy4lanes ,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes ); function [71:0] generate_bytelanes_ddr_ck; input [143:0] ck_byte_map; integer v ; begin generate_bytelanes_ddr_ck = 'b0 ; for (v = 0; v < CK_WIDTH; v = v + 1) begin if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2) generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1) generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; else generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; end end endfunction function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map; input [143:0] ck_byte_map; integer g; begin generate_ddr_ck_map = 'b0 ; for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" : (ck_byte_map[(g*8)+:4] == 4'd1) ? "B" : (ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ; generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" : (ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location end end endfunction // Enable low power mode for input buffer localparam IBUF_LOW_PWR = (IBUF_LPWR_MODE == "OFF") ? "FALSE" : ((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL"); // Ratio of data to strobe localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH; // number of data phases per internal clock localparam PHASE_PER_CLK = 2*nCK_PER_CLK; // used to determine routing to OUT_FIFO for control/address for 2:1 // vs. 4:1 memory:internal clock ratio modes localparam PHASE_DIV = 4 / nCK_PER_CLK; localparam CLK_PERIOD = tCK * nCK_PER_CLK; // Create an aggregate parameters for data mapping to reduce # of generate // statements required in remapping code. Need to account for the case // when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP // parameter will have fewer than 8 elements used localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0], DATA16_MAP[12*DQ_PER_DQS-1:0], DATA15_MAP[12*DQ_PER_DQS-1:0], DATA14_MAP[12*DQ_PER_DQS-1:0], DATA13_MAP[12*DQ_PER_DQS-1:0], DATA12_MAP[12*DQ_PER_DQS-1:0], DATA11_MAP[12*DQ_PER_DQS-1:0], DATA10_MAP[12*DQ_PER_DQS-1:0], DATA9_MAP[12*DQ_PER_DQS-1:0], DATA8_MAP[12*DQ_PER_DQS-1:0], DATA7_MAP[12*DQ_PER_DQS-1:0], DATA6_MAP[12*DQ_PER_DQS-1:0], DATA5_MAP[12*DQ_PER_DQS-1:0], DATA4_MAP[12*DQ_PER_DQS-1:0], DATA3_MAP[12*DQ_PER_DQS-1:0], DATA2_MAP[12*DQ_PER_DQS-1:0], DATA1_MAP[12*DQ_PER_DQS-1:0], DATA0_MAP[12*DQ_PER_DQS-1:0]}; // Same deal, but for data mask mapping localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP}; localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ; localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ; // Temporary parameters to determine which bank is outputting the CK/CK# // Eventually there will be support for multiple CK/CK# output //localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]); //// Temporary method to force MC_PHY to generate ODDR associated with //// CK/CK# output only for a single byte lane in the design. All banks //// that won't be generating the CK/CK# will have "UNUSED" as their //// PHY_GENERATE_DDR_CK parameter //localparam TMP_PHY_0_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); //localparam TMP_PHY_1_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); //localparam TMP_PHY_2_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); // Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx // which indicates which bit lanes in data byte lanes are // output-only bitlanes (e.g. used specifically for data mask outputs) function [143:0] calc_phy_bitlanes_outonly; input [215:0] data_mask_in; integer z; begin calc_phy_bitlanes_outonly = 'b0; // Only enable BITLANES parameters for data masks if, well, if // the data masks are actually enabled if (USE_DM_PORT == 1) for (z = 0; z < DM_WIDTH; z = z + 1) calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] + 12*data_mask_in[(12*z+4)+:2] + data_mask_in[12*z+:4]] = 1'b1; end endfunction localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP); localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0]; localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48]; localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96]; // Determine which bank and byte lane generates the RCLK used to clock // out the auxilliary (ODT, CKE) outputs localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON = (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1)))); localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON = (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL"))); localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF = (CKE_MAP[11:8] == 4'h0) ? 0 : ((CKE_MAP[11:8] == 4'h1) ? 1 : ((CKE_MAP[11:8] == 4'h2) ? 2 : ((CKE_MAP[11:8] == 4'h3) ? 3 : ((CKE_MAP[11:8] == 4'h4) ? 4 : -1)))); localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF = (CKE_MAP[7:4] == 4'h0) ? "A" : ((CKE_MAP[7:4] == 4'h1) ? "B" : ((CKE_MAP[7:4] == 4'h2) ? "C" : ((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL"))); localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ; localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ; //*************************************************************************** // OCLKDELAYED tap setting calculation: // Parameters for calculating amount of phase shifting output clock to // achieve 90 degree offset between DQS and DQ on writes //*************************************************************************** //90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz // and 1.25 for Mem_RefClk > 300 MHz localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE"; //DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400, //DIV4: MemRefClk < 200 MHz localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" : tCK > 2500 ? "DIV2": "NONE"; localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 : PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1); // Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK; // Whether OCLK_DELAY output comes inverted or not localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0); // Phaser-Out Stage3 Tap delay for 90 deg shift. // Maximum tap delay is FreqRefClk period distributed over 64 taps // localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV; localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) - (INT_DELAY + HALF_CYCLE_DELAY)) * 63 * FREQ_REF_DIV; //localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY; localparam integer PHY_0_A_PO_OCLK_DELAY_HW = (tCK > 2273) ? 34 : (tCK > 2000) ? 33 : (tCK > 1724) ? 32 : (tCK > 1515) ? 31 : (tCK > 1315) ? 30 : (tCK > 1136) ? 29 : (tCK > 1021) ? 28 : 27; // Note that simulation requires a different value than in H/W because of the // difference in the way delays are modeled localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ? ((tCK > 2500) ? 8 : (DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) : MC_OCLK_DELAY; // Initial DQ IDELAY value localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 : (tCK < 1000) ? 0 : (tCK < 1330) ? 0 : (tCK < 2300) ? 0 : (tCK < 2500) ? 2 : 0; //localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0; // Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3? localparam PHY_0_RD_CMD_OFFSET_0 = 10; localparam PHY_0_RD_CMD_OFFSET_1 = 10; localparam PHY_0_RD_CMD_OFFSET_2 = 10; localparam PHY_0_RD_CMD_OFFSET_3 = 10; // 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4; // 4:1 and 2:1 have different values localparam PHY_0_WR_DURATION_0 = 7; localparam PHY_0_WR_DURATION_1 = 7; localparam PHY_0_WR_DURATION_2 = 7; localparam PHY_0_WR_DURATION_3 = 7; // Aux_out parameters for toggle mode (CKE) localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 : (CWL < 7) ? 4 + ((CWL_M % 2) ? 0 : 1) : 5 + ((CWL_M % 2) ? 0 : 1); // temporary parameter to enable/disable PHY PC counters. In both 4:1 and // 2:1 cases, this should be disabled. For now, enable for 4:1 mode to // avoid making too many changes at once. localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE"; wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out; wire [HIGHEST_LANE-1:0] mem_dqs_in; wire [HIGHEST_LANE-1:0] mem_dqs_out; wire [HIGHEST_LANE-1:0] mem_dqs_ts; wire [HIGHEST_LANE*10-1:0] mem_dq_in; wire [HIGHEST_LANE*12-1:0] mem_dq_out; wire [HIGHEST_LANE*12-1:0] mem_dq_ts; wire [DQ_WIDTH-1:0] in_dq; wire [DQS_WIDTH-1:0] in_dqs; wire [ROW_WIDTH-1:0] out_addr; wire [BANK_WIDTH-1:0] out_ba; wire out_cas_n; wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n; wire [DM_WIDTH-1:0] out_dm; wire [ODT_WIDTH -1:0] out_odt; wire [CKE_WIDTH -1 :0] out_cke ; wire [DQ_WIDTH-1:0] out_dq; wire [DQS_WIDTH-1:0] out_dqs; wire out_parity; wire out_ras_n; wire out_we_n; wire [HIGHEST_LANE*80-1:0] phy_din; wire [HIGHEST_LANE*80-1:0] phy_dout; wire phy_rd_en; wire [DM_WIDTH-1:0] ts_dm; wire [DQ_WIDTH-1:0] ts_dq; wire [DQS_WIDTH-1:0] ts_dqs; wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr; wire [DQS_WIDTH-1:0] pd_out_pre; //wire metaQ; reg [31:0] phy_ctl_wd_i1; reg [31:0] phy_ctl_wd_i2; reg phy_ctl_wr_i1; reg phy_ctl_wr_i2; reg [5:0] data_offset_1_i1; reg [5:0] data_offset_1_i2; reg [5:0] data_offset_2_i1; reg [5:0] data_offset_2_i2; wire [31:0] phy_ctl_wd_temp; wire phy_ctl_wr_temp; wire [5:0] data_offset_1_temp; wire [5:0] data_offset_2_temp; wire [5:0] data_offset_1_of; wire [5:0] data_offset_2_of; wire [31:0] phy_ctl_wd_of; wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */; wire [3:0] phy_ctl_full_temp; wire data_io_idle_pwrdwn; reg [29:0] fine_delay_mod; //3 bit per DQ reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb (* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1; // Always read from input data FIFOs when not empty assign phy_rd_en = !if_empty; // IDELAYE2 initial value assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE; assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY; // Idle powerdown when there are no pending reads in the MC assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0; //*************************************************************************** // Auxiliary output steering //*************************************************************************** // For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be // mapped to ddr_odt and the aux_out[7:4] from one of the data banks // will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the // addr/ctl bank would bank would map to both ddr_odt and ddr_cke. generate if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins if (CKE_WIDTH == 1) begin : gen_cke // Explicitly instantiate OBUF to ensure that these are present // in the netlist. Typically this is not required since NGDBUILD // at the top-level knows to infer an I/O/IOBUF and therefore a // top-level LOC constraint can be attached to that pin. This does // not work when a hierarchical flow is used and the LOC is applied // at the individual core-level UCF OBUF u_cke_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), .O (ddr_cke) ); end else begin: gen_2rank_cke OBUF u_cke0_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), .O (ddr_cke[0]) ); OBUF u_cke1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_cke[1]) ); end end endgenerate generate if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins if (USE_ODT_PORT == 1) begin : gen_use_odt // Explicitly instantiate OBUF to ensure that these are present // in the netlist. Typically this is not required since NGDBUILD // at the top-level knows to infer an I/O/IOBUF and therefore a // top-level LOC constraint can be attached to that pin. This does // not work when a hierarchical flow is used and the LOC is applied // at the individual core-level UCF OBUF u_odt_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]), .O (ddr_odt[0]) ); if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_odt[1]) ); end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), .O (ddr_odt[1]) ); end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_odt[1]) ); OBUF u_odt2_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), .O (ddr_odt[2]) ); end end else begin assign ddr_odt = 'b0; end end endgenerate //*************************************************************************** // Read data bit steering //*************************************************************************** // Transpose elements of rd_data_map to form final read data output: // phy_din elements are grouped according to "physical bit" - e.g. // for nCK_PER_CLK = 4, there are 8 data phases transfered per physical // bit per clock cycle: // = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2, // dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0} // whereas rd_data is are grouped according to "phase" - e.g. // = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0, // dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0} // therefore rd_data is formed by transposing phy_din - e.g. // for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY // bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then // the assignments for bits of rd_data corresponding to DQ[1:0] // would be: // {rd_data[112], rd_data[96], rd_data[80], rd_data[64], // rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0] // {rd_data[113], rd_data[97], rd_data[81], rd_data[65], // rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8] generate genvar i, j; for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1 for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2 assign rd_data[DQ_WIDTH*j + i] = phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+ 80*FULL_DATA_MAP[(12*i+4)+:2] + 8*FULL_DATA_MAP[12*i+:4]) + j]; end end endgenerate //generage idelay_inc per bits reg [11:0] cal_tmp; reg [95:0] byte_sel_data_map; assign byte_sel_cnt_w1 = byte_sel_cnt; always @ (posedge clk) begin byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96]; end always @ (posedge clk) begin fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00}; fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00}; fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00}; fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00}; fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00}; fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00}; fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00}; fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00}; fine_delay_sel_r <= #TCQ fine_delay_sel; end //*************************************************************************** // Control/address //*************************************************************************** assign out_cas_n = mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]]; generate // if signal placed on bit lanes [0-9] if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10 // Determine routing based on clock ratio mode. If running in 4:1 // mode, then all four bits from logic are used. If 2:1 mode, only // 2-bits are provided by logic, and each bit is repeated 2x to form // 4-bit input to IN_FIFO, e.g. // 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]} // 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]} assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + 8*CAS_MAP[3:0])+:4] = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; end else begin: gen_cas_ge10 // If signal is placed in bit lane [10] or [11], route to upper // nibble of phy_dout lane [5] or [6] respectively (in this case // phy_dout lane [5, 6] are multiplexed to take input for two // different SDR signals - this is how bits[10,11] need to be // provided to the OUT_FIFO assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + 8*(CAS_MAP[3:0]-5) + 4)+:4] = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; end endgenerate assign out_ras_n = mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]]; generate if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10 assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + 8*RAS_MAP[3:0])+:4] = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; end else begin: gen_ras_ge10 assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + 8*(RAS_MAP[3:0]-5) + 4)+:4] = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; end endgenerate assign out_we_n = mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]]; generate if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10 assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + 8*WE_MAP[3:0])+:4] = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], mux_we_n[1/PHASE_DIV], mux_we_n[0]}; end else begin: gen_we_ge10 assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + 8*(WE_MAP[3:0]-5) + 4)+:4] = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], mux_we_n[1/PHASE_DIV], mux_we_n[0]}; end endgenerate generate if (REG_CTRL == "ON") begin: gen_parity_out // Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs assign out_parity = mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] + PARITY_MAP[3:0]]; if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10 assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + 8*PARITY_MAP[3:0])+:4] = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], parity_in[1/PHASE_DIV], parity_in[0]}; end else begin: gen_ge10 assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + 8*(PARITY_MAP[3:0]-5) + 4)+:4] = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], parity_in[1/PHASE_DIV], parity_in[0]}; end end endgenerate //***************************************************************** generate genvar m, n,x; //***************************************************************** // Control/address (multi-bit) buses //***************************************************************** // Row/Column address for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out assign out_addr[m] = mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] + 12*ADDR_MAP[(12*m+4)+:2] + ADDR_MAP[12*m+:4]]; if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10 // For multi-bit buses, we also have to deal with transposition // when going from the logic-side control bus to phy_dout for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + 80*ADDR_MAP[(12*m+4)+:2] + 8*ADDR_MAP[12*m+:4] + n] = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + 80*ADDR_MAP[(12*m+4)+:2] + 8*(ADDR_MAP[12*m+:4]-5) + 4 + n] = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; end end end // Bank address for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out assign out_ba[m] = mem_dq_out[48*BANK_MAP[(12*m+8)+:3] + 12*BANK_MAP[(12*m+4)+:2] + BANK_MAP[12*m+:4]]; if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + 80*BANK_MAP[(12*m+4)+:2] + 8*BANK_MAP[12*m+:4] + n] = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + 80*BANK_MAP[(12*m+4)+:2] + 8*(BANK_MAP[12*m+:4]-5) + 4 + n] = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; end end end // Chip select if (USE_CS_PORT == 1) begin: gen_cs_n_out for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out assign out_cs_n[m] = mem_dq_out[48*CS_MAP[(12*m+8)+:3] + 12*CS_MAP[(12*m+4)+:2] + CS_MAP[12*m+:4]]; if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CS_MAP[(12*m+8)+:3] + 80*CS_MAP[(12*m+4)+:2] + 8*CS_MAP[12*m+:4] + n] = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CS_MAP[(12*m+8)+:3] + 80*CS_MAP[(12*m+4)+:2] + 8*(CS_MAP[12*m+:4]-5) + 4 + n] = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; end end end end if(CKE_ODT_AUX == "FALSE") begin // ODT_ports wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ; if(RANKS == 1) begin for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ; end end else begin for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ; assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ; end end if (USE_ODT_PORT == 1) begin: gen_odt_out for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1 assign out_odt[m] = mem_dq_out[48*ODT_MAP[(12*m+8)+:3] + 12*ODT_MAP[(12*m+4)+:2] + ODT_MAP[12*m+:4]]; if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + 80*ODT_MAP[(12*m+4)+:2] + 8*ODT_MAP[12*m+:4] + n] = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + 80*ODT_MAP[(12*m+4)+:2] + 8*(ODT_MAP[12*m+:4]-5) + 4 + n] = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; end end end end wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ; for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ; end for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out assign out_cke[m] = mem_dq_out[48*CKE_MAP[(12*m+8)+:3] + 12*CKE_MAP[(12*m+4)+:2] + CKE_MAP[12*m+:4]]; if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + 80*CKE_MAP[(12*m+4)+:2] + 8*CKE_MAP[12*m+:4] + n] = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + 80*CKE_MAP[(12*m+4)+:2] + 8*(CKE_MAP[12*m+:4]-5) + 4 + n] = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; end end end end //***************************************************************** // Data mask //***************************************************************** if (USE_DM_PORT == 1) begin: gen_dm_out for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out assign out_dm[m] = mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] + 12*FULL_MASK_MAP[(12*m+4)+:2] + FULL_MASK_MAP[12*m+:4]]; assign ts_dm[m] = mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] + 12*FULL_MASK_MAP[(12*m+4)+:2] + FULL_MASK_MAP[12*m+:4]]; for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] + 80*FULL_MASK_MAP[(12*m+4)+:2] + 8*FULL_MASK_MAP[12*m+:4] + n] = mux_wrdata_mask[DM_WIDTH*n + m]; end end end //***************************************************************** // Input and output DQ //***************************************************************** for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout // to MC_PHY assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] + 10*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]] = in_dq[m]; // to I/O buffers assign out_dq[m] = mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] + 12*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]]; assign ts_dq[m] = mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] + 12*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]]; for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] + 80*FULL_DATA_MAP[(12*m+4)+:2] + 8*FULL_DATA_MAP[12*m+:4] + n] = mux_wrdata[DQ_WIDTH*n + m]; end end //***************************************************************** // Input and output DQS //***************************************************************** for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout // to MC_PHY assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]] = in_dqs[m]; // to I/O buffers assign out_dqs[m] = mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; assign ts_dqs[m] = mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; end endgenerate assign pd_out = pd_out_pre[byte_sel_cnt_w1]; //*************************************************************************** // Memory I/F output and I/O buffer instantiation //*************************************************************************** // Note on instantiation - generally at the minimum, it's not required to // instantiate the output buffers - they can be inferred by the synthesis // tool, and there aren't any attributes that need to be associated with // them. Consider as a future option to take out the OBUF instantiations OBUF u_cas_n_obuf ( .I (out_cas_n), .O (ddr_cas_n) ); OBUF u_ras_n_obuf ( .I (out_ras_n), .O (ddr_ras_n) ); OBUF u_we_n_obuf ( .I (out_we_n), .O (ddr_we_n) ); generate genvar p; for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf OBUF u_addr_obuf ( .I (out_addr[p]), .O (ddr_addr[p]) ); end for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf OBUF u_bank_obuf ( .I (out_ba[p]), .O (ddr_ba[p]) ); end if (USE_CS_PORT == 1) begin: gen_cs_n_obuf for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf OBUF u_cs_n_obuf ( .I (out_cs_n[p]), .O (ddr_cs_n[p]) ); end end if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo if (USE_ODT_PORT== 1) begin: gen_odt_obuf for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf OBUF u_cs_n_obuf ( .I (out_odt[p]), .O (ddr_odt[p]) ); end end for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf OBUF u_cs_n_obuf ( .I (out_cke[p]), .O (ddr_cke[p]) ); end end if (REG_CTRL == "ON") begin: gen_parity_obuf // Generate addr/ctrl parity output only for DDR3 registered DIMMs OBUF u_parity_obuf ( .I (out_parity), .O (ddr_parity) ); end else begin: gen_parity_tieoff assign ddr_parity = 1'b0; end if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf // Generate reset output only for DDR3 and DDR2 RDIMMs OBUF u_reset_obuf ( .I (mux_reset_n), .O (ddr_reset_n) ); end else begin: gen_reset_tieoff assign ddr_reset_n = 1'b1; end if (USE_DM_PORT == 1) begin: gen_dm_obuf for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm OBUFT u_dm_obuf ( .I (out_dm[p]), .T (ts_dm[p]), .O (ddr_dm[p]) ); end end else begin: gen_dm_tieoff assign ddr_dm = 'b0; end if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end else begin: gen_dq_iobuf_default for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end //if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else if ((DRAM_TYPE == "DDR2") || (tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff IOBUFDS_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS_DIFF_OUT_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE"), .SIM_DEVICE ("7SERIES"), .USE_IBUFDISABLE ("FALSE") ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .TM (ts_dqs[p]), .TS (ts_dqs[p]), .OB (in_dqs_lpbk_to_iddr[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); mig_7series_v2_3_poc_pd # ( .TCQ (TCQ), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) ) u_iddr_edge_det ( .clk (clk), .iddr_rst (iddr_rst), .kclk (in_dqs_lpbk_to_iddr[p]), .mmcm_ps_clk (mmcm_ps_clk), .pd_out (pd_out_pre[p]) ); end end //end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else if ((DRAM_TYPE == "DDR2") || (tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff IOBUFDS_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS_DIFF_OUT_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE"), .SIM_DEVICE ("7SERIES"), .USE_IBUFDISABLE ("FALSE") ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), //.IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .TM (ts_dqs[p]), .TS (ts_dqs[p]), .OB (in_dqs_lpbk_to_iddr[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); mig_7series_v2_3_poc_pd # ( .TCQ (TCQ), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) ) u_iddr_edge_det ( .clk (clk), .iddr_rst (iddr_rst), .kclk (in_dqs_lpbk_to_iddr[p]), .mmcm_ps_clk (mmcm_ps_clk), .pd_out (pd_out_pre[p]) ); end end end else begin: gen_dqs_iobuf_default for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end end end endgenerate always @(posedge clk) begin phy_ctl_wd_i1 <= #TCQ phy_ctl_wd; phy_ctl_wr_i1 <= #TCQ phy_ctl_wr; phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1; phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1; data_offset_1_i1 <= #TCQ data_offset_1; data_offset_1_i2 <= #TCQ data_offset_1_i1; data_offset_2_i1 <= #TCQ data_offset_2; data_offset_2_i2 <= #TCQ data_offset_2_i1; end // 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it. // 2:1 mode the command goes through pre fifo assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of; assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of; assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of; assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of; generate begin mig_7series_v2_3_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (32) ) phy_ctl_pre_fifo_0 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[1]), .wr_en_in (phy_ctl_wr), .d_in (phy_ctl_wd), .wr_en_out (phy_ctl_wr_of), .d_out (phy_ctl_wd_of) ); mig_7series_v2_3_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (6) ) phy_ctl_pre_fifo_1 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[2]), .wr_en_in (phy_ctl_wr), .d_in (data_offset_1), .wr_en_out (), .d_out (data_offset_1_of) ); mig_7series_v2_3_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (6) ) phy_ctl_pre_fifo_2 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[3]), .wr_en_in (phy_ctl_wr), .d_in (data_offset_2), .wr_en_out (), .d_out (data_offset_2_of) ); end endgenerate //*************************************************************************** // Hard PHY instantiation //*************************************************************************** assign phy_ctl_full = phy_ctl_full_temp[0]; mig_7series_v2_3_ddr_mc_phy # ( .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .PHY_0_BITLANES (PHY_0_BITLANES), .PHY_1_BITLANES (PHY_1_BITLANES), .PHY_2_BITLANES (PHY_2_BITLANES), .PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY), .PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY), .PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY), .RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK), .RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE), //.CKE_ODT_AUX (CKE_ODT_AUX), .GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP), .BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK), .NUM_DDR_CK (CK_WIDTH), .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH), .PO_CTL_COARSE_BYPASS ("FALSE"), .PHYCTL_CMD_FIFO ("FALSE"), .PHY_CLK_RATIO (nCK_PER_CLK), .MASTER_PHY_CTL (MASTER_PHY_CTL), .PHY_FOUR_WINDOW_CLOCKS (63), .PHY_EVENTS_DELAY (18), .PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN .PHY_SYNC_MODE ("FALSE"), .SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"), .PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE" .PHY_0_GENERATE_IDELAYCTRL ("FALSE"), .PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV), .PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE .PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0), .PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1), .PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2), .PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3), .PHY_0_RD_DURATION_0 (6), .PHY_0_RD_DURATION_1 (6), .PHY_0_RD_DURATION_2 (6), .PHY_0_RD_DURATION_3 (6), .PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0), .PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1), .PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2), .PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3), .PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0), .PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1), .PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2), .PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3), .PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5), .PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV), .PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_GENERATE_IDELAYCTRL ("FALSE"), //.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK), //.PHY_1_NUM_DDR_CK (1), .PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_GENERATE_IDELAYCTRL ("FALSE"), //.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK), //.PHY_2_NUM_DDR_CK (1), .PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .TCK (tCK), .PHY_0_IODELAY_GRP (IODELAY_GRP), .PHY_1_IODELAY_GRP (IODELAY_GRP), .PHY_2_IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .CKE_ODT_AUX (CKE_ODT_AUX) ) u_ddr_mc_phy ( .rst (rst), // Don't use MC_PHY to generate DDR_RESET_N output. Instead // generate this output outside of MC_PHY (and synchronous to CLK) .ddr_rst_in_n (1'b1), .phy_clk (clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), // Remove later - always same connection as phy_clk port .mem_refclk_div4 (clk), .pll_lock (pll_lock), .auxout_clk (), .sync_pulse (sync_pulse), // IDELAYCTRL instantiated outside of mc_phy module .idelayctrl_refclk (), .phy_dout (phy_dout), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phy_ctl_wd (phy_ctl_wd_temp), .phy_ctl_wr (phy_ctl_wr_temp), .if_empty_def (phy_if_empty_def), .if_rst (phy_if_reset), .phyGo ('b1), .aux_in_1 (aux_in_1), .aux_in_2 (aux_in_2), // No support yet for different data offsets for different I/O banks // (possible use in supporting wider range of skew among bytes) .data_offset_1 (data_offset_1_temp), .data_offset_2 (data_offset_2_temp), .cke_in (), .if_a_empty (), .if_empty (if_empty), .if_empty_or (), .if_empty_and (), .of_ctl_a_full (), // .of_data_a_full (phy_data_full), .of_ctl_full (phy_cmd_full), .of_data_full (), .pre_data_a_full (phy_pre_data_a_full), .idelay_ld (idelay_ld), .idelay_ce (idelay_ce), .idelay_inc (idelay_inc), .input_sink (), .phy_din (phy_din), .phy_ctl_a_full (), .phy_ctl_full (phy_ctl_full_temp), .mem_dq_out (mem_dq_out), .mem_dq_ts (mem_dq_ts), .mem_dq_in (mem_dq_in), .mem_dqs_out (mem_dqs_out), .mem_dqs_ts (mem_dqs_ts), .mem_dqs_in (mem_dqs_in), .aux_out (aux_out), .phy_ctl_ready (), .rst_out (), .ddr_clk (ddr_clk), //.rclk (), .mcGo (phy_mc_go), .phy_write_calib (phy_write_calib), .phy_read_calib (phy_read_calib), .calib_sel (calib_sel), .calib_in_common (calib_in_common), .calib_zero_inputs (calib_zero_inputs), .calib_zero_ctrl (calib_zero_ctrl), .calib_zero_lanes ('b0), .po_fine_enable (po_fine_enable), .po_coarse_enable (po_coarse_enable), .po_fine_inc (po_fine_inc), .po_coarse_inc (po_coarse_inc), .po_counter_load_en (po_counter_load_en), .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay), .po_counter_load_val (po_counter_load_val), .po_counter_read_en (po_counter_read_en), .po_coarse_overflow (), .po_fine_overflow (), .po_counter_read_val (po_counter_read_val), .pi_rst_dqs_find (pi_rst_dqs_find), .pi_fine_enable (pi_fine_enable), .pi_fine_inc (pi_fine_inc), .pi_counter_load_en (pi_counter_load_en), .pi_counter_read_en (dbg_pi_counter_read_en), .pi_counter_load_val (pi_counter_load_val), .pi_fine_overflow (), .pi_counter_read_val (pi_counter_read_val), .pi_phase_locked (pi_phase_locked), .pi_phase_locked_all (pi_phase_locked_all), .pi_dqs_found (), .pi_dqs_found_any (pi_dqs_found), .pi_dqs_found_all (pi_dqs_found_all), .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes), // Currently not being used. May be used in future if periodic // reads become a requirement. This output could be used to signal // a catastrophic failure in read capture and the need for // re-calibration. .pi_dqs_out_of_range (pi_dqs_out_of_range) ,.ref_dll_lock (ref_dll_lock) ,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes) ,.fine_delay (fine_delay_mod) ,.fine_delay_sel (fine_delay_sel_r) // ,.rst_phaser_ref (rst_phaser_ref) ); endmodule

//***************************************************************************** // (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ddr_mc_phy_wrapper.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Oct 10 2010 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Wrapper file that encompasses the MC_PHY module // instantiation and handles the vector remapping between // the MC_PHY ports and the user's DDR3 ports. Vector // remapping affects DDR3 control, address, and DQ/DQS/DM. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_ddr_mc_phy_wrapper # ( parameter TCQ = 100, // Register delay (simulation only) parameter tCK = 2500, // ps parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" parameter IODELAY_GRP = "IODELAY_MIG", parameter FPGA_SPEED_GRADE = 1, parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank parameter BANK_WIDTH = 3, // # of bank address parameter CKE_WIDTH = 1, // # of clock enable outputs parameter CS_WIDTH = 1, // # of chip select parameter CK_WIDTH = 1, // # of CK parameter CWL = 5, // CAS Write latency parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter DM_WIDTH = 8, // # of data mask parameter DQ_WIDTH = 16, // # of data bits parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of strobe pairs parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3) parameter RANKS = 4, // # of ranks parameter ODT_WIDTH = 1, // # of ODT outputs parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter REG_CTRL = "OFF", // "ON" for registered DIMM parameter ROW_WIDTH = 16, // # of row/column address parameter USE_CS_PORT = 1, // Support chip select output parameter USE_DM_PORT = 1, // Support data mask output parameter USE_ODT_PORT = 1, // Support ODT output parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option parameter LP_DDR_CK_WIDTH = 2, // Hard PHY parameters parameter PHYCTL_CMD_FIFO = "FALSE", parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf, parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter PHY_0_BITLANES = 48'h0000_0000_0000, parameter PHY_1_BITLANES = 48'h0000_0000_0000, parameter PHY_2_BITLANES = 48'h0000_0000_0000, // Parameters calculated outside of this block parameter HIGHEST_BANK = 3, // Highest I/O bank index parameter HIGHEST_LANE = 12, // Highest byte lane index // ** Pin mapping parameters // Parameters for mapping between hard PHY and physical DDR3 signals // There are 2 classes of parameters: // - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of // 8-bit elements. Each element indicates the bank and byte lane // location of that particular signal. The bit lane in this case // doesn't need to be specified, either because there's only one // pin pair in each byte lane that the DQS or CK pair can be // located at, or in the case of CKE_ODT_BYTE_MAP, only the byte // lane needs to be specified in order to determine which byte // lane generates the RCLK (Note that CKE, and ODT must be located // in the same bank, thus only one element in CKE_ODT_BYTE_MAP) // [7:4] = bank # (0-4) // [3:0] = byte lane # (0-3) // - All other MAP parameters: These consist of 12-bit elements. Each // element indicates the bank, byte lane, and bit lane location of // that particular signal: // [11:8] = bank # (0-4) // [7:4] = byte lane # (0-3) // [3:0] = bit lane # (0-11) // Note that not all elements in all parameters will be used - it // depends on the actual widths of the DDR3 buses. The parameters are // structured to support a maximum of: // - DQS groups: 18 // - data mask bits: 18 // In addition, the default parameter size of some of the parameters will // support a certain number of bits, however, this can be expanded at // compile time by expanding the width of the vector passed into this // parameter // - chip selects: 10 // - bank bits: 3 // - address bits: 16 parameter CK_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter ADDR_MAP = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, parameter BANK_MAP = 36'h000_000_000, parameter CAS_MAP = 12'h000, parameter CKE_ODT_BYTE_MAP = 8'h00, parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000, parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000, parameter CKE_ODT_AUX = "FALSE", parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, parameter PARITY_MAP = 12'h000, parameter RAS_MAP = 12'h000, parameter WE_MAP = 12'h000, parameter DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, // DATAx_MAP parameter is used for byte lane X in the design parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000, parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000, // MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9] parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, // Simulation options parameter SIM_CAL_OPTION = "NONE", // The PHY_CONTROL primitive in the bank where PLL exists is declared // as the Master PHY_CONTROL. parameter MASTER_PHY_CTL = 1, parameter DRAM_WIDTH = 8 ) ( input rst, input iddr_rst, input clk, input freq_refclk, input mem_refclk, input pll_lock, input sync_pulse, input mmcm_ps_clk, input idelayctrl_refclk, input phy_cmd_wr_en, input phy_data_wr_en, input [31:0] phy_ctl_wd, input phy_ctl_wr, input phy_if_empty_def, input phy_if_reset, input [5:0] data_offset_1, input [5:0] data_offset_2, input [3:0] aux_in_1, input [3:0] aux_in_2, output [4:0] idelaye2_init_val, output [5:0] oclkdelay_init_val, output if_empty, output phy_ctl_full, output phy_cmd_full, output phy_data_full, output phy_pre_data_a_full, output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk, output phy_mc_go, input phy_write_calib, input phy_read_calib, input calib_in_common, input [5:0] calib_sel, input [DQS_CNT_WIDTH:0] byte_sel_cnt, input [DRAM_WIDTH-1:0] fine_delay_incdec_pb, input fine_delay_sel, input [HIGHEST_BANK-1:0] calib_zero_inputs, input [HIGHEST_BANK-1:0] calib_zero_ctrl, input [2:0] po_fine_enable, input [2:0] po_coarse_enable, input [2:0] po_fine_inc, input [2:0] po_coarse_inc, input po_counter_load_en, input po_counter_read_en, input [2:0] po_sel_fine_oclk_delay, input [8:0] po_counter_load_val, output [8:0] po_counter_read_val, output [5:0] pi_counter_read_val, input [HIGHEST_BANK-1:0] pi_rst_dqs_find, input pi_fine_enable, input pi_fine_inc, input pi_counter_load_en, input [5:0] pi_counter_load_val, input idelay_ce, input idelay_inc, input idelay_ld, input idle, output pi_phase_locked, output pi_phase_locked_all, output pi_dqs_found, output pi_dqs_found_all, output pi_dqs_out_of_range, // From/to calibration logic/soft PHY input phy_init_data_sel, input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address, input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank, input [nCK_PER_CLK-1:0] mux_cas_n, input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n, input [nCK_PER_CLK-1:0] mux_ras_n, input [1:0] mux_odt, input [nCK_PER_CLK-1:0] mux_cke, input [nCK_PER_CLK-1:0] mux_we_n, input [nCK_PER_CLK-1:0] parity_in, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata, input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask, input mux_reset_n, output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, // Memory I/F output [ROW_WIDTH-1:0] ddr_addr, output [BANK_WIDTH-1:0] ddr_ba, output ddr_cas_n, output [CKE_WIDTH-1:0] ddr_cke, output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, output [DM_WIDTH-1:0] ddr_dm, output [ODT_WIDTH-1:0] ddr_odt, output ddr_parity, output ddr_ras_n, output ddr_we_n, output ddr_reset_n, inout [DQ_WIDTH-1:0] ddr_dq, inout [DQS_WIDTH-1:0] ddr_dqs, inout [DQS_WIDTH-1:0] ddr_dqs_n, //output iodelay_ctrl_rdy, output pd_out ,input dbg_pi_counter_read_en ,output ref_dll_lock ,input rst_phaser_ref ,output [11:0] dbg_pi_phase_locked_phy4lanes ,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes ); function [71:0] generate_bytelanes_ddr_ck; input [143:0] ck_byte_map; integer v ; begin generate_bytelanes_ddr_ck = 'b0 ; for (v = 0; v < CK_WIDTH; v = v + 1) begin if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2) generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1) generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; else generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1; end end endfunction function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map; input [143:0] ck_byte_map; integer g; begin generate_ddr_ck_map = 'b0 ; for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" : (ck_byte_map[(g*8)+:4] == 4'd1) ? "B" : (ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ; generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" : (ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location end end endfunction // Enable low power mode for input buffer localparam IBUF_LOW_PWR = (IBUF_LPWR_MODE == "OFF") ? "FALSE" : ((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL"); // Ratio of data to strobe localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH; // number of data phases per internal clock localparam PHASE_PER_CLK = 2*nCK_PER_CLK; // used to determine routing to OUT_FIFO for control/address for 2:1 // vs. 4:1 memory:internal clock ratio modes localparam PHASE_DIV = 4 / nCK_PER_CLK; localparam CLK_PERIOD = tCK * nCK_PER_CLK; // Create an aggregate parameters for data mapping to reduce # of generate // statements required in remapping code. Need to account for the case // when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP // parameter will have fewer than 8 elements used localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0], DATA16_MAP[12*DQ_PER_DQS-1:0], DATA15_MAP[12*DQ_PER_DQS-1:0], DATA14_MAP[12*DQ_PER_DQS-1:0], DATA13_MAP[12*DQ_PER_DQS-1:0], DATA12_MAP[12*DQ_PER_DQS-1:0], DATA11_MAP[12*DQ_PER_DQS-1:0], DATA10_MAP[12*DQ_PER_DQS-1:0], DATA9_MAP[12*DQ_PER_DQS-1:0], DATA8_MAP[12*DQ_PER_DQS-1:0], DATA7_MAP[12*DQ_PER_DQS-1:0], DATA6_MAP[12*DQ_PER_DQS-1:0], DATA5_MAP[12*DQ_PER_DQS-1:0], DATA4_MAP[12*DQ_PER_DQS-1:0], DATA3_MAP[12*DQ_PER_DQS-1:0], DATA2_MAP[12*DQ_PER_DQS-1:0], DATA1_MAP[12*DQ_PER_DQS-1:0], DATA0_MAP[12*DQ_PER_DQS-1:0]}; // Same deal, but for data mask mapping localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP}; localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ; localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ; // Temporary parameters to determine which bank is outputting the CK/CK# // Eventually there will be support for multiple CK/CK# output //localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]); //// Temporary method to force MC_PHY to generate ODDR associated with //// CK/CK# output only for a single byte lane in the design. All banks //// that won't be generating the CK/CK# will have "UNUSED" as their //// PHY_GENERATE_DDR_CK parameter //localparam TMP_PHY_0_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); //localparam TMP_PHY_1_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); //localparam TMP_PHY_2_GENERATE_DDR_CK // = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" : // ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" : // ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" : // ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D"))); // Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx // which indicates which bit lanes in data byte lanes are // output-only bitlanes (e.g. used specifically for data mask outputs) function [143:0] calc_phy_bitlanes_outonly; input [215:0] data_mask_in; integer z; begin calc_phy_bitlanes_outonly = 'b0; // Only enable BITLANES parameters for data masks if, well, if // the data masks are actually enabled if (USE_DM_PORT == 1) for (z = 0; z < DM_WIDTH; z = z + 1) calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] + 12*data_mask_in[(12*z+4)+:2] + data_mask_in[12*z+:4]] = 1'b1; end endfunction localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP); localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0]; localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48]; localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96]; // Determine which bank and byte lane generates the RCLK used to clock // out the auxilliary (ODT, CKE) outputs localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON = (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 : ((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1)))); localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON = (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" : ((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL"))); localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF = (CKE_MAP[11:8] == 4'h0) ? 0 : ((CKE_MAP[11:8] == 4'h1) ? 1 : ((CKE_MAP[11:8] == 4'h2) ? 2 : ((CKE_MAP[11:8] == 4'h3) ? 3 : ((CKE_MAP[11:8] == 4'h4) ? 4 : -1)))); localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF = (CKE_MAP[7:4] == 4'h0) ? "A" : ((CKE_MAP[7:4] == 4'h1) ? "B" : ((CKE_MAP[7:4] == 4'h2) ? "C" : ((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL"))); localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ; localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ; //*************************************************************************** // OCLKDELAYED tap setting calculation: // Parameters for calculating amount of phase shifting output clock to // achieve 90 degree offset between DQS and DQ on writes //*************************************************************************** //90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz // and 1.25 for Mem_RefClk > 300 MHz localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE"; //DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400, //DIV4: MemRefClk < 200 MHz localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" : tCK > 2500 ? "DIV2": "NONE"; localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 : PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1); // Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK; // Whether OCLK_DELAY output comes inverted or not localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0); // Phaser-Out Stage3 Tap delay for 90 deg shift. // Maximum tap delay is FreqRefClk period distributed over 64 taps // localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV; localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) - (INT_DELAY + HALF_CYCLE_DELAY)) * 63 * FREQ_REF_DIV; //localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY; localparam integer PHY_0_A_PO_OCLK_DELAY_HW = (tCK > 2273) ? 34 : (tCK > 2000) ? 33 : (tCK > 1724) ? 32 : (tCK > 1515) ? 31 : (tCK > 1315) ? 30 : (tCK > 1136) ? 29 : (tCK > 1021) ? 28 : 27; // Note that simulation requires a different value than in H/W because of the // difference in the way delays are modeled localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ? ((tCK > 2500) ? 8 : (DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) : MC_OCLK_DELAY; // Initial DQ IDELAY value localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 : (tCK < 1000) ? 0 : (tCK < 1330) ? 0 : (tCK < 2300) ? 0 : (tCK < 2500) ? 2 : 0; //localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0; // Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3? localparam PHY_0_RD_CMD_OFFSET_0 = 10; localparam PHY_0_RD_CMD_OFFSET_1 = 10; localparam PHY_0_RD_CMD_OFFSET_2 = 10; localparam PHY_0_RD_CMD_OFFSET_3 = 10; // 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4; localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4; // 4:1 and 2:1 have different values localparam PHY_0_WR_DURATION_0 = 7; localparam PHY_0_WR_DURATION_1 = 7; localparam PHY_0_WR_DURATION_2 = 7; localparam PHY_0_WR_DURATION_3 = 7; // Aux_out parameters for toggle mode (CKE) localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 : (CWL < 7) ? 4 + ((CWL_M % 2) ? 0 : 1) : 5 + ((CWL_M % 2) ? 0 : 1); // temporary parameter to enable/disable PHY PC counters. In both 4:1 and // 2:1 cases, this should be disabled. For now, enable for 4:1 mode to // avoid making too many changes at once. localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE"; wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out; wire [HIGHEST_LANE-1:0] mem_dqs_in; wire [HIGHEST_LANE-1:0] mem_dqs_out; wire [HIGHEST_LANE-1:0] mem_dqs_ts; wire [HIGHEST_LANE*10-1:0] mem_dq_in; wire [HIGHEST_LANE*12-1:0] mem_dq_out; wire [HIGHEST_LANE*12-1:0] mem_dq_ts; wire [DQ_WIDTH-1:0] in_dq; wire [DQS_WIDTH-1:0] in_dqs; wire [ROW_WIDTH-1:0] out_addr; wire [BANK_WIDTH-1:0] out_ba; wire out_cas_n; wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n; wire [DM_WIDTH-1:0] out_dm; wire [ODT_WIDTH -1:0] out_odt; wire [CKE_WIDTH -1 :0] out_cke ; wire [DQ_WIDTH-1:0] out_dq; wire [DQS_WIDTH-1:0] out_dqs; wire out_parity; wire out_ras_n; wire out_we_n; wire [HIGHEST_LANE*80-1:0] phy_din; wire [HIGHEST_LANE*80-1:0] phy_dout; wire phy_rd_en; wire [DM_WIDTH-1:0] ts_dm; wire [DQ_WIDTH-1:0] ts_dq; wire [DQS_WIDTH-1:0] ts_dqs; wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr; wire [DQS_WIDTH-1:0] pd_out_pre; //wire metaQ; reg [31:0] phy_ctl_wd_i1; reg [31:0] phy_ctl_wd_i2; reg phy_ctl_wr_i1; reg phy_ctl_wr_i2; reg [5:0] data_offset_1_i1; reg [5:0] data_offset_1_i2; reg [5:0] data_offset_2_i1; reg [5:0] data_offset_2_i2; wire [31:0] phy_ctl_wd_temp; wire phy_ctl_wr_temp; wire [5:0] data_offset_1_temp; wire [5:0] data_offset_2_temp; wire [5:0] data_offset_1_of; wire [5:0] data_offset_2_of; wire [31:0] phy_ctl_wd_of; wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */; wire [3:0] phy_ctl_full_temp; wire data_io_idle_pwrdwn; reg [29:0] fine_delay_mod; //3 bit per DQ reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb (* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1; // Always read from input data FIFOs when not empty assign phy_rd_en = !if_empty; // IDELAYE2 initial value assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE; assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY; // Idle powerdown when there are no pending reads in the MC assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0; //*************************************************************************** // Auxiliary output steering //*************************************************************************** // For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be // mapped to ddr_odt and the aux_out[7:4] from one of the data banks // will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the // addr/ctl bank would bank would map to both ddr_odt and ddr_cke. generate if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins if (CKE_WIDTH == 1) begin : gen_cke // Explicitly instantiate OBUF to ensure that these are present // in the netlist. Typically this is not required since NGDBUILD // at the top-level knows to infer an I/O/IOBUF and therefore a // top-level LOC constraint can be attached to that pin. This does // not work when a hierarchical flow is used and the LOC is applied // at the individual core-level UCF OBUF u_cke_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), .O (ddr_cke) ); end else begin: gen_2rank_cke OBUF u_cke0_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]), .O (ddr_cke[0]) ); OBUF u_cke1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_cke[1]) ); end end endgenerate generate if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins if (USE_ODT_PORT == 1) begin : gen_use_odt // Explicitly instantiate OBUF to ensure that these are present // in the netlist. Typically this is not required since NGDBUILD // at the top-level knows to infer an I/O/IOBUF and therefore a // top-level LOC constraint can be attached to that pin. This does // not work when a hierarchical flow is used and the LOC is applied // at the individual core-level UCF OBUF u_odt_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]), .O (ddr_odt[0]) ); if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_odt[1]) ); end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), .O (ddr_odt[1]) ); end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt OBUF u_odt1_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]), .O (ddr_odt[1]) ); OBUF u_odt2_obuf ( .I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]), .O (ddr_odt[2]) ); end end else begin assign ddr_odt = 'b0; end end endgenerate //*************************************************************************** // Read data bit steering //*************************************************************************** // Transpose elements of rd_data_map to form final read data output: // phy_din elements are grouped according to "physical bit" - e.g. // for nCK_PER_CLK = 4, there are 8 data phases transfered per physical // bit per clock cycle: // = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2, // dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0} // whereas rd_data is are grouped according to "phase" - e.g. // = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0, // dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0} // therefore rd_data is formed by transposing phy_din - e.g. // for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY // bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then // the assignments for bits of rd_data corresponding to DQ[1:0] // would be: // {rd_data[112], rd_data[96], rd_data[80], rd_data[64], // rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0] // {rd_data[113], rd_data[97], rd_data[81], rd_data[65], // rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8] generate genvar i, j; for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1 for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2 assign rd_data[DQ_WIDTH*j + i] = phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+ 80*FULL_DATA_MAP[(12*i+4)+:2] + 8*FULL_DATA_MAP[12*i+:4]) + j]; end end endgenerate //generage idelay_inc per bits reg [11:0] cal_tmp; reg [95:0] byte_sel_data_map; assign byte_sel_cnt_w1 = byte_sel_cnt; always @ (posedge clk) begin byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96]; end always @ (posedge clk) begin fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00}; fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00}; fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00}; fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00}; fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00}; fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00}; fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00}; fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00}; fine_delay_sel_r <= #TCQ fine_delay_sel; end //*************************************************************************** // Control/address //*************************************************************************** assign out_cas_n = mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]]; generate // if signal placed on bit lanes [0-9] if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10 // Determine routing based on clock ratio mode. If running in 4:1 // mode, then all four bits from logic are used. If 2:1 mode, only // 2-bits are provided by logic, and each bit is repeated 2x to form // 4-bit input to IN_FIFO, e.g. // 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]} // 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]} assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + 8*CAS_MAP[3:0])+:4] = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; end else begin: gen_cas_ge10 // If signal is placed in bit lane [10] or [11], route to upper // nibble of phy_dout lane [5] or [6] respectively (in this case // phy_dout lane [5, 6] are multiplexed to take input for two // different SDR signals - this is how bits[10,11] need to be // provided to the OUT_FIFO assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] + 8*(CAS_MAP[3:0]-5) + 4)+:4] = {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV], mux_cas_n[1/PHASE_DIV], mux_cas_n[0]}; end endgenerate assign out_ras_n = mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]]; generate if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10 assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + 8*RAS_MAP[3:0])+:4] = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; end else begin: gen_ras_ge10 assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] + 8*(RAS_MAP[3:0]-5) + 4)+:4] = {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV], mux_ras_n[1/PHASE_DIV], mux_ras_n[0]}; end endgenerate assign out_we_n = mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]]; generate if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10 assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + 8*WE_MAP[3:0])+:4] = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], mux_we_n[1/PHASE_DIV], mux_we_n[0]}; end else begin: gen_we_ge10 assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] + 8*(WE_MAP[3:0]-5) + 4)+:4] = {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV], mux_we_n[1/PHASE_DIV], mux_we_n[0]}; end endgenerate generate if (REG_CTRL == "ON") begin: gen_parity_out // Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs assign out_parity = mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] + PARITY_MAP[3:0]]; if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10 assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + 8*PARITY_MAP[3:0])+:4] = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], parity_in[1/PHASE_DIV], parity_in[0]}; end else begin: gen_ge10 assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] + 8*(PARITY_MAP[3:0]-5) + 4)+:4] = {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV], parity_in[1/PHASE_DIV], parity_in[0]}; end end endgenerate //***************************************************************** generate genvar m, n,x; //***************************************************************** // Control/address (multi-bit) buses //***************************************************************** // Row/Column address for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out assign out_addr[m] = mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] + 12*ADDR_MAP[(12*m+4)+:2] + ADDR_MAP[12*m+:4]]; if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10 // For multi-bit buses, we also have to deal with transposition // when going from the logic-side control bus to phy_dout for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + 80*ADDR_MAP[(12*m+4)+:2] + 8*ADDR_MAP[12*m+:4] + n] = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] + 80*ADDR_MAP[(12*m+4)+:2] + 8*(ADDR_MAP[12*m+:4]-5) + 4 + n] = mux_address[ROW_WIDTH*(n/PHASE_DIV) + m]; end end end // Bank address for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out assign out_ba[m] = mem_dq_out[48*BANK_MAP[(12*m+8)+:3] + 12*BANK_MAP[(12*m+4)+:2] + BANK_MAP[12*m+:4]]; if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + 80*BANK_MAP[(12*m+4)+:2] + 8*BANK_MAP[12*m+:4] + n] = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*BANK_MAP[(12*m+8)+:3] + 80*BANK_MAP[(12*m+4)+:2] + 8*(BANK_MAP[12*m+:4]-5) + 4 + n] = mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m]; end end end // Chip select if (USE_CS_PORT == 1) begin: gen_cs_n_out for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out assign out_cs_n[m] = mem_dq_out[48*CS_MAP[(12*m+8)+:3] + 12*CS_MAP[(12*m+4)+:2] + CS_MAP[12*m+:4]]; if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CS_MAP[(12*m+8)+:3] + 80*CS_MAP[(12*m+4)+:2] + 8*CS_MAP[12*m+:4] + n] = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CS_MAP[(12*m+8)+:3] + 80*CS_MAP[(12*m+4)+:2] + 8*(CS_MAP[12*m+:4]-5) + 4 + n] = mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m]; end end end end if(CKE_ODT_AUX == "FALSE") begin // ODT_ports wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ; if(RANKS == 1) begin for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ; end end else begin for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ; assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ; end end if (USE_ODT_PORT == 1) begin: gen_odt_out for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1 assign out_odt[m] = mem_dq_out[48*ODT_MAP[(12*m+8)+:3] + 12*ODT_MAP[(12*m+4)+:2] + ODT_MAP[12*m+:4]]; if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + 80*ODT_MAP[(12*m+4)+:2] + 8*ODT_MAP[12*m+:4] + n] = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*ODT_MAP[(12*m+8)+:3] + 80*ODT_MAP[(12*m+4)+:2] + 8*(ODT_MAP[12*m+:4]-5) + 4 + n] = mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m]; end end end end wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ; for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ; end for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out assign out_cke[m] = mem_dq_out[48*CKE_MAP[(12*m+8)+:3] + 12*CKE_MAP[(12*m+4)+:2] + CKE_MAP[12*m+:4]]; if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + 80*CKE_MAP[(12*m+4)+:2] + 8*CKE_MAP[12*m+:4] + n] = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; end end else begin: gen_ge10 for (n = 0; n < 4; n = n + 1) begin: loop_xpose assign phy_dout[320*CKE_MAP[(12*m+8)+:3] + 80*CKE_MAP[(12*m+4)+:2] + 8*(CKE_MAP[12*m+:4]-5) + 4 + n] = mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m]; end end end end //***************************************************************** // Data mask //***************************************************************** if (USE_DM_PORT == 1) begin: gen_dm_out for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out assign out_dm[m] = mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] + 12*FULL_MASK_MAP[(12*m+4)+:2] + FULL_MASK_MAP[12*m+:4]]; assign ts_dm[m] = mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] + 12*FULL_MASK_MAP[(12*m+4)+:2] + FULL_MASK_MAP[12*m+:4]]; for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] + 80*FULL_MASK_MAP[(12*m+4)+:2] + 8*FULL_MASK_MAP[12*m+:4] + n] = mux_wrdata_mask[DM_WIDTH*n + m]; end end end //***************************************************************** // Input and output DQ //***************************************************************** for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout // to MC_PHY assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] + 10*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]] = in_dq[m]; // to I/O buffers assign out_dq[m] = mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] + 12*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]]; assign ts_dq[m] = mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] + 12*FULL_DATA_MAP[(12*m+4)+:2] + FULL_DATA_MAP[12*m+:4]]; for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] + 80*FULL_DATA_MAP[(12*m+4)+:2] + 8*FULL_DATA_MAP[12*m+:4] + n] = mux_wrdata[DQ_WIDTH*n + m]; end end //***************************************************************** // Input and output DQS //***************************************************************** for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout // to MC_PHY assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]] = in_dqs[m]; // to I/O buffers assign out_dqs[m] = mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; assign ts_dqs[m] = mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]; end endgenerate assign pd_out = pd_out_pre[byte_sel_cnt_w1]; //*************************************************************************** // Memory I/F output and I/O buffer instantiation //*************************************************************************** // Note on instantiation - generally at the minimum, it's not required to // instantiate the output buffers - they can be inferred by the synthesis // tool, and there aren't any attributes that need to be associated with // them. Consider as a future option to take out the OBUF instantiations OBUF u_cas_n_obuf ( .I (out_cas_n), .O (ddr_cas_n) ); OBUF u_ras_n_obuf ( .I (out_ras_n), .O (ddr_ras_n) ); OBUF u_we_n_obuf ( .I (out_we_n), .O (ddr_we_n) ); generate genvar p; for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf OBUF u_addr_obuf ( .I (out_addr[p]), .O (ddr_addr[p]) ); end for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf OBUF u_bank_obuf ( .I (out_ba[p]), .O (ddr_ba[p]) ); end if (USE_CS_PORT == 1) begin: gen_cs_n_obuf for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf OBUF u_cs_n_obuf ( .I (out_cs_n[p]), .O (ddr_cs_n[p]) ); end end if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo if (USE_ODT_PORT== 1) begin: gen_odt_obuf for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf OBUF u_cs_n_obuf ( .I (out_odt[p]), .O (ddr_odt[p]) ); end end for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf OBUF u_cs_n_obuf ( .I (out_cke[p]), .O (ddr_cke[p]) ); end end if (REG_CTRL == "ON") begin: gen_parity_obuf // Generate addr/ctrl parity output only for DDR3 registered DIMMs OBUF u_parity_obuf ( .I (out_parity), .O (ddr_parity) ); end else begin: gen_parity_tieoff assign ddr_parity = 1'b0; end if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf // Generate reset output only for DDR3 and DDR2 RDIMMs OBUF u_reset_obuf ( .I (mux_reset_n), .O (ddr_reset_n) ); end else begin: gen_reset_tieoff assign ddr_reset_n = 1'b1; end if (USE_DM_PORT == 1) begin: gen_dm_obuf for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm OBUFT u_dm_obuf ( .I (out_dm[p]), .T (ts_dm[p]), .O (ddr_dm[p]) ); end end else begin: gen_dm_tieoff assign ddr_dm = 'b0; end if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end else begin: gen_dq_iobuf_default for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf IOBUF # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dq ( .I (out_dq[p]), .T (ts_dq[p]), .O (in_dq[p]), .IO (ddr_dq[p]) ); end end //if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else if ((DRAM_TYPE == "DDR2") || (tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff IOBUFDS_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS_DIFF_OUT_DCIEN # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE"), .SIM_DEVICE ("7SERIES"), .USE_IBUFDISABLE ("FALSE") ) u_iobuf_dqs ( .DCITERMDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .TM (ts_dqs[p]), .TS (ts_dqs[p]), .OB (in_dqs_lpbk_to_iddr[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); mig_7series_v2_3_poc_pd # ( .TCQ (TCQ), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) ) u_iddr_edge_det ( .clk (clk), .iddr_rst (iddr_rst), .kclk (in_dqs_lpbk_to_iddr[p]), .mmcm_ps_clk (mmcm_ps_clk), .pd_out (pd_out_pre[p]) ); end end //end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else if ((DRAM_TYPE == "DDR2") || (tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff IOBUFDS_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), .IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS_DIFF_OUT_INTERMDISABLE # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE"), .SIM_DEVICE ("7SERIES"), .USE_IBUFDISABLE ("FALSE") ) u_iobuf_dqs ( .INTERMDISABLE (data_io_idle_pwrdwn), //.IBUFDISABLE (data_io_idle_pwrdwn), .I (out_dqs[p]), .TM (ts_dqs[p]), .TS (ts_dqs[p]), .OB (in_dqs_lpbk_to_iddr[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); mig_7series_v2_3_poc_pd # ( .TCQ (TCQ), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP) ) u_iddr_edge_det ( .clk (clk), .iddr_rst (iddr_rst), .kclk (in_dqs_lpbk_to_iddr[p]), .mmcm_ps_clk (mmcm_ps_clk), .pd_out (pd_out_pre[p]) ); end end end else begin: gen_dqs_iobuf_default for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf if ((DRAM_TYPE == "DDR2") && (DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se IOBUF # ( .IBUF_LOW_PWR (IBUF_LOW_PWR) ) u_iobuf_dqs ( .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]) ); assign ddr_dqs_n[p] = 1'b0; assign pd_out_pre[p] = 1'b0; end else begin: gen_dqs_diff IOBUFDS # ( .IBUF_LOW_PWR (IBUF_LOW_PWR), .DQS_BIAS ("TRUE") ) u_iobuf_dqs ( .I (out_dqs[p]), .T (ts_dqs[p]), .O (in_dqs[p]), .IO (ddr_dqs[p]), .IOB (ddr_dqs_n[p]) ); assign pd_out_pre[p] = 1'b0; end end end endgenerate always @(posedge clk) begin phy_ctl_wd_i1 <= #TCQ phy_ctl_wd; phy_ctl_wr_i1 <= #TCQ phy_ctl_wr; phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1; phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1; data_offset_1_i1 <= #TCQ data_offset_1; data_offset_1_i2 <= #TCQ data_offset_1_i1; data_offset_2_i1 <= #TCQ data_offset_2; data_offset_2_i2 <= #TCQ data_offset_2_i1; end // 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it. // 2:1 mode the command goes through pre fifo assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of; assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of; assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of; assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of; generate begin mig_7series_v2_3_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (32) ) phy_ctl_pre_fifo_0 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[1]), .wr_en_in (phy_ctl_wr), .d_in (phy_ctl_wd), .wr_en_out (phy_ctl_wr_of), .d_out (phy_ctl_wd_of) ); mig_7series_v2_3_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (6) ) phy_ctl_pre_fifo_1 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[2]), .wr_en_in (phy_ctl_wr), .d_in (data_offset_1), .wr_en_out (), .d_out (data_offset_1_of) ); mig_7series_v2_3_ddr_of_pre_fifo # ( .TCQ (25), .DEPTH (8), .WIDTH (6) ) phy_ctl_pre_fifo_2 ( .clk (clk), .rst (rst), .full_in (phy_ctl_full_temp[3]), .wr_en_in (phy_ctl_wr), .d_in (data_offset_2), .wr_en_out (), .d_out (data_offset_2_of) ); end endgenerate //*************************************************************************** // Hard PHY instantiation //*************************************************************************** assign phy_ctl_full = phy_ctl_full_temp[0]; mig_7series_v2_3_ddr_mc_phy # ( .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .PHY_0_BITLANES (PHY_0_BITLANES), .PHY_1_BITLANES (PHY_1_BITLANES), .PHY_2_BITLANES (PHY_2_BITLANES), .PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY), .PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY), .PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY), .RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK), .RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE), //.CKE_ODT_AUX (CKE_ODT_AUX), .GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP), .BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK), .NUM_DDR_CK (CK_WIDTH), .LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH), .PO_CTL_COARSE_BYPASS ("FALSE"), .PHYCTL_CMD_FIFO ("FALSE"), .PHY_CLK_RATIO (nCK_PER_CLK), .MASTER_PHY_CTL (MASTER_PHY_CTL), .PHY_FOUR_WINDOW_CLOCKS (63), .PHY_EVENTS_DELAY (18), .PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN .PHY_SYNC_MODE ("FALSE"), .SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"), .PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE" .PHY_0_GENERATE_IDELAYCTRL ("FALSE"), .PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV), .PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE .PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0), .PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1), .PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2), .PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3), .PHY_0_RD_DURATION_0 (6), .PHY_0_RD_DURATION_1 (6), .PHY_0_RD_DURATION_2 (6), .PHY_0_RD_DURATION_3 (6), .PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0), .PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1), .PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2), .PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3), .PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0), .PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1), .PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2), .PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3), .PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5), .PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV), .PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_GENERATE_IDELAYCTRL ("FALSE"), //.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK), //.PHY_1_NUM_DDR_CK (1), .PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_GENERATE_IDELAYCTRL ("FALSE"), //.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK), //.PHY_2_NUM_DDR_CK (1), .PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY), .PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE), .TCK (tCK), .PHY_0_IODELAY_GRP (IODELAY_GRP), .PHY_1_IODELAY_GRP (IODELAY_GRP), .PHY_2_IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .BANK_TYPE (BANK_TYPE), .CKE_ODT_AUX (CKE_ODT_AUX) ) u_ddr_mc_phy ( .rst (rst), // Don't use MC_PHY to generate DDR_RESET_N output. Instead // generate this output outside of MC_PHY (and synchronous to CLK) .ddr_rst_in_n (1'b1), .phy_clk (clk), .freq_refclk (freq_refclk), .mem_refclk (mem_refclk), // Remove later - always same connection as phy_clk port .mem_refclk_div4 (clk), .pll_lock (pll_lock), .auxout_clk (), .sync_pulse (sync_pulse), // IDELAYCTRL instantiated outside of mc_phy module .idelayctrl_refclk (), .phy_dout (phy_dout), .phy_cmd_wr_en (phy_cmd_wr_en), .phy_data_wr_en (phy_data_wr_en), .phy_rd_en (phy_rd_en), .phy_ctl_wd (phy_ctl_wd_temp), .phy_ctl_wr (phy_ctl_wr_temp), .if_empty_def (phy_if_empty_def), .if_rst (phy_if_reset), .phyGo ('b1), .aux_in_1 (aux_in_1), .aux_in_2 (aux_in_2), // No support yet for different data offsets for different I/O banks // (possible use in supporting wider range of skew among bytes) .data_offset_1 (data_offset_1_temp), .data_offset_2 (data_offset_2_temp), .cke_in (), .if_a_empty (), .if_empty (if_empty), .if_empty_or (), .if_empty_and (), .of_ctl_a_full (), // .of_data_a_full (phy_data_full), .of_ctl_full (phy_cmd_full), .of_data_full (), .pre_data_a_full (phy_pre_data_a_full), .idelay_ld (idelay_ld), .idelay_ce (idelay_ce), .idelay_inc (idelay_inc), .input_sink (), .phy_din (phy_din), .phy_ctl_a_full (), .phy_ctl_full (phy_ctl_full_temp), .mem_dq_out (mem_dq_out), .mem_dq_ts (mem_dq_ts), .mem_dq_in (mem_dq_in), .mem_dqs_out (mem_dqs_out), .mem_dqs_ts (mem_dqs_ts), .mem_dqs_in (mem_dqs_in), .aux_out (aux_out), .phy_ctl_ready (), .rst_out (), .ddr_clk (ddr_clk), //.rclk (), .mcGo (phy_mc_go), .phy_write_calib (phy_write_calib), .phy_read_calib (phy_read_calib), .calib_sel (calib_sel), .calib_in_common (calib_in_common), .calib_zero_inputs (calib_zero_inputs), .calib_zero_ctrl (calib_zero_ctrl), .calib_zero_lanes ('b0), .po_fine_enable (po_fine_enable), .po_coarse_enable (po_coarse_enable), .po_fine_inc (po_fine_inc), .po_coarse_inc (po_coarse_inc), .po_counter_load_en (po_counter_load_en), .po_sel_fine_oclk_delay (po_sel_fine_oclk_delay), .po_counter_load_val (po_counter_load_val), .po_counter_read_en (po_counter_read_en), .po_coarse_overflow (), .po_fine_overflow (), .po_counter_read_val (po_counter_read_val), .pi_rst_dqs_find (pi_rst_dqs_find), .pi_fine_enable (pi_fine_enable), .pi_fine_inc (pi_fine_inc), .pi_counter_load_en (pi_counter_load_en), .pi_counter_read_en (dbg_pi_counter_read_en), .pi_counter_load_val (pi_counter_load_val), .pi_fine_overflow (), .pi_counter_read_val (pi_counter_read_val), .pi_phase_locked (pi_phase_locked), .pi_phase_locked_all (pi_phase_locked_all), .pi_dqs_found (), .pi_dqs_found_any (pi_dqs_found), .pi_dqs_found_all (pi_dqs_found_all), .pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes), // Currently not being used. May be used in future if periodic // reads become a requirement. This output could be used to signal // a catastrophic failure in read capture and the need for // re-calibration. .pi_dqs_out_of_range (pi_dqs_out_of_range) ,.ref_dll_lock (ref_dll_lock) ,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes) ,.fine_delay (fine_delay_mod) ,.fine_delay_sel (fine_delay_sel_r) // ,.rst_phaser_ref (rst_phaser_ref) ); endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ecc_buf.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ecc_buf #( parameter TCQ = 100, parameter PAYLOAD_WIDTH = 64, parameter DATA_BUF_ADDR_WIDTH = 4, parameter DATA_BUF_OFFSET_WIDTH = 1, parameter DATA_WIDTH = 64, parameter nCK_PER_CLK = 4 ) ( /*AUTOARG*/ // Outputs rd_merge_data, // Inputs clk, rst, rd_data_addr, rd_data_offset, wr_data_addr, wr_data_offset, rd_data, wr_ecc_buf ); input clk; input rst; // RMW architecture supports only 16 data buffer entries. // Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but // assume the upper bits are used for tagging. input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset; wire [4:0] buf_wr_addr; input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset; reg [4:0] buf_rd_addr_r; generate if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits always @(posedge clk) buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset}; assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset}; end else begin : lt_4_addr_bits always @(posedge clk) buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}}, wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0], wr_data_offset}; assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}}, rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0], rd_data_offset}; end endgenerate input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data; reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload; integer h; always @(/*AS*/rd_data) for (h=0; h<2*nCK_PER_CLK; h=h+1) payload[h*DATA_WIDTH+:DATA_WIDTH] = rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH]; input wr_ecc_buf; localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH; localparam FULL_RAM_CNT = (BUF_WIDTH/6); localparam REMAINDER = BUF_WIDTH % 6; localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); localparam RAM_WIDTH = (RAM_CNT*6); wire [RAM_WIDTH-1:0] buf_out_data; generate begin : ram_buf wire [RAM_WIDTH-1:0] buf_in_data; if (REMAINDER == 0) assign buf_in_data = payload; else assign buf_in_data = {{6-REMAINDER{1'b0}}, payload}; genvar i; for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(buf_out_data[((i*6)+4)+:2]), .DOB(buf_out_data[((i*6)+2)+:2]), .DOC(buf_out_data[((i*6)+0)+:2]), .DOD(), .DIA(buf_in_data[((i*6)+4)+:2]), .DIB(buf_in_data[((i*6)+2)+:2]), .DIC(buf_in_data[((i*6)+0)+:2]), .DID(2'b0), .ADDRA(buf_rd_addr_r), .ADDRB(buf_rd_addr_r), .ADDRC(buf_rd_addr_r), .ADDRD(buf_wr_addr), .WE(wr_ecc_buf), .WCLK(clk) ); end // block: rd_buffer_ram end endgenerate output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data; assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0]; endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ecc_buf.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ecc_buf #( parameter TCQ = 100, parameter PAYLOAD_WIDTH = 64, parameter DATA_BUF_ADDR_WIDTH = 4, parameter DATA_BUF_OFFSET_WIDTH = 1, parameter DATA_WIDTH = 64, parameter nCK_PER_CLK = 4 ) ( /*AUTOARG*/ // Outputs rd_merge_data, // Inputs clk, rst, rd_data_addr, rd_data_offset, wr_data_addr, wr_data_offset, rd_data, wr_ecc_buf ); input clk; input rst; // RMW architecture supports only 16 data buffer entries. // Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but // assume the upper bits are used for tagging. input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset; wire [4:0] buf_wr_addr; input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset; reg [4:0] buf_rd_addr_r; generate if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits always @(posedge clk) buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset}; assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset}; end else begin : lt_4_addr_bits always @(posedge clk) buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}}, wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0], wr_data_offset}; assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}}, rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0], rd_data_offset}; end endgenerate input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data; reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload; integer h; always @(/*AS*/rd_data) for (h=0; h<2*nCK_PER_CLK; h=h+1) payload[h*DATA_WIDTH+:DATA_WIDTH] = rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH]; input wr_ecc_buf; localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH; localparam FULL_RAM_CNT = (BUF_WIDTH/6); localparam REMAINDER = BUF_WIDTH % 6; localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); localparam RAM_WIDTH = (RAM_CNT*6); wire [RAM_WIDTH-1:0] buf_out_data; generate begin : ram_buf wire [RAM_WIDTH-1:0] buf_in_data; if (REMAINDER == 0) assign buf_in_data = payload; else assign buf_in_data = {{6-REMAINDER{1'b0}}, payload}; genvar i; for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(buf_out_data[((i*6)+4)+:2]), .DOB(buf_out_data[((i*6)+2)+:2]), .DOC(buf_out_data[((i*6)+0)+:2]), .DOD(), .DIA(buf_in_data[((i*6)+4)+:2]), .DIB(buf_in_data[((i*6)+2)+:2]), .DIC(buf_in_data[((i*6)+0)+:2]), .DID(2'b0), .ADDRA(buf_rd_addr_r), .ADDRB(buf_rd_addr_r), .ADDRC(buf_rd_addr_r), .ADDRD(buf_wr_addr), .WE(wr_ecc_buf), .WCLK(clk) ); end // block: rd_buffer_ram end endgenerate output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data; assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0]; endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2.0 // \ \ Application : MIG // / / Filename : mig_7series_v2_3_axi_fi_xor.v // /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $ // \ \ / \ Date Created : Tue Sept 21 2010 // \___\/\___\ // //***************************************************************************** /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v2_3_fi_xor # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // External Memory Data Width parameter integer DQ_WIDTH = 72, parameter integer DQS_WIDTH = 9, parameter integer nCK_PER_CLK = 4 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_in , output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_out , input wire wrdata_en , input wire [DQS_WIDTH-1:0] fi_xor_we , input wire [DQ_WIDTH-1:0] fi_xor_wrdata ); ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// reg [DQ_WIDTH-1:0] fi_xor_data = {DQ_WIDTH{1'b0}}; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// // Register in the fi_xor_wrdata on a byte width basis generate begin genvar i; for (i = 0; i < DQS_WIDTH; i = i + 1) begin : assign_fi_xor_data always @(posedge clk) begin if (wrdata_en) begin fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= {DQ_PER_DQS{1'b0}}; end else if (fi_xor_we[i]) begin fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_wrdata[i*DQ_PER_DQS+:DQ_PER_DQS]; end else begin fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS]; end end end end endgenerate assign wrdata_out[0+:DQ_WIDTH] = wrdata_in[0+:DQ_WIDTH] ^ fi_xor_data[0+:DQ_WIDTH]; // Pass through upper bits assign wrdata_out[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH] = wrdata_in[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH]; endmodule `default_nettype wire

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2.0 // \ \ Application : MIG // / / Filename : mig_7series_v2_3_axi_fi_xor.v // /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $ // \ \ / \ Date Created : Tue Sept 21 2010 // \___\/\___\ // //***************************************************************************** /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v2_3_fi_xor # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // External Memory Data Width parameter integer DQ_WIDTH = 72, parameter integer DQS_WIDTH = 9, parameter integer nCK_PER_CLK = 4 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_in , output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_out , input wire wrdata_en , input wire [DQS_WIDTH-1:0] fi_xor_we , input wire [DQ_WIDTH-1:0] fi_xor_wrdata ); ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// reg [DQ_WIDTH-1:0] fi_xor_data = {DQ_WIDTH{1'b0}}; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// // Register in the fi_xor_wrdata on a byte width basis generate begin genvar i; for (i = 0; i < DQS_WIDTH; i = i + 1) begin : assign_fi_xor_data always @(posedge clk) begin if (wrdata_en) begin fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= {DQ_PER_DQS{1'b0}}; end else if (fi_xor_we[i]) begin fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_wrdata[i*DQ_PER_DQS+:DQ_PER_DQS]; end else begin fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS]; end end end end endgenerate assign wrdata_out[0+:DQ_WIDTH] = wrdata_in[0+:DQ_WIDTH] ^ fi_xor_data[0+:DQ_WIDTH]; // Pass through upper bits assign wrdata_out[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH] = wrdata_in[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH]; endmodule `default_nettype wire

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 2.0 // \ \ Application : MIG // / / Filename : mig_7series_v2_3_axi_fi_xor.v // /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $ // \ \ / \ Date Created : Tue Sept 21 2010 // \___\/\___\ // //***************************************************************************** /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none module mig_7series_v2_3_fi_xor # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // External Memory Data Width parameter integer DQ_WIDTH = 72, parameter integer DQS_WIDTH = 9, parameter integer nCK_PER_CLK = 4 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_in , output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_out , input wire wrdata_en , input wire [DQS_WIDTH-1:0] fi_xor_we , input wire [DQ_WIDTH-1:0] fi_xor_wrdata ); ///////////////////////////////////////////////////////////////////////////// // Functions ///////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // Local parameters //////////////////////////////////////////////////////////////////////////////// localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH; //////////////////////////////////////////////////////////////////////////////// // Wires/Reg declarations //////////////////////////////////////////////////////////////////////////////// reg [DQ_WIDTH-1:0] fi_xor_data = {DQ_WIDTH{1'b0}}; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL /////////////////////////////////////////////////////////////////////////////// // Register in the fi_xor_wrdata on a byte width basis generate begin genvar i; for (i = 0; i < DQS_WIDTH; i = i + 1) begin : assign_fi_xor_data always @(posedge clk) begin if (wrdata_en) begin fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= {DQ_PER_DQS{1'b0}}; end else if (fi_xor_we[i]) begin fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_wrdata[i*DQ_PER_DQS+:DQ_PER_DQS]; end else begin fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS]; end end end end endgenerate assign wrdata_out[0+:DQ_WIDTH] = wrdata_in[0+:DQ_WIDTH] ^ fi_xor_data[0+:DQ_WIDTH]; // Pass through upper bits assign wrdata_out[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH] = wrdata_in[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH]; endmodule `default_nettype wire

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : mc.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** //***************************************************************************** // Top level memory sequencer structural block. This block // instantiates the rank, bank, and column machines. //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_mc # ( parameter TCQ = 100, // clk->out delay(sim only) parameter ADDR_CMD_MODE = "1T", // registered or // 1Tfered mem? parameter BANK_WIDTH = 3, // bank address width parameter BM_CNT_WIDTH = 2, // # BM counter width // i.e., log2(nBANK_MACHS) parameter BURST_MODE = "8", // Burst length parameter CL = 5, // Read CAS latency // (in clk cyc) parameter CMD_PIPE_PLUS1 = "ON", // add register stage // between MC and PHY parameter COL_WIDTH = 12, // column address width parameter CS_WIDTH = 4, // # of unique CS outputs parameter CWL = 5, // Write CAS latency // (in clk cyc) parameter DATA_BUF_ADDR_WIDTH = 8, // User request tag (e.g. // user src/dest buf addr) parameter DATA_BUF_OFFSET_WIDTH = 1, // User buffer offset width parameter DATA_WIDTH = 64, // Data bus width parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_TYPE = "DDR3", // Memory I/F type: // "DDR3", "DDR2" parameter ECC = "OFF", // ECC ON/OFF? parameter ECC_WIDTH = 8, // # of ECC bits parameter MAINT_PRESCALER_PERIOD= 200000, // maintenance period (ps) parameter MC_ERR_ADDR_WIDTH = 31, // # of error address bits parameter nBANK_MACHS = 4, // # of bank machines (BM) parameter nCK_PER_CLK = 4, // DRAM clock : MC clock // frequency ratio parameter nCS_PER_RANK = 1, // # of unique CS outputs // per rank parameter nREFRESH_BANK = 1, // # of REF cmds to pull-in parameter nSLOTS = 1, // # DIMM slots in system parameter ORDERING = "NORM", // request ordering mode parameter PAYLOAD_WIDTH = 64, // Width of data payload // from PHY parameter RANK_WIDTH = 2, // # of bits to count ranks parameter RANKS = 4, // # of ranks of DRAM parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter ROW_WIDTH = 16, // row address width parameter RTT_NOM = "40", // Nominal ODT value parameter RTT_WR = "120", // Write ODT value parameter SLOT_0_CONFIG = 8'b0000_0101, // ranks allowed in slot 0 parameter SLOT_1_CONFIG = 8'b0000_1010, // ranks allowed in slot 1 parameter STARVE_LIMIT = 2, // max # of times a user // request is allowed to // lose arbitration when // reordering is enabled parameter tCK = 2500, // memory clk period(ps) parameter tCKE = 10000, // CKE minimum pulse (ps) parameter tFAW = 40000, // four activate window(ps) parameter tRAS = 37500, // ACT->PRE cmd period (ps) parameter tRCD = 12500, // ACT->R/W delay (ps) parameter tREFI = 7800000, // average periodic // refresh interval(ps) parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal parameter tRFC = 110000, // REF->ACT/REF delay (ps) parameter tRP = 12500, // PRE cmd period (ps) parameter tRRD = 10000, // ACT->ACT period (ps) parameter tRTP = 7500, // Read->PRE cmd delay (ps) parameter tWTR = 7500, // Internal write->read // delay (ps) // requiring DLL lock (CKs) parameter tZQCS = 64, // ZQCS cmd period (CKs) parameter tZQI = 128_000_000, // ZQCS interval (ps) parameter tPRDI = 1_000_000, // pS parameter USER_REFRESH = "OFF" // Whether user manages REF ) ( // System inputs input clk, input rst, // Physical memory slot presence input [7:0] slot_0_present, input [7:0] slot_1_present, // Native Interface input [2:0] cmd, input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr, input hi_priority, input size, input [BANK_WIDTH-1:0] bank, input [COL_WIDTH-1:0] col, input [RANK_WIDTH-1:0] rank, input [ROW_WIDTH-1:0] row, input use_addr, input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data, input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask, output accept, output accept_ns, output [BM_CNT_WIDTH-1:0] bank_mach_next, output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data, output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, output rd_data_en, output rd_data_end, output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset, output reg [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr /* synthesis syn_maxfan = 30 */, output reg wr_data_en, output reg [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset /* synthesis syn_maxfan = 30 */, output mc_read_idle, output mc_ref_zq_wip, // ECC interface input correct_en, input [2*nCK_PER_CLK-1:0] raw_not_ecc, input [DQS_WIDTH - 1:0] fi_xor_we, input [DQ_WIDTH -1 :0 ] fi_xor_wrdata, output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr, output [2*nCK_PER_CLK-1:0] ecc_single, output [2*nCK_PER_CLK-1:0] ecc_multiple, // User maintenance requests input app_periodic_rd_req, input app_ref_req, input app_zq_req, input app_sr_req, output app_sr_active, output app_ref_ack, output app_zq_ack, // MC <==> PHY Interface output reg [nCK_PER_CLK-1:0] mc_ras_n, output reg [nCK_PER_CLK-1:0] mc_cas_n, output reg [nCK_PER_CLK-1:0] mc_we_n, output reg [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, output reg [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, output reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, output reg [1:0] mc_odt, output reg [nCK_PER_CLK-1:0] mc_cke, output wire mc_reset_n, output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata, output wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0]mc_wrdata_mask, output reg mc_wrdata_en, output wire mc_cmd_wren, output wire mc_ctl_wren, output reg [2:0] mc_cmd, output reg [5:0] mc_data_offset, output reg [5:0] mc_data_offset_1, output reg [5:0] mc_data_offset_2, output reg [1:0] mc_cas_slot, output reg [3:0] mc_aux_out0, output reg [3:0] mc_aux_out1, output reg [1:0] mc_rank_cnt, input phy_mc_ctl_full, input phy_mc_cmd_full, input phy_mc_data_full, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data, input phy_rddata_valid, input init_calib_complete, input [6*RANKS-1:0] calib_rd_data_offset, input [6*RANKS-1:0] calib_rd_data_offset_1, input [6*RANKS-1:0] calib_rd_data_offset_2 ); assign mc_reset_n = 1'b1; // never reset memory assign mc_cmd_wren = 1'b1; // always write CMD FIFO(issue DSEL when idle) assign mc_ctl_wren = 1'b1; // always write CTL FIFO(issue nondata when idle) // Ensure there is always at least one rank present during operation `ifdef MC_SVA ranks_present: assert property (@(posedge clk) (rst || (|(slot_0_present | slot_1_present)))); `endif // Reserved. Do not change. localparam nPHY_WRLAT = 2; // always delay write data control unless ECC mode is enabled localparam DELAY_WR_DATA_CNTRL = ECC == "ON" ? 0 : 1; // Ensure that write control is delayed for appropriate CWL /*`ifdef MC_SVA delay_wr_data_zero_CWL_le_6: assert property (@(posedge clk) ((CWL > 6) || (DELAY_WR_DATA_CNTRL == 0))); `endif*/ // Never retrieve WR_DATA_ADDR early localparam EARLY_WR_DATA_ADDR = "OFF"; //*************************************************************************** // Convert timing parameters from time to clock cycles //*************************************************************************** localparam nCKE = cdiv(tCKE, tCK); localparam nRP = cdiv(tRP, tCK); localparam nRCD = cdiv(tRCD, tCK); localparam nRAS = cdiv(tRAS, tCK); localparam nFAW = cdiv(tFAW, tCK); localparam nRFC = cdiv(tRFC, tCK); // Convert tWR. As per specification, write recover for autoprecharge // cycles doesn't support values of 9 and 11. Round up 9 to 10 and 11 to 12 localparam nWR_CK = cdiv(15000, tCK) ; localparam nWR = (nWR_CK == 9) ? 10 : (nWR_CK == 11) ? 12 : nWR_CK; // tRRD, tWTR at tRTP have a 4 cycle floor in DDR3 and 2 cycle floor in DDR2 localparam nRRD_CK = cdiv(tRRD, tCK); localparam nRRD = (DRAM_TYPE == "DDR3") ? (nRRD_CK < 4) ? 4 : nRRD_CK : (nRRD_CK < 2) ? 2 : nRRD_CK; localparam nWTR_CK = cdiv(tWTR, tCK); localparam nWTR = (DRAM_TYPE == "DDR3") ? (nWTR_CK < 4) ? 4 : nWTR_CK : (nWTR_CK < 2) ? 2 : nWTR_CK; localparam nRTP_CK = cdiv(tRTP, tCK); localparam nRTP = (DRAM_TYPE == "DDR3") ? (nRTP_CK < 4) ? 4 : nRTP_CK : (nRTP_CK < 2) ? 2 : nRTP_CK; // Add a cycle to CL/CWL for the register in RDIMM devices localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; localparam CL_M = (REG_CTRL == "ON") ? CL + 1 : CL; // Tuneable delay between read and write data on the DQ bus localparam DQRD2DQWR_DLY = 4; // CKE minimum pulse width for self-refresh (SRE->SRX minimum time) localparam nCKESR = nCKE + 1; // Delay from SRE to command requiring locked DLL. Currently fixed at 512 for // all devices per JEDEC spec. localparam tXSDLL = 512; //*************************************************************************** // Set up maintenance counter dividers //*************************************************************************** // CK clock divisor to generate maintenance prescaler period (round down) localparam MAINT_PRESCALER_DIV = MAINT_PRESCALER_PERIOD / (tCK*nCK_PER_CLK); // Maintenance prescaler divisor for refresh timer. Essentially, this is // just (tREFI / MAINT_PRESCALER_PERIOD), but we must account for the worst // case delay from the time we get a tick from the refresh counter to the // time that we can actually issue the REF command. Thus, subtract tRCD, CL, // data burst time and tRP for each implemented bank machine to ensure that // all transactions can complete before tREFI expires localparam REFRESH_TIMER_DIV = USER_REFRESH == "ON" ? 0 : (tREFI-((tRCD+((CL+4)*tCK)+tRP)*nBANK_MACHS)) / MAINT_PRESCALER_PERIOD; // Periodic read (RESERVED - not currently required or supported in 7 series) // tPRDI should only be set to 0 // localparam tPRDI = 0; // Do NOT change. localparam PERIODIC_RD_TIMER_DIV = tPRDI / MAINT_PRESCALER_PERIOD; // Convert maintenance prescaler from ps to ns localparam MAINT_PRESCALER_PERIOD_NS = MAINT_PRESCALER_PERIOD / 1000; // Maintenance prescaler divisor for ZQ calibration (ZQCS) timer localparam ZQ_TIMER_DIV = tZQI / MAINT_PRESCALER_PERIOD_NS; // Bus width required to broadcast a single bit rank signal among all the // bank machines - 1 bit per rank, per bank localparam RANK_BM_BV_WIDTH = nBANK_MACHS * RANKS; //*************************************************************************** // Define 2T, CWL-even mode to enable multi-fabric-cycle 2T commands //*************************************************************************** localparam EVEN_CWL_2T_MODE = ((ADDR_CMD_MODE == "2T") && (!(CWL % 2))) ? "ON" : "OFF"; //*************************************************************************** // Reserved feature control. //*************************************************************************** // Open page wait mode is reserved. // nOP_WAIT is the number of states a bank machine will park itself // on an otherwise inactive open page before closing the page. If // nOP_WAIT == 0, open page wait mode is disabled. If nOP_WAIT == -1, // the bank machine will remain parked until the pool of idle bank machines // are less than LOW_IDLE_CNT. At which point parked bank machines // are selected to exit until the number of idle bank machines exceeds the // LOW_IDLE_CNT. localparam nOP_WAIT = 0; // Open page mode localparam LOW_IDLE_CNT = 0; // Low idle bank machine threshold //*************************************************************************** // Internal wires //*************************************************************************** wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; wire [ROW_WIDTH-1:0] col_a; wire [BANK_WIDTH-1:0] col_ba; wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr; wire col_periodic_rd; wire [RANK_WIDTH-1:0] col_ra; wire col_rmw; wire col_rd_wr; wire [ROW_WIDTH-1:0] col_row; wire col_size; wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr; wire dq_busy_data; wire ecc_status_valid; wire [RANKS-1:0] inhbt_act_faw_r; wire [RANKS-1:0] inhbt_rd; wire [RANKS-1:0] inhbt_wr; wire insert_maint_r1; wire [RANK_WIDTH-1:0] maint_rank_r; wire maint_req_r; wire maint_wip_r; wire maint_zq_r; wire maint_sre_r; wire maint_srx_r; wire periodic_rd_ack_r; wire periodic_rd_r; wire [RANK_WIDTH-1:0] periodic_rd_rank_r; wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; wire rd_rmw; wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; wire [nBANK_MACHS-1:0] sending_col; wire [nBANK_MACHS-1:0] sending_row; wire sent_col; wire sent_col_r; wire wr_ecc_buf; wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // MC/PHY optional pipeline stage support wire [nCK_PER_CLK-1:0] mc_ras_n_ns; wire [nCK_PER_CLK-1:0] mc_cas_n_ns; wire [nCK_PER_CLK-1:0] mc_we_n_ns; wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address_ns; wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank_ns; wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_ns; wire [1:0] mc_odt_ns; wire [nCK_PER_CLK-1:0] mc_cke_ns; wire [3:0] mc_aux_out0_ns; wire [3:0] mc_aux_out1_ns; wire [1:0] mc_rank_cnt_ns = col_ra; wire [2:0] mc_cmd_ns; wire [5:0] mc_data_offset_ns; wire [5:0] mc_data_offset_1_ns; wire [5:0] mc_data_offset_2_ns; wire [1:0] mc_cas_slot_ns; wire mc_wrdata_en_ns; wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr_ns; wire wr_data_en_ns; wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset_ns; integer i; // MC Read idle support wire col_read_fifo_empty; wire mc_read_idle_ns; reg mc_read_idle_r; // MC Maintenance in progress with bus idle indication wire maint_ref_zq_wip; wire mc_ref_zq_wip_ns; reg mc_ref_zq_wip_r; //*************************************************************************** // Function cdiv // Description: // This function performs ceiling division (divide and round-up) // Inputs: // num: integer to be divided // div: divisor // Outputs: // cdiv: result of ceiling division (num/div, rounded up) //*************************************************************************** function integer cdiv (input integer num, input integer div); begin // perform division, then add 1 if and only if remainder is non-zero cdiv = (num/div) + (((num%div)>0) ? 1 : 0); end endfunction // cdiv //*************************************************************************** // Optional pipeline register stage on MC/PHY interface //*************************************************************************** generate if (CMD_PIPE_PLUS1 == "ON") begin : cmd_pipe_plus // register interface always @(posedge clk) begin mc_address <= #TCQ mc_address_ns; mc_bank <= #TCQ mc_bank_ns; mc_cas_n <= #TCQ mc_cas_n_ns; mc_cs_n <= #TCQ mc_cs_n_ns; mc_odt <= #TCQ mc_odt_ns; mc_cke <= #TCQ mc_cke_ns; mc_aux_out0 <= #TCQ mc_aux_out0_ns; mc_aux_out1 <= #TCQ mc_aux_out1_ns; mc_cmd <= #TCQ mc_cmd_ns; mc_ras_n <= #TCQ mc_ras_n_ns; mc_we_n <= #TCQ mc_we_n_ns; mc_data_offset <= #TCQ mc_data_offset_ns; mc_data_offset_1 <= #TCQ mc_data_offset_1_ns; mc_data_offset_2 <= #TCQ mc_data_offset_2_ns; mc_cas_slot <= #TCQ mc_cas_slot_ns; mc_wrdata_en <= #TCQ mc_wrdata_en_ns; mc_rank_cnt <= #TCQ mc_rank_cnt_ns; wr_data_addr <= #TCQ wr_data_addr_ns; wr_data_en <= #TCQ wr_data_en_ns; wr_data_offset <= #TCQ wr_data_offset_ns; end // always @ (posedge clk) end // block: cmd_pipe_plus else begin : cmd_pipe_plus0 // don't register interface always @( mc_address_ns or mc_aux_out0_ns or mc_aux_out1_ns or mc_bank_ns or mc_cas_n_ns or mc_cmd_ns or mc_cs_n_ns or mc_odt_ns or mc_cke_ns or mc_data_offset_ns or mc_data_offset_1_ns or mc_data_offset_2_ns or mc_rank_cnt_ns or mc_ras_n_ns or mc_we_n_ns or mc_wrdata_en_ns or wr_data_addr_ns or wr_data_en_ns or wr_data_offset_ns or mc_cas_slot_ns) begin mc_address = #TCQ mc_address_ns; mc_bank = #TCQ mc_bank_ns; mc_cas_n = #TCQ mc_cas_n_ns; mc_cs_n = #TCQ mc_cs_n_ns; mc_odt = #TCQ mc_odt_ns; mc_cke = #TCQ mc_cke_ns; mc_aux_out0 = #TCQ mc_aux_out0_ns; mc_aux_out1 = #TCQ mc_aux_out1_ns; mc_cmd = #TCQ mc_cmd_ns; mc_ras_n = #TCQ mc_ras_n_ns; mc_we_n = #TCQ mc_we_n_ns; mc_data_offset = #TCQ mc_data_offset_ns; mc_data_offset_1 = #TCQ mc_data_offset_1_ns; mc_data_offset_2 = #TCQ mc_data_offset_2_ns; mc_cas_slot = #TCQ mc_cas_slot_ns; mc_wrdata_en = #TCQ mc_wrdata_en_ns; mc_rank_cnt = #TCQ mc_rank_cnt_ns; wr_data_addr = #TCQ wr_data_addr_ns; wr_data_en = #TCQ wr_data_en_ns; wr_data_offset = #TCQ wr_data_offset_ns; end // always @ (... end // block: cmd_pipe_plus0 endgenerate //*************************************************************************** // Indicate when there are no pending reads so that input features can be // powered down //*************************************************************************** assign mc_read_idle_ns = col_read_fifo_empty & init_calib_complete; always @(posedge clk) mc_read_idle_r <= #TCQ mc_read_idle_ns; assign mc_read_idle = mc_read_idle_r; //*************************************************************************** // Indicate when there is a refresh in progress and the bus is idle so that // tap adjustments can be made //*************************************************************************** assign mc_ref_zq_wip_ns = maint_ref_zq_wip && col_read_fifo_empty; always @(posedge clk) mc_ref_zq_wip_r <= mc_ref_zq_wip_ns; assign mc_ref_zq_wip = mc_ref_zq_wip_r; //*************************************************************************** // Manage rank-level timing and maintanence //*************************************************************************** mig_7series_v2_3_rank_mach # ( // Parameters .BURST_MODE (BURST_MODE), .CL (CL), .CWL (CWL), .CS_WIDTH (CS_WIDTH), .DQRD2DQWR_DLY (DQRD2DQWR_DLY), .DRAM_TYPE (DRAM_TYPE), .MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV), .nBANK_MACHS (nBANK_MACHS), .nCKESR (nCKESR), .nCK_PER_CLK (nCK_PER_CLK), .nFAW (nFAW), .nREFRESH_BANK (nREFRESH_BANK), .nRRD (nRRD), .nWTR (nWTR), .PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV), .RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .REFRESH_TIMER_DIV (REFRESH_TIMER_DIV), .ZQ_TIMER_DIV (ZQ_TIMER_DIV) ) rank_mach0 ( // Outputs .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), .inhbt_rd (inhbt_rd[RANKS-1:0]), .inhbt_wr (inhbt_wr[RANKS-1:0]), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .maint_ref_zq_wip (maint_ref_zq_wip), .periodic_rd_r (periodic_rd_r), .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), // Inputs .act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .app_periodic_rd_req (app_periodic_rd_req), .app_ref_req (app_ref_req), .app_ref_ack (app_ref_ack), .app_zq_req (app_zq_req), .app_zq_ack (app_zq_ack), .app_sr_req (app_sr_req), .app_sr_active (app_sr_active), .col_rd_wr (col_rd_wr), .clk (clk), .init_calib_complete (init_calib_complete), .insert_maint_r1 (insert_maint_r1), .maint_wip_r (maint_wip_r), .periodic_rd_ack_r (periodic_rd_ack_r), .rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]), .rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .rst (rst), .sending_col (sending_col[nBANK_MACHS-1:0]), .sending_row (sending_row[nBANK_MACHS-1:0]), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0]), .wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]) ); //*************************************************************************** // Manage requests, reordering and bank timing //*************************************************************************** mig_7series_v2_3_bank_mach # ( // Parameters .TCQ (TCQ), .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_WIDTH (BANK_WIDTH), .BM_CNT_WIDTH (BM_CNT_WIDTH), .BURST_MODE (BURST_MODE), .COL_WIDTH (COL_WIDTH), .CS_WIDTH (CS_WIDTH), .CL (CL_M), .CWL (CWL_M), .CKE_ODT_AUX (CKE_ODT_AUX), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .LOW_IDLE_CNT (LOW_IDLE_CNT), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nCS_PER_RANK (nCS_PER_RANK), .nOP_WAIT (nOP_WAIT), .nRAS (nRAS), .nRCD (nRCD), .nRFC (nRFC), .nRP (nRP), .nRTP (nRTP), .nSLOTS (nSLOTS), .nWR (nWR), .nXSDLL (tXSDLL), .ORDERING (ORDERING), .RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .ROW_WIDTH (ROW_WIDTH), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG), .STARVE_LIMIT (STARVE_LIMIT), .tZQCS (tZQCS) ) bank_mach0 ( // Outputs .accept (accept), .accept_ns (accept_ns), .act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]), .col_a (col_a[ROW_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_row (col_row[ROW_WIDTH-1:0]), .col_size (col_size), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .mc_bank (mc_bank_ns), .mc_address (mc_address_ns), .mc_ras_n (mc_ras_n_ns), .mc_cas_n (mc_cas_n_ns), .mc_we_n (mc_we_n_ns), .mc_cs_n (mc_cs_n_ns), .mc_odt (mc_odt_ns), .mc_cke (mc_cke_ns), .mc_aux_out0 (mc_aux_out0_ns), .mc_aux_out1 (mc_aux_out1_ns), .mc_cmd (mc_cmd_ns), .mc_data_offset (mc_data_offset_ns), .mc_data_offset_1 (mc_data_offset_1_ns), .mc_data_offset_2 (mc_data_offset_2_ns), .mc_cas_slot (mc_cas_slot_ns), .insert_maint_r1 (insert_maint_r1), .maint_wip_r (maint_wip_r), .periodic_rd_ack_r (periodic_rd_ack_r), .rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]), .rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .sending_row (sending_row[nBANK_MACHS-1:0]), .sending_col (sending_col[nBANK_MACHS-1:0]), .sent_col (sent_col), .sent_col_r (sent_col_r), .wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]), // Inputs .bank (bank[BANK_WIDTH-1:0]), .calib_rddata_offset (calib_rd_data_offset), .calib_rddata_offset_1 (calib_rd_data_offset_1), .calib_rddata_offset_2 (calib_rd_data_offset_2), .clk (clk), .cmd (cmd[2:0]), .col (col[COL_WIDTH-1:0]), .data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .init_calib_complete (init_calib_complete), .phy_rddata_valid (phy_rddata_valid), .dq_busy_data (dq_busy_data), .hi_priority (hi_priority), .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), .inhbt_rd (inhbt_rd[RANKS-1:0]), .inhbt_wr (inhbt_wr[RANKS-1:0]), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .periodic_rd_r (periodic_rd_r), .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), .phy_mc_cmd_full (phy_mc_cmd_full), .phy_mc_ctl_full (phy_mc_ctl_full), .phy_mc_data_full (phy_mc_data_full), .rank (rank[RANK_WIDTH-1:0]), .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), .rd_rmw (rd_rmw), .row (row[ROW_WIDTH-1:0]), .rst (rst), .size (size), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0]), .use_addr (use_addr) ); //*************************************************************************** // Manage DQ bus //*************************************************************************** mig_7series_v2_3_col_mach # ( // Parameters .TCQ (TCQ), .BANK_WIDTH (BANK_WIDTH), .BURST_MODE (BURST_MODE), .COL_WIDTH (COL_WIDTH), .CS_WIDTH (CS_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH), .DELAY_WR_DATA_CNTRL (DELAY_WR_DATA_CNTRL), .DQS_WIDTH (DQS_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH), .nCK_PER_CLK (nCK_PER_CLK), .nPHY_WRLAT (nPHY_WRLAT), .RANK_WIDTH (RANK_WIDTH), .ROW_WIDTH (ROW_WIDTH) ) col_mach0 ( // Outputs .mc_wrdata_en (mc_wrdata_en_ns), .dq_busy_data (dq_busy_data), .ecc_err_addr (ecc_err_addr[MC_ERR_ADDR_WIDTH-1:0]), .ecc_status_valid (ecc_status_valid), .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), .rd_data_en (rd_data_en), .rd_data_end (rd_data_end), .rd_data_offset (rd_data_offset), .rd_rmw (rd_rmw), .wr_data_addr (wr_data_addr_ns), .wr_data_en (wr_data_en_ns), .wr_data_offset (wr_data_offset_ns), .wr_ecc_buf (wr_ecc_buf), .col_read_fifo_empty (col_read_fifo_empty), // Inputs .clk (clk), .rst (rst), .col_a (col_a[ROW_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_row (col_row[ROW_WIDTH-1:0]), .col_size (col_size), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .phy_rddata_valid (phy_rddata_valid), .sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col) ); //*************************************************************************** // Implement ECC //*************************************************************************** // Total ECC word length = ECC code width + Data width localparam CODE_WIDTH = DATA_WIDTH + ECC_WIDTH; generate if (ECC == "OFF") begin : ecc_off assign rd_data = phy_rd_data; assign mc_wrdata = wr_data; assign mc_wrdata_mask = wr_data_mask; assign ecc_single = 4'b0; assign ecc_multiple = 4'b0; end else begin : ecc_on wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data; wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_i; // Merge and encode mig_7series_v2_3_ecc_merge_enc # ( // Parameters .TCQ (TCQ), .CODE_WIDTH (CODE_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .DQ_WIDTH (DQ_WIDTH), .ECC_WIDTH (ECC_WIDTH), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) ecc_merge_enc0 ( // Outputs .mc_wrdata (mc_wrdata_i), .mc_wrdata_mask (mc_wrdata_mask), // Inputs .clk (clk), .rst (rst), .h_rows (h_rows), .rd_merge_data (rd_merge_data), .raw_not_ecc (raw_not_ecc), .wr_data (wr_data), .wr_data_mask (wr_data_mask) ); // Decode and fix mig_7series_v2_3_ecc_dec_fix # ( // Parameters .TCQ (TCQ), .CODE_WIDTH (CODE_WIDTH), .DATA_WIDTH (DATA_WIDTH), .DQ_WIDTH (DQ_WIDTH), .ECC_WIDTH (ECC_WIDTH), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) ecc_dec_fix0 ( // Outputs .ecc_multiple (ecc_multiple), .ecc_single (ecc_single), .rd_data (rd_data), // Inputs .clk (clk), .rst (rst), .correct_en (correct_en), .phy_rddata (phy_rd_data), .ecc_status_valid (ecc_status_valid), .h_rows (h_rows) ); // ECC Buffer mig_7series_v2_3_ecc_buf # ( // Parameters .TCQ (TCQ), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH), .DATA_WIDTH (DATA_WIDTH), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) ecc_buf0 ( // Outputs .rd_merge_data (rd_merge_data), // Inputs .clk (clk), .rst (rst), .rd_data (rd_data), .rd_data_addr (rd_data_addr), .rd_data_offset (rd_data_offset), .wr_data_addr (wr_data_addr), .wr_data_offset (wr_data_offset), .wr_ecc_buf (wr_ecc_buf) ); // Generate ECC table mig_7series_v2_3_ecc_gen # ( // Parameters .CODE_WIDTH (CODE_WIDTH), .DATA_WIDTH (DATA_WIDTH), .ECC_WIDTH (ECC_WIDTH) ) ecc_gen0 ( // Outputs .h_rows (h_rows) ); if (ECC == "ON") begin : gen_fi_xor_inst reg mc_wrdata_en_r; wire mc_wrdata_en_i; always @(posedge clk) begin mc_wrdata_en_r <= mc_wrdata_en; end assign mc_wrdata_en_i = mc_wrdata_en_r; mig_7series_v2_3_fi_xor #( .DQ_WIDTH (DQ_WIDTH), .DQS_WIDTH (DQS_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) fi_xor0 ( .clk (clk), .wrdata_in (mc_wrdata_i), .wrdata_out (mc_wrdata), .wrdata_en (mc_wrdata_en_i), .fi_xor_we (fi_xor_we), .fi_xor_wrdata (fi_xor_wrdata) ); end else begin : gen_wrdata_passthru assign mc_wrdata = mc_wrdata_i; end `ifdef DISPLAY_H_MATRIX integer i; always @(negedge rst) begin $display ("**********************************************"); $display ("H Matrix:"); for (i=0; i<ECC_WIDTH; i=i+1) $display ("%b", h_rows[i*CODE_WIDTH+:CODE_WIDTH]); $display ("**********************************************"); end `endif end endgenerate endmodule // mc

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : mc.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** //***************************************************************************** // Top level memory sequencer structural block. This block // instantiates the rank, bank, and column machines. //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_mc # ( parameter TCQ = 100, // clk->out delay(sim only) parameter ADDR_CMD_MODE = "1T", // registered or // 1Tfered mem? parameter BANK_WIDTH = 3, // bank address width parameter BM_CNT_WIDTH = 2, // # BM counter width // i.e., log2(nBANK_MACHS) parameter BURST_MODE = "8", // Burst length parameter CL = 5, // Read CAS latency // (in clk cyc) parameter CMD_PIPE_PLUS1 = "ON", // add register stage // between MC and PHY parameter COL_WIDTH = 12, // column address width parameter CS_WIDTH = 4, // # of unique CS outputs parameter CWL = 5, // Write CAS latency // (in clk cyc) parameter DATA_BUF_ADDR_WIDTH = 8, // User request tag (e.g. // user src/dest buf addr) parameter DATA_BUF_OFFSET_WIDTH = 1, // User buffer offset width parameter DATA_WIDTH = 64, // Data bus width parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_TYPE = "DDR3", // Memory I/F type: // "DDR3", "DDR2" parameter ECC = "OFF", // ECC ON/OFF? parameter ECC_WIDTH = 8, // # of ECC bits parameter MAINT_PRESCALER_PERIOD= 200000, // maintenance period (ps) parameter MC_ERR_ADDR_WIDTH = 31, // # of error address bits parameter nBANK_MACHS = 4, // # of bank machines (BM) parameter nCK_PER_CLK = 4, // DRAM clock : MC clock // frequency ratio parameter nCS_PER_RANK = 1, // # of unique CS outputs // per rank parameter nREFRESH_BANK = 1, // # of REF cmds to pull-in parameter nSLOTS = 1, // # DIMM slots in system parameter ORDERING = "NORM", // request ordering mode parameter PAYLOAD_WIDTH = 64, // Width of data payload // from PHY parameter RANK_WIDTH = 2, // # of bits to count ranks parameter RANKS = 4, // # of ranks of DRAM parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter ROW_WIDTH = 16, // row address width parameter RTT_NOM = "40", // Nominal ODT value parameter RTT_WR = "120", // Write ODT value parameter SLOT_0_CONFIG = 8'b0000_0101, // ranks allowed in slot 0 parameter SLOT_1_CONFIG = 8'b0000_1010, // ranks allowed in slot 1 parameter STARVE_LIMIT = 2, // max # of times a user // request is allowed to // lose arbitration when // reordering is enabled parameter tCK = 2500, // memory clk period(ps) parameter tCKE = 10000, // CKE minimum pulse (ps) parameter tFAW = 40000, // four activate window(ps) parameter tRAS = 37500, // ACT->PRE cmd period (ps) parameter tRCD = 12500, // ACT->R/W delay (ps) parameter tREFI = 7800000, // average periodic // refresh interval(ps) parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal parameter tRFC = 110000, // REF->ACT/REF delay (ps) parameter tRP = 12500, // PRE cmd period (ps) parameter tRRD = 10000, // ACT->ACT period (ps) parameter tRTP = 7500, // Read->PRE cmd delay (ps) parameter tWTR = 7500, // Internal write->read // delay (ps) // requiring DLL lock (CKs) parameter tZQCS = 64, // ZQCS cmd period (CKs) parameter tZQI = 128_000_000, // ZQCS interval (ps) parameter tPRDI = 1_000_000, // pS parameter USER_REFRESH = "OFF" // Whether user manages REF ) ( // System inputs input clk, input rst, // Physical memory slot presence input [7:0] slot_0_present, input [7:0] slot_1_present, // Native Interface input [2:0] cmd, input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr, input hi_priority, input size, input [BANK_WIDTH-1:0] bank, input [COL_WIDTH-1:0] col, input [RANK_WIDTH-1:0] rank, input [ROW_WIDTH-1:0] row, input use_addr, input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data, input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask, output accept, output accept_ns, output [BM_CNT_WIDTH-1:0] bank_mach_next, output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data, output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, output rd_data_en, output rd_data_end, output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset, output reg [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr /* synthesis syn_maxfan = 30 */, output reg wr_data_en, output reg [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset /* synthesis syn_maxfan = 30 */, output mc_read_idle, output mc_ref_zq_wip, // ECC interface input correct_en, input [2*nCK_PER_CLK-1:0] raw_not_ecc, input [DQS_WIDTH - 1:0] fi_xor_we, input [DQ_WIDTH -1 :0 ] fi_xor_wrdata, output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr, output [2*nCK_PER_CLK-1:0] ecc_single, output [2*nCK_PER_CLK-1:0] ecc_multiple, // User maintenance requests input app_periodic_rd_req, input app_ref_req, input app_zq_req, input app_sr_req, output app_sr_active, output app_ref_ack, output app_zq_ack, // MC <==> PHY Interface output reg [nCK_PER_CLK-1:0] mc_ras_n, output reg [nCK_PER_CLK-1:0] mc_cas_n, output reg [nCK_PER_CLK-1:0] mc_we_n, output reg [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, output reg [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, output reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, output reg [1:0] mc_odt, output reg [nCK_PER_CLK-1:0] mc_cke, output wire mc_reset_n, output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata, output wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0]mc_wrdata_mask, output reg mc_wrdata_en, output wire mc_cmd_wren, output wire mc_ctl_wren, output reg [2:0] mc_cmd, output reg [5:0] mc_data_offset, output reg [5:0] mc_data_offset_1, output reg [5:0] mc_data_offset_2, output reg [1:0] mc_cas_slot, output reg [3:0] mc_aux_out0, output reg [3:0] mc_aux_out1, output reg [1:0] mc_rank_cnt, input phy_mc_ctl_full, input phy_mc_cmd_full, input phy_mc_data_full, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data, input phy_rddata_valid, input init_calib_complete, input [6*RANKS-1:0] calib_rd_data_offset, input [6*RANKS-1:0] calib_rd_data_offset_1, input [6*RANKS-1:0] calib_rd_data_offset_2 ); assign mc_reset_n = 1'b1; // never reset memory assign mc_cmd_wren = 1'b1; // always write CMD FIFO(issue DSEL when idle) assign mc_ctl_wren = 1'b1; // always write CTL FIFO(issue nondata when idle) // Ensure there is always at least one rank present during operation `ifdef MC_SVA ranks_present: assert property (@(posedge clk) (rst || (|(slot_0_present | slot_1_present)))); `endif // Reserved. Do not change. localparam nPHY_WRLAT = 2; // always delay write data control unless ECC mode is enabled localparam DELAY_WR_DATA_CNTRL = ECC == "ON" ? 0 : 1; // Ensure that write control is delayed for appropriate CWL /*`ifdef MC_SVA delay_wr_data_zero_CWL_le_6: assert property (@(posedge clk) ((CWL > 6) || (DELAY_WR_DATA_CNTRL == 0))); `endif*/ // Never retrieve WR_DATA_ADDR early localparam EARLY_WR_DATA_ADDR = "OFF"; //*************************************************************************** // Convert timing parameters from time to clock cycles //*************************************************************************** localparam nCKE = cdiv(tCKE, tCK); localparam nRP = cdiv(tRP, tCK); localparam nRCD = cdiv(tRCD, tCK); localparam nRAS = cdiv(tRAS, tCK); localparam nFAW = cdiv(tFAW, tCK); localparam nRFC = cdiv(tRFC, tCK); // Convert tWR. As per specification, write recover for autoprecharge // cycles doesn't support values of 9 and 11. Round up 9 to 10 and 11 to 12 localparam nWR_CK = cdiv(15000, tCK) ; localparam nWR = (nWR_CK == 9) ? 10 : (nWR_CK == 11) ? 12 : nWR_CK; // tRRD, tWTR at tRTP have a 4 cycle floor in DDR3 and 2 cycle floor in DDR2 localparam nRRD_CK = cdiv(tRRD, tCK); localparam nRRD = (DRAM_TYPE == "DDR3") ? (nRRD_CK < 4) ? 4 : nRRD_CK : (nRRD_CK < 2) ? 2 : nRRD_CK; localparam nWTR_CK = cdiv(tWTR, tCK); localparam nWTR = (DRAM_TYPE == "DDR3") ? (nWTR_CK < 4) ? 4 : nWTR_CK : (nWTR_CK < 2) ? 2 : nWTR_CK; localparam nRTP_CK = cdiv(tRTP, tCK); localparam nRTP = (DRAM_TYPE == "DDR3") ? (nRTP_CK < 4) ? 4 : nRTP_CK : (nRTP_CK < 2) ? 2 : nRTP_CK; // Add a cycle to CL/CWL for the register in RDIMM devices localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; localparam CL_M = (REG_CTRL == "ON") ? CL + 1 : CL; // Tuneable delay between read and write data on the DQ bus localparam DQRD2DQWR_DLY = 4; // CKE minimum pulse width for self-refresh (SRE->SRX minimum time) localparam nCKESR = nCKE + 1; // Delay from SRE to command requiring locked DLL. Currently fixed at 512 for // all devices per JEDEC spec. localparam tXSDLL = 512; //*************************************************************************** // Set up maintenance counter dividers //*************************************************************************** // CK clock divisor to generate maintenance prescaler period (round down) localparam MAINT_PRESCALER_DIV = MAINT_PRESCALER_PERIOD / (tCK*nCK_PER_CLK); // Maintenance prescaler divisor for refresh timer. Essentially, this is // just (tREFI / MAINT_PRESCALER_PERIOD), but we must account for the worst // case delay from the time we get a tick from the refresh counter to the // time that we can actually issue the REF command. Thus, subtract tRCD, CL, // data burst time and tRP for each implemented bank machine to ensure that // all transactions can complete before tREFI expires localparam REFRESH_TIMER_DIV = USER_REFRESH == "ON" ? 0 : (tREFI-((tRCD+((CL+4)*tCK)+tRP)*nBANK_MACHS)) / MAINT_PRESCALER_PERIOD; // Periodic read (RESERVED - not currently required or supported in 7 series) // tPRDI should only be set to 0 // localparam tPRDI = 0; // Do NOT change. localparam PERIODIC_RD_TIMER_DIV = tPRDI / MAINT_PRESCALER_PERIOD; // Convert maintenance prescaler from ps to ns localparam MAINT_PRESCALER_PERIOD_NS = MAINT_PRESCALER_PERIOD / 1000; // Maintenance prescaler divisor for ZQ calibration (ZQCS) timer localparam ZQ_TIMER_DIV = tZQI / MAINT_PRESCALER_PERIOD_NS; // Bus width required to broadcast a single bit rank signal among all the // bank machines - 1 bit per rank, per bank localparam RANK_BM_BV_WIDTH = nBANK_MACHS * RANKS; //*************************************************************************** // Define 2T, CWL-even mode to enable multi-fabric-cycle 2T commands //*************************************************************************** localparam EVEN_CWL_2T_MODE = ((ADDR_CMD_MODE == "2T") && (!(CWL % 2))) ? "ON" : "OFF"; //*************************************************************************** // Reserved feature control. //*************************************************************************** // Open page wait mode is reserved. // nOP_WAIT is the number of states a bank machine will park itself // on an otherwise inactive open page before closing the page. If // nOP_WAIT == 0, open page wait mode is disabled. If nOP_WAIT == -1, // the bank machine will remain parked until the pool of idle bank machines // are less than LOW_IDLE_CNT. At which point parked bank machines // are selected to exit until the number of idle bank machines exceeds the // LOW_IDLE_CNT. localparam nOP_WAIT = 0; // Open page mode localparam LOW_IDLE_CNT = 0; // Low idle bank machine threshold //*************************************************************************** // Internal wires //*************************************************************************** wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; wire [ROW_WIDTH-1:0] col_a; wire [BANK_WIDTH-1:0] col_ba; wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr; wire col_periodic_rd; wire [RANK_WIDTH-1:0] col_ra; wire col_rmw; wire col_rd_wr; wire [ROW_WIDTH-1:0] col_row; wire col_size; wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr; wire dq_busy_data; wire ecc_status_valid; wire [RANKS-1:0] inhbt_act_faw_r; wire [RANKS-1:0] inhbt_rd; wire [RANKS-1:0] inhbt_wr; wire insert_maint_r1; wire [RANK_WIDTH-1:0] maint_rank_r; wire maint_req_r; wire maint_wip_r; wire maint_zq_r; wire maint_sre_r; wire maint_srx_r; wire periodic_rd_ack_r; wire periodic_rd_r; wire [RANK_WIDTH-1:0] periodic_rd_rank_r; wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; wire rd_rmw; wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; wire [nBANK_MACHS-1:0] sending_col; wire [nBANK_MACHS-1:0] sending_row; wire sent_col; wire sent_col_r; wire wr_ecc_buf; wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // MC/PHY optional pipeline stage support wire [nCK_PER_CLK-1:0] mc_ras_n_ns; wire [nCK_PER_CLK-1:0] mc_cas_n_ns; wire [nCK_PER_CLK-1:0] mc_we_n_ns; wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address_ns; wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank_ns; wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_ns; wire [1:0] mc_odt_ns; wire [nCK_PER_CLK-1:0] mc_cke_ns; wire [3:0] mc_aux_out0_ns; wire [3:0] mc_aux_out1_ns; wire [1:0] mc_rank_cnt_ns = col_ra; wire [2:0] mc_cmd_ns; wire [5:0] mc_data_offset_ns; wire [5:0] mc_data_offset_1_ns; wire [5:0] mc_data_offset_2_ns; wire [1:0] mc_cas_slot_ns; wire mc_wrdata_en_ns; wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr_ns; wire wr_data_en_ns; wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset_ns; integer i; // MC Read idle support wire col_read_fifo_empty; wire mc_read_idle_ns; reg mc_read_idle_r; // MC Maintenance in progress with bus idle indication wire maint_ref_zq_wip; wire mc_ref_zq_wip_ns; reg mc_ref_zq_wip_r; //*************************************************************************** // Function cdiv // Description: // This function performs ceiling division (divide and round-up) // Inputs: // num: integer to be divided // div: divisor // Outputs: // cdiv: result of ceiling division (num/div, rounded up) //*************************************************************************** function integer cdiv (input integer num, input integer div); begin // perform division, then add 1 if and only if remainder is non-zero cdiv = (num/div) + (((num%div)>0) ? 1 : 0); end endfunction // cdiv //*************************************************************************** // Optional pipeline register stage on MC/PHY interface //*************************************************************************** generate if (CMD_PIPE_PLUS1 == "ON") begin : cmd_pipe_plus // register interface always @(posedge clk) begin mc_address <= #TCQ mc_address_ns; mc_bank <= #TCQ mc_bank_ns; mc_cas_n <= #TCQ mc_cas_n_ns; mc_cs_n <= #TCQ mc_cs_n_ns; mc_odt <= #TCQ mc_odt_ns; mc_cke <= #TCQ mc_cke_ns; mc_aux_out0 <= #TCQ mc_aux_out0_ns; mc_aux_out1 <= #TCQ mc_aux_out1_ns; mc_cmd <= #TCQ mc_cmd_ns; mc_ras_n <= #TCQ mc_ras_n_ns; mc_we_n <= #TCQ mc_we_n_ns; mc_data_offset <= #TCQ mc_data_offset_ns; mc_data_offset_1 <= #TCQ mc_data_offset_1_ns; mc_data_offset_2 <= #TCQ mc_data_offset_2_ns; mc_cas_slot <= #TCQ mc_cas_slot_ns; mc_wrdata_en <= #TCQ mc_wrdata_en_ns; mc_rank_cnt <= #TCQ mc_rank_cnt_ns; wr_data_addr <= #TCQ wr_data_addr_ns; wr_data_en <= #TCQ wr_data_en_ns; wr_data_offset <= #TCQ wr_data_offset_ns; end // always @ (posedge clk) end // block: cmd_pipe_plus else begin : cmd_pipe_plus0 // don't register interface always @( mc_address_ns or mc_aux_out0_ns or mc_aux_out1_ns or mc_bank_ns or mc_cas_n_ns or mc_cmd_ns or mc_cs_n_ns or mc_odt_ns or mc_cke_ns or mc_data_offset_ns or mc_data_offset_1_ns or mc_data_offset_2_ns or mc_rank_cnt_ns or mc_ras_n_ns or mc_we_n_ns or mc_wrdata_en_ns or wr_data_addr_ns or wr_data_en_ns or wr_data_offset_ns or mc_cas_slot_ns) begin mc_address = #TCQ mc_address_ns; mc_bank = #TCQ mc_bank_ns; mc_cas_n = #TCQ mc_cas_n_ns; mc_cs_n = #TCQ mc_cs_n_ns; mc_odt = #TCQ mc_odt_ns; mc_cke = #TCQ mc_cke_ns; mc_aux_out0 = #TCQ mc_aux_out0_ns; mc_aux_out1 = #TCQ mc_aux_out1_ns; mc_cmd = #TCQ mc_cmd_ns; mc_ras_n = #TCQ mc_ras_n_ns; mc_we_n = #TCQ mc_we_n_ns; mc_data_offset = #TCQ mc_data_offset_ns; mc_data_offset_1 = #TCQ mc_data_offset_1_ns; mc_data_offset_2 = #TCQ mc_data_offset_2_ns; mc_cas_slot = #TCQ mc_cas_slot_ns; mc_wrdata_en = #TCQ mc_wrdata_en_ns; mc_rank_cnt = #TCQ mc_rank_cnt_ns; wr_data_addr = #TCQ wr_data_addr_ns; wr_data_en = #TCQ wr_data_en_ns; wr_data_offset = #TCQ wr_data_offset_ns; end // always @ (... end // block: cmd_pipe_plus0 endgenerate //*************************************************************************** // Indicate when there are no pending reads so that input features can be // powered down //*************************************************************************** assign mc_read_idle_ns = col_read_fifo_empty & init_calib_complete; always @(posedge clk) mc_read_idle_r <= #TCQ mc_read_idle_ns; assign mc_read_idle = mc_read_idle_r; //*************************************************************************** // Indicate when there is a refresh in progress and the bus is idle so that // tap adjustments can be made //*************************************************************************** assign mc_ref_zq_wip_ns = maint_ref_zq_wip && col_read_fifo_empty; always @(posedge clk) mc_ref_zq_wip_r <= mc_ref_zq_wip_ns; assign mc_ref_zq_wip = mc_ref_zq_wip_r; //*************************************************************************** // Manage rank-level timing and maintanence //*************************************************************************** mig_7series_v2_3_rank_mach # ( // Parameters .BURST_MODE (BURST_MODE), .CL (CL), .CWL (CWL), .CS_WIDTH (CS_WIDTH), .DQRD2DQWR_DLY (DQRD2DQWR_DLY), .DRAM_TYPE (DRAM_TYPE), .MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV), .nBANK_MACHS (nBANK_MACHS), .nCKESR (nCKESR), .nCK_PER_CLK (nCK_PER_CLK), .nFAW (nFAW), .nREFRESH_BANK (nREFRESH_BANK), .nRRD (nRRD), .nWTR (nWTR), .PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV), .RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .REFRESH_TIMER_DIV (REFRESH_TIMER_DIV), .ZQ_TIMER_DIV (ZQ_TIMER_DIV) ) rank_mach0 ( // Outputs .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), .inhbt_rd (inhbt_rd[RANKS-1:0]), .inhbt_wr (inhbt_wr[RANKS-1:0]), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .maint_ref_zq_wip (maint_ref_zq_wip), .periodic_rd_r (periodic_rd_r), .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), // Inputs .act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .app_periodic_rd_req (app_periodic_rd_req), .app_ref_req (app_ref_req), .app_ref_ack (app_ref_ack), .app_zq_req (app_zq_req), .app_zq_ack (app_zq_ack), .app_sr_req (app_sr_req), .app_sr_active (app_sr_active), .col_rd_wr (col_rd_wr), .clk (clk), .init_calib_complete (init_calib_complete), .insert_maint_r1 (insert_maint_r1), .maint_wip_r (maint_wip_r), .periodic_rd_ack_r (periodic_rd_ack_r), .rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]), .rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .rst (rst), .sending_col (sending_col[nBANK_MACHS-1:0]), .sending_row (sending_row[nBANK_MACHS-1:0]), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0]), .wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]) ); //*************************************************************************** // Manage requests, reordering and bank timing //*************************************************************************** mig_7series_v2_3_bank_mach # ( // Parameters .TCQ (TCQ), .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_WIDTH (BANK_WIDTH), .BM_CNT_WIDTH (BM_CNT_WIDTH), .BURST_MODE (BURST_MODE), .COL_WIDTH (COL_WIDTH), .CS_WIDTH (CS_WIDTH), .CL (CL_M), .CWL (CWL_M), .CKE_ODT_AUX (CKE_ODT_AUX), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .LOW_IDLE_CNT (LOW_IDLE_CNT), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nCS_PER_RANK (nCS_PER_RANK), .nOP_WAIT (nOP_WAIT), .nRAS (nRAS), .nRCD (nRCD), .nRFC (nRFC), .nRP (nRP), .nRTP (nRTP), .nSLOTS (nSLOTS), .nWR (nWR), .nXSDLL (tXSDLL), .ORDERING (ORDERING), .RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .ROW_WIDTH (ROW_WIDTH), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG), .STARVE_LIMIT (STARVE_LIMIT), .tZQCS (tZQCS) ) bank_mach0 ( // Outputs .accept (accept), .accept_ns (accept_ns), .act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]), .col_a (col_a[ROW_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_row (col_row[ROW_WIDTH-1:0]), .col_size (col_size), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .mc_bank (mc_bank_ns), .mc_address (mc_address_ns), .mc_ras_n (mc_ras_n_ns), .mc_cas_n (mc_cas_n_ns), .mc_we_n (mc_we_n_ns), .mc_cs_n (mc_cs_n_ns), .mc_odt (mc_odt_ns), .mc_cke (mc_cke_ns), .mc_aux_out0 (mc_aux_out0_ns), .mc_aux_out1 (mc_aux_out1_ns), .mc_cmd (mc_cmd_ns), .mc_data_offset (mc_data_offset_ns), .mc_data_offset_1 (mc_data_offset_1_ns), .mc_data_offset_2 (mc_data_offset_2_ns), .mc_cas_slot (mc_cas_slot_ns), .insert_maint_r1 (insert_maint_r1), .maint_wip_r (maint_wip_r), .periodic_rd_ack_r (periodic_rd_ack_r), .rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]), .rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .sending_row (sending_row[nBANK_MACHS-1:0]), .sending_col (sending_col[nBANK_MACHS-1:0]), .sent_col (sent_col), .sent_col_r (sent_col_r), .wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]), // Inputs .bank (bank[BANK_WIDTH-1:0]), .calib_rddata_offset (calib_rd_data_offset), .calib_rddata_offset_1 (calib_rd_data_offset_1), .calib_rddata_offset_2 (calib_rd_data_offset_2), .clk (clk), .cmd (cmd[2:0]), .col (col[COL_WIDTH-1:0]), .data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .init_calib_complete (init_calib_complete), .phy_rddata_valid (phy_rddata_valid), .dq_busy_data (dq_busy_data), .hi_priority (hi_priority), .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), .inhbt_rd (inhbt_rd[RANKS-1:0]), .inhbt_wr (inhbt_wr[RANKS-1:0]), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .periodic_rd_r (periodic_rd_r), .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), .phy_mc_cmd_full (phy_mc_cmd_full), .phy_mc_ctl_full (phy_mc_ctl_full), .phy_mc_data_full (phy_mc_data_full), .rank (rank[RANK_WIDTH-1:0]), .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), .rd_rmw (rd_rmw), .row (row[ROW_WIDTH-1:0]), .rst (rst), .size (size), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0]), .use_addr (use_addr) ); //*************************************************************************** // Manage DQ bus //*************************************************************************** mig_7series_v2_3_col_mach # ( // Parameters .TCQ (TCQ), .BANK_WIDTH (BANK_WIDTH), .BURST_MODE (BURST_MODE), .COL_WIDTH (COL_WIDTH), .CS_WIDTH (CS_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH), .DELAY_WR_DATA_CNTRL (DELAY_WR_DATA_CNTRL), .DQS_WIDTH (DQS_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH), .nCK_PER_CLK (nCK_PER_CLK), .nPHY_WRLAT (nPHY_WRLAT), .RANK_WIDTH (RANK_WIDTH), .ROW_WIDTH (ROW_WIDTH) ) col_mach0 ( // Outputs .mc_wrdata_en (mc_wrdata_en_ns), .dq_busy_data (dq_busy_data), .ecc_err_addr (ecc_err_addr[MC_ERR_ADDR_WIDTH-1:0]), .ecc_status_valid (ecc_status_valid), .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), .rd_data_en (rd_data_en), .rd_data_end (rd_data_end), .rd_data_offset (rd_data_offset), .rd_rmw (rd_rmw), .wr_data_addr (wr_data_addr_ns), .wr_data_en (wr_data_en_ns), .wr_data_offset (wr_data_offset_ns), .wr_ecc_buf (wr_ecc_buf), .col_read_fifo_empty (col_read_fifo_empty), // Inputs .clk (clk), .rst (rst), .col_a (col_a[ROW_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_row (col_row[ROW_WIDTH-1:0]), .col_size (col_size), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .phy_rddata_valid (phy_rddata_valid), .sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col) ); //*************************************************************************** // Implement ECC //*************************************************************************** // Total ECC word length = ECC code width + Data width localparam CODE_WIDTH = DATA_WIDTH + ECC_WIDTH; generate if (ECC == "OFF") begin : ecc_off assign rd_data = phy_rd_data; assign mc_wrdata = wr_data; assign mc_wrdata_mask = wr_data_mask; assign ecc_single = 4'b0; assign ecc_multiple = 4'b0; end else begin : ecc_on wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data; wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_i; // Merge and encode mig_7series_v2_3_ecc_merge_enc # ( // Parameters .TCQ (TCQ), .CODE_WIDTH (CODE_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DATA_WIDTH (DATA_WIDTH), .DQ_WIDTH (DQ_WIDTH), .ECC_WIDTH (ECC_WIDTH), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) ecc_merge_enc0 ( // Outputs .mc_wrdata (mc_wrdata_i), .mc_wrdata_mask (mc_wrdata_mask), // Inputs .clk (clk), .rst (rst), .h_rows (h_rows), .rd_merge_data (rd_merge_data), .raw_not_ecc (raw_not_ecc), .wr_data (wr_data), .wr_data_mask (wr_data_mask) ); // Decode and fix mig_7series_v2_3_ecc_dec_fix # ( // Parameters .TCQ (TCQ), .CODE_WIDTH (CODE_WIDTH), .DATA_WIDTH (DATA_WIDTH), .DQ_WIDTH (DQ_WIDTH), .ECC_WIDTH (ECC_WIDTH), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) ecc_dec_fix0 ( // Outputs .ecc_multiple (ecc_multiple), .ecc_single (ecc_single), .rd_data (rd_data), // Inputs .clk (clk), .rst (rst), .correct_en (correct_en), .phy_rddata (phy_rd_data), .ecc_status_valid (ecc_status_valid), .h_rows (h_rows) ); // ECC Buffer mig_7series_v2_3_ecc_buf # ( // Parameters .TCQ (TCQ), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH), .DATA_WIDTH (DATA_WIDTH), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) ecc_buf0 ( // Outputs .rd_merge_data (rd_merge_data), // Inputs .clk (clk), .rst (rst), .rd_data (rd_data), .rd_data_addr (rd_data_addr), .rd_data_offset (rd_data_offset), .wr_data_addr (wr_data_addr), .wr_data_offset (wr_data_offset), .wr_ecc_buf (wr_ecc_buf) ); // Generate ECC table mig_7series_v2_3_ecc_gen # ( // Parameters .CODE_WIDTH (CODE_WIDTH), .DATA_WIDTH (DATA_WIDTH), .ECC_WIDTH (ECC_WIDTH) ) ecc_gen0 ( // Outputs .h_rows (h_rows) ); if (ECC == "ON") begin : gen_fi_xor_inst reg mc_wrdata_en_r; wire mc_wrdata_en_i; always @(posedge clk) begin mc_wrdata_en_r <= mc_wrdata_en; end assign mc_wrdata_en_i = mc_wrdata_en_r; mig_7series_v2_3_fi_xor #( .DQ_WIDTH (DQ_WIDTH), .DQS_WIDTH (DQS_WIDTH), .nCK_PER_CLK (nCK_PER_CLK) ) fi_xor0 ( .clk (clk), .wrdata_in (mc_wrdata_i), .wrdata_out (mc_wrdata), .wrdata_en (mc_wrdata_en_i), .fi_xor_we (fi_xor_we), .fi_xor_wrdata (fi_xor_wrdata) ); end else begin : gen_wrdata_passthru assign mc_wrdata = mc_wrdata_i; end `ifdef DISPLAY_H_MATRIX integer i; always @(negedge rst) begin $display ("**********************************************"); $display ("H Matrix:"); for (i=0; i<ECC_WIDTH; i=i+1) $display ("%b", h_rows[i*CODE_WIDTH+:CODE_WIDTH]); $display ("**********************************************"); end `endif end endgenerate endmodule // mc

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_dqs_found_cal.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Read leveling calibration logic // NOTES: // 1. Phaser_In DQSFOUND calibration //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $ **$Date: 2011/06/02 08:35:08 $ **$Author: **$Revision: **$Source: ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_dqs_found_cal_hr # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter nCL = 5, // Read CAS latency parameter AL = "0", parameter nCWL = 5, // Write CAS latency parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" parameter RANKS = 1, // # of memory ranks in the system parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate parameter N_CTL_LANES = 3, // Number of control byte lanes parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl) parameter HIGHEST_BANK = 3, // Sum of I/O Banks parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf ) ( input clk, input rst, input dqsfound_retry, // From phy_init input pi_dqs_found_start, input detect_pi_found_dqs, input prech_done, // DQSFOUND per Phaser_IN input [HIGHEST_LANE-1:0] pi_dqs_found_lanes, output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal, // To phy_init output [5:0] rd_data_offset_0, output [5:0] rd_data_offset_1, output [5:0] rd_data_offset_2, output pi_dqs_found_rank_done, output pi_dqs_found_done, output reg pi_dqs_found_err, output [6*RANKS-1:0] rd_data_offset_ranks_0, output [6*RANKS-1:0] rd_data_offset_ranks_1, output [6*RANKS-1:0] rd_data_offset_ranks_2, output reg dqsfound_retry_done, output reg dqs_found_prech_req, //To MC output [6*RANKS-1:0] rd_data_offset_ranks_mc_0, output [6*RANKS-1:0] rd_data_offset_ranks_mc_1, output [6*RANKS-1:0] rd_data_offset_ranks_mc_2, input [8:0] po_counter_read_val, output rd_data_offset_cal_done, output fine_adjust_done, output [N_CTL_LANES-1:0] fine_adjust_lane_cnt, output reg ck_po_stg2_f_indec, output reg ck_po_stg2_f_en, output [255:0] dbg_dqs_found_cal ); // For non-zero AL values localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; // Adding the register dimm latency to write latency localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; // Added to reduce simulation time localparam LATENCY_FACTOR = 13; localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1; localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]), (DATA_CTL_B4[2] & BYTE_LANES_B4[2]), (DATA_CTL_B4[1] & BYTE_LANES_B4[1]), (DATA_CTL_B4[0] & BYTE_LANES_B4[0]), (DATA_CTL_B3[3] & BYTE_LANES_B3[3]), (DATA_CTL_B3[2] & BYTE_LANES_B3[2]), (DATA_CTL_B3[1] & BYTE_LANES_B3[1]), (DATA_CTL_B3[0] & BYTE_LANES_B3[0]), (DATA_CTL_B2[3] & BYTE_LANES_B2[3]), (DATA_CTL_B2[2] & BYTE_LANES_B2[2]), (DATA_CTL_B2[1] & BYTE_LANES_B2[1]), (DATA_CTL_B2[0] & BYTE_LANES_B2[0]), (DATA_CTL_B1[3] & BYTE_LANES_B1[3]), (DATA_CTL_B1[2] & BYTE_LANES_B1[2]), (DATA_CTL_B1[1] & BYTE_LANES_B1[1]), (DATA_CTL_B1[0] & BYTE_LANES_B1[0]), (DATA_CTL_B0[3] & BYTE_LANES_B0[3]), (DATA_CTL_B0[2] & BYTE_LANES_B0[2]), (DATA_CTL_B0[1] & BYTE_LANES_B0[1]), (DATA_CTL_B0[0] & BYTE_LANES_B0[0])}; localparam FINE_ADJ_IDLE = 4'h0; localparam RST_POSTWAIT = 4'h1; localparam RST_POSTWAIT1 = 4'h2; localparam RST_WAIT = 4'h3; localparam FINE_ADJ_INIT = 4'h4; localparam FINE_INC = 4'h5; localparam FINE_INC_WAIT = 4'h6; localparam FINE_INC_PREWAIT = 4'h7; localparam DETECT_PREWAIT = 4'h8; localparam DETECT_DQSFOUND = 4'h9; localparam PRECH_WAIT = 4'hA; localparam FINE_DEC = 4'hB; localparam FINE_DEC_WAIT = 4'hC; localparam FINE_DEC_PREWAIT = 4'hD; localparam FINAL_WAIT = 4'hE; localparam FINE_ADJ_DONE = 4'hF; integer k,l,m,n,p,q,r,s; reg dqs_found_start_r; reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1]; reg rank_done_r; reg rank_done_r1; reg dqs_found_done_r; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3; reg init_dqsfound_done_r; reg init_dqsfound_done_r1; reg init_dqsfound_done_r2; reg init_dqsfound_done_r3; reg init_dqsfound_done_r4; reg init_dqsfound_done_r5; reg [1:0] rnk_cnt_r; reg [2:0 ] final_do_index[0:RANKS-1]; reg [5:0 ] final_do_max[0:RANKS-1]; reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1]; reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1]; reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r; reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1; reg [10*HIGHEST_BANK-1:0] retry_cnt; reg dqsfound_retry_r1; wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int; reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank; reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r; reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank; reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r; reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r; // CK/Control byte lanes fine adjust stage reg fine_adjust; reg [N_CTL_LANES-1:0] ctl_lane_cnt; reg [3:0] fine_adj_state_r; reg fine_adjust_done_r; reg rst_dqs_find; reg rst_dqs_find_r1; reg rst_dqs_find_r2; reg [5:0] init_dec_cnt; reg [5:0] dec_cnt; reg [5:0] inc_cnt; reg final_dec_done; reg init_dec_done; reg first_fail_detect; reg second_fail_detect; reg [5:0] first_fail_taps; reg [5:0] second_fail_taps; reg [5:0] stable_pass_cnt; reg [3:0] detect_rd_cnt; //*************************************************************************** // Debug signals // //*************************************************************************** assign dbg_dqs_found_cal[5:0] = first_fail_taps; assign dbg_dqs_found_cal[11:6] = second_fail_taps; assign dbg_dqs_found_cal[12] = first_fail_detect; assign dbg_dqs_found_cal[13] = second_fail_detect; assign dbg_dqs_found_cal[14] = fine_adjust_done_r; assign pi_dqs_found_rank_done = rank_done_r; assign pi_dqs_found_done = dqs_found_done_r; generate genvar rnk_cnt; if (HIGHEST_BANK == 3) begin // Three Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12]; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12]; end end else if (HIGHEST_BANK == 2) begin // Two Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; end end else begin // Single Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; end end endgenerate // final_data_offset is used during write calibration and during // normal operation. One rd_data_offset value per rank for entire // interface generate if (HIGHEST_BANK == 3) begin // Three I/O Bank interface assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : final_data_offset[rnk_cnt_r][6+:6]; assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] : final_data_offset[rnk_cnt_r][12+:6]; end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : final_data_offset[rnk_cnt_r][6+:6]; assign rd_data_offset_2 = 'd0; end else begin assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = 'd0; assign rd_data_offset_2 = 'd0; end endgenerate assign rd_data_offset_cal_done = init_dqsfound_done_r; assign fine_adjust_lane_cnt = ctl_lane_cnt; //************************************************************************** // DQSFOUND all and any generation // pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are // asserted // pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx // is asserted //************************************************************************** generate if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12)) assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3; else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11)) assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3}; else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10)) assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3}; else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9)) assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3}; endgenerate always @(posedge clk) begin if (rst) begin for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found pi_dqs_found_all_bank[k] <= #TCQ 'b0; pi_dqs_found_any_bank[k] <= #TCQ 'b0; end end else if (pi_dqs_found_start) begin for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) & (!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) & (!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) & (!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]); pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) | (DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) | (DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) | (DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]); end end end always @(posedge clk) begin pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank; pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank; end //***************************************************************************** // Counter to increase number of 4 back-to-back reads per rd_data_offset and // per CK/A/C tap value //***************************************************************************** always @(posedge clk) begin if (rst || (detect_rd_cnt == 'd0)) detect_rd_cnt <= #TCQ NUM_READS; else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0)) detect_rd_cnt <= #TCQ detect_rd_cnt - 1; end //************************************************************************** // Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls // //************************************************************************** assign fine_adjust_done = fine_adjust_done_r; always @(posedge clk) begin rst_dqs_find_r1 <= #TCQ rst_dqs_find; rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1; end always @(posedge clk) begin if(rst)begin fine_adjust <= #TCQ 1'b0; ctl_lane_cnt <= #TCQ 'd0; fine_adj_state_r <= #TCQ FINE_ADJ_IDLE; fine_adjust_done_r <= #TCQ 1'b0; ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; rst_dqs_find <= #TCQ 1'b0; init_dec_cnt <= #TCQ 'd31; dec_cnt <= #TCQ 'd0; inc_cnt <= #TCQ 'd0; init_dec_done <= #TCQ 1'b0; final_dec_done <= #TCQ 1'b0; first_fail_detect <= #TCQ 1'b0; second_fail_detect <= #TCQ 1'b0; first_fail_taps <= #TCQ 'd0; second_fail_taps <= #TCQ 'd0; stable_pass_cnt <= #TCQ 'd0; dqs_found_prech_req<= #TCQ 1'b0; end else begin case (fine_adj_state_r) FINE_ADJ_IDLE: begin if (init_dqsfound_done_r5) begin if (SIM_CAL_OPTION == "FAST_CAL") begin fine_adjust <= #TCQ 1'b1; fine_adj_state_r <= #TCQ FINE_ADJ_DONE; rst_dqs_find <= #TCQ 1'b0; end else begin fine_adjust <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; rst_dqs_find <= #TCQ 1'b1; end end end RST_WAIT: begin if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin rst_dqs_find <= #TCQ 1'b0; if (|init_dec_cnt) fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; else if (final_dec_done) fine_adj_state_r <= #TCQ FINE_ADJ_DONE; else fine_adj_state_r <= #TCQ RST_POSTWAIT; end end RST_POSTWAIT: begin fine_adj_state_r <= #TCQ RST_POSTWAIT1; end RST_POSTWAIT1: begin fine_adj_state_r <= #TCQ FINE_ADJ_INIT; end FINE_ADJ_INIT: begin //if (detect_pi_found_dqs && (inc_cnt < 'd63)) fine_adj_state_r <= #TCQ FINE_INC; end FINE_INC: begin fine_adj_state_r <= #TCQ FINE_INC_WAIT; ck_po_stg2_f_indec <= #TCQ 1'b1; ck_po_stg2_f_en <= #TCQ 1'b1; if (ctl_lane_cnt == N_CTL_LANES-1) inc_cnt <= #TCQ inc_cnt + 1; end FINE_INC_WAIT: begin ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; if (ctl_lane_cnt != N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; fine_adj_state_r <= #TCQ FINE_INC_PREWAIT; end else if (ctl_lane_cnt == N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ 'd0; fine_adj_state_r <= #TCQ DETECT_PREWAIT; end end FINE_INC_PREWAIT: begin fine_adj_state_r <= #TCQ FINE_INC; end DETECT_PREWAIT: begin if (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) fine_adj_state_r <= #TCQ DETECT_DQSFOUND; else fine_adj_state_r <= #TCQ DETECT_PREWAIT; end DETECT_DQSFOUND: begin if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin stable_pass_cnt <= #TCQ 'd0; if (~first_fail_detect && (inc_cnt == 'd63)) begin // First failing tap detected at 63 taps // then decrement to 31 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ 'd32; end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin // First failing tap detected at greater than 30 taps // then stop looking for second edge and decrement first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ (inc_cnt>>1) + 1; end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin // First failing tap detected, continue incrementing // until either second failing tap detected or 63 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; rst_dqs_find <= #TCQ 1'b1; if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else fine_adj_state_r <= #TCQ RST_WAIT; end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin // Consecutive 30 taps of passing region was not found // continue incrementing first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; rst_dqs_find <= #TCQ 1'b1; if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else fine_adj_state_r <= #TCQ RST_WAIT; end else if (first_fail_detect && (inc_cnt == 'd63)) begin if (stable_pass_cnt < 'd30) begin // Consecutive 30 taps of passing region was not found // from tap 0 to 63 so decrement back to 31 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ 'd32; end else begin // Consecutive 30 taps of passing region was found // between first_fail_taps and 63 fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); end end else begin // Second failing tap detected, decrement to center of // failing taps second_fail_detect <= #TCQ 1'b1; second_fail_taps <= #TCQ inc_cnt; dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); fine_adj_state_r <= #TCQ FINE_DEC; end end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin stable_pass_cnt <= #TCQ stable_pass_cnt + 1; if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else if (inc_cnt < 'd63) begin rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end else begin fine_adj_state_r <= #TCQ FINE_DEC; if (~first_fail_detect || (first_fail_taps > 'd33)) // No failing taps detected, decrement by 31 dec_cnt <= #TCQ 'd32; //else if (first_fail_detect && (stable_pass_cnt > 'd28)) // // First failing tap detected between 0 and 34 // // decrement midpoint between 63 and failing tap // dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); else // First failing tap detected // decrement to midpoint between 63 and failing tap dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); end end end PRECH_WAIT: begin if (prech_done) begin dqs_found_prech_req <= #TCQ 1'b0; rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end end FINE_DEC: begin fine_adj_state_r <= #TCQ FINE_DEC_WAIT; ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b1; if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0)) init_dec_cnt <= #TCQ init_dec_cnt - 1; else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0)) dec_cnt <= #TCQ dec_cnt - 1; end FINE_DEC_WAIT: begin ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; if (ctl_lane_cnt != N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; end else if (ctl_lane_cnt == N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ 'd0; if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0)) fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; else begin fine_adj_state_r <= #TCQ FINAL_WAIT; if ((init_dec_cnt == 'd0) && ~init_dec_done) init_dec_done <= #TCQ 1'b1; else final_dec_done <= #TCQ 1'b1; end end end FINE_DEC_PREWAIT: begin fine_adj_state_r <= #TCQ FINE_DEC; end FINAL_WAIT: begin rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end FINE_ADJ_DONE: begin if (&pi_dqs_found_all_bank) begin fine_adjust_done_r <= #TCQ 1'b1; rst_dqs_find <= #TCQ 1'b0; fine_adj_state_r <= #TCQ FINE_ADJ_DONE; end end endcase end end //***************************************************************************** always@(posedge clk) dqs_found_start_r <= #TCQ pi_dqs_found_start; always @(posedge clk) begin if (rst) rnk_cnt_r <= #TCQ 2'b00; else if (init_dqsfound_done_r) rnk_cnt_r <= #TCQ rnk_cnt_r; else if (rank_done_r) rnk_cnt_r <= #TCQ rnk_cnt_r + 1; end //***************************************************************** // Read data_offset calibration done signal //***************************************************************** always @(posedge clk) begin if (rst || (|pi_rst_stg1_cal_r)) init_dqsfound_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank) begin if (rnk_cnt_r == RANKS-1) init_dqsfound_done_r <= #TCQ 1'b1; else init_dqsfound_done_r <= #TCQ 1'b0; end end always @(posedge clk) begin if (rst || (init_dqsfound_done_r && (rnk_cnt_r == RANKS-1))) rank_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r)) rank_done_r <= #TCQ 1'b1; else rank_done_r <= #TCQ 1'b0; end always @(posedge clk) begin pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes; pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1; pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2; init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r; init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1; init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2; init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3; init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4; rank_done_r1 <= #TCQ rank_done_r; dqsfound_retry_r1 <= #TCQ dqsfound_retry; end always @(posedge clk) begin if (rst) dqs_found_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 && (fine_adj_state_r == FINE_ADJ_DONE)) dqs_found_done_r <= #TCQ 1'b1; else dqs_found_done_r <= #TCQ 1'b0; end generate if (HIGHEST_BANK == 3) begin // Three I/O Bank interface // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[1]) || (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust) pi_rst_stg1_cal_r[2] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[2]) || (pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) || (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_rst_stg1_cal_r[2] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[2]) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[10+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && ~pi_dqs_found_all_bank[1]) retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; else retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[20+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && ~pi_dqs_found_all_bank[2]) retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1; else retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[1] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_dqs_found_err_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[2] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_dqs_found_err_r[2] <= #TCQ 1'b1; end // Read data offset value for all DQS in a Bank always @(posedge clk) begin if (rst) begin for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1; end always @(posedge clk) begin if (rst) begin for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && //(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1; end always @(posedge clk) begin if (rst) begin for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL - 2; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL - 2; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] && //(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL + LATENCY_FACTOR)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] + 1; end //***************************************************************************** // Two I/O Bank Interface //***************************************************************************** end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[1]) || (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[10+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && ~pi_dqs_found_all_bank[1]) retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; else retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[1] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_dqs_found_err_r[1] <= #TCQ 1'b1; end // Read data offset value for all DQS in a Bank always @(posedge clk) begin if (rst) begin for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1; end always @(posedge clk) begin if (rst) begin for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && //(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1; end //***************************************************************************** // One I/O Bank Interface //***************************************************************************** end else begin // One I/O Bank Interface // Read data offset value for all DQS in Bank0 always @(posedge clk) begin if (rst) begin for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop rd_byte_data_offset[l] <= #TCQ nCL + nAL - 2; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL + LATENCY_FACTOR - 1))) rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL - 2; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL + LATENCY_FACTOR)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r] <= #TCQ rd_byte_data_offset[rnk_cnt_r] + 1; end // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted even with 3 dqfound retries always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end end endgenerate always @(posedge clk) begin if (rst) pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}}; else if (rst_dqs_find) pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}}; else pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r; end // Final read data offset value to be used during write calibration and // normal operation generate genvar i; genvar j; for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop reg [5:0] final_do_cand [RANKS-1:0]; // combinatorially select the candidate offset for the bank // indexed by final_do_index if (HIGHEST_BANK == 3) begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; 3'b010: final_do_cand[i] = final_data_offset[i][17:12]; default: final_do_cand[i] = 'd0; endcase end end else if (HIGHEST_BANK == 2) begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; 3'b010: final_do_cand[i] = 'd0; default: final_do_cand[i] = 'd0; endcase end end else begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = 'd0; 3'b010: final_do_cand[i] = 'd0; default: final_do_cand[i] = 'd0; endcase end end always @(posedge clk) begin if (rst) final_do_max[i] <= #TCQ 0; else begin final_do_max[i] <= #TCQ final_do_max[i]; // default case (final_do_index[i]) 3'b000: if ( | DATA_PRESENT[3:0]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; 3'b001: if ( | DATA_PRESENT[7:4]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; 3'b010: if ( | DATA_PRESENT[11:8]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; default: final_do_max[i] <= #TCQ final_do_max[i]; endcase end end always @(posedge clk) if (rst) begin final_do_index[i] <= #TCQ 0; end else begin final_do_index[i] <= #TCQ final_do_index[i] + 1; end for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop always @(posedge clk) begin if (rst) begin final_data_offset[i][6*j+:6] <= #TCQ 'b0; end else begin //if (dqsfound_retry[j]) // final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; //else if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; if (CWL_M % 2) // odd latency CAS slot 1 final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1; else // even latency CAS slot 0 final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; end end else if (init_dqsfound_done_r5 ) begin if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i]; final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i]; end end end end end end endgenerate // Error generation in case pi_found_dqs signal from Phaser_IN // is not asserted when a common rddata_offset value is used always @(posedge clk) begin pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r; end endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ui_wr_data.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // User interface write data buffer. Consists of four counters, // a pointer RAM and the write data storage RAM. // // All RAMs are implemented with distributed RAM. // // Whe ordering is set to STRICT or NORM, data moves through // the write data buffer in strictly FIFO order. In RELAXED // mode, data may be retired from the write data RAM in any // order relative to the input order. This implementation // supports all ordering modes. // // The pointer RAM stores a list of pointers to the write data storage RAM. // This is a list of vacant entries. As data is written into the RAM, a // pointer is pulled from the pointer RAM and used to index the write // operation. In a semi autonomously manner, pointers are also pulled, in // the same order, and provided to the command port as the data_buf_addr. // // When the MC reads data from the write data buffer, it uses the // data_buf_addr provided with the command to extract the data from the // write data buffer. It also writes this pointer into the end // of the pointer RAM. // // The occupancy counter keeps track of how many entries are valid // in the write data storage RAM. app_wdf_rdy and app_rdy will be // de-asserted when there is no more storage in the write data buffer. // // Three sequentially incrementing counters/indexes are used to maintain // and use the contents of the pointer RAM. // // The write buffer write data address index generates the pointer // used to extract the write data address from the pointer RAM. It // is incremented with each buffer write. The counter is actually one // ahead of the current write address so that the actual data buffer // write address can be registered to give a full state to propagate to // the write data distributed RAMs. // // The data_buf_addr counter is used to extract the data_buf_addr for // the command port. It is incremented as each command is written // into the MC. // // The read data index points to the end of the list of free // buffers. When the MC fetches data from the write data buffer, it // provides the buffer address. The buffer address is used to fetch // the data, but is also written into the pointer at the location indicated // by the read data index. // // Enter and exiting a buffer full condition generates corner cases. Upon // entering a full condition, incrementing the write buffer write data // address index must be inhibited. When exiting the full condition, // the just arrived pointer must propagate through the pointer RAM, then // indexed by the current value of the write buffer write data // address counter, the value is registered in the write buffer write // data address register, then the counter can be advanced. // // The pointer RAM must be initialized with valid data after reset. This is // accomplished by stepping through each pointer RAM entry and writing // the locations address into the pointer RAM. For the FIFO modes, this means // that buffer address will always proceed in a sequential order. In the // RELAXED mode, the original write traversal will be in sequential // order, but once the MC begins to retire out of order, the entries in // the pointer RAM will become randomized. The ui_rd_data module provides // the control information for the initialization process. `timescale 1 ps / 1 ps module mig_7series_v2_3_ui_wr_data # ( parameter TCQ = 100, parameter APP_DATA_WIDTH = 256, parameter APP_MASK_WIDTH = 32, parameter ECC = "OFF", parameter nCK_PER_CLK = 2 , parameter ECC_TEST = "OFF", parameter CWL = 5 ) (/*AUTOARG*/ // Outputs app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask, raw_not_ecc, // Inputs rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren, app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted, ram_init_done_r, ram_init_addr ); input rst; input clk; input [APP_DATA_WIDTH-1:0] app_wdf_data; input [APP_MASK_WIDTH-1:0] app_wdf_mask; input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; input app_wdf_wren; input app_wdf_end; reg [APP_DATA_WIDTH-1:0] app_wdf_data_r1; reg [APP_MASK_WIDTH-1:0] app_wdf_mask_r1; reg [2*nCK_PER_CLK-1:0] app_raw_not_ecc_r1 = 4'b0; reg app_wdf_wren_r1; reg app_wdf_end_r1; reg app_wdf_rdy_r; //Adding few copies of the app_wdf_rdy_r signal in order to meet //timing. This is signal has a very high fanout. So grouped into //few functional groups and alloted one copy per group. (* equivalent_register_removal = "no" *) reg app_wdf_rdy_r_copy1; (* equivalent_register_removal = "no" *) reg app_wdf_rdy_r_copy2; (* equivalent_register_removal = "no" *) reg app_wdf_rdy_r_copy3; (* equivalent_register_removal = "no" *) reg app_wdf_rdy_r_copy4; wire [APP_DATA_WIDTH-1:0] app_wdf_data_ns1 = ~app_wdf_rdy_r_copy2 ? app_wdf_data_r1 : app_wdf_data; wire [APP_MASK_WIDTH-1:0] app_wdf_mask_ns1 = ~app_wdf_rdy_r_copy2 ? app_wdf_mask_r1 : app_wdf_mask; wire app_wdf_wren_ns1 = ~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_wren_r1 : app_wdf_wren); wire app_wdf_end_ns1 = ~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_end_r1 : app_wdf_end); generate if (ECC_TEST != "OFF") begin : ecc_on always @(app_raw_not_ecc) app_raw_not_ecc_r1 = app_raw_not_ecc; end endgenerate // Be explicit about the latch enable on these registers. always @(posedge clk) begin app_wdf_data_r1 <= #TCQ app_wdf_data_ns1; app_wdf_mask_r1 <= #TCQ app_wdf_mask_ns1; app_wdf_wren_r1 <= #TCQ app_wdf_wren_ns1; app_wdf_end_r1 <= #TCQ app_wdf_end_ns1; end // The signals wr_data_addr and wr_data_offset come at different // times depending on ECC and the value of CWL. The data portion // always needs to look a the raw wires, the control portion needs // to look at a delayed version when ECC is on and CWL != 8. The // currently supported write data delays do not require this // functionality, but preserve for future use. input wr_data_offset; input [3:0] wr_data_addr; reg wr_data_offset_r; reg [3:0] wr_data_addr_r; generate if (ECC == "OFF" || CWL >= 0) begin : pass_wr_addr always @(wr_data_offset) wr_data_offset_r = wr_data_offset; always @(wr_data_addr) wr_data_addr_r = wr_data_addr; end else begin : delay_wr_addr always @(posedge clk) wr_data_offset_r <= #TCQ wr_data_offset; always @(posedge clk) wr_data_addr_r <= #TCQ wr_data_addr; end endgenerate // rd_data_cnt is the pointer RAM index for data read from the write data // buffer. Ie, its the data on its way out to the DRAM. input wr_data_en; wire new_rd_data = wr_data_en && ~wr_data_offset_r; reg [3:0] rd_data_indx_r; reg rd_data_upd_indx_r; generate begin : read_data_indx reg [3:0] rd_data_indx_ns; always @(/*AS*/new_rd_data or rd_data_indx_r or rst) begin rd_data_indx_ns = rd_data_indx_r; if (rst) rd_data_indx_ns = 5'b0; else if (new_rd_data) rd_data_indx_ns = rd_data_indx_r + 5'h1; end always @(posedge clk) rd_data_indx_r <= #TCQ rd_data_indx_ns; always @(posedge clk) rd_data_upd_indx_r <= #TCQ new_rd_data; end endgenerate // data_buf_addr_cnt generates the pointer for the pointer RAM on behalf // of data buf address that comes with the wr_data_en. // The data buf address is written into the memory // controller along with the command and address. input wr_accepted; reg [3:0] data_buf_addr_cnt_r; generate begin : data_buf_address_counter reg [3:0] data_buf_addr_cnt_ns; always @(/*AS*/data_buf_addr_cnt_r or rst or wr_accepted) begin data_buf_addr_cnt_ns = data_buf_addr_cnt_r; if (rst) data_buf_addr_cnt_ns = 4'b0; else if (wr_accepted) data_buf_addr_cnt_ns = data_buf_addr_cnt_r + 4'h1; end always @(posedge clk) data_buf_addr_cnt_r <= #TCQ data_buf_addr_cnt_ns; end endgenerate // Control writing data into the write data buffer. wire wdf_rdy_ns; always @( posedge clk ) begin app_wdf_rdy_r_copy1 <= #TCQ wdf_rdy_ns; app_wdf_rdy_r_copy2 <= #TCQ wdf_rdy_ns; app_wdf_rdy_r_copy3 <= #TCQ wdf_rdy_ns; app_wdf_rdy_r_copy4 <= #TCQ wdf_rdy_ns; end wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1; wire [3:0] wr_data_pntr; wire [4:0] wb_wr_data_addr; wire [4:0] wb_wr_data_addr_w; reg [3:0] wr_data_indx_r; generate begin : write_data_control wire wr_data_addr_le = (wr_data_end && wdf_rdy_ns) || (rd_data_upd_indx_r && ~app_wdf_rdy_r_copy1); // For pointer RAM. Initialize to one since this is one ahead of // what's being registered in wb_wr_data_addr. Assumes pointer RAM // has been initialized such that address equals contents. reg [3:0] wr_data_indx_ns; always @(/*AS*/rst or wr_data_addr_le or wr_data_indx_r) begin wr_data_indx_ns = wr_data_indx_r; if (rst) wr_data_indx_ns = 4'b1; else if (wr_data_addr_le) wr_data_indx_ns = wr_data_indx_r + 4'h1; end always @(posedge clk) wr_data_indx_r <= #TCQ wr_data_indx_ns; // Take pointer from pointer RAM and set into the write data address. // Needs to be split into zeroth bit and everything else because synthesis // tools don't always allow assigning bit vectors seperately. Bit zero of the // address is computed via an entirely different algorithm. reg [4:1] wb_wr_data_addr_ns; reg [4:1] wb_wr_data_addr_r; always @(/*AS*/rst or wb_wr_data_addr_r or wr_data_addr_le or wr_data_pntr) begin wb_wr_data_addr_ns = wb_wr_data_addr_r; if (rst) wb_wr_data_addr_ns = 4'b0; else if (wr_data_addr_le) wb_wr_data_addr_ns = wr_data_pntr; end always @(posedge clk) wb_wr_data_addr_r <= #TCQ wb_wr_data_addr_ns; // If we see the first getting accepted, then // second half is unconditionally accepted. reg wb_wr_data_addr0_r; wire wb_wr_data_addr0_ns = ~rst && ((app_wdf_rdy_r_copy3 && app_wdf_wren_r1 && ~app_wdf_end_r1) || (wb_wr_data_addr0_r && ~app_wdf_wren_r1)); always @(posedge clk) wb_wr_data_addr0_r <= #TCQ wb_wr_data_addr0_ns; assign wb_wr_data_addr = {wb_wr_data_addr_r, wb_wr_data_addr0_r}; assign wb_wr_data_addr_w = {wb_wr_data_addr_ns, wb_wr_data_addr0_ns}; end endgenerate // Keep track of how many entries in the queue hold data. input ram_init_done_r; output wire app_wdf_rdy; generate begin : occupied_counter //reg [4:0] occ_cnt_ns; //reg [4:0] occ_cnt_r; //always @(/*AS*/occ_cnt_r or rd_data_upd_indx_r or rst // or wr_data_end) begin // occ_cnt_ns = occ_cnt_r; // if (rst) occ_cnt_ns = 5'b0; // else case ({wr_data_end, rd_data_upd_indx_r}) // 2'b01 : occ_cnt_ns = occ_cnt_r - 5'b1; // 2'b10 : occ_cnt_ns = occ_cnt_r + 5'b1; // endcase // case ({wr_data_end, rd_data_upd_indx_r}) //end //always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns; //assign wdf_rdy_ns = !(rst || ~ram_init_done_r || occ_cnt_ns[4]); //always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns; //assign app_wdf_rdy = app_wdf_rdy_r; reg [15:0] occ_cnt; always @(posedge clk) begin if ( rst ) occ_cnt <= #TCQ 16'h0000; else case ({wr_data_end, rd_data_upd_indx_r}) 2'b01 : occ_cnt <= #TCQ {1'b0,occ_cnt[15:1]}; 2'b10 : occ_cnt <= #TCQ {occ_cnt[14:0],1'b1}; endcase // case ({wr_data_end, rd_data_upd_indx_r}) end assign wdf_rdy_ns = !(rst || ~ram_init_done_r || (occ_cnt[14] && wr_data_end && ~rd_data_upd_indx_r) || (occ_cnt[15] && ~rd_data_upd_indx_r)); always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns; assign app_wdf_rdy = app_wdf_rdy_r; `ifdef MC_SVA wr_data_buffer_full: cover property (@(posedge clk) (~rst && ~app_wdf_rdy_r)); // wr_data_buffer_inc_dec_15: cover property (@(posedge clk) // (~rst && wr_data_end && rd_data_upd_indx_r && (occ_cnt_r == 5'hf))); // wr_data_underflow: assert property (@(posedge clk) // (rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f)))); // wr_data_overflow: assert property (@(posedge clk) // (rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11)))); `endif end // block: occupied_counter endgenerate // Keep track of how many write requests are in the memory controller. We // must limit this to 16 because we only have that many data_buf_addrs to // hand out. Since the memory controller queue and the write data buffer // queue are distinct, the number of valid entries can be different. // Throttle request acceptance once there are sixteen write requests in // the memory controller. Note that there is still a requirement // for a write reqeusts corresponding write data to be written into the // write data queue with two states of the request. output wire wr_req_16; generate begin : wr_req_counter reg [4:0] wr_req_cnt_ns; reg [4:0] wr_req_cnt_r; always @(/*AS*/rd_data_upd_indx_r or rst or wr_accepted or wr_req_cnt_r) begin wr_req_cnt_ns = wr_req_cnt_r; if (rst) wr_req_cnt_ns = 5'b0; else case ({wr_accepted, rd_data_upd_indx_r}) 2'b01 : wr_req_cnt_ns = wr_req_cnt_r - 5'b1; 2'b10 : wr_req_cnt_ns = wr_req_cnt_r + 5'b1; endcase // case ({wr_accepted, rd_data_upd_indx_r}) end always @(posedge clk) wr_req_cnt_r <= #TCQ wr_req_cnt_ns; assign wr_req_16 = (wr_req_cnt_ns == 5'h10); `ifdef MC_SVA wr_req_mc_full: cover property (@(posedge clk) (~rst && wr_req_16)); wr_req_mc_full_inc_dec_15: cover property (@(posedge clk) (~rst && wr_accepted && rd_data_upd_indx_r && (wr_req_cnt_r == 5'hf))); wr_req_underflow: assert property (@(posedge clk) (rst || !((wr_req_cnt_r == 5'b0) && (wr_req_cnt_ns == 5'h1f)))); wr_req_overflow: assert property (@(posedge clk) (rst || !((wr_req_cnt_r == 5'h10) && (wr_req_cnt_ns == 5'h11)))); `endif end // block: wr_req_counter endgenerate // Instantiate pointer RAM. Made up of RAM32M in single write, two read // port mode, 2 bit wide mode. input [3:0] ram_init_addr; output wire [3:0] wr_data_buf_addr; localparam PNTR_RAM_CNT = 2; generate begin : pointer_ram wire pointer_we = new_rd_data || ~ram_init_done_r; wire [3:0] pointer_wr_data = ram_init_done_r ? wr_data_addr_r : ram_init_addr; wire [3:0] pointer_wr_addr = ram_init_done_r ? rd_data_indx_r : ram_init_addr; genvar i; for (i=0; i<PNTR_RAM_CNT; i=i+1) begin : rams RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(), .DOB(wr_data_buf_addr[i*2+:2]), .DOC(wr_data_pntr[i*2+:2]), .DOD(), .DIA(2'b0), .DIB(pointer_wr_data[i*2+:2]), .DIC(pointer_wr_data[i*2+:2]), .DID(2'b0), .ADDRA(5'b0), .ADDRB({1'b0, data_buf_addr_cnt_r}), .ADDRC({1'b0, wr_data_indx_r}), .ADDRD({1'b0, pointer_wr_addr}), .WE(pointer_we), .WCLK(clk) ); end // block : rams end // block: pointer_ram endgenerate // Instantiate write data buffer. Depending on width of DQ bus and // DRAM CK to fabric ratio, number of RAM32Ms is variable. RAM32Ms are // used in single write, single read, 6 bit wide mode. localparam WR_BUF_WIDTH = APP_DATA_WIDTH + APP_MASK_WIDTH + (ECC_TEST == "OFF" ? 0 : 2*nCK_PER_CLK); localparam FULL_RAM_CNT = (WR_BUF_WIDTH/6); localparam REMAINDER = WR_BUF_WIDTH % 6; localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); localparam RAM_WIDTH = (RAM_CNT*6); wire [RAM_WIDTH-1:0] wr_buf_out_data_w; reg [RAM_WIDTH-1:0] wr_buf_out_data; generate begin : write_buffer wire [RAM_WIDTH-1:0] wr_buf_in_data; if (REMAINDER == 0) if (ECC_TEST == "OFF") assign wr_buf_in_data = {app_wdf_mask_ns1, app_wdf_data_ns1}; else assign wr_buf_in_data = {app_raw_not_ecc_r1, app_wdf_mask_ns1, app_wdf_data_ns1}; else if (ECC_TEST == "OFF") assign wr_buf_in_data = {{6-REMAINDER{1'b0}}, app_wdf_mask_ns1, app_wdf_data_ns1}; else assign wr_buf_in_data = {{6-REMAINDER{1'b0}}, app_raw_not_ecc_r1,//app_raw_not_ecc_r1 is not ff app_wdf_mask_ns1, app_wdf_data_ns1}; wire [4:0] rd_addr_w; assign rd_addr_w = {wr_data_addr, wr_data_offset}; always @(posedge clk) wr_buf_out_data <= #TCQ wr_buf_out_data_w; genvar i; for (i=0; i<RAM_CNT; i=i+1) begin : wr_buffer_ram RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(wr_buf_out_data_w[((i*6)+4)+:2]), .DOB(wr_buf_out_data_w[((i*6)+2)+:2]), .DOC(wr_buf_out_data_w[((i*6)+0)+:2]), .DOD(), .DIA(wr_buf_in_data[((i*6)+4)+:2]), .DIB(wr_buf_in_data[((i*6)+2)+:2]), .DIC(wr_buf_in_data[((i*6)+0)+:2]), .DID(2'b0), .ADDRA(rd_addr_w), .ADDRB(rd_addr_w), .ADDRC(rd_addr_w), .ADDRD(wb_wr_data_addr_w), .WE(wdf_rdy_ns), .WCLK(clk) ); end // block: wr_buffer_ram end endgenerate output [APP_DATA_WIDTH-1:0] wr_data; output [APP_MASK_WIDTH-1:0] wr_data_mask; assign {wr_data_mask, wr_data} = wr_buf_out_data[WR_BUF_WIDTH-1:0]; output [2*nCK_PER_CLK-1:0] raw_not_ecc; generate if (ECC_TEST == "OFF") assign raw_not_ecc = {2*nCK_PER_CLK{1'b0}}; else assign raw_not_ecc = wr_buf_out_data[WR_BUF_WIDTH-1-:(2*nCK_PER_CLK)]; endgenerate endmodule // ui_wr_data // Local Variables: // verilog-library-directories:(".") // End:

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ui_wr_data.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // User interface write data buffer. Consists of four counters, // a pointer RAM and the write data storage RAM. // // All RAMs are implemented with distributed RAM. // // Whe ordering is set to STRICT or NORM, data moves through // the write data buffer in strictly FIFO order. In RELAXED // mode, data may be retired from the write data RAM in any // order relative to the input order. This implementation // supports all ordering modes. // // The pointer RAM stores a list of pointers to the write data storage RAM. // This is a list of vacant entries. As data is written into the RAM, a // pointer is pulled from the pointer RAM and used to index the write // operation. In a semi autonomously manner, pointers are also pulled, in // the same order, and provided to the command port as the data_buf_addr. // // When the MC reads data from the write data buffer, it uses the // data_buf_addr provided with the command to extract the data from the // write data buffer. It also writes this pointer into the end // of the pointer RAM. // // The occupancy counter keeps track of how many entries are valid // in the write data storage RAM. app_wdf_rdy and app_rdy will be // de-asserted when there is no more storage in the write data buffer. // // Three sequentially incrementing counters/indexes are used to maintain // and use the contents of the pointer RAM. // // The write buffer write data address index generates the pointer // used to extract the write data address from the pointer RAM. It // is incremented with each buffer write. The counter is actually one // ahead of the current write address so that the actual data buffer // write address can be registered to give a full state to propagate to // the write data distributed RAMs. // // The data_buf_addr counter is used to extract the data_buf_addr for // the command port. It is incremented as each command is written // into the MC. // // The read data index points to the end of the list of free // buffers. When the MC fetches data from the write data buffer, it // provides the buffer address. The buffer address is used to fetch // the data, but is also written into the pointer at the location indicated // by the read data index. // // Enter and exiting a buffer full condition generates corner cases. Upon // entering a full condition, incrementing the write buffer write data // address index must be inhibited. When exiting the full condition, // the just arrived pointer must propagate through the pointer RAM, then // indexed by the current value of the write buffer write data // address counter, the value is registered in the write buffer write // data address register, then the counter can be advanced. // // The pointer RAM must be initialized with valid data after reset. This is // accomplished by stepping through each pointer RAM entry and writing // the locations address into the pointer RAM. For the FIFO modes, this means // that buffer address will always proceed in a sequential order. In the // RELAXED mode, the original write traversal will be in sequential // order, but once the MC begins to retire out of order, the entries in // the pointer RAM will become randomized. The ui_rd_data module provides // the control information for the initialization process. `timescale 1 ps / 1 ps module mig_7series_v2_3_ui_wr_data # ( parameter TCQ = 100, parameter APP_DATA_WIDTH = 256, parameter APP_MASK_WIDTH = 32, parameter ECC = "OFF", parameter nCK_PER_CLK = 2 , parameter ECC_TEST = "OFF", parameter CWL = 5 ) (/*AUTOARG*/ // Outputs app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask, raw_not_ecc, // Inputs rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren, app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted, ram_init_done_r, ram_init_addr ); input rst; input clk; input [APP_DATA_WIDTH-1:0] app_wdf_data; input [APP_MASK_WIDTH-1:0] app_wdf_mask; input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; input app_wdf_wren; input app_wdf_end; reg [APP_DATA_WIDTH-1:0] app_wdf_data_r1; reg [APP_MASK_WIDTH-1:0] app_wdf_mask_r1; reg [2*nCK_PER_CLK-1:0] app_raw_not_ecc_r1 = 4'b0; reg app_wdf_wren_r1; reg app_wdf_end_r1; reg app_wdf_rdy_r; //Adding few copies of the app_wdf_rdy_r signal in order to meet //timing. This is signal has a very high fanout. So grouped into //few functional groups and alloted one copy per group. (* equivalent_register_removal = "no" *) reg app_wdf_rdy_r_copy1; (* equivalent_register_removal = "no" *) reg app_wdf_rdy_r_copy2; (* equivalent_register_removal = "no" *) reg app_wdf_rdy_r_copy3; (* equivalent_register_removal = "no" *) reg app_wdf_rdy_r_copy4; wire [APP_DATA_WIDTH-1:0] app_wdf_data_ns1 = ~app_wdf_rdy_r_copy2 ? app_wdf_data_r1 : app_wdf_data; wire [APP_MASK_WIDTH-1:0] app_wdf_mask_ns1 = ~app_wdf_rdy_r_copy2 ? app_wdf_mask_r1 : app_wdf_mask; wire app_wdf_wren_ns1 = ~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_wren_r1 : app_wdf_wren); wire app_wdf_end_ns1 = ~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_end_r1 : app_wdf_end); generate if (ECC_TEST != "OFF") begin : ecc_on always @(app_raw_not_ecc) app_raw_not_ecc_r1 = app_raw_not_ecc; end endgenerate // Be explicit about the latch enable on these registers. always @(posedge clk) begin app_wdf_data_r1 <= #TCQ app_wdf_data_ns1; app_wdf_mask_r1 <= #TCQ app_wdf_mask_ns1; app_wdf_wren_r1 <= #TCQ app_wdf_wren_ns1; app_wdf_end_r1 <= #TCQ app_wdf_end_ns1; end // The signals wr_data_addr and wr_data_offset come at different // times depending on ECC and the value of CWL. The data portion // always needs to look a the raw wires, the control portion needs // to look at a delayed version when ECC is on and CWL != 8. The // currently supported write data delays do not require this // functionality, but preserve for future use. input wr_data_offset; input [3:0] wr_data_addr; reg wr_data_offset_r; reg [3:0] wr_data_addr_r; generate if (ECC == "OFF" || CWL >= 0) begin : pass_wr_addr always @(wr_data_offset) wr_data_offset_r = wr_data_offset; always @(wr_data_addr) wr_data_addr_r = wr_data_addr; end else begin : delay_wr_addr always @(posedge clk) wr_data_offset_r <= #TCQ wr_data_offset; always @(posedge clk) wr_data_addr_r <= #TCQ wr_data_addr; end endgenerate // rd_data_cnt is the pointer RAM index for data read from the write data // buffer. Ie, its the data on its way out to the DRAM. input wr_data_en; wire new_rd_data = wr_data_en && ~wr_data_offset_r; reg [3:0] rd_data_indx_r; reg rd_data_upd_indx_r; generate begin : read_data_indx reg [3:0] rd_data_indx_ns; always @(/*AS*/new_rd_data or rd_data_indx_r or rst) begin rd_data_indx_ns = rd_data_indx_r; if (rst) rd_data_indx_ns = 5'b0; else if (new_rd_data) rd_data_indx_ns = rd_data_indx_r + 5'h1; end always @(posedge clk) rd_data_indx_r <= #TCQ rd_data_indx_ns; always @(posedge clk) rd_data_upd_indx_r <= #TCQ new_rd_data; end endgenerate // data_buf_addr_cnt generates the pointer for the pointer RAM on behalf // of data buf address that comes with the wr_data_en. // The data buf address is written into the memory // controller along with the command and address. input wr_accepted; reg [3:0] data_buf_addr_cnt_r; generate begin : data_buf_address_counter reg [3:0] data_buf_addr_cnt_ns; always @(/*AS*/data_buf_addr_cnt_r or rst or wr_accepted) begin data_buf_addr_cnt_ns = data_buf_addr_cnt_r; if (rst) data_buf_addr_cnt_ns = 4'b0; else if (wr_accepted) data_buf_addr_cnt_ns = data_buf_addr_cnt_r + 4'h1; end always @(posedge clk) data_buf_addr_cnt_r <= #TCQ data_buf_addr_cnt_ns; end endgenerate // Control writing data into the write data buffer. wire wdf_rdy_ns; always @( posedge clk ) begin app_wdf_rdy_r_copy1 <= #TCQ wdf_rdy_ns; app_wdf_rdy_r_copy2 <= #TCQ wdf_rdy_ns; app_wdf_rdy_r_copy3 <= #TCQ wdf_rdy_ns; app_wdf_rdy_r_copy4 <= #TCQ wdf_rdy_ns; end wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1; wire [3:0] wr_data_pntr; wire [4:0] wb_wr_data_addr; wire [4:0] wb_wr_data_addr_w; reg [3:0] wr_data_indx_r; generate begin : write_data_control wire wr_data_addr_le = (wr_data_end && wdf_rdy_ns) || (rd_data_upd_indx_r && ~app_wdf_rdy_r_copy1); // For pointer RAM. Initialize to one since this is one ahead of // what's being registered in wb_wr_data_addr. Assumes pointer RAM // has been initialized such that address equals contents. reg [3:0] wr_data_indx_ns; always @(/*AS*/rst or wr_data_addr_le or wr_data_indx_r) begin wr_data_indx_ns = wr_data_indx_r; if (rst) wr_data_indx_ns = 4'b1; else if (wr_data_addr_le) wr_data_indx_ns = wr_data_indx_r + 4'h1; end always @(posedge clk) wr_data_indx_r <= #TCQ wr_data_indx_ns; // Take pointer from pointer RAM and set into the write data address. // Needs to be split into zeroth bit and everything else because synthesis // tools don't always allow assigning bit vectors seperately. Bit zero of the // address is computed via an entirely different algorithm. reg [4:1] wb_wr_data_addr_ns; reg [4:1] wb_wr_data_addr_r; always @(/*AS*/rst or wb_wr_data_addr_r or wr_data_addr_le or wr_data_pntr) begin wb_wr_data_addr_ns = wb_wr_data_addr_r; if (rst) wb_wr_data_addr_ns = 4'b0; else if (wr_data_addr_le) wb_wr_data_addr_ns = wr_data_pntr; end always @(posedge clk) wb_wr_data_addr_r <= #TCQ wb_wr_data_addr_ns; // If we see the first getting accepted, then // second half is unconditionally accepted. reg wb_wr_data_addr0_r; wire wb_wr_data_addr0_ns = ~rst && ((app_wdf_rdy_r_copy3 && app_wdf_wren_r1 && ~app_wdf_end_r1) || (wb_wr_data_addr0_r && ~app_wdf_wren_r1)); always @(posedge clk) wb_wr_data_addr0_r <= #TCQ wb_wr_data_addr0_ns; assign wb_wr_data_addr = {wb_wr_data_addr_r, wb_wr_data_addr0_r}; assign wb_wr_data_addr_w = {wb_wr_data_addr_ns, wb_wr_data_addr0_ns}; end endgenerate // Keep track of how many entries in the queue hold data. input ram_init_done_r; output wire app_wdf_rdy; generate begin : occupied_counter //reg [4:0] occ_cnt_ns; //reg [4:0] occ_cnt_r; //always @(/*AS*/occ_cnt_r or rd_data_upd_indx_r or rst // or wr_data_end) begin // occ_cnt_ns = occ_cnt_r; // if (rst) occ_cnt_ns = 5'b0; // else case ({wr_data_end, rd_data_upd_indx_r}) // 2'b01 : occ_cnt_ns = occ_cnt_r - 5'b1; // 2'b10 : occ_cnt_ns = occ_cnt_r + 5'b1; // endcase // case ({wr_data_end, rd_data_upd_indx_r}) //end //always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns; //assign wdf_rdy_ns = !(rst || ~ram_init_done_r || occ_cnt_ns[4]); //always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns; //assign app_wdf_rdy = app_wdf_rdy_r; reg [15:0] occ_cnt; always @(posedge clk) begin if ( rst ) occ_cnt <= #TCQ 16'h0000; else case ({wr_data_end, rd_data_upd_indx_r}) 2'b01 : occ_cnt <= #TCQ {1'b0,occ_cnt[15:1]}; 2'b10 : occ_cnt <= #TCQ {occ_cnt[14:0],1'b1}; endcase // case ({wr_data_end, rd_data_upd_indx_r}) end assign wdf_rdy_ns = !(rst || ~ram_init_done_r || (occ_cnt[14] && wr_data_end && ~rd_data_upd_indx_r) || (occ_cnt[15] && ~rd_data_upd_indx_r)); always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns; assign app_wdf_rdy = app_wdf_rdy_r; `ifdef MC_SVA wr_data_buffer_full: cover property (@(posedge clk) (~rst && ~app_wdf_rdy_r)); // wr_data_buffer_inc_dec_15: cover property (@(posedge clk) // (~rst && wr_data_end && rd_data_upd_indx_r && (occ_cnt_r == 5'hf))); // wr_data_underflow: assert property (@(posedge clk) // (rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f)))); // wr_data_overflow: assert property (@(posedge clk) // (rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11)))); `endif end // block: occupied_counter endgenerate // Keep track of how many write requests are in the memory controller. We // must limit this to 16 because we only have that many data_buf_addrs to // hand out. Since the memory controller queue and the write data buffer // queue are distinct, the number of valid entries can be different. // Throttle request acceptance once there are sixteen write requests in // the memory controller. Note that there is still a requirement // for a write reqeusts corresponding write data to be written into the // write data queue with two states of the request. output wire wr_req_16; generate begin : wr_req_counter reg [4:0] wr_req_cnt_ns; reg [4:0] wr_req_cnt_r; always @(/*AS*/rd_data_upd_indx_r or rst or wr_accepted or wr_req_cnt_r) begin wr_req_cnt_ns = wr_req_cnt_r; if (rst) wr_req_cnt_ns = 5'b0; else case ({wr_accepted, rd_data_upd_indx_r}) 2'b01 : wr_req_cnt_ns = wr_req_cnt_r - 5'b1; 2'b10 : wr_req_cnt_ns = wr_req_cnt_r + 5'b1; endcase // case ({wr_accepted, rd_data_upd_indx_r}) end always @(posedge clk) wr_req_cnt_r <= #TCQ wr_req_cnt_ns; assign wr_req_16 = (wr_req_cnt_ns == 5'h10); `ifdef MC_SVA wr_req_mc_full: cover property (@(posedge clk) (~rst && wr_req_16)); wr_req_mc_full_inc_dec_15: cover property (@(posedge clk) (~rst && wr_accepted && rd_data_upd_indx_r && (wr_req_cnt_r == 5'hf))); wr_req_underflow: assert property (@(posedge clk) (rst || !((wr_req_cnt_r == 5'b0) && (wr_req_cnt_ns == 5'h1f)))); wr_req_overflow: assert property (@(posedge clk) (rst || !((wr_req_cnt_r == 5'h10) && (wr_req_cnt_ns == 5'h11)))); `endif end // block: wr_req_counter endgenerate // Instantiate pointer RAM. Made up of RAM32M in single write, two read // port mode, 2 bit wide mode. input [3:0] ram_init_addr; output wire [3:0] wr_data_buf_addr; localparam PNTR_RAM_CNT = 2; generate begin : pointer_ram wire pointer_we = new_rd_data || ~ram_init_done_r; wire [3:0] pointer_wr_data = ram_init_done_r ? wr_data_addr_r : ram_init_addr; wire [3:0] pointer_wr_addr = ram_init_done_r ? rd_data_indx_r : ram_init_addr; genvar i; for (i=0; i<PNTR_RAM_CNT; i=i+1) begin : rams RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(), .DOB(wr_data_buf_addr[i*2+:2]), .DOC(wr_data_pntr[i*2+:2]), .DOD(), .DIA(2'b0), .DIB(pointer_wr_data[i*2+:2]), .DIC(pointer_wr_data[i*2+:2]), .DID(2'b0), .ADDRA(5'b0), .ADDRB({1'b0, data_buf_addr_cnt_r}), .ADDRC({1'b0, wr_data_indx_r}), .ADDRD({1'b0, pointer_wr_addr}), .WE(pointer_we), .WCLK(clk) ); end // block : rams end // block: pointer_ram endgenerate // Instantiate write data buffer. Depending on width of DQ bus and // DRAM CK to fabric ratio, number of RAM32Ms is variable. RAM32Ms are // used in single write, single read, 6 bit wide mode. localparam WR_BUF_WIDTH = APP_DATA_WIDTH + APP_MASK_WIDTH + (ECC_TEST == "OFF" ? 0 : 2*nCK_PER_CLK); localparam FULL_RAM_CNT = (WR_BUF_WIDTH/6); localparam REMAINDER = WR_BUF_WIDTH % 6; localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); localparam RAM_WIDTH = (RAM_CNT*6); wire [RAM_WIDTH-1:0] wr_buf_out_data_w; reg [RAM_WIDTH-1:0] wr_buf_out_data; generate begin : write_buffer wire [RAM_WIDTH-1:0] wr_buf_in_data; if (REMAINDER == 0) if (ECC_TEST == "OFF") assign wr_buf_in_data = {app_wdf_mask_ns1, app_wdf_data_ns1}; else assign wr_buf_in_data = {app_raw_not_ecc_r1, app_wdf_mask_ns1, app_wdf_data_ns1}; else if (ECC_TEST == "OFF") assign wr_buf_in_data = {{6-REMAINDER{1'b0}}, app_wdf_mask_ns1, app_wdf_data_ns1}; else assign wr_buf_in_data = {{6-REMAINDER{1'b0}}, app_raw_not_ecc_r1,//app_raw_not_ecc_r1 is not ff app_wdf_mask_ns1, app_wdf_data_ns1}; wire [4:0] rd_addr_w; assign rd_addr_w = {wr_data_addr, wr_data_offset}; always @(posedge clk) wr_buf_out_data <= #TCQ wr_buf_out_data_w; genvar i; for (i=0; i<RAM_CNT; i=i+1) begin : wr_buffer_ram RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(wr_buf_out_data_w[((i*6)+4)+:2]), .DOB(wr_buf_out_data_w[((i*6)+2)+:2]), .DOC(wr_buf_out_data_w[((i*6)+0)+:2]), .DOD(), .DIA(wr_buf_in_data[((i*6)+4)+:2]), .DIB(wr_buf_in_data[((i*6)+2)+:2]), .DIC(wr_buf_in_data[((i*6)+0)+:2]), .DID(2'b0), .ADDRA(rd_addr_w), .ADDRB(rd_addr_w), .ADDRC(rd_addr_w), .ADDRD(wb_wr_data_addr_w), .WE(wdf_rdy_ns), .WCLK(clk) ); end // block: wr_buffer_ram end endgenerate output [APP_DATA_WIDTH-1:0] wr_data; output [APP_MASK_WIDTH-1:0] wr_data_mask; assign {wr_data_mask, wr_data} = wr_buf_out_data[WR_BUF_WIDTH-1:0]; output [2*nCK_PER_CLK-1:0] raw_not_ecc; generate if (ECC_TEST == "OFF") assign raw_not_ecc = {2*nCK_PER_CLK{1'b0}}; else assign raw_not_ecc = wr_buf_out_data[WR_BUF_WIDTH-1-:(2*nCK_PER_CLK)]; endgenerate endmodule // ui_wr_data // Local Variables: // verilog-library-directories:(".") // End:

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_v2_3_phy_ocd_samp.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Controls the number of samples and generates an aggregate //sampling result. // // The following shows the nesting of the sampling loop. Nominally built // to accomodate the "complex" sampling protocol. Adapted for use with // "simple" samplng. // // simple complex // // samples OCAL_SIMPLE_SCAN_SAMPS 1 or 50 Depends on SIM_CAL_OPTION // rd_victim_sel 0 0 to 7 // data_cnt 1 157 // // First it collects comparison results provided on the // two bit "match" bus. A particular phaser tap setting may be recorded one // or many times depending on various parameter settings. // The two bit match bus corresponds to comparisons for the // zero or rising phase, and the oneeighty or falling phase. The "aggregate" // starts out as NULL and then begins collecting comparison results // when phy_rddata_en_1 is high. The first result is always set into // the aggregate result. Subsequent results that match aggregate, don't // make any change. Subsequent compare results that don't match cause the aggregate // to turn to FUZZ. // // A "sample" is defined as a single DRAM burst for the simple step, and // an entire 157 DRAM data bursts across the 8 victim bits for complex. // // Once all samples have been taken, the samp_result is computed by // comparing the number of successful compares against the threshold. // // The second function is to track and control the number of samples. For // "simple" data, the number of samples is set by OCAL_SIMPLE_SCAN_SAMPS. // For "complex" data, nominally // the complex data pattern consists of a sequence of 157 DRAM chunks. This // sequence is run with each bit in the byte designated as the "victim". This sequence // is repeated 50 times, although when SIM_CAL_OPTION is set to none "NONE", it is only // repeated once. // // This block generates oclk_calib_resume. For the simple pattern, a single DRAM // burst is returned For complex its 157 which indicates the start of the 157*50 // sequence for a bit. samp_done is pulsed. // //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_ocd_samp # (parameter nCK_PER_CLK = 4, parameter OCAL_SIMPLE_SCAN_SAMPS = 2, parameter SCAN_PCT_SAMPS_SOLID = 95, parameter TCQ = 100, parameter SIM_CAL_OPTION = "NONE") (/*AUTOARG*/ // Outputs samp_done, oclk_calib_resume, rd_victim_sel, samp_result, // Inputs complex_oclkdelay_calib_start, clk, rst, reset_scan, ocal_num_samples_inc, match, phy_rddata_en_1, taps_set ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam ONE = 1; localparam CMPLX_DATA_CNT = nCK_PER_CLK == 2 ? 157 * 2 : 157; localparam SIMP_DATA_CNT = nCK_PER_CLK == 2 ? 2 : 1; localparam DATA_CNT_WIDTH = nCK_PER_CLK == 2 ? 9 : 8; localparam CMPLX_SAMPS = SIM_CAL_OPTION == "NONE" ? 50 : 1; // Plus one because were counting in natural numbers. localparam SAMP_CNT_WIDTH = clogb2(OCAL_SIMPLE_SCAN_SAMPS > CMPLX_SAMPS ? OCAL_SIMPLE_SCAN_SAMPS : CMPLX_SAMPS) + 1; // Remember SAMPLES is natural number counting. One corresponds to one sample. localparam integer SIMP_SAMPS_SOLID_THRESH = OCAL_SIMPLE_SCAN_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01; localparam integer CMPLX_SAMPS_SOLID_THRESH = CMPLX_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01; input complex_oclkdelay_calib_start; wire [SAMP_CNT_WIDTH-1:0] samples = complex_oclkdelay_calib_start ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0] : OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0]; localparam [1:0] NULL = 2'b11, FUZZ = 2'b00, ONEEIGHTY = 2'b10, ZERO = 2'b01; input clk; input rst; input reset_scan; // Given the need to count phy_data_en, this is not useful. input ocal_num_samples_inc; input [1:0] match; input phy_rddata_en_1; input taps_set; reg samp_done_ns, samp_done_r; always @(posedge clk) samp_done_r <= #TCQ samp_done_ns; output samp_done; assign samp_done = samp_done_r; reg [1:0] agg_samp_ns, agg_samp_r; always @(posedge clk) agg_samp_r <= #TCQ agg_samp_ns; reg oclk_calib_resume_ns, oclk_calib_resume_r; always @(posedge clk) oclk_calib_resume_r <= #TCQ oclk_calib_resume_ns; output oclk_calib_resume; assign oclk_calib_resume = oclk_calib_resume_r; // Complex data counting. // Inner most loop. 157 phy_data_en. reg [DATA_CNT_WIDTH-1:0] data_cnt_ns, data_cnt_r; always @(posedge clk) data_cnt_r <= #TCQ data_cnt_ns; // Nominally, 50 samples of the above 157 phy_data_en. reg [SAMP_CNT_WIDTH-1:0] samps_ns, samps_r; always @(posedge clk) samps_r <= #TCQ samps_ns; // Step through the 8 bits in the byte. reg [2:0] rd_victim_sel_ns, rd_victim_sel_r; always @(posedge clk) rd_victim_sel_r <= #TCQ rd_victim_sel_ns; output [2:0] rd_victim_sel; assign rd_victim_sel = rd_victim_sel_r; reg [SAMP_CNT_WIDTH-1:0] zero_ns, zero_r, oneeighty_ns, oneeighty_r; always @(posedge clk) zero_r <= #TCQ zero_ns; always @(posedge clk) oneeighty_r <= #TCQ oneeighty_ns; output [1:0] samp_result; assign samp_result[0] = zero_r >= (complex_oclkdelay_calib_start ? CMPLX_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0] : SIMP_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]); assign samp_result[1] = oneeighty_r >= (complex_oclkdelay_calib_start ? CMPLX_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0] : SIMP_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]); reg [0:0] sm_ns, sm_r; always @(posedge clk) sm_r <= #TCQ sm_ns; wire [DATA_CNT_WIDTH-1:0] data_cnt = complex_oclkdelay_calib_start ? CMPLX_DATA_CNT[DATA_CNT_WIDTH-1:0] : SIMP_DATA_CNT[DATA_CNT_WIDTH-1:0]; wire [2:0] rd_victim_end = complex_oclkdelay_calib_start ? 3'h7 : 3'h0; wire data_end = data_cnt_r == ONE[DATA_CNT_WIDTH-1:0]; wire samp_end = samps_r == ONE[SAMP_CNT_WIDTH-1:0]; // Primary state machine. always @(*) begin // Default next state assignments. agg_samp_ns = agg_samp_r; data_cnt_ns = data_cnt_r; oclk_calib_resume_ns = 1'b0; oneeighty_ns = oneeighty_r; rd_victim_sel_ns = rd_victim_sel_r; samp_done_ns = samp_done_r; samps_ns = samps_r; sm_ns = sm_r; zero_ns = zero_r; if (rst == 1'b1) begin // RESET next states sm_ns = /*AK("READY")*/1'd0; end else // State based actions and next states. case (sm_r) /*AL("READY")*/1'd0:begin agg_samp_ns = NULL; data_cnt_ns = data_cnt; oneeighty_ns = {SAMP_CNT_WIDTH{1'b0}}; rd_victim_sel_ns = 3'b0; samps_ns = complex_oclkdelay_calib_start ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0] : OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0]; zero_ns = {SAMP_CNT_WIDTH{1'b0}}; if (taps_set) begin samp_done_ns = 1'b0; sm_ns = /*AK("AWAITING_DATA")*/1'd1; oclk_calib_resume_ns = 1'b1; end end /*AL("AWAITING_DATA")*/1'd1:begin if (phy_rddata_en_1) begin case (agg_samp_r) NULL : if (~&match) agg_samp_ns = match; ZERO, ONEEIGHTY : if (~(agg_samp_r == match || &match)) agg_samp_ns = FUZZ; FUZZ : ; endcase // case (agg_samp_r) if (~data_end) data_cnt_ns = data_cnt_r - ONE[DATA_CNT_WIDTH-1:0]; else begin data_cnt_ns = data_cnt; if (rd_victim_end != rd_victim_sel_r) rd_victim_sel_ns = rd_victim_sel_r + 3'h1; else begin rd_victim_sel_ns = 3'h0; if (agg_samp_ns == ZERO) zero_ns = zero_r + ONE[SAMP_CNT_WIDTH-1:0]; if (agg_samp_ns == ONEEIGHTY) oneeighty_ns = oneeighty_r + ONE[SAMP_CNT_WIDTH-1:0]; agg_samp_ns = NULL; if (~samp_end) samps_ns = samps_r - ONE[SAMP_CNT_WIDTH-1:0]; else samp_done_ns = 1'b1; end end if (samp_done_ns) sm_ns = /*AK("READY")*/1'd0; else oclk_calib_resume_ns = ~complex_oclkdelay_calib_start && data_end; end end endcase // case (sm_r) end // always @ begin endmodule // mig_7series_v2_3_ddr_phy_ocd_samp // Local Variables: // verilog-autolabel-prefix: "1'd" // End:

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_v2_3_phy_ocd_samp.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Controls the number of samples and generates an aggregate //sampling result. // // The following shows the nesting of the sampling loop. Nominally built // to accomodate the "complex" sampling protocol. Adapted for use with // "simple" samplng. // // simple complex // // samples OCAL_SIMPLE_SCAN_SAMPS 1 or 50 Depends on SIM_CAL_OPTION // rd_victim_sel 0 0 to 7 // data_cnt 1 157 // // First it collects comparison results provided on the // two bit "match" bus. A particular phaser tap setting may be recorded one // or many times depending on various parameter settings. // The two bit match bus corresponds to comparisons for the // zero or rising phase, and the oneeighty or falling phase. The "aggregate" // starts out as NULL and then begins collecting comparison results // when phy_rddata_en_1 is high. The first result is always set into // the aggregate result. Subsequent results that match aggregate, don't // make any change. Subsequent compare results that don't match cause the aggregate // to turn to FUZZ. // // A "sample" is defined as a single DRAM burst for the simple step, and // an entire 157 DRAM data bursts across the 8 victim bits for complex. // // Once all samples have been taken, the samp_result is computed by // comparing the number of successful compares against the threshold. // // The second function is to track and control the number of samples. For // "simple" data, the number of samples is set by OCAL_SIMPLE_SCAN_SAMPS. // For "complex" data, nominally // the complex data pattern consists of a sequence of 157 DRAM chunks. This // sequence is run with each bit in the byte designated as the "victim". This sequence // is repeated 50 times, although when SIM_CAL_OPTION is set to none "NONE", it is only // repeated once. // // This block generates oclk_calib_resume. For the simple pattern, a single DRAM // burst is returned For complex its 157 which indicates the start of the 157*50 // sequence for a bit. samp_done is pulsed. // //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_ocd_samp # (parameter nCK_PER_CLK = 4, parameter OCAL_SIMPLE_SCAN_SAMPS = 2, parameter SCAN_PCT_SAMPS_SOLID = 95, parameter TCQ = 100, parameter SIM_CAL_OPTION = "NONE") (/*AUTOARG*/ // Outputs samp_done, oclk_calib_resume, rd_victim_sel, samp_result, // Inputs complex_oclkdelay_calib_start, clk, rst, reset_scan, ocal_num_samples_inc, match, phy_rddata_en_1, taps_set ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam ONE = 1; localparam CMPLX_DATA_CNT = nCK_PER_CLK == 2 ? 157 * 2 : 157; localparam SIMP_DATA_CNT = nCK_PER_CLK == 2 ? 2 : 1; localparam DATA_CNT_WIDTH = nCK_PER_CLK == 2 ? 9 : 8; localparam CMPLX_SAMPS = SIM_CAL_OPTION == "NONE" ? 50 : 1; // Plus one because were counting in natural numbers. localparam SAMP_CNT_WIDTH = clogb2(OCAL_SIMPLE_SCAN_SAMPS > CMPLX_SAMPS ? OCAL_SIMPLE_SCAN_SAMPS : CMPLX_SAMPS) + 1; // Remember SAMPLES is natural number counting. One corresponds to one sample. localparam integer SIMP_SAMPS_SOLID_THRESH = OCAL_SIMPLE_SCAN_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01; localparam integer CMPLX_SAMPS_SOLID_THRESH = CMPLX_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01; input complex_oclkdelay_calib_start; wire [SAMP_CNT_WIDTH-1:0] samples = complex_oclkdelay_calib_start ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0] : OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0]; localparam [1:0] NULL = 2'b11, FUZZ = 2'b00, ONEEIGHTY = 2'b10, ZERO = 2'b01; input clk; input rst; input reset_scan; // Given the need to count phy_data_en, this is not useful. input ocal_num_samples_inc; input [1:0] match; input phy_rddata_en_1; input taps_set; reg samp_done_ns, samp_done_r; always @(posedge clk) samp_done_r <= #TCQ samp_done_ns; output samp_done; assign samp_done = samp_done_r; reg [1:0] agg_samp_ns, agg_samp_r; always @(posedge clk) agg_samp_r <= #TCQ agg_samp_ns; reg oclk_calib_resume_ns, oclk_calib_resume_r; always @(posedge clk) oclk_calib_resume_r <= #TCQ oclk_calib_resume_ns; output oclk_calib_resume; assign oclk_calib_resume = oclk_calib_resume_r; // Complex data counting. // Inner most loop. 157 phy_data_en. reg [DATA_CNT_WIDTH-1:0] data_cnt_ns, data_cnt_r; always @(posedge clk) data_cnt_r <= #TCQ data_cnt_ns; // Nominally, 50 samples of the above 157 phy_data_en. reg [SAMP_CNT_WIDTH-1:0] samps_ns, samps_r; always @(posedge clk) samps_r <= #TCQ samps_ns; // Step through the 8 bits in the byte. reg [2:0] rd_victim_sel_ns, rd_victim_sel_r; always @(posedge clk) rd_victim_sel_r <= #TCQ rd_victim_sel_ns; output [2:0] rd_victim_sel; assign rd_victim_sel = rd_victim_sel_r; reg [SAMP_CNT_WIDTH-1:0] zero_ns, zero_r, oneeighty_ns, oneeighty_r; always @(posedge clk) zero_r <= #TCQ zero_ns; always @(posedge clk) oneeighty_r <= #TCQ oneeighty_ns; output [1:0] samp_result; assign samp_result[0] = zero_r >= (complex_oclkdelay_calib_start ? CMPLX_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0] : SIMP_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]); assign samp_result[1] = oneeighty_r >= (complex_oclkdelay_calib_start ? CMPLX_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0] : SIMP_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]); reg [0:0] sm_ns, sm_r; always @(posedge clk) sm_r <= #TCQ sm_ns; wire [DATA_CNT_WIDTH-1:0] data_cnt = complex_oclkdelay_calib_start ? CMPLX_DATA_CNT[DATA_CNT_WIDTH-1:0] : SIMP_DATA_CNT[DATA_CNT_WIDTH-1:0]; wire [2:0] rd_victim_end = complex_oclkdelay_calib_start ? 3'h7 : 3'h0; wire data_end = data_cnt_r == ONE[DATA_CNT_WIDTH-1:0]; wire samp_end = samps_r == ONE[SAMP_CNT_WIDTH-1:0]; // Primary state machine. always @(*) begin // Default next state assignments. agg_samp_ns = agg_samp_r; data_cnt_ns = data_cnt_r; oclk_calib_resume_ns = 1'b0; oneeighty_ns = oneeighty_r; rd_victim_sel_ns = rd_victim_sel_r; samp_done_ns = samp_done_r; samps_ns = samps_r; sm_ns = sm_r; zero_ns = zero_r; if (rst == 1'b1) begin // RESET next states sm_ns = /*AK("READY")*/1'd0; end else // State based actions and next states. case (sm_r) /*AL("READY")*/1'd0:begin agg_samp_ns = NULL; data_cnt_ns = data_cnt; oneeighty_ns = {SAMP_CNT_WIDTH{1'b0}}; rd_victim_sel_ns = 3'b0; samps_ns = complex_oclkdelay_calib_start ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0] : OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0]; zero_ns = {SAMP_CNT_WIDTH{1'b0}}; if (taps_set) begin samp_done_ns = 1'b0; sm_ns = /*AK("AWAITING_DATA")*/1'd1; oclk_calib_resume_ns = 1'b1; end end /*AL("AWAITING_DATA")*/1'd1:begin if (phy_rddata_en_1) begin case (agg_samp_r) NULL : if (~&match) agg_samp_ns = match; ZERO, ONEEIGHTY : if (~(agg_samp_r == match || &match)) agg_samp_ns = FUZZ; FUZZ : ; endcase // case (agg_samp_r) if (~data_end) data_cnt_ns = data_cnt_r - ONE[DATA_CNT_WIDTH-1:0]; else begin data_cnt_ns = data_cnt; if (rd_victim_end != rd_victim_sel_r) rd_victim_sel_ns = rd_victim_sel_r + 3'h1; else begin rd_victim_sel_ns = 3'h0; if (agg_samp_ns == ZERO) zero_ns = zero_r + ONE[SAMP_CNT_WIDTH-1:0]; if (agg_samp_ns == ONEEIGHTY) oneeighty_ns = oneeighty_r + ONE[SAMP_CNT_WIDTH-1:0]; agg_samp_ns = NULL; if (~samp_end) samps_ns = samps_r - ONE[SAMP_CNT_WIDTH-1:0]; else samp_done_ns = 1'b1; end end if (samp_done_ns) sm_ns = /*AK("READY")*/1'd0; else oclk_calib_resume_ns = ~complex_oclkdelay_calib_start && data_end; end end endcase // case (sm_r) end // always @ begin endmodule // mig_7series_v2_3_ddr_phy_ocd_samp // Local Variables: // verilog-autolabel-prefix: "1'd" // End:

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : col_mach.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // The column machine manages the dq bus. Since there is a single DQ // bus, and the column part of the DRAM is tightly coupled to this DQ // bus, conceptually, the DQ bus and all of the column hardware in // a multi rank DRAM array are managed as a single unit. // // // The column machine does not "enforce" the column timing directly. // It generates information and sends it to the bank machines. If the // bank machines incorrectly make a request, the column machine will // simply overwrite the existing request with the new request even // if this would result in a timing or protocol violation. // // The column machine // hosts the block that controls read and write data transfer // to and from the dq bus. // // And if configured, there is provision for tracking the address // of a command as it moves through the column pipeline. This // address will be logged for detected ECC errors. `timescale 1 ps / 1 ps module mig_7series_v2_3_col_mach # ( parameter TCQ = 100, parameter BANK_WIDTH = 3, parameter BURST_MODE = "8", parameter COL_WIDTH = 12, parameter CS_WIDTH = 4, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DATA_BUF_OFFSET_WIDTH = 1, parameter DELAY_WR_DATA_CNTRL = 0, parameter DQS_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter EARLY_WR_DATA_ADDR = "OFF", parameter ECC = "OFF", parameter MC_ERR_ADDR_WIDTH = 31, parameter nCK_PER_CLK = 2, parameter nPHY_WRLAT = 0, parameter RANK_WIDTH = 2, parameter ROW_WIDTH = 16 ) (/*AUTOARG*/ // Outputs dq_busy_data, wr_data_offset, mc_wrdata_en, wr_data_en, wr_data_addr, rd_rmw, ecc_err_addr, ecc_status_valid, wr_ecc_buf, rd_data_end, rd_data_addr, rd_data_offset, rd_data_en, col_read_fifo_empty, // Inputs clk, rst, sent_col, col_size, col_wr_data_buf_addr, phy_rddata_valid, col_periodic_rd, col_data_buf_addr, col_rmw, col_rd_wr, col_ra, col_ba, col_row, col_a ); input clk; input rst; input sent_col; input col_rd_wr; output reg dq_busy_data = 1'b0; // The following generates a column command disable based mostly on the type // of DRAM and the fabric to DRAM CK ratio. generate if ((nCK_PER_CLK == 1) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3"))) begin : three_bumps reg [1:0] granted_col_d_r; wire [1:0] granted_col_d_ns = {sent_col, granted_col_d_r[1]}; always @(posedge clk) granted_col_d_r <= #TCQ granted_col_d_ns; always @(/*AS*/granted_col_d_r or sent_col) dq_busy_data = sent_col || |granted_col_d_r; end if (((nCK_PER_CLK == 2) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3"))) || ((nCK_PER_CLK == 1) && ((BURST_MODE == "4") || (DRAM_TYPE == "DDR2")))) begin : one_bump always @(/*AS*/sent_col) dq_busy_data = sent_col; end endgenerate // This generates a data offset based on fabric clock to DRAM CK ratio and // the size bit. Note that this is different that the dq_busy_data signal // generated above. reg [1:0] offset_r = 2'b0; reg [1:0] offset_ns = 2'b0; input col_size; wire data_end; generate if(nCK_PER_CLK == 4) begin : data_valid_4_1 // For 4:1 mode all data is transfered in a single beat so the default // values of 0 for offset_r/offset_ns suffice - just tie off data_end assign data_end = 1'b1; end else begin if(DATA_BUF_OFFSET_WIDTH == 2) begin : data_valid_1_1 always @(col_size or offset_r or rst or sent_col) begin if (rst) offset_ns = 2'b0; else begin offset_ns = offset_r; if (sent_col) offset_ns = 2'b1; else if (|offset_r && (offset_r != {col_size, 1'b1})) offset_ns = offset_r + 2'b1; else offset_ns = 2'b0; end end always @(posedge clk) offset_r <= #TCQ offset_ns; assign data_end = col_size ? (offset_r == 2'b11) : offset_r[0]; end else begin : data_valid_2_1 always @(col_size or rst or sent_col) offset_ns[0] = rst ? 1'b0 : sent_col && col_size; always @(posedge clk) offset_r[0] <= #TCQ offset_ns[0]; assign data_end = col_size ? offset_r[0] : 1'b1; end end endgenerate reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r1 = {DATA_BUF_OFFSET_WIDTH{1'b0}}; reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r2 = {DATA_BUF_OFFSET_WIDTH{1'b0}}; reg col_rd_wr_r1; reg col_rd_wr_r2; generate if ((nPHY_WRLAT >= 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0 always @(posedge clk) offset_r1 <= #TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0]; always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr; end if(nPHY_WRLAT == 2) begin : offset_pipe_1 always @(posedge clk) offset_r2 <= #TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]; always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1; end endgenerate output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset; assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1) ? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0] : (EARLY_WR_DATA_ADDR == "OFF") ? offset_r[DATA_BUF_OFFSET_WIDTH-1:0] : offset_ns[DATA_BUF_OFFSET_WIDTH-1:0]; reg sent_col_r1; reg sent_col_r2; always @(posedge clk) sent_col_r1 <= #TCQ sent_col; always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1; wire wrdata_en = (nPHY_WRLAT == 0) ? (sent_col || |offset_r) & ~col_rd_wr : (nPHY_WRLAT == 1) ? (sent_col_r1 || |offset_r1) & ~col_rd_wr_r1 : //(nPHY_WRLAT >= 2) ? (sent_col_r2 || |offset_r2) & ~col_rd_wr_r2; output wire mc_wrdata_en; assign mc_wrdata_en = wrdata_en; output wire wr_data_en; assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1) ? ((sent_col_r1 || |offset_r1) && ~col_rd_wr_r1) : ((sent_col || |offset_r) && ~col_rd_wr); input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr; output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; generate if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1 reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r; always @(posedge clk) col_wr_data_buf_addr_r <= #TCQ col_wr_data_buf_addr; assign wr_data_addr = col_wr_data_buf_addr_r; end else begin : delay_wr_data_cntrl_ne_1 assign wr_data_addr = col_wr_data_buf_addr; end endgenerate // CAS-RD to mc_rddata_en wire read_data_valid = (sent_col || |offset_r) && col_rd_wr; function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 // Implement FIFO that records reads as they are sent to the DRAM. // When phy_rddata_valid is returned some unknown time later, the // FIFO output is used to control how the data is interpreted. input phy_rddata_valid; output wire rd_rmw; output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr; output reg ecc_status_valid; output reg wr_ecc_buf; output reg rd_data_end; output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset; output reg rd_data_en /* synthesis syn_maxfan = 10 */; output col_read_fifo_empty; input col_periodic_rd; input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr; input col_rmw; input [RANK_WIDTH-1:0] col_ra; input [BANK_WIDTH-1:0] col_ba; input [ROW_WIDTH-1:0] col_row; input [ROW_WIDTH-1:0] col_a; // Real column address (skip A10/AP and A12/BC#). The maximum width is 12; // the width will be tailored for the target DRAM downstream. wire [11:0] col_a_full; // Minimum row width is 12; take remaining 11 bits after omitting A10/AP assign col_a_full[10:0] = {col_a[11], col_a[9:0]}; // Get the 12th bit when row address width accommodates it; omit A12/BC# generate if (ROW_WIDTH >= 14) begin : COL_A_FULL_11_1 assign col_a_full[11] = col_a[13]; end else begin : COL_A_FULL_11_0 assign col_a_full[11] = 0; end endgenerate // Extract only the width of the target DRAM wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0]; localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH; localparam FIFO_WIDTH = 1 /*data_end*/ + 1 /*periodic_rd*/ + DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH + ((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH); localparam FULL_RAM_CNT = (FIFO_WIDTH/6); localparam REMAINDER = FIFO_WIDTH % 6; localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); localparam RAM_WIDTH = (RAM_CNT*6); generate begin : read_fifo wire [MC_ERR_LINE_WIDTH:0] ecc_line; if (CS_WIDTH == 1) assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted}; else assign ecc_line = {col_rmw, col_ra, col_ba, col_row, col_a_extracted}; wire [FIFO_WIDTH-1:0] real_fifo_data; if (ECC == "OFF") assign real_fifo_data = {data_end, col_periodic_rd, col_data_buf_addr, offset_r[DATA_BUF_OFFSET_WIDTH-1:0]}; else assign real_fifo_data = {data_end, col_periodic_rd, col_data_buf_addr, offset_r[DATA_BUF_OFFSET_WIDTH-1:0], ecc_line}; wire [RAM_WIDTH-1:0] fifo_in_data; if (REMAINDER == 0) assign fifo_in_data = real_fifo_data; else assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data}; wire [RAM_WIDTH-1:0] fifo_out_data_ns; reg [4:0] head_r; wire [4:0] head_ns = rst ? 5'b0 : read_data_valid ? (head_r + 5'b1) : head_r; always @(posedge clk) head_r <= #TCQ head_ns; reg [4:0] tail_r; wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid ? (tail_r + 5'b1) : tail_r; always @(posedge clk) tail_r <= #TCQ tail_ns; assign col_read_fifo_empty = head_r == tail_r ? 1'b1 : 1'b0; genvar i; for (i=0; i<RAM_CNT; i=i+1) begin : fifo_ram RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(fifo_out_data_ns[((i*6)+4)+:2]), .DOB(fifo_out_data_ns[((i*6)+2)+:2]), .DOC(fifo_out_data_ns[((i*6)+0)+:2]), .DOD(), .DIA(fifo_in_data[((i*6)+4)+:2]), .DIB(fifo_in_data[((i*6)+2)+:2]), .DIC(fifo_in_data[((i*6)+0)+:2]), .DID(2'b0), .ADDRA(tail_ns), .ADDRB(tail_ns), .ADDRC(tail_ns), .ADDRD(head_r), .WE(1'b1), .WCLK(clk) ); end // block: fifo_ram reg [RAM_WIDTH-1:0] fifo_out_data_r; always @(posedge clk) fifo_out_data_r <= #TCQ fifo_out_data_ns; // When ECC is ON, most of the FIFO output is delayed // by one state. if (ECC == "OFF") begin reg periodic_rd; always @(/*AS*/phy_rddata_valid or fifo_out_data_r) begin {rd_data_end, periodic_rd, rd_data_addr, rd_data_offset} = fifo_out_data_r[FIFO_WIDTH-1:0]; ecc_err_addr = {MC_ERR_ADDR_WIDTH{1'b0}}; rd_data_en = phy_rddata_valid && ~periodic_rd; ecc_status_valid = 1'b0; wr_ecc_buf = 1'b0; end assign rd_rmw = 1'b0; end else begin wire rd_data_end_ns; wire periodic_rd; wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr_ns; wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset_ns; wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr_ns; assign {rd_data_end_ns, periodic_rd, rd_data_addr_ns, rd_data_offset_ns, rd_rmw, ecc_err_addr_ns[DATA_BUF_OFFSET_WIDTH+:MC_ERR_LINE_WIDTH]} = {fifo_out_data_r[FIFO_WIDTH-1:0]}; assign ecc_err_addr_ns[0+:DATA_BUF_OFFSET_WIDTH] = rd_data_offset_ns; always @(posedge clk) rd_data_end <= #TCQ rd_data_end_ns; always @(posedge clk) rd_data_addr <= #TCQ rd_data_addr_ns; always @(posedge clk) rd_data_offset <= #TCQ rd_data_offset_ns; always @(posedge clk) ecc_err_addr <= #TCQ ecc_err_addr_ns; wire rd_data_en_ns = phy_rddata_valid && ~(periodic_rd || rd_rmw); always @(posedge clk) rd_data_en <= rd_data_en_ns; wire ecc_status_valid_ns = phy_rddata_valid && ~periodic_rd; always @(posedge clk) ecc_status_valid <= #TCQ ecc_status_valid_ns; wire wr_ecc_buf_ns = phy_rddata_valid && ~periodic_rd && rd_rmw; always @(posedge clk) wr_ecc_buf <= #TCQ wr_ecc_buf_ns; end end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : col_mach.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // The column machine manages the dq bus. Since there is a single DQ // bus, and the column part of the DRAM is tightly coupled to this DQ // bus, conceptually, the DQ bus and all of the column hardware in // a multi rank DRAM array are managed as a single unit. // // // The column machine does not "enforce" the column timing directly. // It generates information and sends it to the bank machines. If the // bank machines incorrectly make a request, the column machine will // simply overwrite the existing request with the new request even // if this would result in a timing or protocol violation. // // The column machine // hosts the block that controls read and write data transfer // to and from the dq bus. // // And if configured, there is provision for tracking the address // of a command as it moves through the column pipeline. This // address will be logged for detected ECC errors. `timescale 1 ps / 1 ps module mig_7series_v2_3_col_mach # ( parameter TCQ = 100, parameter BANK_WIDTH = 3, parameter BURST_MODE = "8", parameter COL_WIDTH = 12, parameter CS_WIDTH = 4, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DATA_BUF_OFFSET_WIDTH = 1, parameter DELAY_WR_DATA_CNTRL = 0, parameter DQS_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter EARLY_WR_DATA_ADDR = "OFF", parameter ECC = "OFF", parameter MC_ERR_ADDR_WIDTH = 31, parameter nCK_PER_CLK = 2, parameter nPHY_WRLAT = 0, parameter RANK_WIDTH = 2, parameter ROW_WIDTH = 16 ) (/*AUTOARG*/ // Outputs dq_busy_data, wr_data_offset, mc_wrdata_en, wr_data_en, wr_data_addr, rd_rmw, ecc_err_addr, ecc_status_valid, wr_ecc_buf, rd_data_end, rd_data_addr, rd_data_offset, rd_data_en, col_read_fifo_empty, // Inputs clk, rst, sent_col, col_size, col_wr_data_buf_addr, phy_rddata_valid, col_periodic_rd, col_data_buf_addr, col_rmw, col_rd_wr, col_ra, col_ba, col_row, col_a ); input clk; input rst; input sent_col; input col_rd_wr; output reg dq_busy_data = 1'b0; // The following generates a column command disable based mostly on the type // of DRAM and the fabric to DRAM CK ratio. generate if ((nCK_PER_CLK == 1) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3"))) begin : three_bumps reg [1:0] granted_col_d_r; wire [1:0] granted_col_d_ns = {sent_col, granted_col_d_r[1]}; always @(posedge clk) granted_col_d_r <= #TCQ granted_col_d_ns; always @(/*AS*/granted_col_d_r or sent_col) dq_busy_data = sent_col || |granted_col_d_r; end if (((nCK_PER_CLK == 2) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3"))) || ((nCK_PER_CLK == 1) && ((BURST_MODE == "4") || (DRAM_TYPE == "DDR2")))) begin : one_bump always @(/*AS*/sent_col) dq_busy_data = sent_col; end endgenerate // This generates a data offset based on fabric clock to DRAM CK ratio and // the size bit. Note that this is different that the dq_busy_data signal // generated above. reg [1:0] offset_r = 2'b0; reg [1:0] offset_ns = 2'b0; input col_size; wire data_end; generate if(nCK_PER_CLK == 4) begin : data_valid_4_1 // For 4:1 mode all data is transfered in a single beat so the default // values of 0 for offset_r/offset_ns suffice - just tie off data_end assign data_end = 1'b1; end else begin if(DATA_BUF_OFFSET_WIDTH == 2) begin : data_valid_1_1 always @(col_size or offset_r or rst or sent_col) begin if (rst) offset_ns = 2'b0; else begin offset_ns = offset_r; if (sent_col) offset_ns = 2'b1; else if (|offset_r && (offset_r != {col_size, 1'b1})) offset_ns = offset_r + 2'b1; else offset_ns = 2'b0; end end always @(posedge clk) offset_r <= #TCQ offset_ns; assign data_end = col_size ? (offset_r == 2'b11) : offset_r[0]; end else begin : data_valid_2_1 always @(col_size or rst or sent_col) offset_ns[0] = rst ? 1'b0 : sent_col && col_size; always @(posedge clk) offset_r[0] <= #TCQ offset_ns[0]; assign data_end = col_size ? offset_r[0] : 1'b1; end end endgenerate reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r1 = {DATA_BUF_OFFSET_WIDTH{1'b0}}; reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r2 = {DATA_BUF_OFFSET_WIDTH{1'b0}}; reg col_rd_wr_r1; reg col_rd_wr_r2; generate if ((nPHY_WRLAT >= 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0 always @(posedge clk) offset_r1 <= #TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0]; always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr; end if(nPHY_WRLAT == 2) begin : offset_pipe_1 always @(posedge clk) offset_r2 <= #TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]; always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1; end endgenerate output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset; assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1) ? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0] : (EARLY_WR_DATA_ADDR == "OFF") ? offset_r[DATA_BUF_OFFSET_WIDTH-1:0] : offset_ns[DATA_BUF_OFFSET_WIDTH-1:0]; reg sent_col_r1; reg sent_col_r2; always @(posedge clk) sent_col_r1 <= #TCQ sent_col; always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1; wire wrdata_en = (nPHY_WRLAT == 0) ? (sent_col || |offset_r) & ~col_rd_wr : (nPHY_WRLAT == 1) ? (sent_col_r1 || |offset_r1) & ~col_rd_wr_r1 : //(nPHY_WRLAT >= 2) ? (sent_col_r2 || |offset_r2) & ~col_rd_wr_r2; output wire mc_wrdata_en; assign mc_wrdata_en = wrdata_en; output wire wr_data_en; assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1) ? ((sent_col_r1 || |offset_r1) && ~col_rd_wr_r1) : ((sent_col || |offset_r) && ~col_rd_wr); input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr; output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; generate if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1 reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r; always @(posedge clk) col_wr_data_buf_addr_r <= #TCQ col_wr_data_buf_addr; assign wr_data_addr = col_wr_data_buf_addr_r; end else begin : delay_wr_data_cntrl_ne_1 assign wr_data_addr = col_wr_data_buf_addr; end endgenerate // CAS-RD to mc_rddata_en wire read_data_valid = (sent_col || |offset_r) && col_rd_wr; function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 // Implement FIFO that records reads as they are sent to the DRAM. // When phy_rddata_valid is returned some unknown time later, the // FIFO output is used to control how the data is interpreted. input phy_rddata_valid; output wire rd_rmw; output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr; output reg ecc_status_valid; output reg wr_ecc_buf; output reg rd_data_end; output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset; output reg rd_data_en /* synthesis syn_maxfan = 10 */; output col_read_fifo_empty; input col_periodic_rd; input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr; input col_rmw; input [RANK_WIDTH-1:0] col_ra; input [BANK_WIDTH-1:0] col_ba; input [ROW_WIDTH-1:0] col_row; input [ROW_WIDTH-1:0] col_a; // Real column address (skip A10/AP and A12/BC#). The maximum width is 12; // the width will be tailored for the target DRAM downstream. wire [11:0] col_a_full; // Minimum row width is 12; take remaining 11 bits after omitting A10/AP assign col_a_full[10:0] = {col_a[11], col_a[9:0]}; // Get the 12th bit when row address width accommodates it; omit A12/BC# generate if (ROW_WIDTH >= 14) begin : COL_A_FULL_11_1 assign col_a_full[11] = col_a[13]; end else begin : COL_A_FULL_11_0 assign col_a_full[11] = 0; end endgenerate // Extract only the width of the target DRAM wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0]; localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH; localparam FIFO_WIDTH = 1 /*data_end*/ + 1 /*periodic_rd*/ + DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH + ((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH); localparam FULL_RAM_CNT = (FIFO_WIDTH/6); localparam REMAINDER = FIFO_WIDTH % 6; localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); localparam RAM_WIDTH = (RAM_CNT*6); generate begin : read_fifo wire [MC_ERR_LINE_WIDTH:0] ecc_line; if (CS_WIDTH == 1) assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted}; else assign ecc_line = {col_rmw, col_ra, col_ba, col_row, col_a_extracted}; wire [FIFO_WIDTH-1:0] real_fifo_data; if (ECC == "OFF") assign real_fifo_data = {data_end, col_periodic_rd, col_data_buf_addr, offset_r[DATA_BUF_OFFSET_WIDTH-1:0]}; else assign real_fifo_data = {data_end, col_periodic_rd, col_data_buf_addr, offset_r[DATA_BUF_OFFSET_WIDTH-1:0], ecc_line}; wire [RAM_WIDTH-1:0] fifo_in_data; if (REMAINDER == 0) assign fifo_in_data = real_fifo_data; else assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data}; wire [RAM_WIDTH-1:0] fifo_out_data_ns; reg [4:0] head_r; wire [4:0] head_ns = rst ? 5'b0 : read_data_valid ? (head_r + 5'b1) : head_r; always @(posedge clk) head_r <= #TCQ head_ns; reg [4:0] tail_r; wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid ? (tail_r + 5'b1) : tail_r; always @(posedge clk) tail_r <= #TCQ tail_ns; assign col_read_fifo_empty = head_r == tail_r ? 1'b1 : 1'b0; genvar i; for (i=0; i<RAM_CNT; i=i+1) begin : fifo_ram RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(fifo_out_data_ns[((i*6)+4)+:2]), .DOB(fifo_out_data_ns[((i*6)+2)+:2]), .DOC(fifo_out_data_ns[((i*6)+0)+:2]), .DOD(), .DIA(fifo_in_data[((i*6)+4)+:2]), .DIB(fifo_in_data[((i*6)+2)+:2]), .DIC(fifo_in_data[((i*6)+0)+:2]), .DID(2'b0), .ADDRA(tail_ns), .ADDRB(tail_ns), .ADDRC(tail_ns), .ADDRD(head_r), .WE(1'b1), .WCLK(clk) ); end // block: fifo_ram reg [RAM_WIDTH-1:0] fifo_out_data_r; always @(posedge clk) fifo_out_data_r <= #TCQ fifo_out_data_ns; // When ECC is ON, most of the FIFO output is delayed // by one state. if (ECC == "OFF") begin reg periodic_rd; always @(/*AS*/phy_rddata_valid or fifo_out_data_r) begin {rd_data_end, periodic_rd, rd_data_addr, rd_data_offset} = fifo_out_data_r[FIFO_WIDTH-1:0]; ecc_err_addr = {MC_ERR_ADDR_WIDTH{1'b0}}; rd_data_en = phy_rddata_valid && ~periodic_rd; ecc_status_valid = 1'b0; wr_ecc_buf = 1'b0; end assign rd_rmw = 1'b0; end else begin wire rd_data_end_ns; wire periodic_rd; wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr_ns; wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset_ns; wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr_ns; assign {rd_data_end_ns, periodic_rd, rd_data_addr_ns, rd_data_offset_ns, rd_rmw, ecc_err_addr_ns[DATA_BUF_OFFSET_WIDTH+:MC_ERR_LINE_WIDTH]} = {fifo_out_data_r[FIFO_WIDTH-1:0]}; assign ecc_err_addr_ns[0+:DATA_BUF_OFFSET_WIDTH] = rd_data_offset_ns; always @(posedge clk) rd_data_end <= #TCQ rd_data_end_ns; always @(posedge clk) rd_data_addr <= #TCQ rd_data_addr_ns; always @(posedge clk) rd_data_offset <= #TCQ rd_data_offset_ns; always @(posedge clk) ecc_err_addr <= #TCQ ecc_err_addr_ns; wire rd_data_en_ns = phy_rddata_valid && ~(periodic_rd || rd_rmw); always @(posedge clk) rd_data_en <= rd_data_en_ns; wire ecc_status_valid_ns = phy_rddata_valid && ~periodic_rd; always @(posedge clk) ecc_status_valid <= #TCQ ecc_status_valid_ns; wire wr_ecc_buf_ns = phy_rddata_valid && ~periodic_rd && rd_rmw; always @(posedge clk) wr_ecc_buf <= #TCQ wr_ecc_buf_ns; end end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : col_mach.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // The column machine manages the dq bus. Since there is a single DQ // bus, and the column part of the DRAM is tightly coupled to this DQ // bus, conceptually, the DQ bus and all of the column hardware in // a multi rank DRAM array are managed as a single unit. // // // The column machine does not "enforce" the column timing directly. // It generates information and sends it to the bank machines. If the // bank machines incorrectly make a request, the column machine will // simply overwrite the existing request with the new request even // if this would result in a timing or protocol violation. // // The column machine // hosts the block that controls read and write data transfer // to and from the dq bus. // // And if configured, there is provision for tracking the address // of a command as it moves through the column pipeline. This // address will be logged for detected ECC errors. `timescale 1 ps / 1 ps module mig_7series_v2_3_col_mach # ( parameter TCQ = 100, parameter BANK_WIDTH = 3, parameter BURST_MODE = "8", parameter COL_WIDTH = 12, parameter CS_WIDTH = 4, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DATA_BUF_OFFSET_WIDTH = 1, parameter DELAY_WR_DATA_CNTRL = 0, parameter DQS_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter EARLY_WR_DATA_ADDR = "OFF", parameter ECC = "OFF", parameter MC_ERR_ADDR_WIDTH = 31, parameter nCK_PER_CLK = 2, parameter nPHY_WRLAT = 0, parameter RANK_WIDTH = 2, parameter ROW_WIDTH = 16 ) (/*AUTOARG*/ // Outputs dq_busy_data, wr_data_offset, mc_wrdata_en, wr_data_en, wr_data_addr, rd_rmw, ecc_err_addr, ecc_status_valid, wr_ecc_buf, rd_data_end, rd_data_addr, rd_data_offset, rd_data_en, col_read_fifo_empty, // Inputs clk, rst, sent_col, col_size, col_wr_data_buf_addr, phy_rddata_valid, col_periodic_rd, col_data_buf_addr, col_rmw, col_rd_wr, col_ra, col_ba, col_row, col_a ); input clk; input rst; input sent_col; input col_rd_wr; output reg dq_busy_data = 1'b0; // The following generates a column command disable based mostly on the type // of DRAM and the fabric to DRAM CK ratio. generate if ((nCK_PER_CLK == 1) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3"))) begin : three_bumps reg [1:0] granted_col_d_r; wire [1:0] granted_col_d_ns = {sent_col, granted_col_d_r[1]}; always @(posedge clk) granted_col_d_r <= #TCQ granted_col_d_ns; always @(/*AS*/granted_col_d_r or sent_col) dq_busy_data = sent_col || |granted_col_d_r; end if (((nCK_PER_CLK == 2) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3"))) || ((nCK_PER_CLK == 1) && ((BURST_MODE == "4") || (DRAM_TYPE == "DDR2")))) begin : one_bump always @(/*AS*/sent_col) dq_busy_data = sent_col; end endgenerate // This generates a data offset based on fabric clock to DRAM CK ratio and // the size bit. Note that this is different that the dq_busy_data signal // generated above. reg [1:0] offset_r = 2'b0; reg [1:0] offset_ns = 2'b0; input col_size; wire data_end; generate if(nCK_PER_CLK == 4) begin : data_valid_4_1 // For 4:1 mode all data is transfered in a single beat so the default // values of 0 for offset_r/offset_ns suffice - just tie off data_end assign data_end = 1'b1; end else begin if(DATA_BUF_OFFSET_WIDTH == 2) begin : data_valid_1_1 always @(col_size or offset_r or rst or sent_col) begin if (rst) offset_ns = 2'b0; else begin offset_ns = offset_r; if (sent_col) offset_ns = 2'b1; else if (|offset_r && (offset_r != {col_size, 1'b1})) offset_ns = offset_r + 2'b1; else offset_ns = 2'b0; end end always @(posedge clk) offset_r <= #TCQ offset_ns; assign data_end = col_size ? (offset_r == 2'b11) : offset_r[0]; end else begin : data_valid_2_1 always @(col_size or rst or sent_col) offset_ns[0] = rst ? 1'b0 : sent_col && col_size; always @(posedge clk) offset_r[0] <= #TCQ offset_ns[0]; assign data_end = col_size ? offset_r[0] : 1'b1; end end endgenerate reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r1 = {DATA_BUF_OFFSET_WIDTH{1'b0}}; reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r2 = {DATA_BUF_OFFSET_WIDTH{1'b0}}; reg col_rd_wr_r1; reg col_rd_wr_r2; generate if ((nPHY_WRLAT >= 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0 always @(posedge clk) offset_r1 <= #TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0]; always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr; end if(nPHY_WRLAT == 2) begin : offset_pipe_1 always @(posedge clk) offset_r2 <= #TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]; always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1; end endgenerate output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset; assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1) ? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0] : (EARLY_WR_DATA_ADDR == "OFF") ? offset_r[DATA_BUF_OFFSET_WIDTH-1:0] : offset_ns[DATA_BUF_OFFSET_WIDTH-1:0]; reg sent_col_r1; reg sent_col_r2; always @(posedge clk) sent_col_r1 <= #TCQ sent_col; always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1; wire wrdata_en = (nPHY_WRLAT == 0) ? (sent_col || |offset_r) & ~col_rd_wr : (nPHY_WRLAT == 1) ? (sent_col_r1 || |offset_r1) & ~col_rd_wr_r1 : //(nPHY_WRLAT >= 2) ? (sent_col_r2 || |offset_r2) & ~col_rd_wr_r2; output wire mc_wrdata_en; assign mc_wrdata_en = wrdata_en; output wire wr_data_en; assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1) ? ((sent_col_r1 || |offset_r1) && ~col_rd_wr_r1) : ((sent_col || |offset_r) && ~col_rd_wr); input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr; output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; generate if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1 reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r; always @(posedge clk) col_wr_data_buf_addr_r <= #TCQ col_wr_data_buf_addr; assign wr_data_addr = col_wr_data_buf_addr_r; end else begin : delay_wr_data_cntrl_ne_1 assign wr_data_addr = col_wr_data_buf_addr; end endgenerate // CAS-RD to mc_rddata_en wire read_data_valid = (sent_col || |offset_r) && col_rd_wr; function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 // Implement FIFO that records reads as they are sent to the DRAM. // When phy_rddata_valid is returned some unknown time later, the // FIFO output is used to control how the data is interpreted. input phy_rddata_valid; output wire rd_rmw; output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr; output reg ecc_status_valid; output reg wr_ecc_buf; output reg rd_data_end; output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset; output reg rd_data_en /* synthesis syn_maxfan = 10 */; output col_read_fifo_empty; input col_periodic_rd; input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr; input col_rmw; input [RANK_WIDTH-1:0] col_ra; input [BANK_WIDTH-1:0] col_ba; input [ROW_WIDTH-1:0] col_row; input [ROW_WIDTH-1:0] col_a; // Real column address (skip A10/AP and A12/BC#). The maximum width is 12; // the width will be tailored for the target DRAM downstream. wire [11:0] col_a_full; // Minimum row width is 12; take remaining 11 bits after omitting A10/AP assign col_a_full[10:0] = {col_a[11], col_a[9:0]}; // Get the 12th bit when row address width accommodates it; omit A12/BC# generate if (ROW_WIDTH >= 14) begin : COL_A_FULL_11_1 assign col_a_full[11] = col_a[13]; end else begin : COL_A_FULL_11_0 assign col_a_full[11] = 0; end endgenerate // Extract only the width of the target DRAM wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0]; localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH; localparam FIFO_WIDTH = 1 /*data_end*/ + 1 /*periodic_rd*/ + DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH + ((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH); localparam FULL_RAM_CNT = (FIFO_WIDTH/6); localparam REMAINDER = FIFO_WIDTH % 6; localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); localparam RAM_WIDTH = (RAM_CNT*6); generate begin : read_fifo wire [MC_ERR_LINE_WIDTH:0] ecc_line; if (CS_WIDTH == 1) assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted}; else assign ecc_line = {col_rmw, col_ra, col_ba, col_row, col_a_extracted}; wire [FIFO_WIDTH-1:0] real_fifo_data; if (ECC == "OFF") assign real_fifo_data = {data_end, col_periodic_rd, col_data_buf_addr, offset_r[DATA_BUF_OFFSET_WIDTH-1:0]}; else assign real_fifo_data = {data_end, col_periodic_rd, col_data_buf_addr, offset_r[DATA_BUF_OFFSET_WIDTH-1:0], ecc_line}; wire [RAM_WIDTH-1:0] fifo_in_data; if (REMAINDER == 0) assign fifo_in_data = real_fifo_data; else assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data}; wire [RAM_WIDTH-1:0] fifo_out_data_ns; reg [4:0] head_r; wire [4:0] head_ns = rst ? 5'b0 : read_data_valid ? (head_r + 5'b1) : head_r; always @(posedge clk) head_r <= #TCQ head_ns; reg [4:0] tail_r; wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid ? (tail_r + 5'b1) : tail_r; always @(posedge clk) tail_r <= #TCQ tail_ns; assign col_read_fifo_empty = head_r == tail_r ? 1'b1 : 1'b0; genvar i; for (i=0; i<RAM_CNT; i=i+1) begin : fifo_ram RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(fifo_out_data_ns[((i*6)+4)+:2]), .DOB(fifo_out_data_ns[((i*6)+2)+:2]), .DOC(fifo_out_data_ns[((i*6)+0)+:2]), .DOD(), .DIA(fifo_in_data[((i*6)+4)+:2]), .DIB(fifo_in_data[((i*6)+2)+:2]), .DIC(fifo_in_data[((i*6)+0)+:2]), .DID(2'b0), .ADDRA(tail_ns), .ADDRB(tail_ns), .ADDRC(tail_ns), .ADDRD(head_r), .WE(1'b1), .WCLK(clk) ); end // block: fifo_ram reg [RAM_WIDTH-1:0] fifo_out_data_r; always @(posedge clk) fifo_out_data_r <= #TCQ fifo_out_data_ns; // When ECC is ON, most of the FIFO output is delayed // by one state. if (ECC == "OFF") begin reg periodic_rd; always @(/*AS*/phy_rddata_valid or fifo_out_data_r) begin {rd_data_end, periodic_rd, rd_data_addr, rd_data_offset} = fifo_out_data_r[FIFO_WIDTH-1:0]; ecc_err_addr = {MC_ERR_ADDR_WIDTH{1'b0}}; rd_data_en = phy_rddata_valid && ~periodic_rd; ecc_status_valid = 1'b0; wr_ecc_buf = 1'b0; end assign rd_rmw = 1'b0; end else begin wire rd_data_end_ns; wire periodic_rd; wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr_ns; wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset_ns; wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr_ns; assign {rd_data_end_ns, periodic_rd, rd_data_addr_ns, rd_data_offset_ns, rd_rmw, ecc_err_addr_ns[DATA_BUF_OFFSET_WIDTH+:MC_ERR_LINE_WIDTH]} = {fifo_out_data_r[FIFO_WIDTH-1:0]}; assign ecc_err_addr_ns[0+:DATA_BUF_OFFSET_WIDTH] = rd_data_offset_ns; always @(posedge clk) rd_data_end <= #TCQ rd_data_end_ns; always @(posedge clk) rd_data_addr <= #TCQ rd_data_addr_ns; always @(posedge clk) rd_data_offset <= #TCQ rd_data_offset_ns; always @(posedge clk) ecc_err_addr <= #TCQ ecc_err_addr_ns; wire rd_data_en_ns = phy_rddata_valid && ~(periodic_rd || rd_rmw); always @(posedge clk) rd_data_en <= rd_data_en_ns; wire ecc_status_valid_ns = phy_rddata_valid && ~periodic_rd; always @(posedge clk) ecc_status_valid <= #TCQ ecc_status_valid_ns; wire wr_ecc_buf_ns = phy_rddata_valid && ~periodic_rd && rd_rmw; always @(posedge clk) wr_ecc_buf <= #TCQ wr_ecc_buf_ns; end end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : col_mach.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // The column machine manages the dq bus. Since there is a single DQ // bus, and the column part of the DRAM is tightly coupled to this DQ // bus, conceptually, the DQ bus and all of the column hardware in // a multi rank DRAM array are managed as a single unit. // // // The column machine does not "enforce" the column timing directly. // It generates information and sends it to the bank machines. If the // bank machines incorrectly make a request, the column machine will // simply overwrite the existing request with the new request even // if this would result in a timing or protocol violation. // // The column machine // hosts the block that controls read and write data transfer // to and from the dq bus. // // And if configured, there is provision for tracking the address // of a command as it moves through the column pipeline. This // address will be logged for detected ECC errors. `timescale 1 ps / 1 ps module mig_7series_v2_3_col_mach # ( parameter TCQ = 100, parameter BANK_WIDTH = 3, parameter BURST_MODE = "8", parameter COL_WIDTH = 12, parameter CS_WIDTH = 4, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DATA_BUF_OFFSET_WIDTH = 1, parameter DELAY_WR_DATA_CNTRL = 0, parameter DQS_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter EARLY_WR_DATA_ADDR = "OFF", parameter ECC = "OFF", parameter MC_ERR_ADDR_WIDTH = 31, parameter nCK_PER_CLK = 2, parameter nPHY_WRLAT = 0, parameter RANK_WIDTH = 2, parameter ROW_WIDTH = 16 ) (/*AUTOARG*/ // Outputs dq_busy_data, wr_data_offset, mc_wrdata_en, wr_data_en, wr_data_addr, rd_rmw, ecc_err_addr, ecc_status_valid, wr_ecc_buf, rd_data_end, rd_data_addr, rd_data_offset, rd_data_en, col_read_fifo_empty, // Inputs clk, rst, sent_col, col_size, col_wr_data_buf_addr, phy_rddata_valid, col_periodic_rd, col_data_buf_addr, col_rmw, col_rd_wr, col_ra, col_ba, col_row, col_a ); input clk; input rst; input sent_col; input col_rd_wr; output reg dq_busy_data = 1'b0; // The following generates a column command disable based mostly on the type // of DRAM and the fabric to DRAM CK ratio. generate if ((nCK_PER_CLK == 1) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3"))) begin : three_bumps reg [1:0] granted_col_d_r; wire [1:0] granted_col_d_ns = {sent_col, granted_col_d_r[1]}; always @(posedge clk) granted_col_d_r <= #TCQ granted_col_d_ns; always @(/*AS*/granted_col_d_r or sent_col) dq_busy_data = sent_col || |granted_col_d_r; end if (((nCK_PER_CLK == 2) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3"))) || ((nCK_PER_CLK == 1) && ((BURST_MODE == "4") || (DRAM_TYPE == "DDR2")))) begin : one_bump always @(/*AS*/sent_col) dq_busy_data = sent_col; end endgenerate // This generates a data offset based on fabric clock to DRAM CK ratio and // the size bit. Note that this is different that the dq_busy_data signal // generated above. reg [1:0] offset_r = 2'b0; reg [1:0] offset_ns = 2'b0; input col_size; wire data_end; generate if(nCK_PER_CLK == 4) begin : data_valid_4_1 // For 4:1 mode all data is transfered in a single beat so the default // values of 0 for offset_r/offset_ns suffice - just tie off data_end assign data_end = 1'b1; end else begin if(DATA_BUF_OFFSET_WIDTH == 2) begin : data_valid_1_1 always @(col_size or offset_r or rst or sent_col) begin if (rst) offset_ns = 2'b0; else begin offset_ns = offset_r; if (sent_col) offset_ns = 2'b1; else if (|offset_r && (offset_r != {col_size, 1'b1})) offset_ns = offset_r + 2'b1; else offset_ns = 2'b0; end end always @(posedge clk) offset_r <= #TCQ offset_ns; assign data_end = col_size ? (offset_r == 2'b11) : offset_r[0]; end else begin : data_valid_2_1 always @(col_size or rst or sent_col) offset_ns[0] = rst ? 1'b0 : sent_col && col_size; always @(posedge clk) offset_r[0] <= #TCQ offset_ns[0]; assign data_end = col_size ? offset_r[0] : 1'b1; end end endgenerate reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r1 = {DATA_BUF_OFFSET_WIDTH{1'b0}}; reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r2 = {DATA_BUF_OFFSET_WIDTH{1'b0}}; reg col_rd_wr_r1; reg col_rd_wr_r2; generate if ((nPHY_WRLAT >= 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0 always @(posedge clk) offset_r1 <= #TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0]; always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr; end if(nPHY_WRLAT == 2) begin : offset_pipe_1 always @(posedge clk) offset_r2 <= #TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]; always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1; end endgenerate output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset; assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1) ? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0] : (EARLY_WR_DATA_ADDR == "OFF") ? offset_r[DATA_BUF_OFFSET_WIDTH-1:0] : offset_ns[DATA_BUF_OFFSET_WIDTH-1:0]; reg sent_col_r1; reg sent_col_r2; always @(posedge clk) sent_col_r1 <= #TCQ sent_col; always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1; wire wrdata_en = (nPHY_WRLAT == 0) ? (sent_col || |offset_r) & ~col_rd_wr : (nPHY_WRLAT == 1) ? (sent_col_r1 || |offset_r1) & ~col_rd_wr_r1 : //(nPHY_WRLAT >= 2) ? (sent_col_r2 || |offset_r2) & ~col_rd_wr_r2; output wire mc_wrdata_en; assign mc_wrdata_en = wrdata_en; output wire wr_data_en; assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1) ? ((sent_col_r1 || |offset_r1) && ~col_rd_wr_r1) : ((sent_col || |offset_r) && ~col_rd_wr); input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr; output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; generate if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1 reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r; always @(posedge clk) col_wr_data_buf_addr_r <= #TCQ col_wr_data_buf_addr; assign wr_data_addr = col_wr_data_buf_addr_r; end else begin : delay_wr_data_cntrl_ne_1 assign wr_data_addr = col_wr_data_buf_addr; end endgenerate // CAS-RD to mc_rddata_en wire read_data_valid = (sent_col || |offset_r) && col_rd_wr; function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 // Implement FIFO that records reads as they are sent to the DRAM. // When phy_rddata_valid is returned some unknown time later, the // FIFO output is used to control how the data is interpreted. input phy_rddata_valid; output wire rd_rmw; output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr; output reg ecc_status_valid; output reg wr_ecc_buf; output reg rd_data_end; output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset; output reg rd_data_en /* synthesis syn_maxfan = 10 */; output col_read_fifo_empty; input col_periodic_rd; input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr; input col_rmw; input [RANK_WIDTH-1:0] col_ra; input [BANK_WIDTH-1:0] col_ba; input [ROW_WIDTH-1:0] col_row; input [ROW_WIDTH-1:0] col_a; // Real column address (skip A10/AP and A12/BC#). The maximum width is 12; // the width will be tailored for the target DRAM downstream. wire [11:0] col_a_full; // Minimum row width is 12; take remaining 11 bits after omitting A10/AP assign col_a_full[10:0] = {col_a[11], col_a[9:0]}; // Get the 12th bit when row address width accommodates it; omit A12/BC# generate if (ROW_WIDTH >= 14) begin : COL_A_FULL_11_1 assign col_a_full[11] = col_a[13]; end else begin : COL_A_FULL_11_0 assign col_a_full[11] = 0; end endgenerate // Extract only the width of the target DRAM wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0]; localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH; localparam FIFO_WIDTH = 1 /*data_end*/ + 1 /*periodic_rd*/ + DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH + ((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH); localparam FULL_RAM_CNT = (FIFO_WIDTH/6); localparam REMAINDER = FIFO_WIDTH % 6; localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); localparam RAM_WIDTH = (RAM_CNT*6); generate begin : read_fifo wire [MC_ERR_LINE_WIDTH:0] ecc_line; if (CS_WIDTH == 1) assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted}; else assign ecc_line = {col_rmw, col_ra, col_ba, col_row, col_a_extracted}; wire [FIFO_WIDTH-1:0] real_fifo_data; if (ECC == "OFF") assign real_fifo_data = {data_end, col_periodic_rd, col_data_buf_addr, offset_r[DATA_BUF_OFFSET_WIDTH-1:0]}; else assign real_fifo_data = {data_end, col_periodic_rd, col_data_buf_addr, offset_r[DATA_BUF_OFFSET_WIDTH-1:0], ecc_line}; wire [RAM_WIDTH-1:0] fifo_in_data; if (REMAINDER == 0) assign fifo_in_data = real_fifo_data; else assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data}; wire [RAM_WIDTH-1:0] fifo_out_data_ns; reg [4:0] head_r; wire [4:0] head_ns = rst ? 5'b0 : read_data_valid ? (head_r + 5'b1) : head_r; always @(posedge clk) head_r <= #TCQ head_ns; reg [4:0] tail_r; wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid ? (tail_r + 5'b1) : tail_r; always @(posedge clk) tail_r <= #TCQ tail_ns; assign col_read_fifo_empty = head_r == tail_r ? 1'b1 : 1'b0; genvar i; for (i=0; i<RAM_CNT; i=i+1) begin : fifo_ram RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(fifo_out_data_ns[((i*6)+4)+:2]), .DOB(fifo_out_data_ns[((i*6)+2)+:2]), .DOC(fifo_out_data_ns[((i*6)+0)+:2]), .DOD(), .DIA(fifo_in_data[((i*6)+4)+:2]), .DIB(fifo_in_data[((i*6)+2)+:2]), .DIC(fifo_in_data[((i*6)+0)+:2]), .DID(2'b0), .ADDRA(tail_ns), .ADDRB(tail_ns), .ADDRC(tail_ns), .ADDRD(head_r), .WE(1'b1), .WCLK(clk) ); end // block: fifo_ram reg [RAM_WIDTH-1:0] fifo_out_data_r; always @(posedge clk) fifo_out_data_r <= #TCQ fifo_out_data_ns; // When ECC is ON, most of the FIFO output is delayed // by one state. if (ECC == "OFF") begin reg periodic_rd; always @(/*AS*/phy_rddata_valid or fifo_out_data_r) begin {rd_data_end, periodic_rd, rd_data_addr, rd_data_offset} = fifo_out_data_r[FIFO_WIDTH-1:0]; ecc_err_addr = {MC_ERR_ADDR_WIDTH{1'b0}}; rd_data_en = phy_rddata_valid && ~periodic_rd; ecc_status_valid = 1'b0; wr_ecc_buf = 1'b0; end assign rd_rmw = 1'b0; end else begin wire rd_data_end_ns; wire periodic_rd; wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr_ns; wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset_ns; wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr_ns; assign {rd_data_end_ns, periodic_rd, rd_data_addr_ns, rd_data_offset_ns, rd_rmw, ecc_err_addr_ns[DATA_BUF_OFFSET_WIDTH+:MC_ERR_LINE_WIDTH]} = {fifo_out_data_r[FIFO_WIDTH-1:0]}; assign ecc_err_addr_ns[0+:DATA_BUF_OFFSET_WIDTH] = rd_data_offset_ns; always @(posedge clk) rd_data_end <= #TCQ rd_data_end_ns; always @(posedge clk) rd_data_addr <= #TCQ rd_data_addr_ns; always @(posedge clk) rd_data_offset <= #TCQ rd_data_offset_ns; always @(posedge clk) ecc_err_addr <= #TCQ ecc_err_addr_ns; wire rd_data_en_ns = phy_rddata_valid && ~(periodic_rd || rd_rmw); always @(posedge clk) rd_data_en <= rd_data_en_ns; wire ecc_status_valid_ns = phy_rddata_valid && ~periodic_rd; always @(posedge clk) ecc_status_valid <= #TCQ ecc_status_valid_ns; wire wr_ecc_buf_ns = phy_rddata_valid && ~periodic_rd && rd_rmw; always @(posedge clk) wr_ecc_buf <= #TCQ wr_ecc_buf_ns; end end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v2_3_poc_pd.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 15 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff // prevents any noise that could happen when the phase shift clock is very // nearly aligned to the fabric clock. //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_poc_pd # (parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter SIM_CAL_OPTION = "NONE", parameter TCQ = 100) (/*AUTOARG*/ // Outputs pd_out, // Inputs iddr_rst, clk, kclk, mmcm_ps_clk ); input iddr_rst; input clk; input kclk; input mmcm_ps_clk; wire q1; IDDR # (.DDR_CLK_EDGE ("OPPOSITE_EDGE"), .INIT_Q1 (1'b0), .INIT_Q2 (1'b0), .SRTYPE ("SYNC")) u_phase_detector (.Q1 (q1), .Q2 (), .C (mmcm_ps_clk), .CE (1'b1), .D (kclk), .R (iddr_rst), .S (1'b0)); // Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME reg pos_edge_samp; generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes always @(posedge clk) pos_edge_samp <= #TCQ q1; end else begin : eXes reg q1_delayed; reg rising_clk_seen; always @(posedge mmcm_ps_clk) begin rising_clk_seen <= 1'b0; q1_delayed <= 1'bx; end always @(posedge clk) begin rising_clk_seen = 1'b1; if (rising_clk_seen) q1_delayed <= q1; end always @(posedge clk) begin pos_edge_samp <= q1_delayed; end end endgenerate reg pd_out_r; always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp; output pd_out; assign pd_out = pd_out_r; endmodule // mic_7series_v2_3_poc_pd

//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v2_3_poc_pd.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 15 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff // prevents any noise that could happen when the phase shift clock is very // nearly aligned to the fabric clock. //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_poc_pd # (parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter SIM_CAL_OPTION = "NONE", parameter TCQ = 100) (/*AUTOARG*/ // Outputs pd_out, // Inputs iddr_rst, clk, kclk, mmcm_ps_clk ); input iddr_rst; input clk; input kclk; input mmcm_ps_clk; wire q1; IDDR # (.DDR_CLK_EDGE ("OPPOSITE_EDGE"), .INIT_Q1 (1'b0), .INIT_Q2 (1'b0), .SRTYPE ("SYNC")) u_phase_detector (.Q1 (q1), .Q2 (), .C (mmcm_ps_clk), .CE (1'b1), .D (kclk), .R (iddr_rst), .S (1'b0)); // Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME reg pos_edge_samp; generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes always @(posedge clk) pos_edge_samp <= #TCQ q1; end else begin : eXes reg q1_delayed; reg rising_clk_seen; always @(posedge mmcm_ps_clk) begin rising_clk_seen <= 1'b0; q1_delayed <= 1'bx; end always @(posedge clk) begin rising_clk_seen = 1'b1; if (rising_clk_seen) q1_delayed <= q1; end always @(posedge clk) begin pos_edge_samp <= q1_delayed; end end endgenerate reg pd_out_r; always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp; output pd_out; assign pd_out = pd_out_r; endmodule // mic_7series_v2_3_poc_pd

//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v2_3_poc_pd.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 15 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff // prevents any noise that could happen when the phase shift clock is very // nearly aligned to the fabric clock. //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_poc_pd # (parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter SIM_CAL_OPTION = "NONE", parameter TCQ = 100) (/*AUTOARG*/ // Outputs pd_out, // Inputs iddr_rst, clk, kclk, mmcm_ps_clk ); input iddr_rst; input clk; input kclk; input mmcm_ps_clk; wire q1; IDDR # (.DDR_CLK_EDGE ("OPPOSITE_EDGE"), .INIT_Q1 (1'b0), .INIT_Q2 (1'b0), .SRTYPE ("SYNC")) u_phase_detector (.Q1 (q1), .Q2 (), .C (mmcm_ps_clk), .CE (1'b1), .D (kclk), .R (iddr_rst), .S (1'b0)); // Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME reg pos_edge_samp; generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes always @(posedge clk) pos_edge_samp <= #TCQ q1; end else begin : eXes reg q1_delayed; reg rising_clk_seen; always @(posedge mmcm_ps_clk) begin rising_clk_seen <= 1'b0; q1_delayed <= 1'bx; end always @(posedge clk) begin rising_clk_seen = 1'b1; if (rising_clk_seen) q1_delayed <= q1; end always @(posedge clk) begin pos_edge_samp <= q1_delayed; end end endgenerate reg pd_out_r; always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp; output pd_out; assign pd_out = pd_out_r; endmodule // mic_7series_v2_3_poc_pd

//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v2_3_poc_pd.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 15 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff // prevents any noise that could happen when the phase shift clock is very // nearly aligned to the fabric clock. //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_poc_pd # (parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter SIM_CAL_OPTION = "NONE", parameter TCQ = 100) (/*AUTOARG*/ // Outputs pd_out, // Inputs iddr_rst, clk, kclk, mmcm_ps_clk ); input iddr_rst; input clk; input kclk; input mmcm_ps_clk; wire q1; IDDR # (.DDR_CLK_EDGE ("OPPOSITE_EDGE"), .INIT_Q1 (1'b0), .INIT_Q2 (1'b0), .SRTYPE ("SYNC")) u_phase_detector (.Q1 (q1), .Q2 (), .C (mmcm_ps_clk), .CE (1'b1), .D (kclk), .R (iddr_rst), .S (1'b0)); // Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME reg pos_edge_samp; generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes always @(posedge clk) pos_edge_samp <= #TCQ q1; end else begin : eXes reg q1_delayed; reg rising_clk_seen; always @(posedge mmcm_ps_clk) begin rising_clk_seen <= 1'b0; q1_delayed <= 1'bx; end always @(posedge clk) begin rising_clk_seen = 1'b1; if (rising_clk_seen) q1_delayed <= q1; end always @(posedge clk) begin pos_edge_samp <= q1_delayed; end end endgenerate reg pd_out_r; always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp; output pd_out; assign pd_out = pd_out_r; endmodule // mic_7series_v2_3_poc_pd

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ddr_of_pre_fifo.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Feb 08 2011 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries //Reference : //Revision History : //***************************************************************************** /****************************************************************************** **$Id: ddr_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $ **$Date: 2011/06/02 08:35:07 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_of_pre_fifo.v,v $ ******************************************************************************/ `timescale 1 ps / 1 ps module mig_7series_v2_3_ddr_of_pre_fifo # ( parameter TCQ = 100, // clk->out delay (sim only) parameter DEPTH = 4, // # of entries parameter WIDTH = 32 // data bus width ) ( input clk, // clock input rst, // synchronous reset input full_in, // FULL flag from OUT_FIFO input wr_en_in, // write enable from controller input [WIDTH-1:0] d_in, // write data from controller output wr_en_out, // write enable to OUT_FIFO output [WIDTH-1:0] d_out, // write data to OUT_FIFO output afull // almost full signal to controller ); // # of bits used to represent read/write pointers localparam PTR_BITS = (DEPTH == 2) ? 1 : ((DEPTH == 3) || (DEPTH == 4)) ? 2 : (((DEPTH == 5) || (DEPTH == 6) || (DEPTH == 7) || (DEPTH == 8)) ? 3 : DEPTH == 9 ? 4 : 'bx); // Set watermark. Always give the MC 5 cycles to engage flow control. localparam ALMOST_FULL_VALUE = DEPTH - 5; integer i; reg [WIDTH-1:0] mem[0:DEPTH-1] ; reg [8:0] my_empty /* synthesis syn_maxfan = 3 */; reg [5:0] my_full /* synthesis syn_maxfan = 3 */; reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */; reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */; (* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */; (* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] wr_ptr_timing /* synthesis syn_maxfan = 10 */; reg [PTR_BITS:0] entry_cnt; wire [PTR_BITS-1:0] nxt_rd_ptr; wire [PTR_BITS-1:0] nxt_wr_ptr; wire [WIDTH-1:0] mem_out; (* max_fanout = 50 *) wire wr_en; assign d_out = my_empty[0] ? d_in : mem_out; assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in); assign wr_en = wr_en_in & ((!my_empty[3] & !full_in)|(!my_full[2] & full_in)); always @ (posedge clk) if (wr_en) mem[wr_ptr] <= #TCQ d_in; assign mem_out = mem[rd_ptr]; assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH; always @ (posedge clk) begin if (rst) begin rd_ptr <= 'b0; rd_ptr_timing <= 'b0; end else if ((!my_empty[4]) & (!full_in)) begin rd_ptr <= nxt_rd_ptr; rd_ptr_timing <= nxt_rd_ptr; end end always @ (posedge clk) begin if (rst) my_empty <= 9'h1ff; else begin if (my_empty[2] & !my_full[3] & full_in & wr_en_in) my_empty[3:0] <= 4'b0000; else if (!my_empty[2] & !my_full[3] & !full_in & !wr_en_in) begin my_empty[0] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[1] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[2] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[3] <= (nxt_rd_ptr == wr_ptr_timing); end if (my_empty[8] & !my_full[5] & full_in & wr_en_in) my_empty[8:4] <= 5'b00000; else if (!my_empty[8] & !my_full[5] & !full_in & !wr_en_in) begin my_empty[4] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[5] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[6] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[7] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[8] <= (nxt_rd_ptr == wr_ptr_timing); end end end assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH; always @ (posedge clk) begin if (rst) begin wr_ptr <= 'b0; wr_ptr_timing <= 'b0; end else if ((wr_en_in) & ((!my_empty[5] & !full_in) | (!my_full[1] & full_in))) begin wr_ptr <= nxt_wr_ptr; wr_ptr_timing <= nxt_wr_ptr; end end always @ (posedge clk) begin if (rst) my_full <= 6'b000000; else if (!my_empty[6] & my_full[0] & !full_in & !wr_en_in) my_full <= 6'b000000; else if (!my_empty[6] & !my_full[0] & full_in & wr_en_in) begin my_full[0] <= (nxt_wr_ptr == rd_ptr_timing); my_full[1] <= (nxt_wr_ptr == rd_ptr_timing); my_full[2] <= (nxt_wr_ptr == rd_ptr_timing); my_full[3] <= (nxt_wr_ptr == rd_ptr_timing); my_full[4] <= (nxt_wr_ptr == rd_ptr_timing); my_full[5] <= (nxt_wr_ptr == rd_ptr_timing); end end always @ (posedge clk) begin if (rst) entry_cnt <= 'b0; else if (wr_en_in & full_in & !my_full[4]) entry_cnt <= entry_cnt + 1'b1; else if (!wr_en_in & !full_in & !my_empty[7]) entry_cnt <= entry_cnt - 1'b1; end assign afull = (entry_cnt >= ALMOST_FULL_VALUE); endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ddr_of_pre_fifo.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Feb 08 2011 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries //Reference : //Revision History : //***************************************************************************** /****************************************************************************** **$Id: ddr_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $ **$Date: 2011/06/02 08:35:07 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_of_pre_fifo.v,v $ ******************************************************************************/ `timescale 1 ps / 1 ps module mig_7series_v2_3_ddr_of_pre_fifo # ( parameter TCQ = 100, // clk->out delay (sim only) parameter DEPTH = 4, // # of entries parameter WIDTH = 32 // data bus width ) ( input clk, // clock input rst, // synchronous reset input full_in, // FULL flag from OUT_FIFO input wr_en_in, // write enable from controller input [WIDTH-1:0] d_in, // write data from controller output wr_en_out, // write enable to OUT_FIFO output [WIDTH-1:0] d_out, // write data to OUT_FIFO output afull // almost full signal to controller ); // # of bits used to represent read/write pointers localparam PTR_BITS = (DEPTH == 2) ? 1 : ((DEPTH == 3) || (DEPTH == 4)) ? 2 : (((DEPTH == 5) || (DEPTH == 6) || (DEPTH == 7) || (DEPTH == 8)) ? 3 : DEPTH == 9 ? 4 : 'bx); // Set watermark. Always give the MC 5 cycles to engage flow control. localparam ALMOST_FULL_VALUE = DEPTH - 5; integer i; reg [WIDTH-1:0] mem[0:DEPTH-1] ; reg [8:0] my_empty /* synthesis syn_maxfan = 3 */; reg [5:0] my_full /* synthesis syn_maxfan = 3 */; reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */; reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */; (* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */; (* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] wr_ptr_timing /* synthesis syn_maxfan = 10 */; reg [PTR_BITS:0] entry_cnt; wire [PTR_BITS-1:0] nxt_rd_ptr; wire [PTR_BITS-1:0] nxt_wr_ptr; wire [WIDTH-1:0] mem_out; (* max_fanout = 50 *) wire wr_en; assign d_out = my_empty[0] ? d_in : mem_out; assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in); assign wr_en = wr_en_in & ((!my_empty[3] & !full_in)|(!my_full[2] & full_in)); always @ (posedge clk) if (wr_en) mem[wr_ptr] <= #TCQ d_in; assign mem_out = mem[rd_ptr]; assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH; always @ (posedge clk) begin if (rst) begin rd_ptr <= 'b0; rd_ptr_timing <= 'b0; end else if ((!my_empty[4]) & (!full_in)) begin rd_ptr <= nxt_rd_ptr; rd_ptr_timing <= nxt_rd_ptr; end end always @ (posedge clk) begin if (rst) my_empty <= 9'h1ff; else begin if (my_empty[2] & !my_full[3] & full_in & wr_en_in) my_empty[3:0] <= 4'b0000; else if (!my_empty[2] & !my_full[3] & !full_in & !wr_en_in) begin my_empty[0] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[1] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[2] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[3] <= (nxt_rd_ptr == wr_ptr_timing); end if (my_empty[8] & !my_full[5] & full_in & wr_en_in) my_empty[8:4] <= 5'b00000; else if (!my_empty[8] & !my_full[5] & !full_in & !wr_en_in) begin my_empty[4] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[5] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[6] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[7] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[8] <= (nxt_rd_ptr == wr_ptr_timing); end end end assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH; always @ (posedge clk) begin if (rst) begin wr_ptr <= 'b0; wr_ptr_timing <= 'b0; end else if ((wr_en_in) & ((!my_empty[5] & !full_in) | (!my_full[1] & full_in))) begin wr_ptr <= nxt_wr_ptr; wr_ptr_timing <= nxt_wr_ptr; end end always @ (posedge clk) begin if (rst) my_full <= 6'b000000; else if (!my_empty[6] & my_full[0] & !full_in & !wr_en_in) my_full <= 6'b000000; else if (!my_empty[6] & !my_full[0] & full_in & wr_en_in) begin my_full[0] <= (nxt_wr_ptr == rd_ptr_timing); my_full[1] <= (nxt_wr_ptr == rd_ptr_timing); my_full[2] <= (nxt_wr_ptr == rd_ptr_timing); my_full[3] <= (nxt_wr_ptr == rd_ptr_timing); my_full[4] <= (nxt_wr_ptr == rd_ptr_timing); my_full[5] <= (nxt_wr_ptr == rd_ptr_timing); end end always @ (posedge clk) begin if (rst) entry_cnt <= 'b0; else if (wr_en_in & full_in & !my_full[4]) entry_cnt <= entry_cnt + 1'b1; else if (!wr_en_in & !full_in & !my_empty[7]) entry_cnt <= entry_cnt - 1'b1; end assign afull = (entry_cnt >= ALMOST_FULL_VALUE); endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ddr_of_pre_fifo.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Feb 08 2011 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries //Reference : //Revision History : //***************************************************************************** /****************************************************************************** **$Id: ddr_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $ **$Date: 2011/06/02 08:35:07 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_of_pre_fifo.v,v $ ******************************************************************************/ `timescale 1 ps / 1 ps module mig_7series_v2_3_ddr_of_pre_fifo # ( parameter TCQ = 100, // clk->out delay (sim only) parameter DEPTH = 4, // # of entries parameter WIDTH = 32 // data bus width ) ( input clk, // clock input rst, // synchronous reset input full_in, // FULL flag from OUT_FIFO input wr_en_in, // write enable from controller input [WIDTH-1:0] d_in, // write data from controller output wr_en_out, // write enable to OUT_FIFO output [WIDTH-1:0] d_out, // write data to OUT_FIFO output afull // almost full signal to controller ); // # of bits used to represent read/write pointers localparam PTR_BITS = (DEPTH == 2) ? 1 : ((DEPTH == 3) || (DEPTH == 4)) ? 2 : (((DEPTH == 5) || (DEPTH == 6) || (DEPTH == 7) || (DEPTH == 8)) ? 3 : DEPTH == 9 ? 4 : 'bx); // Set watermark. Always give the MC 5 cycles to engage flow control. localparam ALMOST_FULL_VALUE = DEPTH - 5; integer i; reg [WIDTH-1:0] mem[0:DEPTH-1] ; reg [8:0] my_empty /* synthesis syn_maxfan = 3 */; reg [5:0] my_full /* synthesis syn_maxfan = 3 */; reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */; reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */; (* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */; (* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] wr_ptr_timing /* synthesis syn_maxfan = 10 */; reg [PTR_BITS:0] entry_cnt; wire [PTR_BITS-1:0] nxt_rd_ptr; wire [PTR_BITS-1:0] nxt_wr_ptr; wire [WIDTH-1:0] mem_out; (* max_fanout = 50 *) wire wr_en; assign d_out = my_empty[0] ? d_in : mem_out; assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in); assign wr_en = wr_en_in & ((!my_empty[3] & !full_in)|(!my_full[2] & full_in)); always @ (posedge clk) if (wr_en) mem[wr_ptr] <= #TCQ d_in; assign mem_out = mem[rd_ptr]; assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH; always @ (posedge clk) begin if (rst) begin rd_ptr <= 'b0; rd_ptr_timing <= 'b0; end else if ((!my_empty[4]) & (!full_in)) begin rd_ptr <= nxt_rd_ptr; rd_ptr_timing <= nxt_rd_ptr; end end always @ (posedge clk) begin if (rst) my_empty <= 9'h1ff; else begin if (my_empty[2] & !my_full[3] & full_in & wr_en_in) my_empty[3:0] <= 4'b0000; else if (!my_empty[2] & !my_full[3] & !full_in & !wr_en_in) begin my_empty[0] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[1] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[2] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[3] <= (nxt_rd_ptr == wr_ptr_timing); end if (my_empty[8] & !my_full[5] & full_in & wr_en_in) my_empty[8:4] <= 5'b00000; else if (!my_empty[8] & !my_full[5] & !full_in & !wr_en_in) begin my_empty[4] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[5] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[6] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[7] <= (nxt_rd_ptr == wr_ptr_timing); my_empty[8] <= (nxt_rd_ptr == wr_ptr_timing); end end end assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH; always @ (posedge clk) begin if (rst) begin wr_ptr <= 'b0; wr_ptr_timing <= 'b0; end else if ((wr_en_in) & ((!my_empty[5] & !full_in) | (!my_full[1] & full_in))) begin wr_ptr <= nxt_wr_ptr; wr_ptr_timing <= nxt_wr_ptr; end end always @ (posedge clk) begin if (rst) my_full <= 6'b000000; else if (!my_empty[6] & my_full[0] & !full_in & !wr_en_in) my_full <= 6'b000000; else if (!my_empty[6] & !my_full[0] & full_in & wr_en_in) begin my_full[0] <= (nxt_wr_ptr == rd_ptr_timing); my_full[1] <= (nxt_wr_ptr == rd_ptr_timing); my_full[2] <= (nxt_wr_ptr == rd_ptr_timing); my_full[3] <= (nxt_wr_ptr == rd_ptr_timing); my_full[4] <= (nxt_wr_ptr == rd_ptr_timing); my_full[5] <= (nxt_wr_ptr == rd_ptr_timing); end end always @ (posedge clk) begin if (rst) entry_cnt <= 'b0; else if (wr_en_in & full_in & !my_full[4]) entry_cnt <= entry_cnt + 1'b1; else if (!wr_en_in & !full_in & !my_empty[7]) entry_cnt <= entry_cnt - 1'b1; end assign afull = (entry_cnt >= ALMOST_FULL_VALUE); endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_ck_addr_cmd_delay.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Module to decrement initial PO delay to 0 and add 1/4 tck for tdqss //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_wrlvl_off_delay # ( parameter TCQ = 100, parameter tCK = 3636, parameter nCK_PER_CLK = 2, parameter CLK_PERIOD = 4, parameter PO_INITIAL_DLY= 46, parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 8, parameter N_CTL_LANES = 3 ) ( input clk, input rst, input pi_fine_dly_dec_done, input cmd_delay_start, // Control lane being shifted using Phaser_Out fine delay taps output reg [DQS_CNT_WIDTH:0] ctl_lane_cnt, // Inc/dec Phaser_Out fine delay line output reg po_s2_incdec_f, output reg po_en_s2_f, // Inc/dec Phaser_Out coarse delay line output reg po_s2_incdec_c, output reg po_en_s2_c, // Completed adjusting delays for dq, dqs for tdqss output po_ck_addr_cmd_delay_done, // completed decrementing initialPO delays output po_dec_done, output phy_ctl_rdy_dly ); localparam TAP_LIMIT = 63; // PO fine delay tap resolution change by frequency. tCK > 2500, need // twice the amount of taps // localparam D_DLY_F = (tCK > 2500 ) ? D_DLY * 2 : D_DLY; // coarse delay tap is added DQ/DQS to meet the TDQSS specification. localparam TDQSS_DLY = (tCK > 2500 )? 2: 1; reg delay_done; reg delay_done_r1; reg delay_done_r2; reg delay_done_r3; reg delay_done_r4; reg [5:0] po_delay_cnt_r; reg po_cnt_inc; reg cmd_delay_start_r1; reg cmd_delay_start_r2; reg cmd_delay_start_r3; reg cmd_delay_start_r4; reg cmd_delay_start_r5; reg cmd_delay_start_r6; reg po_delay_done; reg po_delay_done_r1; reg po_delay_done_r2; reg po_delay_done_r3; reg po_delay_done_r4; reg pi_fine_dly_dec_done_r; reg po_en_stg2_c; reg po_en_stg2_f; reg po_stg2_incdec_c; reg po_stg2_f_incdec; reg [DQS_CNT_WIDTH:0] lane_cnt_dqs_c_r; reg [DQS_CNT_WIDTH:0] lane_cnt_po_r; reg [5:0] delay_cnt_r; always @(posedge clk) begin cmd_delay_start_r1 <= #TCQ cmd_delay_start; cmd_delay_start_r2 <= #TCQ cmd_delay_start_r1; cmd_delay_start_r3 <= #TCQ cmd_delay_start_r2; cmd_delay_start_r4 <= #TCQ cmd_delay_start_r3; cmd_delay_start_r5 <= #TCQ cmd_delay_start_r4; cmd_delay_start_r6 <= #TCQ cmd_delay_start_r5; pi_fine_dly_dec_done_r <= #TCQ pi_fine_dly_dec_done; end assign phy_ctl_rdy_dly = cmd_delay_start_r6; // logic for decrementing initial fine delay taps for all PO // Decrement done for add, ctrl and data phaser outs assign po_dec_done = (PO_INITIAL_DLY == 0) ? 1 : po_delay_done_r4; always @(posedge clk) if (rst || ~cmd_delay_start_r6 || po_delay_done) begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b0; end else if (po_delay_cnt_r > 6'd0) begin po_en_stg2_f <= #TCQ ~po_en_stg2_f; end always @(posedge clk) if (rst || ~cmd_delay_start_r6 || (po_delay_cnt_r == 6'd0)) // set all the PO delays to 31. Decrement from 46 to 31. // Requirement comes from dqs_found logic po_delay_cnt_r <= #TCQ (PO_INITIAL_DLY - 31); else if ( po_en_stg2_f && (po_delay_cnt_r > 6'd0)) po_delay_cnt_r <= #TCQ po_delay_cnt_r - 1; always @(posedge clk) if (rst) lane_cnt_po_r <= #TCQ 'd0; else if ( po_en_stg2_f && (po_delay_cnt_r == 6'd1)) lane_cnt_po_r <= #TCQ lane_cnt_po_r + 1; always @(posedge clk) if (rst || ~cmd_delay_start_r6 ) po_delay_done <= #TCQ 1'b0; else if ((po_delay_cnt_r == 6'd1) && (lane_cnt_po_r ==1'b0)) po_delay_done <= #TCQ 1'b1; always @(posedge clk) begin po_delay_done_r1 <= #TCQ po_delay_done; po_delay_done_r2 <= #TCQ po_delay_done_r1; po_delay_done_r3 <= #TCQ po_delay_done_r2; po_delay_done_r4 <= #TCQ po_delay_done_r3; end // logic to select between all PO delays and data path delay. always @(posedge clk) begin po_s2_incdec_f <= #TCQ po_stg2_f_incdec; po_en_s2_f <= #TCQ po_en_stg2_f; end // Logic to add 1/4 taps amount of delay to data path for tdqss. // After all the initial PO delays are decremented the 1/4 delay will // be added. Coarse delay taps will be added here . // Delay added only to data path assign po_ck_addr_cmd_delay_done = (TDQSS_DLY == 0) ? pi_fine_dly_dec_done_r : delay_done_r4; always @(posedge clk) if (rst || ~pi_fine_dly_dec_done_r || delay_done) begin po_stg2_incdec_c <= #TCQ 1'b1; po_en_stg2_c <= #TCQ 1'b0; end else if (delay_cnt_r > 6'd0) begin po_en_stg2_c <= #TCQ ~po_en_stg2_c; end always @(posedge clk) if (rst || ~pi_fine_dly_dec_done_r || (delay_cnt_r == 6'd0)) delay_cnt_r <= #TCQ TDQSS_DLY; else if ( po_en_stg2_c && (delay_cnt_r > 6'd0)) delay_cnt_r <= #TCQ delay_cnt_r - 1; always @(posedge clk) if (rst) lane_cnt_dqs_c_r <= #TCQ 'd0; else if ( po_en_stg2_c && (delay_cnt_r == 6'd1)) lane_cnt_dqs_c_r <= #TCQ lane_cnt_dqs_c_r + 1; always @(posedge clk) if (rst || ~pi_fine_dly_dec_done_r) delay_done <= #TCQ 1'b0; else if ((delay_cnt_r == 6'd1) && (lane_cnt_dqs_c_r == 1'b0)) delay_done <= #TCQ 1'b1; always @(posedge clk) begin delay_done_r1 <= #TCQ delay_done; delay_done_r2 <= #TCQ delay_done_r1; delay_done_r3 <= #TCQ delay_done_r2; delay_done_r4 <= #TCQ delay_done_r3; end always @(posedge clk) begin po_s2_incdec_c <= #TCQ po_stg2_incdec_c; po_en_s2_c <= #TCQ po_en_stg2_c; ctl_lane_cnt <= #TCQ lane_cnt_dqs_c_r; end endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_ck_addr_cmd_delay.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Module to decrement initial PO delay to 0 and add 1/4 tck for tdqss //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_wrlvl_off_delay # ( parameter TCQ = 100, parameter tCK = 3636, parameter nCK_PER_CLK = 2, parameter CLK_PERIOD = 4, parameter PO_INITIAL_DLY= 46, parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 8, parameter N_CTL_LANES = 3 ) ( input clk, input rst, input pi_fine_dly_dec_done, input cmd_delay_start, // Control lane being shifted using Phaser_Out fine delay taps output reg [DQS_CNT_WIDTH:0] ctl_lane_cnt, // Inc/dec Phaser_Out fine delay line output reg po_s2_incdec_f, output reg po_en_s2_f, // Inc/dec Phaser_Out coarse delay line output reg po_s2_incdec_c, output reg po_en_s2_c, // Completed adjusting delays for dq, dqs for tdqss output po_ck_addr_cmd_delay_done, // completed decrementing initialPO delays output po_dec_done, output phy_ctl_rdy_dly ); localparam TAP_LIMIT = 63; // PO fine delay tap resolution change by frequency. tCK > 2500, need // twice the amount of taps // localparam D_DLY_F = (tCK > 2500 ) ? D_DLY * 2 : D_DLY; // coarse delay tap is added DQ/DQS to meet the TDQSS specification. localparam TDQSS_DLY = (tCK > 2500 )? 2: 1; reg delay_done; reg delay_done_r1; reg delay_done_r2; reg delay_done_r3; reg delay_done_r4; reg [5:0] po_delay_cnt_r; reg po_cnt_inc; reg cmd_delay_start_r1; reg cmd_delay_start_r2; reg cmd_delay_start_r3; reg cmd_delay_start_r4; reg cmd_delay_start_r5; reg cmd_delay_start_r6; reg po_delay_done; reg po_delay_done_r1; reg po_delay_done_r2; reg po_delay_done_r3; reg po_delay_done_r4; reg pi_fine_dly_dec_done_r; reg po_en_stg2_c; reg po_en_stg2_f; reg po_stg2_incdec_c; reg po_stg2_f_incdec; reg [DQS_CNT_WIDTH:0] lane_cnt_dqs_c_r; reg [DQS_CNT_WIDTH:0] lane_cnt_po_r; reg [5:0] delay_cnt_r; always @(posedge clk) begin cmd_delay_start_r1 <= #TCQ cmd_delay_start; cmd_delay_start_r2 <= #TCQ cmd_delay_start_r1; cmd_delay_start_r3 <= #TCQ cmd_delay_start_r2; cmd_delay_start_r4 <= #TCQ cmd_delay_start_r3; cmd_delay_start_r5 <= #TCQ cmd_delay_start_r4; cmd_delay_start_r6 <= #TCQ cmd_delay_start_r5; pi_fine_dly_dec_done_r <= #TCQ pi_fine_dly_dec_done; end assign phy_ctl_rdy_dly = cmd_delay_start_r6; // logic for decrementing initial fine delay taps for all PO // Decrement done for add, ctrl and data phaser outs assign po_dec_done = (PO_INITIAL_DLY == 0) ? 1 : po_delay_done_r4; always @(posedge clk) if (rst || ~cmd_delay_start_r6 || po_delay_done) begin po_stg2_f_incdec <= #TCQ 1'b0; po_en_stg2_f <= #TCQ 1'b0; end else if (po_delay_cnt_r > 6'd0) begin po_en_stg2_f <= #TCQ ~po_en_stg2_f; end always @(posedge clk) if (rst || ~cmd_delay_start_r6 || (po_delay_cnt_r == 6'd0)) // set all the PO delays to 31. Decrement from 46 to 31. // Requirement comes from dqs_found logic po_delay_cnt_r <= #TCQ (PO_INITIAL_DLY - 31); else if ( po_en_stg2_f && (po_delay_cnt_r > 6'd0)) po_delay_cnt_r <= #TCQ po_delay_cnt_r - 1; always @(posedge clk) if (rst) lane_cnt_po_r <= #TCQ 'd0; else if ( po_en_stg2_f && (po_delay_cnt_r == 6'd1)) lane_cnt_po_r <= #TCQ lane_cnt_po_r + 1; always @(posedge clk) if (rst || ~cmd_delay_start_r6 ) po_delay_done <= #TCQ 1'b0; else if ((po_delay_cnt_r == 6'd1) && (lane_cnt_po_r ==1'b0)) po_delay_done <= #TCQ 1'b1; always @(posedge clk) begin po_delay_done_r1 <= #TCQ po_delay_done; po_delay_done_r2 <= #TCQ po_delay_done_r1; po_delay_done_r3 <= #TCQ po_delay_done_r2; po_delay_done_r4 <= #TCQ po_delay_done_r3; end // logic to select between all PO delays and data path delay. always @(posedge clk) begin po_s2_incdec_f <= #TCQ po_stg2_f_incdec; po_en_s2_f <= #TCQ po_en_stg2_f; end // Logic to add 1/4 taps amount of delay to data path for tdqss. // After all the initial PO delays are decremented the 1/4 delay will // be added. Coarse delay taps will be added here . // Delay added only to data path assign po_ck_addr_cmd_delay_done = (TDQSS_DLY == 0) ? pi_fine_dly_dec_done_r : delay_done_r4; always @(posedge clk) if (rst || ~pi_fine_dly_dec_done_r || delay_done) begin po_stg2_incdec_c <= #TCQ 1'b1; po_en_stg2_c <= #TCQ 1'b0; end else if (delay_cnt_r > 6'd0) begin po_en_stg2_c <= #TCQ ~po_en_stg2_c; end always @(posedge clk) if (rst || ~pi_fine_dly_dec_done_r || (delay_cnt_r == 6'd0)) delay_cnt_r <= #TCQ TDQSS_DLY; else if ( po_en_stg2_c && (delay_cnt_r > 6'd0)) delay_cnt_r <= #TCQ delay_cnt_r - 1; always @(posedge clk) if (rst) lane_cnt_dqs_c_r <= #TCQ 'd0; else if ( po_en_stg2_c && (delay_cnt_r == 6'd1)) lane_cnt_dqs_c_r <= #TCQ lane_cnt_dqs_c_r + 1; always @(posedge clk) if (rst || ~pi_fine_dly_dec_done_r) delay_done <= #TCQ 1'b0; else if ((delay_cnt_r == 6'd1) && (lane_cnt_dqs_c_r == 1'b0)) delay_done <= #TCQ 1'b1; always @(posedge clk) begin delay_done_r1 <= #TCQ delay_done; delay_done_r2 <= #TCQ delay_done_r1; delay_done_r3 <= #TCQ delay_done_r2; delay_done_r4 <= #TCQ delay_done_r3; end always @(posedge clk) begin po_s2_incdec_c <= #TCQ po_stg2_incdec_c; po_en_s2_c <= #TCQ po_en_stg2_c; ctl_lane_cnt <= #TCQ lane_cnt_dqs_c_r; end endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : mig_7series_v1_x_ddr_if_post_fifo.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Feb 08 2011 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Extends the depth of a PHASER IN_FIFO up to 4 entries //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_ddr_if_post_fifo # ( parameter TCQ = 100, // clk->out delay (sim only) parameter DEPTH = 4, // # of entries parameter WIDTH = 32 // data bus width ) ( input clk, // clock input rst, // synchronous reset input [3:0] empty_in, input rd_en_in, input [WIDTH-1:0] d_in, // write data from controller output empty_out, output byte_rd_en, output [WIDTH-1:0] d_out // write data to OUT_FIFO ); // # of bits used to represent read/write pointers localparam PTR_BITS = (DEPTH == 2) ? 1 : (((DEPTH == 3) || (DEPTH == 4)) ? 2 : 'bx); integer i; reg [WIDTH-1:0] mem[0:DEPTH-1]; (* max_fanout = 40 *) reg [4:0] my_empty /* synthesis syn_maxfan = 3 */; (* max_fanout = 40 *) reg [1:0] my_full /* synthesis syn_maxfan = 3 */; reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */; // Register duplication to reduce the fan out (* KEEP = "TRUE" *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */; reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */; wire [WIDTH-1:0] mem_out; (* max_fanout = 40 *) wire wr_en /* synthesis syn_maxfan = 10 */; task updt_ptrs; input rd; input wr; reg [1:0] next_rd_ptr; reg [1:0] next_wr_ptr; begin next_rd_ptr = (rd_ptr + 1'b1)%DEPTH; next_wr_ptr = (wr_ptr + 1'b1)%DEPTH; casez ({rd, wr, my_empty[1], my_full[1]}) 4'b00zz: ; // No access, do nothing 4'b0100: begin // Write when neither empty, nor full; check for full wr_ptr <= #TCQ next_wr_ptr; my_full[0] <= #TCQ (next_wr_ptr == rd_ptr); my_full[1] <= #TCQ (next_wr_ptr == rd_ptr); //mem[wr_ptr] <= #TCQ d_in; end 4'b0110: begin // Write when empty; no need to check for full wr_ptr <= #TCQ next_wr_ptr; my_empty <= #TCQ 5'b00000; //mem[wr_ptr] <= #TCQ d_in; end 4'b1000: begin // Read when neither empty, nor full; check for empty rd_ptr <= #TCQ next_rd_ptr; rd_ptr_timing <= #TCQ next_rd_ptr; my_empty[0] <= #TCQ (next_rd_ptr == wr_ptr); my_empty[1] <= #TCQ (next_rd_ptr == wr_ptr); my_empty[2] <= #TCQ (next_rd_ptr == wr_ptr); my_empty[3] <= #TCQ (next_rd_ptr == wr_ptr); my_empty[4] <= #TCQ (next_rd_ptr == wr_ptr); end 4'b1001: begin // Read when full; no need to check for empty rd_ptr <= #TCQ next_rd_ptr; rd_ptr_timing <= #TCQ next_rd_ptr; my_full[0] <= #TCQ 1'b0; my_full[1] <= #TCQ 1'b0; end 4'b1100, 4'b1101, 4'b1110: begin // Read and write when empty, full, or neither empty/full; no need // to check for empty or full conditions rd_ptr <= #TCQ next_rd_ptr; rd_ptr_timing <= #TCQ next_rd_ptr; wr_ptr <= #TCQ next_wr_ptr; //mem[wr_ptr] <= #TCQ d_in; end 4'b0101, 4'b1010: ; // Read when empty, Write when full; Keep all pointers the same // and don't change any of the flags (i.e. ignore the read/write). // This might happen because a faulty DQS_FOUND calibration could // result in excessive skew between when the various IN_FIFO's // first become not empty. In this case, the data going to each // post-FIFO/IN_FIFO should be read out and discarded // synthesis translate_off default: begin // Covers any other cases, in particular for simulation if // any signals are X's $display("ERR %m @%t: Bad access: rd:%b,wr:%b,empty:%b,full:%b", $time, rd, wr, my_empty[1], my_full[1]); rd_ptr <= #TCQ 2'bxx; rd_ptr_timing <= #TCQ 2'bxx; wr_ptr <= #TCQ 2'bxx; end // synthesis translate_on endcase end endtask assign d_out = my_empty[4] ? d_in : mem_out;//mem[rd_ptr]; // The combined IN_FIFO + post FIFO is only "empty" when both are empty assign empty_out = empty_in[0] & my_empty[0]; assign byte_rd_en = !empty_in[3] || !my_empty[3]; always @(posedge clk) if (rst) begin my_empty <= #TCQ 5'b11111; my_full <= #TCQ 2'b00; rd_ptr <= #TCQ 'b0; rd_ptr_timing <= #TCQ 'b0; wr_ptr <= #TCQ 'b0; end else begin // Special mode: If IN_FIFO has data, and controller is reading at // the same time, then operate post-FIFO in "passthrough" mode (i.e. // don't update any of the read/write pointers, and route IN_FIFO // data to post-FIFO data) if (my_empty[1] && !my_full[1] && rd_en_in && !empty_in[1]) ; else // Otherwise, we're writing to FIFO when IN_FIFO is not empty, // and reading from the FIFO based on the rd_en_in signal (read // enable from controller). The functino updt_ptrs should catch // an illegal conditions. updt_ptrs(rd_en_in, !empty_in[1]); end assign wr_en = (!empty_in[2] & ((!rd_en_in & !my_full[0]) | (rd_en_in & !my_empty[2]))); always @ (posedge clk) begin if (wr_en) mem[wr_ptr] <= #TCQ d_in; end assign mem_out = mem[rd_ptr_timing]; endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_oclkdelay_cal.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3 // delay //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_oclkdelay_cal # (parameter TCQ = 100, parameter nCK_PER_CLK = 4, parameter DRAM_WIDTH = 8, parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 8, parameter DQ_WIDTH = 64, parameter MMCM_SAMP_WAIT = 10, parameter OCAL_SIMPLE_SCAN_SAMPS = 2, parameter PCT_SAMPS_SOLID = 95, parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter SCAN_PCT_SAMPS_SOLID = 95, parameter SIM_CAL_OPTION = "NONE", parameter SAMPCNTRWIDTH = 8, parameter SAMPLES = 128, parameter TAPCNTRWIDTH = 7, parameter TAPSPERKCLK = 56, parameter BYPASS_COMPLEX_OCAL = "FALSE") (/*AUTOARG*/ // Outputs wrlvl_final, rd_victim_sel, psincdec, psen, poc_error, po_stg3_incdec, po_stg23_sel, po_stg23_incdec, po_en_stg3, po_en_stg23, oclkdelay_center_calib_start, oclkdelay_center_calib_done, oclk_prech_req, oclk_init_delay_done, oclk_center_write_resume, oclk_calib_resume, ocal_num_samples_done_r, lim2init_write_request, complex_wrlvl_final, complex_oclkdelay_calib_done, oclkdelay_calib_cnt, dbg_phy_oclkdelay_cal, dbg_oclkdelay_rd_data, oclkdelay_calib_done, f2o, f2z, o2f, z2f, fuzz2oneeighty, fuzz2zero, oneeighty2fuzz, zero2fuzz, lim_done, dbg_ocd_lim, // Inputs wl_po_fine_cnt, rst, poc_sample_pd, psdone, prech_done, prbs_o, prbs_ignore_last_bytes, prbs_ignore_first_byte, po_counter_read_val, phy_rddata_en, phy_rddata, oclkdelay_init_val, oclkdelay_calib_start, ocal_num_samples_inc, metaQ, complex_oclkdelay_calib_start, clk ); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input clk; // To u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v, ... input complex_oclkdelay_calib_start;// To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v, ... input metaQ; // To u_poc of mig_7series_v2_3_poc_top.v input ocal_num_samples_inc; // To u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v input oclkdelay_calib_start; // To u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v input [5:0] oclkdelay_init_val; // To u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v, ... input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;// To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v input phy_rddata_en; // To u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v input [8:0] po_counter_read_val; // To u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v, ... input poc_sample_pd; input prbs_ignore_first_byte; // To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v input prbs_ignore_last_bytes; // To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; // To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v input prech_done; // To u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v, ... input psdone; // To u_poc of mig_7series_v2_3_poc_top.v input rst; // To u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v, ... input [6*DQS_WIDTH-1:0] wl_po_fine_cnt; // To u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output complex_oclkdelay_calib_done;// From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v output complex_wrlvl_final; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v output lim2init_write_request; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v output ocal_num_samples_done_r;// From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v output oclk_calib_resume; // From u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v output oclk_center_write_resume;// From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v output oclk_init_delay_done; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v output oclk_prech_req; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v output oclkdelay_center_calib_done;// From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v output oclkdelay_center_calib_start;// From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v output po_en_stg23; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v output po_en_stg3; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v output po_stg23_incdec; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v output po_stg23_sel; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v output po_stg3_incdec; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v output poc_error; // From u_poc of mig_7series_v2_3_poc_top.v output psen; // From u_poc of mig_7series_v2_3_poc_top.v output psincdec; // From u_poc of mig_7series_v2_3_poc_top.v output [2:0] rd_victim_sel; // From u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v output wrlvl_final; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire ktap_at_left_edge; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v wire ktap_at_right_edge; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v wire lim2init_prech_req; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire [5:0] lim2ocal_stg3_left_lim; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire [5:0] lim2ocal_stg3_right_lim;// From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire lim2poc_ktap_right; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire lim2poc_rdy; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire lim2stg2_dec; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire lim2stg2_inc; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire lim2stg3_dec; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire lim2stg3_inc; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire lim_start; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v wire [1:0] match; // From u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v wire mmcm_edge_detect_done; // From u_poc of mig_7series_v2_3_poc_top.v wire mmcm_edge_detect_rdy; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v wire mmcm_lbclk_edge_aligned;// From u_poc of mig_7series_v2_3_poc_top.v wire [1:0] ninety_offsets; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd2stg2_dec; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd2stg2_inc; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd2stg3_dec; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd2stg3_inc; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd_cntlr2stg2_dec; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v wire ocd_edge_detect_rdy; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd_ktap_left; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd_ktap_right; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd_prech_req; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v wire phy_rddata_en_1; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v wire phy_rddata_en_2; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v wire phy_rddata_en_3; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v wire po_rdy; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v wire poc_backup; // From u_poc of mig_7series_v2_3_poc_top.v wire reset_scan; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v wire [TAPCNTRWIDTH-1:0] rise_lead_right; // From u_poc of mig_7series_v2_3_poc_top.v wire [TAPCNTRWIDTH-1:0] rise_trail_right; // From u_poc of mig_7series_v2_3_poc_top.v wire samp_done; // From u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v wire [1:0] samp_result; // From u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v wire scan_done; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire scan_right; // From u_ocd_edge of mig_7series_v2_3_ddr_phy_ocd_edge.v wire scanning_right; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire [5:0] simp_stg3_final_sel; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire [5:0] stg3; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire taps_set; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire use_noise_window; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire [5:0] wl_po_fine_cnt_sel; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v // End of automatics wire [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final; wire ocal_scan_win_not_found; output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; output [255:0] dbg_phy_oclkdelay_cal; output [16*DRAM_WIDTH-1:0] dbg_oclkdelay_rd_data; output oclkdelay_calib_done; output f2o; output f2z; output o2f; output z2f; output [5:0] fuzz2oneeighty; output [5:0] fuzz2zero; output [5:0] oneeighty2fuzz; output [5:0] zero2fuzz; output lim_done; output [255:0] dbg_ocd_lim; // Debug signals assign dbg_phy_oclkdelay_cal[0] = f2o; assign dbg_phy_oclkdelay_cal[1] = f2z; assign dbg_phy_oclkdelay_cal[2] = o2f; assign dbg_phy_oclkdelay_cal[3] = z2f; assign dbg_phy_oclkdelay_cal[4+:6] = fuzz2oneeighty; assign dbg_phy_oclkdelay_cal[10+:6] = fuzz2zero; assign dbg_phy_oclkdelay_cal[16+:6] = oneeighty2fuzz; assign dbg_phy_oclkdelay_cal[22+:6] = zero2fuzz; assign dbg_phy_oclkdelay_cal[28+:3] = oclkdelay_calib_cnt; assign dbg_phy_oclkdelay_cal[31] = oclkdelay_calib_start; assign dbg_phy_oclkdelay_cal[32] = lim_done; assign dbg_phy_oclkdelay_cal[33+:6] =lim2ocal_stg3_left_lim ; assign dbg_phy_oclkdelay_cal[39+:6] = lim2ocal_stg3_right_lim ; assign dbg_phy_oclkdelay_cal[45+:8] = po_counter_read_val[8:0]; assign dbg_phy_oclkdelay_cal[53+:54] = simp_stg3_final[DQS_WIDTH*6-1:0]; assign dbg_phy_oclkdelay_cal[107] = ocal_scan_win_not_found; assign dbg_phy_oclkdelay_cal[108] = oclkdelay_center_calib_start; assign dbg_phy_oclkdelay_cal[109] = oclkdelay_center_calib_done; assign dbg_phy_oclkdelay_cal[115:110] = stg3[5:0]; mig_7series_v2_3_ddr_phy_ocd_lim # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ), .TDQSS_DEGREES (), .BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL)) // Templated u_ocd_lim (/*AUTOINST*/ // Outputs .lim2init_prech_req (lim2init_prech_req), .lim2init_write_request (lim2init_write_request), .lim2ocal_stg3_left_lim (lim2ocal_stg3_left_lim[5:0]), .lim2ocal_stg3_right_lim (lim2ocal_stg3_right_lim[5:0]), .lim2poc_ktap_right (lim2poc_ktap_right), .lim2poc_rdy (lim2poc_rdy), .lim2stg2_dec (lim2stg2_dec), .lim2stg2_inc (lim2stg2_inc), .lim2stg3_dec (lim2stg3_dec), .lim2stg3_inc (lim2stg3_inc), .lim_done (lim_done), // Inputs .clk (clk), .lim_start (lim_start), .oclkdelay_calib_done (oclkdelay_calib_done), .oclkdelay_init_val (oclkdelay_init_val[5:0]), .po_rdy (po_rdy), .poc2lim_detect_done (mmcm_edge_detect_done), // Templated .poc2lim_fall_align_taps_lead ({TAPCNTRWIDTH{1'b0}}), // Templated .poc2lim_fall_align_taps_trail ({TAPCNTRWIDTH{1'b0}}), // Templated .poc2lim_rise_align_taps_lead (rise_lead_right), // Templated .poc2lim_rise_align_taps_trail (rise_trail_right), // Templated .prech_done (prech_done), .rst (rst), .simp_stg3_final_sel (simp_stg3_final_sel[5:0]), .wl_po_fine_cnt (wl_po_fine_cnt_sel[5:0]), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .dbg_ocd_lim (dbg_ocd_lim)); // Templated /*mig_7series_v2_3_poc_top AUTO_TEMPLATE( .CCENABLE (0), .SCANFROMRIGHT (1), .pd_out (metaQ),); */ mig_7series_v2_3_poc_top # (/*AUTOINSTPARAM*/ // Parameters .CCENABLE (0), // Templated .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), .PCT_SAMPS_SOLID (PCT_SAMPS_SOLID), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .SAMPLES (SAMPLES), .SCANFROMRIGHT (1), // Templated .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_poc (/*AUTOINST*/ // Outputs .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .poc_backup (poc_backup), .poc_error (poc_error), .psen (psen), .psincdec (psincdec), .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), // Inputs .clk (clk), .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), .ninety_offsets (ninety_offsets[1:0]), .pd_out (metaQ), // Templated .poc_sample_pd (poc_sample_pd), .psdone (psdone), .rst (rst), .use_noise_window (use_noise_window)); mig_7series_v2_3_ddr_phy_ocd_mux # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .TCQ (TCQ)) u_ocd_mux (/*AUTOINST*/ // Outputs .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), .oclk_prech_req (oclk_prech_req), .po_en_stg23 (po_en_stg23), .po_en_stg3 (po_en_stg3), .po_rdy (po_rdy), .po_stg23_incdec (po_stg23_incdec), .po_stg23_sel (po_stg23_sel), .po_stg3_incdec (po_stg3_incdec), .wl_po_fine_cnt_sel (wl_po_fine_cnt_sel[5:0]), // Inputs .clk (clk), .lim2init_prech_req (lim2init_prech_req), .lim2poc_ktap_right (lim2poc_ktap_right), .lim2poc_rdy (lim2poc_rdy), .lim2stg2_dec (lim2stg2_dec), .lim2stg2_inc (lim2stg2_inc), .lim2stg3_dec (lim2stg3_dec), .lim2stg3_inc (lim2stg3_inc), .ocd2stg2_dec (ocd2stg2_dec), .ocd2stg2_inc (ocd2stg2_inc), .ocd2stg3_dec (ocd2stg3_dec), .ocd2stg3_inc (ocd2stg3_inc), .ocd_cntlr2stg2_dec (ocd_cntlr2stg2_dec), .ocd_edge_detect_rdy (ocd_edge_detect_rdy), .ocd_ktap_left (ocd_ktap_left), .ocd_ktap_right (ocd_ktap_right), .ocd_prech_req (ocd_prech_req), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .rst (rst), .wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0])); mig_7series_v2_3_ddr_phy_ocd_data # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQ_WIDTH (DQ_WIDTH), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK)) u_ocd_data (/*AUTOINST*/ // Outputs .match (match[1:0]), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]), .phy_rddata_en_1 (phy_rddata_en_1), .prbs_ignore_first_byte (prbs_ignore_first_byte), .prbs_ignore_last_bytes (prbs_ignore_last_bytes), .prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]), .rst (rst)); mig_7series_v2_3_ddr_phy_ocd_samp # (/*AUTOINSTPARAM*/ // Parameters .OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS), .SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID), .SIM_CAL_OPTION (SIM_CAL_OPTION), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK)) u_ocd_samp (/*AUTOINST*/ // Outputs .oclk_calib_resume (oclk_calib_resume), .rd_victim_sel (rd_victim_sel[2:0]), .samp_done (samp_done), .samp_result (samp_result[1:0]), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .match (match[1:0]), .ocal_num_samples_inc (ocal_num_samples_inc), .phy_rddata_en_1 (phy_rddata_en_1), .reset_scan (reset_scan), .rst (rst), .taps_set (taps_set)); mig_7series_v2_3_ddr_phy_ocd_edge # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ)) u_ocd_edge (/*AUTOINST*/ // Outputs .f2o (f2o), .f2z (f2z), .fuzz2oneeighty (fuzz2oneeighty[5:0]), .fuzz2zero (fuzz2zero[5:0]), .o2f (o2f), .oneeighty2fuzz (oneeighty2fuzz[5:0]), .scan_right (scan_right), .z2f (z2f), .zero2fuzz (zero2fuzz[5:0]), // Inputs .clk (clk), .phy_rddata_en_2 (phy_rddata_en_2), .reset_scan (reset_scan), .samp_done (samp_done), .samp_result (samp_result[1:0]), .scanning_right (scanning_right), .stg3 (stg3[5:0])); mig_7series_v2_3_ddr_phy_ocd_cntlr # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .TCQ (TCQ)) u_ocd_cntlr (/*AUTOINST*/ // Outputs .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done), .complex_wrlvl_final (complex_wrlvl_final), .lim_start (lim_start), .ocd_cntlr2stg2_dec (ocd_cntlr2stg2_dec), .ocd_prech_req (ocd_prech_req), .oclk_init_delay_done (oclk_init_delay_done), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .oclkdelay_calib_done (oclkdelay_calib_done), .phy_rddata_en_1 (phy_rddata_en_1), .phy_rddata_en_2 (phy_rddata_en_2), .phy_rddata_en_3 (phy_rddata_en_3), .reset_scan (reset_scan), .wrlvl_final (wrlvl_final), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .lim_done (lim_done), .oclkdelay_calib_start (oclkdelay_calib_start), .phy_rddata_en (phy_rddata_en), .po_counter_read_val (po_counter_read_val[8:0]), .po_rdy (po_rdy), .prech_done (prech_done), .rst (rst), .scan_done (scan_done)); mig_7series_v2_3_ddr_phy_ocd_po_cntlr # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK)) u_ocd_po_cntlr (.cmplx_stg3_final (cmplx_stg3_final[DQS_WIDTH*6-1:0]), .ocal_scan_win_not_found (ocal_scan_win_not_found), .simp_stg3_final (simp_stg3_final[DQS_WIDTH*6-1:0]), /*AUTOINST*/ // Outputs .ninety_offsets (ninety_offsets[1:0]), .ocal_num_samples_done_r (ocal_num_samples_done_r), .ocd2stg2_dec (ocd2stg2_dec), .ocd2stg2_inc (ocd2stg2_inc), .ocd2stg3_dec (ocd2stg3_dec), .ocd2stg3_inc (ocd2stg3_inc), .ocd_edge_detect_rdy (ocd_edge_detect_rdy), .ocd_ktap_left (ocd_ktap_left), .ocd_ktap_right (ocd_ktap_right), .oclk_center_write_resume (oclk_center_write_resume), .oclkdelay_center_calib_done (oclkdelay_center_calib_done), .oclkdelay_center_calib_start (oclkdelay_center_calib_start), .scan_done (scan_done), .scanning_right (scanning_right), .simp_stg3_final_sel (simp_stg3_final_sel[5:0]), .stg3 (stg3[5:0]), .taps_set (taps_set), .use_noise_window (use_noise_window), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .f2o (f2o), .f2z (f2z), .fuzz2oneeighty (fuzz2oneeighty[5:0]), .fuzz2zero (fuzz2zero[5:0]), .lim2ocal_stg3_left_lim (lim2ocal_stg3_left_lim[5:0]), .lim2ocal_stg3_right_lim (lim2ocal_stg3_right_lim[5:0]), .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .o2f (o2f), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .oclkdelay_init_val (oclkdelay_init_val[5:0]), .oneeighty2fuzz (oneeighty2fuzz[5:0]), .phy_rddata_en_3 (phy_rddata_en_3), .po_counter_read_val (po_counter_read_val[8:0]), .po_rdy (po_rdy), .poc_backup (poc_backup), .reset_scan (reset_scan), .rst (rst), .samp_done (samp_done), .scan_right (scan_right), .wl_po_fine_cnt_sel (wl_po_fine_cnt_sel[5:0]), .z2f (z2f), .zero2fuzz (zero2fuzz[5:0])); endmodule // mig_7series_v2_3_ddr_phy_oclkdelay_cal // Local Variables: // verilog-library-directories:(".") // verilog-library-extensions:(".v") // End:

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Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_oclkdelay_cal.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3 // delay //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_oclkdelay_cal # (parameter TCQ = 100, parameter nCK_PER_CLK = 4, parameter DRAM_WIDTH = 8, parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 8, parameter DQ_WIDTH = 64, parameter MMCM_SAMP_WAIT = 10, parameter OCAL_SIMPLE_SCAN_SAMPS = 2, parameter PCT_SAMPS_SOLID = 95, parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter SCAN_PCT_SAMPS_SOLID = 95, parameter SIM_CAL_OPTION = "NONE", parameter SAMPCNTRWIDTH = 8, parameter SAMPLES = 128, parameter TAPCNTRWIDTH = 7, parameter TAPSPERKCLK = 56, parameter BYPASS_COMPLEX_OCAL = "FALSE") (/*AUTOARG*/ // Outputs wrlvl_final, rd_victim_sel, psincdec, psen, poc_error, po_stg3_incdec, po_stg23_sel, po_stg23_incdec, po_en_stg3, po_en_stg23, oclkdelay_center_calib_start, oclkdelay_center_calib_done, oclk_prech_req, oclk_init_delay_done, oclk_center_write_resume, oclk_calib_resume, ocal_num_samples_done_r, lim2init_write_request, complex_wrlvl_final, complex_oclkdelay_calib_done, oclkdelay_calib_cnt, dbg_phy_oclkdelay_cal, dbg_oclkdelay_rd_data, oclkdelay_calib_done, f2o, f2z, o2f, z2f, fuzz2oneeighty, fuzz2zero, oneeighty2fuzz, zero2fuzz, lim_done, dbg_ocd_lim, // Inputs wl_po_fine_cnt, rst, poc_sample_pd, psdone, prech_done, prbs_o, prbs_ignore_last_bytes, prbs_ignore_first_byte, po_counter_read_val, phy_rddata_en, phy_rddata, oclkdelay_init_val, oclkdelay_calib_start, ocal_num_samples_inc, metaQ, complex_oclkdelay_calib_start, clk ); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input clk; // To u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v, ... input complex_oclkdelay_calib_start;// To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v, ... input metaQ; // To u_poc of mig_7series_v2_3_poc_top.v input ocal_num_samples_inc; // To u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v input oclkdelay_calib_start; // To u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v input [5:0] oclkdelay_init_val; // To u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v, ... input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;// To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v input phy_rddata_en; // To u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v input [8:0] po_counter_read_val; // To u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v, ... input poc_sample_pd; input prbs_ignore_first_byte; // To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v input prbs_ignore_last_bytes; // To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; // To u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v input prech_done; // To u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v, ... input psdone; // To u_poc of mig_7series_v2_3_poc_top.v input rst; // To u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v, ... input [6*DQS_WIDTH-1:0] wl_po_fine_cnt; // To u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output complex_oclkdelay_calib_done;// From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v output complex_wrlvl_final; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v output lim2init_write_request; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v output ocal_num_samples_done_r;// From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v output oclk_calib_resume; // From u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v output oclk_center_write_resume;// From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v output oclk_init_delay_done; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v output oclk_prech_req; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v output oclkdelay_center_calib_done;// From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v output oclkdelay_center_calib_start;// From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v output po_en_stg23; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v output po_en_stg3; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v output po_stg23_incdec; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v output po_stg23_sel; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v output po_stg3_incdec; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v output poc_error; // From u_poc of mig_7series_v2_3_poc_top.v output psen; // From u_poc of mig_7series_v2_3_poc_top.v output psincdec; // From u_poc of mig_7series_v2_3_poc_top.v output [2:0] rd_victim_sel; // From u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v output wrlvl_final; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire ktap_at_left_edge; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v wire ktap_at_right_edge; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v wire lim2init_prech_req; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire [5:0] lim2ocal_stg3_left_lim; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire [5:0] lim2ocal_stg3_right_lim;// From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire lim2poc_ktap_right; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire lim2poc_rdy; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire lim2stg2_dec; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire lim2stg2_inc; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire lim2stg3_dec; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire lim2stg3_inc; // From u_ocd_lim of mig_7series_v2_3_ddr_phy_ocd_lim.v wire lim_start; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v wire [1:0] match; // From u_ocd_data of mig_7series_v2_3_ddr_phy_ocd_data.v wire mmcm_edge_detect_done; // From u_poc of mig_7series_v2_3_poc_top.v wire mmcm_edge_detect_rdy; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v wire mmcm_lbclk_edge_aligned;// From u_poc of mig_7series_v2_3_poc_top.v wire [1:0] ninety_offsets; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd2stg2_dec; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd2stg2_inc; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd2stg3_dec; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd2stg3_inc; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd_cntlr2stg2_dec; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v wire ocd_edge_detect_rdy; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd_ktap_left; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd_ktap_right; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire ocd_prech_req; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v wire phy_rddata_en_1; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v wire phy_rddata_en_2; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v wire phy_rddata_en_3; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v wire po_rdy; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v wire poc_backup; // From u_poc of mig_7series_v2_3_poc_top.v wire reset_scan; // From u_ocd_cntlr of mig_7series_v2_3_ddr_phy_ocd_cntlr.v wire [TAPCNTRWIDTH-1:0] rise_lead_right; // From u_poc of mig_7series_v2_3_poc_top.v wire [TAPCNTRWIDTH-1:0] rise_trail_right; // From u_poc of mig_7series_v2_3_poc_top.v wire samp_done; // From u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v wire [1:0] samp_result; // From u_ocd_samp of mig_7series_v2_3_ddr_phy_ocd_samp.v wire scan_done; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire scan_right; // From u_ocd_edge of mig_7series_v2_3_ddr_phy_ocd_edge.v wire scanning_right; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire [5:0] simp_stg3_final_sel; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire [5:0] stg3; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire taps_set; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire use_noise_window; // From u_ocd_po_cntlr of mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v wire [5:0] wl_po_fine_cnt_sel; // From u_ocd_mux of mig_7series_v2_3_ddr_phy_ocd_mux.v // End of automatics wire [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final; wire ocal_scan_win_not_found; output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; output [255:0] dbg_phy_oclkdelay_cal; output [16*DRAM_WIDTH-1:0] dbg_oclkdelay_rd_data; output oclkdelay_calib_done; output f2o; output f2z; output o2f; output z2f; output [5:0] fuzz2oneeighty; output [5:0] fuzz2zero; output [5:0] oneeighty2fuzz; output [5:0] zero2fuzz; output lim_done; output [255:0] dbg_ocd_lim; // Debug signals assign dbg_phy_oclkdelay_cal[0] = f2o; assign dbg_phy_oclkdelay_cal[1] = f2z; assign dbg_phy_oclkdelay_cal[2] = o2f; assign dbg_phy_oclkdelay_cal[3] = z2f; assign dbg_phy_oclkdelay_cal[4+:6] = fuzz2oneeighty; assign dbg_phy_oclkdelay_cal[10+:6] = fuzz2zero; assign dbg_phy_oclkdelay_cal[16+:6] = oneeighty2fuzz; assign dbg_phy_oclkdelay_cal[22+:6] = zero2fuzz; assign dbg_phy_oclkdelay_cal[28+:3] = oclkdelay_calib_cnt; assign dbg_phy_oclkdelay_cal[31] = oclkdelay_calib_start; assign dbg_phy_oclkdelay_cal[32] = lim_done; assign dbg_phy_oclkdelay_cal[33+:6] =lim2ocal_stg3_left_lim ; assign dbg_phy_oclkdelay_cal[39+:6] = lim2ocal_stg3_right_lim ; assign dbg_phy_oclkdelay_cal[45+:8] = po_counter_read_val[8:0]; assign dbg_phy_oclkdelay_cal[53+:54] = simp_stg3_final[DQS_WIDTH*6-1:0]; assign dbg_phy_oclkdelay_cal[107] = ocal_scan_win_not_found; assign dbg_phy_oclkdelay_cal[108] = oclkdelay_center_calib_start; assign dbg_phy_oclkdelay_cal[109] = oclkdelay_center_calib_done; assign dbg_phy_oclkdelay_cal[115:110] = stg3[5:0]; mig_7series_v2_3_ddr_phy_ocd_lim # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ), .TDQSS_DEGREES (), .BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL)) // Templated u_ocd_lim (/*AUTOINST*/ // Outputs .lim2init_prech_req (lim2init_prech_req), .lim2init_write_request (lim2init_write_request), .lim2ocal_stg3_left_lim (lim2ocal_stg3_left_lim[5:0]), .lim2ocal_stg3_right_lim (lim2ocal_stg3_right_lim[5:0]), .lim2poc_ktap_right (lim2poc_ktap_right), .lim2poc_rdy (lim2poc_rdy), .lim2stg2_dec (lim2stg2_dec), .lim2stg2_inc (lim2stg2_inc), .lim2stg3_dec (lim2stg3_dec), .lim2stg3_inc (lim2stg3_inc), .lim_done (lim_done), // Inputs .clk (clk), .lim_start (lim_start), .oclkdelay_calib_done (oclkdelay_calib_done), .oclkdelay_init_val (oclkdelay_init_val[5:0]), .po_rdy (po_rdy), .poc2lim_detect_done (mmcm_edge_detect_done), // Templated .poc2lim_fall_align_taps_lead ({TAPCNTRWIDTH{1'b0}}), // Templated .poc2lim_fall_align_taps_trail ({TAPCNTRWIDTH{1'b0}}), // Templated .poc2lim_rise_align_taps_lead (rise_lead_right), // Templated .poc2lim_rise_align_taps_trail (rise_trail_right), // Templated .prech_done (prech_done), .rst (rst), .simp_stg3_final_sel (simp_stg3_final_sel[5:0]), .wl_po_fine_cnt (wl_po_fine_cnt_sel[5:0]), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .dbg_ocd_lim (dbg_ocd_lim)); // Templated /*mig_7series_v2_3_poc_top AUTO_TEMPLATE( .CCENABLE (0), .SCANFROMRIGHT (1), .pd_out (metaQ),); */ mig_7series_v2_3_poc_top # (/*AUTOINSTPARAM*/ // Parameters .CCENABLE (0), // Templated .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), .PCT_SAMPS_SOLID (PCT_SAMPS_SOLID), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .SAMPLES (SAMPLES), .SCANFROMRIGHT (1), // Templated .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ)) u_poc (/*AUTOINST*/ // Outputs .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .poc_backup (poc_backup), .poc_error (poc_error), .psen (psen), .psincdec (psincdec), .rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]), .rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]), // Inputs .clk (clk), .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), .ninety_offsets (ninety_offsets[1:0]), .pd_out (metaQ), // Templated .poc_sample_pd (poc_sample_pd), .psdone (psdone), .rst (rst), .use_noise_window (use_noise_window)); mig_7series_v2_3_ddr_phy_ocd_mux # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .TCQ (TCQ)) u_ocd_mux (/*AUTOINST*/ // Outputs .ktap_at_left_edge (ktap_at_left_edge), .ktap_at_right_edge (ktap_at_right_edge), .mmcm_edge_detect_rdy (mmcm_edge_detect_rdy), .oclk_prech_req (oclk_prech_req), .po_en_stg23 (po_en_stg23), .po_en_stg3 (po_en_stg3), .po_rdy (po_rdy), .po_stg23_incdec (po_stg23_incdec), .po_stg23_sel (po_stg23_sel), .po_stg3_incdec (po_stg3_incdec), .wl_po_fine_cnt_sel (wl_po_fine_cnt_sel[5:0]), // Inputs .clk (clk), .lim2init_prech_req (lim2init_prech_req), .lim2poc_ktap_right (lim2poc_ktap_right), .lim2poc_rdy (lim2poc_rdy), .lim2stg2_dec (lim2stg2_dec), .lim2stg2_inc (lim2stg2_inc), .lim2stg3_dec (lim2stg3_dec), .lim2stg3_inc (lim2stg3_inc), .ocd2stg2_dec (ocd2stg2_dec), .ocd2stg2_inc (ocd2stg2_inc), .ocd2stg3_dec (ocd2stg3_dec), .ocd2stg3_inc (ocd2stg3_inc), .ocd_cntlr2stg2_dec (ocd_cntlr2stg2_dec), .ocd_edge_detect_rdy (ocd_edge_detect_rdy), .ocd_ktap_left (ocd_ktap_left), .ocd_ktap_right (ocd_ktap_right), .ocd_prech_req (ocd_prech_req), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .rst (rst), .wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0])); mig_7series_v2_3_ddr_phy_ocd_data # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQ_WIDTH (DQ_WIDTH), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK)) u_ocd_data (/*AUTOINST*/ // Outputs .match (match[1:0]), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]), .phy_rddata_en_1 (phy_rddata_en_1), .prbs_ignore_first_byte (prbs_ignore_first_byte), .prbs_ignore_last_bytes (prbs_ignore_last_bytes), .prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]), .rst (rst)); mig_7series_v2_3_ddr_phy_ocd_samp # (/*AUTOINSTPARAM*/ // Parameters .OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS), .SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID), .SIM_CAL_OPTION (SIM_CAL_OPTION), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK)) u_ocd_samp (/*AUTOINST*/ // Outputs .oclk_calib_resume (oclk_calib_resume), .rd_victim_sel (rd_victim_sel[2:0]), .samp_done (samp_done), .samp_result (samp_result[1:0]), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .match (match[1:0]), .ocal_num_samples_inc (ocal_num_samples_inc), .phy_rddata_en_1 (phy_rddata_en_1), .reset_scan (reset_scan), .rst (rst), .taps_set (taps_set)); mig_7series_v2_3_ddr_phy_ocd_edge # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ)) u_ocd_edge (/*AUTOINST*/ // Outputs .f2o (f2o), .f2z (f2z), .fuzz2oneeighty (fuzz2oneeighty[5:0]), .fuzz2zero (fuzz2zero[5:0]), .o2f (o2f), .oneeighty2fuzz (oneeighty2fuzz[5:0]), .scan_right (scan_right), .z2f (z2f), .zero2fuzz (zero2fuzz[5:0]), // Inputs .clk (clk), .phy_rddata_en_2 (phy_rddata_en_2), .reset_scan (reset_scan), .samp_done (samp_done), .samp_result (samp_result[1:0]), .scanning_right (scanning_right), .stg3 (stg3[5:0])); mig_7series_v2_3_ddr_phy_ocd_cntlr # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .TCQ (TCQ)) u_ocd_cntlr (/*AUTOINST*/ // Outputs .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done), .complex_wrlvl_final (complex_wrlvl_final), .lim_start (lim_start), .ocd_cntlr2stg2_dec (ocd_cntlr2stg2_dec), .ocd_prech_req (ocd_prech_req), .oclk_init_delay_done (oclk_init_delay_done), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .oclkdelay_calib_done (oclkdelay_calib_done), .phy_rddata_en_1 (phy_rddata_en_1), .phy_rddata_en_2 (phy_rddata_en_2), .phy_rddata_en_3 (phy_rddata_en_3), .reset_scan (reset_scan), .wrlvl_final (wrlvl_final), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .lim_done (lim_done), .oclkdelay_calib_start (oclkdelay_calib_start), .phy_rddata_en (phy_rddata_en), .po_counter_read_val (po_counter_read_val[8:0]), .po_rdy (po_rdy), .prech_done (prech_done), .rst (rst), .scan_done (scan_done)); mig_7series_v2_3_ddr_phy_ocd_po_cntlr # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK)) u_ocd_po_cntlr (.cmplx_stg3_final (cmplx_stg3_final[DQS_WIDTH*6-1:0]), .ocal_scan_win_not_found (ocal_scan_win_not_found), .simp_stg3_final (simp_stg3_final[DQS_WIDTH*6-1:0]), /*AUTOINST*/ // Outputs .ninety_offsets (ninety_offsets[1:0]), .ocal_num_samples_done_r (ocal_num_samples_done_r), .ocd2stg2_dec (ocd2stg2_dec), .ocd2stg2_inc (ocd2stg2_inc), .ocd2stg3_dec (ocd2stg3_dec), .ocd2stg3_inc (ocd2stg3_inc), .ocd_edge_detect_rdy (ocd_edge_detect_rdy), .ocd_ktap_left (ocd_ktap_left), .ocd_ktap_right (ocd_ktap_right), .oclk_center_write_resume (oclk_center_write_resume), .oclkdelay_center_calib_done (oclkdelay_center_calib_done), .oclkdelay_center_calib_start (oclkdelay_center_calib_start), .scan_done (scan_done), .scanning_right (scanning_right), .simp_stg3_final_sel (simp_stg3_final_sel[5:0]), .stg3 (stg3[5:0]), .taps_set (taps_set), .use_noise_window (use_noise_window), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .f2o (f2o), .f2z (f2z), .fuzz2oneeighty (fuzz2oneeighty[5:0]), .fuzz2zero (fuzz2zero[5:0]), .lim2ocal_stg3_left_lim (lim2ocal_stg3_left_lim[5:0]), .lim2ocal_stg3_right_lim (lim2ocal_stg3_right_lim[5:0]), .mmcm_edge_detect_done (mmcm_edge_detect_done), .mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned), .o2f (o2f), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .oclkdelay_init_val (oclkdelay_init_val[5:0]), .oneeighty2fuzz (oneeighty2fuzz[5:0]), .phy_rddata_en_3 (phy_rddata_en_3), .po_counter_read_val (po_counter_read_val[8:0]), .po_rdy (po_rdy), .poc_backup (poc_backup), .reset_scan (reset_scan), .rst (rst), .samp_done (samp_done), .scan_right (scan_right), .wl_po_fine_cnt_sel (wl_po_fine_cnt_sel[5:0]), .z2f (z2f), .zero2fuzz (zero2fuzz[5:0])); endmodule // mig_7series_v2_3_ddr_phy_oclkdelay_cal // Local Variables: // verilog-library-directories:(".") // verilog-library-extensions:(".v") // End:

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_v2_3_phy_ocd_mux.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: The limit block and the _po_cntlr block both manipulate // the phaser out and the POC. This block muxes those commands // together, and encapsulates logic required for meeting phaser // setup and wait times. // //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_ocd_mux # (parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 8, parameter TCQ = 100) (/*AUTOARG*/ // Outputs ktap_at_left_edge, ktap_at_right_edge, mmcm_edge_detect_rdy, po_stg3_incdec, po_en_stg3, po_en_stg23, po_stg23_sel, po_stg23_incdec, po_rdy, wl_po_fine_cnt_sel, oclk_prech_req, // Inputs clk, rst, ocd_ktap_right, ocd_ktap_left, lim2poc_ktap_right, lim2poc_rdy, ocd_edge_detect_rdy, lim2stg2_inc, lim2stg2_dec, lim2stg3_inc, lim2stg3_dec, ocd2stg2_inc, ocd2stg2_dec, ocd_cntlr2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, wl_po_fine_cnt, oclkdelay_calib_cnt, lim2init_prech_req, ocd_prech_req ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam PO_WAIT = 15; localparam POW_WIDTH = clogb2(PO_WAIT); localparam ONE = 1; localparam TWO = 2; input clk; input rst; input ocd_ktap_right, ocd_ktap_left; input lim2poc_ktap_right; output ktap_at_left_edge, ktap_at_right_edge; assign ktap_at_left_edge = ocd_ktap_left; assign ktap_at_right_edge = lim2poc_ktap_right || ocd_ktap_right; input lim2poc_rdy; input ocd_edge_detect_rdy; output mmcm_edge_detect_rdy; assign mmcm_edge_detect_rdy = lim2poc_rdy || ocd_edge_detect_rdy; // po_stg3_incdec and po_en_stg3 are deprecated and should be removed. output po_stg3_incdec; output po_en_stg3; assign po_stg3_incdec = 1'b0; assign po_en_stg3 = 1'b0; reg [1:0] po_setup_ns, po_setup_r; always @(posedge clk) po_setup_r <= #TCQ po_setup_ns; input lim2stg2_inc; input lim2stg2_dec; input lim2stg3_inc; input lim2stg3_dec; input ocd2stg2_inc; input ocd2stg2_dec; input ocd_cntlr2stg2_dec; input ocd2stg3_inc; input ocd2stg3_dec; wire setup_po = lim2stg2_inc || lim2stg2_dec || lim2stg3_inc || lim2stg3_dec || ocd2stg2_inc || ocd2stg2_dec || ocd2stg3_inc || ocd2stg3_dec || ocd_cntlr2stg2_dec; always @(*) begin po_setup_ns = po_setup_r; if (rst) po_setup_ns = 2'b00; else if (setup_po) po_setup_ns = 2'b11; else if (|po_setup_r) po_setup_ns = po_setup_r - 2'b01; end reg po_en_stg23_r; wire po_en_stg23_ns = ~rst && po_setup_r == 2'b01; always @(posedge clk) po_en_stg23_r <= #TCQ po_en_stg23_ns; output po_en_stg23; assign po_en_stg23 = po_en_stg23_r; wire sel_stg3 = lim2stg3_inc || lim2stg3_dec || ocd2stg3_inc || ocd2stg3_dec; reg [POW_WIDTH-1:0] po_wait_r, po_wait_ns; reg po_stg23_sel_r; // Reset to zero at the end. Makes adjust stg2 at end of centering // get the correct value of po_counter_read_val. wire po_stg23_sel_ns = ~rst && (setup_po ? sel_stg3 ? 1'b1 : 1'b0 : po_stg23_sel_r && !(po_wait_r == ONE[POW_WIDTH-1:0])); always @(posedge clk) po_stg23_sel_r <= #TCQ po_stg23_sel_ns; output po_stg23_sel; assign po_stg23_sel = po_stg23_sel_r; wire po_inc = lim2stg2_inc || lim2stg3_inc || ocd2stg2_inc || ocd2stg3_inc; reg po_stg23_incdec_r; wire po_stg23_incdec_ns = ~rst && (setup_po ? po_inc ? 1'b1 : 1'b0 : po_stg23_incdec_r); always @(posedge clk) po_stg23_incdec_r <= #TCQ po_stg23_incdec_ns; output po_stg23_incdec; assign po_stg23_incdec = po_stg23_incdec_r; always @(posedge clk) po_wait_r <= #TCQ po_wait_ns; always @(*) begin po_wait_ns = po_wait_r; if (rst) po_wait_ns = {POW_WIDTH{1'b0}}; else if (po_en_stg23_r) po_wait_ns = PO_WAIT[POW_WIDTH-1:0] - ONE[POW_WIDTH-1:0]; else if (po_wait_r != {POW_WIDTH{1'b0}}) po_wait_ns = po_wait_r - ONE[POW_WIDTH-1:0]; end wire po_rdy_ns = ~(setup_po || |po_setup_r || |po_wait_ns); reg po_rdy_r; always @(posedge clk) po_rdy_r <= #TCQ po_rdy_ns; output po_rdy; assign po_rdy = po_rdy_r; input [6*DQS_WIDTH-1:0] wl_po_fine_cnt; input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; wire [6*DQS_WIDTH-1:0] wl_po_fine_shifted = wl_po_fine_cnt >> oclkdelay_calib_cnt*6; output [5:0] wl_po_fine_cnt_sel; assign wl_po_fine_cnt_sel = wl_po_fine_shifted[5:0]; input lim2init_prech_req; input ocd_prech_req; output oclk_prech_req; assign oclk_prech_req = ocd_prech_req || lim2init_prech_req; endmodule // mig_7series_v2_3_ddr_phy_ocd_mux

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_v2_3_phy_ocd_mux.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: The limit block and the _po_cntlr block both manipulate // the phaser out and the POC. This block muxes those commands // together, and encapsulates logic required for meeting phaser // setup and wait times. // //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_ocd_mux # (parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 8, parameter TCQ = 100) (/*AUTOARG*/ // Outputs ktap_at_left_edge, ktap_at_right_edge, mmcm_edge_detect_rdy, po_stg3_incdec, po_en_stg3, po_en_stg23, po_stg23_sel, po_stg23_incdec, po_rdy, wl_po_fine_cnt_sel, oclk_prech_req, // Inputs clk, rst, ocd_ktap_right, ocd_ktap_left, lim2poc_ktap_right, lim2poc_rdy, ocd_edge_detect_rdy, lim2stg2_inc, lim2stg2_dec, lim2stg3_inc, lim2stg3_dec, ocd2stg2_inc, ocd2stg2_dec, ocd_cntlr2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, wl_po_fine_cnt, oclkdelay_calib_cnt, lim2init_prech_req, ocd_prech_req ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam PO_WAIT = 15; localparam POW_WIDTH = clogb2(PO_WAIT); localparam ONE = 1; localparam TWO = 2; input clk; input rst; input ocd_ktap_right, ocd_ktap_left; input lim2poc_ktap_right; output ktap_at_left_edge, ktap_at_right_edge; assign ktap_at_left_edge = ocd_ktap_left; assign ktap_at_right_edge = lim2poc_ktap_right || ocd_ktap_right; input lim2poc_rdy; input ocd_edge_detect_rdy; output mmcm_edge_detect_rdy; assign mmcm_edge_detect_rdy = lim2poc_rdy || ocd_edge_detect_rdy; // po_stg3_incdec and po_en_stg3 are deprecated and should be removed. output po_stg3_incdec; output po_en_stg3; assign po_stg3_incdec = 1'b0; assign po_en_stg3 = 1'b0; reg [1:0] po_setup_ns, po_setup_r; always @(posedge clk) po_setup_r <= #TCQ po_setup_ns; input lim2stg2_inc; input lim2stg2_dec; input lim2stg3_inc; input lim2stg3_dec; input ocd2stg2_inc; input ocd2stg2_dec; input ocd_cntlr2stg2_dec; input ocd2stg3_inc; input ocd2stg3_dec; wire setup_po = lim2stg2_inc || lim2stg2_dec || lim2stg3_inc || lim2stg3_dec || ocd2stg2_inc || ocd2stg2_dec || ocd2stg3_inc || ocd2stg3_dec || ocd_cntlr2stg2_dec; always @(*) begin po_setup_ns = po_setup_r; if (rst) po_setup_ns = 2'b00; else if (setup_po) po_setup_ns = 2'b11; else if (|po_setup_r) po_setup_ns = po_setup_r - 2'b01; end reg po_en_stg23_r; wire po_en_stg23_ns = ~rst && po_setup_r == 2'b01; always @(posedge clk) po_en_stg23_r <= #TCQ po_en_stg23_ns; output po_en_stg23; assign po_en_stg23 = po_en_stg23_r; wire sel_stg3 = lim2stg3_inc || lim2stg3_dec || ocd2stg3_inc || ocd2stg3_dec; reg [POW_WIDTH-1:0] po_wait_r, po_wait_ns; reg po_stg23_sel_r; // Reset to zero at the end. Makes adjust stg2 at end of centering // get the correct value of po_counter_read_val. wire po_stg23_sel_ns = ~rst && (setup_po ? sel_stg3 ? 1'b1 : 1'b0 : po_stg23_sel_r && !(po_wait_r == ONE[POW_WIDTH-1:0])); always @(posedge clk) po_stg23_sel_r <= #TCQ po_stg23_sel_ns; output po_stg23_sel; assign po_stg23_sel = po_stg23_sel_r; wire po_inc = lim2stg2_inc || lim2stg3_inc || ocd2stg2_inc || ocd2stg3_inc; reg po_stg23_incdec_r; wire po_stg23_incdec_ns = ~rst && (setup_po ? po_inc ? 1'b1 : 1'b0 : po_stg23_incdec_r); always @(posedge clk) po_stg23_incdec_r <= #TCQ po_stg23_incdec_ns; output po_stg23_incdec; assign po_stg23_incdec = po_stg23_incdec_r; always @(posedge clk) po_wait_r <= #TCQ po_wait_ns; always @(*) begin po_wait_ns = po_wait_r; if (rst) po_wait_ns = {POW_WIDTH{1'b0}}; else if (po_en_stg23_r) po_wait_ns = PO_WAIT[POW_WIDTH-1:0] - ONE[POW_WIDTH-1:0]; else if (po_wait_r != {POW_WIDTH{1'b0}}) po_wait_ns = po_wait_r - ONE[POW_WIDTH-1:0]; end wire po_rdy_ns = ~(setup_po || |po_setup_r || |po_wait_ns); reg po_rdy_r; always @(posedge clk) po_rdy_r <= #TCQ po_rdy_ns; output po_rdy; assign po_rdy = po_rdy_r; input [6*DQS_WIDTH-1:0] wl_po_fine_cnt; input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; wire [6*DQS_WIDTH-1:0] wl_po_fine_shifted = wl_po_fine_cnt >> oclkdelay_calib_cnt*6; output [5:0] wl_po_fine_cnt_sel; assign wl_po_fine_cnt_sel = wl_po_fine_shifted[5:0]; input lim2init_prech_req; input ocd_prech_req; output oclk_prech_req; assign oclk_prech_req = ocd_prech_req || lim2init_prech_req; endmodule // mig_7series_v2_3_ddr_phy_ocd_mux

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_v2_3_phy_ocd_mux.v // /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: The limit block and the _po_cntlr block both manipulate // the phaser out and the POC. This block muxes those commands // together, and encapsulates logic required for meeting phaser // setup and wait times. // //Reference: //Revision History: //***************************************************************************** `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_ocd_mux # (parameter DQS_CNT_WIDTH = 3, parameter DQS_WIDTH = 8, parameter TCQ = 100) (/*AUTOARG*/ // Outputs ktap_at_left_edge, ktap_at_right_edge, mmcm_edge_detect_rdy, po_stg3_incdec, po_en_stg3, po_en_stg23, po_stg23_sel, po_stg23_incdec, po_rdy, wl_po_fine_cnt_sel, oclk_prech_req, // Inputs clk, rst, ocd_ktap_right, ocd_ktap_left, lim2poc_ktap_right, lim2poc_rdy, ocd_edge_detect_rdy, lim2stg2_inc, lim2stg2_dec, lim2stg3_inc, lim2stg3_dec, ocd2stg2_inc, ocd2stg2_dec, ocd_cntlr2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, wl_po_fine_cnt, oclkdelay_calib_cnt, lim2init_prech_req, ocd_prech_req ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam PO_WAIT = 15; localparam POW_WIDTH = clogb2(PO_WAIT); localparam ONE = 1; localparam TWO = 2; input clk; input rst; input ocd_ktap_right, ocd_ktap_left; input lim2poc_ktap_right; output ktap_at_left_edge, ktap_at_right_edge; assign ktap_at_left_edge = ocd_ktap_left; assign ktap_at_right_edge = lim2poc_ktap_right || ocd_ktap_right; input lim2poc_rdy; input ocd_edge_detect_rdy; output mmcm_edge_detect_rdy; assign mmcm_edge_detect_rdy = lim2poc_rdy || ocd_edge_detect_rdy; // po_stg3_incdec and po_en_stg3 are deprecated and should be removed. output po_stg3_incdec; output po_en_stg3; assign po_stg3_incdec = 1'b0; assign po_en_stg3 = 1'b0; reg [1:0] po_setup_ns, po_setup_r; always @(posedge clk) po_setup_r <= #TCQ po_setup_ns; input lim2stg2_inc; input lim2stg2_dec; input lim2stg3_inc; input lim2stg3_dec; input ocd2stg2_inc; input ocd2stg2_dec; input ocd_cntlr2stg2_dec; input ocd2stg3_inc; input ocd2stg3_dec; wire setup_po = lim2stg2_inc || lim2stg2_dec || lim2stg3_inc || lim2stg3_dec || ocd2stg2_inc || ocd2stg2_dec || ocd2stg3_inc || ocd2stg3_dec || ocd_cntlr2stg2_dec; always @(*) begin po_setup_ns = po_setup_r; if (rst) po_setup_ns = 2'b00; else if (setup_po) po_setup_ns = 2'b11; else if (|po_setup_r) po_setup_ns = po_setup_r - 2'b01; end reg po_en_stg23_r; wire po_en_stg23_ns = ~rst && po_setup_r == 2'b01; always @(posedge clk) po_en_stg23_r <= #TCQ po_en_stg23_ns; output po_en_stg23; assign po_en_stg23 = po_en_stg23_r; wire sel_stg3 = lim2stg3_inc || lim2stg3_dec || ocd2stg3_inc || ocd2stg3_dec; reg [POW_WIDTH-1:0] po_wait_r, po_wait_ns; reg po_stg23_sel_r; // Reset to zero at the end. Makes adjust stg2 at end of centering // get the correct value of po_counter_read_val. wire po_stg23_sel_ns = ~rst && (setup_po ? sel_stg3 ? 1'b1 : 1'b0 : po_stg23_sel_r && !(po_wait_r == ONE[POW_WIDTH-1:0])); always @(posedge clk) po_stg23_sel_r <= #TCQ po_stg23_sel_ns; output po_stg23_sel; assign po_stg23_sel = po_stg23_sel_r; wire po_inc = lim2stg2_inc || lim2stg3_inc || ocd2stg2_inc || ocd2stg3_inc; reg po_stg23_incdec_r; wire po_stg23_incdec_ns = ~rst && (setup_po ? po_inc ? 1'b1 : 1'b0 : po_stg23_incdec_r); always @(posedge clk) po_stg23_incdec_r <= #TCQ po_stg23_incdec_ns; output po_stg23_incdec; assign po_stg23_incdec = po_stg23_incdec_r; always @(posedge clk) po_wait_r <= #TCQ po_wait_ns; always @(*) begin po_wait_ns = po_wait_r; if (rst) po_wait_ns = {POW_WIDTH{1'b0}}; else if (po_en_stg23_r) po_wait_ns = PO_WAIT[POW_WIDTH-1:0] - ONE[POW_WIDTH-1:0]; else if (po_wait_r != {POW_WIDTH{1'b0}}) po_wait_ns = po_wait_r - ONE[POW_WIDTH-1:0]; end wire po_rdy_ns = ~(setup_po || |po_setup_r || |po_wait_ns); reg po_rdy_r; always @(posedge clk) po_rdy_r <= #TCQ po_rdy_ns; output po_rdy; assign po_rdy = po_rdy_r; input [6*DQS_WIDTH-1:0] wl_po_fine_cnt; input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; wire [6*DQS_WIDTH-1:0] wl_po_fine_shifted = wl_po_fine_cnt >> oclkdelay_calib_cnt*6; output [5:0] wl_po_fine_cnt_sel; assign wl_po_fine_cnt_sel = wl_po_fine_shifted[5:0]; input lim2init_prech_req; input ocd_prech_req; output oclk_prech_req; assign oclk_prech_req = ocd_prech_req || lim2init_prech_req; endmodule // mig_7series_v2_3_ddr_phy_ocd_mux

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ui_rd_data.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // User interface read buffer. Re orders read data returned from the // memory controller back to the request order. // // Consists of a large buffer for the data, a status RAM and two counters. // // The large buffer is implemented with distributed RAM in 6 bit wide, // 1 read, 1 write mode. The status RAM is implemented with a distributed // RAM configured as 2 bits wide 1 read/write, 1 read mode. // // As read requests are received from the application, the data_buf_addr // counter supplies the data_buf_addr sent into the memory controller. // With each read request, the counter is incremented, eventually rolling // over. This mechanism labels each read request with an incrementing number. // // When the memory controller returns read data, it echos the original // data_buf_addr with the read data. // // The status RAM is indexed with the same address as the data buffer // RAM. Each word of the data buffer RAM has an associated status bit // and "end" bit. Requests of size 1 return a data burst on two consecutive // states. Requests of size zero return with a single assertion of rd_data_en. // // Upon returning data, the status and end bits are updated for each // corresponding location in the status RAM indexed by the data_buf_addr // echoed on the rd_data_addr field. // // The other side of the status and data RAMs is indexed by the rd_buf_indx. // The rd_buf_indx constantly monitors the status bit it is currently // pointing to. When the status becomes set to the proper state (more on // this later) read data is returned to the application, and the rd_buf_indx // is incremented. // // At rst the rd_buf_indx is initialized to zero. Data will not have been // returned from the memory controller yet, so there is nothing to return // to the application. Evenutally, read requests will be made, and the // memory controller will return the corresponding data. The memory // controller may not return this data in the request order. In which // case, the status bit at location zero, will not indicate // the data for request zero is ready. Eventually, the memory controller // will return data for request zero. The data is forwarded on to the // application, and rd_buf_indx is incremented to point to the next status // bits and data in the buffers. The status bit will be examined, and if // data is valid, this data will be returned as well. This process // continues until the status bit indexed by rd_buf_indx indicates data // is not ready. This may be because the rd_data_buf // is empty, or that some data was returned out of order. Since rd_buf_indx // always increments sequentially, data is always returned to the application // in request order. // // Some further discussion of the status bit is in order. The rd_data_buf // is a circular buffer. The status bit is a single bit. Distributed RAM // supports only a single write port. The write port is consumed by // memory controller read data updates. If a simple '1' were used to // indicate the status, when rd_data_indx rolled over it would immediately // encounter a one for a request that may not be ready. // // This problem is solved by causing read data returns to flip the // status bit, and adding hi order bit beyond the size required to // index the rd_data_buf. Data is considered ready when the status bit // and this hi order bit are equal. // // The status RAM needs to be initialized to zero after reset. This is // accomplished by cycling through all rd_buf_indx valus and writing a // zero to the status bits directly following deassertion of reset. This // mechanism is used for similar purposes // for the wr_data_buf. // // When ORDERING == "STRICT", read data reordering is unnecessary. For thi // case, most of the logic in the block is not generated. `timescale 1 ps / 1 ps // User interface read data. module mig_7series_v2_3_ui_rd_data # ( parameter TCQ = 100, parameter APP_DATA_WIDTH = 256, parameter DATA_BUF_ADDR_WIDTH = 5, parameter ECC = "OFF", parameter nCK_PER_CLK = 2 , parameter ORDERING = "NORM" ) (/*AUTOARG*/ // Outputs ram_init_done_r, ram_init_addr, app_rd_data_valid, app_rd_data_end, app_rd_data, app_ecc_multiple_err, rd_buf_full, rd_data_buf_addr_r, // Inputs rst, clk, rd_data_en, rd_data_addr, rd_data_offset, rd_data_end, rd_data, ecc_multiple, rd_accepted ); input rst; input clk; output wire ram_init_done_r; output wire [3:0] ram_init_addr; // rd_buf_indx points to the status and data storage rams for // reading data out to the app. reg [5:0] rd_buf_indx_r; reg ram_init_done_r_lcl /* synthesis syn_maxfan = 10 */; assign ram_init_done_r = ram_init_done_r_lcl; wire app_rd_data_valid_ns; wire single_data; reg [5:0] rd_buf_indx_ns; generate begin : rd_buf_indx wire upd_rd_buf_indx = ~ram_init_done_r_lcl || app_rd_data_valid_ns; // Loop through all status write addresses once after rst. Initializes // the status and pointer RAMs. wire ram_init_done_ns = ~rst && (ram_init_done_r_lcl || (rd_buf_indx_r[4:0] == 5'h1f)); always @(posedge clk) ram_init_done_r_lcl <= #TCQ ram_init_done_ns; always @(/*AS*/rd_buf_indx_r or rst or single_data or upd_rd_buf_indx) begin rd_buf_indx_ns = rd_buf_indx_r; if (rst) rd_buf_indx_ns = 6'b0; else if (upd_rd_buf_indx) rd_buf_indx_ns = // need to use every slot of RAMB32 if all address bits are used rd_buf_indx_r + 6'h1 + (DATA_BUF_ADDR_WIDTH == 5 ? 0 : single_data); end always @(posedge clk) rd_buf_indx_r <= #TCQ rd_buf_indx_ns; end endgenerate assign ram_init_addr = rd_buf_indx_r[3:0]; input rd_data_en; input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; input rd_data_offset; input rd_data_end; input [APP_DATA_WIDTH-1:0] rd_data; output reg app_rd_data_valid /* synthesis syn_maxfan = 10 */; output reg app_rd_data_end; output reg [APP_DATA_WIDTH-1:0] app_rd_data; input [3:0] ecc_multiple; reg [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_r = 'b0; output wire [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; assign app_ecc_multiple_err = app_ecc_multiple_err_r; input rd_accepted; output wire rd_buf_full; output wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r; // Compute dimensions of read data buffer. Depending on width of // DQ bus and DRAM CK // to fabric ratio, number of RAM32Ms is variable. RAM32Ms are used in // single write, single read, 6 bit wide mode. localparam RD_BUF_WIDTH = APP_DATA_WIDTH + (ECC == "OFF" ? 0 : 2*nCK_PER_CLK); localparam FULL_RAM_CNT = (RD_BUF_WIDTH/6); localparam REMAINDER = RD_BUF_WIDTH % 6; localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); localparam RAM_WIDTH = (RAM_CNT*6); generate if (ORDERING == "STRICT") begin : strict_mode assign app_rd_data_valid_ns = 1'b0; assign single_data = 1'b0; assign rd_buf_full = 1'b0; reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl; wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns = rst ? 0 : rd_data_buf_addr_r_lcl + rd_accepted; always @(posedge clk) rd_data_buf_addr_r_lcl <= #TCQ rd_data_buf_addr_ns; assign rd_data_buf_addr_r = rd_data_buf_addr_ns; // app_* signals required to be registered. if (ECC == "OFF") begin : ecc_off always @(/*AS*/rd_data) app_rd_data = rd_data; always @(/*AS*/rd_data_en) app_rd_data_valid = rd_data_en; always @(/*AS*/rd_data_end) app_rd_data_end = rd_data_end; end else begin : ecc_on always @(posedge clk) app_rd_data <= #TCQ rd_data; always @(posedge clk) app_rd_data_valid <= #TCQ rd_data_en; always @(posedge clk) app_rd_data_end <= #TCQ rd_data_end; always @(posedge clk) app_ecc_multiple_err_r <= #TCQ ecc_multiple; end end else begin : not_strict_mode wire rd_buf_we = ~ram_init_done_r_lcl || rd_data_en /* synthesis syn_maxfan = 10 */; // In configurations where read data is returned in a single fabric cycle // the offset is always zero and we can use the bit to get a deeper // FIFO. The RAMB32 has 5 address bits, so when the DATA_BUF_ADDR_WIDTH // is set to use them all, discard the offset. Otherwise, include the // offset. wire [4:0] rd_buf_wr_addr = DATA_BUF_ADDR_WIDTH == 5 ? rd_data_addr : {rd_data_addr, rd_data_offset}; wire [1:0] rd_status; // Instantiate status RAM. One bit for status and one for "end". begin : status_ram // Turns out read to write back status is a timing path. Update // the status in the ram on the state following the read. Bypass // the write data into the status read path. wire [4:0] status_ram_wr_addr_ns = ram_init_done_r_lcl ? rd_buf_wr_addr : rd_buf_indx_r[4:0]; reg [4:0] status_ram_wr_addr_r; always @(posedge clk) status_ram_wr_addr_r <= #TCQ status_ram_wr_addr_ns; wire [1:0] wr_status; // Not guaranteed to write second status bit. If it is written, always // copy in the first status bit. reg wr_status_r1; always @(posedge clk) wr_status_r1 <= #TCQ wr_status[0]; wire [1:0] status_ram_wr_data_ns = ram_init_done_r_lcl ? {rd_data_end, ~(rd_data_offset ? wr_status_r1 : wr_status[0])} : 2'b0; reg [1:0] status_ram_wr_data_r; always @(posedge clk) status_ram_wr_data_r <= #TCQ status_ram_wr_data_ns; reg rd_buf_we_r1; always @(posedge clk) rd_buf_we_r1 <= #TCQ rd_buf_we; RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(rd_status), .DOB(), .DOC(wr_status), .DOD(), .DIA(status_ram_wr_data_r), .DIB(2'b0), .DIC(status_ram_wr_data_r), .DID(status_ram_wr_data_r), .ADDRA(rd_buf_indx_r[4:0]), .ADDRB(5'b0), .ADDRC(status_ram_wr_addr_ns), .ADDRD(status_ram_wr_addr_r), .WE(rd_buf_we_r1), .WCLK(clk) ); end // block: status_ram wire [RAM_WIDTH-1:0] rd_buf_out_data; begin : rd_buf wire [RAM_WIDTH-1:0] rd_buf_in_data; if (REMAINDER == 0) if (ECC == "OFF") assign rd_buf_in_data = rd_data; else assign rd_buf_in_data = {ecc_multiple, rd_data}; else if (ECC == "OFF") assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, rd_data}; else assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, ecc_multiple, rd_data}; // Dedicated copy for driving distributed RAM. (* keep = "true" *) reg [4:0] rd_buf_indx_copy_r /* synthesis syn_keep = 1 */; always @(posedge clk) rd_buf_indx_copy_r <= #TCQ rd_buf_indx_ns[4:0]; genvar i; for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(rd_buf_out_data[((i*6)+4)+:2]), .DOB(rd_buf_out_data[((i*6)+2)+:2]), .DOC(rd_buf_out_data[((i*6)+0)+:2]), .DOD(), .DIA(rd_buf_in_data[((i*6)+4)+:2]), .DIB(rd_buf_in_data[((i*6)+2)+:2]), .DIC(rd_buf_in_data[((i*6)+0)+:2]), .DID(2'b0), .ADDRA(rd_buf_indx_copy_r[4:0]), .ADDRB(rd_buf_indx_copy_r[4:0]), .ADDRC(rd_buf_indx_copy_r[4:0]), .ADDRD(rd_buf_wr_addr), .WE(rd_buf_we), .WCLK(clk) ); end // block: rd_buffer_ram end wire rd_data_rdy = (rd_status[0] == rd_buf_indx_r[5]); wire bypass = rd_data_en && (rd_buf_wr_addr[4:0] == rd_buf_indx_r[4:0]) /* synthesis syn_maxfan = 10 */; assign app_rd_data_valid_ns = ram_init_done_r_lcl && (bypass || rd_data_rdy); wire app_rd_data_end_ns = bypass ? rd_data_end : rd_status[1]; always @(posedge clk) app_rd_data_valid <= #TCQ app_rd_data_valid_ns; always @(posedge clk) app_rd_data_end <= #TCQ app_rd_data_end_ns; assign single_data = app_rd_data_valid_ns && app_rd_data_end_ns && ~rd_buf_indx_r[0]; wire [APP_DATA_WIDTH-1:0] app_rd_data_ns = bypass ? rd_data : rd_buf_out_data[APP_DATA_WIDTH-1:0]; always @(posedge clk) app_rd_data <= #TCQ app_rd_data_ns; if (ECC != "OFF") begin : assign_app_ecc_multiple wire [3:0] app_ecc_multiple_err_ns = bypass ? ecc_multiple : rd_buf_out_data[APP_DATA_WIDTH+:4]; always @(posedge clk) app_ecc_multiple_err_r <= #TCQ app_ecc_multiple_err_ns; end //Added to fix timing. The signal app_rd_data_valid has //a very high fanout. So making a dedicated copy for usage //with the occ_cnt counter. (* equivalent_register_removal = "no" *) reg app_rd_data_valid_copy; always @(posedge clk) app_rd_data_valid_copy <= #TCQ app_rd_data_valid_ns; // Keep track of how many entries in the queue hold data. wire free_rd_buf = app_rd_data_valid_copy && app_rd_data_end; //changed to use registered version //of the signals in ordered to fix timing reg [DATA_BUF_ADDR_WIDTH:0] occ_cnt_r; wire [DATA_BUF_ADDR_WIDTH:0] occ_minus_one = occ_cnt_r - 1; wire [DATA_BUF_ADDR_WIDTH:0] occ_plus_one = occ_cnt_r + 1; begin : occupied_counter reg [DATA_BUF_ADDR_WIDTH:0] occ_cnt_ns; always @(/*AS*/free_rd_buf or occ_cnt_r or rd_accepted or rst or occ_minus_one or occ_plus_one) begin occ_cnt_ns = occ_cnt_r; if (rst) occ_cnt_ns = 0; else case ({rd_accepted, free_rd_buf}) 2'b01 : occ_cnt_ns = occ_minus_one; 2'b10 : occ_cnt_ns = occ_plus_one; endcase // case ({wr_data_end, new_rd_data}) end always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns; assign rd_buf_full = occ_cnt_ns[DATA_BUF_ADDR_WIDTH]; `ifdef MC_SVA rd_data_buffer_full: cover property (@(posedge clk) (~rst && rd_buf_full)); rd_data_buffer_inc_dec_15: cover property (@(posedge clk) (~rst && rd_accepted && free_rd_buf && (occ_cnt_r == 'hf))); rd_data_underflow: assert property (@(posedge clk) (rst || !((occ_cnt_r == 'b0) && (occ_cnt_ns == 'h1f)))); rd_data_overflow: assert property (@(posedge clk) (rst || !((occ_cnt_r == 'h10) && (occ_cnt_ns == 'h11)))); `endif end // block: occupied_counter // Generate the data_buf_address written into the memory controller // for reads. Increment with each accepted read, and rollover at 0xf. reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl; assign rd_data_buf_addr_r = rd_data_buf_addr_r_lcl; begin : data_buf_addr reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns; always @(/*AS*/rd_accepted or rd_data_buf_addr_r_lcl or rst) begin rd_data_buf_addr_ns = rd_data_buf_addr_r_lcl; if (rst) rd_data_buf_addr_ns = 0; else if (rd_accepted) rd_data_buf_addr_ns = rd_data_buf_addr_r_lcl + 1; end always @(posedge clk) rd_data_buf_addr_r_lcl <= #TCQ rd_data_buf_addr_ns; end // block: data_buf_addr end // block: not_strict_mode endgenerate endmodule // ui_rd_data // Local Variables: // verilog-library-directories:(".") // End:

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ui_rd_data.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // User interface read buffer. Re orders read data returned from the // memory controller back to the request order. // // Consists of a large buffer for the data, a status RAM and two counters. // // The large buffer is implemented with distributed RAM in 6 bit wide, // 1 read, 1 write mode. The status RAM is implemented with a distributed // RAM configured as 2 bits wide 1 read/write, 1 read mode. // // As read requests are received from the application, the data_buf_addr // counter supplies the data_buf_addr sent into the memory controller. // With each read request, the counter is incremented, eventually rolling // over. This mechanism labels each read request with an incrementing number. // // When the memory controller returns read data, it echos the original // data_buf_addr with the read data. // // The status RAM is indexed with the same address as the data buffer // RAM. Each word of the data buffer RAM has an associated status bit // and "end" bit. Requests of size 1 return a data burst on two consecutive // states. Requests of size zero return with a single assertion of rd_data_en. // // Upon returning data, the status and end bits are updated for each // corresponding location in the status RAM indexed by the data_buf_addr // echoed on the rd_data_addr field. // // The other side of the status and data RAMs is indexed by the rd_buf_indx. // The rd_buf_indx constantly monitors the status bit it is currently // pointing to. When the status becomes set to the proper state (more on // this later) read data is returned to the application, and the rd_buf_indx // is incremented. // // At rst the rd_buf_indx is initialized to zero. Data will not have been // returned from the memory controller yet, so there is nothing to return // to the application. Evenutally, read requests will be made, and the // memory controller will return the corresponding data. The memory // controller may not return this data in the request order. In which // case, the status bit at location zero, will not indicate // the data for request zero is ready. Eventually, the memory controller // will return data for request zero. The data is forwarded on to the // application, and rd_buf_indx is incremented to point to the next status // bits and data in the buffers. The status bit will be examined, and if // data is valid, this data will be returned as well. This process // continues until the status bit indexed by rd_buf_indx indicates data // is not ready. This may be because the rd_data_buf // is empty, or that some data was returned out of order. Since rd_buf_indx // always increments sequentially, data is always returned to the application // in request order. // // Some further discussion of the status bit is in order. The rd_data_buf // is a circular buffer. The status bit is a single bit. Distributed RAM // supports only a single write port. The write port is consumed by // memory controller read data updates. If a simple '1' were used to // indicate the status, when rd_data_indx rolled over it would immediately // encounter a one for a request that may not be ready. // // This problem is solved by causing read data returns to flip the // status bit, and adding hi order bit beyond the size required to // index the rd_data_buf. Data is considered ready when the status bit // and this hi order bit are equal. // // The status RAM needs to be initialized to zero after reset. This is // accomplished by cycling through all rd_buf_indx valus and writing a // zero to the status bits directly following deassertion of reset. This // mechanism is used for similar purposes // for the wr_data_buf. // // When ORDERING == "STRICT", read data reordering is unnecessary. For thi // case, most of the logic in the block is not generated. `timescale 1 ps / 1 ps // User interface read data. module mig_7series_v2_3_ui_rd_data # ( parameter TCQ = 100, parameter APP_DATA_WIDTH = 256, parameter DATA_BUF_ADDR_WIDTH = 5, parameter ECC = "OFF", parameter nCK_PER_CLK = 2 , parameter ORDERING = "NORM" ) (/*AUTOARG*/ // Outputs ram_init_done_r, ram_init_addr, app_rd_data_valid, app_rd_data_end, app_rd_data, app_ecc_multiple_err, rd_buf_full, rd_data_buf_addr_r, // Inputs rst, clk, rd_data_en, rd_data_addr, rd_data_offset, rd_data_end, rd_data, ecc_multiple, rd_accepted ); input rst; input clk; output wire ram_init_done_r; output wire [3:0] ram_init_addr; // rd_buf_indx points to the status and data storage rams for // reading data out to the app. reg [5:0] rd_buf_indx_r; reg ram_init_done_r_lcl /* synthesis syn_maxfan = 10 */; assign ram_init_done_r = ram_init_done_r_lcl; wire app_rd_data_valid_ns; wire single_data; reg [5:0] rd_buf_indx_ns; generate begin : rd_buf_indx wire upd_rd_buf_indx = ~ram_init_done_r_lcl || app_rd_data_valid_ns; // Loop through all status write addresses once after rst. Initializes // the status and pointer RAMs. wire ram_init_done_ns = ~rst && (ram_init_done_r_lcl || (rd_buf_indx_r[4:0] == 5'h1f)); always @(posedge clk) ram_init_done_r_lcl <= #TCQ ram_init_done_ns; always @(/*AS*/rd_buf_indx_r or rst or single_data or upd_rd_buf_indx) begin rd_buf_indx_ns = rd_buf_indx_r; if (rst) rd_buf_indx_ns = 6'b0; else if (upd_rd_buf_indx) rd_buf_indx_ns = // need to use every slot of RAMB32 if all address bits are used rd_buf_indx_r + 6'h1 + (DATA_BUF_ADDR_WIDTH == 5 ? 0 : single_data); end always @(posedge clk) rd_buf_indx_r <= #TCQ rd_buf_indx_ns; end endgenerate assign ram_init_addr = rd_buf_indx_r[3:0]; input rd_data_en; input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; input rd_data_offset; input rd_data_end; input [APP_DATA_WIDTH-1:0] rd_data; output reg app_rd_data_valid /* synthesis syn_maxfan = 10 */; output reg app_rd_data_end; output reg [APP_DATA_WIDTH-1:0] app_rd_data; input [3:0] ecc_multiple; reg [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_r = 'b0; output wire [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; assign app_ecc_multiple_err = app_ecc_multiple_err_r; input rd_accepted; output wire rd_buf_full; output wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r; // Compute dimensions of read data buffer. Depending on width of // DQ bus and DRAM CK // to fabric ratio, number of RAM32Ms is variable. RAM32Ms are used in // single write, single read, 6 bit wide mode. localparam RD_BUF_WIDTH = APP_DATA_WIDTH + (ECC == "OFF" ? 0 : 2*nCK_PER_CLK); localparam FULL_RAM_CNT = (RD_BUF_WIDTH/6); localparam REMAINDER = RD_BUF_WIDTH % 6; localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); localparam RAM_WIDTH = (RAM_CNT*6); generate if (ORDERING == "STRICT") begin : strict_mode assign app_rd_data_valid_ns = 1'b0; assign single_data = 1'b0; assign rd_buf_full = 1'b0; reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl; wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns = rst ? 0 : rd_data_buf_addr_r_lcl + rd_accepted; always @(posedge clk) rd_data_buf_addr_r_lcl <= #TCQ rd_data_buf_addr_ns; assign rd_data_buf_addr_r = rd_data_buf_addr_ns; // app_* signals required to be registered. if (ECC == "OFF") begin : ecc_off always @(/*AS*/rd_data) app_rd_data = rd_data; always @(/*AS*/rd_data_en) app_rd_data_valid = rd_data_en; always @(/*AS*/rd_data_end) app_rd_data_end = rd_data_end; end else begin : ecc_on always @(posedge clk) app_rd_data <= #TCQ rd_data; always @(posedge clk) app_rd_data_valid <= #TCQ rd_data_en; always @(posedge clk) app_rd_data_end <= #TCQ rd_data_end; always @(posedge clk) app_ecc_multiple_err_r <= #TCQ ecc_multiple; end end else begin : not_strict_mode wire rd_buf_we = ~ram_init_done_r_lcl || rd_data_en /* synthesis syn_maxfan = 10 */; // In configurations where read data is returned in a single fabric cycle // the offset is always zero and we can use the bit to get a deeper // FIFO. The RAMB32 has 5 address bits, so when the DATA_BUF_ADDR_WIDTH // is set to use them all, discard the offset. Otherwise, include the // offset. wire [4:0] rd_buf_wr_addr = DATA_BUF_ADDR_WIDTH == 5 ? rd_data_addr : {rd_data_addr, rd_data_offset}; wire [1:0] rd_status; // Instantiate status RAM. One bit for status and one for "end". begin : status_ram // Turns out read to write back status is a timing path. Update // the status in the ram on the state following the read. Bypass // the write data into the status read path. wire [4:0] status_ram_wr_addr_ns = ram_init_done_r_lcl ? rd_buf_wr_addr : rd_buf_indx_r[4:0]; reg [4:0] status_ram_wr_addr_r; always @(posedge clk) status_ram_wr_addr_r <= #TCQ status_ram_wr_addr_ns; wire [1:0] wr_status; // Not guaranteed to write second status bit. If it is written, always // copy in the first status bit. reg wr_status_r1; always @(posedge clk) wr_status_r1 <= #TCQ wr_status[0]; wire [1:0] status_ram_wr_data_ns = ram_init_done_r_lcl ? {rd_data_end, ~(rd_data_offset ? wr_status_r1 : wr_status[0])} : 2'b0; reg [1:0] status_ram_wr_data_r; always @(posedge clk) status_ram_wr_data_r <= #TCQ status_ram_wr_data_ns; reg rd_buf_we_r1; always @(posedge clk) rd_buf_we_r1 <= #TCQ rd_buf_we; RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(rd_status), .DOB(), .DOC(wr_status), .DOD(), .DIA(status_ram_wr_data_r), .DIB(2'b0), .DIC(status_ram_wr_data_r), .DID(status_ram_wr_data_r), .ADDRA(rd_buf_indx_r[4:0]), .ADDRB(5'b0), .ADDRC(status_ram_wr_addr_ns), .ADDRD(status_ram_wr_addr_r), .WE(rd_buf_we_r1), .WCLK(clk) ); end // block: status_ram wire [RAM_WIDTH-1:0] rd_buf_out_data; begin : rd_buf wire [RAM_WIDTH-1:0] rd_buf_in_data; if (REMAINDER == 0) if (ECC == "OFF") assign rd_buf_in_data = rd_data; else assign rd_buf_in_data = {ecc_multiple, rd_data}; else if (ECC == "OFF") assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, rd_data}; else assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, ecc_multiple, rd_data}; // Dedicated copy for driving distributed RAM. (* keep = "true" *) reg [4:0] rd_buf_indx_copy_r /* synthesis syn_keep = 1 */; always @(posedge clk) rd_buf_indx_copy_r <= #TCQ rd_buf_indx_ns[4:0]; genvar i; for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(rd_buf_out_data[((i*6)+4)+:2]), .DOB(rd_buf_out_data[((i*6)+2)+:2]), .DOC(rd_buf_out_data[((i*6)+0)+:2]), .DOD(), .DIA(rd_buf_in_data[((i*6)+4)+:2]), .DIB(rd_buf_in_data[((i*6)+2)+:2]), .DIC(rd_buf_in_data[((i*6)+0)+:2]), .DID(2'b0), .ADDRA(rd_buf_indx_copy_r[4:0]), .ADDRB(rd_buf_indx_copy_r[4:0]), .ADDRC(rd_buf_indx_copy_r[4:0]), .ADDRD(rd_buf_wr_addr), .WE(rd_buf_we), .WCLK(clk) ); end // block: rd_buffer_ram end wire rd_data_rdy = (rd_status[0] == rd_buf_indx_r[5]); wire bypass = rd_data_en && (rd_buf_wr_addr[4:0] == rd_buf_indx_r[4:0]) /* synthesis syn_maxfan = 10 */; assign app_rd_data_valid_ns = ram_init_done_r_lcl && (bypass || rd_data_rdy); wire app_rd_data_end_ns = bypass ? rd_data_end : rd_status[1]; always @(posedge clk) app_rd_data_valid <= #TCQ app_rd_data_valid_ns; always @(posedge clk) app_rd_data_end <= #TCQ app_rd_data_end_ns; assign single_data = app_rd_data_valid_ns && app_rd_data_end_ns && ~rd_buf_indx_r[0]; wire [APP_DATA_WIDTH-1:0] app_rd_data_ns = bypass ? rd_data : rd_buf_out_data[APP_DATA_WIDTH-1:0]; always @(posedge clk) app_rd_data <= #TCQ app_rd_data_ns; if (ECC != "OFF") begin : assign_app_ecc_multiple wire [3:0] app_ecc_multiple_err_ns = bypass ? ecc_multiple : rd_buf_out_data[APP_DATA_WIDTH+:4]; always @(posedge clk) app_ecc_multiple_err_r <= #TCQ app_ecc_multiple_err_ns; end //Added to fix timing. The signal app_rd_data_valid has //a very high fanout. So making a dedicated copy for usage //with the occ_cnt counter. (* equivalent_register_removal = "no" *) reg app_rd_data_valid_copy; always @(posedge clk) app_rd_data_valid_copy <= #TCQ app_rd_data_valid_ns; // Keep track of how many entries in the queue hold data. wire free_rd_buf = app_rd_data_valid_copy && app_rd_data_end; //changed to use registered version //of the signals in ordered to fix timing reg [DATA_BUF_ADDR_WIDTH:0] occ_cnt_r; wire [DATA_BUF_ADDR_WIDTH:0] occ_minus_one = occ_cnt_r - 1; wire [DATA_BUF_ADDR_WIDTH:0] occ_plus_one = occ_cnt_r + 1; begin : occupied_counter reg [DATA_BUF_ADDR_WIDTH:0] occ_cnt_ns; always @(/*AS*/free_rd_buf or occ_cnt_r or rd_accepted or rst or occ_minus_one or occ_plus_one) begin occ_cnt_ns = occ_cnt_r; if (rst) occ_cnt_ns = 0; else case ({rd_accepted, free_rd_buf}) 2'b01 : occ_cnt_ns = occ_minus_one; 2'b10 : occ_cnt_ns = occ_plus_one; endcase // case ({wr_data_end, new_rd_data}) end always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns; assign rd_buf_full = occ_cnt_ns[DATA_BUF_ADDR_WIDTH]; `ifdef MC_SVA rd_data_buffer_full: cover property (@(posedge clk) (~rst && rd_buf_full)); rd_data_buffer_inc_dec_15: cover property (@(posedge clk) (~rst && rd_accepted && free_rd_buf && (occ_cnt_r == 'hf))); rd_data_underflow: assert property (@(posedge clk) (rst || !((occ_cnt_r == 'b0) && (occ_cnt_ns == 'h1f)))); rd_data_overflow: assert property (@(posedge clk) (rst || !((occ_cnt_r == 'h10) && (occ_cnt_ns == 'h11)))); `endif end // block: occupied_counter // Generate the data_buf_address written into the memory controller // for reads. Increment with each accepted read, and rollover at 0xf. reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl; assign rd_data_buf_addr_r = rd_data_buf_addr_r_lcl; begin : data_buf_addr reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns; always @(/*AS*/rd_accepted or rd_data_buf_addr_r_lcl or rst) begin rd_data_buf_addr_ns = rd_data_buf_addr_r_lcl; if (rst) rd_data_buf_addr_ns = 0; else if (rd_accepted) rd_data_buf_addr_ns = rd_data_buf_addr_r_lcl + 1; end always @(posedge clk) rd_data_buf_addr_r_lcl <= #TCQ rd_data_buf_addr_ns; end // block: data_buf_addr end // block: not_strict_mode endgenerate endmodule // ui_rd_data // Local Variables: // verilog-library-directories:(".") // End:

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ui_rd_data.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // User interface read buffer. Re orders read data returned from the // memory controller back to the request order. // // Consists of a large buffer for the data, a status RAM and two counters. // // The large buffer is implemented with distributed RAM in 6 bit wide, // 1 read, 1 write mode. The status RAM is implemented with a distributed // RAM configured as 2 bits wide 1 read/write, 1 read mode. // // As read requests are received from the application, the data_buf_addr // counter supplies the data_buf_addr sent into the memory controller. // With each read request, the counter is incremented, eventually rolling // over. This mechanism labels each read request with an incrementing number. // // When the memory controller returns read data, it echos the original // data_buf_addr with the read data. // // The status RAM is indexed with the same address as the data buffer // RAM. Each word of the data buffer RAM has an associated status bit // and "end" bit. Requests of size 1 return a data burst on two consecutive // states. Requests of size zero return with a single assertion of rd_data_en. // // Upon returning data, the status and end bits are updated for each // corresponding location in the status RAM indexed by the data_buf_addr // echoed on the rd_data_addr field. // // The other side of the status and data RAMs is indexed by the rd_buf_indx. // The rd_buf_indx constantly monitors the status bit it is currently // pointing to. When the status becomes set to the proper state (more on // this later) read data is returned to the application, and the rd_buf_indx // is incremented. // // At rst the rd_buf_indx is initialized to zero. Data will not have been // returned from the memory controller yet, so there is nothing to return // to the application. Evenutally, read requests will be made, and the // memory controller will return the corresponding data. The memory // controller may not return this data in the request order. In which // case, the status bit at location zero, will not indicate // the data for request zero is ready. Eventually, the memory controller // will return data for request zero. The data is forwarded on to the // application, and rd_buf_indx is incremented to point to the next status // bits and data in the buffers. The status bit will be examined, and if // data is valid, this data will be returned as well. This process // continues until the status bit indexed by rd_buf_indx indicates data // is not ready. This may be because the rd_data_buf // is empty, or that some data was returned out of order. Since rd_buf_indx // always increments sequentially, data is always returned to the application // in request order. // // Some further discussion of the status bit is in order. The rd_data_buf // is a circular buffer. The status bit is a single bit. Distributed RAM // supports only a single write port. The write port is consumed by // memory controller read data updates. If a simple '1' were used to // indicate the status, when rd_data_indx rolled over it would immediately // encounter a one for a request that may not be ready. // // This problem is solved by causing read data returns to flip the // status bit, and adding hi order bit beyond the size required to // index the rd_data_buf. Data is considered ready when the status bit // and this hi order bit are equal. // // The status RAM needs to be initialized to zero after reset. This is // accomplished by cycling through all rd_buf_indx valus and writing a // zero to the status bits directly following deassertion of reset. This // mechanism is used for similar purposes // for the wr_data_buf. // // When ORDERING == "STRICT", read data reordering is unnecessary. For thi // case, most of the logic in the block is not generated. `timescale 1 ps / 1 ps // User interface read data. module mig_7series_v2_3_ui_rd_data # ( parameter TCQ = 100, parameter APP_DATA_WIDTH = 256, parameter DATA_BUF_ADDR_WIDTH = 5, parameter ECC = "OFF", parameter nCK_PER_CLK = 2 , parameter ORDERING = "NORM" ) (/*AUTOARG*/ // Outputs ram_init_done_r, ram_init_addr, app_rd_data_valid, app_rd_data_end, app_rd_data, app_ecc_multiple_err, rd_buf_full, rd_data_buf_addr_r, // Inputs rst, clk, rd_data_en, rd_data_addr, rd_data_offset, rd_data_end, rd_data, ecc_multiple, rd_accepted ); input rst; input clk; output wire ram_init_done_r; output wire [3:0] ram_init_addr; // rd_buf_indx points to the status and data storage rams for // reading data out to the app. reg [5:0] rd_buf_indx_r; reg ram_init_done_r_lcl /* synthesis syn_maxfan = 10 */; assign ram_init_done_r = ram_init_done_r_lcl; wire app_rd_data_valid_ns; wire single_data; reg [5:0] rd_buf_indx_ns; generate begin : rd_buf_indx wire upd_rd_buf_indx = ~ram_init_done_r_lcl || app_rd_data_valid_ns; // Loop through all status write addresses once after rst. Initializes // the status and pointer RAMs. wire ram_init_done_ns = ~rst && (ram_init_done_r_lcl || (rd_buf_indx_r[4:0] == 5'h1f)); always @(posedge clk) ram_init_done_r_lcl <= #TCQ ram_init_done_ns; always @(/*AS*/rd_buf_indx_r or rst or single_data or upd_rd_buf_indx) begin rd_buf_indx_ns = rd_buf_indx_r; if (rst) rd_buf_indx_ns = 6'b0; else if (upd_rd_buf_indx) rd_buf_indx_ns = // need to use every slot of RAMB32 if all address bits are used rd_buf_indx_r + 6'h1 + (DATA_BUF_ADDR_WIDTH == 5 ? 0 : single_data); end always @(posedge clk) rd_buf_indx_r <= #TCQ rd_buf_indx_ns; end endgenerate assign ram_init_addr = rd_buf_indx_r[3:0]; input rd_data_en; input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; input rd_data_offset; input rd_data_end; input [APP_DATA_WIDTH-1:0] rd_data; output reg app_rd_data_valid /* synthesis syn_maxfan = 10 */; output reg app_rd_data_end; output reg [APP_DATA_WIDTH-1:0] app_rd_data; input [3:0] ecc_multiple; reg [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_r = 'b0; output wire [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; assign app_ecc_multiple_err = app_ecc_multiple_err_r; input rd_accepted; output wire rd_buf_full; output wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r; // Compute dimensions of read data buffer. Depending on width of // DQ bus and DRAM CK // to fabric ratio, number of RAM32Ms is variable. RAM32Ms are used in // single write, single read, 6 bit wide mode. localparam RD_BUF_WIDTH = APP_DATA_WIDTH + (ECC == "OFF" ? 0 : 2*nCK_PER_CLK); localparam FULL_RAM_CNT = (RD_BUF_WIDTH/6); localparam REMAINDER = RD_BUF_WIDTH % 6; localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1); localparam RAM_WIDTH = (RAM_CNT*6); generate if (ORDERING == "STRICT") begin : strict_mode assign app_rd_data_valid_ns = 1'b0; assign single_data = 1'b0; assign rd_buf_full = 1'b0; reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl; wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns = rst ? 0 : rd_data_buf_addr_r_lcl + rd_accepted; always @(posedge clk) rd_data_buf_addr_r_lcl <= #TCQ rd_data_buf_addr_ns; assign rd_data_buf_addr_r = rd_data_buf_addr_ns; // app_* signals required to be registered. if (ECC == "OFF") begin : ecc_off always @(/*AS*/rd_data) app_rd_data = rd_data; always @(/*AS*/rd_data_en) app_rd_data_valid = rd_data_en; always @(/*AS*/rd_data_end) app_rd_data_end = rd_data_end; end else begin : ecc_on always @(posedge clk) app_rd_data <= #TCQ rd_data; always @(posedge clk) app_rd_data_valid <= #TCQ rd_data_en; always @(posedge clk) app_rd_data_end <= #TCQ rd_data_end; always @(posedge clk) app_ecc_multiple_err_r <= #TCQ ecc_multiple; end end else begin : not_strict_mode wire rd_buf_we = ~ram_init_done_r_lcl || rd_data_en /* synthesis syn_maxfan = 10 */; // In configurations where read data is returned in a single fabric cycle // the offset is always zero and we can use the bit to get a deeper // FIFO. The RAMB32 has 5 address bits, so when the DATA_BUF_ADDR_WIDTH // is set to use them all, discard the offset. Otherwise, include the // offset. wire [4:0] rd_buf_wr_addr = DATA_BUF_ADDR_WIDTH == 5 ? rd_data_addr : {rd_data_addr, rd_data_offset}; wire [1:0] rd_status; // Instantiate status RAM. One bit for status and one for "end". begin : status_ram // Turns out read to write back status is a timing path. Update // the status in the ram on the state following the read. Bypass // the write data into the status read path. wire [4:0] status_ram_wr_addr_ns = ram_init_done_r_lcl ? rd_buf_wr_addr : rd_buf_indx_r[4:0]; reg [4:0] status_ram_wr_addr_r; always @(posedge clk) status_ram_wr_addr_r <= #TCQ status_ram_wr_addr_ns; wire [1:0] wr_status; // Not guaranteed to write second status bit. If it is written, always // copy in the first status bit. reg wr_status_r1; always @(posedge clk) wr_status_r1 <= #TCQ wr_status[0]; wire [1:0] status_ram_wr_data_ns = ram_init_done_r_lcl ? {rd_data_end, ~(rd_data_offset ? wr_status_r1 : wr_status[0])} : 2'b0; reg [1:0] status_ram_wr_data_r; always @(posedge clk) status_ram_wr_data_r <= #TCQ status_ram_wr_data_ns; reg rd_buf_we_r1; always @(posedge clk) rd_buf_we_r1 <= #TCQ rd_buf_we; RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(rd_status), .DOB(), .DOC(wr_status), .DOD(), .DIA(status_ram_wr_data_r), .DIB(2'b0), .DIC(status_ram_wr_data_r), .DID(status_ram_wr_data_r), .ADDRA(rd_buf_indx_r[4:0]), .ADDRB(5'b0), .ADDRC(status_ram_wr_addr_ns), .ADDRD(status_ram_wr_addr_r), .WE(rd_buf_we_r1), .WCLK(clk) ); end // block: status_ram wire [RAM_WIDTH-1:0] rd_buf_out_data; begin : rd_buf wire [RAM_WIDTH-1:0] rd_buf_in_data; if (REMAINDER == 0) if (ECC == "OFF") assign rd_buf_in_data = rd_data; else assign rd_buf_in_data = {ecc_multiple, rd_data}; else if (ECC == "OFF") assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, rd_data}; else assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, ecc_multiple, rd_data}; // Dedicated copy for driving distributed RAM. (* keep = "true" *) reg [4:0] rd_buf_indx_copy_r /* synthesis syn_keep = 1 */; always @(posedge clk) rd_buf_indx_copy_r <= #TCQ rd_buf_indx_ns[4:0]; genvar i; for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram RAM32M #(.INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000) ) RAM32M0 ( .DOA(rd_buf_out_data[((i*6)+4)+:2]), .DOB(rd_buf_out_data[((i*6)+2)+:2]), .DOC(rd_buf_out_data[((i*6)+0)+:2]), .DOD(), .DIA(rd_buf_in_data[((i*6)+4)+:2]), .DIB(rd_buf_in_data[((i*6)+2)+:2]), .DIC(rd_buf_in_data[((i*6)+0)+:2]), .DID(2'b0), .ADDRA(rd_buf_indx_copy_r[4:0]), .ADDRB(rd_buf_indx_copy_r[4:0]), .ADDRC(rd_buf_indx_copy_r[4:0]), .ADDRD(rd_buf_wr_addr), .WE(rd_buf_we), .WCLK(clk) ); end // block: rd_buffer_ram end wire rd_data_rdy = (rd_status[0] == rd_buf_indx_r[5]); wire bypass = rd_data_en && (rd_buf_wr_addr[4:0] == rd_buf_indx_r[4:0]) /* synthesis syn_maxfan = 10 */; assign app_rd_data_valid_ns = ram_init_done_r_lcl && (bypass || rd_data_rdy); wire app_rd_data_end_ns = bypass ? rd_data_end : rd_status[1]; always @(posedge clk) app_rd_data_valid <= #TCQ app_rd_data_valid_ns; always @(posedge clk) app_rd_data_end <= #TCQ app_rd_data_end_ns; assign single_data = app_rd_data_valid_ns && app_rd_data_end_ns && ~rd_buf_indx_r[0]; wire [APP_DATA_WIDTH-1:0] app_rd_data_ns = bypass ? rd_data : rd_buf_out_data[APP_DATA_WIDTH-1:0]; always @(posedge clk) app_rd_data <= #TCQ app_rd_data_ns; if (ECC != "OFF") begin : assign_app_ecc_multiple wire [3:0] app_ecc_multiple_err_ns = bypass ? ecc_multiple : rd_buf_out_data[APP_DATA_WIDTH+:4]; always @(posedge clk) app_ecc_multiple_err_r <= #TCQ app_ecc_multiple_err_ns; end //Added to fix timing. The signal app_rd_data_valid has //a very high fanout. So making a dedicated copy for usage //with the occ_cnt counter. (* equivalent_register_removal = "no" *) reg app_rd_data_valid_copy; always @(posedge clk) app_rd_data_valid_copy <= #TCQ app_rd_data_valid_ns; // Keep track of how many entries in the queue hold data. wire free_rd_buf = app_rd_data_valid_copy && app_rd_data_end; //changed to use registered version //of the signals in ordered to fix timing reg [DATA_BUF_ADDR_WIDTH:0] occ_cnt_r; wire [DATA_BUF_ADDR_WIDTH:0] occ_minus_one = occ_cnt_r - 1; wire [DATA_BUF_ADDR_WIDTH:0] occ_plus_one = occ_cnt_r + 1; begin : occupied_counter reg [DATA_BUF_ADDR_WIDTH:0] occ_cnt_ns; always @(/*AS*/free_rd_buf or occ_cnt_r or rd_accepted or rst or occ_minus_one or occ_plus_one) begin occ_cnt_ns = occ_cnt_r; if (rst) occ_cnt_ns = 0; else case ({rd_accepted, free_rd_buf}) 2'b01 : occ_cnt_ns = occ_minus_one; 2'b10 : occ_cnt_ns = occ_plus_one; endcase // case ({wr_data_end, new_rd_data}) end always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns; assign rd_buf_full = occ_cnt_ns[DATA_BUF_ADDR_WIDTH]; `ifdef MC_SVA rd_data_buffer_full: cover property (@(posedge clk) (~rst && rd_buf_full)); rd_data_buffer_inc_dec_15: cover property (@(posedge clk) (~rst && rd_accepted && free_rd_buf && (occ_cnt_r == 'hf))); rd_data_underflow: assert property (@(posedge clk) (rst || !((occ_cnt_r == 'b0) && (occ_cnt_ns == 'h1f)))); rd_data_overflow: assert property (@(posedge clk) (rst || !((occ_cnt_r == 'h10) && (occ_cnt_ns == 'h11)))); `endif end // block: occupied_counter // Generate the data_buf_address written into the memory controller // for reads. Increment with each accepted read, and rollover at 0xf. reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl; assign rd_data_buf_addr_r = rd_data_buf_addr_r_lcl; begin : data_buf_addr reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns; always @(/*AS*/rd_accepted or rd_data_buf_addr_r_lcl or rst) begin rd_data_buf_addr_ns = rd_data_buf_addr_r_lcl; if (rst) rd_data_buf_addr_ns = 0; else if (rd_accepted) rd_data_buf_addr_ns = rd_data_buf_addr_r_lcl + 1; end always @(posedge clk) rd_data_buf_addr_r_lcl <= #TCQ rd_data_buf_addr_ns; end // block: data_buf_addr end // block: not_strict_mode endgenerate endmodule // ui_rd_data // Local Variables: // verilog-library-directories:(".") // End:

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_dqs_found_cal.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Read leveling calibration logic // NOTES: // 1. Phaser_In DQSFOUND calibration //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $ **$Date: 2011/06/02 08:35:08 $ **$Author: **$Revision: **$Source: ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_dqs_found_cal # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter nCL = 5, // Read CAS latency parameter AL = "0", parameter nCWL = 5, // Write CAS latency parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" parameter RANKS = 1, // # of memory ranks in the system parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate parameter N_CTL_LANES = 3, // Number of control byte lanes parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl) parameter HIGHEST_BANK = 3, // Sum of I/O Banks parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf ) ( input clk, input rst, input dqsfound_retry, // From phy_init input pi_dqs_found_start, input detect_pi_found_dqs, input prech_done, // DQSFOUND per Phaser_IN input [HIGHEST_LANE-1:0] pi_dqs_found_lanes, output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal, // To phy_init output [5:0] rd_data_offset_0, output [5:0] rd_data_offset_1, output [5:0] rd_data_offset_2, output pi_dqs_found_rank_done, output pi_dqs_found_done, output reg pi_dqs_found_err, output [6*RANKS-1:0] rd_data_offset_ranks_0, output [6*RANKS-1:0] rd_data_offset_ranks_1, output [6*RANKS-1:0] rd_data_offset_ranks_2, output reg dqsfound_retry_done, output reg dqs_found_prech_req, //To MC output [6*RANKS-1:0] rd_data_offset_ranks_mc_0, output [6*RANKS-1:0] rd_data_offset_ranks_mc_1, output [6*RANKS-1:0] rd_data_offset_ranks_mc_2, input [8:0] po_counter_read_val, output rd_data_offset_cal_done, output fine_adjust_done, output [N_CTL_LANES-1:0] fine_adjust_lane_cnt, output reg ck_po_stg2_f_indec, output reg ck_po_stg2_f_en, output [255:0] dbg_dqs_found_cal ); // For non-zero AL values localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; // Adding the register dimm latency to write latency localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; // Added to reduce simulation time localparam LATENCY_FACTOR = 13; localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1; localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]), (DATA_CTL_B4[2] & BYTE_LANES_B4[2]), (DATA_CTL_B4[1] & BYTE_LANES_B4[1]), (DATA_CTL_B4[0] & BYTE_LANES_B4[0]), (DATA_CTL_B3[3] & BYTE_LANES_B3[3]), (DATA_CTL_B3[2] & BYTE_LANES_B3[2]), (DATA_CTL_B3[1] & BYTE_LANES_B3[1]), (DATA_CTL_B3[0] & BYTE_LANES_B3[0]), (DATA_CTL_B2[3] & BYTE_LANES_B2[3]), (DATA_CTL_B2[2] & BYTE_LANES_B2[2]), (DATA_CTL_B2[1] & BYTE_LANES_B2[1]), (DATA_CTL_B2[0] & BYTE_LANES_B2[0]), (DATA_CTL_B1[3] & BYTE_LANES_B1[3]), (DATA_CTL_B1[2] & BYTE_LANES_B1[2]), (DATA_CTL_B1[1] & BYTE_LANES_B1[1]), (DATA_CTL_B1[0] & BYTE_LANES_B1[0]), (DATA_CTL_B0[3] & BYTE_LANES_B0[3]), (DATA_CTL_B0[2] & BYTE_LANES_B0[2]), (DATA_CTL_B0[1] & BYTE_LANES_B0[1]), (DATA_CTL_B0[0] & BYTE_LANES_B0[0])}; localparam FINE_ADJ_IDLE = 4'h0; localparam RST_POSTWAIT = 4'h1; localparam RST_POSTWAIT1 = 4'h2; localparam RST_WAIT = 4'h3; localparam FINE_ADJ_INIT = 4'h4; localparam FINE_INC = 4'h5; localparam FINE_INC_WAIT = 4'h6; localparam FINE_INC_PREWAIT = 4'h7; localparam DETECT_PREWAIT = 4'h8; localparam DETECT_DQSFOUND = 4'h9; localparam PRECH_WAIT = 4'hA; localparam FINE_DEC = 4'hB; localparam FINE_DEC_WAIT = 4'hC; localparam FINE_DEC_PREWAIT = 4'hD; localparam FINAL_WAIT = 4'hE; localparam FINE_ADJ_DONE = 4'hF; integer k,l,m,n,p,q,r,s; reg dqs_found_start_r; reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1]; reg rank_done_r; reg rank_done_r1; reg dqs_found_done_r; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3; reg init_dqsfound_done_r; reg init_dqsfound_done_r1; reg init_dqsfound_done_r2; reg init_dqsfound_done_r3; reg init_dqsfound_done_r4; reg init_dqsfound_done_r5; reg [1:0] rnk_cnt_r; reg [2:0 ] final_do_index[0:RANKS-1]; reg [5:0 ] final_do_max[0:RANKS-1]; reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1]; reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1]; reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r; reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1; reg [10*HIGHEST_BANK-1:0] retry_cnt; reg dqsfound_retry_r1; wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int; reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank; reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r; reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank; reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r; reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r; // CK/Control byte lanes fine adjust stage reg fine_adjust; reg [N_CTL_LANES-1:0] ctl_lane_cnt; reg [3:0] fine_adj_state_r; reg fine_adjust_done_r; reg rst_dqs_find; reg rst_dqs_find_r1; reg rst_dqs_find_r2; reg [5:0] init_dec_cnt; reg [5:0] dec_cnt; reg [5:0] inc_cnt; reg final_dec_done; reg init_dec_done; reg first_fail_detect; reg second_fail_detect; reg [5:0] first_fail_taps; reg [5:0] second_fail_taps; reg [5:0] stable_pass_cnt; reg [3:0] detect_rd_cnt; //*************************************************************************** // Debug signals // //*************************************************************************** assign dbg_dqs_found_cal[5:0] = first_fail_taps; assign dbg_dqs_found_cal[11:6] = second_fail_taps; assign dbg_dqs_found_cal[12] = first_fail_detect; assign dbg_dqs_found_cal[13] = second_fail_detect; assign dbg_dqs_found_cal[14] = fine_adjust_done_r; assign pi_dqs_found_rank_done = rank_done_r; assign pi_dqs_found_done = dqs_found_done_r; generate genvar rnk_cnt; if (HIGHEST_BANK == 3) begin // Three Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12]; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12]; end end else if (HIGHEST_BANK == 2) begin // Two Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; end end else begin // Single Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; end end endgenerate // final_data_offset is used during write calibration and during // normal operation. One rd_data_offset value per rank for entire // interface generate if (HIGHEST_BANK == 3) begin // Three I/O Bank interface assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : final_data_offset[rnk_cnt_r][6+:6]; assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] : final_data_offset[rnk_cnt_r][12+:6]; end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : final_data_offset[rnk_cnt_r][6+:6]; assign rd_data_offset_2 = 'd0; end else begin assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = 'd0; assign rd_data_offset_2 = 'd0; end endgenerate assign rd_data_offset_cal_done = init_dqsfound_done_r; assign fine_adjust_lane_cnt = ctl_lane_cnt; //************************************************************************** // DQSFOUND all and any generation // pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are // asserted // pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx // is asserted //************************************************************************** generate if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12)) assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3; else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11)) assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3}; else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10)) assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3}; else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9)) assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3}; endgenerate always @(posedge clk) begin if (rst) begin for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found pi_dqs_found_all_bank[k] <= #TCQ 'b0; pi_dqs_found_any_bank[k] <= #TCQ 'b0; end end else if (pi_dqs_found_start) begin for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) & (!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) & (!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) & (!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]); pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) | (DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) | (DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) | (DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]); end end end always @(posedge clk) begin pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank; pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank; end //***************************************************************************** // Counter to increase number of 4 back-to-back reads per rd_data_offset and // per CK/A/C tap value //***************************************************************************** always @(posedge clk) begin if (rst || (detect_rd_cnt == 'd0)) detect_rd_cnt <= #TCQ NUM_READS; else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0)) detect_rd_cnt <= #TCQ detect_rd_cnt - 1; end //************************************************************************** // Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls // //************************************************************************** assign fine_adjust_done = fine_adjust_done_r; always @(posedge clk) begin rst_dqs_find_r1 <= #TCQ rst_dqs_find; rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1; end always @(posedge clk) begin if(rst)begin fine_adjust <= #TCQ 1'b0; ctl_lane_cnt <= #TCQ 'd0; fine_adj_state_r <= #TCQ FINE_ADJ_IDLE; fine_adjust_done_r <= #TCQ 1'b0; ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; rst_dqs_find <= #TCQ 1'b0; init_dec_cnt <= #TCQ 'd31; dec_cnt <= #TCQ 'd0; inc_cnt <= #TCQ 'd0; init_dec_done <= #TCQ 1'b0; final_dec_done <= #TCQ 1'b0; first_fail_detect <= #TCQ 1'b0; second_fail_detect <= #TCQ 1'b0; first_fail_taps <= #TCQ 'd0; second_fail_taps <= #TCQ 'd0; stable_pass_cnt <= #TCQ 'd0; dqs_found_prech_req<= #TCQ 1'b0; end else begin case (fine_adj_state_r) FINE_ADJ_IDLE: begin if (init_dqsfound_done_r5) begin if (SIM_CAL_OPTION == "FAST_CAL") begin fine_adjust <= #TCQ 1'b1; fine_adj_state_r <= #TCQ FINE_ADJ_DONE; rst_dqs_find <= #TCQ 1'b0; end else begin fine_adjust <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; rst_dqs_find <= #TCQ 1'b1; end end end RST_WAIT: begin if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin rst_dqs_find <= #TCQ 1'b0; if (|init_dec_cnt) fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; else if (final_dec_done) fine_adj_state_r <= #TCQ FINE_ADJ_DONE; else fine_adj_state_r <= #TCQ RST_POSTWAIT; end end RST_POSTWAIT: begin fine_adj_state_r <= #TCQ RST_POSTWAIT1; end RST_POSTWAIT1: begin fine_adj_state_r <= #TCQ FINE_ADJ_INIT; end FINE_ADJ_INIT: begin //if (detect_pi_found_dqs && (inc_cnt < 'd63)) fine_adj_state_r <= #TCQ FINE_INC; end FINE_INC: begin fine_adj_state_r <= #TCQ FINE_INC_WAIT; ck_po_stg2_f_indec <= #TCQ 1'b1; ck_po_stg2_f_en <= #TCQ 1'b1; if (ctl_lane_cnt == N_CTL_LANES-1) inc_cnt <= #TCQ inc_cnt + 1; end FINE_INC_WAIT: begin ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; if (ctl_lane_cnt != N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; fine_adj_state_r <= #TCQ FINE_INC_PREWAIT; end else if (ctl_lane_cnt == N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ 'd0; fine_adj_state_r <= #TCQ DETECT_PREWAIT; end end FINE_INC_PREWAIT: begin fine_adj_state_r <= #TCQ FINE_INC; end DETECT_PREWAIT: begin if (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) fine_adj_state_r <= #TCQ DETECT_DQSFOUND; else fine_adj_state_r <= #TCQ DETECT_PREWAIT; end DETECT_DQSFOUND: begin if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin stable_pass_cnt <= #TCQ 'd0; if (~first_fail_detect && (inc_cnt == 'd63)) begin // First failing tap detected at 63 taps // then decrement to 31 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ 'd32; end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin // First failing tap detected at greater than 30 taps // then stop looking for second edge and decrement first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ (inc_cnt>>1) + 1; end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin // First failing tap detected, continue incrementing // until either second failing tap detected or 63 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; rst_dqs_find <= #TCQ 1'b1; if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else fine_adj_state_r <= #TCQ RST_WAIT; end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin // Consecutive 30 taps of passing region was not found // continue incrementing first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; rst_dqs_find <= #TCQ 1'b1; if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else fine_adj_state_r <= #TCQ RST_WAIT; end else if (first_fail_detect && (inc_cnt == 'd63)) begin if (stable_pass_cnt < 'd30) begin // Consecutive 30 taps of passing region was not found // from tap 0 to 63 so decrement back to 31 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ 'd32; end else begin // Consecutive 30 taps of passing region was found // between first_fail_taps and 63 fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); end end else begin // Second failing tap detected, decrement to center of // failing taps second_fail_detect <= #TCQ 1'b1; second_fail_taps <= #TCQ inc_cnt; dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); fine_adj_state_r <= #TCQ FINE_DEC; end end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin stable_pass_cnt <= #TCQ stable_pass_cnt + 1; if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else if (inc_cnt < 'd63) begin rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end else begin fine_adj_state_r <= #TCQ FINE_DEC; if (~first_fail_detect || (first_fail_taps > 'd33)) // No failing taps detected, decrement by 31 dec_cnt <= #TCQ 'd32; //else if (first_fail_detect && (stable_pass_cnt > 'd28)) // // First failing tap detected between 0 and 34 // // decrement midpoint between 63 and failing tap // dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); else // First failing tap detected // decrement to midpoint between 63 and failing tap dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); end end end PRECH_WAIT: begin if (prech_done) begin dqs_found_prech_req <= #TCQ 1'b0; rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end end FINE_DEC: begin fine_adj_state_r <= #TCQ FINE_DEC_WAIT; ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b1; if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0)) init_dec_cnt <= #TCQ init_dec_cnt - 1; else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0)) dec_cnt <= #TCQ dec_cnt - 1; end FINE_DEC_WAIT: begin ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; if (ctl_lane_cnt != N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; end else if (ctl_lane_cnt == N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ 'd0; if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0)) fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; else begin fine_adj_state_r <= #TCQ FINAL_WAIT; if ((init_dec_cnt == 'd0) && ~init_dec_done) init_dec_done <= #TCQ 1'b1; else final_dec_done <= #TCQ 1'b1; end end end FINE_DEC_PREWAIT: begin fine_adj_state_r <= #TCQ FINE_DEC; end FINAL_WAIT: begin rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end FINE_ADJ_DONE: begin if (&pi_dqs_found_all_bank) begin fine_adjust_done_r <= #TCQ 1'b1; rst_dqs_find <= #TCQ 1'b0; fine_adj_state_r <= #TCQ FINE_ADJ_DONE; end end endcase end end //***************************************************************************** always@(posedge clk) dqs_found_start_r <= #TCQ pi_dqs_found_start; always @(posedge clk) begin if (rst) rnk_cnt_r <= #TCQ 2'b00; else if (init_dqsfound_done_r) rnk_cnt_r <= #TCQ rnk_cnt_r; else if (rank_done_r) rnk_cnt_r <= #TCQ rnk_cnt_r + 1; end //***************************************************************** // Read data_offset calibration done signal //***************************************************************** always @(posedge clk) begin if (rst || (|pi_rst_stg1_cal_r)) init_dqsfound_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank) begin if (rnk_cnt_r == RANKS-1) init_dqsfound_done_r <= #TCQ 1'b1; else init_dqsfound_done_r <= #TCQ 1'b0; end end always @(posedge clk) begin if (rst || (init_dqsfound_done_r && (rnk_cnt_r == RANKS-1))) rank_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r)) rank_done_r <= #TCQ 1'b1; else rank_done_r <= #TCQ 1'b0; end always @(posedge clk) begin pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes; pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1; pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2; init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r; init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1; init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2; init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3; init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4; rank_done_r1 <= #TCQ rank_done_r; dqsfound_retry_r1 <= #TCQ dqsfound_retry; end always @(posedge clk) begin if (rst) dqs_found_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 && (fine_adj_state_r == FINE_ADJ_DONE)) dqs_found_done_r <= #TCQ 1'b1; else dqs_found_done_r <= #TCQ 1'b0; end generate if (HIGHEST_BANK == 3) begin // Three I/O Bank interface // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[1]) || (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust) pi_rst_stg1_cal_r[2] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[2]) || (pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) || (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[2] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[2]) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[10+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[1]) retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; else retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[20+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[2]) retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1; else retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[1] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[2] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[2] <= #TCQ 1'b1; end // Read data offset value for all DQS in a Bank always @(posedge clk) begin if (rst) begin for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1; end always @(posedge clk) begin if (rst) begin for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && //(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1; end always @(posedge clk) begin if (rst) begin for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] && //(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] - 1; end //***************************************************************************** // Two I/O Bank Interface //***************************************************************************** end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[1]) || (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[10+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[1]) retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; else retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[1] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[1] <= #TCQ 1'b1; end // Read data offset value for all DQS in a Bank always @(posedge clk) begin if (rst) begin for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1; end always @(posedge clk) begin if (rst) begin for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && //(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1; end //***************************************************************************** // One I/O Bank Interface //***************************************************************************** end else begin // One I/O Bank Interface // Read data offset value for all DQS in Bank0 always @(posedge clk) begin if (rst) begin for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop rd_byte_data_offset[l] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r] <= #TCQ rd_byte_data_offset[rnk_cnt_r] - 1; end // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted even with 3 dqfound retries always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end end endgenerate always @(posedge clk) begin if (rst) pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}}; else if (rst_dqs_find) pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}}; else pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r; end // Final read data offset value to be used during write calibration and // normal operation generate genvar i; genvar j; for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop reg [5:0] final_do_cand [RANKS-1:0]; // combinatorially select the candidate offset for the bank // indexed by final_do_index if (HIGHEST_BANK == 3) begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; 3'b010: final_do_cand[i] = final_data_offset[i][17:12]; default: final_do_cand[i] = 'd0; endcase end end else if (HIGHEST_BANK == 2) begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; 3'b010: final_do_cand[i] = 'd0; default: final_do_cand[i] = 'd0; endcase end end else begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = 'd0; 3'b010: final_do_cand[i] = 'd0; default: final_do_cand[i] = 'd0; endcase end end always @(posedge clk) begin if (rst) final_do_max[i] <= #TCQ 0; else begin final_do_max[i] <= #TCQ final_do_max[i]; // default case (final_do_index[i]) 3'b000: if ( | DATA_PRESENT[3:0]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; 3'b001: if ( | DATA_PRESENT[7:4]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; 3'b010: if ( | DATA_PRESENT[11:8]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; default: final_do_max[i] <= #TCQ final_do_max[i]; endcase end end always @(posedge clk) if (rst) begin final_do_index[i] <= #TCQ 0; end else begin final_do_index[i] <= #TCQ final_do_index[i] + 1; end for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop always @(posedge clk) begin if (rst) begin final_data_offset[i][6*j+:6] <= #TCQ 'b0; end else begin //if (dqsfound_retry[j]) // final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; //else if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; if (CWL_M % 2) // odd latency CAS slot 1 final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1; else // even latency CAS slot 0 final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; end end else if (init_dqsfound_done_r5 ) begin if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i]; final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i]; end end end end end end endgenerate // Error generation in case pi_found_dqs signal from Phaser_IN // is not asserted when a common rddata_offset value is used always @(posedge clk) begin pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r; end endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_dqs_found_cal.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Read leveling calibration logic // NOTES: // 1. Phaser_In DQSFOUND calibration //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $ **$Date: 2011/06/02 08:35:08 $ **$Author: **$Revision: **$Source: ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_dqs_found_cal # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter nCL = 5, // Read CAS latency parameter AL = "0", parameter nCWL = 5, // Write CAS latency parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" parameter RANKS = 1, // # of memory ranks in the system parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate parameter N_CTL_LANES = 3, // Number of control byte lanes parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl) parameter HIGHEST_BANK = 3, // Sum of I/O Banks parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf ) ( input clk, input rst, input dqsfound_retry, // From phy_init input pi_dqs_found_start, input detect_pi_found_dqs, input prech_done, // DQSFOUND per Phaser_IN input [HIGHEST_LANE-1:0] pi_dqs_found_lanes, output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal, // To phy_init output [5:0] rd_data_offset_0, output [5:0] rd_data_offset_1, output [5:0] rd_data_offset_2, output pi_dqs_found_rank_done, output pi_dqs_found_done, output reg pi_dqs_found_err, output [6*RANKS-1:0] rd_data_offset_ranks_0, output [6*RANKS-1:0] rd_data_offset_ranks_1, output [6*RANKS-1:0] rd_data_offset_ranks_2, output reg dqsfound_retry_done, output reg dqs_found_prech_req, //To MC output [6*RANKS-1:0] rd_data_offset_ranks_mc_0, output [6*RANKS-1:0] rd_data_offset_ranks_mc_1, output [6*RANKS-1:0] rd_data_offset_ranks_mc_2, input [8:0] po_counter_read_val, output rd_data_offset_cal_done, output fine_adjust_done, output [N_CTL_LANES-1:0] fine_adjust_lane_cnt, output reg ck_po_stg2_f_indec, output reg ck_po_stg2_f_en, output [255:0] dbg_dqs_found_cal ); // For non-zero AL values localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; // Adding the register dimm latency to write latency localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; // Added to reduce simulation time localparam LATENCY_FACTOR = 13; localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1; localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]), (DATA_CTL_B4[2] & BYTE_LANES_B4[2]), (DATA_CTL_B4[1] & BYTE_LANES_B4[1]), (DATA_CTL_B4[0] & BYTE_LANES_B4[0]), (DATA_CTL_B3[3] & BYTE_LANES_B3[3]), (DATA_CTL_B3[2] & BYTE_LANES_B3[2]), (DATA_CTL_B3[1] & BYTE_LANES_B3[1]), (DATA_CTL_B3[0] & BYTE_LANES_B3[0]), (DATA_CTL_B2[3] & BYTE_LANES_B2[3]), (DATA_CTL_B2[2] & BYTE_LANES_B2[2]), (DATA_CTL_B2[1] & BYTE_LANES_B2[1]), (DATA_CTL_B2[0] & BYTE_LANES_B2[0]), (DATA_CTL_B1[3] & BYTE_LANES_B1[3]), (DATA_CTL_B1[2] & BYTE_LANES_B1[2]), (DATA_CTL_B1[1] & BYTE_LANES_B1[1]), (DATA_CTL_B1[0] & BYTE_LANES_B1[0]), (DATA_CTL_B0[3] & BYTE_LANES_B0[3]), (DATA_CTL_B0[2] & BYTE_LANES_B0[2]), (DATA_CTL_B0[1] & BYTE_LANES_B0[1]), (DATA_CTL_B0[0] & BYTE_LANES_B0[0])}; localparam FINE_ADJ_IDLE = 4'h0; localparam RST_POSTWAIT = 4'h1; localparam RST_POSTWAIT1 = 4'h2; localparam RST_WAIT = 4'h3; localparam FINE_ADJ_INIT = 4'h4; localparam FINE_INC = 4'h5; localparam FINE_INC_WAIT = 4'h6; localparam FINE_INC_PREWAIT = 4'h7; localparam DETECT_PREWAIT = 4'h8; localparam DETECT_DQSFOUND = 4'h9; localparam PRECH_WAIT = 4'hA; localparam FINE_DEC = 4'hB; localparam FINE_DEC_WAIT = 4'hC; localparam FINE_DEC_PREWAIT = 4'hD; localparam FINAL_WAIT = 4'hE; localparam FINE_ADJ_DONE = 4'hF; integer k,l,m,n,p,q,r,s; reg dqs_found_start_r; reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1]; reg rank_done_r; reg rank_done_r1; reg dqs_found_done_r; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2; (* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3; reg init_dqsfound_done_r; reg init_dqsfound_done_r1; reg init_dqsfound_done_r2; reg init_dqsfound_done_r3; reg init_dqsfound_done_r4; reg init_dqsfound_done_r5; reg [1:0] rnk_cnt_r; reg [2:0 ] final_do_index[0:RANKS-1]; reg [5:0 ] final_do_max[0:RANKS-1]; reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1]; reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1]; reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r; reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1; reg [10*HIGHEST_BANK-1:0] retry_cnt; reg dqsfound_retry_r1; wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int; reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank; reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r; reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank; reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r; reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r; // CK/Control byte lanes fine adjust stage reg fine_adjust; reg [N_CTL_LANES-1:0] ctl_lane_cnt; reg [3:0] fine_adj_state_r; reg fine_adjust_done_r; reg rst_dqs_find; reg rst_dqs_find_r1; reg rst_dqs_find_r2; reg [5:0] init_dec_cnt; reg [5:0] dec_cnt; reg [5:0] inc_cnt; reg final_dec_done; reg init_dec_done; reg first_fail_detect; reg second_fail_detect; reg [5:0] first_fail_taps; reg [5:0] second_fail_taps; reg [5:0] stable_pass_cnt; reg [3:0] detect_rd_cnt; //*************************************************************************** // Debug signals // //*************************************************************************** assign dbg_dqs_found_cal[5:0] = first_fail_taps; assign dbg_dqs_found_cal[11:6] = second_fail_taps; assign dbg_dqs_found_cal[12] = first_fail_detect; assign dbg_dqs_found_cal[13] = second_fail_detect; assign dbg_dqs_found_cal[14] = fine_adjust_done_r; assign pi_dqs_found_rank_done = rank_done_r; assign pi_dqs_found_done = dqs_found_done_r; generate genvar rnk_cnt; if (HIGHEST_BANK == 3) begin // Three Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12]; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12]; end end else if (HIGHEST_BANK == 2) begin // Two Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6]; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6]; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; end end else begin // Single Bank Interface for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0]; assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0]; assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0; assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0; end end endgenerate // final_data_offset is used during write calibration and during // normal operation. One rd_data_offset value per rank for entire // interface generate if (HIGHEST_BANK == 3) begin // Three I/O Bank interface assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : final_data_offset[rnk_cnt_r][6+:6]; assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] : final_data_offset[rnk_cnt_r][12+:6]; end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] : final_data_offset[rnk_cnt_r][6+:6]; assign rd_data_offset_2 = 'd0; end else begin assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] : final_data_offset[rnk_cnt_r][0+:6]; assign rd_data_offset_1 = 'd0; assign rd_data_offset_2 = 'd0; end endgenerate assign rd_data_offset_cal_done = init_dqsfound_done_r; assign fine_adjust_lane_cnt = ctl_lane_cnt; //************************************************************************** // DQSFOUND all and any generation // pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are // asserted // pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx // is asserted //************************************************************************** generate if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12)) assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3; else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11)) assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3}; else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10)) assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3}; else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9)) assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3}; endgenerate always @(posedge clk) begin if (rst) begin for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found pi_dqs_found_all_bank[k] <= #TCQ 'b0; pi_dqs_found_any_bank[k] <= #TCQ 'b0; end end else if (pi_dqs_found_start) begin for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) & (!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) & (!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) & (!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]); pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) | (DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) | (DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) | (DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]); end end end always @(posedge clk) begin pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank; pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank; end //***************************************************************************** // Counter to increase number of 4 back-to-back reads per rd_data_offset and // per CK/A/C tap value //***************************************************************************** always @(posedge clk) begin if (rst || (detect_rd_cnt == 'd0)) detect_rd_cnt <= #TCQ NUM_READS; else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0)) detect_rd_cnt <= #TCQ detect_rd_cnt - 1; end //************************************************************************** // Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls // //************************************************************************** assign fine_adjust_done = fine_adjust_done_r; always @(posedge clk) begin rst_dqs_find_r1 <= #TCQ rst_dqs_find; rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1; end always @(posedge clk) begin if(rst)begin fine_adjust <= #TCQ 1'b0; ctl_lane_cnt <= #TCQ 'd0; fine_adj_state_r <= #TCQ FINE_ADJ_IDLE; fine_adjust_done_r <= #TCQ 1'b0; ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; rst_dqs_find <= #TCQ 1'b0; init_dec_cnt <= #TCQ 'd31; dec_cnt <= #TCQ 'd0; inc_cnt <= #TCQ 'd0; init_dec_done <= #TCQ 1'b0; final_dec_done <= #TCQ 1'b0; first_fail_detect <= #TCQ 1'b0; second_fail_detect <= #TCQ 1'b0; first_fail_taps <= #TCQ 'd0; second_fail_taps <= #TCQ 'd0; stable_pass_cnt <= #TCQ 'd0; dqs_found_prech_req<= #TCQ 1'b0; end else begin case (fine_adj_state_r) FINE_ADJ_IDLE: begin if (init_dqsfound_done_r5) begin if (SIM_CAL_OPTION == "FAST_CAL") begin fine_adjust <= #TCQ 1'b1; fine_adj_state_r <= #TCQ FINE_ADJ_DONE; rst_dqs_find <= #TCQ 1'b0; end else begin fine_adjust <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; rst_dqs_find <= #TCQ 1'b1; end end end RST_WAIT: begin if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin rst_dqs_find <= #TCQ 1'b0; if (|init_dec_cnt) fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; else if (final_dec_done) fine_adj_state_r <= #TCQ FINE_ADJ_DONE; else fine_adj_state_r <= #TCQ RST_POSTWAIT; end end RST_POSTWAIT: begin fine_adj_state_r <= #TCQ RST_POSTWAIT1; end RST_POSTWAIT1: begin fine_adj_state_r <= #TCQ FINE_ADJ_INIT; end FINE_ADJ_INIT: begin //if (detect_pi_found_dqs && (inc_cnt < 'd63)) fine_adj_state_r <= #TCQ FINE_INC; end FINE_INC: begin fine_adj_state_r <= #TCQ FINE_INC_WAIT; ck_po_stg2_f_indec <= #TCQ 1'b1; ck_po_stg2_f_en <= #TCQ 1'b1; if (ctl_lane_cnt == N_CTL_LANES-1) inc_cnt <= #TCQ inc_cnt + 1; end FINE_INC_WAIT: begin ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; if (ctl_lane_cnt != N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; fine_adj_state_r <= #TCQ FINE_INC_PREWAIT; end else if (ctl_lane_cnt == N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ 'd0; fine_adj_state_r <= #TCQ DETECT_PREWAIT; end end FINE_INC_PREWAIT: begin fine_adj_state_r <= #TCQ FINE_INC; end DETECT_PREWAIT: begin if (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) fine_adj_state_r <= #TCQ DETECT_DQSFOUND; else fine_adj_state_r <= #TCQ DETECT_PREWAIT; end DETECT_DQSFOUND: begin if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin stable_pass_cnt <= #TCQ 'd0; if (~first_fail_detect && (inc_cnt == 'd63)) begin // First failing tap detected at 63 taps // then decrement to 31 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ 'd32; end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin // First failing tap detected at greater than 30 taps // then stop looking for second edge and decrement first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ (inc_cnt>>1) + 1; end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin // First failing tap detected, continue incrementing // until either second failing tap detected or 63 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; rst_dqs_find <= #TCQ 1'b1; if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else fine_adj_state_r <= #TCQ RST_WAIT; end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin // Consecutive 30 taps of passing region was not found // continue incrementing first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; rst_dqs_find <= #TCQ 1'b1; if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else fine_adj_state_r <= #TCQ RST_WAIT; end else if (first_fail_detect && (inc_cnt == 'd63)) begin if (stable_pass_cnt < 'd30) begin // Consecutive 30 taps of passing region was not found // from tap 0 to 63 so decrement back to 31 first_fail_detect <= #TCQ 1'b1; first_fail_taps <= #TCQ inc_cnt; fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ 'd32; end else begin // Consecutive 30 taps of passing region was found // between first_fail_taps and 63 fine_adj_state_r <= #TCQ FINE_DEC; dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); end end else begin // Second failing tap detected, decrement to center of // failing taps second_fail_detect <= #TCQ 1'b1; second_fail_taps <= #TCQ inc_cnt; dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); fine_adj_state_r <= #TCQ FINE_DEC; end end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin stable_pass_cnt <= #TCQ stable_pass_cnt + 1; if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin dqs_found_prech_req <= #TCQ 1'b1; fine_adj_state_r <= #TCQ PRECH_WAIT; end else if (inc_cnt < 'd63) begin rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end else begin fine_adj_state_r <= #TCQ FINE_DEC; if (~first_fail_detect || (first_fail_taps > 'd33)) // No failing taps detected, decrement by 31 dec_cnt <= #TCQ 'd32; //else if (first_fail_detect && (stable_pass_cnt > 'd28)) // // First failing tap detected between 0 and 34 // // decrement midpoint between 63 and failing tap // dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); else // First failing tap detected // decrement to midpoint between 63 and failing tap dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1); end end end PRECH_WAIT: begin if (prech_done) begin dqs_found_prech_req <= #TCQ 1'b0; rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end end FINE_DEC: begin fine_adj_state_r <= #TCQ FINE_DEC_WAIT; ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b1; if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0)) init_dec_cnt <= #TCQ init_dec_cnt - 1; else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0)) dec_cnt <= #TCQ dec_cnt - 1; end FINE_DEC_WAIT: begin ck_po_stg2_f_indec <= #TCQ 1'b0; ck_po_stg2_f_en <= #TCQ 1'b0; if (ctl_lane_cnt != N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1; fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; end else if (ctl_lane_cnt == N_CTL_LANES-1) begin ctl_lane_cnt <= #TCQ 'd0; if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0)) fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT; else begin fine_adj_state_r <= #TCQ FINAL_WAIT; if ((init_dec_cnt == 'd0) && ~init_dec_done) init_dec_done <= #TCQ 1'b1; else final_dec_done <= #TCQ 1'b1; end end end FINE_DEC_PREWAIT: begin fine_adj_state_r <= #TCQ FINE_DEC; end FINAL_WAIT: begin rst_dqs_find <= #TCQ 1'b1; fine_adj_state_r <= #TCQ RST_WAIT; end FINE_ADJ_DONE: begin if (&pi_dqs_found_all_bank) begin fine_adjust_done_r <= #TCQ 1'b1; rst_dqs_find <= #TCQ 1'b0; fine_adj_state_r <= #TCQ FINE_ADJ_DONE; end end endcase end end //***************************************************************************** always@(posedge clk) dqs_found_start_r <= #TCQ pi_dqs_found_start; always @(posedge clk) begin if (rst) rnk_cnt_r <= #TCQ 2'b00; else if (init_dqsfound_done_r) rnk_cnt_r <= #TCQ rnk_cnt_r; else if (rank_done_r) rnk_cnt_r <= #TCQ rnk_cnt_r + 1; end //***************************************************************** // Read data_offset calibration done signal //***************************************************************** always @(posedge clk) begin if (rst || (|pi_rst_stg1_cal_r)) init_dqsfound_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank) begin if (rnk_cnt_r == RANKS-1) init_dqsfound_done_r <= #TCQ 1'b1; else init_dqsfound_done_r <= #TCQ 1'b0; end end always @(posedge clk) begin if (rst || (init_dqsfound_done_r && (rnk_cnt_r == RANKS-1))) rank_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r)) rank_done_r <= #TCQ 1'b1; else rank_done_r <= #TCQ 1'b0; end always @(posedge clk) begin pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes; pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1; pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2; init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r; init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1; init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2; init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3; init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4; rank_done_r1 <= #TCQ rank_done_r; dqsfound_retry_r1 <= #TCQ dqsfound_retry; end always @(posedge clk) begin if (rst) dqs_found_done_r <= #TCQ 1'b0; else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 && (fine_adj_state_r == FINE_ADJ_DONE)) dqs_found_done_r <= #TCQ 1'b1; else dqs_found_done_r <= #TCQ 1'b0; end generate if (HIGHEST_BANK == 3) begin // Three I/O Bank interface // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[1]) || (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust) pi_rst_stg1_cal_r[2] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[2]) || (pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) || (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[2] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[2]) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[10+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[1]) retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; else retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[20+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[2]) retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1; else retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[1] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[2] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[2] <= #TCQ 1'b1; end // Read data offset value for all DQS in a Bank always @(posedge clk) begin if (rst) begin for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1; end always @(posedge clk) begin if (rst) begin for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && //(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1; end always @(posedge clk) begin if (rst) begin for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] && //(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] - 1; end //***************************************************************************** // Two I/O Bank Interface //***************************************************************************** end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust) pi_rst_stg1_cal_r[1] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[1]) || (pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) || (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[1] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[10+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[1]) retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1; else retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) pi_dqs_found_err_r[1] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[1] <= #TCQ 1'b1; end // Read data offset value for all DQS in a Bank always @(posedge clk) begin if (rst) begin for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1; end always @(posedge clk) begin if (rst) begin for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] && //(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1; end //***************************************************************************** // One I/O Bank Interface //***************************************************************************** end else begin // One I/O Bank Interface // Read data offset value for all DQS in Bank0 always @(posedge clk) begin if (rst) begin for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop rd_byte_data_offset[l] <= #TCQ nCL + nAL + LATENCY_FACTOR; end end else if ((rank_done_r1 && ~init_dqsfound_done_r) || (rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL - 1))) rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL + LATENCY_FACTOR; else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] && //(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL -1)) && (detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust) rd_byte_data_offset[rnk_cnt_r] <= #TCQ rd_byte_data_offset[rnk_cnt_r] - 1; end // Reset read data offset calibration in all DQS Phaser_INs // in a Bank after the read data offset value for a rank is determined // or if within a Bank DQSFOUND is not asserted for all DQSs always @(posedge clk) begin if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust) pi_rst_stg1_cal_r[0] <= #TCQ 1'b0; else if ((pi_dqs_found_start && ~dqs_found_start_r) || //(dqsfound_retry[0]) || (pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) || (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_rst_stg1_cal_r[0] <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || fine_adjust) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; else if (pi_rst_stg1_cal_r[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1; else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0; end //***************************************************************************** // Retry counter to track number of DQSFOUND retries //***************************************************************************** always @(posedge clk) begin if (rst || rank_done_r) retry_cnt[0+:10] <= #TCQ 'b0; else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) && ~pi_dqs_found_all_bank[0]) retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1; else retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10]; end // Error generation in case pi_dqs_found_all_bank // is not asserted even with 3 dqfound retries always @(posedge clk) begin if (rst) pi_dqs_found_err_r[0] <= #TCQ 1'b0; else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) && (rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1))) pi_dqs_found_err_r[0] <= #TCQ 1'b1; end end endgenerate always @(posedge clk) begin if (rst) pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}}; else if (rst_dqs_find) pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}}; else pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r; end // Final read data offset value to be used during write calibration and // normal operation generate genvar i; genvar j; for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop reg [5:0] final_do_cand [RANKS-1:0]; // combinatorially select the candidate offset for the bank // indexed by final_do_index if (HIGHEST_BANK == 3) begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; 3'b010: final_do_cand[i] = final_data_offset[i][17:12]; default: final_do_cand[i] = 'd0; endcase end end else if (HIGHEST_BANK == 2) begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = final_data_offset[i][11:6]; 3'b010: final_do_cand[i] = 'd0; default: final_do_cand[i] = 'd0; endcase end end else begin always @(*) begin case (final_do_index[i]) 3'b000: final_do_cand[i] = final_data_offset[i][5:0]; 3'b001: final_do_cand[i] = 'd0; 3'b010: final_do_cand[i] = 'd0; default: final_do_cand[i] = 'd0; endcase end end always @(posedge clk) begin if (rst) final_do_max[i] <= #TCQ 0; else begin final_do_max[i] <= #TCQ final_do_max[i]; // default case (final_do_index[i]) 3'b000: if ( | DATA_PRESENT[3:0]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; 3'b001: if ( | DATA_PRESENT[7:4]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; 3'b010: if ( | DATA_PRESENT[11:8]) if (final_do_max[i] < final_do_cand[i]) if (CWL_M % 2) // odd latency CAS slot 1 final_do_max[i] <= #TCQ final_do_cand[i] - 1; else final_do_max[i] <= #TCQ final_do_cand[i]; default: final_do_max[i] <= #TCQ final_do_max[i]; endcase end end always @(posedge clk) if (rst) begin final_do_index[i] <= #TCQ 0; end else begin final_do_index[i] <= #TCQ final_do_index[i] + 1; end for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop always @(posedge clk) begin if (rst) begin final_data_offset[i][6*j+:6] <= #TCQ 'b0; end else begin //if (dqsfound_retry[j]) // final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; //else if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; if (CWL_M % 2) // odd latency CAS slot 1 final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1; else // even latency CAS slot 0 final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6]; end end else if (init_dqsfound_done_r5 ) begin if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i]; final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i]; end end end end end end endgenerate // Error generation in case pi_found_dqs signal from Phaser_IN // is not asserted when a common rddata_offset value is used always @(posedge clk) begin pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r; end endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : rank_common.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Block for logic common to all rank machines. Contains // a clock prescaler, and arbiters for refresh and periodic // read functions. `timescale 1 ps / 1 ps module mig_7series_v2_3_rank_common # ( parameter TCQ = 100, parameter DRAM_TYPE = "DDR3", parameter MAINT_PRESCALER_DIV = 40, parameter nBANK_MACHS = 4, parameter nCKESR = 4, parameter nCK_PER_CLK = 2, parameter PERIODIC_RD_TIMER_DIV = 20, parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter REFRESH_TIMER_DIV = 39, parameter ZQ_TIMER_DIV = 640000 ) (/*AUTOARG*/ // Outputs maint_prescaler_tick_r, refresh_tick, maint_zq_r, maint_sre_r, maint_srx_r, maint_req_r, maint_rank_r, clear_periodic_rd_request, periodic_rd_r, periodic_rd_rank_r, app_ref_ack, app_zq_ack, app_sr_active, maint_ref_zq_wip, // Inputs clk, rst, init_calib_complete, app_ref_req, app_zq_req, app_sr_req, insert_maint_r1, refresh_request, maint_wip_r, slot_0_present, slot_1_present, periodic_rd_request, periodic_rd_ack_r ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 input clk; input rst; // Maintenance and periodic read prescaler. Nominally 200 nS. localparam ONE = 1; localparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1); input init_calib_complete; reg maint_prescaler_tick_r_lcl; generate begin : maint_prescaler reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r; reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns; wire maint_prescaler_tick_ns = (maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]); always @(/*AS*/init_calib_complete or maint_prescaler_r or maint_prescaler_tick_ns) begin maint_prescaler_ns = maint_prescaler_r; if (~init_calib_complete || maint_prescaler_tick_ns) maint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0]; else if (|maint_prescaler_r) maint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0]; end always @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns; always @(posedge clk) maint_prescaler_tick_r_lcl <= #TCQ maint_prescaler_tick_ns; end endgenerate output wire maint_prescaler_tick_r; assign maint_prescaler_tick_r = maint_prescaler_tick_r_lcl; // Refresh timebase. Nominically 7800 nS. localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER_DIV + /*idle*/ 1); wire refresh_tick_lcl; generate begin : refresh_timer reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_r; reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_ns; always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl or refresh_tick_lcl or refresh_timer_r) begin refresh_timer_ns = refresh_timer_r; if (~init_calib_complete || refresh_tick_lcl) refresh_timer_ns = REFRESH_TIMER_DIV[REFRESH_TIMER_WIDTH-1:0]; else if (|refresh_timer_r && maint_prescaler_tick_r_lcl) refresh_timer_ns = refresh_timer_r - ONE[REFRESH_TIMER_WIDTH-1:0]; end always @(posedge clk) refresh_timer_r <= #TCQ refresh_timer_ns; assign refresh_tick_lcl = (refresh_timer_r == ONE[REFRESH_TIMER_WIDTH-1:0]) && maint_prescaler_tick_r_lcl; end endgenerate output wire refresh_tick; assign refresh_tick = refresh_tick_lcl; // ZQ timebase. Nominally 128 mS localparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1); input app_zq_req; input insert_maint_r1; reg maint_zq_r_lcl; reg zq_request = 1'b0; generate if (DRAM_TYPE == "DDR3") begin : zq_cntrl reg zq_tick = 1'b0; if (ZQ_TIMER_DIV !=0) begin : zq_timer reg [ZQ_TIMER_WIDTH-1:0] zq_timer_r; reg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns; always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl or zq_tick or zq_timer_r) begin zq_timer_ns = zq_timer_r; if (~init_calib_complete || zq_tick) zq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0]; else if (|zq_timer_r && maint_prescaler_tick_r_lcl) zq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0]; end always @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns; always @(/*AS*/maint_prescaler_tick_r_lcl or zq_timer_r) zq_tick = (zq_timer_r == ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick_r_lcl); end // zq_timer // ZQ request. Set request with timer tick, and when exiting PHY init. Never // request if ZQ_TIMER_DIV == 0. begin : zq_request_logic wire zq_clears_zq_request = insert_maint_r1 && maint_zq_r_lcl; reg zq_request_r; wire zq_request_ns = ~rst && (DRAM_TYPE == "DDR3") && ((~init_calib_complete && (ZQ_TIMER_DIV != 0)) || (zq_request_r && ~zq_clears_zq_request) || zq_tick || (app_zq_req && init_calib_complete)); always @(posedge clk) zq_request_r <= #TCQ zq_request_ns; always @(/*AS*/init_calib_complete or zq_request_r) zq_request = init_calib_complete && zq_request_r; end // zq_request_logic end endgenerate // Self-refresh control localparam nCKESR_CLKS = (nCKESR / nCK_PER_CLK) + (nCKESR % nCK_PER_CLK ? 1 : 0); localparam CKESR_TIMER_WIDTH = clogb2(nCKESR_CLKS + 1); input app_sr_req; reg maint_sre_r_lcl; reg maint_srx_r_lcl; reg sre_request = 1'b0; wire inhbt_srx; generate begin : sr_cntrl // SRE request. Set request with user request. begin : sre_request_logic reg sre_request_r; wire sre_clears_sre_request = insert_maint_r1 && maint_sre_r_lcl; wire sre_request_ns = ~rst && ((sre_request_r && ~sre_clears_sre_request) || (app_sr_req && init_calib_complete && ~maint_sre_r_lcl)); always @(posedge clk) sre_request_r <= #TCQ sre_request_ns; always @(init_calib_complete or sre_request_r) sre_request = init_calib_complete && sre_request_r; end // sre_request_logic // CKESR timer: Self-Refresh must be maintained for a minimum of tCKESR begin : ckesr_timer reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_r = {CKESR_TIMER_WIDTH{1'b0}}; reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_ns = {CKESR_TIMER_WIDTH{1'b0}}; always @(insert_maint_r1 or ckesr_timer_r or maint_sre_r_lcl) begin ckesr_timer_ns = ckesr_timer_r; if (insert_maint_r1 && maint_sre_r_lcl) ckesr_timer_ns = nCKESR_CLKS[CKESR_TIMER_WIDTH-1:0]; else if(|ckesr_timer_r) ckesr_timer_ns = ckesr_timer_r - ONE[CKESR_TIMER_WIDTH-1:0]; end always @(posedge clk) ckesr_timer_r <= #TCQ ckesr_timer_ns; assign inhbt_srx = |ckesr_timer_r; end // ckesr_timer end endgenerate // DRAM maintenance operations of refresh and ZQ calibration, and self-refresh // DRAM maintenance operations and self-refresh have their own channel in the // queue. There is also a single, very simple bank machine // dedicated to these operations. Its assumed that the // maintenance operations can be completed quickly enough // to avoid any queuing. // // ZQ, refresh and self-refresh requests share a channel into controller. // Self-refresh is appended to the uppermost bit of the request bus and ZQ is // appended just below that. input[RANKS-1:0] refresh_request; input maint_wip_r; reg maint_req_r_lcl; reg [RANK_WIDTH-1:0] maint_rank_r_lcl; input [7:0] slot_0_present; input [7:0] slot_1_present; generate begin : maintenance_request // Maintenance request pipeline. reg upd_last_master_r; reg new_maint_rank_r; wire maint_busy = upd_last_master_r || new_maint_rank_r || maint_req_r_lcl || maint_wip_r; wire [RANKS+1:0] maint_request = {sre_request, zq_request, refresh_request[RANKS-1:0]}; wire upd_last_master_ns = |maint_request && ~maint_busy; always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns; always @(posedge clk) new_maint_rank_r <= #TCQ upd_last_master_r; always @(posedge clk) maint_req_r_lcl <= #TCQ new_maint_rank_r; // Arbitrate maintenance requests. wire [RANKS+1:0] maint_grant_ns; wire [RANKS+1:0] maint_grant_r; mig_7series_v2_3_round_robin_arb # (.WIDTH (RANKS+2)) maint_arb0 (.grant_ns (maint_grant_ns), .grant_r (maint_grant_r), .upd_last_master (upd_last_master_r), .current_master (maint_grant_r), .req (maint_request), .disable_grant (1'b0), /*AUTOINST*/ // Inputs .clk (clk), .rst (rst)); // Look at arbitration results. Decide if ZQ, refresh or self-refresh. // If refresh select the maintenance rank from the winning rank controller. // If ZQ or self-refresh, generate a sequence of rank numbers corresponding to // slots populated maint_rank_r is not used for comparisons in the queue for ZQ // or self-refresh requests. The bank machine will enable CS for the number of // states equal to the the number of occupied slots. This will produce a // command to every occupied slot, but not in any particular order. wire [7:0] present = slot_0_present | slot_1_present; integer i; reg [RANK_WIDTH-1:0] maint_rank_ns; wire maint_zq_ns = ~rst && (upd_last_master_r ? maint_grant_r[RANKS] : maint_zq_r_lcl); wire maint_srx_ns = ~rst && (maint_sre_r_lcl ? ~app_sr_req & ~inhbt_srx : maint_srx_r_lcl && upd_last_master_r ? maint_grant_r[RANKS+1] : maint_srx_r_lcl); wire maint_sre_ns = ~rst && (upd_last_master_r ? maint_grant_r[RANKS+1] : maint_sre_r_lcl && ~maint_srx_ns); always @(/*AS*/maint_grant_r or maint_rank_r_lcl or maint_zq_ns or maint_sre_ns or maint_srx_ns or present or rst or upd_last_master_r) begin if (rst) maint_rank_ns = {RANK_WIDTH{1'b0}}; else begin maint_rank_ns = maint_rank_r_lcl; if (maint_zq_ns || maint_sre_ns || maint_srx_ns) begin maint_rank_ns = maint_rank_r_lcl + ONE[RANK_WIDTH-1:0]; for (i=0; i<8; i=i+1) if (~present[maint_rank_ns]) maint_rank_ns = maint_rank_ns + ONE[RANK_WIDTH-1:0]; end else if (upd_last_master_r) for (i=0; i<RANKS; i=i+1) if (maint_grant_r[i]) maint_rank_ns = i[RANK_WIDTH-1:0]; end end always @(posedge clk) maint_rank_r_lcl <= #TCQ maint_rank_ns; always @(posedge clk) maint_zq_r_lcl <= #TCQ maint_zq_ns; always @(posedge clk) maint_sre_r_lcl <= #TCQ maint_sre_ns; always @(posedge clk) maint_srx_r_lcl <= #TCQ maint_srx_ns; end // block: maintenance_request endgenerate output wire maint_zq_r; assign maint_zq_r = maint_zq_r_lcl; output wire maint_sre_r; assign maint_sre_r = maint_sre_r_lcl; output wire maint_srx_r; assign maint_srx_r = maint_srx_r_lcl; output wire maint_req_r; assign maint_req_r = maint_req_r_lcl; output wire [RANK_WIDTH-1:0] maint_rank_r; assign maint_rank_r = maint_rank_r_lcl; // Indicate whether self-refresh is active or not. output app_sr_active; reg app_sr_active_r; wire app_sr_active_ns = insert_maint_r1 ? maint_sre_r && ~maint_srx_r : app_sr_active_r; always @(posedge clk) app_sr_active_r <= #TCQ app_sr_active_ns; assign app_sr_active = app_sr_active_r; // Acknowledge user REF and ZQ Requests input app_ref_req; output app_ref_ack; wire app_ref_ack_ns; wire app_ref_ns; reg app_ref_ack_r = 1'b0; reg app_ref_r = 1'b0; assign app_ref_ns = init_calib_complete && (app_ref_req || app_ref_r && |refresh_request); assign app_ref_ack_ns = app_ref_r && ~|refresh_request; always @(posedge clk) app_ref_r <= #TCQ app_ref_ns; always @(posedge clk) app_ref_ack_r <= #TCQ app_ref_ack_ns; assign app_ref_ack = app_ref_ack_r; output app_zq_ack; wire app_zq_ack_ns; wire app_zq_ns; reg app_zq_ack_r = 1'b0; reg app_zq_r = 1'b0; assign app_zq_ns = init_calib_complete && (app_zq_req || app_zq_r && zq_request); assign app_zq_ack_ns = app_zq_r && ~zq_request; always @(posedge clk) app_zq_r <= #TCQ app_zq_ns; always @(posedge clk) app_zq_ack_r <= #TCQ app_zq_ack_ns; assign app_zq_ack = app_zq_ack_r; // Periodic reads to maintain PHY alignment. // Demand insertion of periodic read as soon as // possible. Since the is a single rank, bank compare mechanism // must be used, periodic reads must be forced in at the // expense of not accepting a normal request. input [RANKS-1:0] periodic_rd_request; reg periodic_rd_r_lcl; reg [RANK_WIDTH-1:0] periodic_rd_rank_r_lcl; input periodic_rd_ack_r; output wire [RANKS-1:0] clear_periodic_rd_request; output wire periodic_rd_r; output wire [RANK_WIDTH-1:0] periodic_rd_rank_r; generate // This is not needed in 7-Series and should remain disabled if ( PERIODIC_RD_TIMER_DIV != 0 ) begin : periodic_read_request // Maintenance request pipeline. reg periodic_rd_r_cnt; wire int_periodic_rd_ack_r = (periodic_rd_ack_r && periodic_rd_r_cnt); reg upd_last_master_r; wire periodic_rd_busy = upd_last_master_r || periodic_rd_r_lcl; wire upd_last_master_ns = init_calib_complete && (|periodic_rd_request && ~periodic_rd_busy); always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns; wire periodic_rd_ns = init_calib_complete && (upd_last_master_r || (periodic_rd_r_lcl && ~int_periodic_rd_ack_r)); always @(posedge clk) periodic_rd_r_lcl <= #TCQ periodic_rd_ns; always @(posedge clk) begin if (rst) periodic_rd_r_cnt <= #TCQ 1'b0; else if (periodic_rd_r_lcl && periodic_rd_ack_r) periodic_rd_r_cnt <= ~periodic_rd_r_cnt; end // Arbitrate periodic read requests. wire [RANKS-1:0] periodic_rd_grant_ns; reg [RANKS-1:0] periodic_rd_grant_r; mig_7series_v2_3_round_robin_arb # (.WIDTH (RANKS)) periodic_rd_arb0 (.grant_ns (periodic_rd_grant_ns[RANKS-1:0]), .grant_r (), .upd_last_master (upd_last_master_r), .current_master (periodic_rd_grant_r[RANKS-1:0]), .req (periodic_rd_request[RANKS-1:0]), .disable_grant (1'b0), /*AUTOINST*/ // Inputs .clk (clk), .rst (rst)); always @(posedge clk) periodic_rd_grant_r = upd_last_master_ns ? periodic_rd_grant_ns : periodic_rd_grant_r; // Encode and set periodic read rank into periodic_rd_rank_r. integer i; reg [RANK_WIDTH-1:0] periodic_rd_rank_ns; always @(/*AS*/periodic_rd_grant_r or periodic_rd_rank_r_lcl or upd_last_master_r) begin periodic_rd_rank_ns = periodic_rd_rank_r_lcl; if (upd_last_master_r) for (i=0; i<RANKS; i=i+1) if (periodic_rd_grant_r[i]) periodic_rd_rank_ns = i[RANK_WIDTH-1:0]; end always @(posedge clk) periodic_rd_rank_r_lcl <= #TCQ periodic_rd_rank_ns; // Once the request is dropped in the queue, it might be a while before it // emerges. Can't clear the request based on seeing the read issued. // Need to clear the request as soon as its made it into the queue. assign clear_periodic_rd_request = periodic_rd_grant_r & {RANKS{periodic_rd_ack_r}}; assign periodic_rd_r = periodic_rd_r_lcl; assign periodic_rd_rank_r = periodic_rd_rank_r_lcl; end else begin // Disable periodic reads assign clear_periodic_rd_request = {RANKS{1'b0}}; assign periodic_rd_r = 1'b0; assign periodic_rd_rank_r = {RANK_WIDTH{1'b0}}; end // block: periodic_read_request endgenerate // Indicate that a refresh is in progress. The PHY will use this to schedule // tap adjustments during idle bus time reg maint_ref_zq_wip_r = 1'b0; output maint_ref_zq_wip; always @(posedge clk) if(rst) maint_ref_zq_wip_r <= #TCQ 1'b0; else if((zq_request || |refresh_request) && insert_maint_r1) maint_ref_zq_wip_r <= #TCQ 1'b1; else if(~maint_wip_r) maint_ref_zq_wip_r <= #TCQ 1'b0; assign maint_ref_zq_wip = maint_ref_zq_wip_r; endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : rank_common.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Block for logic common to all rank machines. Contains // a clock prescaler, and arbiters for refresh and periodic // read functions. `timescale 1 ps / 1 ps module mig_7series_v2_3_rank_common # ( parameter TCQ = 100, parameter DRAM_TYPE = "DDR3", parameter MAINT_PRESCALER_DIV = 40, parameter nBANK_MACHS = 4, parameter nCKESR = 4, parameter nCK_PER_CLK = 2, parameter PERIODIC_RD_TIMER_DIV = 20, parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter REFRESH_TIMER_DIV = 39, parameter ZQ_TIMER_DIV = 640000 ) (/*AUTOARG*/ // Outputs maint_prescaler_tick_r, refresh_tick, maint_zq_r, maint_sre_r, maint_srx_r, maint_req_r, maint_rank_r, clear_periodic_rd_request, periodic_rd_r, periodic_rd_rank_r, app_ref_ack, app_zq_ack, app_sr_active, maint_ref_zq_wip, // Inputs clk, rst, init_calib_complete, app_ref_req, app_zq_req, app_sr_req, insert_maint_r1, refresh_request, maint_wip_r, slot_0_present, slot_1_present, periodic_rd_request, periodic_rd_ack_r ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 input clk; input rst; // Maintenance and periodic read prescaler. Nominally 200 nS. localparam ONE = 1; localparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1); input init_calib_complete; reg maint_prescaler_tick_r_lcl; generate begin : maint_prescaler reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r; reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns; wire maint_prescaler_tick_ns = (maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]); always @(/*AS*/init_calib_complete or maint_prescaler_r or maint_prescaler_tick_ns) begin maint_prescaler_ns = maint_prescaler_r; if (~init_calib_complete || maint_prescaler_tick_ns) maint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0]; else if (|maint_prescaler_r) maint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0]; end always @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns; always @(posedge clk) maint_prescaler_tick_r_lcl <= #TCQ maint_prescaler_tick_ns; end endgenerate output wire maint_prescaler_tick_r; assign maint_prescaler_tick_r = maint_prescaler_tick_r_lcl; // Refresh timebase. Nominically 7800 nS. localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER_DIV + /*idle*/ 1); wire refresh_tick_lcl; generate begin : refresh_timer reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_r; reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_ns; always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl or refresh_tick_lcl or refresh_timer_r) begin refresh_timer_ns = refresh_timer_r; if (~init_calib_complete || refresh_tick_lcl) refresh_timer_ns = REFRESH_TIMER_DIV[REFRESH_TIMER_WIDTH-1:0]; else if (|refresh_timer_r && maint_prescaler_tick_r_lcl) refresh_timer_ns = refresh_timer_r - ONE[REFRESH_TIMER_WIDTH-1:0]; end always @(posedge clk) refresh_timer_r <= #TCQ refresh_timer_ns; assign refresh_tick_lcl = (refresh_timer_r == ONE[REFRESH_TIMER_WIDTH-1:0]) && maint_prescaler_tick_r_lcl; end endgenerate output wire refresh_tick; assign refresh_tick = refresh_tick_lcl; // ZQ timebase. Nominally 128 mS localparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1); input app_zq_req; input insert_maint_r1; reg maint_zq_r_lcl; reg zq_request = 1'b0; generate if (DRAM_TYPE == "DDR3") begin : zq_cntrl reg zq_tick = 1'b0; if (ZQ_TIMER_DIV !=0) begin : zq_timer reg [ZQ_TIMER_WIDTH-1:0] zq_timer_r; reg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns; always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl or zq_tick or zq_timer_r) begin zq_timer_ns = zq_timer_r; if (~init_calib_complete || zq_tick) zq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0]; else if (|zq_timer_r && maint_prescaler_tick_r_lcl) zq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0]; end always @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns; always @(/*AS*/maint_prescaler_tick_r_lcl or zq_timer_r) zq_tick = (zq_timer_r == ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick_r_lcl); end // zq_timer // ZQ request. Set request with timer tick, and when exiting PHY init. Never // request if ZQ_TIMER_DIV == 0. begin : zq_request_logic wire zq_clears_zq_request = insert_maint_r1 && maint_zq_r_lcl; reg zq_request_r; wire zq_request_ns = ~rst && (DRAM_TYPE == "DDR3") && ((~init_calib_complete && (ZQ_TIMER_DIV != 0)) || (zq_request_r && ~zq_clears_zq_request) || zq_tick || (app_zq_req && init_calib_complete)); always @(posedge clk) zq_request_r <= #TCQ zq_request_ns; always @(/*AS*/init_calib_complete or zq_request_r) zq_request = init_calib_complete && zq_request_r; end // zq_request_logic end endgenerate // Self-refresh control localparam nCKESR_CLKS = (nCKESR / nCK_PER_CLK) + (nCKESR % nCK_PER_CLK ? 1 : 0); localparam CKESR_TIMER_WIDTH = clogb2(nCKESR_CLKS + 1); input app_sr_req; reg maint_sre_r_lcl; reg maint_srx_r_lcl; reg sre_request = 1'b0; wire inhbt_srx; generate begin : sr_cntrl // SRE request. Set request with user request. begin : sre_request_logic reg sre_request_r; wire sre_clears_sre_request = insert_maint_r1 && maint_sre_r_lcl; wire sre_request_ns = ~rst && ((sre_request_r && ~sre_clears_sre_request) || (app_sr_req && init_calib_complete && ~maint_sre_r_lcl)); always @(posedge clk) sre_request_r <= #TCQ sre_request_ns; always @(init_calib_complete or sre_request_r) sre_request = init_calib_complete && sre_request_r; end // sre_request_logic // CKESR timer: Self-Refresh must be maintained for a minimum of tCKESR begin : ckesr_timer reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_r = {CKESR_TIMER_WIDTH{1'b0}}; reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_ns = {CKESR_TIMER_WIDTH{1'b0}}; always @(insert_maint_r1 or ckesr_timer_r or maint_sre_r_lcl) begin ckesr_timer_ns = ckesr_timer_r; if (insert_maint_r1 && maint_sre_r_lcl) ckesr_timer_ns = nCKESR_CLKS[CKESR_TIMER_WIDTH-1:0]; else if(|ckesr_timer_r) ckesr_timer_ns = ckesr_timer_r - ONE[CKESR_TIMER_WIDTH-1:0]; end always @(posedge clk) ckesr_timer_r <= #TCQ ckesr_timer_ns; assign inhbt_srx = |ckesr_timer_r; end // ckesr_timer end endgenerate // DRAM maintenance operations of refresh and ZQ calibration, and self-refresh // DRAM maintenance operations and self-refresh have their own channel in the // queue. There is also a single, very simple bank machine // dedicated to these operations. Its assumed that the // maintenance operations can be completed quickly enough // to avoid any queuing. // // ZQ, refresh and self-refresh requests share a channel into controller. // Self-refresh is appended to the uppermost bit of the request bus and ZQ is // appended just below that. input[RANKS-1:0] refresh_request; input maint_wip_r; reg maint_req_r_lcl; reg [RANK_WIDTH-1:0] maint_rank_r_lcl; input [7:0] slot_0_present; input [7:0] slot_1_present; generate begin : maintenance_request // Maintenance request pipeline. reg upd_last_master_r; reg new_maint_rank_r; wire maint_busy = upd_last_master_r || new_maint_rank_r || maint_req_r_lcl || maint_wip_r; wire [RANKS+1:0] maint_request = {sre_request, zq_request, refresh_request[RANKS-1:0]}; wire upd_last_master_ns = |maint_request && ~maint_busy; always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns; always @(posedge clk) new_maint_rank_r <= #TCQ upd_last_master_r; always @(posedge clk) maint_req_r_lcl <= #TCQ new_maint_rank_r; // Arbitrate maintenance requests. wire [RANKS+1:0] maint_grant_ns; wire [RANKS+1:0] maint_grant_r; mig_7series_v2_3_round_robin_arb # (.WIDTH (RANKS+2)) maint_arb0 (.grant_ns (maint_grant_ns), .grant_r (maint_grant_r), .upd_last_master (upd_last_master_r), .current_master (maint_grant_r), .req (maint_request), .disable_grant (1'b0), /*AUTOINST*/ // Inputs .clk (clk), .rst (rst)); // Look at arbitration results. Decide if ZQ, refresh or self-refresh. // If refresh select the maintenance rank from the winning rank controller. // If ZQ or self-refresh, generate a sequence of rank numbers corresponding to // slots populated maint_rank_r is not used for comparisons in the queue for ZQ // or self-refresh requests. The bank machine will enable CS for the number of // states equal to the the number of occupied slots. This will produce a // command to every occupied slot, but not in any particular order. wire [7:0] present = slot_0_present | slot_1_present; integer i; reg [RANK_WIDTH-1:0] maint_rank_ns; wire maint_zq_ns = ~rst && (upd_last_master_r ? maint_grant_r[RANKS] : maint_zq_r_lcl); wire maint_srx_ns = ~rst && (maint_sre_r_lcl ? ~app_sr_req & ~inhbt_srx : maint_srx_r_lcl && upd_last_master_r ? maint_grant_r[RANKS+1] : maint_srx_r_lcl); wire maint_sre_ns = ~rst && (upd_last_master_r ? maint_grant_r[RANKS+1] : maint_sre_r_lcl && ~maint_srx_ns); always @(/*AS*/maint_grant_r or maint_rank_r_lcl or maint_zq_ns or maint_sre_ns or maint_srx_ns or present or rst or upd_last_master_r) begin if (rst) maint_rank_ns = {RANK_WIDTH{1'b0}}; else begin maint_rank_ns = maint_rank_r_lcl; if (maint_zq_ns || maint_sre_ns || maint_srx_ns) begin maint_rank_ns = maint_rank_r_lcl + ONE[RANK_WIDTH-1:0]; for (i=0; i<8; i=i+1) if (~present[maint_rank_ns]) maint_rank_ns = maint_rank_ns + ONE[RANK_WIDTH-1:0]; end else if (upd_last_master_r) for (i=0; i<RANKS; i=i+1) if (maint_grant_r[i]) maint_rank_ns = i[RANK_WIDTH-1:0]; end end always @(posedge clk) maint_rank_r_lcl <= #TCQ maint_rank_ns; always @(posedge clk) maint_zq_r_lcl <= #TCQ maint_zq_ns; always @(posedge clk) maint_sre_r_lcl <= #TCQ maint_sre_ns; always @(posedge clk) maint_srx_r_lcl <= #TCQ maint_srx_ns; end // block: maintenance_request endgenerate output wire maint_zq_r; assign maint_zq_r = maint_zq_r_lcl; output wire maint_sre_r; assign maint_sre_r = maint_sre_r_lcl; output wire maint_srx_r; assign maint_srx_r = maint_srx_r_lcl; output wire maint_req_r; assign maint_req_r = maint_req_r_lcl; output wire [RANK_WIDTH-1:0] maint_rank_r; assign maint_rank_r = maint_rank_r_lcl; // Indicate whether self-refresh is active or not. output app_sr_active; reg app_sr_active_r; wire app_sr_active_ns = insert_maint_r1 ? maint_sre_r && ~maint_srx_r : app_sr_active_r; always @(posedge clk) app_sr_active_r <= #TCQ app_sr_active_ns; assign app_sr_active = app_sr_active_r; // Acknowledge user REF and ZQ Requests input app_ref_req; output app_ref_ack; wire app_ref_ack_ns; wire app_ref_ns; reg app_ref_ack_r = 1'b0; reg app_ref_r = 1'b0; assign app_ref_ns = init_calib_complete && (app_ref_req || app_ref_r && |refresh_request); assign app_ref_ack_ns = app_ref_r && ~|refresh_request; always @(posedge clk) app_ref_r <= #TCQ app_ref_ns; always @(posedge clk) app_ref_ack_r <= #TCQ app_ref_ack_ns; assign app_ref_ack = app_ref_ack_r; output app_zq_ack; wire app_zq_ack_ns; wire app_zq_ns; reg app_zq_ack_r = 1'b0; reg app_zq_r = 1'b0; assign app_zq_ns = init_calib_complete && (app_zq_req || app_zq_r && zq_request); assign app_zq_ack_ns = app_zq_r && ~zq_request; always @(posedge clk) app_zq_r <= #TCQ app_zq_ns; always @(posedge clk) app_zq_ack_r <= #TCQ app_zq_ack_ns; assign app_zq_ack = app_zq_ack_r; // Periodic reads to maintain PHY alignment. // Demand insertion of periodic read as soon as // possible. Since the is a single rank, bank compare mechanism // must be used, periodic reads must be forced in at the // expense of not accepting a normal request. input [RANKS-1:0] periodic_rd_request; reg periodic_rd_r_lcl; reg [RANK_WIDTH-1:0] periodic_rd_rank_r_lcl; input periodic_rd_ack_r; output wire [RANKS-1:0] clear_periodic_rd_request; output wire periodic_rd_r; output wire [RANK_WIDTH-1:0] periodic_rd_rank_r; generate // This is not needed in 7-Series and should remain disabled if ( PERIODIC_RD_TIMER_DIV != 0 ) begin : periodic_read_request // Maintenance request pipeline. reg periodic_rd_r_cnt; wire int_periodic_rd_ack_r = (periodic_rd_ack_r && periodic_rd_r_cnt); reg upd_last_master_r; wire periodic_rd_busy = upd_last_master_r || periodic_rd_r_lcl; wire upd_last_master_ns = init_calib_complete && (|periodic_rd_request && ~periodic_rd_busy); always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns; wire periodic_rd_ns = init_calib_complete && (upd_last_master_r || (periodic_rd_r_lcl && ~int_periodic_rd_ack_r)); always @(posedge clk) periodic_rd_r_lcl <= #TCQ periodic_rd_ns; always @(posedge clk) begin if (rst) periodic_rd_r_cnt <= #TCQ 1'b0; else if (periodic_rd_r_lcl && periodic_rd_ack_r) periodic_rd_r_cnt <= ~periodic_rd_r_cnt; end // Arbitrate periodic read requests. wire [RANKS-1:0] periodic_rd_grant_ns; reg [RANKS-1:0] periodic_rd_grant_r; mig_7series_v2_3_round_robin_arb # (.WIDTH (RANKS)) periodic_rd_arb0 (.grant_ns (periodic_rd_grant_ns[RANKS-1:0]), .grant_r (), .upd_last_master (upd_last_master_r), .current_master (periodic_rd_grant_r[RANKS-1:0]), .req (periodic_rd_request[RANKS-1:0]), .disable_grant (1'b0), /*AUTOINST*/ // Inputs .clk (clk), .rst (rst)); always @(posedge clk) periodic_rd_grant_r = upd_last_master_ns ? periodic_rd_grant_ns : periodic_rd_grant_r; // Encode and set periodic read rank into periodic_rd_rank_r. integer i; reg [RANK_WIDTH-1:0] periodic_rd_rank_ns; always @(/*AS*/periodic_rd_grant_r or periodic_rd_rank_r_lcl or upd_last_master_r) begin periodic_rd_rank_ns = periodic_rd_rank_r_lcl; if (upd_last_master_r) for (i=0; i<RANKS; i=i+1) if (periodic_rd_grant_r[i]) periodic_rd_rank_ns = i[RANK_WIDTH-1:0]; end always @(posedge clk) periodic_rd_rank_r_lcl <= #TCQ periodic_rd_rank_ns; // Once the request is dropped in the queue, it might be a while before it // emerges. Can't clear the request based on seeing the read issued. // Need to clear the request as soon as its made it into the queue. assign clear_periodic_rd_request = periodic_rd_grant_r & {RANKS{periodic_rd_ack_r}}; assign periodic_rd_r = periodic_rd_r_lcl; assign periodic_rd_rank_r = periodic_rd_rank_r_lcl; end else begin // Disable periodic reads assign clear_periodic_rd_request = {RANKS{1'b0}}; assign periodic_rd_r = 1'b0; assign periodic_rd_rank_r = {RANK_WIDTH{1'b0}}; end // block: periodic_read_request endgenerate // Indicate that a refresh is in progress. The PHY will use this to schedule // tap adjustments during idle bus time reg maint_ref_zq_wip_r = 1'b0; output maint_ref_zq_wip; always @(posedge clk) if(rst) maint_ref_zq_wip_r <= #TCQ 1'b0; else if((zq_request || |refresh_request) && insert_maint_r1) maint_ref_zq_wip_r <= #TCQ 1'b1; else if(~maint_wip_r) maint_ref_zq_wip_r <= #TCQ 1'b0; assign maint_ref_zq_wip = maint_ref_zq_wip_r; endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : rank_common.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Block for logic common to all rank machines. Contains // a clock prescaler, and arbiters for refresh and periodic // read functions. `timescale 1 ps / 1 ps module mig_7series_v2_3_rank_common # ( parameter TCQ = 100, parameter DRAM_TYPE = "DDR3", parameter MAINT_PRESCALER_DIV = 40, parameter nBANK_MACHS = 4, parameter nCKESR = 4, parameter nCK_PER_CLK = 2, parameter PERIODIC_RD_TIMER_DIV = 20, parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter REFRESH_TIMER_DIV = 39, parameter ZQ_TIMER_DIV = 640000 ) (/*AUTOARG*/ // Outputs maint_prescaler_tick_r, refresh_tick, maint_zq_r, maint_sre_r, maint_srx_r, maint_req_r, maint_rank_r, clear_periodic_rd_request, periodic_rd_r, periodic_rd_rank_r, app_ref_ack, app_zq_ack, app_sr_active, maint_ref_zq_wip, // Inputs clk, rst, init_calib_complete, app_ref_req, app_zq_req, app_sr_req, insert_maint_r1, refresh_request, maint_wip_r, slot_0_present, slot_1_present, periodic_rd_request, periodic_rd_ack_r ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 input clk; input rst; // Maintenance and periodic read prescaler. Nominally 200 nS. localparam ONE = 1; localparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1); input init_calib_complete; reg maint_prescaler_tick_r_lcl; generate begin : maint_prescaler reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r; reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns; wire maint_prescaler_tick_ns = (maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]); always @(/*AS*/init_calib_complete or maint_prescaler_r or maint_prescaler_tick_ns) begin maint_prescaler_ns = maint_prescaler_r; if (~init_calib_complete || maint_prescaler_tick_ns) maint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0]; else if (|maint_prescaler_r) maint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0]; end always @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns; always @(posedge clk) maint_prescaler_tick_r_lcl <= #TCQ maint_prescaler_tick_ns; end endgenerate output wire maint_prescaler_tick_r; assign maint_prescaler_tick_r = maint_prescaler_tick_r_lcl; // Refresh timebase. Nominically 7800 nS. localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER_DIV + /*idle*/ 1); wire refresh_tick_lcl; generate begin : refresh_timer reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_r; reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_ns; always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl or refresh_tick_lcl or refresh_timer_r) begin refresh_timer_ns = refresh_timer_r; if (~init_calib_complete || refresh_tick_lcl) refresh_timer_ns = REFRESH_TIMER_DIV[REFRESH_TIMER_WIDTH-1:0]; else if (|refresh_timer_r && maint_prescaler_tick_r_lcl) refresh_timer_ns = refresh_timer_r - ONE[REFRESH_TIMER_WIDTH-1:0]; end always @(posedge clk) refresh_timer_r <= #TCQ refresh_timer_ns; assign refresh_tick_lcl = (refresh_timer_r == ONE[REFRESH_TIMER_WIDTH-1:0]) && maint_prescaler_tick_r_lcl; end endgenerate output wire refresh_tick; assign refresh_tick = refresh_tick_lcl; // ZQ timebase. Nominally 128 mS localparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1); input app_zq_req; input insert_maint_r1; reg maint_zq_r_lcl; reg zq_request = 1'b0; generate if (DRAM_TYPE == "DDR3") begin : zq_cntrl reg zq_tick = 1'b0; if (ZQ_TIMER_DIV !=0) begin : zq_timer reg [ZQ_TIMER_WIDTH-1:0] zq_timer_r; reg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns; always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl or zq_tick or zq_timer_r) begin zq_timer_ns = zq_timer_r; if (~init_calib_complete || zq_tick) zq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0]; else if (|zq_timer_r && maint_prescaler_tick_r_lcl) zq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0]; end always @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns; always @(/*AS*/maint_prescaler_tick_r_lcl or zq_timer_r) zq_tick = (zq_timer_r == ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick_r_lcl); end // zq_timer // ZQ request. Set request with timer tick, and when exiting PHY init. Never // request if ZQ_TIMER_DIV == 0. begin : zq_request_logic wire zq_clears_zq_request = insert_maint_r1 && maint_zq_r_lcl; reg zq_request_r; wire zq_request_ns = ~rst && (DRAM_TYPE == "DDR3") && ((~init_calib_complete && (ZQ_TIMER_DIV != 0)) || (zq_request_r && ~zq_clears_zq_request) || zq_tick || (app_zq_req && init_calib_complete)); always @(posedge clk) zq_request_r <= #TCQ zq_request_ns; always @(/*AS*/init_calib_complete or zq_request_r) zq_request = init_calib_complete && zq_request_r; end // zq_request_logic end endgenerate // Self-refresh control localparam nCKESR_CLKS = (nCKESR / nCK_PER_CLK) + (nCKESR % nCK_PER_CLK ? 1 : 0); localparam CKESR_TIMER_WIDTH = clogb2(nCKESR_CLKS + 1); input app_sr_req; reg maint_sre_r_lcl; reg maint_srx_r_lcl; reg sre_request = 1'b0; wire inhbt_srx; generate begin : sr_cntrl // SRE request. Set request with user request. begin : sre_request_logic reg sre_request_r; wire sre_clears_sre_request = insert_maint_r1 && maint_sre_r_lcl; wire sre_request_ns = ~rst && ((sre_request_r && ~sre_clears_sre_request) || (app_sr_req && init_calib_complete && ~maint_sre_r_lcl)); always @(posedge clk) sre_request_r <= #TCQ sre_request_ns; always @(init_calib_complete or sre_request_r) sre_request = init_calib_complete && sre_request_r; end // sre_request_logic // CKESR timer: Self-Refresh must be maintained for a minimum of tCKESR begin : ckesr_timer reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_r = {CKESR_TIMER_WIDTH{1'b0}}; reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_ns = {CKESR_TIMER_WIDTH{1'b0}}; always @(insert_maint_r1 or ckesr_timer_r or maint_sre_r_lcl) begin ckesr_timer_ns = ckesr_timer_r; if (insert_maint_r1 && maint_sre_r_lcl) ckesr_timer_ns = nCKESR_CLKS[CKESR_TIMER_WIDTH-1:0]; else if(|ckesr_timer_r) ckesr_timer_ns = ckesr_timer_r - ONE[CKESR_TIMER_WIDTH-1:0]; end always @(posedge clk) ckesr_timer_r <= #TCQ ckesr_timer_ns; assign inhbt_srx = |ckesr_timer_r; end // ckesr_timer end endgenerate // DRAM maintenance operations of refresh and ZQ calibration, and self-refresh // DRAM maintenance operations and self-refresh have their own channel in the // queue. There is also a single, very simple bank machine // dedicated to these operations. Its assumed that the // maintenance operations can be completed quickly enough // to avoid any queuing. // // ZQ, refresh and self-refresh requests share a channel into controller. // Self-refresh is appended to the uppermost bit of the request bus and ZQ is // appended just below that. input[RANKS-1:0] refresh_request; input maint_wip_r; reg maint_req_r_lcl; reg [RANK_WIDTH-1:0] maint_rank_r_lcl; input [7:0] slot_0_present; input [7:0] slot_1_present; generate begin : maintenance_request // Maintenance request pipeline. reg upd_last_master_r; reg new_maint_rank_r; wire maint_busy = upd_last_master_r || new_maint_rank_r || maint_req_r_lcl || maint_wip_r; wire [RANKS+1:0] maint_request = {sre_request, zq_request, refresh_request[RANKS-1:0]}; wire upd_last_master_ns = |maint_request && ~maint_busy; always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns; always @(posedge clk) new_maint_rank_r <= #TCQ upd_last_master_r; always @(posedge clk) maint_req_r_lcl <= #TCQ new_maint_rank_r; // Arbitrate maintenance requests. wire [RANKS+1:0] maint_grant_ns; wire [RANKS+1:0] maint_grant_r; mig_7series_v2_3_round_robin_arb # (.WIDTH (RANKS+2)) maint_arb0 (.grant_ns (maint_grant_ns), .grant_r (maint_grant_r), .upd_last_master (upd_last_master_r), .current_master (maint_grant_r), .req (maint_request), .disable_grant (1'b0), /*AUTOINST*/ // Inputs .clk (clk), .rst (rst)); // Look at arbitration results. Decide if ZQ, refresh or self-refresh. // If refresh select the maintenance rank from the winning rank controller. // If ZQ or self-refresh, generate a sequence of rank numbers corresponding to // slots populated maint_rank_r is not used for comparisons in the queue for ZQ // or self-refresh requests. The bank machine will enable CS for the number of // states equal to the the number of occupied slots. This will produce a // command to every occupied slot, but not in any particular order. wire [7:0] present = slot_0_present | slot_1_present; integer i; reg [RANK_WIDTH-1:0] maint_rank_ns; wire maint_zq_ns = ~rst && (upd_last_master_r ? maint_grant_r[RANKS] : maint_zq_r_lcl); wire maint_srx_ns = ~rst && (maint_sre_r_lcl ? ~app_sr_req & ~inhbt_srx : maint_srx_r_lcl && upd_last_master_r ? maint_grant_r[RANKS+1] : maint_srx_r_lcl); wire maint_sre_ns = ~rst && (upd_last_master_r ? maint_grant_r[RANKS+1] : maint_sre_r_lcl && ~maint_srx_ns); always @(/*AS*/maint_grant_r or maint_rank_r_lcl or maint_zq_ns or maint_sre_ns or maint_srx_ns or present or rst or upd_last_master_r) begin if (rst) maint_rank_ns = {RANK_WIDTH{1'b0}}; else begin maint_rank_ns = maint_rank_r_lcl; if (maint_zq_ns || maint_sre_ns || maint_srx_ns) begin maint_rank_ns = maint_rank_r_lcl + ONE[RANK_WIDTH-1:0]; for (i=0; i<8; i=i+1) if (~present[maint_rank_ns]) maint_rank_ns = maint_rank_ns + ONE[RANK_WIDTH-1:0]; end else if (upd_last_master_r) for (i=0; i<RANKS; i=i+1) if (maint_grant_r[i]) maint_rank_ns = i[RANK_WIDTH-1:0]; end end always @(posedge clk) maint_rank_r_lcl <= #TCQ maint_rank_ns; always @(posedge clk) maint_zq_r_lcl <= #TCQ maint_zq_ns; always @(posedge clk) maint_sre_r_lcl <= #TCQ maint_sre_ns; always @(posedge clk) maint_srx_r_lcl <= #TCQ maint_srx_ns; end // block: maintenance_request endgenerate output wire maint_zq_r; assign maint_zq_r = maint_zq_r_lcl; output wire maint_sre_r; assign maint_sre_r = maint_sre_r_lcl; output wire maint_srx_r; assign maint_srx_r = maint_srx_r_lcl; output wire maint_req_r; assign maint_req_r = maint_req_r_lcl; output wire [RANK_WIDTH-1:0] maint_rank_r; assign maint_rank_r = maint_rank_r_lcl; // Indicate whether self-refresh is active or not. output app_sr_active; reg app_sr_active_r; wire app_sr_active_ns = insert_maint_r1 ? maint_sre_r && ~maint_srx_r : app_sr_active_r; always @(posedge clk) app_sr_active_r <= #TCQ app_sr_active_ns; assign app_sr_active = app_sr_active_r; // Acknowledge user REF and ZQ Requests input app_ref_req; output app_ref_ack; wire app_ref_ack_ns; wire app_ref_ns; reg app_ref_ack_r = 1'b0; reg app_ref_r = 1'b0; assign app_ref_ns = init_calib_complete && (app_ref_req || app_ref_r && |refresh_request); assign app_ref_ack_ns = app_ref_r && ~|refresh_request; always @(posedge clk) app_ref_r <= #TCQ app_ref_ns; always @(posedge clk) app_ref_ack_r <= #TCQ app_ref_ack_ns; assign app_ref_ack = app_ref_ack_r; output app_zq_ack; wire app_zq_ack_ns; wire app_zq_ns; reg app_zq_ack_r = 1'b0; reg app_zq_r = 1'b0; assign app_zq_ns = init_calib_complete && (app_zq_req || app_zq_r && zq_request); assign app_zq_ack_ns = app_zq_r && ~zq_request; always @(posedge clk) app_zq_r <= #TCQ app_zq_ns; always @(posedge clk) app_zq_ack_r <= #TCQ app_zq_ack_ns; assign app_zq_ack = app_zq_ack_r; // Periodic reads to maintain PHY alignment. // Demand insertion of periodic read as soon as // possible. Since the is a single rank, bank compare mechanism // must be used, periodic reads must be forced in at the // expense of not accepting a normal request. input [RANKS-1:0] periodic_rd_request; reg periodic_rd_r_lcl; reg [RANK_WIDTH-1:0] periodic_rd_rank_r_lcl; input periodic_rd_ack_r; output wire [RANKS-1:0] clear_periodic_rd_request; output wire periodic_rd_r; output wire [RANK_WIDTH-1:0] periodic_rd_rank_r; generate // This is not needed in 7-Series and should remain disabled if ( PERIODIC_RD_TIMER_DIV != 0 ) begin : periodic_read_request // Maintenance request pipeline. reg periodic_rd_r_cnt; wire int_periodic_rd_ack_r = (periodic_rd_ack_r && periodic_rd_r_cnt); reg upd_last_master_r; wire periodic_rd_busy = upd_last_master_r || periodic_rd_r_lcl; wire upd_last_master_ns = init_calib_complete && (|periodic_rd_request && ~periodic_rd_busy); always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns; wire periodic_rd_ns = init_calib_complete && (upd_last_master_r || (periodic_rd_r_lcl && ~int_periodic_rd_ack_r)); always @(posedge clk) periodic_rd_r_lcl <= #TCQ periodic_rd_ns; always @(posedge clk) begin if (rst) periodic_rd_r_cnt <= #TCQ 1'b0; else if (periodic_rd_r_lcl && periodic_rd_ack_r) periodic_rd_r_cnt <= ~periodic_rd_r_cnt; end // Arbitrate periodic read requests. wire [RANKS-1:0] periodic_rd_grant_ns; reg [RANKS-1:0] periodic_rd_grant_r; mig_7series_v2_3_round_robin_arb # (.WIDTH (RANKS)) periodic_rd_arb0 (.grant_ns (periodic_rd_grant_ns[RANKS-1:0]), .grant_r (), .upd_last_master (upd_last_master_r), .current_master (periodic_rd_grant_r[RANKS-1:0]), .req (periodic_rd_request[RANKS-1:0]), .disable_grant (1'b0), /*AUTOINST*/ // Inputs .clk (clk), .rst (rst)); always @(posedge clk) periodic_rd_grant_r = upd_last_master_ns ? periodic_rd_grant_ns : periodic_rd_grant_r; // Encode and set periodic read rank into periodic_rd_rank_r. integer i; reg [RANK_WIDTH-1:0] periodic_rd_rank_ns; always @(/*AS*/periodic_rd_grant_r or periodic_rd_rank_r_lcl or upd_last_master_r) begin periodic_rd_rank_ns = periodic_rd_rank_r_lcl; if (upd_last_master_r) for (i=0; i<RANKS; i=i+1) if (periodic_rd_grant_r[i]) periodic_rd_rank_ns = i[RANK_WIDTH-1:0]; end always @(posedge clk) periodic_rd_rank_r_lcl <= #TCQ periodic_rd_rank_ns; // Once the request is dropped in the queue, it might be a while before it // emerges. Can't clear the request based on seeing the read issued. // Need to clear the request as soon as its made it into the queue. assign clear_periodic_rd_request = periodic_rd_grant_r & {RANKS{periodic_rd_ack_r}}; assign periodic_rd_r = periodic_rd_r_lcl; assign periodic_rd_rank_r = periodic_rd_rank_r_lcl; end else begin // Disable periodic reads assign clear_periodic_rd_request = {RANKS{1'b0}}; assign periodic_rd_r = 1'b0; assign periodic_rd_rank_r = {RANK_WIDTH{1'b0}}; end // block: periodic_read_request endgenerate // Indicate that a refresh is in progress. The PHY will use this to schedule // tap adjustments during idle bus time reg maint_ref_zq_wip_r = 1'b0; output maint_ref_zq_wip; always @(posedge clk) if(rst) maint_ref_zq_wip_r <= #TCQ 1'b0; else if((zq_request || |refresh_request) && insert_maint_r1) maint_ref_zq_wip_r <= #TCQ 1'b1; else if(~maint_wip_r) maint_ref_zq_wip_r <= #TCQ 1'b0; assign maint_ref_zq_wip = maint_ref_zq_wip_r; endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : rank_common.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Block for logic common to all rank machines. Contains // a clock prescaler, and arbiters for refresh and periodic // read functions. `timescale 1 ps / 1 ps module mig_7series_v2_3_rank_common # ( parameter TCQ = 100, parameter DRAM_TYPE = "DDR3", parameter MAINT_PRESCALER_DIV = 40, parameter nBANK_MACHS = 4, parameter nCKESR = 4, parameter nCK_PER_CLK = 2, parameter PERIODIC_RD_TIMER_DIV = 20, parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter REFRESH_TIMER_DIV = 39, parameter ZQ_TIMER_DIV = 640000 ) (/*AUTOARG*/ // Outputs maint_prescaler_tick_r, refresh_tick, maint_zq_r, maint_sre_r, maint_srx_r, maint_req_r, maint_rank_r, clear_periodic_rd_request, periodic_rd_r, periodic_rd_rank_r, app_ref_ack, app_zq_ack, app_sr_active, maint_ref_zq_wip, // Inputs clk, rst, init_calib_complete, app_ref_req, app_zq_req, app_sr_req, insert_maint_r1, refresh_request, maint_wip_r, slot_0_present, slot_1_present, periodic_rd_request, periodic_rd_ack_r ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 input clk; input rst; // Maintenance and periodic read prescaler. Nominally 200 nS. localparam ONE = 1; localparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1); input init_calib_complete; reg maint_prescaler_tick_r_lcl; generate begin : maint_prescaler reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r; reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns; wire maint_prescaler_tick_ns = (maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]); always @(/*AS*/init_calib_complete or maint_prescaler_r or maint_prescaler_tick_ns) begin maint_prescaler_ns = maint_prescaler_r; if (~init_calib_complete || maint_prescaler_tick_ns) maint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0]; else if (|maint_prescaler_r) maint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0]; end always @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns; always @(posedge clk) maint_prescaler_tick_r_lcl <= #TCQ maint_prescaler_tick_ns; end endgenerate output wire maint_prescaler_tick_r; assign maint_prescaler_tick_r = maint_prescaler_tick_r_lcl; // Refresh timebase. Nominically 7800 nS. localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER_DIV + /*idle*/ 1); wire refresh_tick_lcl; generate begin : refresh_timer reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_r; reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_ns; always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl or refresh_tick_lcl or refresh_timer_r) begin refresh_timer_ns = refresh_timer_r; if (~init_calib_complete || refresh_tick_lcl) refresh_timer_ns = REFRESH_TIMER_DIV[REFRESH_TIMER_WIDTH-1:0]; else if (|refresh_timer_r && maint_prescaler_tick_r_lcl) refresh_timer_ns = refresh_timer_r - ONE[REFRESH_TIMER_WIDTH-1:0]; end always @(posedge clk) refresh_timer_r <= #TCQ refresh_timer_ns; assign refresh_tick_lcl = (refresh_timer_r == ONE[REFRESH_TIMER_WIDTH-1:0]) && maint_prescaler_tick_r_lcl; end endgenerate output wire refresh_tick; assign refresh_tick = refresh_tick_lcl; // ZQ timebase. Nominally 128 mS localparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1); input app_zq_req; input insert_maint_r1; reg maint_zq_r_lcl; reg zq_request = 1'b0; generate if (DRAM_TYPE == "DDR3") begin : zq_cntrl reg zq_tick = 1'b0; if (ZQ_TIMER_DIV !=0) begin : zq_timer reg [ZQ_TIMER_WIDTH-1:0] zq_timer_r; reg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns; always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl or zq_tick or zq_timer_r) begin zq_timer_ns = zq_timer_r; if (~init_calib_complete || zq_tick) zq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0]; else if (|zq_timer_r && maint_prescaler_tick_r_lcl) zq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0]; end always @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns; always @(/*AS*/maint_prescaler_tick_r_lcl or zq_timer_r) zq_tick = (zq_timer_r == ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick_r_lcl); end // zq_timer // ZQ request. Set request with timer tick, and when exiting PHY init. Never // request if ZQ_TIMER_DIV == 0. begin : zq_request_logic wire zq_clears_zq_request = insert_maint_r1 && maint_zq_r_lcl; reg zq_request_r; wire zq_request_ns = ~rst && (DRAM_TYPE == "DDR3") && ((~init_calib_complete && (ZQ_TIMER_DIV != 0)) || (zq_request_r && ~zq_clears_zq_request) || zq_tick || (app_zq_req && init_calib_complete)); always @(posedge clk) zq_request_r <= #TCQ zq_request_ns; always @(/*AS*/init_calib_complete or zq_request_r) zq_request = init_calib_complete && zq_request_r; end // zq_request_logic end endgenerate // Self-refresh control localparam nCKESR_CLKS = (nCKESR / nCK_PER_CLK) + (nCKESR % nCK_PER_CLK ? 1 : 0); localparam CKESR_TIMER_WIDTH = clogb2(nCKESR_CLKS + 1); input app_sr_req; reg maint_sre_r_lcl; reg maint_srx_r_lcl; reg sre_request = 1'b0; wire inhbt_srx; generate begin : sr_cntrl // SRE request. Set request with user request. begin : sre_request_logic reg sre_request_r; wire sre_clears_sre_request = insert_maint_r1 && maint_sre_r_lcl; wire sre_request_ns = ~rst && ((sre_request_r && ~sre_clears_sre_request) || (app_sr_req && init_calib_complete && ~maint_sre_r_lcl)); always @(posedge clk) sre_request_r <= #TCQ sre_request_ns; always @(init_calib_complete or sre_request_r) sre_request = init_calib_complete && sre_request_r; end // sre_request_logic // CKESR timer: Self-Refresh must be maintained for a minimum of tCKESR begin : ckesr_timer reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_r = {CKESR_TIMER_WIDTH{1'b0}}; reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_ns = {CKESR_TIMER_WIDTH{1'b0}}; always @(insert_maint_r1 or ckesr_timer_r or maint_sre_r_lcl) begin ckesr_timer_ns = ckesr_timer_r; if (insert_maint_r1 && maint_sre_r_lcl) ckesr_timer_ns = nCKESR_CLKS[CKESR_TIMER_WIDTH-1:0]; else if(|ckesr_timer_r) ckesr_timer_ns = ckesr_timer_r - ONE[CKESR_TIMER_WIDTH-1:0]; end always @(posedge clk) ckesr_timer_r <= #TCQ ckesr_timer_ns; assign inhbt_srx = |ckesr_timer_r; end // ckesr_timer end endgenerate // DRAM maintenance operations of refresh and ZQ calibration, and self-refresh // DRAM maintenance operations and self-refresh have their own channel in the // queue. There is also a single, very simple bank machine // dedicated to these operations. Its assumed that the // maintenance operations can be completed quickly enough // to avoid any queuing. // // ZQ, refresh and self-refresh requests share a channel into controller. // Self-refresh is appended to the uppermost bit of the request bus and ZQ is // appended just below that. input[RANKS-1:0] refresh_request; input maint_wip_r; reg maint_req_r_lcl; reg [RANK_WIDTH-1:0] maint_rank_r_lcl; input [7:0] slot_0_present; input [7:0] slot_1_present; generate begin : maintenance_request // Maintenance request pipeline. reg upd_last_master_r; reg new_maint_rank_r; wire maint_busy = upd_last_master_r || new_maint_rank_r || maint_req_r_lcl || maint_wip_r; wire [RANKS+1:0] maint_request = {sre_request, zq_request, refresh_request[RANKS-1:0]}; wire upd_last_master_ns = |maint_request && ~maint_busy; always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns; always @(posedge clk) new_maint_rank_r <= #TCQ upd_last_master_r; always @(posedge clk) maint_req_r_lcl <= #TCQ new_maint_rank_r; // Arbitrate maintenance requests. wire [RANKS+1:0] maint_grant_ns; wire [RANKS+1:0] maint_grant_r; mig_7series_v2_3_round_robin_arb # (.WIDTH (RANKS+2)) maint_arb0 (.grant_ns (maint_grant_ns), .grant_r (maint_grant_r), .upd_last_master (upd_last_master_r), .current_master (maint_grant_r), .req (maint_request), .disable_grant (1'b0), /*AUTOINST*/ // Inputs .clk (clk), .rst (rst)); // Look at arbitration results. Decide if ZQ, refresh or self-refresh. // If refresh select the maintenance rank from the winning rank controller. // If ZQ or self-refresh, generate a sequence of rank numbers corresponding to // slots populated maint_rank_r is not used for comparisons in the queue for ZQ // or self-refresh requests. The bank machine will enable CS for the number of // states equal to the the number of occupied slots. This will produce a // command to every occupied slot, but not in any particular order. wire [7:0] present = slot_0_present | slot_1_present; integer i; reg [RANK_WIDTH-1:0] maint_rank_ns; wire maint_zq_ns = ~rst && (upd_last_master_r ? maint_grant_r[RANKS] : maint_zq_r_lcl); wire maint_srx_ns = ~rst && (maint_sre_r_lcl ? ~app_sr_req & ~inhbt_srx : maint_srx_r_lcl && upd_last_master_r ? maint_grant_r[RANKS+1] : maint_srx_r_lcl); wire maint_sre_ns = ~rst && (upd_last_master_r ? maint_grant_r[RANKS+1] : maint_sre_r_lcl && ~maint_srx_ns); always @(/*AS*/maint_grant_r or maint_rank_r_lcl or maint_zq_ns or maint_sre_ns or maint_srx_ns or present or rst or upd_last_master_r) begin if (rst) maint_rank_ns = {RANK_WIDTH{1'b0}}; else begin maint_rank_ns = maint_rank_r_lcl; if (maint_zq_ns || maint_sre_ns || maint_srx_ns) begin maint_rank_ns = maint_rank_r_lcl + ONE[RANK_WIDTH-1:0]; for (i=0; i<8; i=i+1) if (~present[maint_rank_ns]) maint_rank_ns = maint_rank_ns + ONE[RANK_WIDTH-1:0]; end else if (upd_last_master_r) for (i=0; i<RANKS; i=i+1) if (maint_grant_r[i]) maint_rank_ns = i[RANK_WIDTH-1:0]; end end always @(posedge clk) maint_rank_r_lcl <= #TCQ maint_rank_ns; always @(posedge clk) maint_zq_r_lcl <= #TCQ maint_zq_ns; always @(posedge clk) maint_sre_r_lcl <= #TCQ maint_sre_ns; always @(posedge clk) maint_srx_r_lcl <= #TCQ maint_srx_ns; end // block: maintenance_request endgenerate output wire maint_zq_r; assign maint_zq_r = maint_zq_r_lcl; output wire maint_sre_r; assign maint_sre_r = maint_sre_r_lcl; output wire maint_srx_r; assign maint_srx_r = maint_srx_r_lcl; output wire maint_req_r; assign maint_req_r = maint_req_r_lcl; output wire [RANK_WIDTH-1:0] maint_rank_r; assign maint_rank_r = maint_rank_r_lcl; // Indicate whether self-refresh is active or not. output app_sr_active; reg app_sr_active_r; wire app_sr_active_ns = insert_maint_r1 ? maint_sre_r && ~maint_srx_r : app_sr_active_r; always @(posedge clk) app_sr_active_r <= #TCQ app_sr_active_ns; assign app_sr_active = app_sr_active_r; // Acknowledge user REF and ZQ Requests input app_ref_req; output app_ref_ack; wire app_ref_ack_ns; wire app_ref_ns; reg app_ref_ack_r = 1'b0; reg app_ref_r = 1'b0; assign app_ref_ns = init_calib_complete && (app_ref_req || app_ref_r && |refresh_request); assign app_ref_ack_ns = app_ref_r && ~|refresh_request; always @(posedge clk) app_ref_r <= #TCQ app_ref_ns; always @(posedge clk) app_ref_ack_r <= #TCQ app_ref_ack_ns; assign app_ref_ack = app_ref_ack_r; output app_zq_ack; wire app_zq_ack_ns; wire app_zq_ns; reg app_zq_ack_r = 1'b0; reg app_zq_r = 1'b0; assign app_zq_ns = init_calib_complete && (app_zq_req || app_zq_r && zq_request); assign app_zq_ack_ns = app_zq_r && ~zq_request; always @(posedge clk) app_zq_r <= #TCQ app_zq_ns; always @(posedge clk) app_zq_ack_r <= #TCQ app_zq_ack_ns; assign app_zq_ack = app_zq_ack_r; // Periodic reads to maintain PHY alignment. // Demand insertion of periodic read as soon as // possible. Since the is a single rank, bank compare mechanism // must be used, periodic reads must be forced in at the // expense of not accepting a normal request. input [RANKS-1:0] periodic_rd_request; reg periodic_rd_r_lcl; reg [RANK_WIDTH-1:0] periodic_rd_rank_r_lcl; input periodic_rd_ack_r; output wire [RANKS-1:0] clear_periodic_rd_request; output wire periodic_rd_r; output wire [RANK_WIDTH-1:0] periodic_rd_rank_r; generate // This is not needed in 7-Series and should remain disabled if ( PERIODIC_RD_TIMER_DIV != 0 ) begin : periodic_read_request // Maintenance request pipeline. reg periodic_rd_r_cnt; wire int_periodic_rd_ack_r = (periodic_rd_ack_r && periodic_rd_r_cnt); reg upd_last_master_r; wire periodic_rd_busy = upd_last_master_r || periodic_rd_r_lcl; wire upd_last_master_ns = init_calib_complete && (|periodic_rd_request && ~periodic_rd_busy); always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns; wire periodic_rd_ns = init_calib_complete && (upd_last_master_r || (periodic_rd_r_lcl && ~int_periodic_rd_ack_r)); always @(posedge clk) periodic_rd_r_lcl <= #TCQ periodic_rd_ns; always @(posedge clk) begin if (rst) periodic_rd_r_cnt <= #TCQ 1'b0; else if (periodic_rd_r_lcl && periodic_rd_ack_r) periodic_rd_r_cnt <= ~periodic_rd_r_cnt; end // Arbitrate periodic read requests. wire [RANKS-1:0] periodic_rd_grant_ns; reg [RANKS-1:0] periodic_rd_grant_r; mig_7series_v2_3_round_robin_arb # (.WIDTH (RANKS)) periodic_rd_arb0 (.grant_ns (periodic_rd_grant_ns[RANKS-1:0]), .grant_r (), .upd_last_master (upd_last_master_r), .current_master (periodic_rd_grant_r[RANKS-1:0]), .req (periodic_rd_request[RANKS-1:0]), .disable_grant (1'b0), /*AUTOINST*/ // Inputs .clk (clk), .rst (rst)); always @(posedge clk) periodic_rd_grant_r = upd_last_master_ns ? periodic_rd_grant_ns : periodic_rd_grant_r; // Encode and set periodic read rank into periodic_rd_rank_r. integer i; reg [RANK_WIDTH-1:0] periodic_rd_rank_ns; always @(/*AS*/periodic_rd_grant_r or periodic_rd_rank_r_lcl or upd_last_master_r) begin periodic_rd_rank_ns = periodic_rd_rank_r_lcl; if (upd_last_master_r) for (i=0; i<RANKS; i=i+1) if (periodic_rd_grant_r[i]) periodic_rd_rank_ns = i[RANK_WIDTH-1:0]; end always @(posedge clk) periodic_rd_rank_r_lcl <= #TCQ periodic_rd_rank_ns; // Once the request is dropped in the queue, it might be a while before it // emerges. Can't clear the request based on seeing the read issued. // Need to clear the request as soon as its made it into the queue. assign clear_periodic_rd_request = periodic_rd_grant_r & {RANKS{periodic_rd_ack_r}}; assign periodic_rd_r = periodic_rd_r_lcl; assign periodic_rd_rank_r = periodic_rd_rank_r_lcl; end else begin // Disable periodic reads assign clear_periodic_rd_request = {RANKS{1'b0}}; assign periodic_rd_r = 1'b0; assign periodic_rd_rank_r = {RANK_WIDTH{1'b0}}; end // block: periodic_read_request endgenerate // Indicate that a refresh is in progress. The PHY will use this to schedule // tap adjustments during idle bus time reg maint_ref_zq_wip_r = 1'b0; output maint_ref_zq_wip; always @(posedge clk) if(rst) maint_ref_zq_wip_r <= #TCQ 1'b0; else if((zq_request || |refresh_request) && insert_maint_r1) maint_ref_zq_wip_r <= #TCQ 1'b1; else if(~maint_wip_r) maint_ref_zq_wip_r <= #TCQ 1'b0; assign maint_ref_zq_wip = maint_ref_zq_wip_r; endmodule

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:11:30 08/20/2015 // Design Name: // Module Name: Sixth_Phase // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Comparators //Module Parameter //W_Exp = 9 ; Single Precision Format //W_Exp = 11; Double Precision Format # (parameter W_Exp = 9) /* # (parameter W_Exp = 12)*/ ( input wire [W_Exp-1:0] exp, //exponent of the fifth phase output wire overflow, //overflow flag output wire underflow //underflow flag ); wire [W_Exp-1:0] U_limit; //Max Normal value of the standar ieee 754 wire [W_Exp-1:0] L_limit; //Min Normal value of the standar ieee 754 //Compares the exponent with the Max Normal Value, if the exponent is //larger than U_limit then exist overflow Greater_Comparator #(.W(W_Exp)) GTComparator ( .Data_A(exp), .Data_B(U_limit), .gthan(overflow) ); //Compares the exponent with the Min Normal Value, if the exponent is //smaller than L_limit then exist underflow Comparator_Less #(.W(W_Exp)) LTComparator ( .Data_A(exp), .Data_B(L_limit), .less(underflow) ); //This generate sentence creates the limit values based on the //precision format generate if(W_Exp == 9) begin assign U_limit = 9'hfe; assign L_limit = 9'h01; end else begin assign U_limit = 12'b111111111110; assign L_limit = 12'b000000000001; end endgenerate endmodule

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 14:11:30 08/20/2015 // Design Name: // Module Name: Sixth_Phase // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module Comparators //Module Parameter //W_Exp = 9 ; Single Precision Format //W_Exp = 11; Double Precision Format # (parameter W_Exp = 9) /* # (parameter W_Exp = 12)*/ ( input wire [W_Exp-1:0] exp, //exponent of the fifth phase output wire overflow, //overflow flag output wire underflow //underflow flag ); wire [W_Exp-1:0] U_limit; //Max Normal value of the standar ieee 754 wire [W_Exp-1:0] L_limit; //Min Normal value of the standar ieee 754 //Compares the exponent with the Max Normal Value, if the exponent is //larger than U_limit then exist overflow Greater_Comparator #(.W(W_Exp)) GTComparator ( .Data_A(exp), .Data_B(U_limit), .gthan(overflow) ); //Compares the exponent with the Min Normal Value, if the exponent is //smaller than L_limit then exist underflow Comparator_Less #(.W(W_Exp)) LTComparator ( .Data_A(exp), .Data_B(L_limit), .less(underflow) ); //This generate sentence creates the limit values based on the //precision format generate if(W_Exp == 9) begin assign U_limit = 9'hfe; assign L_limit = 9'h01; end else begin assign U_limit = 12'b111111111110; assign L_limit = 12'b000000000001; end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: // \ \ Application: MIG // / / Filename: ddr_phy_prbs_rdlvl.v // /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // PRBS Read leveling calibration logic // NOTES: // 1. Window detection with PRBS pattern. //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_prbs_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $ **$Date: 2011/06/24 14:49:00 $ **$Author: mgeorge $ **$Revision: 1.2 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_prbs_rdlvl.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_prbs_rdlvl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter RANKS = 1, // # of DRAM ranks parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps parameter PRBS_WIDTH = 8, // PRBS generator output width parameter FIXED_VICTIM = "TRUE", // No victim rotation when "TRUE" parameter FINE_PER_BIT = "ON", parameter CENTER_COMP_MODE = "ON", parameter PI_VAL_ADJ = "ON" ) ( input clk, input rst, // Calibration status, control signals input prbs_rdlvl_start, (* max_fanout = 100 *) output reg prbs_rdlvl_done, output reg prbs_last_byte_done, output reg prbs_rdlvl_prech_req, input complex_sample_cnt_inc, input prech_done, input phy_if_empty, // Captured data in fabric clock domain input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data, //Expected data from PRBS generator input [2*nCK_PER_CLK*DQ_WIDTH-1:0] compare_data, // Decrement initial Phaser_IN Fine tap delay input [5:0] pi_counter_read_val, // Stage 1 calibration outputs output reg pi_en_stg2_f, output reg pi_stg2_f_incdec, output [255:0] dbg_prbs_rdlvl, output [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt, output reg [2:0] rd_victim_sel, output reg complex_victim_inc, output reg reset_rd_addr, output reg read_pause, output reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r, output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps, output reg [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit output reg fine_delay_sel //fine delay selection - actual update of fine delay ); localparam [5:0] PRBS_IDLE = 6'h00; localparam [5:0] PRBS_NEW_DQS_WAIT = 6'h01; localparam [5:0] PRBS_PAT_COMPARE = 6'h02; localparam [5:0] PRBS_DEC_DQS = 6'h03; localparam [5:0] PRBS_DEC_DQS_WAIT = 6'h04; localparam [5:0] PRBS_INC_DQS = 6'h05; localparam [5:0] PRBS_INC_DQS_WAIT = 6'h06; localparam [5:0] PRBS_CALC_TAPS = 6'h07; localparam [5:0] PRBS_NEXT_DQS = 6'h08; localparam [5:0] PRBS_NEW_DQS_PREWAIT = 6'h09; localparam [5:0] PRBS_DONE = 6'h0A; localparam [5:0] PRBS_CALC_TAPS_PRE = 6'h0B; localparam [5:0] PRBS_CALC_TAPS_WAIT = 6'h0C; localparam [5:0] FINE_PI_DEC = 6'h0D; //go back to all fail or back to center localparam [5:0] FINE_PI_DEC_WAIT = 6'h0E; //wait for PI tap dec settle localparam [5:0] FINE_PI_INC = 6'h0F; //increse up to 1 fail localparam [5:0] FINE_PI_INC_WAIT = 6'h10; //wait for PI tap int settle localparam [5:0] FINE_PAT_COMPARE_PER_BIT = 6'h11; //compare per bit error and check left/right/gain/loss localparam [5:0] FINE_CALC_TAPS = 6'h12; //setup fine_delay_incdec_pb for better window size localparam [5:0] FINE_CALC_TAPS_WAIT = 6'h13; //wait for ROM value for dec cnt localparam [11:0] NUM_SAMPLES_CNT = (SIM_CAL_OPTION == "NONE") ? 'd50 : 12'h001; localparam [11:0] NUM_SAMPLES_CNT1 = (SIM_CAL_OPTION == "NONE") ? 'd20 : 12'h001; localparam [11:0] NUM_SAMPLES_CNT2 = (SIM_CAL_OPTION == "NONE") ? 'd10 : 12'h001; wire [DQS_CNT_WIDTH+2:0]prbs_dqs_cnt_timing; reg [DQS_CNT_WIDTH+2:0] prbs_dqs_cnt_timing_r; reg [DQS_CNT_WIDTH:0] prbs_dqs_cnt_r; reg prbs_prech_req_r; reg [5:0] prbs_state_r; reg [5:0] prbs_state_r1; reg wait_state_cnt_en_r; reg [3:0] wait_state_cnt_r; reg cnt_wait_state; reg err_chk_invalid; // reg found_edge_r; reg prbs_found_1st_edge_r; reg prbs_found_2nd_edge_r; reg [5:0] prbs_1st_edge_taps_r; // reg found_stable_eye_r; reg [5:0] prbs_dqs_tap_cnt_r; reg [5:0] prbs_dec_tap_calc_plus_3; reg [5:0] prbs_dec_tap_calc_minus_3; reg prbs_dqs_tap_limit_r; reg [5:0] prbs_inc_tap_cnt; reg [5:0] prbs_dec_tap_cnt; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r1; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r1; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r1; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r1; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r1; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r1; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r1; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r1; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r2; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r2; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r2; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r2; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r2; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r2; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r2; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r2; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r3; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r3; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r3; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r3; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r3; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r3; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r3; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r3; reg [DRAM_WIDTH-1:0] mux_rd_fall0_r4; reg [DRAM_WIDTH-1:0] mux_rd_fall1_r4; reg [DRAM_WIDTH-1:0] mux_rd_rise0_r4; reg [DRAM_WIDTH-1:0] mux_rd_rise1_r4; reg [DRAM_WIDTH-1:0] mux_rd_fall2_r4; reg [DRAM_WIDTH-1:0] mux_rd_fall3_r4; reg [DRAM_WIDTH-1:0] mux_rd_rise2_r4; reg [DRAM_WIDTH-1:0] mux_rd_rise3_r4; reg mux_rd_valid_r; reg rd_valid_r1; reg rd_valid_r2; reg rd_valid_r3; reg new_cnt_dqs_r; reg prbs_tap_en_r; reg prbs_tap_inc_r; reg pi_en_stg2_f_timing; reg pi_stg2_f_incdec_timing; wire [DQ_WIDTH-1:0] rd_data_rise0; wire [DQ_WIDTH-1:0] rd_data_fall0; wire [DQ_WIDTH-1:0] rd_data_rise1; wire [DQ_WIDTH-1:0] rd_data_fall1; wire [DQ_WIDTH-1:0] rd_data_rise2; wire [DQ_WIDTH-1:0] rd_data_fall2; wire [DQ_WIDTH-1:0] rd_data_rise3; wire [DQ_WIDTH-1:0] rd_data_fall3; wire [DQ_WIDTH-1:0] compare_data_r0; wire [DQ_WIDTH-1:0] compare_data_f0; wire [DQ_WIDTH-1:0] compare_data_r1; wire [DQ_WIDTH-1:0] compare_data_f1; wire [DQ_WIDTH-1:0] compare_data_r2; wire [DQ_WIDTH-1:0] compare_data_f2; wire [DQ_WIDTH-1:0] compare_data_r3; wire [DQ_WIDTH-1:0] compare_data_f3; reg [DRAM_WIDTH-1:0] compare_data_rise0_r1; reg [DRAM_WIDTH-1:0] compare_data_fall0_r1; reg [DRAM_WIDTH-1:0] compare_data_rise1_r1; reg [DRAM_WIDTH-1:0] compare_data_fall1_r1; reg [DRAM_WIDTH-1:0] compare_data_rise2_r1; reg [DRAM_WIDTH-1:0] compare_data_fall2_r1; reg [DRAM_WIDTH-1:0] compare_data_rise3_r1; reg [DRAM_WIDTH-1:0] compare_data_fall3_r1; reg [DQS_CNT_WIDTH:0] rd_mux_sel_r; reg [5:0] prbs_2nd_edge_taps_r; // reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r; reg [5:0] rdlvl_cpt_tap_cnt; reg prbs_rdlvl_start_r; reg compare_err; reg compare_err_r0; reg compare_err_f0; reg compare_err_r1; reg compare_err_f1; reg compare_err_r2; reg compare_err_f2; reg compare_err_r3; reg compare_err_f3; reg samples_cnt1_en_r; reg samples_cnt2_en_r; reg [11:0] samples_cnt_r; reg num_samples_done_r; reg num_samples_done_ind; //indicate num_samples_done_r is set in FINE_PAT_COMPARE_PER_BIT to prevent victim_sel_rd out of sync reg [DQS_WIDTH-1:0] prbs_tap_mod; //reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps; //reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps; //************************************************************************** // signals for per-bit algorithm of fine_delay calculations //************************************************************************** reg [6*DRAM_WIDTH-1:0] left_edge_pb; //left edge value per bit reg [6*DRAM_WIDTH-1:0] right_edge_pb; //right edge value per bit reg [5*DRAM_WIDTH-1:0] match_flag_pb; //5 consecutive match flag per bit reg [4:0] match_flag_and; //5 consecute match flag of all bits (1: all bit fail) reg [DRAM_WIDTH-1:0] left_edge_found_pb; //left_edge found per bit - use for loss calculation reg [DRAM_WIDTH-1:0] left_edge_updated; //left edge was updated for this PI tap - used for largest left edge /ref bit update reg [DRAM_WIDTH-1:0] right_edge_found_pb; //right_edge found per bit - use for gail calulation and smallest right edge update reg right_edge_found; //smallest right_edge found reg [DRAM_WIDTH*6-1:0] left_loss_pb; //left_edge loss per bit reg [DRAM_WIDTH*6-1:0] right_gain_pb; //right_edge gain per bit reg [DRAM_WIDTH-1:0] ref_bit; //bit number which has largest left edge (with smaller right edge) reg [DRAM_WIDTH-1:0] bit_cnt; //bit number used to calculate ref bit reg [DRAM_WIDTH-1:0] ref_bit_per_bit; //bit flags which have largest left edge reg [5:0] ref_right_edge; //ref_bit right edge - keep the smallest edge of ref bits reg [5:0] largest_left_edge; //biggest left edge of per bit - will be left edge of byte reg [5:0] smallest_right_edge; //smallest right edge of per bit - will be right edge of byte reg [5:0] fine_pi_dec_cnt; //Phase In tap decrement count (to go back to '0' or center) reg [6:0] center_calc; //used for calculate the dec tap for centering reg [5:0] right_edge_ref; //ref_bit right edge reg [5:0] left_edge_ref; //ref_bit left edge reg [DRAM_WIDTH-1:0] compare_err_pb; //compare error per bit reg [DRAM_WIDTH-1:0] compare_err_pb_latch_r; //sticky compare error per bit used for left/right edge reg compare_err_pb_and; //indicate all bit fail reg fine_inc_stage; //fine_inc_stage (1: increment all except ref_bit, 0: only inc for gain bit) reg [1:0] stage_cnt; //stage cnt (0,1: fine delay inc stage, 2: fine delay dec stage) wire fine_calib; //turn on/off fine delay calibration reg [5:0] mem_out_dec; reg [5:0] dec_cnt; reg fine_dly_error; //indicate it has wrong left/right edge wire center_comp; wire pi_adj; //************************************************************************** // DQS count to hard PHY during write calibration using Phaser_OUT Stage2 // coarse delay //************************************************************************** assign pi_stg2_prbs_rdlvl_cnt = prbs_dqs_cnt_r; //fine delay turn on assign fine_calib = (FINE_PER_BIT=="ON")? 1:0; assign center_comp = (CENTER_COMP_MODE == "ON")? 1: 0; assign pi_adj = (PI_VAL_ADJ == "ON")?1:0; assign dbg_prbs_rdlvl[0+:6] = left_edge_pb[0+:6]; assign dbg_prbs_rdlvl[7:6] = left_loss_pb[0+:2]; assign dbg_prbs_rdlvl[8+:6] = left_edge_pb[6+:6]; assign dbg_prbs_rdlvl[15:14] = left_loss_pb[6+:2]; assign dbg_prbs_rdlvl[16+:6] = left_edge_pb[12+:6] ; assign dbg_prbs_rdlvl[23:22] = left_loss_pb[12+:2]; assign dbg_prbs_rdlvl[24+:6] = left_edge_pb[18+:6] ; assign dbg_prbs_rdlvl[31:30] = left_loss_pb[18+:2]; assign dbg_prbs_rdlvl[32+:6] = left_edge_pb[24+:6]; assign dbg_prbs_rdlvl[39:38] = left_loss_pb[24+:2]; assign dbg_prbs_rdlvl[40+:6] = left_edge_pb[30+:6]; assign dbg_prbs_rdlvl[47:46] = left_loss_pb[30+:2]; assign dbg_prbs_rdlvl[48+:6] = left_edge_pb[36+:6]; assign dbg_prbs_rdlvl[55:54] = left_loss_pb[36+:2]; assign dbg_prbs_rdlvl[56+:6] = left_edge_pb[42+:6]; assign dbg_prbs_rdlvl[63:62] = left_loss_pb[42+:2]; assign dbg_prbs_rdlvl[64+:6] = right_edge_pb[0+:6]; assign dbg_prbs_rdlvl[71:70] = right_gain_pb[0+:2]; assign dbg_prbs_rdlvl[72+:6] = right_edge_pb[6+:6] ; assign dbg_prbs_rdlvl[79:78] = right_gain_pb[6+:2]; assign dbg_prbs_rdlvl[80+:6] = right_edge_pb[12+:6]; assign dbg_prbs_rdlvl[87:86] = right_gain_pb[12+:2]; assign dbg_prbs_rdlvl[88+:6] = right_edge_pb[18+:6]; assign dbg_prbs_rdlvl[95:94] = right_gain_pb[18+:2]; assign dbg_prbs_rdlvl[96+:6] = right_edge_pb[24+:6]; assign dbg_prbs_rdlvl[103:102] = right_gain_pb[24+:2]; assign dbg_prbs_rdlvl[104+:6] = right_edge_pb[30+:6]; assign dbg_prbs_rdlvl[111:110] = right_gain_pb[30+:2]; assign dbg_prbs_rdlvl[112+:6] = right_edge_pb[36+:6]; assign dbg_prbs_rdlvl[119:118] = right_gain_pb[36+:2]; assign dbg_prbs_rdlvl[120+:6] = right_edge_pb[42+:6]; assign dbg_prbs_rdlvl[127:126] = right_gain_pb[42+:2]; assign dbg_prbs_rdlvl[128+:6] = pi_counter_read_val; assign dbg_prbs_rdlvl[134+:6] = prbs_dqs_tap_cnt_r; assign dbg_prbs_rdlvl[140] = prbs_found_1st_edge_r; assign dbg_prbs_rdlvl[141] = prbs_found_2nd_edge_r; assign dbg_prbs_rdlvl[142] = compare_err; assign dbg_prbs_rdlvl[143] = phy_if_empty; assign dbg_prbs_rdlvl[144] = prbs_rdlvl_start; assign dbg_prbs_rdlvl[145] = prbs_rdlvl_done; assign dbg_prbs_rdlvl[146+:5] = prbs_dqs_cnt_r; assign dbg_prbs_rdlvl[151+:6] = left_edge_pb[prbs_dqs_cnt_r*6+:6] ; assign dbg_prbs_rdlvl[157+:6] = right_edge_pb[prbs_dqs_cnt_r*6+:6]; assign dbg_prbs_rdlvl[163+:6] = {2'h0,complex_victim_inc, rd_victim_sel[2:0]}; assign dbg_prbs_rdlvl[169+:6] =right_gain_pb[prbs_dqs_cnt_r*6+:6] ; assign dbg_prbs_rdlvl[177:175] = ref_bit[2:0]; assign dbg_prbs_rdlvl[178+:6] = prbs_state_r1[5:0]; assign dbg_prbs_rdlvl[184] = rd_valid_r2; assign dbg_prbs_rdlvl[185] = compare_err_r0; assign dbg_prbs_rdlvl[186] = compare_err_f0; assign dbg_prbs_rdlvl[187] = compare_err_r1; assign dbg_prbs_rdlvl[188] = compare_err_f1; assign dbg_prbs_rdlvl[189] = compare_err_r2; assign dbg_prbs_rdlvl[190] = compare_err_f2; assign dbg_prbs_rdlvl[191] = compare_err_r3; assign dbg_prbs_rdlvl[192] = compare_err_f3; assign dbg_prbs_rdlvl[193+:8] = left_edge_found_pb; assign dbg_prbs_rdlvl[201+:8] = right_edge_found_pb; assign dbg_prbs_rdlvl[209+:6] =largest_left_edge ; assign dbg_prbs_rdlvl[215+:6] =smallest_right_edge ; assign dbg_prbs_rdlvl[221+:8] = fine_delay_incdec_pb; assign dbg_prbs_rdlvl[229] = fine_delay_sel; assign dbg_prbs_rdlvl[230+:8] = compare_err_pb_latch_r; assign dbg_prbs_rdlvl[238+:6] = fine_pi_dec_cnt; assign dbg_prbs_rdlvl[244+:5] = match_flag_and ; assign dbg_prbs_rdlvl[249+:2] =stage_cnt ; assign dbg_prbs_rdlvl[251] = fine_inc_stage ; assign dbg_prbs_rdlvl[252] = compare_err_pb_and ; assign dbg_prbs_rdlvl[253] = right_edge_found ; assign dbg_prbs_rdlvl[254] = fine_dly_error ; assign dbg_prbs_rdlvl[255]= 'b0;//reserved //************************************************************************** // Record first and second edges found during calibration //************************************************************************** generate always @(posedge clk) if (rst) begin dbg_prbs_first_edge_taps <= #TCQ 'b0; dbg_prbs_second_edge_taps <= #TCQ 'b0; end else if (prbs_state_r == PRBS_CALC_TAPS) begin // Record tap counts of first and second edge edges during // calibration for each DQS group. If neither edge has // been found, then those taps will remain 0 if (prbs_found_1st_edge_r) dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] <= #TCQ prbs_1st_edge_taps_r; if (prbs_found_2nd_edge_r) dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] <= #TCQ prbs_2nd_edge_taps_r; end else if (prbs_state_r == FINE_CALC_TAPS) begin if(stage_cnt == 'd2) begin dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] <= #TCQ largest_left_edge; dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6] <= #TCQ smallest_right_edge; end end endgenerate //padded calculation always @ (smallest_right_edge or largest_left_edge) center_calc <= {1'b0, smallest_right_edge} + {1'b0,largest_left_edge}; //*************************************************************************** //*************************************************************************** // Data mux to route appropriate bit to calibration logic - i.e. calibration // is done sequentially, one bit (or DQS group) at a time //*************************************************************************** generate if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; assign compare_data_r0 = compare_data[DQ_WIDTH-1:0]; assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign compare_data_r2 = compare_data[5*DQ_WIDTH-1:4*DQ_WIDTH]; assign compare_data_f2 = compare_data[6*DQ_WIDTH-1:5*DQ_WIDTH]; assign compare_data_r3 = compare_data[7*DQ_WIDTH-1:6*DQ_WIDTH]; assign compare_data_f3 = compare_data[8*DQ_WIDTH-1:7*DQ_WIDTH]; end else begin: rd_data_div2_logic_clk assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0]; assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign compare_data_r0 = compare_data[DQ_WIDTH-1:0]; assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH]; assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH]; assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH]; assign compare_data_r2 = 'h0; assign compare_data_f2 = 'h0; assign compare_data_r3 = 'h0; assign compare_data_f3 = 'h0; end endgenerate always @(posedge clk) begin rd_mux_sel_r <= #TCQ prbs_dqs_cnt_r; end // Register outputs for improved timing. // NOTE: Will need to change when per-bit DQ deskew is supported. // Currenly all bits in DQS group are checked in aggregate generate genvar mux_i; for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd always @(posedge clk) begin mux_rd_rise0_r1[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall0_r1[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise1_r1[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall1_r1[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise2_r1[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall2_r1[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_rise3_r1[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; mux_rd_fall3_r1[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; //Compare data compare_data_rise0_r1[mux_i] <= #TCQ compare_data_r0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; compare_data_fall0_r1[mux_i] <= #TCQ compare_data_f0[DRAM_WIDTH*rd_mux_sel_r + mux_i]; compare_data_rise1_r1[mux_i] <= #TCQ compare_data_r1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; compare_data_fall1_r1[mux_i] <= #TCQ compare_data_f1[DRAM_WIDTH*rd_mux_sel_r + mux_i]; compare_data_rise2_r1[mux_i] <= #TCQ compare_data_r2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; compare_data_fall2_r1[mux_i] <= #TCQ compare_data_f2[DRAM_WIDTH*rd_mux_sel_r + mux_i]; compare_data_rise3_r1[mux_i] <= #TCQ compare_data_r3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; compare_data_fall3_r1[mux_i] <= #TCQ compare_data_f3[DRAM_WIDTH*rd_mux_sel_r + mux_i]; end end endgenerate generate genvar muxr2_i; if (nCK_PER_CLK == 4) begin: gen_mux_div4 for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_4 always @(posedge clk) begin if (mux_rd_valid_r) begin mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i]; mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i]; mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i]; mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i]; mux_rd_rise2_r2[muxr2_i] <= #TCQ mux_rd_rise2_r1[muxr2_i]; mux_rd_fall2_r2[muxr2_i] <= #TCQ mux_rd_fall2_r1[muxr2_i]; mux_rd_rise3_r2[muxr2_i] <= #TCQ mux_rd_rise3_r1[muxr2_i]; mux_rd_fall3_r2[muxr2_i] <= #TCQ mux_rd_fall3_r1[muxr2_i]; end //pipeline stage mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i]; mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i]; mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i]; mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i]; mux_rd_rise2_r3[muxr2_i] <= #TCQ mux_rd_rise2_r2[muxr2_i]; mux_rd_fall2_r3[muxr2_i] <= #TCQ mux_rd_fall2_r2[muxr2_i]; mux_rd_rise3_r3[muxr2_i] <= #TCQ mux_rd_rise3_r2[muxr2_i]; mux_rd_fall3_r3[muxr2_i] <= #TCQ mux_rd_fall3_r2[muxr2_i]; //pipeline stage mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i]; mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i]; mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i]; mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i]; mux_rd_rise2_r4[muxr2_i] <= #TCQ mux_rd_rise2_r3[muxr2_i]; mux_rd_fall2_r4[muxr2_i] <= #TCQ mux_rd_fall2_r3[muxr2_i]; mux_rd_rise3_r4[muxr2_i] <= #TCQ mux_rd_rise3_r3[muxr2_i]; mux_rd_fall3_r4[muxr2_i] <= #TCQ mux_rd_fall3_r3[muxr2_i]; end end end else if (nCK_PER_CLK == 2) begin: gen_mux_div2 for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_2 always @(posedge clk) begin if (mux_rd_valid_r) begin mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i]; mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i]; mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i]; mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i]; mux_rd_rise2_r2[muxr2_i] <= 'h0; mux_rd_fall2_r2[muxr2_i] <= 'h0; mux_rd_rise3_r2[muxr2_i] <= 'h0; mux_rd_fall3_r2[muxr2_i] <= 'h0; end mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i]; mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i]; mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i]; mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i]; mux_rd_rise2_r3[muxr2_i] <= 'h0; mux_rd_fall2_r3[muxr2_i] <= 'h0; mux_rd_rise3_r3[muxr2_i] <= 'h0; mux_rd_fall3_r3[muxr2_i] <= 'h0; //pipeline stage mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i]; mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i]; mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i]; mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i]; mux_rd_rise2_r4[muxr2_i] <= 'h0; mux_rd_fall2_r4[muxr2_i] <= 'h0; mux_rd_rise3_r4[muxr2_i] <= 'h0; mux_rd_fall3_r4[muxr2_i] <= 'h0; end end end endgenerate // Registered signal indicates when mux_rd_rise/fall_r is valid always @(posedge clk) begin mux_rd_valid_r <= #TCQ ~phy_if_empty && prbs_rdlvl_start; rd_valid_r1 <= #TCQ mux_rd_valid_r; rd_valid_r2 <= #TCQ rd_valid_r1; rd_valid_r3 <= #TCQ rd_valid_r2; end // Counter counts # of samples compared // Reset sample counter when not "sampling" // Otherwise, count # of samples compared // Same counter is shared for three samples checked always @(posedge clk) if (rst) samples_cnt_r <= #TCQ 'b0; else if (samples_cnt_r == NUM_SAMPLES_CNT) begin samples_cnt_r <= #TCQ 'b0; end else if (complex_sample_cnt_inc) begin samples_cnt_r <= #TCQ samples_cnt_r + 1; /*if (!rd_valid_r1 || (prbs_state_r == PRBS_DEC_DQS_WAIT) || (prbs_state_r == PRBS_INC_DQS_WAIT) || (prbs_state_r == PRBS_DEC_DQS) || (prbs_state_r == PRBS_INC_DQS) || (samples_cnt_r == NUM_SAMPLES_CNT) || (samples_cnt_r == NUM_SAMPLES_CNT1)) samples_cnt_r <= #TCQ 'b0; else if (rd_valid_r1 && (((samples_cnt_r < NUM_SAMPLES_CNT) && ~samples_cnt1_en_r) || ((samples_cnt_r < NUM_SAMPLES_CNT1) && ~samples_cnt2_en_r) || ((samples_cnt_r < NUM_SAMPLES_CNT2) && samples_cnt2_en_r))) samples_cnt_r <= #TCQ samples_cnt_r + 1;*/ end // Count #2 enable generation // Assert when correct number of samples compared always @(posedge clk) if (rst) samples_cnt1_en_r <= #TCQ 1'b0; else begin if ((prbs_state_r == PRBS_IDLE) || (prbs_state_r == PRBS_DEC_DQS) || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == FINE_PI_INC) || (prbs_state_r == PRBS_NEW_DQS_PREWAIT)) samples_cnt1_en_r <= #TCQ 1'b0; else if ((samples_cnt_r == NUM_SAMPLES_CNT) && rd_valid_r1) samples_cnt1_en_r <= #TCQ 1'b1; end // Counter #3 enable generation // Assert when correct number of samples compared always @(posedge clk) if (rst) samples_cnt2_en_r <= #TCQ 1'b0; else begin if ((prbs_state_r == PRBS_IDLE) || (prbs_state_r == PRBS_DEC_DQS) || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == FINE_PI_INC) || (prbs_state_r == PRBS_NEW_DQS_PREWAIT)) samples_cnt2_en_r <= #TCQ 1'b0; else if ((samples_cnt_r == NUM_SAMPLES_CNT1) && rd_valid_r1 && samples_cnt1_en_r) samples_cnt2_en_r <= #TCQ 1'b1; end // Victim selection logic always @(posedge clk) if (rst) rd_victim_sel <= #TCQ 'd0; else if (num_samples_done_r) rd_victim_sel <= #TCQ 'd0; else if (samples_cnt_r == NUM_SAMPLES_CNT) begin if (rd_victim_sel < 'd7) rd_victim_sel <= #TCQ rd_victim_sel + 1; end // Output row count increment pulse to phy_init always @(posedge clk) if (rst) complex_victim_inc <= #TCQ 1'b0; else if (samples_cnt_r == NUM_SAMPLES_CNT) complex_victim_inc <= #TCQ 1'b1; else complex_victim_inc <= #TCQ 1'b0; generate if (FIXED_VICTIM == "TRUE") begin: victim_fixed always @(posedge clk) if (rst) num_samples_done_r <= #TCQ 1'b0; else if ((prbs_state_r == PRBS_DEC_DQS) || (prbs_state_r == PRBS_INC_DQS)|| (prbs_state_r == FINE_PI_INC) || (prbs_state_r == FINE_PI_DEC)) num_samples_done_r <= #TCQ 'b0; else if (samples_cnt_r == NUM_SAMPLES_CNT) num_samples_done_r <= #TCQ 1'b1; end else begin: victim_not_fixed always @(posedge clk) if (rst) num_samples_done_r <= #TCQ 1'b0; else if ((prbs_state_r == PRBS_DEC_DQS) || (prbs_state_r == PRBS_INC_DQS)|| (prbs_state_r == FINE_PI_INC) || (prbs_state_r == FINE_PI_DEC)) num_samples_done_r <= #TCQ 'b0; else if ((samples_cnt_r == NUM_SAMPLES_CNT) && (rd_victim_sel == 'd7)) num_samples_done_r <= #TCQ 1'b1; end endgenerate //*************************************************************************** // Compare Read Data for the byte being Leveled with Expected data from PRBS // generator. Resulting compare_err signal used to determine read data valid // edge. //*************************************************************************** generate if (nCK_PER_CLK == 4) begin: cmp_err_4to1 always @ (posedge clk) begin if (rst || new_cnt_dqs_r) begin compare_err <= #TCQ 1'b0; compare_err_r0 <= #TCQ 1'b0; compare_err_f0 <= #TCQ 1'b0; compare_err_r1 <= #TCQ 1'b0; compare_err_f1 <= #TCQ 1'b0; compare_err_r2 <= #TCQ 1'b0; compare_err_f2 <= #TCQ 1'b0; compare_err_r3 <= #TCQ 1'b0; compare_err_f3 <= #TCQ 1'b0; end else if (rd_valid_r2) begin compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1); compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1); compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1); compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1); compare_err_r2 <= #TCQ (mux_rd_rise2_r3 != compare_data_rise2_r1); compare_err_f2 <= #TCQ (mux_rd_fall2_r3 != compare_data_fall2_r1); compare_err_r3 <= #TCQ (mux_rd_rise3_r3 != compare_data_rise3_r1); compare_err_f3 <= #TCQ (mux_rd_fall3_r3 != compare_data_fall3_r1); compare_err <= #TCQ (compare_err_r0 | compare_err_f0 | compare_err_r1 | compare_err_f1 | compare_err_r2 | compare_err_f2 | compare_err_r3 | compare_err_f3); end end end else begin: cmp_err_2to1 always @ (posedge clk) begin if (rst || new_cnt_dqs_r) begin compare_err <= #TCQ 1'b0; compare_err_r0 <= #TCQ 1'b0; compare_err_f0 <= #TCQ 1'b0; compare_err_r1 <= #TCQ 1'b0; compare_err_f1 <= #TCQ 1'b0; end else if (rd_valid_r2) begin compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1); compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1); compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1); compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1); compare_err <= #TCQ (compare_err_r0 | compare_err_f0 | compare_err_r1 | compare_err_f1); end end end endgenerate //*************************************************************************** // Decrement initial Phaser_IN fine delay value before proceeding with // read calibration //*************************************************************************** //*************************************************************************** // Demultiplexor to control Phaser_IN delay values //*************************************************************************** // Read DQS always @(posedge clk) begin if (rst) begin pi_en_stg2_f_timing <= #TCQ 'b0; pi_stg2_f_incdec_timing <= #TCQ 'b0; end else if (prbs_tap_en_r) begin // Change only specified DQS pi_en_stg2_f_timing <= #TCQ 1'b1; pi_stg2_f_incdec_timing <= #TCQ prbs_tap_inc_r; end else begin pi_en_stg2_f_timing <= #TCQ 'b0; pi_stg2_f_incdec_timing <= #TCQ 'b0; end end // registered for timing always @(posedge clk) begin pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing; pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing; end //*************************************************************************** // generate request to PHY_INIT logic to issue precharged. Required when // calibration can take a long time (during which there are only constant // reads present on this bus). In this case need to issue perioidic // precharges to avoid tRAS violation. This signal must meet the following // requirements: (1) only transition from 0->1 when prech is first needed, // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted //*************************************************************************** always @(posedge clk) if (rst) prbs_rdlvl_prech_req <= #TCQ 1'b0; else prbs_rdlvl_prech_req <= #TCQ prbs_prech_req_r; //***************************************************************** // keep track of edge tap counts found, and current capture clock // tap count //***************************************************************** always @(posedge clk) if (rst) begin prbs_dqs_tap_cnt_r <= #TCQ 'b0; rdlvl_cpt_tap_cnt <= #TCQ 'b0; end else if (new_cnt_dqs_r) begin prbs_dqs_tap_cnt_r <= #TCQ pi_counter_read_val; rdlvl_cpt_tap_cnt <= #TCQ pi_counter_read_val; end else if (prbs_tap_en_r) begin if (prbs_tap_inc_r) prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r + 1; else if (prbs_dqs_tap_cnt_r != 'd0) prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r - 1; end always @(posedge clk) if (rst) begin prbs_dec_tap_calc_plus_3 <= #TCQ 'b0; prbs_dec_tap_calc_minus_3 <= #TCQ 'b0; end else if (new_cnt_dqs_r) begin prbs_dec_tap_calc_plus_3 <= #TCQ 'b000011; prbs_dec_tap_calc_minus_3 <= #TCQ 'b111100; end else begin prbs_dec_tap_calc_plus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt + 3); prbs_dec_tap_calc_minus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt - 3); end always @(posedge clk) if (rst || new_cnt_dqs_r) prbs_dqs_tap_limit_r <= #TCQ 1'b0; else if (prbs_dqs_tap_cnt_r == 6'd63) prbs_dqs_tap_limit_r <= #TCQ 1'b1; else prbs_dqs_tap_limit_r <= #TCQ 1'b0; // Temp wire for timing. // The following in the always block below causes timing issues // due to DSP block inference // 6*prbs_dqs_cnt_r. // replacing this with two left shifts + one left shift to avoid // DSP multiplier. assign prbs_dqs_cnt_timing = {2'd0, prbs_dqs_cnt_r}; always @(posedge clk) prbs_dqs_cnt_timing_r <= #TCQ prbs_dqs_cnt_timing; // Storing DQS tap values at the end of each DQS read leveling always @(posedge clk) begin if (rst) begin prbs_final_dqs_tap_cnt_r <= #TCQ 'b0; end else if ((prbs_state_r == PRBS_NEXT_DQS) && (prbs_state_r1 != PRBS_NEXT_DQS)) begin prbs_final_dqs_tap_cnt_r[(prbs_dqs_cnt_timing_r*6)+:6] <= #TCQ prbs_dqs_tap_cnt_r; end end //***************************************************************** always @(posedge clk) begin prbs_state_r1 <= #TCQ prbs_state_r; prbs_rdlvl_start_r <= #TCQ prbs_rdlvl_start; end // Wait counter for wait states always @(posedge clk) if ((prbs_state_r == PRBS_NEW_DQS_WAIT) || (prbs_state_r == PRBS_INC_DQS_WAIT) || (prbs_state_r == PRBS_DEC_DQS_WAIT) || (prbs_state_r == FINE_PI_DEC_WAIT) || (prbs_state_r == FINE_PI_INC_WAIT) || (prbs_state_r == PRBS_NEW_DQS_PREWAIT)) wait_state_cnt_en_r <= #TCQ 1'b1; else wait_state_cnt_en_r <= #TCQ 1'b0; always @(posedge clk) if (!wait_state_cnt_en_r) begin wait_state_cnt_r <= #TCQ 'b0; cnt_wait_state <= #TCQ 1'b0; end else begin if (wait_state_cnt_r < 'd15) begin wait_state_cnt_r <= #TCQ wait_state_cnt_r + 1; cnt_wait_state <= #TCQ 1'b0; end else begin // Need to reset to 0 to handle the case when there are two // different WAIT states back-to-back wait_state_cnt_r <= #TCQ 'b0; cnt_wait_state <= #TCQ 1'b1; end end always @ (posedge clk) err_chk_invalid <= #TCQ (wait_state_cnt_r < 'd14); //***************************************************************** // compare error checking per-bit //**************************************************************** generate genvar pb_i; if (nCK_PER_CLK == 4) begin: cmp_err_pb_4to1 for(pb_i=0 ; pb_i<DRAM_WIDTH; pb_i=pb_i+1) begin always @ (posedge clk) begin //prevent error check during PI inc/dec and wait if (rst || new_cnt_dqs_r || (prbs_state_r == FINE_PI_INC) || (prbs_state_r == FINE_PI_DEC) || (err_chk_invalid && ((prbs_state_r == FINE_PI_DEC_WAIT)||(prbs_state_r == FINE_PI_INC_WAIT)))) compare_err_pb[pb_i] <= #TCQ 1'b0; else if (rd_valid_r2) compare_err_pb[pb_i] <= #TCQ (mux_rd_rise0_r3[pb_i] != compare_data_rise0_r1[pb_i]) | (mux_rd_fall0_r3[pb_i] != compare_data_fall0_r1[pb_i]) | (mux_rd_rise1_r3[pb_i] != compare_data_rise1_r1[pb_i]) | (mux_rd_fall1_r3[pb_i] != compare_data_fall1_r1[pb_i]) | (mux_rd_rise2_r3[pb_i] != compare_data_rise2_r1[pb_i]) | (mux_rd_fall2_r3[pb_i] != compare_data_fall2_r1[pb_i]) | (mux_rd_rise3_r3[pb_i] != compare_data_rise3_r1[pb_i]) | (mux_rd_fall3_r3[pb_i] != compare_data_fall3_r1[pb_i]) ; end //always end //for end else begin: cmp_err_pb_2to1 for(pb_i=0 ; pb_i<DRAM_WIDTH; pb_i=pb_i+1) begin always @ (posedge clk) begin if (rst || new_cnt_dqs_r || (prbs_state_r == FINE_PI_INC) || (prbs_state_r == FINE_PI_DEC) || (err_chk_invalid && ((prbs_state_r == FINE_PI_DEC_WAIT)||(prbs_state_r == FINE_PI_INC_WAIT)))) compare_err_pb[pb_i] <= #TCQ 1'b0; else if (rd_valid_r2) compare_err_pb[pb_i] <= #TCQ (mux_rd_rise0_r3[pb_i] != compare_data_rise0_r1[pb_i]) | (mux_rd_fall0_r3[pb_i] != compare_data_fall0_r1[pb_i]) | (mux_rd_rise1_r3[pb_i] != compare_data_rise1_r1[pb_i]) | (mux_rd_fall1_r3[pb_i] != compare_data_fall1_r1[pb_i]) ; end //always end //for end //if endgenerate //checking all bit has error always @ (posedge clk) begin if(rst || new_cnt_dqs_r) begin compare_err_pb_and <= #TCQ 1'b0; end else begin compare_err_pb_and <= #TCQ &compare_err_pb; end end //generate stick error bit - left/right edge generate genvar pb_r; for(pb_r=0; pb_r<DRAM_WIDTH; pb_r=pb_r+1) begin always @ (posedge clk) begin if((prbs_state_r == FINE_PI_INC) | (prbs_state_r == FINE_PI_DEC) | (~cnt_wait_state && ((prbs_state_r == FINE_PI_INC_WAIT)|(prbs_state_r == FINE_PI_DEC_WAIT)))) compare_err_pb_latch_r[pb_r] <= #TCQ 1'b0; else compare_err_pb_latch_r[pb_r] <= #TCQ compare_err_pb[pb_r]? 1'b1:compare_err_pb_latch_r[pb_r]; end end endgenerate //in stage 0, if left edge found, update ref_bit (one hot) always @ (posedge clk) begin if (rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin ref_bit_per_bit <= #TCQ 'd0; end else if ((prbs_state_r == FINE_PI_INC) && (stage_cnt=='b0)) begin if(|left_edge_updated) ref_bit_per_bit <= #TCQ left_edge_updated; end end //ref bit with samllest right edge //if bit 1 and 3 are set to ref_bit_per_bit but bit 1 has smaller right edge, bit is selected as ref_bit always @ (posedge clk) begin if(rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin bit_cnt <= #TCQ 'd0; ref_right_edge <= #TCQ 6'h3f; ref_bit <= #TCQ 'd0; end else if ((prbs_state_r == FINE_CALC_TAPS_WAIT) && (stage_cnt == 'b0) && (bit_cnt < DRAM_WIDTH)) begin bit_cnt <= #TCQ bit_cnt +'b1; if ((ref_bit_per_bit[bit_cnt]==1'b1) && (right_edge_pb[bit_cnt*6+:6]<= ref_right_edge)) begin ref_bit <= #TCQ bit_cnt; ref_right_edge <= #TCQ right_edge_pb[bit_cnt*6+:6]; end end end //pipe lining for reference bit left/right edge always @ (posedge clk) begin left_edge_ref <= #TCQ left_edge_pb[ref_bit*6+:6]; right_edge_ref <= #TCQ right_edge_pb[ref_bit*6+:6]; end //left_edge/right_edge/left_loss/right_gain update generate genvar eg; for(eg=0; eg<DRAM_WIDTH; eg = eg+1) begin always @ (posedge clk) begin if(rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin match_flag_pb[eg*5+:5] <= #TCQ 5'h1f; left_edge_pb[eg*6+:6] <= #TCQ 'b0; right_edge_pb[eg*6+:6] <= #TCQ 6'h3f; left_edge_found_pb[eg] <= #TCQ 1'b0; right_edge_found_pb[eg] <= #TCQ 1'b0; left_loss_pb[eg*6+:6] <= #TCQ 'b0; right_gain_pb[eg*6+:6] <= #TCQ 'b0; left_edge_updated[eg] <= #TCQ 'b0; end else begin if((prbs_state_r == FINE_PAT_COMPARE_PER_BIT) && (num_samples_done_r || compare_err_pb_and)) begin //left edge is updated when match flag becomes 100000 (1 fail , 5 success) if(match_flag_pb[eg*5+:5]==5'b10000 && compare_err_pb_latch_r[eg]==0) begin left_edge_pb[eg*6+:6] <= #TCQ prbs_dqs_tap_cnt_r-4; left_edge_found_pb[eg] <= #TCQ 1'b1; //used for update largest_left_edge left_edge_updated[eg] <= #TCQ 1'b1; //check the loss of bit - update only for left edge found if(~left_edge_found_pb[eg]) left_loss_pb[eg*6+:6] <= #TCQ (left_edge_ref > prbs_dqs_tap_cnt_r - 4)? 'd0 : prbs_dqs_tap_cnt_r-4-left_edge_ref; //right edge is updated when match flag becomes 000001 (5 success, 1 fail) end else if (match_flag_pb[eg*5+:5]==5'b00000 && compare_err_pb_latch_r[eg]) begin right_edge_pb[eg*6+:6] <= #TCQ prbs_dqs_tap_cnt_r-1; right_edge_found_pb[eg] <= #TCQ 1'b1; //check the gain of bit - update only for right edge found if(~right_edge_found_pb[eg]) right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > prbs_dqs_tap_cnt_r-1)? ((right_edge_pb[eg*6 +:6] > prbs_dqs_tap_cnt_r-1)? 0: prbs_dqs_tap_cnt_r-1- right_edge_pb[eg*6+:6]): ((right_edge_pb[eg*6+:6] > right_edge_ref)? 0 : right_edge_ref - right_edge_pb[eg*6+:6]); //no right edge found end else if (prbs_dqs_tap_cnt_r == 6'h3f && ~right_edge_found_pb[eg]) begin right_edge_pb[eg*6+:6] <= #TCQ 6'h3f; right_edge_found_pb[eg] <= #TCQ 1'b1; //right edge at 63. gain = max(0, ref_bit_right_tap - prev_right_edge) right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > right_edge_pb[eg*6+:6])? (right_edge_ref - right_edge_pb[eg*6+:6]) : 0; end //update match flag - shift and update match_flag_pb[eg*5+:5] <= #TCQ {match_flag_pb[(eg*5)+:4],compare_err_pb_latch_r[eg]}; end else if (prbs_state_r == FINE_PI_DEC) begin left_edge_found_pb[eg] <= #TCQ 1'b0; right_edge_found_pb[eg] <= #TCQ 1'b0; left_loss_pb[eg*6+:6] <= #TCQ 'b0; right_gain_pb[eg*6+:6] <= #TCQ 'b0; match_flag_pb[eg*5+:5] <= #TCQ 5'h1f; //new fix end else if (prbs_state_r == FINE_PI_INC) begin left_edge_updated[eg] <= #TCQ 'b0; //used only for update largest ref_bit and largest_left_edge end end end //always end //for endgenerate //update fine_delay according to loss/gain value per bit generate genvar f_pb; for(f_pb=0; f_pb<DRAM_WIDTH; f_pb=f_pb+1) begin always @ (posedge clk) begin if(rst | prbs_state_r == PRBS_NEW_DQS_WAIT ) begin fine_delay_incdec_pb[f_pb] <= #TCQ 1'b0; end else if((prbs_state_r == FINE_CALC_TAPS_WAIT) && (bit_cnt == DRAM_WIDTH)) begin if(stage_cnt == 'd0) fine_delay_incdec_pb[f_pb] <= #TCQ (f_pb==ref_bit)? 1'b0:1'b1; //only for initial stage else if(stage_cnt == 'd1) fine_delay_incdec_pb[f_pb] <= #TCQ (right_gain_pb[f_pb*6+:6]>left_loss_pb[f_pb*6+:6])?1'b1:1'b0; end end end endgenerate //fine inc stage (stage cnt 0,1,2), fine dec stage (stage cnt 3) always @ (posedge clk) begin if (rst) fine_inc_stage <= #TCQ 'b1; else fine_inc_stage <= #TCQ (stage_cnt!='d3); end //***************************************************************** always @(posedge clk) if (rst) begin prbs_dqs_cnt_r <= #TCQ 'b0; prbs_tap_en_r <= #TCQ 1'b0; prbs_tap_inc_r <= #TCQ 1'b0; prbs_prech_req_r <= #TCQ 1'b0; prbs_state_r <= #TCQ PRBS_IDLE; prbs_found_1st_edge_r <= #TCQ 1'b0; prbs_found_2nd_edge_r <= #TCQ 1'b0; prbs_1st_edge_taps_r <= #TCQ 6'bxxxxxx; prbs_inc_tap_cnt <= #TCQ 'b0; prbs_dec_tap_cnt <= #TCQ 'b0; new_cnt_dqs_r <= #TCQ 1'b0; if (SIM_CAL_OPTION == "FAST_CAL") prbs_rdlvl_done <= #TCQ 1'b1; else prbs_rdlvl_done <= #TCQ 1'b0; prbs_2nd_edge_taps_r <= #TCQ 6'bxxxxxx; prbs_last_byte_done <= #TCQ 1'b0; prbs_tap_mod <= #TCQ 'd0; reset_rd_addr <= #TCQ 'b0; read_pause <= #TCQ 'b0; fine_pi_dec_cnt <= #TCQ 'b0; match_flag_and <= #TCQ 5'h1f; stage_cnt <= #TCQ 2'b00; right_edge_found <= #TCQ 1'b0; largest_left_edge <= #TCQ 6'b000000; smallest_right_edge <= #TCQ 6'b111111; num_samples_done_ind <= #TCQ 'b0; fine_delay_sel <= #TCQ 'b0; fine_dly_error <= #TCQ 'b0; end else begin case (prbs_state_r) PRBS_IDLE: begin prbs_last_byte_done <= #TCQ 1'b0; prbs_prech_req_r <= #TCQ 1'b0; if (prbs_rdlvl_start && ~prbs_rdlvl_start_r) begin if (SIM_CAL_OPTION == "SKIP_CAL" || SIM_CAL_OPTION == "FAST_CAL") begin prbs_state_r <= #TCQ PRBS_DONE; reset_rd_addr <= #TCQ 1'b1; end else begin new_cnt_dqs_r <= #TCQ 1'b1; prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT; fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//. end end end // Wait for the new DQS group to change // also gives time for the read data IN_FIFO to // output the updated data for the new DQS group PRBS_NEW_DQS_WAIT: begin reset_rd_addr <= #TCQ 'b0; prbs_last_byte_done <= #TCQ 1'b0; prbs_prech_req_r <= #TCQ 1'b0; //fine_inc_stage <= #TCQ 1'b1; stage_cnt <= #TCQ 2'b0; match_flag_and <= #TCQ 5'h1f; if (cnt_wait_state) begin new_cnt_dqs_r <= #TCQ 1'b0; prbs_state_r <= #TCQ fine_calib? FINE_PI_DEC:PRBS_PAT_COMPARE; end end // Check for presence of data eye edge. During this state, we // sample the read data multiple times, and look for changes // in the read data, specifically: // 1. A change in the read data compared with the value of // read data from the previous delay tap. This indicates // that the most recent tap delay increment has moved us // into either a new window, or moved/kept us in the // transition/jitter region between windows. Note that this // condition only needs to be checked for once, and for // logistical purposes, we check this soon after entering // this state (see comment in PRBS_PAT_COMPARE below for // why this is done) // 2. A change in the read data while we are in this state // (i.e. in the absence of a tap delay increment). This // indicates that we're close enough to a window edge that // jitter will cause the read data to change even in the // absence of a tap delay change PRBS_PAT_COMPARE: begin // Continue to sample read data and look for edges until the // appropriate time interval (shorter for simulation-only, // much, much longer for actual h/w) has elapsed if (num_samples_done_r || compare_err) begin if (prbs_dqs_tap_limit_r) // Only one edge detected and ran out of taps since only one // bit time worth of taps available for window detection. This // can happen if at tap 0 DQS is in previous window which results // in only left edge being detected. Or at tap 0 DQS is in the // current window resulting in only right edge being detected. // Depending on the frequency this case can also happen if at // tap 0 DQS is in the left noise region resulting in only left // edge being detected. prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; else if (compare_err || (prbs_dqs_tap_cnt_r == 'd0)) begin // Sticky bit - asserted after we encounter an edge, although // the current edge may not be considered the "first edge" this // just means we found at least one edge prbs_found_1st_edge_r <= #TCQ 1'b1; // Both edges of data valid window found: // If we've found a second edge after a region of stability // then we must have just passed the second ("right" edge of // the window. Record this second_edge_taps = current tap-1, // because we're one past the actual second edge tap, where // the edge taps represent the extremes of the data valid // window (i.e. smallest & largest taps where data still valid if (prbs_found_1st_edge_r) begin prbs_found_2nd_edge_r <= #TCQ 1'b1; prbs_2nd_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r - 1; prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; end else begin // Otherwise, an edge was found (just not the "second" edge) // Assuming DQS is in the correct window at tap 0 of Phaser IN // fine tap. The first edge found is the right edge of the valid // window and is the beginning of the jitter region hence done! if (compare_err) prbs_1st_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r + 1; else prbs_1st_edge_taps_r <= #TCQ 'd0; prbs_inc_tap_cnt <= #TCQ rdlvl_cpt_tap_cnt - prbs_dqs_tap_cnt_r; prbs_state_r <= #TCQ PRBS_INC_DQS; end end else begin // Otherwise, if we haven't found an edge.... // If we still have taps left to use, then keep incrementing if (prbs_found_1st_edge_r) prbs_state_r <= #TCQ PRBS_INC_DQS; else prbs_state_r <= #TCQ PRBS_DEC_DQS; end end end // Increment Phaser_IN delay for DQS PRBS_INC_DQS: begin prbs_state_r <= #TCQ PRBS_INC_DQS_WAIT; if (prbs_inc_tap_cnt > 'd0) prbs_inc_tap_cnt <= #TCQ prbs_inc_tap_cnt - 1; if (~prbs_dqs_tap_limit_r) begin prbs_tap_en_r <= #TCQ 1'b1; prbs_tap_inc_r <= #TCQ 1'b1; end end // Wait for Phaser_In to settle, before checking again for an edge PRBS_INC_DQS_WAIT: begin prbs_tap_en_r <= #TCQ 1'b0; prbs_tap_inc_r <= #TCQ 1'b0; if (cnt_wait_state) begin if (prbs_inc_tap_cnt > 'd0) prbs_state_r <= #TCQ PRBS_INC_DQS; else prbs_state_r <= #TCQ PRBS_PAT_COMPARE; end end // Calculate final value of Phaser_IN taps. At this point, one or both // edges of data eye have been found, and/or all taps have been // exhausted looking for the edges // NOTE: The amount to be decrement by is calculated, not the // absolute setting for DQS. // CENTER compensation with shift by 1 PRBS_CALC_TAPS: begin if (center_comp) begin prbs_dec_tap_cnt <= #TCQ (dec_cnt[5] & dec_cnt[0])? 'd32: dec_cnt + pi_adj; fine_dly_error <= #TCQ (dec_cnt[5] & dec_cnt[0])? 1'b1: fine_dly_error; //sticky bit read_pause <= #TCQ 'b1; prbs_state_r <= #TCQ PRBS_DEC_DQS; end else begin //No center compensation if (prbs_found_2nd_edge_r && prbs_found_1st_edge_r) // Both edges detected prbs_dec_tap_cnt <= #TCQ ((prbs_2nd_edge_taps_r - prbs_1st_edge_taps_r)>>1) + 1 + pi_adj; else if (~prbs_found_2nd_edge_r && prbs_found_1st_edge_r) // Only left edge detected prbs_dec_tap_cnt <= #TCQ ((prbs_dqs_tap_cnt_r - prbs_1st_edge_taps_r)>>1) + pi_adj; else // No edges detected prbs_dec_tap_cnt <= #TCQ (prbs_dqs_tap_cnt_r>>1) + pi_adj; // Now use the value we just calculated to decrement CPT taps // to the desired calibration point read_pause <= #TCQ 'b1; prbs_state_r <= #TCQ PRBS_DEC_DQS; end end // decrement capture clock for final adjustment - center // capture clock in middle of data eye. This adjustment will occur // only when both the edges are found usign CPT taps. Must do this // incrementally to avoid clock glitching (since CPT drives clock // divider within each ISERDES) PRBS_DEC_DQS: begin prbs_tap_en_r <= #TCQ 1'b1; prbs_tap_inc_r <= #TCQ 1'b0; // once adjustment is complete, we're done with calibration for // this DQS, repeat for next DQS if (prbs_dec_tap_cnt > 'd0) prbs_dec_tap_cnt <= #TCQ prbs_dec_tap_cnt - 1; if (prbs_dec_tap_cnt == 6'b000001) prbs_state_r <= #TCQ PRBS_NEXT_DQS; else prbs_state_r <= #TCQ PRBS_DEC_DQS_WAIT; end PRBS_DEC_DQS_WAIT: begin prbs_tap_en_r <= #TCQ 1'b0; prbs_tap_inc_r <= #TCQ 1'b0; if (cnt_wait_state) begin if (prbs_dec_tap_cnt > 'd0) prbs_state_r <= #TCQ PRBS_DEC_DQS; else prbs_state_r <= #TCQ PRBS_PAT_COMPARE; end end // Determine whether we're done, or have more DQS's to calibrate // Also request precharge after every byte, as appropriate PRBS_NEXT_DQS: begin read_pause <= #TCQ 'b0; reset_rd_addr <= #TCQ 'b1; prbs_prech_req_r <= #TCQ 1'b1; prbs_tap_en_r <= #TCQ 1'b0; prbs_tap_inc_r <= #TCQ 1'b0; // Prepare for another iteration with next DQS group prbs_found_1st_edge_r <= #TCQ 1'b0; prbs_found_2nd_edge_r <= #TCQ 1'b0; prbs_1st_edge_taps_r <= #TCQ 'd0; prbs_2nd_edge_taps_r <= #TCQ 'd0; largest_left_edge <= #TCQ 6'b000000; smallest_right_edge <= #TCQ 6'b111111; if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin prbs_last_byte_done <= #TCQ 1'b1; end // Wait until precharge that occurs in between calibration of // DQS groups is finished if (prech_done) begin prbs_prech_req_r <= #TCQ 1'b0; if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin // All DQS groups done prbs_state_r <= #TCQ PRBS_DONE; end else begin // Process next DQS group new_cnt_dqs_r <= #TCQ 1'b1; //fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//. prbs_dqs_cnt_r <= #TCQ prbs_dqs_cnt_r + 1; prbs_state_r <= #TCQ PRBS_NEW_DQS_PREWAIT; end end end PRBS_NEW_DQS_PREWAIT: begin if (cnt_wait_state) begin prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT; fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//. end end PRBS_CALC_TAPS_PRE: begin if(num_samples_done_r) begin prbs_state_r <= #TCQ fine_calib? PRBS_NEXT_DQS:PRBS_CALC_TAPS_WAIT; if(center_comp && ~fine_calib) begin if(prbs_found_1st_edge_r) largest_left_edge <= #TCQ prbs_1st_edge_taps_r; else largest_left_edge <= #TCQ 6'd0; if(prbs_found_2nd_edge_r) smallest_right_edge <= #TCQ prbs_2nd_edge_taps_r; else smallest_right_edge <= #TCQ 6'd63; end end end //wait for center compensation PRBS_CALC_TAPS_WAIT: begin prbs_state_r <= #TCQ PRBS_CALC_TAPS; end //if it is fine_inc stage (first/second stage): dec to 0 //if it is fine_dec stage (third stage): dec to center FINE_PI_DEC: begin fine_delay_sel <= #TCQ 'b0; if(fine_pi_dec_cnt > 0) begin prbs_tap_en_r <= #TCQ 1'b1; prbs_tap_inc_r <= #TCQ 1'b0; fine_pi_dec_cnt <= #TCQ fine_pi_dec_cnt - 'd1; end prbs_state_r <= #TCQ FINE_PI_DEC_WAIT; end //wait for phaser_in tap decrement. //if first/second stage is done, goes to FINE_PI_INC //if last stage is done, goes to NEXT_DQS FINE_PI_DEC_WAIT: begin prbs_tap_en_r <= #TCQ 1'b0; prbs_tap_inc_r <= #TCQ 1'b0; if(cnt_wait_state) begin if(fine_pi_dec_cnt >0) prbs_state_r <= #TCQ FINE_PI_DEC; else if(fine_inc_stage) // prbs_state_r <= #TCQ FINE_PI_INC; //for temp change prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT; //start from pi tap "0" else prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; //finish the process and go to the next DQS end end FINE_PI_INC: begin if(|left_edge_updated) largest_left_edge <= #TCQ prbs_dqs_tap_cnt_r-4; if(|right_edge_found_pb && ~right_edge_found) begin smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r -1 ; right_edge_found <= #TCQ 'b1; end //left_edge_found_pb <= #TCQ {DRAM_WIDTH{1'b0}}; prbs_state_r <= #TCQ FINE_PI_INC_WAIT; if(~prbs_dqs_tap_limit_r) begin prbs_tap_en_r <= #TCQ 1'b1; prbs_tap_inc_r <= #TCQ 1'b1; end end //wait for phase_in tap increment //need to do pattern compare for every bit FINE_PI_INC_WAIT: begin prbs_tap_en_r <= #TCQ 1'b0; prbs_tap_inc_r <= #TCQ 1'b0; if (cnt_wait_state) begin prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT; end end //compare per bit data and update flags,left/right edge FINE_PAT_COMPARE_PER_BIT: begin if(num_samples_done_r || compare_err_pb_and) begin //update and_flag - shift and add match_flag_and <= #TCQ {match_flag_and[3:0],compare_err_pb_and}; //if it is consecutive 5 passing taps followed by fail or tap limit (finish the search) //don't go to fine_FINE_CALC_TAPS to prevent to skip whole stage //Or if all right edge are found if((match_flag_and == 5'b00000 && compare_err_pb_and && (prbs_dqs_tap_cnt_r > 5)) || prbs_dqs_tap_limit_r || (&right_edge_found_pb)) begin prbs_state_r <= #TCQ FINE_CALC_TAPS; //if all right edge are alined (all right edge found at the same time), update smallest right edge in here //doesnt need to set right_edge_found to 1 since it is not used after this stage if(!right_edge_found) smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r-1; end else begin prbs_state_r <= #TCQ FINE_PI_INC; //keep increase until all fail end num_samples_done_ind <= num_samples_done_r; end end //for fine_inc stage, inc all fine delay //for fine_dec stage, apply dec fine delay for specific bits (by calculating the loss/gain) // put phaser_in taps to the center FINE_CALC_TAPS: begin if(num_samples_done_ind || num_samples_done_r) begin num_samples_done_ind <= #TCQ 'b0; //indicate num_samples_done_r is set right_edge_found <= #TCQ 1'b0; //reset right edge found match_flag_and <= #TCQ 5'h1f; //reset match flag for all bits prbs_state_r <= #TCQ FINE_CALC_TAPS_WAIT; end end FINE_CALC_TAPS_WAIT: begin //wait for ROM read out if(stage_cnt == 'd2) begin //last stage : back to center if(center_comp) begin fine_pi_dec_cnt <= #TCQ (dec_cnt[5]&dec_cnt[0])? 'd32: prbs_dqs_tap_cnt_r - smallest_right_edge + dec_cnt - 1 + pi_adj ; //going to the center value & shift by 1 fine_dly_error <= #TCQ (dec_cnt[5]&dec_cnt[0]) ? 1'b1: fine_dly_error; end else begin fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r - center_calc[6:1] - center_calc[0] + pi_adj; //going to the center value & shift left by 1 fine_dly_error <= #TCQ 1'b0; end end else begin fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r; end if (bit_cnt == DRAM_WIDTH) begin fine_delay_sel <= #TCQ 'b1; stage_cnt <= #TCQ stage_cnt + 1; prbs_state_r <= #TCQ FINE_PI_DEC; end end // Done with this stage of calibration PRBS_DONE: begin prbs_prech_req_r <= #TCQ 1'b0; prbs_last_byte_done <= #TCQ 1'b0; prbs_rdlvl_done <= #TCQ 1'b1; reset_rd_addr <= #TCQ 1'b0; end endcase end //ROM generation for dec counter always @ (largest_left_edge or smallest_right_edge) begin case ({largest_left_edge, smallest_right_edge}) 12'd0 : mem_out_dec = 6'b111111; 12'd1 : mem_out_dec = 6'b111111; 12'd2 : mem_out_dec = 6'b111111; 12'd3 : mem_out_dec = 6'b111111; 12'd4 : mem_out_dec = 6'b111111; 12'd5 : mem_out_dec = 6'b111111; 12'd6 : mem_out_dec = 6'b000100; 12'd7 : mem_out_dec = 6'b000101; 12'd8 : mem_out_dec = 6'b000101; 12'd9 : mem_out_dec = 6'b000110; 12'd10 : mem_out_dec = 6'b000110; 12'd11 : mem_out_dec = 6'b000111; 12'd12 : mem_out_dec = 6'b001000; 12'd13 : mem_out_dec = 6'b001000; 12'd14 : mem_out_dec = 6'b001001; 12'd15 : mem_out_dec = 6'b001010; 12'd16 : mem_out_dec = 6'b001010; 12'd17 : mem_out_dec = 6'b001011; 12'd18 : mem_out_dec = 6'b001011; 12'd19 : mem_out_dec = 6'b001100; 12'd20 : mem_out_dec = 6'b001100; 12'd21 : mem_out_dec = 6'b001100; 12'd22 : mem_out_dec = 6'b001100; 12'd23 : mem_out_dec = 6'b001101; 12'd24 : mem_out_dec = 6'b001100; 12'd25 : mem_out_dec = 6'b001100; 12'd26 : mem_out_dec = 6'b001101; 12'd27 : mem_out_dec = 6'b001110; 12'd28 : mem_out_dec = 6'b001110; 12'd29 : mem_out_dec = 6'b001111; 12'd30 : mem_out_dec = 6'b010000; 12'd31 : mem_out_dec = 6'b010001; 12'd32 : mem_out_dec = 6'b010001; 12'd33 : mem_out_dec = 6'b010010; 12'd34 : mem_out_dec = 6'b010010; 12'd35 : mem_out_dec = 6'b010010; 12'd36 : mem_out_dec = 6'b010011; 12'd37 : mem_out_dec = 6'b010100; 12'd38 : mem_out_dec = 6'b010100; 12'd39 : mem_out_dec = 6'b010101; 12'd40 : mem_out_dec = 6'b010101; 12'd41 : mem_out_dec = 6'b010110; 12'd42 : mem_out_dec = 6'b010110; 12'd43 : mem_out_dec = 6'b010111; 12'd44 : mem_out_dec = 6'b011000; 12'd45 : mem_out_dec = 6'b011001; 12'd46 : mem_out_dec = 6'b011001; 12'd47 : mem_out_dec = 6'b011010; 12'd48 : mem_out_dec = 6'b011010; 12'd49 : mem_out_dec = 6'b011011; 12'd50 : mem_out_dec = 6'b011011; 12'd51 : mem_out_dec = 6'b011100; 12'd52 : mem_out_dec = 6'b011100; 12'd53 : mem_out_dec = 6'b011100; 12'd54 : mem_out_dec = 6'b011100; 12'd55 : mem_out_dec = 6'b011100; 12'd56 : mem_out_dec = 6'b011100; 12'd57 : mem_out_dec = 6'b011100; 12'd58 : mem_out_dec = 6'b011100; 12'd59 : mem_out_dec = 6'b011101; 12'd60 : mem_out_dec = 6'b011110; 12'd61 : mem_out_dec = 6'b011111; 12'd62 : mem_out_dec = 6'b100000; 12'd63 : mem_out_dec = 6'b100000; 12'd64 : mem_out_dec = 6'b111111; 12'd65 : mem_out_dec = 6'b111111; 12'd66 : mem_out_dec = 6'b111111; 12'd67 : mem_out_dec = 6'b111111; 12'd68 : mem_out_dec = 6'b111111; 12'd69 : mem_out_dec = 6'b111111; 12'd70 : mem_out_dec = 6'b111111; 12'd71 : mem_out_dec = 6'b000100; 12'd72 : mem_out_dec = 6'b000100; 12'd73 : mem_out_dec = 6'b000101; 12'd74 : mem_out_dec = 6'b000110; 12'd75 : mem_out_dec = 6'b000111; 12'd76 : mem_out_dec = 6'b000111; 12'd77 : mem_out_dec = 6'b001000; 12'd78 : mem_out_dec = 6'b001001; 12'd79 : mem_out_dec = 6'b001001; 12'd80 : mem_out_dec = 6'b001010; 12'd81 : mem_out_dec = 6'b001010; 12'd82 : mem_out_dec = 6'b001011; 12'd83 : mem_out_dec = 6'b001011; 12'd84 : mem_out_dec = 6'b001011; 12'd85 : mem_out_dec = 6'b001011; 12'd86 : mem_out_dec = 6'b001011; 12'd87 : mem_out_dec = 6'b001100; 12'd88 : mem_out_dec = 6'b001011; 12'd89 : mem_out_dec = 6'b001100; 12'd90 : mem_out_dec = 6'b001100; 12'd91 : mem_out_dec = 6'b001101; 12'd92 : mem_out_dec = 6'b001110; 12'd93 : mem_out_dec = 6'b001111; 12'd94 : mem_out_dec = 6'b001111; 12'd95 : mem_out_dec = 6'b010000; 12'd96 : mem_out_dec = 6'b010001; 12'd97 : mem_out_dec = 6'b010001; 12'd98 : mem_out_dec = 6'b010010; 12'd99 : mem_out_dec = 6'b010010; 12'd100 : mem_out_dec = 6'b010011; 12'd101 : mem_out_dec = 6'b010011; 12'd102 : mem_out_dec = 6'b010100; 12'd103 : mem_out_dec = 6'b010100; 12'd104 : mem_out_dec = 6'b010100; 12'd105 : mem_out_dec = 6'b010101; 12'd106 : mem_out_dec = 6'b010110; 12'd107 : mem_out_dec = 6'b010111; 12'd108 : mem_out_dec = 6'b010111; 12'd109 : mem_out_dec = 6'b011000; 12'd110 : mem_out_dec = 6'b011001; 12'd111 : mem_out_dec = 6'b011001; 12'd112 : mem_out_dec = 6'b011010; 12'd113 : mem_out_dec = 6'b011010; 12'd114 : mem_out_dec = 6'b011011; 12'd115 : mem_out_dec = 6'b011011; 12'd116 : mem_out_dec = 6'b011011; 12'd117 : mem_out_dec = 6'b011011; 12'd118 : mem_out_dec = 6'b011011; 12'd119 : mem_out_dec = 6'b011011; 12'd120 : mem_out_dec = 6'b011011; 12'd121 : mem_out_dec = 6'b011011; 12'd122 : mem_out_dec = 6'b011100; 12'd123 : mem_out_dec = 6'b011101; 12'd124 : mem_out_dec = 6'b011110; 12'd125 : mem_out_dec = 6'b011110; 12'd126 : mem_out_dec = 6'b011111; 12'd127 : mem_out_dec = 6'b100000; 12'd128 : mem_out_dec = 6'b111111; 12'd129 : mem_out_dec = 6'b111111; 12'd130 : mem_out_dec = 6'b111111; 12'd131 : mem_out_dec = 6'b111111; 12'd132 : mem_out_dec = 6'b111111; 12'd133 : mem_out_dec = 6'b111111; 12'd134 : mem_out_dec = 6'b111111; 12'd135 : mem_out_dec = 6'b111111; 12'd136 : mem_out_dec = 6'b000100; 12'd137 : mem_out_dec = 6'b000101; 12'd138 : mem_out_dec = 6'b000101; 12'd139 : mem_out_dec = 6'b000110; 12'd140 : mem_out_dec = 6'b000110; 12'd141 : mem_out_dec = 6'b000111; 12'd142 : mem_out_dec = 6'b001000; 12'd143 : mem_out_dec = 6'b001001; 12'd144 : mem_out_dec = 6'b001001; 12'd145 : mem_out_dec = 6'b001010; 12'd146 : mem_out_dec = 6'b001010; 12'd147 : mem_out_dec = 6'b001010; 12'd148 : mem_out_dec = 6'b001010; 12'd149 : mem_out_dec = 6'b001010; 12'd150 : mem_out_dec = 6'b001010; 12'd151 : mem_out_dec = 6'b001011; 12'd152 : mem_out_dec = 6'b001010; 12'd153 : mem_out_dec = 6'b001011; 12'd154 : mem_out_dec = 6'b001100; 12'd155 : mem_out_dec = 6'b001101; 12'd156 : mem_out_dec = 6'b001101; 12'd157 : mem_out_dec = 6'b001110; 12'd158 : mem_out_dec = 6'b001111; 12'd159 : mem_out_dec = 6'b010000; 12'd160 : mem_out_dec = 6'b010000; 12'd161 : mem_out_dec = 6'b010001; 12'd162 : mem_out_dec = 6'b010001; 12'd163 : mem_out_dec = 6'b010010; 12'd164 : mem_out_dec = 6'b010010; 12'd165 : mem_out_dec = 6'b010011; 12'd166 : mem_out_dec = 6'b010011; 12'd167 : mem_out_dec = 6'b010100; 12'd168 : mem_out_dec = 6'b010100; 12'd169 : mem_out_dec = 6'b010101; 12'd170 : mem_out_dec = 6'b010101; 12'd171 : mem_out_dec = 6'b010110; 12'd172 : mem_out_dec = 6'b010111; 12'd173 : mem_out_dec = 6'b010111; 12'd174 : mem_out_dec = 6'b011000; 12'd175 : mem_out_dec = 6'b011001; 12'd176 : mem_out_dec = 6'b011001; 12'd177 : mem_out_dec = 6'b011010; 12'd178 : mem_out_dec = 6'b011010; 12'd179 : mem_out_dec = 6'b011010; 12'd180 : mem_out_dec = 6'b011010; 12'd181 : mem_out_dec = 6'b011010; 12'd182 : mem_out_dec = 6'b011010; 12'd183 : mem_out_dec = 6'b011010; 12'd184 : mem_out_dec = 6'b011010; 12'd185 : mem_out_dec = 6'b011011; 12'd186 : mem_out_dec = 6'b011100; 12'd187 : mem_out_dec = 6'b011100; 12'd188 : mem_out_dec = 6'b011101; 12'd189 : mem_out_dec = 6'b011110; 12'd190 : mem_out_dec = 6'b011111; 12'd191 : mem_out_dec = 6'b100000; 12'd192 : mem_out_dec = 6'b111111; 12'd193 : mem_out_dec = 6'b111111; 12'd194 : mem_out_dec = 6'b111111; 12'd195 : mem_out_dec = 6'b111111; 12'd196 : mem_out_dec = 6'b111111; 12'd197 : mem_out_dec = 6'b111111; 12'd198 : mem_out_dec = 6'b111111; 12'd199 : mem_out_dec = 6'b111111; 12'd200 : mem_out_dec = 6'b111111; 12'd201 : mem_out_dec = 6'b000100; 12'd202 : mem_out_dec = 6'b000100; 12'd203 : mem_out_dec = 6'b000101; 12'd204 : mem_out_dec = 6'b000110; 12'd205 : mem_out_dec = 6'b000111; 12'd206 : mem_out_dec = 6'b001000; 12'd207 : mem_out_dec = 6'b001000; 12'd208 : mem_out_dec = 6'b001001; 12'd209 : mem_out_dec = 6'b001001; 12'd210 : mem_out_dec = 6'b001001; 12'd211 : mem_out_dec = 6'b001001; 12'd212 : mem_out_dec = 6'b001001; 12'd213 : mem_out_dec = 6'b001001; 12'd214 : mem_out_dec = 6'b001001; 12'd215 : mem_out_dec = 6'b001010; 12'd216 : mem_out_dec = 6'b001010; 12'd217 : mem_out_dec = 6'b001011; 12'd218 : mem_out_dec = 6'b001011; 12'd219 : mem_out_dec = 6'b001100; 12'd220 : mem_out_dec = 6'b001101; 12'd221 : mem_out_dec = 6'b001110; 12'd222 : mem_out_dec = 6'b001111; 12'd223 : mem_out_dec = 6'b001111; 12'd224 : mem_out_dec = 6'b010000; 12'd225 : mem_out_dec = 6'b010000; 12'd226 : mem_out_dec = 6'b010001; 12'd227 : mem_out_dec = 6'b010001; 12'd228 : mem_out_dec = 6'b010010; 12'd229 : mem_out_dec = 6'b010010; 12'd230 : mem_out_dec = 6'b010011; 12'd231 : mem_out_dec = 6'b010011; 12'd232 : mem_out_dec = 6'b010011; 12'd233 : mem_out_dec = 6'b010100; 12'd234 : mem_out_dec = 6'b010100; 12'd235 : mem_out_dec = 6'b010101; 12'd236 : mem_out_dec = 6'b010110; 12'd237 : mem_out_dec = 6'b010111; 12'd238 : mem_out_dec = 6'b011000; 12'd239 : mem_out_dec = 6'b011000; 12'd240 : mem_out_dec = 6'b011001; 12'd241 : mem_out_dec = 6'b011001; 12'd242 : mem_out_dec = 6'b011001; 12'd243 : mem_out_dec = 6'b011001; 12'd244 : mem_out_dec = 6'b011001; 12'd245 : mem_out_dec = 6'b011001; 12'd246 : mem_out_dec = 6'b011001; 12'd247 : mem_out_dec = 6'b011001; 12'd248 : mem_out_dec = 6'b011010; 12'd249 : mem_out_dec = 6'b011010; 12'd250 : mem_out_dec = 6'b011011; 12'd251 : mem_out_dec = 6'b011100; 12'd252 : mem_out_dec = 6'b011101; 12'd253 : mem_out_dec = 6'b011110; 12'd254 : mem_out_dec = 6'b011110; 12'd255 : mem_out_dec = 6'b011111; 12'd256 : mem_out_dec = 6'b111111; 12'd257 : mem_out_dec = 6'b111111; 12'd258 : mem_out_dec = 6'b111111; 12'd259 : mem_out_dec = 6'b111111; 12'd260 : mem_out_dec = 6'b111111; 12'd261 : mem_out_dec = 6'b111111; 12'd262 : mem_out_dec = 6'b111111; 12'd263 : mem_out_dec = 6'b111111; 12'd264 : mem_out_dec = 6'b111111; 12'd265 : mem_out_dec = 6'b111111; 12'd266 : mem_out_dec = 6'b000100; 12'd267 : mem_out_dec = 6'b000101; 12'd268 : mem_out_dec = 6'b000110; 12'd269 : mem_out_dec = 6'b000110; 12'd270 : mem_out_dec = 6'b000111; 12'd271 : mem_out_dec = 6'b001000; 12'd272 : mem_out_dec = 6'b001000; 12'd273 : mem_out_dec = 6'b001000; 12'd274 : mem_out_dec = 6'b001000; 12'd275 : mem_out_dec = 6'b001000; 12'd276 : mem_out_dec = 6'b001000; 12'd277 : mem_out_dec = 6'b001000; 12'd278 : mem_out_dec = 6'b001000; 12'd279 : mem_out_dec = 6'b001001; 12'd280 : mem_out_dec = 6'b001001; 12'd281 : mem_out_dec = 6'b001010; 12'd282 : mem_out_dec = 6'b001011; 12'd283 : mem_out_dec = 6'b001100; 12'd284 : mem_out_dec = 6'b001101; 12'd285 : mem_out_dec = 6'b001101; 12'd286 : mem_out_dec = 6'b001110; 12'd287 : mem_out_dec = 6'b001111; 12'd288 : mem_out_dec = 6'b001111; 12'd289 : mem_out_dec = 6'b010000; 12'd290 : mem_out_dec = 6'b010000; 12'd291 : mem_out_dec = 6'b010001; 12'd292 : mem_out_dec = 6'b010001; 12'd293 : mem_out_dec = 6'b010010; 12'd294 : mem_out_dec = 6'b010010; 12'd295 : mem_out_dec = 6'b010011; 12'd296 : mem_out_dec = 6'b010010; 12'd297 : mem_out_dec = 6'b010011; 12'd298 : mem_out_dec = 6'b010100; 12'd299 : mem_out_dec = 6'b010101; 12'd300 : mem_out_dec = 6'b010110; 12'd301 : mem_out_dec = 6'b010110; 12'd302 : mem_out_dec = 6'b010111; 12'd303 : mem_out_dec = 6'b011000; 12'd304 : mem_out_dec = 6'b011000; 12'd305 : mem_out_dec = 6'b011000; 12'd306 : mem_out_dec = 6'b011000; 12'd307 : mem_out_dec = 6'b011000; 12'd308 : mem_out_dec = 6'b011000; 12'd309 : mem_out_dec = 6'b011000; 12'd310 : mem_out_dec = 6'b011000; 12'd311 : mem_out_dec = 6'b011001; 12'd312 : mem_out_dec = 6'b011001; 12'd313 : mem_out_dec = 6'b011010; 12'd314 : mem_out_dec = 6'b011011; 12'd315 : mem_out_dec = 6'b011100; 12'd316 : mem_out_dec = 6'b011100; 12'd317 : mem_out_dec = 6'b011101; 12'd318 : mem_out_dec = 6'b011110; 12'd319 : mem_out_dec = 6'b011111; 12'd320 : mem_out_dec = 6'b111111; 12'd321 : mem_out_dec = 6'b111111; 12'd322 : mem_out_dec = 6'b111111; 12'd323 : mem_out_dec = 6'b111111; 12'd324 : mem_out_dec = 6'b111111; 12'd325 : mem_out_dec = 6'b111111; 12'd326 : mem_out_dec = 6'b111111; 12'd327 : mem_out_dec = 6'b111111; 12'd328 : mem_out_dec = 6'b111111; 12'd329 : mem_out_dec = 6'b111111; 12'd330 : mem_out_dec = 6'b111111; 12'd331 : mem_out_dec = 6'b000100; 12'd332 : mem_out_dec = 6'b000101; 12'd333 : mem_out_dec = 6'b000110; 12'd334 : mem_out_dec = 6'b000111; 12'd335 : mem_out_dec = 6'b001000; 12'd336 : mem_out_dec = 6'b000111; 12'd337 : mem_out_dec = 6'b000111; 12'd338 : mem_out_dec = 6'b000111; 12'd339 : mem_out_dec = 6'b000111; 12'd340 : mem_out_dec = 6'b000111; 12'd341 : mem_out_dec = 6'b000111; 12'd342 : mem_out_dec = 6'b001000; 12'd343 : mem_out_dec = 6'b001001; 12'd344 : mem_out_dec = 6'b001001; 12'd345 : mem_out_dec = 6'b001010; 12'd346 : mem_out_dec = 6'b001011; 12'd347 : mem_out_dec = 6'b001011; 12'd348 : mem_out_dec = 6'b001100; 12'd349 : mem_out_dec = 6'b001101; 12'd350 : mem_out_dec = 6'b001110; 12'd351 : mem_out_dec = 6'b001110; 12'd352 : mem_out_dec = 6'b001111; 12'd353 : mem_out_dec = 6'b001111; 12'd354 : mem_out_dec = 6'b010000; 12'd355 : mem_out_dec = 6'b010000; 12'd356 : mem_out_dec = 6'b010001; 12'd357 : mem_out_dec = 6'b010001; 12'd358 : mem_out_dec = 6'b010001; 12'd359 : mem_out_dec = 6'b010010; 12'd360 : mem_out_dec = 6'b010010; 12'd361 : mem_out_dec = 6'b010011; 12'd362 : mem_out_dec = 6'b010100; 12'd363 : mem_out_dec = 6'b010100; 12'd364 : mem_out_dec = 6'b010101; 12'd365 : mem_out_dec = 6'b010110; 12'd366 : mem_out_dec = 6'b010111; 12'd367 : mem_out_dec = 6'b011000; 12'd368 : mem_out_dec = 6'b010111; 12'd369 : mem_out_dec = 6'b010111; 12'd370 : mem_out_dec = 6'b010111; 12'd371 : mem_out_dec = 6'b010111; 12'd372 : mem_out_dec = 6'b010111; 12'd373 : mem_out_dec = 6'b010111; 12'd374 : mem_out_dec = 6'b011000; 12'd375 : mem_out_dec = 6'b011001; 12'd376 : mem_out_dec = 6'b011001; 12'd377 : mem_out_dec = 6'b011010; 12'd378 : mem_out_dec = 6'b011010; 12'd379 : mem_out_dec = 6'b011011; 12'd380 : mem_out_dec = 6'b011100; 12'd381 : mem_out_dec = 6'b011101; 12'd382 : mem_out_dec = 6'b011101; 12'd383 : mem_out_dec = 6'b011110; 12'd384 : mem_out_dec = 6'b111111; 12'd385 : mem_out_dec = 6'b111111; 12'd386 : mem_out_dec = 6'b111111; 12'd387 : mem_out_dec = 6'b111111; 12'd388 : mem_out_dec = 6'b111111; 12'd389 : mem_out_dec = 6'b111111; 12'd390 : mem_out_dec = 6'b111111; 12'd391 : mem_out_dec = 6'b111111; 12'd392 : mem_out_dec = 6'b111111; 12'd393 : mem_out_dec = 6'b111111; 12'd394 : mem_out_dec = 6'b111111; 12'd395 : mem_out_dec = 6'b111111; 12'd396 : mem_out_dec = 6'b000101; 12'd397 : mem_out_dec = 6'b000110; 12'd398 : mem_out_dec = 6'b000110; 12'd399 : mem_out_dec = 6'b000111; 12'd400 : mem_out_dec = 6'b000110; 12'd401 : mem_out_dec = 6'b000110; 12'd402 : mem_out_dec = 6'b000110; 12'd403 : mem_out_dec = 6'b000110; 12'd404 : mem_out_dec = 6'b000110; 12'd405 : mem_out_dec = 6'b000111; 12'd406 : mem_out_dec = 6'b001000; 12'd407 : mem_out_dec = 6'b001000; 12'd408 : mem_out_dec = 6'b001001; 12'd409 : mem_out_dec = 6'b001001; 12'd410 : mem_out_dec = 6'b001010; 12'd411 : mem_out_dec = 6'b001011; 12'd412 : mem_out_dec = 6'b001100; 12'd413 : mem_out_dec = 6'b001100; 12'd414 : mem_out_dec = 6'b001101; 12'd415 : mem_out_dec = 6'b001110; 12'd416 : mem_out_dec = 6'b001110; 12'd417 : mem_out_dec = 6'b001111; 12'd418 : mem_out_dec = 6'b001111; 12'd419 : mem_out_dec = 6'b010000; 12'd420 : mem_out_dec = 6'b010000; 12'd421 : mem_out_dec = 6'b010000; 12'd422 : mem_out_dec = 6'b010001; 12'd423 : mem_out_dec = 6'b010001; 12'd424 : mem_out_dec = 6'b010010; 12'd425 : mem_out_dec = 6'b010011; 12'd426 : mem_out_dec = 6'b010011; 12'd427 : mem_out_dec = 6'b010100; 12'd428 : mem_out_dec = 6'b010101; 12'd429 : mem_out_dec = 6'b010110; 12'd430 : mem_out_dec = 6'b010111; 12'd431 : mem_out_dec = 6'b010111; 12'd432 : mem_out_dec = 6'b010110; 12'd433 : mem_out_dec = 6'b010110; 12'd434 : mem_out_dec = 6'b010110; 12'd435 : mem_out_dec = 6'b010110; 12'd436 : mem_out_dec = 6'b010110; 12'd437 : mem_out_dec = 6'b010111; 12'd438 : mem_out_dec = 6'b010111; 12'd439 : mem_out_dec = 6'b011000; 12'd440 : mem_out_dec = 6'b011001; 12'd441 : mem_out_dec = 6'b011001; 12'd442 : mem_out_dec = 6'b011010; 12'd443 : mem_out_dec = 6'b011011; 12'd444 : mem_out_dec = 6'b011011; 12'd445 : mem_out_dec = 6'b011100; 12'd446 : mem_out_dec = 6'b011101; 12'd447 : mem_out_dec = 6'b011110; 12'd448 : mem_out_dec = 6'b111111; 12'd449 : mem_out_dec = 6'b111111; 12'd450 : mem_out_dec = 6'b111111; 12'd451 : mem_out_dec = 6'b111111; 12'd452 : mem_out_dec = 6'b111111; 12'd453 : mem_out_dec = 6'b111111; 12'd454 : mem_out_dec = 6'b111111; 12'd455 : mem_out_dec = 6'b111111; 12'd456 : mem_out_dec = 6'b111111; 12'd457 : mem_out_dec = 6'b111111; 12'd458 : mem_out_dec = 6'b111111; 12'd459 : mem_out_dec = 6'b111111; 12'd460 : mem_out_dec = 6'b111111; 12'd461 : mem_out_dec = 6'b000101; 12'd462 : mem_out_dec = 6'b000110; 12'd463 : mem_out_dec = 6'b000110; 12'd464 : mem_out_dec = 6'b000110; 12'd465 : mem_out_dec = 6'b000110; 12'd466 : mem_out_dec = 6'b000110; 12'd467 : mem_out_dec = 6'b000110; 12'd468 : mem_out_dec = 6'b000110; 12'd469 : mem_out_dec = 6'b000111; 12'd470 : mem_out_dec = 6'b000111; 12'd471 : mem_out_dec = 6'b001000; 12'd472 : mem_out_dec = 6'b001000; 12'd473 : mem_out_dec = 6'b001001; 12'd474 : mem_out_dec = 6'b001010; 12'd475 : mem_out_dec = 6'b001011; 12'd476 : mem_out_dec = 6'b001011; 12'd477 : mem_out_dec = 6'b001100; 12'd478 : mem_out_dec = 6'b001101; 12'd479 : mem_out_dec = 6'b001110; 12'd480 : mem_out_dec = 6'b001110; 12'd481 : mem_out_dec = 6'b001110; 12'd482 : mem_out_dec = 6'b001111; 12'd483 : mem_out_dec = 6'b001111; 12'd484 : mem_out_dec = 6'b010000; 12'd485 : mem_out_dec = 6'b010000; 12'd486 : mem_out_dec = 6'b010000; 12'd487 : mem_out_dec = 6'b010001; 12'd488 : mem_out_dec = 6'b010001; 12'd489 : mem_out_dec = 6'b010010; 12'd490 : mem_out_dec = 6'b010011; 12'd491 : mem_out_dec = 6'b010100; 12'd492 : mem_out_dec = 6'b010101; 12'd493 : mem_out_dec = 6'b010101; 12'd494 : mem_out_dec = 6'b010110; 12'd495 : mem_out_dec = 6'b010110; 12'd496 : mem_out_dec = 6'b010110; 12'd497 : mem_out_dec = 6'b010110; 12'd498 : mem_out_dec = 6'b010101; 12'd499 : mem_out_dec = 6'b010101; 12'd500 : mem_out_dec = 6'b010110; 12'd501 : mem_out_dec = 6'b010111; 12'd502 : mem_out_dec = 6'b010111; 12'd503 : mem_out_dec = 6'b011000; 12'd504 : mem_out_dec = 6'b011000; 12'd505 : mem_out_dec = 6'b011001; 12'd506 : mem_out_dec = 6'b011010; 12'd507 : mem_out_dec = 6'b011010; 12'd508 : mem_out_dec = 6'b011011; 12'd509 : mem_out_dec = 6'b011100; 12'd510 : mem_out_dec = 6'b011101; 12'd511 : mem_out_dec = 6'b011101; 12'd512 : mem_out_dec = 6'b111111; 12'd513 : mem_out_dec = 6'b111111; 12'd514 : mem_out_dec = 6'b111111; 12'd515 : mem_out_dec = 6'b111111; 12'd516 : mem_out_dec = 6'b111111; 12'd517 : mem_out_dec = 6'b111111; 12'd518 : mem_out_dec = 6'b111111; 12'd519 : mem_out_dec = 6'b111111; 12'd520 : mem_out_dec = 6'b111111; 12'd521 : mem_out_dec = 6'b111111; 12'd522 : mem_out_dec = 6'b111111; 12'd523 : mem_out_dec = 6'b111111; 12'd524 : mem_out_dec = 6'b111111; 12'd525 : mem_out_dec = 6'b111111; 12'd526 : mem_out_dec = 6'b000100; 12'd527 : mem_out_dec = 6'b000101; 12'd528 : mem_out_dec = 6'b000100; 12'd529 : mem_out_dec = 6'b000100; 12'd530 : mem_out_dec = 6'b000100; 12'd531 : mem_out_dec = 6'b000101; 12'd532 : mem_out_dec = 6'b000101; 12'd533 : mem_out_dec = 6'b000110; 12'd534 : mem_out_dec = 6'b000111; 12'd535 : mem_out_dec = 6'b000111; 12'd536 : mem_out_dec = 6'b000111; 12'd537 : mem_out_dec = 6'b001000; 12'd538 : mem_out_dec = 6'b001001; 12'd539 : mem_out_dec = 6'b001010; 12'd540 : mem_out_dec = 6'b001011; 12'd541 : mem_out_dec = 6'b001011; 12'd542 : mem_out_dec = 6'b001100; 12'd543 : mem_out_dec = 6'b001101; 12'd544 : mem_out_dec = 6'b001101; 12'd545 : mem_out_dec = 6'b001101; 12'd546 : mem_out_dec = 6'b001110; 12'd547 : mem_out_dec = 6'b001110; 12'd548 : mem_out_dec = 6'b001110; 12'd549 : mem_out_dec = 6'b001111; 12'd550 : mem_out_dec = 6'b010000; 12'd551 : mem_out_dec = 6'b010000; 12'd552 : mem_out_dec = 6'b010001; 12'd553 : mem_out_dec = 6'b010001; 12'd554 : mem_out_dec = 6'b010010; 12'd555 : mem_out_dec = 6'b010010; 12'd556 : mem_out_dec = 6'b010011; 12'd557 : mem_out_dec = 6'b010100; 12'd558 : mem_out_dec = 6'b010100; 12'd559 : mem_out_dec = 6'b010100; 12'd560 : mem_out_dec = 6'b010100; 12'd561 : mem_out_dec = 6'b010100; 12'd562 : mem_out_dec = 6'b010100; 12'd563 : mem_out_dec = 6'b010101; 12'd564 : mem_out_dec = 6'b010101; 12'd565 : mem_out_dec = 6'b010110; 12'd566 : mem_out_dec = 6'b010111; 12'd567 : mem_out_dec = 6'b010111; 12'd568 : mem_out_dec = 6'b010111; 12'd569 : mem_out_dec = 6'b011000; 12'd570 : mem_out_dec = 6'b011001; 12'd571 : mem_out_dec = 6'b011010; 12'd572 : mem_out_dec = 6'b011010; 12'd573 : mem_out_dec = 6'b011011; 12'd574 : mem_out_dec = 6'b011100; 12'd575 : mem_out_dec = 6'b011101; 12'd576 : mem_out_dec = 6'b111111; 12'd577 : mem_out_dec = 6'b111111; 12'd578 : mem_out_dec = 6'b111111; 12'd579 : mem_out_dec = 6'b111111; 12'd580 : mem_out_dec = 6'b111111; 12'd581 : mem_out_dec = 6'b111111; 12'd582 : mem_out_dec = 6'b111111; 12'd583 : mem_out_dec = 6'b111111; 12'd584 : mem_out_dec = 6'b111111; 12'd585 : mem_out_dec = 6'b111111; 12'd586 : mem_out_dec = 6'b111111; 12'd587 : mem_out_dec = 6'b111111; 12'd588 : mem_out_dec = 6'b111111; 12'd589 : mem_out_dec = 6'b111111; 12'd590 : mem_out_dec = 6'b111111; 12'd591 : mem_out_dec = 6'b000100; 12'd592 : mem_out_dec = 6'b000011; 12'd593 : mem_out_dec = 6'b000011; 12'd594 : mem_out_dec = 6'b000100; 12'd595 : mem_out_dec = 6'b000101; 12'd596 : mem_out_dec = 6'b000101; 12'd597 : mem_out_dec = 6'b000110; 12'd598 : mem_out_dec = 6'b000110; 12'd599 : mem_out_dec = 6'b000111; 12'd600 : mem_out_dec = 6'b000111; 12'd601 : mem_out_dec = 6'b001000; 12'd602 : mem_out_dec = 6'b001001; 12'd603 : mem_out_dec = 6'b001010; 12'd604 : mem_out_dec = 6'b001010; 12'd605 : mem_out_dec = 6'b001011; 12'd606 : mem_out_dec = 6'b001100; 12'd607 : mem_out_dec = 6'b001101; 12'd608 : mem_out_dec = 6'b001101; 12'd609 : mem_out_dec = 6'b001101; 12'd610 : mem_out_dec = 6'b001110; 12'd611 : mem_out_dec = 6'b001110; 12'd612 : mem_out_dec = 6'b001110; 12'd613 : mem_out_dec = 6'b001111; 12'd614 : mem_out_dec = 6'b010000; 12'd615 : mem_out_dec = 6'b010000; 12'd616 : mem_out_dec = 6'b010000; 12'd617 : mem_out_dec = 6'b010001; 12'd618 : mem_out_dec = 6'b010001; 12'd619 : mem_out_dec = 6'b010010; 12'd620 : mem_out_dec = 6'b010010; 12'd621 : mem_out_dec = 6'b010011; 12'd622 : mem_out_dec = 6'b010011; 12'd623 : mem_out_dec = 6'b010100; 12'd624 : mem_out_dec = 6'b010011; 12'd625 : mem_out_dec = 6'b010011; 12'd626 : mem_out_dec = 6'b010100; 12'd627 : mem_out_dec = 6'b010100; 12'd628 : mem_out_dec = 6'b010101; 12'd629 : mem_out_dec = 6'b010110; 12'd630 : mem_out_dec = 6'b010110; 12'd631 : mem_out_dec = 6'b010111; 12'd632 : mem_out_dec = 6'b010111; 12'd633 : mem_out_dec = 6'b011000; 12'd634 : mem_out_dec = 6'b011001; 12'd635 : mem_out_dec = 6'b011001; 12'd636 : mem_out_dec = 6'b011010; 12'd637 : mem_out_dec = 6'b011011; 12'd638 : mem_out_dec = 6'b011100; 12'd639 : mem_out_dec = 6'b011100; 12'd640 : mem_out_dec = 6'b111111; 12'd641 : mem_out_dec = 6'b111111; 12'd642 : mem_out_dec = 6'b111111; 12'd643 : mem_out_dec = 6'b111111; 12'd644 : mem_out_dec = 6'b111111; 12'd645 : mem_out_dec = 6'b111111; 12'd646 : mem_out_dec = 6'b111111; 12'd647 : mem_out_dec = 6'b111111; 12'd648 : mem_out_dec = 6'b111111; 12'd649 : mem_out_dec = 6'b111111; 12'd650 : mem_out_dec = 6'b111111; 12'd651 : mem_out_dec = 6'b111111; 12'd652 : mem_out_dec = 6'b111111; 12'd653 : mem_out_dec = 6'b111111; 12'd654 : mem_out_dec = 6'b111111; 12'd655 : mem_out_dec = 6'b111111; 12'd656 : mem_out_dec = 6'b000011; 12'd657 : mem_out_dec = 6'b000011; 12'd658 : mem_out_dec = 6'b000100; 12'd659 : mem_out_dec = 6'b000100; 12'd660 : mem_out_dec = 6'b000101; 12'd661 : mem_out_dec = 6'b000110; 12'd662 : mem_out_dec = 6'b000110; 12'd663 : mem_out_dec = 6'b000111; 12'd664 : mem_out_dec = 6'b000111; 12'd665 : mem_out_dec = 6'b001000; 12'd666 : mem_out_dec = 6'b001001; 12'd667 : mem_out_dec = 6'b001001; 12'd668 : mem_out_dec = 6'b001010; 12'd669 : mem_out_dec = 6'b001011; 12'd670 : mem_out_dec = 6'b001100; 12'd671 : mem_out_dec = 6'b001100; 12'd672 : mem_out_dec = 6'b001100; 12'd673 : mem_out_dec = 6'b001101; 12'd674 : mem_out_dec = 6'b001101; 12'd675 : mem_out_dec = 6'b001101; 12'd676 : mem_out_dec = 6'b001110; 12'd677 : mem_out_dec = 6'b001111; 12'd678 : mem_out_dec = 6'b001111; 12'd679 : mem_out_dec = 6'b010000; 12'd680 : mem_out_dec = 6'b010000; 12'd681 : mem_out_dec = 6'b010000; 12'd682 : mem_out_dec = 6'b010001; 12'd683 : mem_out_dec = 6'b010001; 12'd684 : mem_out_dec = 6'b010010; 12'd685 : mem_out_dec = 6'b010010; 12'd686 : mem_out_dec = 6'b010011; 12'd687 : mem_out_dec = 6'b010011; 12'd688 : mem_out_dec = 6'b010011; 12'd689 : mem_out_dec = 6'b010011; 12'd690 : mem_out_dec = 6'b010100; 12'd691 : mem_out_dec = 6'b010100; 12'd692 : mem_out_dec = 6'b010101; 12'd693 : mem_out_dec = 6'b010101; 12'd694 : mem_out_dec = 6'b010110; 12'd695 : mem_out_dec = 6'b010111; 12'd696 : mem_out_dec = 6'b010111; 12'd697 : mem_out_dec = 6'b011000; 12'd698 : mem_out_dec = 6'b011000; 12'd699 : mem_out_dec = 6'b011001; 12'd700 : mem_out_dec = 6'b011010; 12'd701 : mem_out_dec = 6'b011011; 12'd702 : mem_out_dec = 6'b011011; 12'd703 : mem_out_dec = 6'b011100; 12'd704 : mem_out_dec = 6'b111111; 12'd705 : mem_out_dec = 6'b111111; 12'd706 : mem_out_dec = 6'b111111; 12'd707 : mem_out_dec = 6'b111111; 12'd708 : mem_out_dec = 6'b111111; 12'd709 : mem_out_dec = 6'b111111; 12'd710 : mem_out_dec = 6'b111111; 12'd711 : mem_out_dec = 6'b111111; 12'd712 : mem_out_dec = 6'b111111; 12'd713 : mem_out_dec = 6'b111111; 12'd714 : mem_out_dec = 6'b111111; 12'd715 : mem_out_dec = 6'b111111; 12'd716 : mem_out_dec = 6'b111111; 12'd717 : mem_out_dec = 6'b111111; 12'd718 : mem_out_dec = 6'b111111; 12'd719 : mem_out_dec = 6'b111111; 12'd720 : mem_out_dec = 6'b111111; 12'd721 : mem_out_dec = 6'b000011; 12'd722 : mem_out_dec = 6'b000100; 12'd723 : mem_out_dec = 6'b000100; 12'd724 : mem_out_dec = 6'b000101; 12'd725 : mem_out_dec = 6'b000101; 12'd726 : mem_out_dec = 6'b000110; 12'd727 : mem_out_dec = 6'b000111; 12'd728 : mem_out_dec = 6'b000111; 12'd729 : mem_out_dec = 6'b000111; 12'd730 : mem_out_dec = 6'b001000; 12'd731 : mem_out_dec = 6'b001001; 12'd732 : mem_out_dec = 6'b001010; 12'd733 : mem_out_dec = 6'b001011; 12'd734 : mem_out_dec = 6'b001011; 12'd735 : mem_out_dec = 6'b001100; 12'd736 : mem_out_dec = 6'b001100; 12'd737 : mem_out_dec = 6'b001101; 12'd738 : mem_out_dec = 6'b001101; 12'd739 : mem_out_dec = 6'b001101; 12'd740 : mem_out_dec = 6'b001110; 12'd741 : mem_out_dec = 6'b001110; 12'd742 : mem_out_dec = 6'b001111; 12'd743 : mem_out_dec = 6'b010000; 12'd744 : mem_out_dec = 6'b001111; 12'd745 : mem_out_dec = 6'b010000; 12'd746 : mem_out_dec = 6'b010000; 12'd747 : mem_out_dec = 6'b010001; 12'd748 : mem_out_dec = 6'b010001; 12'd749 : mem_out_dec = 6'b010010; 12'd750 : mem_out_dec = 6'b010010; 12'd751 : mem_out_dec = 6'b010011; 12'd752 : mem_out_dec = 6'b010010; 12'd753 : mem_out_dec = 6'b010011; 12'd754 : mem_out_dec = 6'b010011; 12'd755 : mem_out_dec = 6'b010100; 12'd756 : mem_out_dec = 6'b010101; 12'd757 : mem_out_dec = 6'b010101; 12'd758 : mem_out_dec = 6'b010110; 12'd759 : mem_out_dec = 6'b010110; 12'd760 : mem_out_dec = 6'b010111; 12'd761 : mem_out_dec = 6'b010111; 12'd762 : mem_out_dec = 6'b011000; 12'd763 : mem_out_dec = 6'b011001; 12'd764 : mem_out_dec = 6'b011010; 12'd765 : mem_out_dec = 6'b011010; 12'd766 : mem_out_dec = 6'b011011; 12'd767 : mem_out_dec = 6'b011100; 12'd768 : mem_out_dec = 6'b111111; 12'd769 : mem_out_dec = 6'b111111; 12'd770 : mem_out_dec = 6'b111111; 12'd771 : mem_out_dec = 6'b111111; 12'd772 : mem_out_dec = 6'b111111; 12'd773 : mem_out_dec = 6'b111111; 12'd774 : mem_out_dec = 6'b111111; 12'd775 : mem_out_dec = 6'b111111; 12'd776 : mem_out_dec = 6'b111111; 12'd777 : mem_out_dec = 6'b111111; 12'd778 : mem_out_dec = 6'b111111; 12'd779 : mem_out_dec = 6'b111111; 12'd780 : mem_out_dec = 6'b111111; 12'd781 : mem_out_dec = 6'b111111; 12'd782 : mem_out_dec = 6'b111111; 12'd783 : mem_out_dec = 6'b111111; 12'd784 : mem_out_dec = 6'b111111; 12'd785 : mem_out_dec = 6'b111111; 12'd786 : mem_out_dec = 6'b000011; 12'd787 : mem_out_dec = 6'b000100; 12'd788 : mem_out_dec = 6'b000101; 12'd789 : mem_out_dec = 6'b000101; 12'd790 : mem_out_dec = 6'b000110; 12'd791 : mem_out_dec = 6'b000110; 12'd792 : mem_out_dec = 6'b000110; 12'd793 : mem_out_dec = 6'b000111; 12'd794 : mem_out_dec = 6'b001000; 12'd795 : mem_out_dec = 6'b001001; 12'd796 : mem_out_dec = 6'b001010; 12'd797 : mem_out_dec = 6'b001010; 12'd798 : mem_out_dec = 6'b001011; 12'd799 : mem_out_dec = 6'b001100; 12'd800 : mem_out_dec = 6'b001100; 12'd801 : mem_out_dec = 6'b001100; 12'd802 : mem_out_dec = 6'b001101; 12'd803 : mem_out_dec = 6'b001101; 12'd804 : mem_out_dec = 6'b001110; 12'd805 : mem_out_dec = 6'b001110; 12'd806 : mem_out_dec = 6'b001111; 12'd807 : mem_out_dec = 6'b010000; 12'd808 : mem_out_dec = 6'b001111; 12'd809 : mem_out_dec = 6'b001111; 12'd810 : mem_out_dec = 6'b010000; 12'd811 : mem_out_dec = 6'b010000; 12'd812 : mem_out_dec = 6'b010001; 12'd813 : mem_out_dec = 6'b010001; 12'd814 : mem_out_dec = 6'b010010; 12'd815 : mem_out_dec = 6'b010010; 12'd816 : mem_out_dec = 6'b010010; 12'd817 : mem_out_dec = 6'b010011; 12'd818 : mem_out_dec = 6'b010011; 12'd819 : mem_out_dec = 6'b010100; 12'd820 : mem_out_dec = 6'b010100; 12'd821 : mem_out_dec = 6'b010101; 12'd822 : mem_out_dec = 6'b010110; 12'd823 : mem_out_dec = 6'b010110; 12'd824 : mem_out_dec = 6'b010110; 12'd825 : mem_out_dec = 6'b010111; 12'd826 : mem_out_dec = 6'b011000; 12'd827 : mem_out_dec = 6'b011001; 12'd828 : mem_out_dec = 6'b011001; 12'd829 : mem_out_dec = 6'b011010; 12'd830 : mem_out_dec = 6'b011011; 12'd831 : mem_out_dec = 6'b011100; 12'd832 : mem_out_dec = 6'b111111; 12'd833 : mem_out_dec = 6'b111111; 12'd834 : mem_out_dec = 6'b111111; 12'd835 : mem_out_dec = 6'b111111; 12'd836 : mem_out_dec = 6'b111111; 12'd837 : mem_out_dec = 6'b111111; 12'd838 : mem_out_dec = 6'b111111; 12'd839 : mem_out_dec = 6'b111111; 12'd840 : mem_out_dec = 6'b111111; 12'd841 : mem_out_dec = 6'b111111; 12'd842 : mem_out_dec = 6'b111111; 12'd843 : mem_out_dec = 6'b111111; 12'd844 : mem_out_dec = 6'b111111; 12'd845 : mem_out_dec = 6'b111111; 12'd846 : mem_out_dec = 6'b111111; 12'd847 : mem_out_dec = 6'b111111; 12'd848 : mem_out_dec = 6'b111111; 12'd849 : mem_out_dec = 6'b111111; 12'd850 : mem_out_dec = 6'b111111; 12'd851 : mem_out_dec = 6'b000100; 12'd852 : mem_out_dec = 6'b000100; 12'd853 : mem_out_dec = 6'b000101; 12'd854 : mem_out_dec = 6'b000101; 12'd855 : mem_out_dec = 6'b000110; 12'd856 : mem_out_dec = 6'b000110; 12'd857 : mem_out_dec = 6'b000111; 12'd858 : mem_out_dec = 6'b001000; 12'd859 : mem_out_dec = 6'b001001; 12'd860 : mem_out_dec = 6'b001001; 12'd861 : mem_out_dec = 6'b001010; 12'd862 : mem_out_dec = 6'b001011; 12'd863 : mem_out_dec = 6'b001100; 12'd864 : mem_out_dec = 6'b001100; 12'd865 : mem_out_dec = 6'b001100; 12'd866 : mem_out_dec = 6'b001100; 12'd867 : mem_out_dec = 6'b001101; 12'd868 : mem_out_dec = 6'b001101; 12'd869 : mem_out_dec = 6'b001110; 12'd870 : mem_out_dec = 6'b001111; 12'd871 : mem_out_dec = 6'b001111; 12'd872 : mem_out_dec = 6'b001110; 12'd873 : mem_out_dec = 6'b001111; 12'd874 : mem_out_dec = 6'b001111; 12'd875 : mem_out_dec = 6'b010000; 12'd876 : mem_out_dec = 6'b010000; 12'd877 : mem_out_dec = 6'b010001; 12'd878 : mem_out_dec = 6'b010001; 12'd879 : mem_out_dec = 6'b010010; 12'd880 : mem_out_dec = 6'b010010; 12'd881 : mem_out_dec = 6'b010010; 12'd882 : mem_out_dec = 6'b010011; 12'd883 : mem_out_dec = 6'b010100; 12'd884 : mem_out_dec = 6'b010100; 12'd885 : mem_out_dec = 6'b010101; 12'd886 : mem_out_dec = 6'b010101; 12'd887 : mem_out_dec = 6'b010110; 12'd888 : mem_out_dec = 6'b010110; 12'd889 : mem_out_dec = 6'b010111; 12'd890 : mem_out_dec = 6'b011000; 12'd891 : mem_out_dec = 6'b011000; 12'd892 : mem_out_dec = 6'b011001; 12'd893 : mem_out_dec = 6'b011010; 12'd894 : mem_out_dec = 6'b011011; 12'd895 : mem_out_dec = 6'b011011; 12'd896 : mem_out_dec = 6'b111111; 12'd897 : mem_out_dec = 6'b111111; 12'd898 : mem_out_dec = 6'b111111; 12'd899 : mem_out_dec = 6'b111111; 12'd900 : mem_out_dec = 6'b111111; 12'd901 : mem_out_dec = 6'b111111; 12'd902 : mem_out_dec = 6'b111111; 12'd903 : mem_out_dec = 6'b111111; 12'd904 : mem_out_dec = 6'b111111; 12'd905 : mem_out_dec = 6'b111111; 12'd906 : mem_out_dec = 6'b111111; 12'd907 : mem_out_dec = 6'b111111; 12'd908 : mem_out_dec = 6'b111111; 12'd909 : mem_out_dec = 6'b111111; 12'd910 : mem_out_dec = 6'b111111; 12'd911 : mem_out_dec = 6'b111111; 12'd912 : mem_out_dec = 6'b111111; 12'd913 : mem_out_dec = 6'b111111; 12'd914 : mem_out_dec = 6'b111111; 12'd915 : mem_out_dec = 6'b111111; 12'd916 : mem_out_dec = 6'b000100; 12'd917 : mem_out_dec = 6'b000101; 12'd918 : mem_out_dec = 6'b000101; 12'd919 : mem_out_dec = 6'b000110; 12'd920 : mem_out_dec = 6'b000110; 12'd921 : mem_out_dec = 6'b000111; 12'd922 : mem_out_dec = 6'b001000; 12'd923 : mem_out_dec = 6'b001000; 12'd924 : mem_out_dec = 6'b001001; 12'd925 : mem_out_dec = 6'b001010; 12'd926 : mem_out_dec = 6'b001011; 12'd927 : mem_out_dec = 6'b001011; 12'd928 : mem_out_dec = 6'b001011; 12'd929 : mem_out_dec = 6'b001100; 12'd930 : mem_out_dec = 6'b001100; 12'd931 : mem_out_dec = 6'b001101; 12'd932 : mem_out_dec = 6'b001101; 12'd933 : mem_out_dec = 6'b001110; 12'd934 : mem_out_dec = 6'b001110; 12'd935 : mem_out_dec = 6'b001111; 12'd936 : mem_out_dec = 6'b001110; 12'd937 : mem_out_dec = 6'b001110; 12'd938 : mem_out_dec = 6'b001111; 12'd939 : mem_out_dec = 6'b001111; 12'd940 : mem_out_dec = 6'b010000; 12'd941 : mem_out_dec = 6'b010000; 12'd942 : mem_out_dec = 6'b010001; 12'd943 : mem_out_dec = 6'b010001; 12'd944 : mem_out_dec = 6'b010010; 12'd945 : mem_out_dec = 6'b010010; 12'd946 : mem_out_dec = 6'b010011; 12'd947 : mem_out_dec = 6'b010011; 12'd948 : mem_out_dec = 6'b010100; 12'd949 : mem_out_dec = 6'b010100; 12'd950 : mem_out_dec = 6'b010101; 12'd951 : mem_out_dec = 6'b010110; 12'd952 : mem_out_dec = 6'b010110; 12'd953 : mem_out_dec = 6'b010111; 12'd954 : mem_out_dec = 6'b010111; 12'd955 : mem_out_dec = 6'b011000; 12'd956 : mem_out_dec = 6'b011001; 12'd957 : mem_out_dec = 6'b011010; 12'd958 : mem_out_dec = 6'b011010; 12'd959 : mem_out_dec = 6'b011011; 12'd960 : mem_out_dec = 6'b111111; 12'd961 : mem_out_dec = 6'b111111; 12'd962 : mem_out_dec = 6'b111111; 12'd963 : mem_out_dec = 6'b111111; 12'd964 : mem_out_dec = 6'b111111; 12'd965 : mem_out_dec = 6'b111111; 12'd966 : mem_out_dec = 6'b111111; 12'd967 : mem_out_dec = 6'b111111; 12'd968 : mem_out_dec = 6'b111111; 12'd969 : mem_out_dec = 6'b111111; 12'd970 : mem_out_dec = 6'b111111; 12'd971 : mem_out_dec = 6'b111111; 12'd972 : mem_out_dec = 6'b111111; 12'd973 : mem_out_dec = 6'b111111; 12'd974 : mem_out_dec = 6'b111111; 12'd975 : mem_out_dec = 6'b111111; 12'd976 : mem_out_dec = 6'b111111; 12'd977 : mem_out_dec = 6'b111111; 12'd978 : mem_out_dec = 6'b111111; 12'd979 : mem_out_dec = 6'b111111; 12'd980 : mem_out_dec = 6'b111111; 12'd981 : mem_out_dec = 6'b000100; 12'd982 : mem_out_dec = 6'b000101; 12'd983 : mem_out_dec = 6'b000110; 12'd984 : mem_out_dec = 6'b000110; 12'd985 : mem_out_dec = 6'b000111; 12'd986 : mem_out_dec = 6'b000111; 12'd987 : mem_out_dec = 6'b001000; 12'd988 : mem_out_dec = 6'b001001; 12'd989 : mem_out_dec = 6'b001010; 12'd990 : mem_out_dec = 6'b001010; 12'd991 : mem_out_dec = 6'b001011; 12'd992 : mem_out_dec = 6'b001011; 12'd993 : mem_out_dec = 6'b001011; 12'd994 : mem_out_dec = 6'b001100; 12'd995 : mem_out_dec = 6'b001100; 12'd996 : mem_out_dec = 6'b001101; 12'd997 : mem_out_dec = 6'b001110; 12'd998 : mem_out_dec = 6'b001110; 12'd999 : mem_out_dec = 6'b001110; 12'd1000 : mem_out_dec = 6'b001101; 12'd1001 : mem_out_dec = 6'b001110; 12'd1002 : mem_out_dec = 6'b001110; 12'd1003 : mem_out_dec = 6'b001111; 12'd1004 : mem_out_dec = 6'b001111; 12'd1005 : mem_out_dec = 6'b010000; 12'd1006 : mem_out_dec = 6'b010000; 12'd1007 : mem_out_dec = 6'b010001; 12'd1008 : mem_out_dec = 6'b010001; 12'd1009 : mem_out_dec = 6'b010010; 12'd1010 : mem_out_dec = 6'b010011; 12'd1011 : mem_out_dec = 6'b010011; 12'd1012 : mem_out_dec = 6'b010100; 12'd1013 : mem_out_dec = 6'b010100; 12'd1014 : mem_out_dec = 6'b010101; 12'd1015 : mem_out_dec = 6'b010110; 12'd1016 : mem_out_dec = 6'b010110; 12'd1017 : mem_out_dec = 6'b010110; 12'd1018 : mem_out_dec = 6'b010111; 12'd1019 : mem_out_dec = 6'b011000; 12'd1020 : mem_out_dec = 6'b011001; 12'd1021 : mem_out_dec = 6'b011001; 12'd1022 : mem_out_dec = 6'b011010; 12'd1023 : mem_out_dec = 6'b011011; 12'd1024 : mem_out_dec = 6'b111111; 12'd1025 : mem_out_dec = 6'b111111; 12'd1026 : mem_out_dec = 6'b111111; 12'd1027 : mem_out_dec = 6'b111111; 12'd1028 : mem_out_dec = 6'b111111; 12'd1029 : mem_out_dec = 6'b111111; 12'd1030 : mem_out_dec = 6'b111111; 12'd1031 : mem_out_dec = 6'b111111; 12'd1032 : mem_out_dec = 6'b111111; 12'd1033 : mem_out_dec = 6'b111111; 12'd1034 : mem_out_dec = 6'b111111; 12'd1035 : mem_out_dec = 6'b111111; 12'd1036 : mem_out_dec = 6'b111111; 12'd1037 : mem_out_dec = 6'b111111; 12'd1038 : mem_out_dec = 6'b111111; 12'd1039 : mem_out_dec = 6'b111111; 12'd1040 : mem_out_dec = 6'b111111; 12'd1041 : mem_out_dec = 6'b111111; 12'd1042 : mem_out_dec = 6'b111111; 12'd1043 : mem_out_dec = 6'b111111; 12'd1044 : mem_out_dec = 6'b111111; 12'd1045 : mem_out_dec = 6'b111111; 12'd1046 : mem_out_dec = 6'b000100; 12'd1047 : mem_out_dec = 6'b000101; 12'd1048 : mem_out_dec = 6'b000101; 12'd1049 : mem_out_dec = 6'b000110; 12'd1050 : mem_out_dec = 6'b000110; 12'd1051 : mem_out_dec = 6'b000111; 12'd1052 : mem_out_dec = 6'b001000; 12'd1053 : mem_out_dec = 6'b001001; 12'd1054 : mem_out_dec = 6'b001001; 12'd1055 : mem_out_dec = 6'b001010; 12'd1056 : mem_out_dec = 6'b001010; 12'd1057 : mem_out_dec = 6'b001011; 12'd1058 : mem_out_dec = 6'b001011; 12'd1059 : mem_out_dec = 6'b001100; 12'd1060 : mem_out_dec = 6'b001100; 12'd1061 : mem_out_dec = 6'b001100; 12'd1062 : mem_out_dec = 6'b001100; 12'd1063 : mem_out_dec = 6'b001100; 12'd1064 : mem_out_dec = 6'b001100; 12'd1065 : mem_out_dec = 6'b001100; 12'd1066 : mem_out_dec = 6'b001101; 12'd1067 : mem_out_dec = 6'b001101; 12'd1068 : mem_out_dec = 6'b001110; 12'd1069 : mem_out_dec = 6'b001111; 12'd1070 : mem_out_dec = 6'b010000; 12'd1071 : mem_out_dec = 6'b010000; 12'd1072 : mem_out_dec = 6'b010001; 12'd1073 : mem_out_dec = 6'b010001; 12'd1074 : mem_out_dec = 6'b010010; 12'd1075 : mem_out_dec = 6'b010010; 12'd1076 : mem_out_dec = 6'b010011; 12'd1077 : mem_out_dec = 6'b010011; 12'd1078 : mem_out_dec = 6'b010100; 12'd1079 : mem_out_dec = 6'b010101; 12'd1080 : mem_out_dec = 6'b010101; 12'd1081 : mem_out_dec = 6'b010110; 12'd1082 : mem_out_dec = 6'b010110; 12'd1083 : mem_out_dec = 6'b010111; 12'd1084 : mem_out_dec = 6'b011000; 12'd1085 : mem_out_dec = 6'b011000; 12'd1086 : mem_out_dec = 6'b011001; 12'd1087 : mem_out_dec = 6'b011010; 12'd1088 : mem_out_dec = 6'b111111; 12'd1089 : mem_out_dec = 6'b111111; 12'd1090 : mem_out_dec = 6'b111111; 12'd1091 : mem_out_dec = 6'b111111; 12'd1092 : mem_out_dec = 6'b111111; 12'd1093 : mem_out_dec = 6'b111111; 12'd1094 : mem_out_dec = 6'b111111; 12'd1095 : mem_out_dec = 6'b111111; 12'd1096 : mem_out_dec = 6'b111111; 12'd1097 : mem_out_dec = 6'b111111; 12'd1098 : mem_out_dec = 6'b111111; 12'd1099 : mem_out_dec = 6'b111111; 12'd1100 : mem_out_dec = 6'b111111; 12'd1101 : mem_out_dec = 6'b111111; 12'd1102 : mem_out_dec = 6'b111111; 12'd1103 : mem_out_dec = 6'b111111; 12'd1104 : mem_out_dec = 6'b111111; 12'd1105 : mem_out_dec = 6'b111111; 12'd1106 : mem_out_dec = 6'b111111; 12'd1107 : mem_out_dec = 6'b111111; 12'd1108 : mem_out_dec = 6'b111111; 12'd1109 : mem_out_dec = 6'b111111; 12'd1110 : mem_out_dec = 6'b111111; 12'd1111 : mem_out_dec = 6'b000100; 12'd1112 : mem_out_dec = 6'b000100; 12'd1113 : mem_out_dec = 6'b000101; 12'd1114 : mem_out_dec = 6'b000110; 12'd1115 : mem_out_dec = 6'b000111; 12'd1116 : mem_out_dec = 6'b000111; 12'd1117 : mem_out_dec = 6'b001000; 12'd1118 : mem_out_dec = 6'b001001; 12'd1119 : mem_out_dec = 6'b001001; 12'd1120 : mem_out_dec = 6'b001010; 12'd1121 : mem_out_dec = 6'b001010; 12'd1122 : mem_out_dec = 6'b001011; 12'd1123 : mem_out_dec = 6'b001011; 12'd1124 : mem_out_dec = 6'b001011; 12'd1125 : mem_out_dec = 6'b001011; 12'd1126 : mem_out_dec = 6'b001011; 12'd1127 : mem_out_dec = 6'b001011; 12'd1128 : mem_out_dec = 6'b001011; 12'd1129 : mem_out_dec = 6'b001011; 12'd1130 : mem_out_dec = 6'b001100; 12'd1131 : mem_out_dec = 6'b001101; 12'd1132 : mem_out_dec = 6'b001110; 12'd1133 : mem_out_dec = 6'b001110; 12'd1134 : mem_out_dec = 6'b001111; 12'd1135 : mem_out_dec = 6'b010000; 12'd1136 : mem_out_dec = 6'b010000; 12'd1137 : mem_out_dec = 6'b010001; 12'd1138 : mem_out_dec = 6'b010001; 12'd1139 : mem_out_dec = 6'b010010; 12'd1140 : mem_out_dec = 6'b010010; 12'd1141 : mem_out_dec = 6'b010011; 12'd1142 : mem_out_dec = 6'b010100; 12'd1143 : mem_out_dec = 6'b010100; 12'd1144 : mem_out_dec = 6'b010100; 12'd1145 : mem_out_dec = 6'b010101; 12'd1146 : mem_out_dec = 6'b010110; 12'd1147 : mem_out_dec = 6'b010110; 12'd1148 : mem_out_dec = 6'b010111; 12'd1149 : mem_out_dec = 6'b011000; 12'd1150 : mem_out_dec = 6'b011000; 12'd1151 : mem_out_dec = 6'b011001; 12'd1152 : mem_out_dec = 6'b111111; 12'd1153 : mem_out_dec = 6'b111111; 12'd1154 : mem_out_dec = 6'b111111; 12'd1155 : mem_out_dec = 6'b111111; 12'd1156 : mem_out_dec = 6'b111111; 12'd1157 : mem_out_dec = 6'b111111; 12'd1158 : mem_out_dec = 6'b111111; 12'd1159 : mem_out_dec = 6'b111111; 12'd1160 : mem_out_dec = 6'b111111; 12'd1161 : mem_out_dec = 6'b111111; 12'd1162 : mem_out_dec = 6'b111111; 12'd1163 : mem_out_dec = 6'b111111; 12'd1164 : mem_out_dec = 6'b111111; 12'd1165 : mem_out_dec = 6'b111111; 12'd1166 : mem_out_dec = 6'b111111; 12'd1167 : mem_out_dec = 6'b111111; 12'd1168 : mem_out_dec = 6'b111111; 12'd1169 : mem_out_dec = 6'b111111; 12'd1170 : mem_out_dec = 6'b111111; 12'd1171 : mem_out_dec = 6'b111111; 12'd1172 : mem_out_dec = 6'b111111; 12'd1173 : mem_out_dec = 6'b111111; 12'd1174 : mem_out_dec = 6'b111111; 12'd1175 : mem_out_dec = 6'b111111; 12'd1176 : mem_out_dec = 6'b000100; 12'd1177 : mem_out_dec = 6'b000101; 12'd1178 : mem_out_dec = 6'b000101; 12'd1179 : mem_out_dec = 6'b000110; 12'd1180 : mem_out_dec = 6'b000111; 12'd1181 : mem_out_dec = 6'b000111; 12'd1182 : mem_out_dec = 6'b001000; 12'd1183 : mem_out_dec = 6'b001001; 12'd1184 : mem_out_dec = 6'b001001; 12'd1185 : mem_out_dec = 6'b001010; 12'd1186 : mem_out_dec = 6'b001010; 12'd1187 : mem_out_dec = 6'b001010; 12'd1188 : mem_out_dec = 6'b001010; 12'd1189 : mem_out_dec = 6'b001010; 12'd1190 : mem_out_dec = 6'b001010; 12'd1191 : mem_out_dec = 6'b001010; 12'd1192 : mem_out_dec = 6'b001010; 12'd1193 : mem_out_dec = 6'b001011; 12'd1194 : mem_out_dec = 6'b001100; 12'd1195 : mem_out_dec = 6'b001100; 12'd1196 : mem_out_dec = 6'b001101; 12'd1197 : mem_out_dec = 6'b001110; 12'd1198 : mem_out_dec = 6'b001111; 12'd1199 : mem_out_dec = 6'b010000; 12'd1200 : mem_out_dec = 6'b010000; 12'd1201 : mem_out_dec = 6'b010000; 12'd1202 : mem_out_dec = 6'b010001; 12'd1203 : mem_out_dec = 6'b010001; 12'd1204 : mem_out_dec = 6'b010010; 12'd1205 : mem_out_dec = 6'b010011; 12'd1206 : mem_out_dec = 6'b010011; 12'd1207 : mem_out_dec = 6'b010100; 12'd1208 : mem_out_dec = 6'b010100; 12'd1209 : mem_out_dec = 6'b010100; 12'd1210 : mem_out_dec = 6'b010101; 12'd1211 : mem_out_dec = 6'b010110; 12'd1212 : mem_out_dec = 6'b010110; 12'd1213 : mem_out_dec = 6'b010111; 12'd1214 : mem_out_dec = 6'b011000; 12'd1215 : mem_out_dec = 6'b011001; 12'd1216 : mem_out_dec = 6'b111111; 12'd1217 : mem_out_dec = 6'b111111; 12'd1218 : mem_out_dec = 6'b111111; 12'd1219 : mem_out_dec = 6'b111111; 12'd1220 : mem_out_dec = 6'b111111; 12'd1221 : mem_out_dec = 6'b111111; 12'd1222 : mem_out_dec = 6'b111111; 12'd1223 : mem_out_dec = 6'b111111; 12'd1224 : mem_out_dec = 6'b111111; 12'd1225 : mem_out_dec = 6'b111111; 12'd1226 : mem_out_dec = 6'b111111; 12'd1227 : mem_out_dec = 6'b111111; 12'd1228 : mem_out_dec = 6'b111111; 12'd1229 : mem_out_dec = 6'b111111; 12'd1230 : mem_out_dec = 6'b111111; 12'd1231 : mem_out_dec = 6'b111111; 12'd1232 : mem_out_dec = 6'b111111; 12'd1233 : mem_out_dec = 6'b111111; 12'd1234 : mem_out_dec = 6'b111111; 12'd1235 : mem_out_dec = 6'b111111; 12'd1236 : mem_out_dec = 6'b111111; 12'd1237 : mem_out_dec = 6'b111111; 12'd1238 : mem_out_dec = 6'b111111; 12'd1239 : mem_out_dec = 6'b111111; 12'd1240 : mem_out_dec = 6'b111111; 12'd1241 : mem_out_dec = 6'b000100; 12'd1242 : mem_out_dec = 6'b000100; 12'd1243 : mem_out_dec = 6'b000101; 12'd1244 : mem_out_dec = 6'b000110; 12'd1245 : mem_out_dec = 6'b000111; 12'd1246 : mem_out_dec = 6'b001000; 12'd1247 : mem_out_dec = 6'b001000; 12'd1248 : mem_out_dec = 6'b001001; 12'd1249 : mem_out_dec = 6'b001001; 12'd1250 : mem_out_dec = 6'b001001; 12'd1251 : mem_out_dec = 6'b001001; 12'd1252 : mem_out_dec = 6'b001001; 12'd1253 : mem_out_dec = 6'b001001; 12'd1254 : mem_out_dec = 6'b001001; 12'd1255 : mem_out_dec = 6'b001001; 12'd1256 : mem_out_dec = 6'b001010; 12'd1257 : mem_out_dec = 6'b001010; 12'd1258 : mem_out_dec = 6'b001011; 12'd1259 : mem_out_dec = 6'b001100; 12'd1260 : mem_out_dec = 6'b001101; 12'd1261 : mem_out_dec = 6'b001110; 12'd1262 : mem_out_dec = 6'b001110; 12'd1263 : mem_out_dec = 6'b001111; 12'd1264 : mem_out_dec = 6'b001111; 12'd1265 : mem_out_dec = 6'b010000; 12'd1266 : mem_out_dec = 6'b010000; 12'd1267 : mem_out_dec = 6'b010001; 12'd1268 : mem_out_dec = 6'b010001; 12'd1269 : mem_out_dec = 6'b010010; 12'd1270 : mem_out_dec = 6'b010011; 12'd1271 : mem_out_dec = 6'b010011; 12'd1272 : mem_out_dec = 6'b010011; 12'd1273 : mem_out_dec = 6'b010100; 12'd1274 : mem_out_dec = 6'b010100; 12'd1275 : mem_out_dec = 6'b010101; 12'd1276 : mem_out_dec = 6'b010110; 12'd1277 : mem_out_dec = 6'b010111; 12'd1278 : mem_out_dec = 6'b011000; 12'd1279 : mem_out_dec = 6'b011000; 12'd1280 : mem_out_dec = 6'b111111; 12'd1281 : mem_out_dec = 6'b111111; 12'd1282 : mem_out_dec = 6'b111111; 12'd1283 : mem_out_dec = 6'b111111; 12'd1284 : mem_out_dec = 6'b111111; 12'd1285 : mem_out_dec = 6'b111111; 12'd1286 : mem_out_dec = 6'b111111; 12'd1287 : mem_out_dec = 6'b111111; 12'd1288 : mem_out_dec = 6'b111111; 12'd1289 : mem_out_dec = 6'b111111; 12'd1290 : mem_out_dec = 6'b111111; 12'd1291 : mem_out_dec = 6'b111111; 12'd1292 : mem_out_dec = 6'b111111; 12'd1293 : mem_out_dec = 6'b111111; 12'd1294 : mem_out_dec = 6'b111111; 12'd1295 : mem_out_dec = 6'b111111; 12'd1296 : mem_out_dec = 6'b111111; 12'd1297 : mem_out_dec = 6'b111111; 12'd1298 : mem_out_dec = 6'b111111; 12'd1299 : mem_out_dec = 6'b111111; 12'd1300 : mem_out_dec = 6'b111111; 12'd1301 : mem_out_dec = 6'b111111; 12'd1302 : mem_out_dec = 6'b111111; 12'd1303 : mem_out_dec = 6'b111111; 12'd1304 : mem_out_dec = 6'b111111; 12'd1305 : mem_out_dec = 6'b111111; 12'd1306 : mem_out_dec = 6'b000100; 12'd1307 : mem_out_dec = 6'b000101; 12'd1308 : mem_out_dec = 6'b000110; 12'd1309 : mem_out_dec = 6'b000110; 12'd1310 : mem_out_dec = 6'b000111; 12'd1311 : mem_out_dec = 6'b001000; 12'd1312 : mem_out_dec = 6'b001000; 12'd1313 : mem_out_dec = 6'b001000; 12'd1314 : mem_out_dec = 6'b001000; 12'd1315 : mem_out_dec = 6'b001000; 12'd1316 : mem_out_dec = 6'b001000; 12'd1317 : mem_out_dec = 6'b001000; 12'd1318 : mem_out_dec = 6'b001000; 12'd1319 : mem_out_dec = 6'b001001; 12'd1320 : mem_out_dec = 6'b001001; 12'd1321 : mem_out_dec = 6'b001010; 12'd1322 : mem_out_dec = 6'b001011; 12'd1323 : mem_out_dec = 6'b001100; 12'd1324 : mem_out_dec = 6'b001100; 12'd1325 : mem_out_dec = 6'b001101; 12'd1326 : mem_out_dec = 6'b001110; 12'd1327 : mem_out_dec = 6'b001111; 12'd1328 : mem_out_dec = 6'b001111; 12'd1329 : mem_out_dec = 6'b001111; 12'd1330 : mem_out_dec = 6'b010000; 12'd1331 : mem_out_dec = 6'b010000; 12'd1332 : mem_out_dec = 6'b010001; 12'd1333 : mem_out_dec = 6'b010001; 12'd1334 : mem_out_dec = 6'b010010; 12'd1335 : mem_out_dec = 6'b010011; 12'd1336 : mem_out_dec = 6'b010010; 12'd1337 : mem_out_dec = 6'b010011; 12'd1338 : mem_out_dec = 6'b010100; 12'd1339 : mem_out_dec = 6'b010101; 12'd1340 : mem_out_dec = 6'b010110; 12'd1341 : mem_out_dec = 6'b010110; 12'd1342 : mem_out_dec = 6'b010111; 12'd1343 : mem_out_dec = 6'b011000; 12'd1344 : mem_out_dec = 6'b111111; 12'd1345 : mem_out_dec = 6'b111111; 12'd1346 : mem_out_dec = 6'b111111; 12'd1347 : mem_out_dec = 6'b111111; 12'd1348 : mem_out_dec = 6'b111111; 12'd1349 : mem_out_dec = 6'b111111; 12'd1350 : mem_out_dec = 6'b111111; 12'd1351 : mem_out_dec = 6'b111111; 12'd1352 : mem_out_dec = 6'b111111; 12'd1353 : mem_out_dec = 6'b111111; 12'd1354 : mem_out_dec = 6'b111111; 12'd1355 : mem_out_dec = 6'b111111; 12'd1356 : mem_out_dec = 6'b111111; 12'd1357 : mem_out_dec = 6'b111111; 12'd1358 : mem_out_dec = 6'b111111; 12'd1359 : mem_out_dec = 6'b111111; 12'd1360 : mem_out_dec = 6'b111111; 12'd1361 : mem_out_dec = 6'b111111; 12'd1362 : mem_out_dec = 6'b111111; 12'd1363 : mem_out_dec = 6'b111111; 12'd1364 : mem_out_dec = 6'b111111; 12'd1365 : mem_out_dec = 6'b111111; 12'd1366 : mem_out_dec = 6'b111111; 12'd1367 : mem_out_dec = 6'b111111; 12'd1368 : mem_out_dec = 6'b111111; 12'd1369 : mem_out_dec = 6'b111111; 12'd1370 : mem_out_dec = 6'b111111; 12'd1371 : mem_out_dec = 6'b000101; 12'd1372 : mem_out_dec = 6'b000101; 12'd1373 : mem_out_dec = 6'b000110; 12'd1374 : mem_out_dec = 6'b000111; 12'd1375 : mem_out_dec = 6'b001000; 12'd1376 : mem_out_dec = 6'b000111; 12'd1377 : mem_out_dec = 6'b000111; 12'd1378 : mem_out_dec = 6'b000111; 12'd1379 : mem_out_dec = 6'b000111; 12'd1380 : mem_out_dec = 6'b000111; 12'd1381 : mem_out_dec = 6'b000111; 12'd1382 : mem_out_dec = 6'b001000; 12'd1383 : mem_out_dec = 6'b001001; 12'd1384 : mem_out_dec = 6'b001001; 12'd1385 : mem_out_dec = 6'b001010; 12'd1386 : mem_out_dec = 6'b001010; 12'd1387 : mem_out_dec = 6'b001011; 12'd1388 : mem_out_dec = 6'b001100; 12'd1389 : mem_out_dec = 6'b001101; 12'd1390 : mem_out_dec = 6'b001110; 12'd1391 : mem_out_dec = 6'b001110; 12'd1392 : mem_out_dec = 6'b001111; 12'd1393 : mem_out_dec = 6'b001111; 12'd1394 : mem_out_dec = 6'b010000; 12'd1395 : mem_out_dec = 6'b010000; 12'd1396 : mem_out_dec = 6'b010001; 12'd1397 : mem_out_dec = 6'b010001; 12'd1398 : mem_out_dec = 6'b010010; 12'd1399 : mem_out_dec = 6'b010010; 12'd1400 : mem_out_dec = 6'b010010; 12'd1401 : mem_out_dec = 6'b010011; 12'd1402 : mem_out_dec = 6'b010100; 12'd1403 : mem_out_dec = 6'b010100; 12'd1404 : mem_out_dec = 6'b010101; 12'd1405 : mem_out_dec = 6'b010110; 12'd1406 : mem_out_dec = 6'b010111; 12'd1407 : mem_out_dec = 6'b010111; 12'd1408 : mem_out_dec = 6'b111111; 12'd1409 : mem_out_dec = 6'b111111; 12'd1410 : mem_out_dec = 6'b111111; 12'd1411 : mem_out_dec = 6'b111111; 12'd1412 : mem_out_dec = 6'b111111; 12'd1413 : mem_out_dec = 6'b111111; 12'd1414 : mem_out_dec = 6'b111111; 12'd1415 : mem_out_dec = 6'b111111; 12'd1416 : mem_out_dec = 6'b111111; 12'd1417 : mem_out_dec = 6'b111111; 12'd1418 : mem_out_dec = 6'b111111; 12'd1419 : mem_out_dec = 6'b111111; 12'd1420 : mem_out_dec = 6'b111111; 12'd1421 : mem_out_dec = 6'b111111; 12'd1422 : mem_out_dec = 6'b111111; 12'd1423 : mem_out_dec = 6'b111111; 12'd1424 : mem_out_dec = 6'b111111; 12'd1425 : mem_out_dec = 6'b111111; 12'd1426 : mem_out_dec = 6'b111111; 12'd1427 : mem_out_dec = 6'b111111; 12'd1428 : mem_out_dec = 6'b111111; 12'd1429 : mem_out_dec = 6'b111111; 12'd1430 : mem_out_dec = 6'b111111; 12'd1431 : mem_out_dec = 6'b111111; 12'd1432 : mem_out_dec = 6'b111111; 12'd1433 : mem_out_dec = 6'b111111; 12'd1434 : mem_out_dec = 6'b111111; 12'd1435 : mem_out_dec = 6'b111111; 12'd1436 : mem_out_dec = 6'b000101; 12'd1437 : mem_out_dec = 6'b000110; 12'd1438 : mem_out_dec = 6'b000111; 12'd1439 : mem_out_dec = 6'b000111; 12'd1440 : mem_out_dec = 6'b000110; 12'd1441 : mem_out_dec = 6'b000110; 12'd1442 : mem_out_dec = 6'b000110; 12'd1443 : mem_out_dec = 6'b000110; 12'd1444 : mem_out_dec = 6'b000110; 12'd1445 : mem_out_dec = 6'b000111; 12'd1446 : mem_out_dec = 6'b000111; 12'd1447 : mem_out_dec = 6'b001000; 12'd1448 : mem_out_dec = 6'b001001; 12'd1449 : mem_out_dec = 6'b001001; 12'd1450 : mem_out_dec = 6'b001010; 12'd1451 : mem_out_dec = 6'b001011; 12'd1452 : mem_out_dec = 6'b001100; 12'd1453 : mem_out_dec = 6'b001100; 12'd1454 : mem_out_dec = 6'b001101; 12'd1455 : mem_out_dec = 6'b001110; 12'd1456 : mem_out_dec = 6'b001110; 12'd1457 : mem_out_dec = 6'b001111; 12'd1458 : mem_out_dec = 6'b001111; 12'd1459 : mem_out_dec = 6'b010000; 12'd1460 : mem_out_dec = 6'b010000; 12'd1461 : mem_out_dec = 6'b010001; 12'd1462 : mem_out_dec = 6'b010001; 12'd1463 : mem_out_dec = 6'b010010; 12'd1464 : mem_out_dec = 6'b010010; 12'd1465 : mem_out_dec = 6'b010011; 12'd1466 : mem_out_dec = 6'b010011; 12'd1467 : mem_out_dec = 6'b010100; 12'd1468 : mem_out_dec = 6'b010101; 12'd1469 : mem_out_dec = 6'b010110; 12'd1470 : mem_out_dec = 6'b010110; 12'd1471 : mem_out_dec = 6'b010111; 12'd1472 : mem_out_dec = 6'b111111; 12'd1473 : mem_out_dec = 6'b111111; 12'd1474 : mem_out_dec = 6'b111111; 12'd1475 : mem_out_dec = 6'b111111; 12'd1476 : mem_out_dec = 6'b111111; 12'd1477 : mem_out_dec = 6'b111111; 12'd1478 : mem_out_dec = 6'b111111; 12'd1479 : mem_out_dec = 6'b111111; 12'd1480 : mem_out_dec = 6'b111111; 12'd1481 : mem_out_dec = 6'b111111; 12'd1482 : mem_out_dec = 6'b111111; 12'd1483 : mem_out_dec = 6'b111111; 12'd1484 : mem_out_dec = 6'b111111; 12'd1485 : mem_out_dec = 6'b111111; 12'd1486 : mem_out_dec = 6'b111111; 12'd1487 : mem_out_dec = 6'b111111; 12'd1488 : mem_out_dec = 6'b111111; 12'd1489 : mem_out_dec = 6'b111111; 12'd1490 : mem_out_dec = 6'b111111; 12'd1491 : mem_out_dec = 6'b111111; 12'd1492 : mem_out_dec = 6'b111111; 12'd1493 : mem_out_dec = 6'b111111; 12'd1494 : mem_out_dec = 6'b111111; 12'd1495 : mem_out_dec = 6'b111111; 12'd1496 : mem_out_dec = 6'b111111; 12'd1497 : mem_out_dec = 6'b111111; 12'd1498 : mem_out_dec = 6'b111111; 12'd1499 : mem_out_dec = 6'b111111; 12'd1500 : mem_out_dec = 6'b111111; 12'd1501 : mem_out_dec = 6'b000101; 12'd1502 : mem_out_dec = 6'b000110; 12'd1503 : mem_out_dec = 6'b000110; 12'd1504 : mem_out_dec = 6'b000110; 12'd1505 : mem_out_dec = 6'b000110; 12'd1506 : mem_out_dec = 6'b000101; 12'd1507 : mem_out_dec = 6'b000101; 12'd1508 : mem_out_dec = 6'b000110; 12'd1509 : mem_out_dec = 6'b000111; 12'd1510 : mem_out_dec = 6'b000111; 12'd1511 : mem_out_dec = 6'b001000; 12'd1512 : mem_out_dec = 6'b001000; 12'd1513 : mem_out_dec = 6'b001001; 12'd1514 : mem_out_dec = 6'b001010; 12'd1515 : mem_out_dec = 6'b001011; 12'd1516 : mem_out_dec = 6'b001011; 12'd1517 : mem_out_dec = 6'b001100; 12'd1518 : mem_out_dec = 6'b001101; 12'd1519 : mem_out_dec = 6'b001110; 12'd1520 : mem_out_dec = 6'b001110; 12'd1521 : mem_out_dec = 6'b001110; 12'd1522 : mem_out_dec = 6'b001111; 12'd1523 : mem_out_dec = 6'b001111; 12'd1524 : mem_out_dec = 6'b010000; 12'd1525 : mem_out_dec = 6'b010000; 12'd1526 : mem_out_dec = 6'b010001; 12'd1527 : mem_out_dec = 6'b010001; 12'd1528 : mem_out_dec = 6'b010001; 12'd1529 : mem_out_dec = 6'b010010; 12'd1530 : mem_out_dec = 6'b010011; 12'd1531 : mem_out_dec = 6'b010100; 12'd1532 : mem_out_dec = 6'b010101; 12'd1533 : mem_out_dec = 6'b010101; 12'd1534 : mem_out_dec = 6'b010110; 12'd1535 : mem_out_dec = 6'b010110; 12'd1536 : mem_out_dec = 6'b111111; 12'd1537 : mem_out_dec = 6'b111111; 12'd1538 : mem_out_dec = 6'b111111; 12'd1539 : mem_out_dec = 6'b111111; 12'd1540 : mem_out_dec = 6'b111111; 12'd1541 : mem_out_dec = 6'b111111; 12'd1542 : mem_out_dec = 6'b111111; 12'd1543 : mem_out_dec = 6'b111111; 12'd1544 : mem_out_dec = 6'b111111; 12'd1545 : mem_out_dec = 6'b111111; 12'd1546 : mem_out_dec = 6'b111111; 12'd1547 : mem_out_dec = 6'b111111; 12'd1548 : mem_out_dec = 6'b111111; 12'd1549 : mem_out_dec = 6'b111111; 12'd1550 : mem_out_dec = 6'b111111; 12'd1551 : mem_out_dec = 6'b111111; 12'd1552 : mem_out_dec = 6'b111111; 12'd1553 : mem_out_dec = 6'b111111; 12'd1554 : mem_out_dec = 6'b111111; 12'd1555 : mem_out_dec = 6'b111111; 12'd1556 : mem_out_dec = 6'b111111; 12'd1557 : mem_out_dec = 6'b111111; 12'd1558 : mem_out_dec = 6'b111111; 12'd1559 : mem_out_dec = 6'b111111; 12'd1560 : mem_out_dec = 6'b111111; 12'd1561 : mem_out_dec = 6'b111111; 12'd1562 : mem_out_dec = 6'b111111; 12'd1563 : mem_out_dec = 6'b111111; 12'd1564 : mem_out_dec = 6'b111111; 12'd1565 : mem_out_dec = 6'b111111; 12'd1566 : mem_out_dec = 6'b000100; 12'd1567 : mem_out_dec = 6'b000100; 12'd1568 : mem_out_dec = 6'b000100; 12'd1569 : mem_out_dec = 6'b000100; 12'd1570 : mem_out_dec = 6'b000100; 12'd1571 : mem_out_dec = 6'b000101; 12'd1572 : mem_out_dec = 6'b000101; 12'd1573 : mem_out_dec = 6'b000110; 12'd1574 : mem_out_dec = 6'b000111; 12'd1575 : mem_out_dec = 6'b000111; 12'd1576 : mem_out_dec = 6'b000111; 12'd1577 : mem_out_dec = 6'b001000; 12'd1578 : mem_out_dec = 6'b001001; 12'd1579 : mem_out_dec = 6'b001010; 12'd1580 : mem_out_dec = 6'b001010; 12'd1581 : mem_out_dec = 6'b001011; 12'd1582 : mem_out_dec = 6'b001100; 12'd1583 : mem_out_dec = 6'b001101; 12'd1584 : mem_out_dec = 6'b001101; 12'd1585 : mem_out_dec = 6'b001101; 12'd1586 : mem_out_dec = 6'b001110; 12'd1587 : mem_out_dec = 6'b001110; 12'd1588 : mem_out_dec = 6'b001111; 12'd1589 : mem_out_dec = 6'b001111; 12'd1590 : mem_out_dec = 6'b010000; 12'd1591 : mem_out_dec = 6'b010001; 12'd1592 : mem_out_dec = 6'b010001; 12'd1593 : mem_out_dec = 6'b010001; 12'd1594 : mem_out_dec = 6'b010010; 12'd1595 : mem_out_dec = 6'b010010; 12'd1596 : mem_out_dec = 6'b010011; 12'd1597 : mem_out_dec = 6'b010011; 12'd1598 : mem_out_dec = 6'b010100; 12'd1599 : mem_out_dec = 6'b010100; 12'd1600 : mem_out_dec = 6'b111111; 12'd1601 : mem_out_dec = 6'b111111; 12'd1602 : mem_out_dec = 6'b111111; 12'd1603 : mem_out_dec = 6'b111111; 12'd1604 : mem_out_dec = 6'b111111; 12'd1605 : mem_out_dec = 6'b111111; 12'd1606 : mem_out_dec = 6'b111111; 12'd1607 : mem_out_dec = 6'b111111; 12'd1608 : mem_out_dec = 6'b111111; 12'd1609 : mem_out_dec = 6'b111111; 12'd1610 : mem_out_dec = 6'b111111; 12'd1611 : mem_out_dec = 6'b111111; 12'd1612 : mem_out_dec = 6'b111111; 12'd1613 : mem_out_dec = 6'b111111; 12'd1614 : mem_out_dec = 6'b111111; 12'd1615 : mem_out_dec = 6'b111111; 12'd1616 : mem_out_dec = 6'b111111; 12'd1617 : mem_out_dec = 6'b111111; 12'd1618 : mem_out_dec = 6'b111111; 12'd1619 : mem_out_dec = 6'b111111; 12'd1620 : mem_out_dec = 6'b111111; 12'd1621 : mem_out_dec = 6'b111111; 12'd1622 : mem_out_dec = 6'b111111; 12'd1623 : mem_out_dec = 6'b111111; 12'd1624 : mem_out_dec = 6'b111111; 12'd1625 : mem_out_dec = 6'b111111; 12'd1626 : mem_out_dec = 6'b111111; 12'd1627 : mem_out_dec = 6'b111111; 12'd1628 : mem_out_dec = 6'b111111; 12'd1629 : mem_out_dec = 6'b111111; 12'd1630 : mem_out_dec = 6'b111111; 12'd1631 : mem_out_dec = 6'b000100; 12'd1632 : mem_out_dec = 6'b000011; 12'd1633 : mem_out_dec = 6'b000011; 12'd1634 : mem_out_dec = 6'b000100; 12'd1635 : mem_out_dec = 6'b000100; 12'd1636 : mem_out_dec = 6'b000101; 12'd1637 : mem_out_dec = 6'b000110; 12'd1638 : mem_out_dec = 6'b000110; 12'd1639 : mem_out_dec = 6'b000111; 12'd1640 : mem_out_dec = 6'b000111; 12'd1641 : mem_out_dec = 6'b001000; 12'd1642 : mem_out_dec = 6'b001001; 12'd1643 : mem_out_dec = 6'b001001; 12'd1644 : mem_out_dec = 6'b001010; 12'd1645 : mem_out_dec = 6'b001011; 12'd1646 : mem_out_dec = 6'b001100; 12'd1647 : mem_out_dec = 6'b001101; 12'd1648 : mem_out_dec = 6'b001101; 12'd1649 : mem_out_dec = 6'b001101; 12'd1650 : mem_out_dec = 6'b001110; 12'd1651 : mem_out_dec = 6'b001110; 12'd1652 : mem_out_dec = 6'b001110; 12'd1653 : mem_out_dec = 6'b001111; 12'd1654 : mem_out_dec = 6'b010000; 12'd1655 : mem_out_dec = 6'b010000; 12'd1656 : mem_out_dec = 6'b010001; 12'd1657 : mem_out_dec = 6'b010001; 12'd1658 : mem_out_dec = 6'b010001; 12'd1659 : mem_out_dec = 6'b010010; 12'd1660 : mem_out_dec = 6'b010010; 12'd1661 : mem_out_dec = 6'b010011; 12'd1662 : mem_out_dec = 6'b010011; 12'd1663 : mem_out_dec = 6'b010100; 12'd1664 : mem_out_dec = 6'b111111; 12'd1665 : mem_out_dec = 6'b111111; 12'd1666 : mem_out_dec = 6'b111111; 12'd1667 : mem_out_dec = 6'b111111; 12'd1668 : mem_out_dec = 6'b111111; 12'd1669 : mem_out_dec = 6'b111111; 12'd1670 : mem_out_dec = 6'b111111; 12'd1671 : mem_out_dec = 6'b111111; 12'd1672 : mem_out_dec = 6'b111111; 12'd1673 : mem_out_dec = 6'b111111; 12'd1674 : mem_out_dec = 6'b111111; 12'd1675 : mem_out_dec = 6'b111111; 12'd1676 : mem_out_dec = 6'b111111; 12'd1677 : mem_out_dec = 6'b111111; 12'd1678 : mem_out_dec = 6'b111111; 12'd1679 : mem_out_dec = 6'b111111; 12'd1680 : mem_out_dec = 6'b111111; 12'd1681 : mem_out_dec = 6'b111111; 12'd1682 : mem_out_dec = 6'b111111; 12'd1683 : mem_out_dec = 6'b111111; 12'd1684 : mem_out_dec = 6'b111111; 12'd1685 : mem_out_dec = 6'b111111; 12'd1686 : mem_out_dec = 6'b111111; 12'd1687 : mem_out_dec = 6'b111111; 12'd1688 : mem_out_dec = 6'b111111; 12'd1689 : mem_out_dec = 6'b111111; 12'd1690 : mem_out_dec = 6'b111111; 12'd1691 : mem_out_dec = 6'b111111; 12'd1692 : mem_out_dec = 6'b111111; 12'd1693 : mem_out_dec = 6'b111111; 12'd1694 : mem_out_dec = 6'b111111; 12'd1695 : mem_out_dec = 6'b111111; 12'd1696 : mem_out_dec = 6'b000011; 12'd1697 : mem_out_dec = 6'b000011; 12'd1698 : mem_out_dec = 6'b000100; 12'd1699 : mem_out_dec = 6'b000100; 12'd1700 : mem_out_dec = 6'b000101; 12'd1701 : mem_out_dec = 6'b000101; 12'd1702 : mem_out_dec = 6'b000110; 12'd1703 : mem_out_dec = 6'b000111; 12'd1704 : mem_out_dec = 6'b000111; 12'd1705 : mem_out_dec = 6'b001000; 12'd1706 : mem_out_dec = 6'b001000; 12'd1707 : mem_out_dec = 6'b001001; 12'd1708 : mem_out_dec = 6'b001010; 12'd1709 : mem_out_dec = 6'b001011; 12'd1710 : mem_out_dec = 6'b001100; 12'd1711 : mem_out_dec = 6'b001100; 12'd1712 : mem_out_dec = 6'b001100; 12'd1713 : mem_out_dec = 6'b001101; 12'd1714 : mem_out_dec = 6'b001101; 12'd1715 : mem_out_dec = 6'b001110; 12'd1716 : mem_out_dec = 6'b001110; 12'd1717 : mem_out_dec = 6'b001111; 12'd1718 : mem_out_dec = 6'b001111; 12'd1719 : mem_out_dec = 6'b010000; 12'd1720 : mem_out_dec = 6'b010000; 12'd1721 : mem_out_dec = 6'b010000; 12'd1722 : mem_out_dec = 6'b010001; 12'd1723 : mem_out_dec = 6'b010001; 12'd1724 : mem_out_dec = 6'b010010; 12'd1725 : mem_out_dec = 6'b010010; 12'd1726 : mem_out_dec = 6'b010011; 12'd1727 : mem_out_dec = 6'b010011; 12'd1728 : mem_out_dec = 6'b111111; 12'd1729 : mem_out_dec = 6'b111111; 12'd1730 : mem_out_dec = 6'b111111; 12'd1731 : mem_out_dec = 6'b111111; 12'd1732 : mem_out_dec = 6'b111111; 12'd1733 : mem_out_dec = 6'b111111; 12'd1734 : mem_out_dec = 6'b111111; 12'd1735 : mem_out_dec = 6'b111111; 12'd1736 : mem_out_dec = 6'b111111; 12'd1737 : mem_out_dec = 6'b111111; 12'd1738 : mem_out_dec = 6'b111111; 12'd1739 : mem_out_dec = 6'b111111; 12'd1740 : mem_out_dec = 6'b111111; 12'd1741 : mem_out_dec = 6'b111111; 12'd1742 : mem_out_dec = 6'b111111; 12'd1743 : mem_out_dec = 6'b111111; 12'd1744 : mem_out_dec = 6'b111111; 12'd1745 : mem_out_dec = 6'b111111; 12'd1746 : mem_out_dec = 6'b111111; 12'd1747 : mem_out_dec = 6'b111111; 12'd1748 : mem_out_dec = 6'b111111; 12'd1749 : mem_out_dec = 6'b111111; 12'd1750 : mem_out_dec = 6'b111111; 12'd1751 : mem_out_dec = 6'b111111; 12'd1752 : mem_out_dec = 6'b111111; 12'd1753 : mem_out_dec = 6'b111111; 12'd1754 : mem_out_dec = 6'b111111; 12'd1755 : mem_out_dec = 6'b111111; 12'd1756 : mem_out_dec = 6'b111111; 12'd1757 : mem_out_dec = 6'b111111; 12'd1758 : mem_out_dec = 6'b111111; 12'd1759 : mem_out_dec = 6'b111111; 12'd1760 : mem_out_dec = 6'b111111; 12'd1761 : mem_out_dec = 6'b000011; 12'd1762 : mem_out_dec = 6'b000011; 12'd1763 : mem_out_dec = 6'b000100; 12'd1764 : mem_out_dec = 6'b000101; 12'd1765 : mem_out_dec = 6'b000101; 12'd1766 : mem_out_dec = 6'b000110; 12'd1767 : mem_out_dec = 6'b000111; 12'd1768 : mem_out_dec = 6'b000111; 12'd1769 : mem_out_dec = 6'b000111; 12'd1770 : mem_out_dec = 6'b001000; 12'd1771 : mem_out_dec = 6'b001001; 12'd1772 : mem_out_dec = 6'b001010; 12'd1773 : mem_out_dec = 6'b001011; 12'd1774 : mem_out_dec = 6'b001011; 12'd1775 : mem_out_dec = 6'b001100; 12'd1776 : mem_out_dec = 6'b001100; 12'd1777 : mem_out_dec = 6'b001101; 12'd1778 : mem_out_dec = 6'b001101; 12'd1779 : mem_out_dec = 6'b001101; 12'd1780 : mem_out_dec = 6'b001110; 12'd1781 : mem_out_dec = 6'b001111; 12'd1782 : mem_out_dec = 6'b001111; 12'd1783 : mem_out_dec = 6'b010000; 12'd1784 : mem_out_dec = 6'b010000; 12'd1785 : mem_out_dec = 6'b010000; 12'd1786 : mem_out_dec = 6'b010000; 12'd1787 : mem_out_dec = 6'b010001; 12'd1788 : mem_out_dec = 6'b010001; 12'd1789 : mem_out_dec = 6'b010010; 12'd1790 : mem_out_dec = 6'b010010; 12'd1791 : mem_out_dec = 6'b010011; 12'd1792 : mem_out_dec = 6'b111111; 12'd1793 : mem_out_dec = 6'b111111; 12'd1794 : mem_out_dec = 6'b111111; 12'd1795 : mem_out_dec = 6'b111111; 12'd1796 : mem_out_dec = 6'b111111; 12'd1797 : mem_out_dec = 6'b111111; 12'd1798 : mem_out_dec = 6'b111111; 12'd1799 : mem_out_dec = 6'b111111; 12'd1800 : mem_out_dec = 6'b111111; 12'd1801 : mem_out_dec = 6'b111111; 12'd1802 : mem_out_dec = 6'b111111; 12'd1803 : mem_out_dec = 6'b111111; 12'd1804 : mem_out_dec = 6'b111111; 12'd1805 : mem_out_dec = 6'b111111; 12'd1806 : mem_out_dec = 6'b111111; 12'd1807 : mem_out_dec = 6'b111111; 12'd1808 : mem_out_dec = 6'b111111; 12'd1809 : mem_out_dec = 6'b111111; 12'd1810 : mem_out_dec = 6'b111111; 12'd1811 : mem_out_dec = 6'b111111; 12'd1812 : mem_out_dec = 6'b111111; 12'd1813 : mem_out_dec = 6'b111111; 12'd1814 : mem_out_dec = 6'b111111; 12'd1815 : mem_out_dec = 6'b111111; 12'd1816 : mem_out_dec = 6'b111111; 12'd1817 : mem_out_dec = 6'b111111; 12'd1818 : mem_out_dec = 6'b111111; 12'd1819 : mem_out_dec = 6'b111111; 12'd1820 : mem_out_dec = 6'b111111; 12'd1821 : mem_out_dec = 6'b111111; 12'd1822 : mem_out_dec = 6'b111111; 12'd1823 : mem_out_dec = 6'b111111; 12'd1824 : mem_out_dec = 6'b111111; 12'd1825 : mem_out_dec = 6'b111111; 12'd1826 : mem_out_dec = 6'b000011; 12'd1827 : mem_out_dec = 6'b000100; 12'd1828 : mem_out_dec = 6'b000100; 12'd1829 : mem_out_dec = 6'b000101; 12'd1830 : mem_out_dec = 6'b000110; 12'd1831 : mem_out_dec = 6'b000110; 12'd1832 : mem_out_dec = 6'b000110; 12'd1833 : mem_out_dec = 6'b000111; 12'd1834 : mem_out_dec = 6'b001000; 12'd1835 : mem_out_dec = 6'b001001; 12'd1836 : mem_out_dec = 6'b001010; 12'd1837 : mem_out_dec = 6'b001010; 12'd1838 : mem_out_dec = 6'b001011; 12'd1839 : mem_out_dec = 6'b001100; 12'd1840 : mem_out_dec = 6'b001100; 12'd1841 : mem_out_dec = 6'b001100; 12'd1842 : mem_out_dec = 6'b001101; 12'd1843 : mem_out_dec = 6'b001101; 12'd1844 : mem_out_dec = 6'b001110; 12'd1845 : mem_out_dec = 6'b001110; 12'd1846 : mem_out_dec = 6'b001111; 12'd1847 : mem_out_dec = 6'b010000; 12'd1848 : mem_out_dec = 6'b001111; 12'd1849 : mem_out_dec = 6'b001111; 12'd1850 : mem_out_dec = 6'b010000; 12'd1851 : mem_out_dec = 6'b010000; 12'd1852 : mem_out_dec = 6'b010001; 12'd1853 : mem_out_dec = 6'b010001; 12'd1854 : mem_out_dec = 6'b010010; 12'd1855 : mem_out_dec = 6'b010010; 12'd1856 : mem_out_dec = 6'b111111; 12'd1857 : mem_out_dec = 6'b111111; 12'd1858 : mem_out_dec = 6'b111111; 12'd1859 : mem_out_dec = 6'b111111; 12'd1860 : mem_out_dec = 6'b111111; 12'd1861 : mem_out_dec = 6'b111111; 12'd1862 : mem_out_dec = 6'b111111; 12'd1863 : mem_out_dec = 6'b111111; 12'd1864 : mem_out_dec = 6'b111111; 12'd1865 : mem_out_dec = 6'b111111; 12'd1866 : mem_out_dec = 6'b111111; 12'd1867 : mem_out_dec = 6'b111111; 12'd1868 : mem_out_dec = 6'b111111; 12'd1869 : mem_out_dec = 6'b111111; 12'd1870 : mem_out_dec = 6'b111111; 12'd1871 : mem_out_dec = 6'b111111; 12'd1872 : mem_out_dec = 6'b111111; 12'd1873 : mem_out_dec = 6'b111111; 12'd1874 : mem_out_dec = 6'b111111; 12'd1875 : mem_out_dec = 6'b111111; 12'd1876 : mem_out_dec = 6'b111111; 12'd1877 : mem_out_dec = 6'b111111; 12'd1878 : mem_out_dec = 6'b111111; 12'd1879 : mem_out_dec = 6'b111111; 12'd1880 : mem_out_dec = 6'b111111; 12'd1881 : mem_out_dec = 6'b111111; 12'd1882 : mem_out_dec = 6'b111111; 12'd1883 : mem_out_dec = 6'b111111; 12'd1884 : mem_out_dec = 6'b111111; 12'd1885 : mem_out_dec = 6'b111111; 12'd1886 : mem_out_dec = 6'b111111; 12'd1887 : mem_out_dec = 6'b111111; 12'd1888 : mem_out_dec = 6'b111111; 12'd1889 : mem_out_dec = 6'b111111; 12'd1890 : mem_out_dec = 6'b111111; 12'd1891 : mem_out_dec = 6'b000100; 12'd1892 : mem_out_dec = 6'b000100; 12'd1893 : mem_out_dec = 6'b000101; 12'd1894 : mem_out_dec = 6'b000101; 12'd1895 : mem_out_dec = 6'b000110; 12'd1896 : mem_out_dec = 6'b000110; 12'd1897 : mem_out_dec = 6'b000111; 12'd1898 : mem_out_dec = 6'b001000; 12'd1899 : mem_out_dec = 6'b001001; 12'd1900 : mem_out_dec = 6'b001001; 12'd1901 : mem_out_dec = 6'b001010; 12'd1902 : mem_out_dec = 6'b001011; 12'd1903 : mem_out_dec = 6'b001100; 12'd1904 : mem_out_dec = 6'b001100; 12'd1905 : mem_out_dec = 6'b001100; 12'd1906 : mem_out_dec = 6'b001100; 12'd1907 : mem_out_dec = 6'b001101; 12'd1908 : mem_out_dec = 6'b001110; 12'd1909 : mem_out_dec = 6'b001110; 12'd1910 : mem_out_dec = 6'b001111; 12'd1911 : mem_out_dec = 6'b001111; 12'd1912 : mem_out_dec = 6'b001111; 12'd1913 : mem_out_dec = 6'b001111; 12'd1914 : mem_out_dec = 6'b001111; 12'd1915 : mem_out_dec = 6'b010000; 12'd1916 : mem_out_dec = 6'b010000; 12'd1917 : mem_out_dec = 6'b010001; 12'd1918 : mem_out_dec = 6'b010001; 12'd1919 : mem_out_dec = 6'b010010; 12'd1920 : mem_out_dec = 6'b111111; 12'd1921 : mem_out_dec = 6'b111111; 12'd1922 : mem_out_dec = 6'b111111; 12'd1923 : mem_out_dec = 6'b111111; 12'd1924 : mem_out_dec = 6'b111111; 12'd1925 : mem_out_dec = 6'b111111; 12'd1926 : mem_out_dec = 6'b111111; 12'd1927 : mem_out_dec = 6'b111111; 12'd1928 : mem_out_dec = 6'b111111; 12'd1929 : mem_out_dec = 6'b111111; 12'd1930 : mem_out_dec = 6'b111111; 12'd1931 : mem_out_dec = 6'b111111; 12'd1932 : mem_out_dec = 6'b111111; 12'd1933 : mem_out_dec = 6'b111111; 12'd1934 : mem_out_dec = 6'b111111; 12'd1935 : mem_out_dec = 6'b111111; 12'd1936 : mem_out_dec = 6'b111111; 12'd1937 : mem_out_dec = 6'b111111; 12'd1938 : mem_out_dec = 6'b111111; 12'd1939 : mem_out_dec = 6'b111111; 12'd1940 : mem_out_dec = 6'b111111; 12'd1941 : mem_out_dec = 6'b111111; 12'd1942 : mem_out_dec = 6'b111111; 12'd1943 : mem_out_dec = 6'b111111; 12'd1944 : mem_out_dec = 6'b111111; 12'd1945 : mem_out_dec = 6'b111111; 12'd1946 : mem_out_dec = 6'b111111; 12'd1947 : mem_out_dec = 6'b111111; 12'd1948 : mem_out_dec = 6'b111111; 12'd1949 : mem_out_dec = 6'b111111; 12'd1950 : mem_out_dec = 6'b111111; 12'd1951 : mem_out_dec = 6'b111111; 12'd1952 : mem_out_dec = 6'b111111; 12'd1953 : mem_out_dec = 6'b111111; 12'd1954 : mem_out_dec = 6'b111111; 12'd1955 : mem_out_dec = 6'b111111; 12'd1956 : mem_out_dec = 6'b000100; 12'd1957 : mem_out_dec = 6'b000101; 12'd1958 : mem_out_dec = 6'b000101; 12'd1959 : mem_out_dec = 6'b000110; 12'd1960 : mem_out_dec = 6'b000110; 12'd1961 : mem_out_dec = 6'b000111; 12'd1962 : mem_out_dec = 6'b001000; 12'd1963 : mem_out_dec = 6'b001000; 12'd1964 : mem_out_dec = 6'b001001; 12'd1965 : mem_out_dec = 6'b001010; 12'd1966 : mem_out_dec = 6'b001011; 12'd1967 : mem_out_dec = 6'b001011; 12'd1968 : mem_out_dec = 6'b001011; 12'd1969 : mem_out_dec = 6'b001100; 12'd1970 : mem_out_dec = 6'b001100; 12'd1971 : mem_out_dec = 6'b001101; 12'd1972 : mem_out_dec = 6'b001101; 12'd1973 : mem_out_dec = 6'b001110; 12'd1974 : mem_out_dec = 6'b001111; 12'd1975 : mem_out_dec = 6'b001111; 12'd1976 : mem_out_dec = 6'b001110; 12'd1977 : mem_out_dec = 6'b001110; 12'd1978 : mem_out_dec = 6'b001111; 12'd1979 : mem_out_dec = 6'b001111; 12'd1980 : mem_out_dec = 6'b010000; 12'd1981 : mem_out_dec = 6'b010000; 12'd1982 : mem_out_dec = 6'b010001; 12'd1983 : mem_out_dec = 6'b010001; 12'd1984 : mem_out_dec = 6'b111111; 12'd1985 : mem_out_dec = 6'b111111; 12'd1986 : mem_out_dec = 6'b111111; 12'd1987 : mem_out_dec = 6'b111111; 12'd1988 : mem_out_dec = 6'b111111; 12'd1989 : mem_out_dec = 6'b111111; 12'd1990 : mem_out_dec = 6'b111111; 12'd1991 : mem_out_dec = 6'b111111; 12'd1992 : mem_out_dec = 6'b111111; 12'd1993 : mem_out_dec = 6'b111111; 12'd1994 : mem_out_dec = 6'b111111; 12'd1995 : mem_out_dec = 6'b111111; 12'd1996 : mem_out_dec = 6'b111111; 12'd1997 : mem_out_dec = 6'b111111; 12'd1998 : mem_out_dec = 6'b111111; 12'd1999 : mem_out_dec = 6'b111111; 12'd2000 : mem_out_dec = 6'b111111; 12'd2001 : mem_out_dec = 6'b111111; 12'd2002 : mem_out_dec = 6'b111111; 12'd2003 : mem_out_dec = 6'b111111; 12'd2004 : mem_out_dec = 6'b111111; 12'd2005 : mem_out_dec = 6'b111111; 12'd2006 : mem_out_dec = 6'b111111; 12'd2007 : mem_out_dec = 6'b111111; 12'd2008 : mem_out_dec = 6'b111111; 12'd2009 : mem_out_dec = 6'b111111; 12'd2010 : mem_out_dec = 6'b111111; 12'd2011 : mem_out_dec = 6'b111111; 12'd2012 : mem_out_dec = 6'b111111; 12'd2013 : mem_out_dec = 6'b111111; 12'd2014 : mem_out_dec = 6'b111111; 12'd2015 : mem_out_dec = 6'b111111; 12'd2016 : mem_out_dec = 6'b111111; 12'd2017 : mem_out_dec = 6'b111111; 12'd2018 : mem_out_dec = 6'b111111; 12'd2019 : mem_out_dec = 6'b111111; 12'd2020 : mem_out_dec = 6'b111111; 12'd2021 : mem_out_dec = 6'b000100; 12'd2022 : mem_out_dec = 6'b000101; 12'd2023 : mem_out_dec = 6'b000110; 12'd2024 : mem_out_dec = 6'b000110; 12'd2025 : mem_out_dec = 6'b000111; 12'd2026 : mem_out_dec = 6'b000111; 12'd2027 : mem_out_dec = 6'b001000; 12'd2028 : mem_out_dec = 6'b001001; 12'd2029 : mem_out_dec = 6'b001010; 12'd2030 : mem_out_dec = 6'b001010; 12'd2031 : mem_out_dec = 6'b001011; 12'd2032 : mem_out_dec = 6'b001011; 12'd2033 : mem_out_dec = 6'b001011; 12'd2034 : mem_out_dec = 6'b001100; 12'd2035 : mem_out_dec = 6'b001101; 12'd2036 : mem_out_dec = 6'b001101; 12'd2037 : mem_out_dec = 6'b001110; 12'd2038 : mem_out_dec = 6'b001110; 12'd2039 : mem_out_dec = 6'b001110; 12'd2040 : mem_out_dec = 6'b001101; 12'd2041 : mem_out_dec = 6'b001110; 12'd2042 : mem_out_dec = 6'b001110; 12'd2043 : mem_out_dec = 6'b001111; 12'd2044 : mem_out_dec = 6'b001111; 12'd2045 : mem_out_dec = 6'b010000; 12'd2046 : mem_out_dec = 6'b010000; 12'd2047 : mem_out_dec = 6'b010001; 12'd2048 : mem_out_dec = 6'b111111; 12'd2049 : mem_out_dec = 6'b111111; 12'd2050 : mem_out_dec = 6'b111111; 12'd2051 : mem_out_dec = 6'b111111; 12'd2052 : mem_out_dec = 6'b111111; 12'd2053 : mem_out_dec = 6'b111111; 12'd2054 : mem_out_dec = 6'b111111; 12'd2055 : mem_out_dec = 6'b111111; 12'd2056 : mem_out_dec = 6'b111111; 12'd2057 : mem_out_dec = 6'b111111; 12'd2058 : mem_out_dec = 6'b111111; 12'd2059 : mem_out_dec = 6'b111111; 12'd2060 : mem_out_dec = 6'b111111; 12'd2061 : mem_out_dec = 6'b111111; 12'd2062 : mem_out_dec = 6'b111111; 12'd2063 : mem_out_dec = 6'b111111; 12'd2064 : mem_out_dec = 6'b111111; 12'd2065 : mem_out_dec = 6'b111111; 12'd2066 : mem_out_dec = 6'b111111; 12'd2067 : mem_out_dec = 6'b111111; 12'd2068 : mem_out_dec = 6'b111111; 12'd2069 : mem_out_dec = 6'b111111; 12'd2070 : mem_out_dec = 6'b111111; 12'd2071 : mem_out_dec = 6'b111111; 12'd2072 : mem_out_dec = 6'b111111; 12'd2073 : mem_out_dec = 6'b111111; 12'd2074 : mem_out_dec = 6'b111111; 12'd2075 : mem_out_dec = 6'b111111; 12'd2076 : mem_out_dec = 6'b111111; 12'd2077 : mem_out_dec = 6'b111111; 12'd2078 : mem_out_dec = 6'b111111; 12'd2079 : mem_out_dec = 6'b111111; 12'd2080 : mem_out_dec = 6'b111111; 12'd2081 : mem_out_dec = 6'b111111; 12'd2082 : mem_out_dec = 6'b111111; 12'd2083 : mem_out_dec = 6'b111111; 12'd2084 : mem_out_dec = 6'b111111; 12'd2085 : mem_out_dec = 6'b111111; 12'd2086 : mem_out_dec = 6'b000100; 12'd2087 : mem_out_dec = 6'b000101; 12'd2088 : mem_out_dec = 6'b000101; 12'd2089 : mem_out_dec = 6'b000110; 12'd2090 : mem_out_dec = 6'b000110; 12'd2091 : mem_out_dec = 6'b000111; 12'd2092 : mem_out_dec = 6'b001000; 12'd2093 : mem_out_dec = 6'b001001; 12'd2094 : mem_out_dec = 6'b001001; 12'd2095 : mem_out_dec = 6'b001010; 12'd2096 : mem_out_dec = 6'b001010; 12'd2097 : mem_out_dec = 6'b001011; 12'd2098 : mem_out_dec = 6'b001011; 12'd2099 : mem_out_dec = 6'b001100; 12'd2100 : mem_out_dec = 6'b001100; 12'd2101 : mem_out_dec = 6'b001100; 12'd2102 : mem_out_dec = 6'b001100; 12'd2103 : mem_out_dec = 6'b001101; 12'd2104 : mem_out_dec = 6'b001100; 12'd2105 : mem_out_dec = 6'b001100; 12'd2106 : mem_out_dec = 6'b001101; 12'd2107 : mem_out_dec = 6'b001101; 12'd2108 : mem_out_dec = 6'b001110; 12'd2109 : mem_out_dec = 6'b001111; 12'd2110 : mem_out_dec = 6'b010000; 12'd2111 : mem_out_dec = 6'b010000; 12'd2112 : mem_out_dec = 6'b111111; 12'd2113 : mem_out_dec = 6'b111111; 12'd2114 : mem_out_dec = 6'b111111; 12'd2115 : mem_out_dec = 6'b111111; 12'd2116 : mem_out_dec = 6'b111111; 12'd2117 : mem_out_dec = 6'b111111; 12'd2118 : mem_out_dec = 6'b111111; 12'd2119 : mem_out_dec = 6'b111111; 12'd2120 : mem_out_dec = 6'b111111; 12'd2121 : mem_out_dec = 6'b111111; 12'd2122 : mem_out_dec = 6'b111111; 12'd2123 : mem_out_dec = 6'b111111; 12'd2124 : mem_out_dec = 6'b111111; 12'd2125 : mem_out_dec = 6'b111111; 12'd2126 : mem_out_dec = 6'b111111; 12'd2127 : mem_out_dec = 6'b111111; 12'd2128 : mem_out_dec = 6'b111111; 12'd2129 : mem_out_dec = 6'b111111; 12'd2130 : mem_out_dec = 6'b111111; 12'd2131 : mem_out_dec = 6'b111111; 12'd2132 : mem_out_dec = 6'b111111; 12'd2133 : mem_out_dec = 6'b111111; 12'd2134 : mem_out_dec = 6'b111111; 12'd2135 : mem_out_dec = 6'b111111; 12'd2136 : mem_out_dec = 6'b111111; 12'd2137 : mem_out_dec = 6'b111111; 12'd2138 : mem_out_dec = 6'b111111; 12'd2139 : mem_out_dec = 6'b111111; 12'd2140 : mem_out_dec = 6'b111111; 12'd2141 : mem_out_dec = 6'b111111; 12'd2142 : mem_out_dec = 6'b111111; 12'd2143 : mem_out_dec = 6'b111111; 12'd2144 : mem_out_dec = 6'b111111; 12'd2145 : mem_out_dec = 6'b111111; 12'd2146 : mem_out_dec = 6'b111111; 12'd2147 : mem_out_dec = 6'b111111; 12'd2148 : mem_out_dec = 6'b111111; 12'd2149 : mem_out_dec = 6'b111111; 12'd2150 : mem_out_dec = 6'b111111; 12'd2151 : mem_out_dec = 6'b000100; 12'd2152 : mem_out_dec = 6'b000100; 12'd2153 : mem_out_dec = 6'b000101; 12'd2154 : mem_out_dec = 6'b000110; 12'd2155 : mem_out_dec = 6'b000111; 12'd2156 : mem_out_dec = 6'b000111; 12'd2157 : mem_out_dec = 6'b001000; 12'd2158 : mem_out_dec = 6'b001001; 12'd2159 : mem_out_dec = 6'b001001; 12'd2160 : mem_out_dec = 6'b001010; 12'd2161 : mem_out_dec = 6'b001010; 12'd2162 : mem_out_dec = 6'b001011; 12'd2163 : mem_out_dec = 6'b001011; 12'd2164 : mem_out_dec = 6'b001011; 12'd2165 : mem_out_dec = 6'b001011; 12'd2166 : mem_out_dec = 6'b001011; 12'd2167 : mem_out_dec = 6'b001100; 12'd2168 : mem_out_dec = 6'b001011; 12'd2169 : mem_out_dec = 6'b001011; 12'd2170 : mem_out_dec = 6'b001100; 12'd2171 : mem_out_dec = 6'b001101; 12'd2172 : mem_out_dec = 6'b001110; 12'd2173 : mem_out_dec = 6'b001110; 12'd2174 : mem_out_dec = 6'b001111; 12'd2175 : mem_out_dec = 6'b010000; 12'd2176 : mem_out_dec = 6'b111111; 12'd2177 : mem_out_dec = 6'b111111; 12'd2178 : mem_out_dec = 6'b111111; 12'd2179 : mem_out_dec = 6'b111111; 12'd2180 : mem_out_dec = 6'b111111; 12'd2181 : mem_out_dec = 6'b111111; 12'd2182 : mem_out_dec = 6'b111111; 12'd2183 : mem_out_dec = 6'b111111; 12'd2184 : mem_out_dec = 6'b111111; 12'd2185 : mem_out_dec = 6'b111111; 12'd2186 : mem_out_dec = 6'b111111; 12'd2187 : mem_out_dec = 6'b111111; 12'd2188 : mem_out_dec = 6'b111111; 12'd2189 : mem_out_dec = 6'b111111; 12'd2190 : mem_out_dec = 6'b111111; 12'd2191 : mem_out_dec = 6'b111111; 12'd2192 : mem_out_dec = 6'b111111; 12'd2193 : mem_out_dec = 6'b111111; 12'd2194 : mem_out_dec = 6'b111111; 12'd2195 : mem_out_dec = 6'b111111; 12'd2196 : mem_out_dec = 6'b111111; 12'd2197 : mem_out_dec = 6'b111111; 12'd2198 : mem_out_dec = 6'b111111; 12'd2199 : mem_out_dec = 6'b111111; 12'd2200 : mem_out_dec = 6'b111111; 12'd2201 : mem_out_dec = 6'b111111; 12'd2202 : mem_out_dec = 6'b111111; 12'd2203 : mem_out_dec = 6'b111111; 12'd2204 : mem_out_dec = 6'b111111; 12'd2205 : mem_out_dec = 6'b111111; 12'd2206 : mem_out_dec = 6'b111111; 12'd2207 : mem_out_dec = 6'b111111; 12'd2208 : mem_out_dec = 6'b111111; 12'd2209 : mem_out_dec = 6'b111111; 12'd2210 : mem_out_dec = 6'b111111; 12'd2211 : mem_out_dec = 6'b111111; 12'd2212 : mem_out_dec = 6'b111111; 12'd2213 : mem_out_dec = 6'b111111; 12'd2214 : mem_out_dec = 6'b111111; 12'd2215 : mem_out_dec = 6'b111111; 12'd2216 : mem_out_dec = 6'b000100; 12'd2217 : mem_out_dec = 6'b000101; 12'd2218 : mem_out_dec = 6'b000101; 12'd2219 : mem_out_dec = 6'b000110; 12'd2220 : mem_out_dec = 6'b000111; 12'd2221 : mem_out_dec = 6'b000111; 12'd2222 : mem_out_dec = 6'b001000; 12'd2223 : mem_out_dec = 6'b001001; 12'd2224 : mem_out_dec = 6'b001001; 12'd2225 : mem_out_dec = 6'b001010; 12'd2226 : mem_out_dec = 6'b001010; 12'd2227 : mem_out_dec = 6'b001010; 12'd2228 : mem_out_dec = 6'b001010; 12'd2229 : mem_out_dec = 6'b001010; 12'd2230 : mem_out_dec = 6'b001010; 12'd2231 : mem_out_dec = 6'b001010; 12'd2232 : mem_out_dec = 6'b001010; 12'd2233 : mem_out_dec = 6'b001011; 12'd2234 : mem_out_dec = 6'b001100; 12'd2235 : mem_out_dec = 6'b001100; 12'd2236 : mem_out_dec = 6'b001101; 12'd2237 : mem_out_dec = 6'b001110; 12'd2238 : mem_out_dec = 6'b001111; 12'd2239 : mem_out_dec = 6'b010000; 12'd2240 : mem_out_dec = 6'b111111; 12'd2241 : mem_out_dec = 6'b111111; 12'd2242 : mem_out_dec = 6'b111111; 12'd2243 : mem_out_dec = 6'b111111; 12'd2244 : mem_out_dec = 6'b111111; 12'd2245 : mem_out_dec = 6'b111111; 12'd2246 : mem_out_dec = 6'b111111; 12'd2247 : mem_out_dec = 6'b111111; 12'd2248 : mem_out_dec = 6'b111111; 12'd2249 : mem_out_dec = 6'b111111; 12'd2250 : mem_out_dec = 6'b111111; 12'd2251 : mem_out_dec = 6'b111111; 12'd2252 : mem_out_dec = 6'b111111; 12'd2253 : mem_out_dec = 6'b111111; 12'd2254 : mem_out_dec = 6'b111111; 12'd2255 : mem_out_dec = 6'b111111; 12'd2256 : mem_out_dec = 6'b111111; 12'd2257 : mem_out_dec = 6'b111111; 12'd2258 : mem_out_dec = 6'b111111; 12'd2259 : mem_out_dec = 6'b111111; 12'd2260 : mem_out_dec = 6'b111111; 12'd2261 : mem_out_dec = 6'b111111; 12'd2262 : mem_out_dec = 6'b111111; 12'd2263 : mem_out_dec = 6'b111111; 12'd2264 : mem_out_dec = 6'b111111; 12'd2265 : mem_out_dec = 6'b111111; 12'd2266 : mem_out_dec = 6'b111111; 12'd2267 : mem_out_dec = 6'b111111; 12'd2268 : mem_out_dec = 6'b111111; 12'd2269 : mem_out_dec = 6'b111111; 12'd2270 : mem_out_dec = 6'b111111; 12'd2271 : mem_out_dec = 6'b111111; 12'd2272 : mem_out_dec = 6'b111111; 12'd2273 : mem_out_dec = 6'b111111; 12'd2274 : mem_out_dec = 6'b111111; 12'd2275 : mem_out_dec = 6'b111111; 12'd2276 : mem_out_dec = 6'b111111; 12'd2277 : mem_out_dec = 6'b111111; 12'd2278 : mem_out_dec = 6'b111111; 12'd2279 : mem_out_dec = 6'b111111; 12'd2280 : mem_out_dec = 6'b111111; 12'd2281 : mem_out_dec = 6'b000100; 12'd2282 : mem_out_dec = 6'b000101; 12'd2283 : mem_out_dec = 6'b000101; 12'd2284 : mem_out_dec = 6'b000110; 12'd2285 : mem_out_dec = 6'b000111; 12'd2286 : mem_out_dec = 6'b001000; 12'd2287 : mem_out_dec = 6'b001001; 12'd2288 : mem_out_dec = 6'b001001; 12'd2289 : mem_out_dec = 6'b001001; 12'd2290 : mem_out_dec = 6'b001001; 12'd2291 : mem_out_dec = 6'b001001; 12'd2292 : mem_out_dec = 6'b001001; 12'd2293 : mem_out_dec = 6'b001001; 12'd2294 : mem_out_dec = 6'b001001; 12'd2295 : mem_out_dec = 6'b001001; 12'd2296 : mem_out_dec = 6'b001010; 12'd2297 : mem_out_dec = 6'b001010; 12'd2298 : mem_out_dec = 6'b001011; 12'd2299 : mem_out_dec = 6'b001100; 12'd2300 : mem_out_dec = 6'b001101; 12'd2301 : mem_out_dec = 6'b001110; 12'd2302 : mem_out_dec = 6'b001110; 12'd2303 : mem_out_dec = 6'b001111; 12'd2304 : mem_out_dec = 6'b111111; 12'd2305 : mem_out_dec = 6'b111111; 12'd2306 : mem_out_dec = 6'b111111; 12'd2307 : mem_out_dec = 6'b111111; 12'd2308 : mem_out_dec = 6'b111111; 12'd2309 : mem_out_dec = 6'b111111; 12'd2310 : mem_out_dec = 6'b111111; 12'd2311 : mem_out_dec = 6'b111111; 12'd2312 : mem_out_dec = 6'b111111; 12'd2313 : mem_out_dec = 6'b111111; 12'd2314 : mem_out_dec = 6'b111111; 12'd2315 : mem_out_dec = 6'b111111; 12'd2316 : mem_out_dec = 6'b111111; 12'd2317 : mem_out_dec = 6'b111111; 12'd2318 : mem_out_dec = 6'b111111; 12'd2319 : mem_out_dec = 6'b111111; 12'd2320 : mem_out_dec = 6'b111111; 12'd2321 : mem_out_dec = 6'b111111; 12'd2322 : mem_out_dec = 6'b111111; 12'd2323 : mem_out_dec = 6'b111111; 12'd2324 : mem_out_dec = 6'b111111; 12'd2325 : mem_out_dec = 6'b111111; 12'd2326 : mem_out_dec = 6'b111111; 12'd2327 : mem_out_dec = 6'b111111; 12'd2328 : mem_out_dec = 6'b111111; 12'd2329 : mem_out_dec = 6'b111111; 12'd2330 : mem_out_dec = 6'b111111; 12'd2331 : mem_out_dec = 6'b111111; 12'd2332 : mem_out_dec = 6'b111111; 12'd2333 : mem_out_dec = 6'b111111; 12'd2334 : mem_out_dec = 6'b111111; 12'd2335 : mem_out_dec = 6'b111111; 12'd2336 : mem_out_dec = 6'b111111; 12'd2337 : mem_out_dec = 6'b111111; 12'd2338 : mem_out_dec = 6'b111111; 12'd2339 : mem_out_dec = 6'b111111; 12'd2340 : mem_out_dec = 6'b111111; 12'd2341 : mem_out_dec = 6'b111111; 12'd2342 : mem_out_dec = 6'b111111; 12'd2343 : mem_out_dec = 6'b111111; 12'd2344 : mem_out_dec = 6'b111111; 12'd2345 : mem_out_dec = 6'b111111; 12'd2346 : mem_out_dec = 6'b000100; 12'd2347 : mem_out_dec = 6'b000101; 12'd2348 : mem_out_dec = 6'b000110; 12'd2349 : mem_out_dec = 6'b000111; 12'd2350 : mem_out_dec = 6'b000111; 12'd2351 : mem_out_dec = 6'b001000; 12'd2352 : mem_out_dec = 6'b001000; 12'd2353 : mem_out_dec = 6'b001000; 12'd2354 : mem_out_dec = 6'b001000; 12'd2355 : mem_out_dec = 6'b001000; 12'd2356 : mem_out_dec = 6'b001000; 12'd2357 : mem_out_dec = 6'b001000; 12'd2358 : mem_out_dec = 6'b001000; 12'd2359 : mem_out_dec = 6'b001001; 12'd2360 : mem_out_dec = 6'b001001; 12'd2361 : mem_out_dec = 6'b001010; 12'd2362 : mem_out_dec = 6'b001011; 12'd2363 : mem_out_dec = 6'b001100; 12'd2364 : mem_out_dec = 6'b001100; 12'd2365 : mem_out_dec = 6'b001101; 12'd2366 : mem_out_dec = 6'b001110; 12'd2367 : mem_out_dec = 6'b001111; 12'd2368 : mem_out_dec = 6'b111111; 12'd2369 : mem_out_dec = 6'b111111; 12'd2370 : mem_out_dec = 6'b111111; 12'd2371 : mem_out_dec = 6'b111111; 12'd2372 : mem_out_dec = 6'b111111; 12'd2373 : mem_out_dec = 6'b111111; 12'd2374 : mem_out_dec = 6'b111111; 12'd2375 : mem_out_dec = 6'b111111; 12'd2376 : mem_out_dec = 6'b111111; 12'd2377 : mem_out_dec = 6'b111111; 12'd2378 : mem_out_dec = 6'b111111; 12'd2379 : mem_out_dec = 6'b111111; 12'd2380 : mem_out_dec = 6'b111111; 12'd2381 : mem_out_dec = 6'b111111; 12'd2382 : mem_out_dec = 6'b111111; 12'd2383 : mem_out_dec = 6'b111111; 12'd2384 : mem_out_dec = 6'b111111; 12'd2385 : mem_out_dec = 6'b111111; 12'd2386 : mem_out_dec = 6'b111111; 12'd2387 : mem_out_dec = 6'b111111; 12'd2388 : mem_out_dec = 6'b111111; 12'd2389 : mem_out_dec = 6'b111111; 12'd2390 : mem_out_dec = 6'b111111; 12'd2391 : mem_out_dec = 6'b111111; 12'd2392 : mem_out_dec = 6'b111111; 12'd2393 : mem_out_dec = 6'b111111; 12'd2394 : mem_out_dec = 6'b111111; 12'd2395 : mem_out_dec = 6'b111111; 12'd2396 : mem_out_dec = 6'b111111; 12'd2397 : mem_out_dec = 6'b111111; 12'd2398 : mem_out_dec = 6'b111111; 12'd2399 : mem_out_dec = 6'b111111; 12'd2400 : mem_out_dec = 6'b111111; 12'd2401 : mem_out_dec = 6'b111111; 12'd2402 : mem_out_dec = 6'b111111; 12'd2403 : mem_out_dec = 6'b111111; 12'd2404 : mem_out_dec = 6'b111111; 12'd2405 : mem_out_dec = 6'b111111; 12'd2406 : mem_out_dec = 6'b111111; 12'd2407 : mem_out_dec = 6'b111111; 12'd2408 : mem_out_dec = 6'b111111; 12'd2409 : mem_out_dec = 6'b111111; 12'd2410 : mem_out_dec = 6'b111111; 12'd2411 : mem_out_dec = 6'b000101; 12'd2412 : mem_out_dec = 6'b000101; 12'd2413 : mem_out_dec = 6'b000110; 12'd2414 : mem_out_dec = 6'b000111; 12'd2415 : mem_out_dec = 6'b001000; 12'd2416 : mem_out_dec = 6'b000111; 12'd2417 : mem_out_dec = 6'b000111; 12'd2418 : mem_out_dec = 6'b000111; 12'd2419 : mem_out_dec = 6'b000111; 12'd2420 : mem_out_dec = 6'b000111; 12'd2421 : mem_out_dec = 6'b000111; 12'd2422 : mem_out_dec = 6'b001000; 12'd2423 : mem_out_dec = 6'b001001; 12'd2424 : mem_out_dec = 6'b001001; 12'd2425 : mem_out_dec = 6'b001010; 12'd2426 : mem_out_dec = 6'b001010; 12'd2427 : mem_out_dec = 6'b001011; 12'd2428 : mem_out_dec = 6'b001100; 12'd2429 : mem_out_dec = 6'b001101; 12'd2430 : mem_out_dec = 6'b001101; 12'd2431 : mem_out_dec = 6'b001110; 12'd2432 : mem_out_dec = 6'b111111; 12'd2433 : mem_out_dec = 6'b111111; 12'd2434 : mem_out_dec = 6'b111111; 12'd2435 : mem_out_dec = 6'b111111; 12'd2436 : mem_out_dec = 6'b111111; 12'd2437 : mem_out_dec = 6'b111111; 12'd2438 : mem_out_dec = 6'b111111; 12'd2439 : mem_out_dec = 6'b111111; 12'd2440 : mem_out_dec = 6'b111111; 12'd2441 : mem_out_dec = 6'b111111; 12'd2442 : mem_out_dec = 6'b111111; 12'd2443 : mem_out_dec = 6'b111111; 12'd2444 : mem_out_dec = 6'b111111; 12'd2445 : mem_out_dec = 6'b111111; 12'd2446 : mem_out_dec = 6'b111111; 12'd2447 : mem_out_dec = 6'b111111; 12'd2448 : mem_out_dec = 6'b111111; 12'd2449 : mem_out_dec = 6'b111111; 12'd2450 : mem_out_dec = 6'b111111; 12'd2451 : mem_out_dec = 6'b111111; 12'd2452 : mem_out_dec = 6'b111111; 12'd2453 : mem_out_dec = 6'b111111; 12'd2454 : mem_out_dec = 6'b111111; 12'd2455 : mem_out_dec = 6'b111111; 12'd2456 : mem_out_dec = 6'b111111; 12'd2457 : mem_out_dec = 6'b111111; 12'd2458 : mem_out_dec = 6'b111111; 12'd2459 : mem_out_dec = 6'b111111; 12'd2460 : mem_out_dec = 6'b111111; 12'd2461 : mem_out_dec = 6'b111111; 12'd2462 : mem_out_dec = 6'b111111; 12'd2463 : mem_out_dec = 6'b111111; 12'd2464 : mem_out_dec = 6'b111111; 12'd2465 : mem_out_dec = 6'b111111; 12'd2466 : mem_out_dec = 6'b111111; 12'd2467 : mem_out_dec = 6'b111111; 12'd2468 : mem_out_dec = 6'b111111; 12'd2469 : mem_out_dec = 6'b111111; 12'd2470 : mem_out_dec = 6'b111111; 12'd2471 : mem_out_dec = 6'b111111; 12'd2472 : mem_out_dec = 6'b111111; 12'd2473 : mem_out_dec = 6'b111111; 12'd2474 : mem_out_dec = 6'b111111; 12'd2475 : mem_out_dec = 6'b111111; 12'd2476 : mem_out_dec = 6'b000101; 12'd2477 : mem_out_dec = 6'b000110; 12'd2478 : mem_out_dec = 6'b000111; 12'd2479 : mem_out_dec = 6'b000111; 12'd2480 : mem_out_dec = 6'b000110; 12'd2481 : mem_out_dec = 6'b000110; 12'd2482 : mem_out_dec = 6'b000110; 12'd2483 : mem_out_dec = 6'b000110; 12'd2484 : mem_out_dec = 6'b000110; 12'd2485 : mem_out_dec = 6'b000111; 12'd2486 : mem_out_dec = 6'b000111; 12'd2487 : mem_out_dec = 6'b001000; 12'd2488 : mem_out_dec = 6'b001001; 12'd2489 : mem_out_dec = 6'b001001; 12'd2490 : mem_out_dec = 6'b001010; 12'd2491 : mem_out_dec = 6'b001011; 12'd2492 : mem_out_dec = 6'b001011; 12'd2493 : mem_out_dec = 6'b001100; 12'd2494 : mem_out_dec = 6'b001101; 12'd2495 : mem_out_dec = 6'b001110; 12'd2496 : mem_out_dec = 6'b111111; 12'd2497 : mem_out_dec = 6'b111111; 12'd2498 : mem_out_dec = 6'b111111; 12'd2499 : mem_out_dec = 6'b111111; 12'd2500 : mem_out_dec = 6'b111111; 12'd2501 : mem_out_dec = 6'b111111; 12'd2502 : mem_out_dec = 6'b111111; 12'd2503 : mem_out_dec = 6'b111111; 12'd2504 : mem_out_dec = 6'b111111; 12'd2505 : mem_out_dec = 6'b111111; 12'd2506 : mem_out_dec = 6'b111111; 12'd2507 : mem_out_dec = 6'b111111; 12'd2508 : mem_out_dec = 6'b111111; 12'd2509 : mem_out_dec = 6'b111111; 12'd2510 : mem_out_dec = 6'b111111; 12'd2511 : mem_out_dec = 6'b111111; 12'd2512 : mem_out_dec = 6'b111111; 12'd2513 : mem_out_dec = 6'b111111; 12'd2514 : mem_out_dec = 6'b111111; 12'd2515 : mem_out_dec = 6'b111111; 12'd2516 : mem_out_dec = 6'b111111; 12'd2517 : mem_out_dec = 6'b111111; 12'd2518 : mem_out_dec = 6'b111111; 12'd2519 : mem_out_dec = 6'b111111; 12'd2520 : mem_out_dec = 6'b111111; 12'd2521 : mem_out_dec = 6'b111111; 12'd2522 : mem_out_dec = 6'b111111; 12'd2523 : mem_out_dec = 6'b111111; 12'd2524 : mem_out_dec = 6'b111111; 12'd2525 : mem_out_dec = 6'b111111; 12'd2526 : mem_out_dec = 6'b111111; 12'd2527 : mem_out_dec = 6'b111111; 12'd2528 : mem_out_dec = 6'b111111; 12'd2529 : mem_out_dec = 6'b111111; 12'd2530 : mem_out_dec = 6'b111111; 12'd2531 : mem_out_dec = 6'b111111; 12'd2532 : mem_out_dec = 6'b111111; 12'd2533 : mem_out_dec = 6'b111111; 12'd2534 : mem_out_dec = 6'b111111; 12'd2535 : mem_out_dec = 6'b111111; 12'd2536 : mem_out_dec = 6'b111111; 12'd2537 : mem_out_dec = 6'b111111; 12'd2538 : mem_out_dec = 6'b111111; 12'd2539 : mem_out_dec = 6'b111111; 12'd2540 : mem_out_dec = 6'b111111; 12'd2541 : mem_out_dec = 6'b000101; 12'd2542 : mem_out_dec = 6'b000110; 12'd2543 : mem_out_dec = 6'b000110; 12'd2544 : mem_out_dec = 6'b000110; 12'd2545 : mem_out_dec = 6'b000110; 12'd2546 : mem_out_dec = 6'b000101; 12'd2547 : mem_out_dec = 6'b000101; 12'd2548 : mem_out_dec = 6'b000110; 12'd2549 : mem_out_dec = 6'b000111; 12'd2550 : mem_out_dec = 6'b000111; 12'd2551 : mem_out_dec = 6'b001000; 12'd2552 : mem_out_dec = 6'b001000; 12'd2553 : mem_out_dec = 6'b001001; 12'd2554 : mem_out_dec = 6'b001010; 12'd2555 : mem_out_dec = 6'b001010; 12'd2556 : mem_out_dec = 6'b001011; 12'd2557 : mem_out_dec = 6'b001100; 12'd2558 : mem_out_dec = 6'b001101; 12'd2559 : mem_out_dec = 6'b001101; 12'd2560 : mem_out_dec = 6'b111111; 12'd2561 : mem_out_dec = 6'b111111; 12'd2562 : mem_out_dec = 6'b111111; 12'd2563 : mem_out_dec = 6'b111111; 12'd2564 : mem_out_dec = 6'b111111; 12'd2565 : mem_out_dec = 6'b111111; 12'd2566 : mem_out_dec = 6'b111111; 12'd2567 : mem_out_dec = 6'b111111; 12'd2568 : mem_out_dec = 6'b111111; 12'd2569 : mem_out_dec = 6'b111111; 12'd2570 : mem_out_dec = 6'b111111; 12'd2571 : mem_out_dec = 6'b111111; 12'd2572 : mem_out_dec = 6'b111111; 12'd2573 : mem_out_dec = 6'b111111; 12'd2574 : mem_out_dec = 6'b111111; 12'd2575 : mem_out_dec = 6'b111111; 12'd2576 : mem_out_dec = 6'b111111; 12'd2577 : mem_out_dec = 6'b111111; 12'd2578 : mem_out_dec = 6'b111111; 12'd2579 : mem_out_dec = 6'b111111; 12'd2580 : mem_out_dec = 6'b111111; 12'd2581 : mem_out_dec = 6'b111111; 12'd2582 : mem_out_dec = 6'b111111; 12'd2583 : mem_out_dec = 6'b111111; 12'd2584 : mem_out_dec = 6'b111111; 12'd2585 : mem_out_dec = 6'b111111; 12'd2586 : mem_out_dec = 6'b111111; 12'd2587 : mem_out_dec = 6'b111111; 12'd2588 : mem_out_dec = 6'b111111; 12'd2589 : mem_out_dec = 6'b111111; 12'd2590 : mem_out_dec = 6'b111111; 12'd2591 : mem_out_dec = 6'b111111; 12'd2592 : mem_out_dec = 6'b111111; 12'd2593 : mem_out_dec = 6'b111111; 12'd2594 : mem_out_dec = 6'b111111; 12'd2595 : mem_out_dec = 6'b111111; 12'd2596 : mem_out_dec = 6'b111111; 12'd2597 : mem_out_dec = 6'b111111; 12'd2598 : mem_out_dec = 6'b111111; 12'd2599 : mem_out_dec = 6'b111111; 12'd2600 : mem_out_dec = 6'b111111; 12'd2601 : mem_out_dec = 6'b111111; 12'd2602 : mem_out_dec = 6'b111111; 12'd2603 : mem_out_dec = 6'b111111; 12'd2604 : mem_out_dec = 6'b111111; 12'd2605 : mem_out_dec = 6'b111111; 12'd2606 : mem_out_dec = 6'b000100; 12'd2607 : mem_out_dec = 6'b000101; 12'd2608 : mem_out_dec = 6'b000100; 12'd2609 : mem_out_dec = 6'b000100; 12'd2610 : mem_out_dec = 6'b000100; 12'd2611 : mem_out_dec = 6'b000101; 12'd2612 : mem_out_dec = 6'b000101; 12'd2613 : mem_out_dec = 6'b000110; 12'd2614 : mem_out_dec = 6'b000111; 12'd2615 : mem_out_dec = 6'b000111; 12'd2616 : mem_out_dec = 6'b000111; 12'd2617 : mem_out_dec = 6'b001000; 12'd2618 : mem_out_dec = 6'b001001; 12'd2619 : mem_out_dec = 6'b001010; 12'd2620 : mem_out_dec = 6'b001010; 12'd2621 : mem_out_dec = 6'b001011; 12'd2622 : mem_out_dec = 6'b001100; 12'd2623 : mem_out_dec = 6'b001101; 12'd2624 : mem_out_dec = 6'b111111; 12'd2625 : mem_out_dec = 6'b111111; 12'd2626 : mem_out_dec = 6'b111111; 12'd2627 : mem_out_dec = 6'b111111; 12'd2628 : mem_out_dec = 6'b111111; 12'd2629 : mem_out_dec = 6'b111111; 12'd2630 : mem_out_dec = 6'b111111; 12'd2631 : mem_out_dec = 6'b111111; 12'd2632 : mem_out_dec = 6'b111111; 12'd2633 : mem_out_dec = 6'b111111; 12'd2634 : mem_out_dec = 6'b111111; 12'd2635 : mem_out_dec = 6'b111111; 12'd2636 : mem_out_dec = 6'b111111; 12'd2637 : mem_out_dec = 6'b111111; 12'd2638 : mem_out_dec = 6'b111111; 12'd2639 : mem_out_dec = 6'b111111; 12'd2640 : mem_out_dec = 6'b111111; 12'd2641 : mem_out_dec = 6'b111111; 12'd2642 : mem_out_dec = 6'b111111; 12'd2643 : mem_out_dec = 6'b111111; 12'd2644 : mem_out_dec = 6'b111111; 12'd2645 : mem_out_dec = 6'b111111; 12'd2646 : mem_out_dec = 6'b111111; 12'd2647 : mem_out_dec = 6'b111111; 12'd2648 : mem_out_dec = 6'b111111; 12'd2649 : mem_out_dec = 6'b111111; 12'd2650 : mem_out_dec = 6'b111111; 12'd2651 : mem_out_dec = 6'b111111; 12'd2652 : mem_out_dec = 6'b111111; 12'd2653 : mem_out_dec = 6'b111111; 12'd2654 : mem_out_dec = 6'b111111; 12'd2655 : mem_out_dec = 6'b111111; 12'd2656 : mem_out_dec = 6'b111111; 12'd2657 : mem_out_dec = 6'b111111; 12'd2658 : mem_out_dec = 6'b111111; 12'd2659 : mem_out_dec = 6'b111111; 12'd2660 : mem_out_dec = 6'b111111; 12'd2661 : mem_out_dec = 6'b111111; 12'd2662 : mem_out_dec = 6'b111111; 12'd2663 : mem_out_dec = 6'b111111; 12'd2664 : mem_out_dec = 6'b111111; 12'd2665 : mem_out_dec = 6'b111111; 12'd2666 : mem_out_dec = 6'b111111; 12'd2667 : mem_out_dec = 6'b111111; 12'd2668 : mem_out_dec = 6'b111111; 12'd2669 : mem_out_dec = 6'b111111; 12'd2670 : mem_out_dec = 6'b111111; 12'd2671 : mem_out_dec = 6'b000100; 12'd2672 : mem_out_dec = 6'b000011; 12'd2673 : mem_out_dec = 6'b000011; 12'd2674 : mem_out_dec = 6'b000100; 12'd2675 : mem_out_dec = 6'b000100; 12'd2676 : mem_out_dec = 6'b000101; 12'd2677 : mem_out_dec = 6'b000110; 12'd2678 : mem_out_dec = 6'b000110; 12'd2679 : mem_out_dec = 6'b000111; 12'd2680 : mem_out_dec = 6'b000111; 12'd2681 : mem_out_dec = 6'b001000; 12'd2682 : mem_out_dec = 6'b001001; 12'd2683 : mem_out_dec = 6'b001001; 12'd2684 : mem_out_dec = 6'b001010; 12'd2685 : mem_out_dec = 6'b001011; 12'd2686 : mem_out_dec = 6'b001100; 12'd2687 : mem_out_dec = 6'b001100; 12'd2688 : mem_out_dec = 6'b111111; 12'd2689 : mem_out_dec = 6'b111111; 12'd2690 : mem_out_dec = 6'b111111; 12'd2691 : mem_out_dec = 6'b111111; 12'd2692 : mem_out_dec = 6'b111111; 12'd2693 : mem_out_dec = 6'b111111; 12'd2694 : mem_out_dec = 6'b111111; 12'd2695 : mem_out_dec = 6'b111111; 12'd2696 : mem_out_dec = 6'b111111; 12'd2697 : mem_out_dec = 6'b111111; 12'd2698 : mem_out_dec = 6'b111111; 12'd2699 : mem_out_dec = 6'b111111; 12'd2700 : mem_out_dec = 6'b111111; 12'd2701 : mem_out_dec = 6'b111111; 12'd2702 : mem_out_dec = 6'b111111; 12'd2703 : mem_out_dec = 6'b111111; 12'd2704 : mem_out_dec = 6'b111111; 12'd2705 : mem_out_dec = 6'b111111; 12'd2706 : mem_out_dec = 6'b111111; 12'd2707 : mem_out_dec = 6'b111111; 12'd2708 : mem_out_dec = 6'b111111; 12'd2709 : mem_out_dec = 6'b111111; 12'd2710 : mem_out_dec = 6'b111111; 12'd2711 : mem_out_dec = 6'b111111; 12'd2712 : mem_out_dec = 6'b111111; 12'd2713 : mem_out_dec = 6'b111111; 12'd2714 : mem_out_dec = 6'b111111; 12'd2715 : mem_out_dec = 6'b111111; 12'd2716 : mem_out_dec = 6'b111111; 12'd2717 : mem_out_dec = 6'b111111; 12'd2718 : mem_out_dec = 6'b111111; 12'd2719 : mem_out_dec = 6'b111111; 12'd2720 : mem_out_dec = 6'b111111; 12'd2721 : mem_out_dec = 6'b111111; 12'd2722 : mem_out_dec = 6'b111111; 12'd2723 : mem_out_dec = 6'b111111; 12'd2724 : mem_out_dec = 6'b111111; 12'd2725 : mem_out_dec = 6'b111111; 12'd2726 : mem_out_dec = 6'b111111; 12'd2727 : mem_out_dec = 6'b111111; 12'd2728 : mem_out_dec = 6'b111111; 12'd2729 : mem_out_dec = 6'b111111; 12'd2730 : mem_out_dec = 6'b111111; 12'd2731 : mem_out_dec = 6'b111111; 12'd2732 : mem_out_dec = 6'b111111; 12'd2733 : mem_out_dec = 6'b111111; 12'd2734 : mem_out_dec = 6'b111111; 12'd2735 : mem_out_dec = 6'b111111; 12'd2736 : mem_out_dec = 6'b000011; 12'd2737 : mem_out_dec = 6'b000011; 12'd2738 : mem_out_dec = 6'b000100; 12'd2739 : mem_out_dec = 6'b000100; 12'd2740 : mem_out_dec = 6'b000101; 12'd2741 : mem_out_dec = 6'b000101; 12'd2742 : mem_out_dec = 6'b000110; 12'd2743 : mem_out_dec = 6'b000111; 12'd2744 : mem_out_dec = 6'b000111; 12'd2745 : mem_out_dec = 6'b001000; 12'd2746 : mem_out_dec = 6'b001000; 12'd2747 : mem_out_dec = 6'b001001; 12'd2748 : mem_out_dec = 6'b001010; 12'd2749 : mem_out_dec = 6'b001011; 12'd2750 : mem_out_dec = 6'b001011; 12'd2751 : mem_out_dec = 6'b001100; 12'd2752 : mem_out_dec = 6'b111111; 12'd2753 : mem_out_dec = 6'b111111; 12'd2754 : mem_out_dec = 6'b111111; 12'd2755 : mem_out_dec = 6'b111111; 12'd2756 : mem_out_dec = 6'b111111; 12'd2757 : mem_out_dec = 6'b111111; 12'd2758 : mem_out_dec = 6'b111111; 12'd2759 : mem_out_dec = 6'b111111; 12'd2760 : mem_out_dec = 6'b111111; 12'd2761 : mem_out_dec = 6'b111111; 12'd2762 : mem_out_dec = 6'b111111; 12'd2763 : mem_out_dec = 6'b111111; 12'd2764 : mem_out_dec = 6'b111111; 12'd2765 : mem_out_dec = 6'b111111; 12'd2766 : mem_out_dec = 6'b111111; 12'd2767 : mem_out_dec = 6'b111111; 12'd2768 : mem_out_dec = 6'b111111; 12'd2769 : mem_out_dec = 6'b111111; 12'd2770 : mem_out_dec = 6'b111111; 12'd2771 : mem_out_dec = 6'b111111; 12'd2772 : mem_out_dec = 6'b111111; 12'd2773 : mem_out_dec = 6'b111111; 12'd2774 : mem_out_dec = 6'b111111; 12'd2775 : mem_out_dec = 6'b111111; 12'd2776 : mem_out_dec = 6'b111111; 12'd2777 : mem_out_dec = 6'b111111; 12'd2778 : mem_out_dec = 6'b111111; 12'd2779 : mem_out_dec = 6'b111111; 12'd2780 : mem_out_dec = 6'b111111; 12'd2781 : mem_out_dec = 6'b111111; 12'd2782 : mem_out_dec = 6'b111111; 12'd2783 : mem_out_dec = 6'b111111; 12'd2784 : mem_out_dec = 6'b111111; 12'd2785 : mem_out_dec = 6'b111111; 12'd2786 : mem_out_dec = 6'b111111; 12'd2787 : mem_out_dec = 6'b111111; 12'd2788 : mem_out_dec = 6'b111111; 12'd2789 : mem_out_dec = 6'b111111; 12'd2790 : mem_out_dec = 6'b111111; 12'd2791 : mem_out_dec = 6'b111111; 12'd2792 : mem_out_dec = 6'b111111; 12'd2793 : mem_out_dec = 6'b111111; 12'd2794 : mem_out_dec = 6'b111111; 12'd2795 : mem_out_dec = 6'b111111; 12'd2796 : mem_out_dec = 6'b111111; 12'd2797 : mem_out_dec = 6'b111111; 12'd2798 : mem_out_dec = 6'b111111; 12'd2799 : mem_out_dec = 6'b111111; 12'd2800 : mem_out_dec = 6'b111111; 12'd2801 : mem_out_dec = 6'b000011; 12'd2802 : mem_out_dec = 6'b000011; 12'd2803 : mem_out_dec = 6'b000100; 12'd2804 : mem_out_dec = 6'b000101; 12'd2805 : mem_out_dec = 6'b000101; 12'd2806 : mem_out_dec = 6'b000110; 12'd2807 : mem_out_dec = 6'b000111; 12'd2808 : mem_out_dec = 6'b000111; 12'd2809 : mem_out_dec = 6'b000111; 12'd2810 : mem_out_dec = 6'b001000; 12'd2811 : mem_out_dec = 6'b001001; 12'd2812 : mem_out_dec = 6'b001010; 12'd2813 : mem_out_dec = 6'b001010; 12'd2814 : mem_out_dec = 6'b001011; 12'd2815 : mem_out_dec = 6'b001100; 12'd2816 : mem_out_dec = 6'b111111; 12'd2817 : mem_out_dec = 6'b111111; 12'd2818 : mem_out_dec = 6'b111111; 12'd2819 : mem_out_dec = 6'b111111; 12'd2820 : mem_out_dec = 6'b111111; 12'd2821 : mem_out_dec = 6'b111111; 12'd2822 : mem_out_dec = 6'b111111; 12'd2823 : mem_out_dec = 6'b111111; 12'd2824 : mem_out_dec = 6'b111111; 12'd2825 : mem_out_dec = 6'b111111; 12'd2826 : mem_out_dec = 6'b111111; 12'd2827 : mem_out_dec = 6'b111111; 12'd2828 : mem_out_dec = 6'b111111; 12'd2829 : mem_out_dec = 6'b111111; 12'd2830 : mem_out_dec = 6'b111111; 12'd2831 : mem_out_dec = 6'b111111; 12'd2832 : mem_out_dec = 6'b111111; 12'd2833 : mem_out_dec = 6'b111111; 12'd2834 : mem_out_dec = 6'b111111; 12'd2835 : mem_out_dec = 6'b111111; 12'd2836 : mem_out_dec = 6'b111111; 12'd2837 : mem_out_dec = 6'b111111; 12'd2838 : mem_out_dec = 6'b111111; 12'd2839 : mem_out_dec = 6'b111111; 12'd2840 : mem_out_dec = 6'b111111; 12'd2841 : mem_out_dec = 6'b111111; 12'd2842 : mem_out_dec = 6'b111111; 12'd2843 : mem_out_dec = 6'b111111; 12'd2844 : mem_out_dec = 6'b111111; 12'd2845 : mem_out_dec = 6'b111111; 12'd2846 : mem_out_dec = 6'b111111; 12'd2847 : mem_out_dec = 6'b111111; 12'd2848 : mem_out_dec = 6'b111111; 12'd2849 : mem_out_dec = 6'b111111; 12'd2850 : mem_out_dec = 6'b111111; 12'd2851 : mem_out_dec = 6'b111111; 12'd2852 : mem_out_dec = 6'b111111; 12'd2853 : mem_out_dec = 6'b111111; 12'd2854 : mem_out_dec = 6'b111111; 12'd2855 : mem_out_dec = 6'b111111; 12'd2856 : mem_out_dec = 6'b111111; 12'd2857 : mem_out_dec = 6'b111111; 12'd2858 : mem_out_dec = 6'b111111; 12'd2859 : mem_out_dec = 6'b111111; 12'd2860 : mem_out_dec = 6'b111111; 12'd2861 : mem_out_dec = 6'b111111; 12'd2862 : mem_out_dec = 6'b111111; 12'd2863 : mem_out_dec = 6'b111111; 12'd2864 : mem_out_dec = 6'b111111; 12'd2865 : mem_out_dec = 6'b111111; 12'd2866 : mem_out_dec = 6'b000011; 12'd2867 : mem_out_dec = 6'b000100; 12'd2868 : mem_out_dec = 6'b000100; 12'd2869 : mem_out_dec = 6'b000101; 12'd2870 : mem_out_dec = 6'b000110; 12'd2871 : mem_out_dec = 6'b000110; 12'd2872 : mem_out_dec = 6'b000110; 12'd2873 : mem_out_dec = 6'b000111; 12'd2874 : mem_out_dec = 6'b001000; 12'd2875 : mem_out_dec = 6'b001001; 12'd2876 : mem_out_dec = 6'b001001; 12'd2877 : mem_out_dec = 6'b001010; 12'd2878 : mem_out_dec = 6'b001011; 12'd2879 : mem_out_dec = 6'b001100; 12'd2880 : mem_out_dec = 6'b111111; 12'd2881 : mem_out_dec = 6'b111111; 12'd2882 : mem_out_dec = 6'b111111; 12'd2883 : mem_out_dec = 6'b111111; 12'd2884 : mem_out_dec = 6'b111111; 12'd2885 : mem_out_dec = 6'b111111; 12'd2886 : mem_out_dec = 6'b111111; 12'd2887 : mem_out_dec = 6'b111111; 12'd2888 : mem_out_dec = 6'b111111; 12'd2889 : mem_out_dec = 6'b111111; 12'd2890 : mem_out_dec = 6'b111111; 12'd2891 : mem_out_dec = 6'b111111; 12'd2892 : mem_out_dec = 6'b111111; 12'd2893 : mem_out_dec = 6'b111111; 12'd2894 : mem_out_dec = 6'b111111; 12'd2895 : mem_out_dec = 6'b111111; 12'd2896 : mem_out_dec = 6'b111111; 12'd2897 : mem_out_dec = 6'b111111; 12'd2898 : mem_out_dec = 6'b111111; 12'd2899 : mem_out_dec = 6'b111111; 12'd2900 : mem_out_dec = 6'b111111; 12'd2901 : mem_out_dec = 6'b111111; 12'd2902 : mem_out_dec = 6'b111111; 12'd2903 : mem_out_dec = 6'b111111; 12'd2904 : mem_out_dec = 6'b111111; 12'd2905 : mem_out_dec = 6'b111111; 12'd2906 : mem_out_dec = 6'b111111; 12'd2907 : mem_out_dec = 6'b111111; 12'd2908 : mem_out_dec = 6'b111111; 12'd2909 : mem_out_dec = 6'b111111; 12'd2910 : mem_out_dec = 6'b111111; 12'd2911 : mem_out_dec = 6'b111111; 12'd2912 : mem_out_dec = 6'b111111; 12'd2913 : mem_out_dec = 6'b111111; 12'd2914 : mem_out_dec = 6'b111111; 12'd2915 : mem_out_dec = 6'b111111; 12'd2916 : mem_out_dec = 6'b111111; 12'd2917 : mem_out_dec = 6'b111111; 12'd2918 : mem_out_dec = 6'b111111; 12'd2919 : mem_out_dec = 6'b111111; 12'd2920 : mem_out_dec = 6'b111111; 12'd2921 : mem_out_dec = 6'b111111; 12'd2922 : mem_out_dec = 6'b111111; 12'd2923 : mem_out_dec = 6'b111111; 12'd2924 : mem_out_dec = 6'b111111; 12'd2925 : mem_out_dec = 6'b111111; 12'd2926 : mem_out_dec = 6'b111111; 12'd2927 : mem_out_dec = 6'b111111; 12'd2928 : mem_out_dec = 6'b111111; 12'd2929 : mem_out_dec = 6'b111111; 12'd2930 : mem_out_dec = 6'b111111; 12'd2931 : mem_out_dec = 6'b000100; 12'd2932 : mem_out_dec = 6'b000100; 12'd2933 : mem_out_dec = 6'b000101; 12'd2934 : mem_out_dec = 6'b000101; 12'd2935 : mem_out_dec = 6'b000110; 12'd2936 : mem_out_dec = 6'b000110; 12'd2937 : mem_out_dec = 6'b000111; 12'd2938 : mem_out_dec = 6'b001000; 12'd2939 : mem_out_dec = 6'b001000; 12'd2940 : mem_out_dec = 6'b001001; 12'd2941 : mem_out_dec = 6'b001010; 12'd2942 : mem_out_dec = 6'b001011; 12'd2943 : mem_out_dec = 6'b001011; 12'd2944 : mem_out_dec = 6'b111111; 12'd2945 : mem_out_dec = 6'b111111; 12'd2946 : mem_out_dec = 6'b111111; 12'd2947 : mem_out_dec = 6'b111111; 12'd2948 : mem_out_dec = 6'b111111; 12'd2949 : mem_out_dec = 6'b111111; 12'd2950 : mem_out_dec = 6'b111111; 12'd2951 : mem_out_dec = 6'b111111; 12'd2952 : mem_out_dec = 6'b111111; 12'd2953 : mem_out_dec = 6'b111111; 12'd2954 : mem_out_dec = 6'b111111; 12'd2955 : mem_out_dec = 6'b111111; 12'd2956 : mem_out_dec = 6'b111111; 12'd2957 : mem_out_dec = 6'b111111; 12'd2958 : mem_out_dec = 6'b111111; 12'd2959 : mem_out_dec = 6'b111111; 12'd2960 : mem_out_dec = 6'b111111; 12'd2961 : mem_out_dec = 6'b111111; 12'd2962 : mem_out_dec = 6'b111111; 12'd2963 : mem_out_dec = 6'b111111; 12'd2964 : mem_out_dec = 6'b111111; 12'd2965 : mem_out_dec = 6'b111111; 12'd2966 : mem_out_dec = 6'b111111; 12'd2967 : mem_out_dec = 6'b111111; 12'd2968 : mem_out_dec = 6'b111111; 12'd2969 : mem_out_dec = 6'b111111; 12'd2970 : mem_out_dec = 6'b111111; 12'd2971 : mem_out_dec = 6'b111111; 12'd2972 : mem_out_dec = 6'b111111; 12'd2973 : mem_out_dec = 6'b111111; 12'd2974 : mem_out_dec = 6'b111111; 12'd2975 : mem_out_dec = 6'b111111; 12'd2976 : mem_out_dec = 6'b111111; 12'd2977 : mem_out_dec = 6'b111111; 12'd2978 : mem_out_dec = 6'b111111; 12'd2979 : mem_out_dec = 6'b111111; 12'd2980 : mem_out_dec = 6'b111111; 12'd2981 : mem_out_dec = 6'b111111; 12'd2982 : mem_out_dec = 6'b111111; 12'd2983 : mem_out_dec = 6'b111111; 12'd2984 : mem_out_dec = 6'b111111; 12'd2985 : mem_out_dec = 6'b111111; 12'd2986 : mem_out_dec = 6'b111111; 12'd2987 : mem_out_dec = 6'b111111; 12'd2988 : mem_out_dec = 6'b111111; 12'd2989 : mem_out_dec = 6'b111111; 12'd2990 : mem_out_dec = 6'b111111; 12'd2991 : mem_out_dec = 6'b111111; 12'd2992 : mem_out_dec = 6'b111111; 12'd2993 : mem_out_dec = 6'b111111; 12'd2994 : mem_out_dec = 6'b111111; 12'd2995 : mem_out_dec = 6'b111111; 12'd2996 : mem_out_dec = 6'b000100; 12'd2997 : mem_out_dec = 6'b000101; 12'd2998 : mem_out_dec = 6'b000101; 12'd2999 : mem_out_dec = 6'b000110; 12'd3000 : mem_out_dec = 6'b000110; 12'd3001 : mem_out_dec = 6'b000111; 12'd3002 : mem_out_dec = 6'b000111; 12'd3003 : mem_out_dec = 6'b001000; 12'd3004 : mem_out_dec = 6'b001001; 12'd3005 : mem_out_dec = 6'b001010; 12'd3006 : mem_out_dec = 6'b001010; 12'd3007 : mem_out_dec = 6'b001011; 12'd3008 : mem_out_dec = 6'b111111; 12'd3009 : mem_out_dec = 6'b111111; 12'd3010 : mem_out_dec = 6'b111111; 12'd3011 : mem_out_dec = 6'b111111; 12'd3012 : mem_out_dec = 6'b111111; 12'd3013 : mem_out_dec = 6'b111111; 12'd3014 : mem_out_dec = 6'b111111; 12'd3015 : mem_out_dec = 6'b111111; 12'd3016 : mem_out_dec = 6'b111111; 12'd3017 : mem_out_dec = 6'b111111; 12'd3018 : mem_out_dec = 6'b111111; 12'd3019 : mem_out_dec = 6'b111111; 12'd3020 : mem_out_dec = 6'b111111; 12'd3021 : mem_out_dec = 6'b111111; 12'd3022 : mem_out_dec = 6'b111111; 12'd3023 : mem_out_dec = 6'b111111; 12'd3024 : mem_out_dec = 6'b111111; 12'd3025 : mem_out_dec = 6'b111111; 12'd3026 : mem_out_dec = 6'b111111; 12'd3027 : mem_out_dec = 6'b111111; 12'd3028 : mem_out_dec = 6'b111111; 12'd3029 : mem_out_dec = 6'b111111; 12'd3030 : mem_out_dec = 6'b111111; 12'd3031 : mem_out_dec = 6'b111111; 12'd3032 : mem_out_dec = 6'b111111; 12'd3033 : mem_out_dec = 6'b111111; 12'd3034 : mem_out_dec = 6'b111111; 12'd3035 : mem_out_dec = 6'b111111; 12'd3036 : mem_out_dec = 6'b111111; 12'd3037 : mem_out_dec = 6'b111111; 12'd3038 : mem_out_dec = 6'b111111; 12'd3039 : mem_out_dec = 6'b111111; 12'd3040 : mem_out_dec = 6'b111111; 12'd3041 : mem_out_dec = 6'b111111; 12'd3042 : mem_out_dec = 6'b111111; 12'd3043 : mem_out_dec = 6'b111111; 12'd3044 : mem_out_dec = 6'b111111; 12'd3045 : mem_out_dec = 6'b111111; 12'd3046 : mem_out_dec = 6'b111111; 12'd3047 : mem_out_dec = 6'b111111; 12'd3048 : mem_out_dec = 6'b111111; 12'd3049 : mem_out_dec = 6'b111111; 12'd3050 : mem_out_dec = 6'b111111; 12'd3051 : mem_out_dec = 6'b111111; 12'd3052 : mem_out_dec = 6'b111111; 12'd3053 : mem_out_dec = 6'b111111; 12'd3054 : mem_out_dec = 6'b111111; 12'd3055 : mem_out_dec = 6'b111111; 12'd3056 : mem_out_dec = 6'b111111; 12'd3057 : mem_out_dec = 6'b111111; 12'd3058 : mem_out_dec = 6'b111111; 12'd3059 : mem_out_dec = 6'b111111; 12'd3060 : mem_out_dec = 6'b111111; 12'd3061 : mem_out_dec = 6'b000100; 12'd3062 : mem_out_dec = 6'b000101; 12'd3063 : mem_out_dec = 6'b000110; 12'd3064 : mem_out_dec = 6'b000110; 12'd3065 : mem_out_dec = 6'b000111; 12'd3066 : mem_out_dec = 6'b000111; 12'd3067 : mem_out_dec = 6'b001000; 12'd3068 : mem_out_dec = 6'b001001; 12'd3069 : mem_out_dec = 6'b001001; 12'd3070 : mem_out_dec = 6'b001010; 12'd3071 : mem_out_dec = 6'b001011; 12'd3072 : mem_out_dec = 6'b111111; 12'd3073 : mem_out_dec = 6'b111111; 12'd3074 : mem_out_dec = 6'b111111; 12'd3075 : mem_out_dec = 6'b111111; 12'd3076 : mem_out_dec = 6'b111111; 12'd3077 : mem_out_dec = 6'b111111; 12'd3078 : mem_out_dec = 6'b111111; 12'd3079 : mem_out_dec = 6'b111111; 12'd3080 : mem_out_dec = 6'b111111; 12'd3081 : mem_out_dec = 6'b111111; 12'd3082 : mem_out_dec = 6'b111111; 12'd3083 : mem_out_dec = 6'b111111; 12'd3084 : mem_out_dec = 6'b111111; 12'd3085 : mem_out_dec = 6'b111111; 12'd3086 : mem_out_dec = 6'b111111; 12'd3087 : mem_out_dec = 6'b111111; 12'd3088 : mem_out_dec = 6'b111111; 12'd3089 : mem_out_dec = 6'b111111; 12'd3090 : mem_out_dec = 6'b111111; 12'd3091 : mem_out_dec = 6'b111111; 12'd3092 : mem_out_dec = 6'b111111; 12'd3093 : mem_out_dec = 6'b111111; 12'd3094 : mem_out_dec = 6'b111111; 12'd3095 : mem_out_dec = 6'b111111; 12'd3096 : mem_out_dec = 6'b111111; 12'd3097 : mem_out_dec = 6'b111111; 12'd3098 : mem_out_dec = 6'b111111; 12'd3099 : mem_out_dec = 6'b111111; 12'd3100 : mem_out_dec = 6'b111111; 12'd3101 : mem_out_dec = 6'b111111; 12'd3102 : mem_out_dec = 6'b111111; 12'd3103 : mem_out_dec = 6'b111111; 12'd3104 : mem_out_dec = 6'b111111; 12'd3105 : mem_out_dec = 6'b111111; 12'd3106 : mem_out_dec = 6'b111111; 12'd3107 : mem_out_dec = 6'b111111; 12'd3108 : mem_out_dec = 6'b111111; 12'd3109 : mem_out_dec = 6'b111111; 12'd3110 : mem_out_dec = 6'b111111; 12'd3111 : mem_out_dec = 6'b111111; 12'd3112 : mem_out_dec = 6'b111111; 12'd3113 : mem_out_dec = 6'b111111; 12'd3114 : mem_out_dec = 6'b111111; 12'd3115 : mem_out_dec = 6'b111111; 12'd3116 : mem_out_dec = 6'b111111; 12'd3117 : mem_out_dec = 6'b111111; 12'd3118 : mem_out_dec = 6'b111111; 12'd3119 : mem_out_dec = 6'b111111; 12'd3120 : mem_out_dec = 6'b111111; 12'd3121 : mem_out_dec = 6'b111111; 12'd3122 : mem_out_dec = 6'b111111; 12'd3123 : mem_out_dec = 6'b111111; 12'd3124 : mem_out_dec = 6'b111111; 12'd3125 : mem_out_dec = 6'b111111; 12'd3126 : mem_out_dec = 6'b000100; 12'd3127 : mem_out_dec = 6'b000101; 12'd3128 : mem_out_dec = 6'b000101; 12'd3129 : mem_out_dec = 6'b000110; 12'd3130 : mem_out_dec = 6'b000110; 12'd3131 : mem_out_dec = 6'b000111; 12'd3132 : mem_out_dec = 6'b001000; 12'd3133 : mem_out_dec = 6'b001000; 12'd3134 : mem_out_dec = 6'b001001; 12'd3135 : mem_out_dec = 6'b001010; 12'd3136 : mem_out_dec = 6'b111111; 12'd3137 : mem_out_dec = 6'b111111; 12'd3138 : mem_out_dec = 6'b111111; 12'd3139 : mem_out_dec = 6'b111111; 12'd3140 : mem_out_dec = 6'b111111; 12'd3141 : mem_out_dec = 6'b111111; 12'd3142 : mem_out_dec = 6'b111111; 12'd3143 : mem_out_dec = 6'b111111; 12'd3144 : mem_out_dec = 6'b111111; 12'd3145 : mem_out_dec = 6'b111111; 12'd3146 : mem_out_dec = 6'b111111; 12'd3147 : mem_out_dec = 6'b111111; 12'd3148 : mem_out_dec = 6'b111111; 12'd3149 : mem_out_dec = 6'b111111; 12'd3150 : mem_out_dec = 6'b111111; 12'd3151 : mem_out_dec = 6'b111111; 12'd3152 : mem_out_dec = 6'b111111; 12'd3153 : mem_out_dec = 6'b111111; 12'd3154 : mem_out_dec = 6'b111111; 12'd3155 : mem_out_dec = 6'b111111; 12'd3156 : mem_out_dec = 6'b111111; 12'd3157 : mem_out_dec = 6'b111111; 12'd3158 : mem_out_dec = 6'b111111; 12'd3159 : mem_out_dec = 6'b111111; 12'd3160 : mem_out_dec = 6'b111111; 12'd3161 : mem_out_dec = 6'b111111; 12'd3162 : mem_out_dec = 6'b111111; 12'd3163 : mem_out_dec = 6'b111111; 12'd3164 : mem_out_dec = 6'b111111; 12'd3165 : mem_out_dec = 6'b111111; 12'd3166 : mem_out_dec = 6'b111111; 12'd3167 : mem_out_dec = 6'b111111; 12'd3168 : mem_out_dec = 6'b111111; 12'd3169 : mem_out_dec = 6'b111111; 12'd3170 : mem_out_dec = 6'b111111; 12'd3171 : mem_out_dec = 6'b111111; 12'd3172 : mem_out_dec = 6'b111111; 12'd3173 : mem_out_dec = 6'b111111; 12'd3174 : mem_out_dec = 6'b111111; 12'd3175 : mem_out_dec = 6'b111111; 12'd3176 : mem_out_dec = 6'b111111; 12'd3177 : mem_out_dec = 6'b111111; 12'd3178 : mem_out_dec = 6'b111111; 12'd3179 : mem_out_dec = 6'b111111; 12'd3180 : mem_out_dec = 6'b111111; 12'd3181 : mem_out_dec = 6'b111111; 12'd3182 : mem_out_dec = 6'b111111; 12'd3183 : mem_out_dec = 6'b111111; 12'd3184 : mem_out_dec = 6'b111111; 12'd3185 : mem_out_dec = 6'b111111; 12'd3186 : mem_out_dec = 6'b111111; 12'd3187 : mem_out_dec = 6'b111111; 12'd3188 : mem_out_dec = 6'b111111; 12'd3189 : mem_out_dec = 6'b111111; 12'd3190 : mem_out_dec = 6'b111111; 12'd3191 : mem_out_dec = 6'b000100; 12'd3192 : mem_out_dec = 6'b000100; 12'd3193 : mem_out_dec = 6'b000101; 12'd3194 : mem_out_dec = 6'b000110; 12'd3195 : mem_out_dec = 6'b000110; 12'd3196 : mem_out_dec = 6'b000111; 12'd3197 : mem_out_dec = 6'b001000; 12'd3198 : mem_out_dec = 6'b001000; 12'd3199 : mem_out_dec = 6'b001001; 12'd3200 : mem_out_dec = 6'b111111; 12'd3201 : mem_out_dec = 6'b111111; 12'd3202 : mem_out_dec = 6'b111111; 12'd3203 : mem_out_dec = 6'b111111; 12'd3204 : mem_out_dec = 6'b111111; 12'd3205 : mem_out_dec = 6'b111111; 12'd3206 : mem_out_dec = 6'b111111; 12'd3207 : mem_out_dec = 6'b111111; 12'd3208 : mem_out_dec = 6'b111111; 12'd3209 : mem_out_dec = 6'b111111; 12'd3210 : mem_out_dec = 6'b111111; 12'd3211 : mem_out_dec = 6'b111111; 12'd3212 : mem_out_dec = 6'b111111; 12'd3213 : mem_out_dec = 6'b111111; 12'd3214 : mem_out_dec = 6'b111111; 12'd3215 : mem_out_dec = 6'b111111; 12'd3216 : mem_out_dec = 6'b111111; 12'd3217 : mem_out_dec = 6'b111111; 12'd3218 : mem_out_dec = 6'b111111; 12'd3219 : mem_out_dec = 6'b111111; 12'd3220 : mem_out_dec = 6'b111111; 12'd3221 : mem_out_dec = 6'b111111; 12'd3222 : mem_out_dec = 6'b111111; 12'd3223 : mem_out_dec = 6'b111111; 12'd3224 : mem_out_dec = 6'b111111; 12'd3225 : mem_out_dec = 6'b111111; 12'd3226 : mem_out_dec = 6'b111111; 12'd3227 : mem_out_dec = 6'b111111; 12'd3228 : mem_out_dec = 6'b111111; 12'd3229 : mem_out_dec = 6'b111111; 12'd3230 : mem_out_dec = 6'b111111; 12'd3231 : mem_out_dec = 6'b111111; 12'd3232 : mem_out_dec = 6'b111111; 12'd3233 : mem_out_dec = 6'b111111; 12'd3234 : mem_out_dec = 6'b111111; 12'd3235 : mem_out_dec = 6'b111111; 12'd3236 : mem_out_dec = 6'b111111; 12'd3237 : mem_out_dec = 6'b111111; 12'd3238 : mem_out_dec = 6'b111111; 12'd3239 : mem_out_dec = 6'b111111; 12'd3240 : mem_out_dec = 6'b111111; 12'd3241 : mem_out_dec = 6'b111111; 12'd3242 : mem_out_dec = 6'b111111; 12'd3243 : mem_out_dec = 6'b111111; 12'd3244 : mem_out_dec = 6'b111111; 12'd3245 : mem_out_dec = 6'b111111; 12'd3246 : mem_out_dec = 6'b111111; 12'd3247 : mem_out_dec = 6'b111111; 12'd3248 : mem_out_dec = 6'b111111; 12'd3249 : mem_out_dec = 6'b111111; 12'd3250 : mem_out_dec = 6'b111111; 12'd3251 : mem_out_dec = 6'b111111; 12'd3252 : mem_out_dec = 6'b111111; 12'd3253 : mem_out_dec = 6'b111111; 12'd3254 : mem_out_dec = 6'b111111; 12'd3255 : mem_out_dec = 6'b111111; 12'd3256 : mem_out_dec = 6'b000100; 12'd3257 : mem_out_dec = 6'b000100; 12'd3258 : mem_out_dec = 6'b000101; 12'd3259 : mem_out_dec = 6'b000110; 12'd3260 : mem_out_dec = 6'b000110; 12'd3261 : mem_out_dec = 6'b000111; 12'd3262 : mem_out_dec = 6'b001000; 12'd3263 : mem_out_dec = 6'b001001; 12'd3264 : mem_out_dec = 6'b111111; 12'd3265 : mem_out_dec = 6'b111111; 12'd3266 : mem_out_dec = 6'b111111; 12'd3267 : mem_out_dec = 6'b111111; 12'd3268 : mem_out_dec = 6'b111111; 12'd3269 : mem_out_dec = 6'b111111; 12'd3270 : mem_out_dec = 6'b111111; 12'd3271 : mem_out_dec = 6'b111111; 12'd3272 : mem_out_dec = 6'b111111; 12'd3273 : mem_out_dec = 6'b111111; 12'd3274 : mem_out_dec = 6'b111111; 12'd3275 : mem_out_dec = 6'b111111; 12'd3276 : mem_out_dec = 6'b111111; 12'd3277 : mem_out_dec = 6'b111111; 12'd3278 : mem_out_dec = 6'b111111; 12'd3279 : mem_out_dec = 6'b111111; 12'd3280 : mem_out_dec = 6'b111111; 12'd3281 : mem_out_dec = 6'b111111; 12'd3282 : mem_out_dec = 6'b111111; 12'd3283 : mem_out_dec = 6'b111111; 12'd3284 : mem_out_dec = 6'b111111; 12'd3285 : mem_out_dec = 6'b111111; 12'd3286 : mem_out_dec = 6'b111111; 12'd3287 : mem_out_dec = 6'b111111; 12'd3288 : mem_out_dec = 6'b111111; 12'd3289 : mem_out_dec = 6'b111111; 12'd3290 : mem_out_dec = 6'b111111; 12'd3291 : mem_out_dec = 6'b111111; 12'd3292 : mem_out_dec = 6'b111111; 12'd3293 : mem_out_dec = 6'b111111; 12'd3294 : mem_out_dec = 6'b111111; 12'd3295 : mem_out_dec = 6'b111111; 12'd3296 : mem_out_dec = 6'b111111; 12'd3297 : mem_out_dec = 6'b111111; 12'd3298 : mem_out_dec = 6'b111111; 12'd3299 : mem_out_dec = 6'b111111; 12'd3300 : mem_out_dec = 6'b111111; 12'd3301 : mem_out_dec = 6'b111111; 12'd3302 : mem_out_dec = 6'b111111; 12'd3303 : mem_out_dec = 6'b111111; 12'd3304 : mem_out_dec = 6'b111111; 12'd3305 : mem_out_dec = 6'b111111; 12'd3306 : mem_out_dec = 6'b111111; 12'd3307 : mem_out_dec = 6'b111111; 12'd3308 : mem_out_dec = 6'b111111; 12'd3309 : mem_out_dec = 6'b111111; 12'd3310 : mem_out_dec = 6'b111111; 12'd3311 : mem_out_dec = 6'b111111; 12'd3312 : mem_out_dec = 6'b111111; 12'd3313 : mem_out_dec = 6'b111111; 12'd3314 : mem_out_dec = 6'b111111; 12'd3315 : mem_out_dec = 6'b111111; 12'd3316 : mem_out_dec = 6'b111111; 12'd3317 : mem_out_dec = 6'b111111; 12'd3318 : mem_out_dec = 6'b111111; 12'd3319 : mem_out_dec = 6'b111111; 12'd3320 : mem_out_dec = 6'b111111; 12'd3321 : mem_out_dec = 6'b000100; 12'd3322 : mem_out_dec = 6'b000100; 12'd3323 : mem_out_dec = 6'b000101; 12'd3324 : mem_out_dec = 6'b000110; 12'd3325 : mem_out_dec = 6'b000111; 12'd3326 : mem_out_dec = 6'b001000; 12'd3327 : mem_out_dec = 6'b001000; 12'd3328 : mem_out_dec = 6'b111111; 12'd3329 : mem_out_dec = 6'b111111; 12'd3330 : mem_out_dec = 6'b111111; 12'd3331 : mem_out_dec = 6'b111111; 12'd3332 : mem_out_dec = 6'b111111; 12'd3333 : mem_out_dec = 6'b111111; 12'd3334 : mem_out_dec = 6'b111111; 12'd3335 : mem_out_dec = 6'b111111; 12'd3336 : mem_out_dec = 6'b111111; 12'd3337 : mem_out_dec = 6'b111111; 12'd3338 : mem_out_dec = 6'b111111; 12'd3339 : mem_out_dec = 6'b111111; 12'd3340 : mem_out_dec = 6'b111111; 12'd3341 : mem_out_dec = 6'b111111; 12'd3342 : mem_out_dec = 6'b111111; 12'd3343 : mem_out_dec = 6'b111111; 12'd3344 : mem_out_dec = 6'b111111; 12'd3345 : mem_out_dec = 6'b111111; 12'd3346 : mem_out_dec = 6'b111111; 12'd3347 : mem_out_dec = 6'b111111; 12'd3348 : mem_out_dec = 6'b111111; 12'd3349 : mem_out_dec = 6'b111111; 12'd3350 : mem_out_dec = 6'b111111; 12'd3351 : mem_out_dec = 6'b111111; 12'd3352 : mem_out_dec = 6'b111111; 12'd3353 : mem_out_dec = 6'b111111; 12'd3354 : mem_out_dec = 6'b111111; 12'd3355 : mem_out_dec = 6'b111111; 12'd3356 : mem_out_dec = 6'b111111; 12'd3357 : mem_out_dec = 6'b111111; 12'd3358 : mem_out_dec = 6'b111111; 12'd3359 : mem_out_dec = 6'b111111; 12'd3360 : mem_out_dec = 6'b111111; 12'd3361 : mem_out_dec = 6'b111111; 12'd3362 : mem_out_dec = 6'b111111; 12'd3363 : mem_out_dec = 6'b111111; 12'd3364 : mem_out_dec = 6'b111111; 12'd3365 : mem_out_dec = 6'b111111; 12'd3366 : mem_out_dec = 6'b111111; 12'd3367 : mem_out_dec = 6'b111111; 12'd3368 : mem_out_dec = 6'b111111; 12'd3369 : mem_out_dec = 6'b111111; 12'd3370 : mem_out_dec = 6'b111111; 12'd3371 : mem_out_dec = 6'b111111; 12'd3372 : mem_out_dec = 6'b111111; 12'd3373 : mem_out_dec = 6'b111111; 12'd3374 : mem_out_dec = 6'b111111; 12'd3375 : mem_out_dec = 6'b111111; 12'd3376 : mem_out_dec = 6'b111111; 12'd3377 : mem_out_dec = 6'b111111; 12'd3378 : mem_out_dec = 6'b111111; 12'd3379 : mem_out_dec = 6'b111111; 12'd3380 : mem_out_dec = 6'b111111; 12'd3381 : mem_out_dec = 6'b111111; 12'd3382 : mem_out_dec = 6'b111111; 12'd3383 : mem_out_dec = 6'b111111; 12'd3384 : mem_out_dec = 6'b111111; 12'd3385 : mem_out_dec = 6'b111111; 12'd3386 : mem_out_dec = 6'b000100; 12'd3387 : mem_out_dec = 6'b000101; 12'd3388 : mem_out_dec = 6'b000110; 12'd3389 : mem_out_dec = 6'b000110; 12'd3390 : mem_out_dec = 6'b000111; 12'd3391 : mem_out_dec = 6'b001000; 12'd3392 : mem_out_dec = 6'b111111; 12'd3393 : mem_out_dec = 6'b111111; 12'd3394 : mem_out_dec = 6'b111111; 12'd3395 : mem_out_dec = 6'b111111; 12'd3396 : mem_out_dec = 6'b111111; 12'd3397 : mem_out_dec = 6'b111111; 12'd3398 : mem_out_dec = 6'b111111; 12'd3399 : mem_out_dec = 6'b111111; 12'd3400 : mem_out_dec = 6'b111111; 12'd3401 : mem_out_dec = 6'b111111; 12'd3402 : mem_out_dec = 6'b111111; 12'd3403 : mem_out_dec = 6'b111111; 12'd3404 : mem_out_dec = 6'b111111; 12'd3405 : mem_out_dec = 6'b111111; 12'd3406 : mem_out_dec = 6'b111111; 12'd3407 : mem_out_dec = 6'b111111; 12'd3408 : mem_out_dec = 6'b111111; 12'd3409 : mem_out_dec = 6'b111111; 12'd3410 : mem_out_dec = 6'b111111; 12'd3411 : mem_out_dec = 6'b111111; 12'd3412 : mem_out_dec = 6'b111111; 12'd3413 : mem_out_dec = 6'b111111; 12'd3414 : mem_out_dec = 6'b111111; 12'd3415 : mem_out_dec = 6'b111111; 12'd3416 : mem_out_dec = 6'b111111; 12'd3417 : mem_out_dec = 6'b111111; 12'd3418 : mem_out_dec = 6'b111111; 12'd3419 : mem_out_dec = 6'b111111; 12'd3420 : mem_out_dec = 6'b111111; 12'd3421 : mem_out_dec = 6'b111111; 12'd3422 : mem_out_dec = 6'b111111; 12'd3423 : mem_out_dec = 6'b111111; 12'd3424 : mem_out_dec = 6'b111111; 12'd3425 : mem_out_dec = 6'b111111; 12'd3426 : mem_out_dec = 6'b111111; 12'd3427 : mem_out_dec = 6'b111111; 12'd3428 : mem_out_dec = 6'b111111; 12'd3429 : mem_out_dec = 6'b111111; 12'd3430 : mem_out_dec = 6'b111111; 12'd3431 : mem_out_dec = 6'b111111; 12'd3432 : mem_out_dec = 6'b111111; 12'd3433 : mem_out_dec = 6'b111111; 12'd3434 : mem_out_dec = 6'b111111; 12'd3435 : mem_out_dec = 6'b111111; 12'd3436 : mem_out_dec = 6'b111111; 12'd3437 : mem_out_dec = 6'b111111; 12'd3438 : mem_out_dec = 6'b111111; 12'd3439 : mem_out_dec = 6'b111111; 12'd3440 : mem_out_dec = 6'b111111; 12'd3441 : mem_out_dec = 6'b111111; 12'd3442 : mem_out_dec = 6'b111111; 12'd3443 : mem_out_dec = 6'b111111; 12'd3444 : mem_out_dec = 6'b111111; 12'd3445 : mem_out_dec = 6'b111111; 12'd3446 : mem_out_dec = 6'b111111; 12'd3447 : mem_out_dec = 6'b111111; 12'd3448 : mem_out_dec = 6'b111111; 12'd3449 : mem_out_dec = 6'b111111; 12'd3450 : mem_out_dec = 6'b111111; 12'd3451 : mem_out_dec = 6'b000100; 12'd3452 : mem_out_dec = 6'b000101; 12'd3453 : mem_out_dec = 6'b000110; 12'd3454 : mem_out_dec = 6'b000111; 12'd3455 : mem_out_dec = 6'b001000; 12'd3456 : mem_out_dec = 6'b111111; 12'd3457 : mem_out_dec = 6'b111111; 12'd3458 : mem_out_dec = 6'b111111; 12'd3459 : mem_out_dec = 6'b111111; 12'd3460 : mem_out_dec = 6'b111111; 12'd3461 : mem_out_dec = 6'b111111; 12'd3462 : mem_out_dec = 6'b111111; 12'd3463 : mem_out_dec = 6'b111111; 12'd3464 : mem_out_dec = 6'b111111; 12'd3465 : mem_out_dec = 6'b111111; 12'd3466 : mem_out_dec = 6'b111111; 12'd3467 : mem_out_dec = 6'b111111; 12'd3468 : mem_out_dec = 6'b111111; 12'd3469 : mem_out_dec = 6'b111111; 12'd3470 : mem_out_dec = 6'b111111; 12'd3471 : mem_out_dec = 6'b111111; 12'd3472 : mem_out_dec = 6'b111111; 12'd3473 : mem_out_dec = 6'b111111; 12'd3474 : mem_out_dec = 6'b111111; 12'd3475 : mem_out_dec = 6'b111111; 12'd3476 : mem_out_dec = 6'b111111; 12'd3477 : mem_out_dec = 6'b111111; 12'd3478 : mem_out_dec = 6'b111111; 12'd3479 : mem_out_dec = 6'b111111; 12'd3480 : mem_out_dec = 6'b111111; 12'd3481 : mem_out_dec = 6'b111111; 12'd3482 : mem_out_dec = 6'b111111; 12'd3483 : mem_out_dec = 6'b111111; 12'd3484 : mem_out_dec = 6'b111111; 12'd3485 : mem_out_dec = 6'b111111; 12'd3486 : mem_out_dec = 6'b111111; 12'd3487 : mem_out_dec = 6'b111111; 12'd3488 : mem_out_dec = 6'b111111; 12'd3489 : mem_out_dec = 6'b111111; 12'd3490 : mem_out_dec = 6'b111111; 12'd3491 : mem_out_dec = 6'b111111; 12'd3492 : mem_out_dec = 6'b111111; 12'd3493 : mem_out_dec = 6'b111111; 12'd3494 : mem_out_dec = 6'b111111; 12'd3495 : mem_out_dec = 6'b111111; 12'd3496 : mem_out_dec = 6'b111111; 12'd3497 : mem_out_dec = 6'b111111; 12'd3498 : mem_out_dec = 6'b111111; 12'd3499 : mem_out_dec = 6'b111111; 12'd3500 : mem_out_dec = 6'b111111; 12'd3501 : mem_out_dec = 6'b111111; 12'd3502 : mem_out_dec = 6'b111111; 12'd3503 : mem_out_dec = 6'b111111; 12'd3504 : mem_out_dec = 6'b111111; 12'd3505 : mem_out_dec = 6'b111111; 12'd3506 : mem_out_dec = 6'b111111; 12'd3507 : mem_out_dec = 6'b111111; 12'd3508 : mem_out_dec = 6'b111111; 12'd3509 : mem_out_dec = 6'b111111; 12'd3510 : mem_out_dec = 6'b111111; 12'd3511 : mem_out_dec = 6'b111111; 12'd3512 : mem_out_dec = 6'b111111; 12'd3513 : mem_out_dec = 6'b111111; 12'd3514 : mem_out_dec = 6'b111111; 12'd3515 : mem_out_dec = 6'b111111; 12'd3516 : mem_out_dec = 6'b000101; 12'd3517 : mem_out_dec = 6'b000110; 12'd3518 : mem_out_dec = 6'b000110; 12'd3519 : mem_out_dec = 6'b000111; 12'd3520 : mem_out_dec = 6'b111111; 12'd3521 : mem_out_dec = 6'b111111; 12'd3522 : mem_out_dec = 6'b111111; 12'd3523 : mem_out_dec = 6'b111111; 12'd3524 : mem_out_dec = 6'b111111; 12'd3525 : mem_out_dec = 6'b111111; 12'd3526 : mem_out_dec = 6'b111111; 12'd3527 : mem_out_dec = 6'b111111; 12'd3528 : mem_out_dec = 6'b111111; 12'd3529 : mem_out_dec = 6'b111111; 12'd3530 : mem_out_dec = 6'b111111; 12'd3531 : mem_out_dec = 6'b111111; 12'd3532 : mem_out_dec = 6'b111111; 12'd3533 : mem_out_dec = 6'b111111; 12'd3534 : mem_out_dec = 6'b111111; 12'd3535 : mem_out_dec = 6'b111111; 12'd3536 : mem_out_dec = 6'b111111; 12'd3537 : mem_out_dec = 6'b111111; 12'd3538 : mem_out_dec = 6'b111111; 12'd3539 : mem_out_dec = 6'b111111; 12'd3540 : mem_out_dec = 6'b111111; 12'd3541 : mem_out_dec = 6'b111111; 12'd3542 : mem_out_dec = 6'b111111; 12'd3543 : mem_out_dec = 6'b111111; 12'd3544 : mem_out_dec = 6'b111111; 12'd3545 : mem_out_dec = 6'b111111; 12'd3546 : mem_out_dec = 6'b111111; 12'd3547 : mem_out_dec = 6'b111111; 12'd3548 : mem_out_dec = 6'b111111; 12'd3549 : mem_out_dec = 6'b111111; 12'd3550 : mem_out_dec = 6'b111111; 12'd3551 : mem_out_dec = 6'b111111; 12'd3552 : mem_out_dec = 6'b111111; 12'd3553 : mem_out_dec = 6'b111111; 12'd3554 : mem_out_dec = 6'b111111; 12'd3555 : mem_out_dec = 6'b111111; 12'd3556 : mem_out_dec = 6'b111111; 12'd3557 : mem_out_dec = 6'b111111; 12'd3558 : mem_out_dec = 6'b111111; 12'd3559 : mem_out_dec = 6'b111111; 12'd3560 : mem_out_dec = 6'b111111; 12'd3561 : mem_out_dec = 6'b111111; 12'd3562 : mem_out_dec = 6'b111111; 12'd3563 : mem_out_dec = 6'b111111; 12'd3564 : mem_out_dec = 6'b111111; 12'd3565 : mem_out_dec = 6'b111111; 12'd3566 : mem_out_dec = 6'b111111; 12'd3567 : mem_out_dec = 6'b111111; 12'd3568 : mem_out_dec = 6'b111111; 12'd3569 : mem_out_dec = 6'b111111; 12'd3570 : mem_out_dec = 6'b111111; 12'd3571 : mem_out_dec = 6'b111111; 12'd3572 : mem_out_dec = 6'b111111; 12'd3573 : mem_out_dec = 6'b111111; 12'd3574 : mem_out_dec = 6'b111111; 12'd3575 : mem_out_dec = 6'b111111; 12'd3576 : mem_out_dec = 6'b111111; 12'd3577 : mem_out_dec = 6'b111111; 12'd3578 : mem_out_dec = 6'b111111; 12'd3579 : mem_out_dec = 6'b111111; 12'd3580 : mem_out_dec = 6'b111111; 12'd3581 : mem_out_dec = 6'b000101; 12'd3582 : mem_out_dec = 6'b000110; 12'd3583 : mem_out_dec = 6'b000110; 12'd3584 : mem_out_dec = 6'b111111; 12'd3585 : mem_out_dec = 6'b111111; 12'd3586 : mem_out_dec = 6'b111111; 12'd3587 : mem_out_dec = 6'b111111; 12'd3588 : mem_out_dec = 6'b111111; 12'd3589 : mem_out_dec = 6'b111111; 12'd3590 : mem_out_dec = 6'b111111; 12'd3591 : mem_out_dec = 6'b111111; 12'd3592 : mem_out_dec = 6'b111111; 12'd3593 : mem_out_dec = 6'b111111; 12'd3594 : mem_out_dec = 6'b111111; 12'd3595 : mem_out_dec = 6'b111111; 12'd3596 : mem_out_dec = 6'b111111; 12'd3597 : mem_out_dec = 6'b111111; 12'd3598 : mem_out_dec = 6'b111111; 12'd3599 : mem_out_dec = 6'b111111; 12'd3600 : mem_out_dec = 6'b111111; 12'd3601 : mem_out_dec = 6'b111111; 12'd3602 : mem_out_dec = 6'b111111; 12'd3603 : mem_out_dec = 6'b111111; 12'd3604 : mem_out_dec = 6'b111111; 12'd3605 : mem_out_dec = 6'b111111; 12'd3606 : mem_out_dec = 6'b111111; 12'd3607 : mem_out_dec = 6'b111111; 12'd3608 : mem_out_dec = 6'b111111; 12'd3609 : mem_out_dec = 6'b111111; 12'd3610 : mem_out_dec = 6'b111111; 12'd3611 : mem_out_dec = 6'b111111; 12'd3612 : mem_out_dec = 6'b111111; 12'd3613 : mem_out_dec = 6'b111111; 12'd3614 : mem_out_dec = 6'b111111; 12'd3615 : mem_out_dec = 6'b111111; 12'd3616 : mem_out_dec = 6'b111111; 12'd3617 : mem_out_dec = 6'b111111; 12'd3618 : mem_out_dec = 6'b111111; 12'd3619 : mem_out_dec = 6'b111111; 12'd3620 : mem_out_dec = 6'b111111; 12'd3621 : mem_out_dec = 6'b111111; 12'd3622 : mem_out_dec = 6'b111111; 12'd3623 : mem_out_dec = 6'b111111; 12'd3624 : mem_out_dec = 6'b111111; 12'd3625 : mem_out_dec = 6'b111111; 12'd3626 : mem_out_dec = 6'b111111; 12'd3627 : mem_out_dec = 6'b111111; 12'd3628 : mem_out_dec = 6'b111111; 12'd3629 : mem_out_dec = 6'b111111; 12'd3630 : mem_out_dec = 6'b111111; 12'd3631 : mem_out_dec = 6'b111111; 12'd3632 : mem_out_dec = 6'b111111; 12'd3633 : mem_out_dec = 6'b111111; 12'd3634 : mem_out_dec = 6'b111111; 12'd3635 : mem_out_dec = 6'b111111; 12'd3636 : mem_out_dec = 6'b111111; 12'd3637 : mem_out_dec = 6'b111111; 12'd3638 : mem_out_dec = 6'b111111; 12'd3639 : mem_out_dec = 6'b111111; 12'd3640 : mem_out_dec = 6'b111111; 12'd3641 : mem_out_dec = 6'b111111; 12'd3642 : mem_out_dec = 6'b111111; 12'd3643 : mem_out_dec = 6'b111111; 12'd3644 : mem_out_dec = 6'b111111; 12'd3645 : mem_out_dec = 6'b111111; 12'd3646 : mem_out_dec = 6'b000100; 12'd3647 : mem_out_dec = 6'b000101; 12'd3648 : mem_out_dec = 6'b111111; 12'd3649 : mem_out_dec = 6'b111111; 12'd3650 : mem_out_dec = 6'b111111; 12'd3651 : mem_out_dec = 6'b111111; 12'd3652 : mem_out_dec = 6'b111111; 12'd3653 : mem_out_dec = 6'b111111; 12'd3654 : mem_out_dec = 6'b111111; 12'd3655 : mem_out_dec = 6'b111111; 12'd3656 : mem_out_dec = 6'b111111; 12'd3657 : mem_out_dec = 6'b111111; 12'd3658 : mem_out_dec = 6'b111111; 12'd3659 : mem_out_dec = 6'b111111; 12'd3660 : mem_out_dec = 6'b111111; 12'd3661 : mem_out_dec = 6'b111111; 12'd3662 : mem_out_dec = 6'b111111; 12'd3663 : mem_out_dec = 6'b111111; 12'd3664 : mem_out_dec = 6'b111111; 12'd3665 : mem_out_dec = 6'b111111; 12'd3666 : mem_out_dec = 6'b111111; 12'd3667 : mem_out_dec = 6'b111111; 12'd3668 : mem_out_dec = 6'b111111; 12'd3669 : mem_out_dec = 6'b111111; 12'd3670 : mem_out_dec = 6'b111111; 12'd3671 : mem_out_dec = 6'b111111; 12'd3672 : mem_out_dec = 6'b111111; 12'd3673 : mem_out_dec = 6'b111111; 12'd3674 : mem_out_dec = 6'b111111; 12'd3675 : mem_out_dec = 6'b111111; 12'd3676 : mem_out_dec = 6'b111111; 12'd3677 : mem_out_dec = 6'b111111; 12'd3678 : mem_out_dec = 6'b111111; 12'd3679 : mem_out_dec = 6'b111111; 12'd3680 : mem_out_dec = 6'b111111; 12'd3681 : mem_out_dec = 6'b111111; 12'd3682 : mem_out_dec = 6'b111111; 12'd3683 : mem_out_dec = 6'b111111; 12'd3684 : mem_out_dec = 6'b111111; 12'd3685 : mem_out_dec = 6'b111111; 12'd3686 : mem_out_dec = 6'b111111; 12'd3687 : mem_out_dec = 6'b111111; 12'd3688 : mem_out_dec = 6'b111111; 12'd3689 : mem_out_dec = 6'b111111; 12'd3690 : mem_out_dec = 6'b111111; 12'd3691 : mem_out_dec = 6'b111111; 12'd3692 : mem_out_dec = 6'b111111; 12'd3693 : mem_out_dec = 6'b111111; 12'd3694 : mem_out_dec = 6'b111111; 12'd3695 : mem_out_dec = 6'b111111; 12'd3696 : mem_out_dec = 6'b111111; 12'd3697 : mem_out_dec = 6'b111111; 12'd3698 : mem_out_dec = 6'b111111; 12'd3699 : mem_out_dec = 6'b111111; 12'd3700 : mem_out_dec = 6'b111111; 12'd3701 : mem_out_dec = 6'b111111; 12'd3702 : mem_out_dec = 6'b111111; 12'd3703 : mem_out_dec = 6'b111111; 12'd3704 : mem_out_dec = 6'b111111; 12'd3705 : mem_out_dec = 6'b111111; 12'd3706 : mem_out_dec = 6'b111111; 12'd3707 : mem_out_dec = 6'b111111; 12'd3708 : mem_out_dec = 6'b111111; 12'd3709 : mem_out_dec = 6'b111111; 12'd3710 : mem_out_dec = 6'b111111; 12'd3711 : mem_out_dec = 6'b000100; 12'd3712 : mem_out_dec = 6'b111111; 12'd3713 : mem_out_dec = 6'b111111; 12'd3714 : mem_out_dec = 6'b111111; 12'd3715 : mem_out_dec = 6'b111111; 12'd3716 : mem_out_dec = 6'b111111; 12'd3717 : mem_out_dec = 6'b111111; 12'd3718 : mem_out_dec = 6'b111111; 12'd3719 : mem_out_dec = 6'b111111; 12'd3720 : mem_out_dec = 6'b111111; 12'd3721 : mem_out_dec = 6'b111111; 12'd3722 : mem_out_dec = 6'b111111; 12'd3723 : mem_out_dec = 6'b111111; 12'd3724 : mem_out_dec = 6'b111111; 12'd3725 : mem_out_dec = 6'b111111; 12'd3726 : mem_out_dec = 6'b111111; 12'd3727 : mem_out_dec = 6'b111111; 12'd3728 : mem_out_dec = 6'b111111; 12'd3729 : mem_out_dec = 6'b111111; 12'd3730 : mem_out_dec = 6'b111111; 12'd3731 : mem_out_dec = 6'b111111; 12'd3732 : mem_out_dec = 6'b111111; 12'd3733 : mem_out_dec = 6'b111111; 12'd3734 : mem_out_dec = 6'b111111; 12'd3735 : mem_out_dec = 6'b111111; 12'd3736 : mem_out_dec = 6'b111111; 12'd3737 : mem_out_dec = 6'b111111; 12'd3738 : mem_out_dec = 6'b111111; 12'd3739 : mem_out_dec = 6'b111111; 12'd3740 : mem_out_dec = 6'b111111; 12'd3741 : mem_out_dec = 6'b111111; 12'd3742 : mem_out_dec = 6'b111111; 12'd3743 : mem_out_dec = 6'b111111; 12'd3744 : mem_out_dec = 6'b111111; 12'd3745 : mem_out_dec = 6'b111111; 12'd3746 : mem_out_dec = 6'b111111; 12'd3747 : mem_out_dec = 6'b111111; 12'd3748 : mem_out_dec = 6'b111111; 12'd3749 : mem_out_dec = 6'b111111; 12'd3750 : mem_out_dec = 6'b111111; 12'd3751 : mem_out_dec = 6'b111111; 12'd3752 : mem_out_dec = 6'b111111; 12'd3753 : mem_out_dec = 6'b111111; 12'd3754 : mem_out_dec = 6'b111111; 12'd3755 : mem_out_dec = 6'b111111; 12'd3756 : mem_out_dec = 6'b111111; 12'd3757 : mem_out_dec = 6'b111111; 12'd3758 : mem_out_dec = 6'b111111; 12'd3759 : mem_out_dec = 6'b111111; 12'd3760 : mem_out_dec = 6'b111111; 12'd3761 : mem_out_dec = 6'b111111; 12'd3762 : mem_out_dec = 6'b111111; 12'd3763 : mem_out_dec = 6'b111111; 12'd3764 : mem_out_dec = 6'b111111; 12'd3765 : mem_out_dec = 6'b111111; 12'd3766 : mem_out_dec = 6'b111111; 12'd3767 : mem_out_dec = 6'b111111; 12'd3768 : mem_out_dec = 6'b111111; 12'd3769 : mem_out_dec = 6'b111111; 12'd3770 : mem_out_dec = 6'b111111; 12'd3771 : mem_out_dec = 6'b111111; 12'd3772 : mem_out_dec = 6'b111111; 12'd3773 : mem_out_dec = 6'b111111; 12'd3774 : mem_out_dec = 6'b111111; 12'd3775 : mem_out_dec = 6'b111111; 12'd3776 : mem_out_dec = 6'b111111; 12'd3777 : mem_out_dec = 6'b111111; 12'd3778 : mem_out_dec = 6'b111111; 12'd3779 : mem_out_dec = 6'b111111; 12'd3780 : mem_out_dec = 6'b111111; 12'd3781 : mem_out_dec = 6'b111111; 12'd3782 : mem_out_dec = 6'b111111; 12'd3783 : mem_out_dec = 6'b111111; 12'd3784 : mem_out_dec = 6'b111111; 12'd3785 : mem_out_dec = 6'b111111; 12'd3786 : mem_out_dec = 6'b111111; 12'd3787 : mem_out_dec = 6'b111111; 12'd3788 : mem_out_dec = 6'b111111; 12'd3789 : mem_out_dec = 6'b111111; 12'd3790 : mem_out_dec = 6'b111111; 12'd3791 : mem_out_dec = 6'b111111; 12'd3792 : mem_out_dec = 6'b111111; 12'd3793 : mem_out_dec = 6'b111111; 12'd3794 : mem_out_dec = 6'b111111; 12'd3795 : mem_out_dec = 6'b111111; 12'd3796 : mem_out_dec = 6'b111111; 12'd3797 : mem_out_dec = 6'b111111; 12'd3798 : mem_out_dec = 6'b111111; 12'd3799 : mem_out_dec = 6'b111111; 12'd3800 : mem_out_dec = 6'b111111; 12'd3801 : mem_out_dec = 6'b111111; 12'd3802 : mem_out_dec = 6'b111111; 12'd3803 : mem_out_dec = 6'b111111; 12'd3804 : mem_out_dec = 6'b111111; 12'd3805 : mem_out_dec = 6'b111111; 12'd3806 : mem_out_dec = 6'b111111; 12'd3807 : mem_out_dec = 6'b111111; 12'd3808 : mem_out_dec = 6'b111111; 12'd3809 : mem_out_dec = 6'b111111; 12'd3810 : mem_out_dec = 6'b111111; 12'd3811 : mem_out_dec = 6'b111111; 12'd3812 : mem_out_dec = 6'b111111; 12'd3813 : mem_out_dec = 6'b111111; 12'd3814 : mem_out_dec = 6'b111111; 12'd3815 : mem_out_dec = 6'b111111; 12'd3816 : mem_out_dec = 6'b111111; 12'd3817 : mem_out_dec = 6'b111111; 12'd3818 : mem_out_dec = 6'b111111; 12'd3819 : mem_out_dec = 6'b111111; 12'd3820 : mem_out_dec = 6'b111111; 12'd3821 : mem_out_dec = 6'b111111; 12'd3822 : mem_out_dec = 6'b111111; 12'd3823 : mem_out_dec = 6'b111111; 12'd3824 : mem_out_dec = 6'b111111; 12'd3825 : mem_out_dec = 6'b111111; 12'd3826 : mem_out_dec = 6'b111111; 12'd3827 : mem_out_dec = 6'b111111; 12'd3828 : mem_out_dec = 6'b111111; 12'd3829 : mem_out_dec = 6'b111111; 12'd3830 : mem_out_dec = 6'b111111; 12'd3831 : mem_out_dec = 6'b111111; 12'd3832 : mem_out_dec = 6'b111111; 12'd3833 : mem_out_dec = 6'b111111; 12'd3834 : mem_out_dec = 6'b111111; 12'd3835 : mem_out_dec = 6'b111111; 12'd3836 : mem_out_dec = 6'b111111; 12'd3837 : mem_out_dec = 6'b111111; 12'd3838 : mem_out_dec = 6'b111111; 12'd3839 : mem_out_dec = 6'b111111; 12'd3840 : mem_out_dec = 6'b111111; 12'd3841 : mem_out_dec = 6'b111111; 12'd3842 : mem_out_dec = 6'b111111; 12'd3843 : mem_out_dec = 6'b111111; 12'd3844 : mem_out_dec = 6'b111111; 12'd3845 : mem_out_dec = 6'b111111; 12'd3846 : mem_out_dec = 6'b111111; 12'd3847 : mem_out_dec = 6'b111111; 12'd3848 : mem_out_dec = 6'b111111; 12'd3849 : mem_out_dec = 6'b111111; 12'd3850 : mem_out_dec = 6'b111111; 12'd3851 : mem_out_dec = 6'b111111; 12'd3852 : mem_out_dec = 6'b111111; 12'd3853 : mem_out_dec = 6'b111111; 12'd3854 : mem_out_dec = 6'b111111; 12'd3855 : mem_out_dec = 6'b111111; 12'd3856 : mem_out_dec = 6'b111111; 12'd3857 : mem_out_dec = 6'b111111; 12'd3858 : mem_out_dec = 6'b111111; 12'd3859 : mem_out_dec = 6'b111111; 12'd3860 : mem_out_dec = 6'b111111; 12'd3861 : mem_out_dec = 6'b111111; 12'd3862 : mem_out_dec = 6'b111111; 12'd3863 : mem_out_dec = 6'b111111; 12'd3864 : mem_out_dec = 6'b111111; 12'd3865 : mem_out_dec = 6'b111111; 12'd3866 : mem_out_dec = 6'b111111; 12'd3867 : mem_out_dec = 6'b111111; 12'd3868 : mem_out_dec = 6'b111111; 12'd3869 : mem_out_dec = 6'b111111; 12'd3870 : mem_out_dec = 6'b111111; 12'd3871 : mem_out_dec = 6'b111111; 12'd3872 : mem_out_dec = 6'b111111; 12'd3873 : mem_out_dec = 6'b111111; 12'd3874 : mem_out_dec = 6'b111111; 12'd3875 : mem_out_dec = 6'b111111; 12'd3876 : mem_out_dec = 6'b111111; 12'd3877 : mem_out_dec = 6'b111111; 12'd3878 : mem_out_dec = 6'b111111; 12'd3879 : mem_out_dec = 6'b111111; 12'd3880 : mem_out_dec = 6'b111111; 12'd3881 : mem_out_dec = 6'b111111; 12'd3882 : mem_out_dec = 6'b111111; 12'd3883 : mem_out_dec = 6'b111111; 12'd3884 : mem_out_dec = 6'b111111; 12'd3885 : mem_out_dec = 6'b111111; 12'd3886 : mem_out_dec = 6'b111111; 12'd3887 : mem_out_dec = 6'b111111; 12'd3888 : mem_out_dec = 6'b111111; 12'd3889 : mem_out_dec = 6'b111111; 12'd3890 : mem_out_dec = 6'b111111; 12'd3891 : mem_out_dec = 6'b111111; 12'd3892 : mem_out_dec = 6'b111111; 12'd3893 : mem_out_dec = 6'b111111; 12'd3894 : mem_out_dec = 6'b111111; 12'd3895 : mem_out_dec = 6'b111111; 12'd3896 : mem_out_dec = 6'b111111; 12'd3897 : mem_out_dec = 6'b111111; 12'd3898 : mem_out_dec = 6'b111111; 12'd3899 : mem_out_dec = 6'b111111; 12'd3900 : mem_out_dec = 6'b111111; 12'd3901 : mem_out_dec = 6'b111111; 12'd3902 : mem_out_dec = 6'b111111; 12'd3903 : mem_out_dec = 6'b111111; 12'd3904 : mem_out_dec = 6'b111111; 12'd3905 : mem_out_dec = 6'b111111; 12'd3906 : mem_out_dec = 6'b111111; 12'd3907 : mem_out_dec = 6'b111111; 12'd3908 : mem_out_dec = 6'b111111; 12'd3909 : mem_out_dec = 6'b111111; 12'd3910 : mem_out_dec = 6'b111111; 12'd3911 : mem_out_dec = 6'b111111; 12'd3912 : mem_out_dec = 6'b111111; 12'd3913 : mem_out_dec = 6'b111111; 12'd3914 : mem_out_dec = 6'b111111; 12'd3915 : mem_out_dec = 6'b111111; 12'd3916 : mem_out_dec = 6'b111111; 12'd3917 : mem_out_dec = 6'b111111; 12'd3918 : mem_out_dec = 6'b111111; 12'd3919 : mem_out_dec = 6'b111111; 12'd3920 : mem_out_dec = 6'b111111; 12'd3921 : mem_out_dec = 6'b111111; 12'd3922 : mem_out_dec = 6'b111111; 12'd3923 : mem_out_dec = 6'b111111; 12'd3924 : mem_out_dec = 6'b111111; 12'd3925 : mem_out_dec = 6'b111111; 12'd3926 : mem_out_dec = 6'b111111; 12'd3927 : mem_out_dec = 6'b111111; 12'd3928 : mem_out_dec = 6'b111111; 12'd3929 : mem_out_dec = 6'b111111; 12'd3930 : mem_out_dec = 6'b111111; 12'd3931 : mem_out_dec = 6'b111111; 12'd3932 : mem_out_dec = 6'b111111; 12'd3933 : mem_out_dec = 6'b111111; 12'd3934 : mem_out_dec = 6'b111111; 12'd3935 : mem_out_dec = 6'b111111; 12'd3936 : mem_out_dec = 6'b111111; 12'd3937 : mem_out_dec = 6'b111111; 12'd3938 : mem_out_dec = 6'b111111; 12'd3939 : mem_out_dec = 6'b111111; 12'd3940 : mem_out_dec = 6'b111111; 12'd3941 : mem_out_dec = 6'b111111; 12'd3942 : mem_out_dec = 6'b111111; 12'd3943 : mem_out_dec = 6'b111111; 12'd3944 : mem_out_dec = 6'b111111; 12'd3945 : mem_out_dec = 6'b111111; 12'd3946 : mem_out_dec = 6'b111111; 12'd3947 : mem_out_dec = 6'b111111; 12'd3948 : mem_out_dec = 6'b111111; 12'd3949 : mem_out_dec = 6'b111111; 12'd3950 : mem_out_dec = 6'b111111; 12'd3951 : mem_out_dec = 6'b111111; 12'd3952 : mem_out_dec = 6'b111111; 12'd3953 : mem_out_dec = 6'b111111; 12'd3954 : mem_out_dec = 6'b111111; 12'd3955 : mem_out_dec = 6'b111111; 12'd3956 : mem_out_dec = 6'b111111; 12'd3957 : mem_out_dec = 6'b111111; 12'd3958 : mem_out_dec = 6'b111111; 12'd3959 : mem_out_dec = 6'b111111; 12'd3960 : mem_out_dec = 6'b111111; 12'd3961 : mem_out_dec = 6'b111111; 12'd3962 : mem_out_dec = 6'b111111; 12'd3963 : mem_out_dec = 6'b111111; 12'd3964 : mem_out_dec = 6'b111111; 12'd3965 : mem_out_dec = 6'b111111; 12'd3966 : mem_out_dec = 6'b111111; 12'd3967 : mem_out_dec = 6'b111111; 12'd3968 : mem_out_dec = 6'b111111; 12'd3969 : mem_out_dec = 6'b111111; 12'd3970 : mem_out_dec = 6'b111111; 12'd3971 : mem_out_dec = 6'b111111; 12'd3972 : mem_out_dec = 6'b111111; 12'd3973 : mem_out_dec = 6'b111111; 12'd3974 : mem_out_dec = 6'b111111; 12'd3975 : mem_out_dec = 6'b111111; 12'd3976 : mem_out_dec = 6'b111111; 12'd3977 : mem_out_dec = 6'b111111; 12'd3978 : mem_out_dec = 6'b111111; 12'd3979 : mem_out_dec = 6'b111111; 12'd3980 : mem_out_dec = 6'b111111; 12'd3981 : mem_out_dec = 6'b111111; 12'd3982 : mem_out_dec = 6'b111111; 12'd3983 : mem_out_dec = 6'b111111; 12'd3984 : mem_out_dec = 6'b111111; 12'd3985 : mem_out_dec = 6'b111111; 12'd3986 : mem_out_dec = 6'b111111; 12'd3987 : mem_out_dec = 6'b111111; 12'd3988 : mem_out_dec = 6'b111111; 12'd3989 : mem_out_dec = 6'b111111; 12'd3990 : mem_out_dec = 6'b111111; 12'd3991 : mem_out_dec = 6'b111111; 12'd3992 : mem_out_dec = 6'b111111; 12'd3993 : mem_out_dec = 6'b111111; 12'd3994 : mem_out_dec = 6'b111111; 12'd3995 : mem_out_dec = 6'b111111; 12'd3996 : mem_out_dec = 6'b111111; 12'd3997 : mem_out_dec = 6'b111111; 12'd3998 : mem_out_dec = 6'b111111; 12'd3999 : mem_out_dec = 6'b111111; 12'd4000 : mem_out_dec = 6'b111111; 12'd4001 : mem_out_dec = 6'b111111; 12'd4002 : mem_out_dec = 6'b111111; 12'd4003 : mem_out_dec = 6'b111111; 12'd4004 : mem_out_dec = 6'b111111; 12'd4005 : mem_out_dec = 6'b111111; 12'd4006 : mem_out_dec = 6'b111111; 12'd4007 : mem_out_dec = 6'b111111; 12'd4008 : mem_out_dec = 6'b111111; 12'd4009 : mem_out_dec = 6'b111111; 12'd4010 : mem_out_dec = 6'b111111; 12'd4011 : mem_out_dec = 6'b111111; 12'd4012 : mem_out_dec = 6'b111111; 12'd4013 : mem_out_dec = 6'b111111; 12'd4014 : mem_out_dec = 6'b111111; 12'd4015 : mem_out_dec = 6'b111111; 12'd4016 : mem_out_dec = 6'b111111; 12'd4017 : mem_out_dec = 6'b111111; 12'd4018 : mem_out_dec = 6'b111111; 12'd4019 : mem_out_dec = 6'b111111; 12'd4020 : mem_out_dec = 6'b111111; 12'd4021 : mem_out_dec = 6'b111111; 12'd4022 : mem_out_dec = 6'b111111; 12'd4023 : mem_out_dec = 6'b111111; 12'd4024 : mem_out_dec = 6'b111111; 12'd4025 : mem_out_dec = 6'b111111; 12'd4026 : mem_out_dec = 6'b111111; 12'd4027 : mem_out_dec = 6'b111111; 12'd4028 : mem_out_dec = 6'b111111; 12'd4029 : mem_out_dec = 6'b111111; 12'd4030 : mem_out_dec = 6'b111111; 12'd4031 : mem_out_dec = 6'b111111; 12'd4032 : mem_out_dec = 6'b111111; 12'd4033 : mem_out_dec = 6'b111111; 12'd4034 : mem_out_dec = 6'b111111; 12'd4035 : mem_out_dec = 6'b111111; 12'd4036 : mem_out_dec = 6'b111111; 12'd4037 : mem_out_dec = 6'b111111; 12'd4038 : mem_out_dec = 6'b111111; 12'd4039 : mem_out_dec = 6'b111111; 12'd4040 : mem_out_dec = 6'b111111; 12'd4041 : mem_out_dec = 6'b111111; 12'd4042 : mem_out_dec = 6'b111111; 12'd4043 : mem_out_dec = 6'b111111; 12'd4044 : mem_out_dec = 6'b111111; 12'd4045 : mem_out_dec = 6'b111111; 12'd4046 : mem_out_dec = 6'b111111; 12'd4047 : mem_out_dec = 6'b111111; 12'd4048 : mem_out_dec = 6'b111111; 12'd4049 : mem_out_dec = 6'b111111; 12'd4050 : mem_out_dec = 6'b111111; 12'd4051 : mem_out_dec = 6'b111111; 12'd4052 : mem_out_dec = 6'b111111; 12'd4053 : mem_out_dec = 6'b111111; 12'd4054 : mem_out_dec = 6'b111111; 12'd4055 : mem_out_dec = 6'b111111; 12'd4056 : mem_out_dec = 6'b111111; 12'd4057 : mem_out_dec = 6'b111111; 12'd4058 : mem_out_dec = 6'b111111; 12'd4059 : mem_out_dec = 6'b111111; 12'd4060 : mem_out_dec = 6'b111111; 12'd4061 : mem_out_dec = 6'b111111; 12'd4062 : mem_out_dec = 6'b111111; 12'd4063 : mem_out_dec = 6'b111111; 12'd4064 : mem_out_dec = 6'b111111; 12'd4065 : mem_out_dec = 6'b111111; 12'd4066 : mem_out_dec = 6'b111111; 12'd4067 : mem_out_dec = 6'b111111; 12'd4068 : mem_out_dec = 6'b111111; 12'd4069 : mem_out_dec = 6'b111111; 12'd4070 : mem_out_dec = 6'b111111; 12'd4071 : mem_out_dec = 6'b111111; 12'd4072 : mem_out_dec = 6'b111111; 12'd4073 : mem_out_dec = 6'b111111; 12'd4074 : mem_out_dec = 6'b111111; 12'd4075 : mem_out_dec = 6'b111111; 12'd4076 : mem_out_dec = 6'b111111; 12'd4077 : mem_out_dec = 6'b111111; 12'd4078 : mem_out_dec = 6'b111111; 12'd4079 : mem_out_dec = 6'b111111; 12'd4080 : mem_out_dec = 6'b111111; 12'd4081 : mem_out_dec = 6'b111111; 12'd4082 : mem_out_dec = 6'b111111; 12'd4083 : mem_out_dec = 6'b111111; 12'd4084 : mem_out_dec = 6'b111111; 12'd4085 : mem_out_dec = 6'b111111; 12'd4086 : mem_out_dec = 6'b111111; 12'd4087 : mem_out_dec = 6'b111111; 12'd4088 : mem_out_dec = 6'b111111; 12'd4089 : mem_out_dec = 6'b111111; 12'd4090 : mem_out_dec = 6'b111111; 12'd4091 : mem_out_dec = 6'b111111; 12'd4092 : mem_out_dec = 6'b111111; 12'd4093 : mem_out_dec = 6'b111111; 12'd4094 : mem_out_dec = 6'b111111; 12'd4095 : mem_out_dec = 6'b111111; endcase end always @ (posedge clk) begin dec_cnt <= #TCQ mem_out_dec; end endmodule

//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v2_3_poc_tap_base.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 15 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: All your taps are belong to us. // //In general, this block should be able to start up with a random initialization of //the various counters. But its probably easier, more normative and quicker time to solution //to just initialize to zero with rst. // // Following deassertion of reset, endlessly increments the MMCM delay with PSEN. For // each MMCM tap it samples the phase detector output a programmable number of times. // When the sampling count is achieved, PSEN is pulsed and sampling of the next MMCM // tap begins. // // Following a PSEN, sampling pauses for MMCM_SAMP_WAIT clocks. This is workaround // for a bug in the MMCM where its output may have noise for a period following // the PSEN. // // Samples are taken every other fabric clock. This is because the MMCM phase shift // clock operates at half the fabric clock. The reason for this is unknown. // // At the end of the sampling period, a filtering step is implemented. samps_solid_thresh // is the minumum number of samples that must be seen to declare a solid zero or one. If // neithr the one and zero samples cross this threshold, then the sampple is declared fuzz. // // A "run_polarity" bit is maintained. It is set appropriately whenever a solid sample // is observed. // // A "run" counter is maintained. If the current sample is fuzz, or opposite polarity // from a previous sample, then the run counter is reset. If the current sample is the // same polarity run_polarity, then the run counter is incremented. // // If a run_polarity reversal or fuzz is observed and the run counter is not zero // then the run_end strobe is pulsed. // //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_poc_tap_base # (parameter MMCM_SAMP_WAIT = 10, parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter TCQ = 100, parameter SAMPCNTRWIDTH = 8, parameter TAPCNTRWIDTH = 7, parameter TAPSPERKCLK = 112) (/*AUTOARG*/ // Outputs psincdec, psen, run, run_end, run_polarity, samps_hi_held, tap, // Inputs pd_out, clk, samples, samps_solid_thresh, psdone, rst, poc_sample_pd ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 input pd_out; input clk; input [SAMPCNTRWIDTH:0] samples, samps_solid_thresh; input psdone; input rst; localparam ONE = 1; localparam SAMP_WAIT_WIDTH = clogb2(MMCM_SAMP_WAIT); reg [SAMP_WAIT_WIDTH-1:0] samp_wait_ns, samp_wait_r; always @(posedge clk) samp_wait_r <= #TCQ samp_wait_ns; reg pd_out_r; always @(posedge clk) pd_out_r <= #TCQ pd_out; wire pd_out_sel = POC_USE_METASTABLE_SAMP == "TRUE" ? pd_out_r : pd_out; output psincdec; assign psincdec = 1'b1; output psen; reg psen_int; assign psen = psen_int; reg [TAPCNTRWIDTH-1:0] run_r; reg [TAPCNTRWIDTH-1:0] run_ns; always @(posedge clk) run_r <= #TCQ run_ns; output [TAPCNTRWIDTH-1:0] run; assign run = run_r; output run_end; reg run_end_int; assign run_end = run_end_int; reg run_polarity_r; reg run_polarity_ns; always @(posedge clk) run_polarity_r <= #TCQ run_polarity_ns; output run_polarity; assign run_polarity = run_polarity_r; reg [SAMPCNTRWIDTH-1:0] samp_cntr_r; reg [SAMPCNTRWIDTH-1:0] samp_cntr_ns; always @(posedge clk) samp_cntr_r <= #TCQ samp_cntr_ns; reg [SAMPCNTRWIDTH:0] samps_hi_r; reg [SAMPCNTRWIDTH:0] samps_hi_ns; always @(posedge clk) samps_hi_r <= #TCQ samps_hi_ns; reg [SAMPCNTRWIDTH:0] samps_hi_held_r; reg [SAMPCNTRWIDTH:0] samps_hi_held_ns; always @(posedge clk) samps_hi_held_r <= #TCQ samps_hi_held_ns; output [SAMPCNTRWIDTH:0] samps_hi_held; assign samps_hi_held = samps_hi_held_r; reg [TAPCNTRWIDTH-1:0] tap_ns, tap_r; always @(posedge clk) tap_r <= #TCQ tap_ns; output [TAPCNTRWIDTH-1:0] tap; assign tap = tap_r; localparam SMWIDTH = 2; reg [SMWIDTH-1:0] sm_ns; reg [SMWIDTH-1:0] sm_r; always @(posedge clk) sm_r <= #TCQ sm_ns; reg samps_zero_ns, samps_zero_r, samps_one_ns, samps_one_r; always @(posedge clk) samps_zero_r <= #TCQ samps_zero_ns; always @(posedge clk)samps_one_r <= #TCQ samps_one_ns; // Interesting corner case... what if both samps_zero and samps_one are // hi? Could happen for small sample counts and reasonable values of // PCT_SAMPS_SOLID. Doesn't affect samps_solid. run_polarity assignment // consistently breaks tie with samps_one_r. wire [SAMPCNTRWIDTH:0] samps_lo = samples + ONE[SAMPCNTRWIDTH:0] - samps_hi_r; always @(*) begin samps_zero_ns = samps_zero_r; samps_one_ns = samps_one_r; samps_zero_ns = samps_lo >= samps_solid_thresh; samps_one_ns = samps_hi_r >= samps_solid_thresh; end // always @ begin wire new_polarity = run_polarity_ns ^ run_polarity_r; input poc_sample_pd; always @(*) begin if (rst == 1'b1) begin // RESET next states psen_int = 1'b0; sm_ns = /*AUTOLINK("SAMPLE")*/2'd0; run_polarity_ns = 1'b0; run_ns = {TAPCNTRWIDTH{1'b0}}; run_end_int = 1'b0; samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}}; samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}}; tap_ns = {TAPCNTRWIDTH{1'b0}}; samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0]; samps_hi_held_ns = {SAMPCNTRWIDTH+1{1'b0}}; end else begin // Default next states; psen_int = 1'b0; sm_ns = sm_r; run_polarity_ns = run_polarity_r; run_ns = run_r; run_end_int = 1'b0; samp_cntr_ns = samp_cntr_r; samps_hi_ns = samps_hi_r; tap_ns = tap_r; samp_wait_ns = samp_wait_r; if (|samp_wait_r) samp_wait_ns = samp_wait_r - ONE[SAMP_WAIT_WIDTH-1:0]; samps_hi_held_ns = samps_hi_held_r; // State based actions and next states. case (sm_r) /*AL("SAMPLE")*/2'd0: begin if (~|samp_wait_r && poc_sample_pd | POC_USE_METASTABLE_SAMP == "TRUE") begin if (POC_USE_METASTABLE_SAMP == "TRUE") samp_wait_ns = ONE[SAMP_WAIT_WIDTH-1:0]; if ({1'b0, samp_cntr_r} == samples) sm_ns = /*AK("COMPUTE")*/2'd1; samps_hi_ns = samps_hi_r + {{SAMPCNTRWIDTH{1'b0}}, pd_out_sel}; samp_cntr_ns = samp_cntr_r + ONE[SAMPCNTRWIDTH-1:0]; end end /*AL("COMPUTE")*/2'd1:begin sm_ns = /*AK("PSEN")*/2'd2; end /*AL("PSEN")*/2'd2:begin sm_ns = /*AK("PSDONE_WAIT")*/2'd3; psen_int = 1'b1; samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}}; samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}}; samps_hi_held_ns = samps_hi_r; tap_ns = (tap_r < TAPSPERKCLK[TAPCNTRWIDTH-1:0] - ONE[TAPCNTRWIDTH-1:0]) ? tap_r + ONE[TAPCNTRWIDTH-1:0] : {TAPCNTRWIDTH{1'b0}}; if (run_polarity_r) begin if (samps_zero_r) run_polarity_ns = 1'b0; end else begin if (samps_one_r) run_polarity_ns = 1'b1; end if (new_polarity) begin run_ns ={TAPCNTRWIDTH{1'b0}}; run_end_int = 1'b1; end else run_ns = run_r + ONE[TAPCNTRWIDTH-1:0]; end /*AL("PSDONE_WAIT")*/2'd3:begin samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0] - ONE[SAMP_WAIT_WIDTH-1:0]; if (psdone) sm_ns = /*AK("SAMPLE")*/2'd0; end endcase // case (sm_r) end // else: !if(rst == 1'b1) end // always @ (*) endmodule // mig_7series_v2_3_poc_tap_base // Local Variables: // verilog-library-directories:(".") // verilog-library-extensions:(".v") // verilog-autolabel-prefix: "2'd" // End:

//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v2_3_poc_tap_base.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 15 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: All your taps are belong to us. // //In general, this block should be able to start up with a random initialization of //the various counters. But its probably easier, more normative and quicker time to solution //to just initialize to zero with rst. // // Following deassertion of reset, endlessly increments the MMCM delay with PSEN. For // each MMCM tap it samples the phase detector output a programmable number of times. // When the sampling count is achieved, PSEN is pulsed and sampling of the next MMCM // tap begins. // // Following a PSEN, sampling pauses for MMCM_SAMP_WAIT clocks. This is workaround // for a bug in the MMCM where its output may have noise for a period following // the PSEN. // // Samples are taken every other fabric clock. This is because the MMCM phase shift // clock operates at half the fabric clock. The reason for this is unknown. // // At the end of the sampling period, a filtering step is implemented. samps_solid_thresh // is the minumum number of samples that must be seen to declare a solid zero or one. If // neithr the one and zero samples cross this threshold, then the sampple is declared fuzz. // // A "run_polarity" bit is maintained. It is set appropriately whenever a solid sample // is observed. // // A "run" counter is maintained. If the current sample is fuzz, or opposite polarity // from a previous sample, then the run counter is reset. If the current sample is the // same polarity run_polarity, then the run counter is incremented. // // If a run_polarity reversal or fuzz is observed and the run counter is not zero // then the run_end strobe is pulsed. // //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_poc_tap_base # (parameter MMCM_SAMP_WAIT = 10, parameter POC_USE_METASTABLE_SAMP = "FALSE", parameter TCQ = 100, parameter SAMPCNTRWIDTH = 8, parameter TAPCNTRWIDTH = 7, parameter TAPSPERKCLK = 112) (/*AUTOARG*/ // Outputs psincdec, psen, run, run_end, run_polarity, samps_hi_held, tap, // Inputs pd_out, clk, samples, samps_solid_thresh, psdone, rst, poc_sample_pd ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 input pd_out; input clk; input [SAMPCNTRWIDTH:0] samples, samps_solid_thresh; input psdone; input rst; localparam ONE = 1; localparam SAMP_WAIT_WIDTH = clogb2(MMCM_SAMP_WAIT); reg [SAMP_WAIT_WIDTH-1:0] samp_wait_ns, samp_wait_r; always @(posedge clk) samp_wait_r <= #TCQ samp_wait_ns; reg pd_out_r; always @(posedge clk) pd_out_r <= #TCQ pd_out; wire pd_out_sel = POC_USE_METASTABLE_SAMP == "TRUE" ? pd_out_r : pd_out; output psincdec; assign psincdec = 1'b1; output psen; reg psen_int; assign psen = psen_int; reg [TAPCNTRWIDTH-1:0] run_r; reg [TAPCNTRWIDTH-1:0] run_ns; always @(posedge clk) run_r <= #TCQ run_ns; output [TAPCNTRWIDTH-1:0] run; assign run = run_r; output run_end; reg run_end_int; assign run_end = run_end_int; reg run_polarity_r; reg run_polarity_ns; always @(posedge clk) run_polarity_r <= #TCQ run_polarity_ns; output run_polarity; assign run_polarity = run_polarity_r; reg [SAMPCNTRWIDTH-1:0] samp_cntr_r; reg [SAMPCNTRWIDTH-1:0] samp_cntr_ns; always @(posedge clk) samp_cntr_r <= #TCQ samp_cntr_ns; reg [SAMPCNTRWIDTH:0] samps_hi_r; reg [SAMPCNTRWIDTH:0] samps_hi_ns; always @(posedge clk) samps_hi_r <= #TCQ samps_hi_ns; reg [SAMPCNTRWIDTH:0] samps_hi_held_r; reg [SAMPCNTRWIDTH:0] samps_hi_held_ns; always @(posedge clk) samps_hi_held_r <= #TCQ samps_hi_held_ns; output [SAMPCNTRWIDTH:0] samps_hi_held; assign samps_hi_held = samps_hi_held_r; reg [TAPCNTRWIDTH-1:0] tap_ns, tap_r; always @(posedge clk) tap_r <= #TCQ tap_ns; output [TAPCNTRWIDTH-1:0] tap; assign tap = tap_r; localparam SMWIDTH = 2; reg [SMWIDTH-1:0] sm_ns; reg [SMWIDTH-1:0] sm_r; always @(posedge clk) sm_r <= #TCQ sm_ns; reg samps_zero_ns, samps_zero_r, samps_one_ns, samps_one_r; always @(posedge clk) samps_zero_r <= #TCQ samps_zero_ns; always @(posedge clk)samps_one_r <= #TCQ samps_one_ns; // Interesting corner case... what if both samps_zero and samps_one are // hi? Could happen for small sample counts and reasonable values of // PCT_SAMPS_SOLID. Doesn't affect samps_solid. run_polarity assignment // consistently breaks tie with samps_one_r. wire [SAMPCNTRWIDTH:0] samps_lo = samples + ONE[SAMPCNTRWIDTH:0] - samps_hi_r; always @(*) begin samps_zero_ns = samps_zero_r; samps_one_ns = samps_one_r; samps_zero_ns = samps_lo >= samps_solid_thresh; samps_one_ns = samps_hi_r >= samps_solid_thresh; end // always @ begin wire new_polarity = run_polarity_ns ^ run_polarity_r; input poc_sample_pd; always @(*) begin if (rst == 1'b1) begin // RESET next states psen_int = 1'b0; sm_ns = /*AUTOLINK("SAMPLE")*/2'd0; run_polarity_ns = 1'b0; run_ns = {TAPCNTRWIDTH{1'b0}}; run_end_int = 1'b0; samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}}; samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}}; tap_ns = {TAPCNTRWIDTH{1'b0}}; samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0]; samps_hi_held_ns = {SAMPCNTRWIDTH+1{1'b0}}; end else begin // Default next states; psen_int = 1'b0; sm_ns = sm_r; run_polarity_ns = run_polarity_r; run_ns = run_r; run_end_int = 1'b0; samp_cntr_ns = samp_cntr_r; samps_hi_ns = samps_hi_r; tap_ns = tap_r; samp_wait_ns = samp_wait_r; if (|samp_wait_r) samp_wait_ns = samp_wait_r - ONE[SAMP_WAIT_WIDTH-1:0]; samps_hi_held_ns = samps_hi_held_r; // State based actions and next states. case (sm_r) /*AL("SAMPLE")*/2'd0: begin if (~|samp_wait_r && poc_sample_pd | POC_USE_METASTABLE_SAMP == "TRUE") begin if (POC_USE_METASTABLE_SAMP == "TRUE") samp_wait_ns = ONE[SAMP_WAIT_WIDTH-1:0]; if ({1'b0, samp_cntr_r} == samples) sm_ns = /*AK("COMPUTE")*/2'd1; samps_hi_ns = samps_hi_r + {{SAMPCNTRWIDTH{1'b0}}, pd_out_sel}; samp_cntr_ns = samp_cntr_r + ONE[SAMPCNTRWIDTH-1:0]; end end /*AL("COMPUTE")*/2'd1:begin sm_ns = /*AK("PSEN")*/2'd2; end /*AL("PSEN")*/2'd2:begin sm_ns = /*AK("PSDONE_WAIT")*/2'd3; psen_int = 1'b1; samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}}; samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}}; samps_hi_held_ns = samps_hi_r; tap_ns = (tap_r < TAPSPERKCLK[TAPCNTRWIDTH-1:0] - ONE[TAPCNTRWIDTH-1:0]) ? tap_r + ONE[TAPCNTRWIDTH-1:0] : {TAPCNTRWIDTH{1'b0}}; if (run_polarity_r) begin if (samps_zero_r) run_polarity_ns = 1'b0; end else begin if (samps_one_r) run_polarity_ns = 1'b1; end if (new_polarity) begin run_ns ={TAPCNTRWIDTH{1'b0}}; run_end_int = 1'b1; end else run_ns = run_r + ONE[TAPCNTRWIDTH-1:0]; end /*AL("PSDONE_WAIT")*/2'd3:begin samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0] - ONE[SAMP_WAIT_WIDTH-1:0]; if (psdone) sm_ns = /*AK("SAMPLE")*/2'd0; end endcase // case (sm_r) end // else: !if(rst == 1'b1) end // always @ (*) endmodule // mig_7series_v2_3_poc_tap_base // Local Variables: // verilog-library-directories:(".") // verilog-library-extensions:(".v") // verilog-autolabel-prefix: "2'd" // End:

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ui_top.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Top level of simple user interface. `timescale 1 ps / 1 ps module mig_7series_v2_3_ui_top # ( parameter TCQ = 100, parameter APP_DATA_WIDTH = 256, parameter APP_MASK_WIDTH = 32, parameter BANK_WIDTH = 3, parameter COL_WIDTH = 12, parameter CWL = 5, parameter DATA_BUF_ADDR_WIDTH = 5, parameter ECC = "OFF", parameter ECC_TEST = "OFF", parameter ORDERING = "NORM", parameter nCK_PER_CLK = 2, parameter RANKS = 4, parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter RANK_WIDTH = 2, parameter ROW_WIDTH = 16, parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN" ) (/*AUTOARG*/ // Outputs wr_data_mask, wr_data, use_addr, size, row, raw_not_ecc, rank, hi_priority, data_buf_addr, col, cmd, bank, app_wdf_rdy, app_rdy, app_rd_data_valid, app_rd_data_end, app_rd_data, app_ecc_multiple_err, correct_en, sr_req, app_sr_active, ref_req, app_ref_ack, zq_req, app_zq_ack, // Inputs wr_data_offset, wr_data_en, wr_data_addr, rst, rd_data_offset, rd_data_end, rd_data_en, rd_data_addr, rd_data, ecc_multiple, clk, app_wdf_wren, app_wdf_mask, app_wdf_end, app_wdf_data, app_sz, app_raw_not_ecc, app_hi_pri, app_en, app_cmd, app_addr, accept_ns, accept, app_correct_en, app_sr_req, sr_active, app_ref_req, ref_ack, app_zq_req, zq_ack ); input accept; localparam ADDR_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH; // Add a cycle to CWL for the register in RDIMM devices localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; input app_correct_en; output wire correct_en; assign correct_en = app_correct_en; input app_sr_req; output wire sr_req; assign sr_req = app_sr_req; input sr_active; output wire app_sr_active; assign app_sr_active = sr_active; input app_ref_req; output wire ref_req; assign ref_req = app_ref_req; input ref_ack; output wire app_ref_ack; assign app_ref_ack = ref_ack; input app_zq_req; output wire zq_req; assign zq_req = app_zq_req; input zq_ack; output wire app_zq_ack; assign app_zq_ack = zq_ack; /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input accept_ns; // To ui_cmd0 of ui_cmd.v input [ADDR_WIDTH-1:0] app_addr; // To ui_cmd0 of ui_cmd.v input [2:0] app_cmd; // To ui_cmd0 of ui_cmd.v input app_en; // To ui_cmd0 of ui_cmd.v input app_hi_pri; // To ui_cmd0 of ui_cmd.v input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; // To ui_wr_data0 of ui_wr_data.v input app_sz; // To ui_cmd0 of ui_cmd.v input [APP_DATA_WIDTH-1:0] app_wdf_data; // To ui_wr_data0 of ui_wr_data.v input app_wdf_end; // To ui_wr_data0 of ui_wr_data.v input [APP_MASK_WIDTH-1:0] app_wdf_mask; // To ui_wr_data0 of ui_wr_data.v input app_wdf_wren; // To ui_wr_data0 of ui_wr_data.v input clk; // To ui_cmd0 of ui_cmd.v, ... input [2*nCK_PER_CLK-1:0] ecc_multiple; // To ui_rd_data0 of ui_rd_data.v input [APP_DATA_WIDTH-1:0] rd_data; // To ui_rd_data0 of ui_rd_data.v input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To ui_rd_data0 of ui_rd_data.v input rd_data_en; // To ui_rd_data0 of ui_rd_data.v input rd_data_end; // To ui_rd_data0 of ui_rd_data.v input rd_data_offset; // To ui_rd_data0 of ui_rd_data.v input rst; // To ui_cmd0 of ui_cmd.v, ... input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; // To ui_wr_data0 of ui_wr_data.v input wr_data_en; // To ui_wr_data0 of ui_wr_data.v input wr_data_offset; // To ui_wr_data0 of ui_wr_data.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; // From ui_rd_data0 of ui_rd_data.v output [APP_DATA_WIDTH-1:0] app_rd_data; // From ui_rd_data0 of ui_rd_data.v output app_rd_data_end; // From ui_rd_data0 of ui_rd_data.v output app_rd_data_valid; // From ui_rd_data0 of ui_rd_data.v output app_rdy; // From ui_cmd0 of ui_cmd.v output app_wdf_rdy; // From ui_wr_data0 of ui_wr_data.v output [BANK_WIDTH-1:0] bank; // From ui_cmd0 of ui_cmd.v output [2:0] cmd; // From ui_cmd0 of ui_cmd.v output [COL_WIDTH-1:0] col; // From ui_cmd0 of ui_cmd.v output [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;// From ui_cmd0 of ui_cmd.v output hi_priority; // From ui_cmd0 of ui_cmd.v output [RANK_WIDTH-1:0] rank; // From ui_cmd0 of ui_cmd.v output [2*nCK_PER_CLK-1:0] raw_not_ecc; // From ui_wr_data0 of ui_wr_data.v output [ROW_WIDTH-1:0] row; // From ui_cmd0 of ui_cmd.v output size; // From ui_cmd0 of ui_cmd.v output use_addr; // From ui_cmd0 of ui_cmd.v output [APP_DATA_WIDTH-1:0] wr_data; // From ui_wr_data0 of ui_wr_data.v output [APP_MASK_WIDTH-1:0] wr_data_mask; // From ui_wr_data0 of ui_wr_data.v // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] ram_init_addr; // From ui_rd_data0 of ui_rd_data.v wire ram_init_done_r; // From ui_rd_data0 of ui_rd_data.v wire rd_accepted; // From ui_cmd0 of ui_cmd.v wire rd_buf_full; // From ui_rd_data0 of ui_rd_data.v wire [DATA_BUF_ADDR_WIDTH-1:0]rd_data_buf_addr_r;// From ui_rd_data0 of ui_rd_data.v wire wr_accepted; // From ui_cmd0 of ui_cmd.v wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;// From ui_wr_data0 of ui_wr_data.v wire wr_req_16; // From ui_wr_data0 of ui_wr_data.v // End of automatics // In the UI, the read and write buffers are allowed to be asymmetric to // to maximize read performance, but the MC's native interface requires // symmetry, so we zero-fill the write pointer generate if(DATA_BUF_ADDR_WIDTH > 4) begin assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0; end endgenerate mig_7series_v2_3_ui_cmd # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .ADDR_WIDTH (ADDR_WIDTH), .BANK_WIDTH (BANK_WIDTH), .COL_WIDTH (COL_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .RANK_WIDTH (RANK_WIDTH), .ROW_WIDTH (ROW_WIDTH), .RANKS (RANKS), .MEM_ADDR_ORDER (MEM_ADDR_ORDER)) ui_cmd0 (/*AUTOINST*/ // Outputs .app_rdy (app_rdy), .use_addr (use_addr), .rank (rank[RANK_WIDTH-1:0]), .bank (bank[BANK_WIDTH-1:0]), .row (row[ROW_WIDTH-1:0]), .col (col[COL_WIDTH-1:0]), .size (size), .cmd (cmd[2:0]), .hi_priority (hi_priority), .rd_accepted (rd_accepted), .wr_accepted (wr_accepted), .data_buf_addr (data_buf_addr), // Inputs .rst (rst), .clk (clk), .accept_ns (accept_ns), .rd_buf_full (rd_buf_full), .wr_req_16 (wr_req_16), .app_addr (app_addr[ADDR_WIDTH-1:0]), .app_cmd (app_cmd[2:0]), .app_sz (app_sz), .app_hi_pri (app_hi_pri), .app_en (app_en), .wr_data_buf_addr (wr_data_buf_addr), .rd_data_buf_addr_r (rd_data_buf_addr_r)); mig_7series_v2_3_ui_wr_data # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .APP_DATA_WIDTH (APP_DATA_WIDTH), .APP_MASK_WIDTH (APP_MASK_WIDTH), .nCK_PER_CLK (nCK_PER_CLK), .ECC (ECC), .ECC_TEST (ECC_TEST), .CWL (CWL_M)) ui_wr_data0 (/*AUTOINST*/ // Outputs .app_wdf_rdy (app_wdf_rdy), .wr_req_16 (wr_req_16), .wr_data_buf_addr (wr_data_buf_addr[3:0]), .wr_data (wr_data[APP_DATA_WIDTH-1:0]), .wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]), .raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]), // Inputs .rst (rst), .clk (clk), .app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]), .app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]), .app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]), .app_wdf_wren (app_wdf_wren), .app_wdf_end (app_wdf_end), .wr_data_offset (wr_data_offset), .wr_data_addr (wr_data_addr[3:0]), .wr_data_en (wr_data_en), .wr_accepted (wr_accepted), .ram_init_done_r (ram_init_done_r), .ram_init_addr (ram_init_addr)); mig_7series_v2_3_ui_rd_data # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .APP_DATA_WIDTH (APP_DATA_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .nCK_PER_CLK (nCK_PER_CLK), .ECC (ECC), .ORDERING (ORDERING)) ui_rd_data0 (/*AUTOINST*/ // Outputs .ram_init_done_r (ram_init_done_r), .ram_init_addr (ram_init_addr), .app_rd_data_valid (app_rd_data_valid), .app_rd_data_end (app_rd_data_end), .app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]), .app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]), .rd_buf_full (rd_buf_full), .rd_data_buf_addr_r (rd_data_buf_addr_r), // Inputs .rst (rst), .clk (clk), .rd_data_en (rd_data_en), .rd_data_addr (rd_data_addr), .rd_data_offset (rd_data_offset), .rd_data_end (rd_data_end), .rd_data (rd_data[APP_DATA_WIDTH-1:0]), .ecc_multiple (ecc_multiple[3:0]), .rd_accepted (rd_accepted)); endmodule // ui_top // Local Variables: // verilog-library-directories:("." "../mc") // End:

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ui_top.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Top level of simple user interface. `timescale 1 ps / 1 ps module mig_7series_v2_3_ui_top # ( parameter TCQ = 100, parameter APP_DATA_WIDTH = 256, parameter APP_MASK_WIDTH = 32, parameter BANK_WIDTH = 3, parameter COL_WIDTH = 12, parameter CWL = 5, parameter DATA_BUF_ADDR_WIDTH = 5, parameter ECC = "OFF", parameter ECC_TEST = "OFF", parameter ORDERING = "NORM", parameter nCK_PER_CLK = 2, parameter RANKS = 4, parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter RANK_WIDTH = 2, parameter ROW_WIDTH = 16, parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN" ) (/*AUTOARG*/ // Outputs wr_data_mask, wr_data, use_addr, size, row, raw_not_ecc, rank, hi_priority, data_buf_addr, col, cmd, bank, app_wdf_rdy, app_rdy, app_rd_data_valid, app_rd_data_end, app_rd_data, app_ecc_multiple_err, correct_en, sr_req, app_sr_active, ref_req, app_ref_ack, zq_req, app_zq_ack, // Inputs wr_data_offset, wr_data_en, wr_data_addr, rst, rd_data_offset, rd_data_end, rd_data_en, rd_data_addr, rd_data, ecc_multiple, clk, app_wdf_wren, app_wdf_mask, app_wdf_end, app_wdf_data, app_sz, app_raw_not_ecc, app_hi_pri, app_en, app_cmd, app_addr, accept_ns, accept, app_correct_en, app_sr_req, sr_active, app_ref_req, ref_ack, app_zq_req, zq_ack ); input accept; localparam ADDR_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH; // Add a cycle to CWL for the register in RDIMM devices localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; input app_correct_en; output wire correct_en; assign correct_en = app_correct_en; input app_sr_req; output wire sr_req; assign sr_req = app_sr_req; input sr_active; output wire app_sr_active; assign app_sr_active = sr_active; input app_ref_req; output wire ref_req; assign ref_req = app_ref_req; input ref_ack; output wire app_ref_ack; assign app_ref_ack = ref_ack; input app_zq_req; output wire zq_req; assign zq_req = app_zq_req; input zq_ack; output wire app_zq_ack; assign app_zq_ack = zq_ack; /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input accept_ns; // To ui_cmd0 of ui_cmd.v input [ADDR_WIDTH-1:0] app_addr; // To ui_cmd0 of ui_cmd.v input [2:0] app_cmd; // To ui_cmd0 of ui_cmd.v input app_en; // To ui_cmd0 of ui_cmd.v input app_hi_pri; // To ui_cmd0 of ui_cmd.v input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; // To ui_wr_data0 of ui_wr_data.v input app_sz; // To ui_cmd0 of ui_cmd.v input [APP_DATA_WIDTH-1:0] app_wdf_data; // To ui_wr_data0 of ui_wr_data.v input app_wdf_end; // To ui_wr_data0 of ui_wr_data.v input [APP_MASK_WIDTH-1:0] app_wdf_mask; // To ui_wr_data0 of ui_wr_data.v input app_wdf_wren; // To ui_wr_data0 of ui_wr_data.v input clk; // To ui_cmd0 of ui_cmd.v, ... input [2*nCK_PER_CLK-1:0] ecc_multiple; // To ui_rd_data0 of ui_rd_data.v input [APP_DATA_WIDTH-1:0] rd_data; // To ui_rd_data0 of ui_rd_data.v input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To ui_rd_data0 of ui_rd_data.v input rd_data_en; // To ui_rd_data0 of ui_rd_data.v input rd_data_end; // To ui_rd_data0 of ui_rd_data.v input rd_data_offset; // To ui_rd_data0 of ui_rd_data.v input rst; // To ui_cmd0 of ui_cmd.v, ... input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; // To ui_wr_data0 of ui_wr_data.v input wr_data_en; // To ui_wr_data0 of ui_wr_data.v input wr_data_offset; // To ui_wr_data0 of ui_wr_data.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; // From ui_rd_data0 of ui_rd_data.v output [APP_DATA_WIDTH-1:0] app_rd_data; // From ui_rd_data0 of ui_rd_data.v output app_rd_data_end; // From ui_rd_data0 of ui_rd_data.v output app_rd_data_valid; // From ui_rd_data0 of ui_rd_data.v output app_rdy; // From ui_cmd0 of ui_cmd.v output app_wdf_rdy; // From ui_wr_data0 of ui_wr_data.v output [BANK_WIDTH-1:0] bank; // From ui_cmd0 of ui_cmd.v output [2:0] cmd; // From ui_cmd0 of ui_cmd.v output [COL_WIDTH-1:0] col; // From ui_cmd0 of ui_cmd.v output [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;// From ui_cmd0 of ui_cmd.v output hi_priority; // From ui_cmd0 of ui_cmd.v output [RANK_WIDTH-1:0] rank; // From ui_cmd0 of ui_cmd.v output [2*nCK_PER_CLK-1:0] raw_not_ecc; // From ui_wr_data0 of ui_wr_data.v output [ROW_WIDTH-1:0] row; // From ui_cmd0 of ui_cmd.v output size; // From ui_cmd0 of ui_cmd.v output use_addr; // From ui_cmd0 of ui_cmd.v output [APP_DATA_WIDTH-1:0] wr_data; // From ui_wr_data0 of ui_wr_data.v output [APP_MASK_WIDTH-1:0] wr_data_mask; // From ui_wr_data0 of ui_wr_data.v // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] ram_init_addr; // From ui_rd_data0 of ui_rd_data.v wire ram_init_done_r; // From ui_rd_data0 of ui_rd_data.v wire rd_accepted; // From ui_cmd0 of ui_cmd.v wire rd_buf_full; // From ui_rd_data0 of ui_rd_data.v wire [DATA_BUF_ADDR_WIDTH-1:0]rd_data_buf_addr_r;// From ui_rd_data0 of ui_rd_data.v wire wr_accepted; // From ui_cmd0 of ui_cmd.v wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;// From ui_wr_data0 of ui_wr_data.v wire wr_req_16; // From ui_wr_data0 of ui_wr_data.v // End of automatics // In the UI, the read and write buffers are allowed to be asymmetric to // to maximize read performance, but the MC's native interface requires // symmetry, so we zero-fill the write pointer generate if(DATA_BUF_ADDR_WIDTH > 4) begin assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0; end endgenerate mig_7series_v2_3_ui_cmd # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .ADDR_WIDTH (ADDR_WIDTH), .BANK_WIDTH (BANK_WIDTH), .COL_WIDTH (COL_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .RANK_WIDTH (RANK_WIDTH), .ROW_WIDTH (ROW_WIDTH), .RANKS (RANKS), .MEM_ADDR_ORDER (MEM_ADDR_ORDER)) ui_cmd0 (/*AUTOINST*/ // Outputs .app_rdy (app_rdy), .use_addr (use_addr), .rank (rank[RANK_WIDTH-1:0]), .bank (bank[BANK_WIDTH-1:0]), .row (row[ROW_WIDTH-1:0]), .col (col[COL_WIDTH-1:0]), .size (size), .cmd (cmd[2:0]), .hi_priority (hi_priority), .rd_accepted (rd_accepted), .wr_accepted (wr_accepted), .data_buf_addr (data_buf_addr), // Inputs .rst (rst), .clk (clk), .accept_ns (accept_ns), .rd_buf_full (rd_buf_full), .wr_req_16 (wr_req_16), .app_addr (app_addr[ADDR_WIDTH-1:0]), .app_cmd (app_cmd[2:0]), .app_sz (app_sz), .app_hi_pri (app_hi_pri), .app_en (app_en), .wr_data_buf_addr (wr_data_buf_addr), .rd_data_buf_addr_r (rd_data_buf_addr_r)); mig_7series_v2_3_ui_wr_data # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .APP_DATA_WIDTH (APP_DATA_WIDTH), .APP_MASK_WIDTH (APP_MASK_WIDTH), .nCK_PER_CLK (nCK_PER_CLK), .ECC (ECC), .ECC_TEST (ECC_TEST), .CWL (CWL_M)) ui_wr_data0 (/*AUTOINST*/ // Outputs .app_wdf_rdy (app_wdf_rdy), .wr_req_16 (wr_req_16), .wr_data_buf_addr (wr_data_buf_addr[3:0]), .wr_data (wr_data[APP_DATA_WIDTH-1:0]), .wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]), .raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]), // Inputs .rst (rst), .clk (clk), .app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]), .app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]), .app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]), .app_wdf_wren (app_wdf_wren), .app_wdf_end (app_wdf_end), .wr_data_offset (wr_data_offset), .wr_data_addr (wr_data_addr[3:0]), .wr_data_en (wr_data_en), .wr_accepted (wr_accepted), .ram_init_done_r (ram_init_done_r), .ram_init_addr (ram_init_addr)); mig_7series_v2_3_ui_rd_data # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .APP_DATA_WIDTH (APP_DATA_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .nCK_PER_CLK (nCK_PER_CLK), .ECC (ECC), .ORDERING (ORDERING)) ui_rd_data0 (/*AUTOINST*/ // Outputs .ram_init_done_r (ram_init_done_r), .ram_init_addr (ram_init_addr), .app_rd_data_valid (app_rd_data_valid), .app_rd_data_end (app_rd_data_end), .app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]), .app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]), .rd_buf_full (rd_buf_full), .rd_data_buf_addr_r (rd_data_buf_addr_r), // Inputs .rst (rst), .clk (clk), .rd_data_en (rd_data_en), .rd_data_addr (rd_data_addr), .rd_data_offset (rd_data_offset), .rd_data_end (rd_data_end), .rd_data (rd_data[APP_DATA_WIDTH-1:0]), .ecc_multiple (ecc_multiple[3:0]), .rd_accepted (rd_accepted)); endmodule // ui_top // Local Variables: // verilog-library-directories:("." "../mc") // End:

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : ui_top.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Top level of simple user interface. `timescale 1 ps / 1 ps module mig_7series_v2_3_ui_top # ( parameter TCQ = 100, parameter APP_DATA_WIDTH = 256, parameter APP_MASK_WIDTH = 32, parameter BANK_WIDTH = 3, parameter COL_WIDTH = 12, parameter CWL = 5, parameter DATA_BUF_ADDR_WIDTH = 5, parameter ECC = "OFF", parameter ECC_TEST = "OFF", parameter ORDERING = "NORM", parameter nCK_PER_CLK = 2, parameter RANKS = 4, parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter RANK_WIDTH = 2, parameter ROW_WIDTH = 16, parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN" ) (/*AUTOARG*/ // Outputs wr_data_mask, wr_data, use_addr, size, row, raw_not_ecc, rank, hi_priority, data_buf_addr, col, cmd, bank, app_wdf_rdy, app_rdy, app_rd_data_valid, app_rd_data_end, app_rd_data, app_ecc_multiple_err, correct_en, sr_req, app_sr_active, ref_req, app_ref_ack, zq_req, app_zq_ack, // Inputs wr_data_offset, wr_data_en, wr_data_addr, rst, rd_data_offset, rd_data_end, rd_data_en, rd_data_addr, rd_data, ecc_multiple, clk, app_wdf_wren, app_wdf_mask, app_wdf_end, app_wdf_data, app_sz, app_raw_not_ecc, app_hi_pri, app_en, app_cmd, app_addr, accept_ns, accept, app_correct_en, app_sr_req, sr_active, app_ref_req, ref_ack, app_zq_req, zq_ack ); input accept; localparam ADDR_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH; // Add a cycle to CWL for the register in RDIMM devices localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL; input app_correct_en; output wire correct_en; assign correct_en = app_correct_en; input app_sr_req; output wire sr_req; assign sr_req = app_sr_req; input sr_active; output wire app_sr_active; assign app_sr_active = sr_active; input app_ref_req; output wire ref_req; assign ref_req = app_ref_req; input ref_ack; output wire app_ref_ack; assign app_ref_ack = ref_ack; input app_zq_req; output wire zq_req; assign zq_req = app_zq_req; input zq_ack; output wire app_zq_ack; assign app_zq_ack = zq_ack; /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input accept_ns; // To ui_cmd0 of ui_cmd.v input [ADDR_WIDTH-1:0] app_addr; // To ui_cmd0 of ui_cmd.v input [2:0] app_cmd; // To ui_cmd0 of ui_cmd.v input app_en; // To ui_cmd0 of ui_cmd.v input app_hi_pri; // To ui_cmd0 of ui_cmd.v input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; // To ui_wr_data0 of ui_wr_data.v input app_sz; // To ui_cmd0 of ui_cmd.v input [APP_DATA_WIDTH-1:0] app_wdf_data; // To ui_wr_data0 of ui_wr_data.v input app_wdf_end; // To ui_wr_data0 of ui_wr_data.v input [APP_MASK_WIDTH-1:0] app_wdf_mask; // To ui_wr_data0 of ui_wr_data.v input app_wdf_wren; // To ui_wr_data0 of ui_wr_data.v input clk; // To ui_cmd0 of ui_cmd.v, ... input [2*nCK_PER_CLK-1:0] ecc_multiple; // To ui_rd_data0 of ui_rd_data.v input [APP_DATA_WIDTH-1:0] rd_data; // To ui_rd_data0 of ui_rd_data.v input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To ui_rd_data0 of ui_rd_data.v input rd_data_en; // To ui_rd_data0 of ui_rd_data.v input rd_data_end; // To ui_rd_data0 of ui_rd_data.v input rd_data_offset; // To ui_rd_data0 of ui_rd_data.v input rst; // To ui_cmd0 of ui_cmd.v, ... input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; // To ui_wr_data0 of ui_wr_data.v input wr_data_en; // To ui_wr_data0 of ui_wr_data.v input wr_data_offset; // To ui_wr_data0 of ui_wr_data.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; // From ui_rd_data0 of ui_rd_data.v output [APP_DATA_WIDTH-1:0] app_rd_data; // From ui_rd_data0 of ui_rd_data.v output app_rd_data_end; // From ui_rd_data0 of ui_rd_data.v output app_rd_data_valid; // From ui_rd_data0 of ui_rd_data.v output app_rdy; // From ui_cmd0 of ui_cmd.v output app_wdf_rdy; // From ui_wr_data0 of ui_wr_data.v output [BANK_WIDTH-1:0] bank; // From ui_cmd0 of ui_cmd.v output [2:0] cmd; // From ui_cmd0 of ui_cmd.v output [COL_WIDTH-1:0] col; // From ui_cmd0 of ui_cmd.v output [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;// From ui_cmd0 of ui_cmd.v output hi_priority; // From ui_cmd0 of ui_cmd.v output [RANK_WIDTH-1:0] rank; // From ui_cmd0 of ui_cmd.v output [2*nCK_PER_CLK-1:0] raw_not_ecc; // From ui_wr_data0 of ui_wr_data.v output [ROW_WIDTH-1:0] row; // From ui_cmd0 of ui_cmd.v output size; // From ui_cmd0 of ui_cmd.v output use_addr; // From ui_cmd0 of ui_cmd.v output [APP_DATA_WIDTH-1:0] wr_data; // From ui_wr_data0 of ui_wr_data.v output [APP_MASK_WIDTH-1:0] wr_data_mask; // From ui_wr_data0 of ui_wr_data.v // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [3:0] ram_init_addr; // From ui_rd_data0 of ui_rd_data.v wire ram_init_done_r; // From ui_rd_data0 of ui_rd_data.v wire rd_accepted; // From ui_cmd0 of ui_cmd.v wire rd_buf_full; // From ui_rd_data0 of ui_rd_data.v wire [DATA_BUF_ADDR_WIDTH-1:0]rd_data_buf_addr_r;// From ui_rd_data0 of ui_rd_data.v wire wr_accepted; // From ui_cmd0 of ui_cmd.v wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;// From ui_wr_data0 of ui_wr_data.v wire wr_req_16; // From ui_wr_data0 of ui_wr_data.v // End of automatics // In the UI, the read and write buffers are allowed to be asymmetric to // to maximize read performance, but the MC's native interface requires // symmetry, so we zero-fill the write pointer generate if(DATA_BUF_ADDR_WIDTH > 4) begin assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0; end endgenerate mig_7series_v2_3_ui_cmd # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .ADDR_WIDTH (ADDR_WIDTH), .BANK_WIDTH (BANK_WIDTH), .COL_WIDTH (COL_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .RANK_WIDTH (RANK_WIDTH), .ROW_WIDTH (ROW_WIDTH), .RANKS (RANKS), .MEM_ADDR_ORDER (MEM_ADDR_ORDER)) ui_cmd0 (/*AUTOINST*/ // Outputs .app_rdy (app_rdy), .use_addr (use_addr), .rank (rank[RANK_WIDTH-1:0]), .bank (bank[BANK_WIDTH-1:0]), .row (row[ROW_WIDTH-1:0]), .col (col[COL_WIDTH-1:0]), .size (size), .cmd (cmd[2:0]), .hi_priority (hi_priority), .rd_accepted (rd_accepted), .wr_accepted (wr_accepted), .data_buf_addr (data_buf_addr), // Inputs .rst (rst), .clk (clk), .accept_ns (accept_ns), .rd_buf_full (rd_buf_full), .wr_req_16 (wr_req_16), .app_addr (app_addr[ADDR_WIDTH-1:0]), .app_cmd (app_cmd[2:0]), .app_sz (app_sz), .app_hi_pri (app_hi_pri), .app_en (app_en), .wr_data_buf_addr (wr_data_buf_addr), .rd_data_buf_addr_r (rd_data_buf_addr_r)); mig_7series_v2_3_ui_wr_data # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .APP_DATA_WIDTH (APP_DATA_WIDTH), .APP_MASK_WIDTH (APP_MASK_WIDTH), .nCK_PER_CLK (nCK_PER_CLK), .ECC (ECC), .ECC_TEST (ECC_TEST), .CWL (CWL_M)) ui_wr_data0 (/*AUTOINST*/ // Outputs .app_wdf_rdy (app_wdf_rdy), .wr_req_16 (wr_req_16), .wr_data_buf_addr (wr_data_buf_addr[3:0]), .wr_data (wr_data[APP_DATA_WIDTH-1:0]), .wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]), .raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]), // Inputs .rst (rst), .clk (clk), .app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]), .app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]), .app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]), .app_wdf_wren (app_wdf_wren), .app_wdf_end (app_wdf_end), .wr_data_offset (wr_data_offset), .wr_data_addr (wr_data_addr[3:0]), .wr_data_en (wr_data_en), .wr_accepted (wr_accepted), .ram_init_done_r (ram_init_done_r), .ram_init_addr (ram_init_addr)); mig_7series_v2_3_ui_rd_data # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .APP_DATA_WIDTH (APP_DATA_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .nCK_PER_CLK (nCK_PER_CLK), .ECC (ECC), .ORDERING (ORDERING)) ui_rd_data0 (/*AUTOINST*/ // Outputs .ram_init_done_r (ram_init_done_r), .ram_init_addr (ram_init_addr), .app_rd_data_valid (app_rd_data_valid), .app_rd_data_end (app_rd_data_end), .app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]), .app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]), .rd_buf_full (rd_buf_full), .rd_data_buf_addr_r (rd_data_buf_addr_r), // Inputs .rst (rst), .clk (clk), .rd_data_en (rd_data_en), .rd_data_addr (rd_data_addr), .rd_data_offset (rd_data_offset), .rd_data_end (rd_data_end), .rd_data (rd_data[APP_DATA_WIDTH-1:0]), .ecc_multiple (ecc_multiple[3:0]), .rd_accepted (rd_accepted)); endmodule // ui_top // Local Variables: // verilog-library-directories:("." "../mc") // End:

//***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 3.6 // \ \ Application : MIG // / / Filename : memc_ui_top_std.v // /___/ /\ Date Last Modified : $Date: 2011/06/17 11:11:25 $ // \ \ / \ Date Created : Fri Oct 08 2010 // \___\/\___\ // // Device : 7 Series // Design Name : DDR2 SDRAM & DDR3 SDRAM // Purpose : // Top level memory interface block. Instantiates a clock and // reset generator, the memory controller, the phy and the // user interface blocks. // Reference : // Revision History : //***************************************************************************** `timescale 1 ps / 1 ps (* X_CORE_INFO = "mig_7series_v2_3_ddr3_7Series, 2013.4" , CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v2_3,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Vivado, LEVEL=CONTROLLER, AXI_ENABLE=0, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, AXI_ENABLE=0, CLK_PERIOD=1250, PHY_RATIO=4, CLKIN_PERIOD=5000, VCCAUX_IO=2.0V, MEMORY_TYPE=SODIMM, MEMORY_PART=mt8ktf51264hz-1g6, DQ_WIDTH=64, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, CA_MIRROR=OFF, OUTPUT_DRV=HIGH, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=40, MEMORY_ADDRESS_MAP=BANK_ROW_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=0, SYSCLK_TYPE=DIFFERENTIAL, REFCLK_TYPE=USE_SYSTEM_CLOCK}" *) module mig_7series_v2_3_memc_ui_top_std # ( parameter TCQ = 100, parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3 parameter PAYLOAD_WIDTH = 64, parameter ADDR_CMD_MODE = "UNBUF", parameter AL = "0", // Additive Latency option parameter BANK_WIDTH = 3, // # of bank bits parameter BM_CNT_WIDTH = 2, // Bank machine counter width parameter BURST_MODE = "8", // Burst length parameter BURST_TYPE = "SEQ", // Burst type parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory parameter CL = 5, parameter COL_WIDTH = 12, // column address width parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY parameter CS_WIDTH = 1, // # of unique CS outputs parameter CKE_WIDTH = 1, // # of cke outputs parameter CWL = 5, parameter DATA_WIDTH = 64, parameter DATA_BUF_ADDR_WIDTH = 5, parameter DATA_BUF_OFFSET_WIDTH = 1, parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter DM_WIDTH = 8, // # of DM (data mask) parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH)) parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_TYPE = "DDR3", parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter ECC = "OFF", parameter ECC_WIDTH = 8, parameter ECC_TEST = "OFF", parameter MC_ERR_ADDR_WIDTH = 31, parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides parameter nAL = 0, // Additive latency (in clk cyc) parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank parameter ORDERING = "NORM", parameter IBUF_LPWR_MODE = "OFF", parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT" parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF" parameter IODELAY_GRP0 = "IODELAY_MIG0", parameter IODELAY_GRP1 = "IODELAY_MIG1", parameter FPGA_SPEED_GRADE = 1, parameter OUTPUT_DRV = "HIGH", parameter REG_CTRL = "OFF", parameter RTT_NOM = "60", parameter RTT_WR = "120", parameter STARVE_LIMIT = 2, parameter tCK = 2500, // pS parameter tCKE = 10000, // pS parameter tFAW = 40000, // pS parameter tPRDI = 1_000_000, // pS parameter tRAS = 37500, // pS parameter tRCD = 12500, // pS parameter tREFI = 7800000, // pS parameter tRFC = 110000, // pS parameter tRP = 12500, // pS parameter tRRD = 10000, // pS parameter tRTP = 7500, // pS parameter tWTR = 7500, // pS parameter tZQI = 128_000_000, // nS parameter tZQCS = 64, // CKs parameter USER_REFRESH = "OFF", // Whether user manages REF parameter TEMP_MON_EN = "ON", // Enable/Disable tempmon parameter WRLVL = "OFF", parameter DEBUG_PORT = "OFF", parameter CAL_WIDTH = "HALF", parameter RANK_WIDTH = 1, parameter RANKS = 4, parameter ODT_WIDTH = 1, parameter ROW_WIDTH = 16, // DRAM address bus width parameter ADDR_WIDTH = 32, parameter APP_MASK_WIDTH = 8, parameter APP_DATA_WIDTH = 64, parameter [3:0] BYTE_LANES_B0 = 4'b1111, parameter [3:0] BYTE_LANES_B1 = 4'b1111, parameter [3:0] BYTE_LANES_B2 = 4'b1111, parameter [3:0] BYTE_LANES_B3 = 4'b1111, parameter [3:0] BYTE_LANES_B4 = 4'b1111, parameter [3:0] DATA_CTL_B0 = 4'hc, parameter [3:0] DATA_CTL_B1 = 4'hf, parameter [3:0] DATA_CTL_B2 = 4'hf, parameter [3:0] DATA_CTL_B3 = 4'h0, parameter [3:0] DATA_CTL_B4 = 4'h0, parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000, parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000, parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000, // control/address/data pin mapping parameters parameter [143:0] CK_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter [191:0] ADDR_MAP = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000, parameter [35:0] BANK_MAP = 36'h000_000_000, parameter [11:0] CAS_MAP = 12'h000, parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00, parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000, parameter CKE_ODT_AUX = "FALSE", parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000, parameter [11:0] PARITY_MAP = 12'h000, parameter [11:0] RAS_MAP = 12'h000, parameter [11:0] WE_MAP = 12'h000, parameter [143:0] DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000, parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000, parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000, parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000, parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001, parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000, parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN", // calibration Address. The address given below will be used for calibration // read and write operations. parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address parameter SIM_BYPASS_INIT_CAL = "OFF", parameter REFCLK_FREQ = 300.0, parameter USE_CS_PORT = 1, // Support chip select output parameter USE_DM_PORT = 1, // Support data mask output parameter USE_ODT_PORT = 1, // Support ODT output parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering parameter TAPSPERKCLK = 56 ) ( // Clock and reset ports input clk, input [1:0] clk_ref, input mem_refclk , input freq_refclk , input pll_lock, input sync_pulse , input mmcm_ps_clk, input poc_sample_pd, input rst, // memory interface ports inout [DQ_WIDTH-1:0] ddr_dq, inout [DQS_WIDTH-1:0] ddr_dqs_n, inout [DQS_WIDTH-1:0] ddr_dqs, output [ROW_WIDTH-1:0] ddr_addr, output [BANK_WIDTH-1:0] ddr_ba, output ddr_cas_n, output [CK_WIDTH-1:0] ddr_ck_n, output [CK_WIDTH-1:0] ddr_ck, output [CKE_WIDTH-1:0] ddr_cke, output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, output [DM_WIDTH-1:0] ddr_dm, output [ODT_WIDTH-1:0] ddr_odt, output ddr_ras_n, output ddr_reset_n, output ddr_parity, output ddr_we_n, output [BM_CNT_WIDTH-1:0] bank_mach_next, // user interface ports input [ADDR_WIDTH-1:0] app_addr, input [2:0] app_cmd, input app_en, input app_hi_pri, input [APP_DATA_WIDTH-1:0] app_wdf_data, input app_wdf_end, input [APP_MASK_WIDTH-1:0] app_wdf_mask, input app_wdf_wren, input app_correct_en_i, input [2*nCK_PER_CLK-1:0] app_raw_not_ecc, output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err, output [APP_DATA_WIDTH-1:0] app_rd_data, output app_rd_data_end, output app_rd_data_valid, output app_rdy, output app_wdf_rdy, input app_sr_req, output app_sr_active, input app_ref_req, output app_ref_ack, input app_zq_req, output app_zq_ack, // temperature monitor ports input [11:0] device_temp, //phase shift clock control output psen, output psincdec, input psdone, // debug logic ports input dbg_idel_down_all, input dbg_idel_down_cpt, input dbg_idel_up_all, input dbg_idel_up_cpt, input dbg_sel_all_idel_cpt, input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect, output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata, output [1:0] dbg_rdlvl_done, output [1:0] dbg_rdlvl_err, output [1:0] dbg_rdlvl_start, output [5:0] dbg_tap_cnt_during_wrlvl, output dbg_wl_edge_detect_valid, output dbg_wrlvl_done, output dbg_wrlvl_err, output dbg_wrlvl_start, output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, output init_calib_complete, input dbg_sel_pi_incdec, input dbg_sel_po_incdec, input [DQS_CNT_WIDTH:0] dbg_byte_sel, input dbg_pi_f_inc, input dbg_pi_f_dec, input dbg_po_f_inc, input dbg_po_f_stg23_sel, input dbg_po_f_dec, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, output dbg_rddata_valid, output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, output ref_dll_lock, input rst_phaser_ref, input iddr_rst, output [6*RANKS-1:0] dbg_rd_data_offset, output [255:0] dbg_calib_top, output [255:0] dbg_phy_wrlvl, output [255:0] dbg_phy_rdlvl, output [99:0] dbg_phy_wrcal, output [255:0] dbg_phy_init, output [255:0] dbg_prbs_rdlvl, output [255:0] dbg_dqs_found_cal, output [5:0] dbg_pi_counter_read_val, output [8:0] dbg_po_counter_read_val, output dbg_pi_phaselock_start, output dbg_pi_phaselocked_done, output dbg_pi_phaselock_err, output dbg_pi_dqsfound_start, output dbg_pi_dqsfound_done, output dbg_pi_dqsfound_err, output dbg_wrcal_start, output dbg_wrcal_done, output dbg_wrcal_err, output [11:0] dbg_pi_dqs_found_lanes_phy4lanes, output [11:0] dbg_pi_phase_locked_phy4lanes, output [6*RANKS-1:0] dbg_calib_rd_data_offset_1, output [6*RANKS-1:0] dbg_calib_rd_data_offset_2, output [5:0] dbg_data_offset, output [5:0] dbg_data_offset_1, output [5:0] dbg_data_offset_2, output dbg_oclkdelay_calib_start, output dbg_oclkdelay_calib_done, output [255:0] dbg_phy_oclkdelay_cal, output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_final_dqs_tap_cnt_r, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps ); localparam IODELAY_GRP = (tCK <= 1500)? IODELAY_GRP1 : IODELAY_GRP0; // wire [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r; // wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps; // wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps; wire correct_en; wire [2*nCK_PER_CLK-1:0] raw_not_ecc; wire [2*nCK_PER_CLK-1:0] ecc_single; wire [2*nCK_PER_CLK-1:0] ecc_multiple; wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr; wire [DQ_WIDTH/8-1:0] fi_xor_we; wire [DQ_WIDTH-1:0] fi_xor_wrdata; wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset; wire wr_data_en; wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset; wire rd_data_en; wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; wire accept; wire accept_ns; wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data; wire rd_data_end; wire use_addr; wire size; wire [ROW_WIDTH-1:0] row; wire [RANK_WIDTH-1:0] rank; wire hi_priority; wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr; wire [COL_WIDTH-1:0] col; wire [2:0] cmd; wire [BANK_WIDTH-1:0] bank; wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data; wire [2*nCK_PER_CLK*PAYLOAD_WIDTH/8-1:0] wr_data_mask; wire app_sr_req_i; wire app_sr_active_i; wire app_ref_req_i; wire app_ref_ack_i; wire app_zq_req_i; wire app_zq_ack_i; wire rst_tg_mc; wire error; wire init_wrcal_complete; reg reset /* synthesis syn_maxfan = 10 */; //*************************************************************************** always @(posedge clk) reset <= #TCQ (rst | rst_tg_mc); assign fi_xor_we = {DQ_WIDTH/8{1'b0}} ; assign fi_xor_wrdata = {DQ_WIDTH{1'b0}} ; mig_7series_v2_3_mem_intfc # ( .TCQ (TCQ), .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT), .PAYLOAD_WIDTH (PAYLOAD_WIDTH), .ADDR_CMD_MODE (ADDR_CMD_MODE), .AL (AL), .BANK_WIDTH (BANK_WIDTH), .BM_CNT_WIDTH (BM_CNT_WIDTH), .BURST_MODE (BURST_MODE), .BURST_TYPE (BURST_TYPE), .CA_MIRROR (CA_MIRROR), .CK_WIDTH (CK_WIDTH), .COL_WIDTH (COL_WIDTH), .CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1), .CS_WIDTH (CS_WIDTH), .nCS_PER_RANK (nCS_PER_RANK), .CKE_WIDTH (CKE_WIDTH), .DATA_WIDTH (DATA_WIDTH), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .MASTER_PHY_CTL (MASTER_PHY_CTL), .DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH), .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE), .DM_WIDTH (DM_WIDTH), .DQ_CNT_WIDTH (DQ_CNT_WIDTH), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_TYPE (DRAM_TYPE), .DRAM_WIDTH (DRAM_WIDTH), .ECC (ECC), .ECC_WIDTH (ECC_WIDTH), .MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH), .REFCLK_FREQ (REFCLK_FREQ), .nAL (nAL), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .ORDERING (ORDERING), .OUTPUT_DRV (OUTPUT_DRV), .IBUF_LPWR_MODE (IBUF_LPWR_MODE), .BANK_TYPE (BANK_TYPE), .DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE), .DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN), .IODELAY_GRP (IODELAY_GRP), .FPGA_SPEED_GRADE (FPGA_SPEED_GRADE), .REG_CTRL (REG_CTRL), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .CL (CL), .CWL (CWL), .tCK (tCK), .tCKE (tCKE), .tFAW (tFAW), .tPRDI (tPRDI), .tRAS (tRAS), .tRCD (tRCD), .tREFI (tREFI), .tRFC (tRFC), .tRP (tRP), .tRRD (tRRD), .tRTP (tRTP), .tWTR (tWTR), .tZQI (tZQI), .tZQCS (tZQCS), .USER_REFRESH (USER_REFRESH), .TEMP_MON_EN (TEMP_MON_EN), .WRLVL (WRLVL), .DEBUG_PORT (DEBUG_PORT), .CAL_WIDTH (CAL_WIDTH), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .ODT_WIDTH (ODT_WIDTH), .ROW_WIDTH (ROW_WIDTH), .SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4), .PHY_0_BITLANES (PHY_0_BITLANES), .PHY_1_BITLANES (PHY_1_BITLANES), .PHY_2_BITLANES (PHY_2_BITLANES), .CK_BYTE_MAP (CK_BYTE_MAP), .ADDR_MAP (ADDR_MAP), .BANK_MAP (BANK_MAP), .CAS_MAP (CAS_MAP), .CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP), .CKE_MAP (CKE_MAP), .ODT_MAP (ODT_MAP), .CKE_ODT_AUX (CKE_ODT_AUX), .CS_MAP (CS_MAP), .PARITY_MAP (PARITY_MAP), .RAS_MAP (RAS_MAP), .WE_MAP (WE_MAP), .DQS_BYTE_MAP (DQS_BYTE_MAP), .DATA0_MAP (DATA0_MAP), .DATA1_MAP (DATA1_MAP), .DATA2_MAP (DATA2_MAP), .DATA3_MAP (DATA3_MAP), .DATA4_MAP (DATA4_MAP), .DATA5_MAP (DATA5_MAP), .DATA6_MAP (DATA6_MAP), .DATA7_MAP (DATA7_MAP), .DATA8_MAP (DATA8_MAP), .DATA9_MAP (DATA9_MAP), .DATA10_MAP (DATA10_MAP), .DATA11_MAP (DATA11_MAP), .DATA12_MAP (DATA12_MAP), .DATA13_MAP (DATA13_MAP), .DATA14_MAP (DATA14_MAP), .DATA15_MAP (DATA15_MAP), .DATA16_MAP (DATA16_MAP), .DATA17_MAP (DATA17_MAP), .MASK0_MAP (MASK0_MAP), .MASK1_MAP (MASK1_MAP), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG), .CALIB_ROW_ADD (CALIB_ROW_ADD), .CALIB_COL_ADD (CALIB_COL_ADD), .CALIB_BA_ADD (CALIB_BA_ADD), .STARVE_LIMIT (STARVE_LIMIT), .USE_CS_PORT (USE_CS_PORT), .USE_DM_PORT (USE_DM_PORT), .USE_ODT_PORT (USE_ODT_PORT), .IDELAY_ADJ (IDELAY_ADJ), .FINE_PER_BIT (FINE_PER_BIT), .CENTER_COMP_MODE (CENTER_COMP_MODE), .PI_VAL_ADJ (PI_VAL_ADJ), .TAPSPERKCLK (TAPSPERKCLK) ) mem_intfc0 ( .clk (clk), .clk_ref (tCK <= 1500 ? clk_ref[1] : clk_ref[0]), .mem_refclk (mem_refclk), //memory clock .freq_refclk (freq_refclk), .pll_lock (pll_lock), .sync_pulse (sync_pulse), .mmcm_ps_clk (mmcm_ps_clk), .poc_sample_pd (poc_sample_pd), .rst (rst), .error (error), .reset (reset), .rst_tg_mc (rst_tg_mc), .ddr_dq (ddr_dq), .ddr_dqs_n (ddr_dqs_n), .ddr_dqs (ddr_dqs), .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_cas_n (ddr_cas_n), .ddr_ck_n (ddr_ck_n), .ddr_ck (ddr_ck), .ddr_cke (ddr_cke), .ddr_cs_n (ddr_cs_n), .ddr_dm (ddr_dm), .ddr_odt (ddr_odt), .ddr_ras_n (ddr_ras_n), .ddr_reset_n (ddr_reset_n), .ddr_parity (ddr_parity), .ddr_we_n (ddr_we_n), .slot_0_present (SLOT_0_CONFIG), .slot_1_present (SLOT_1_CONFIG), .correct_en (correct_en), .bank (bank), .cmd (cmd), .col (col), .data_buf_addr (data_buf_addr), .wr_data (wr_data), .wr_data_mask (wr_data_mask), .rank (rank), .raw_not_ecc (raw_not_ecc), .row (row), .hi_priority (hi_priority), .size (size), .use_addr (use_addr), .accept (accept), .accept_ns (accept_ns), .ecc_single (ecc_single), .ecc_multiple (ecc_multiple), .ecc_err_addr (ecc_err_addr), .rd_data (rd_data), .rd_data_addr (rd_data_addr), .rd_data_en (rd_data_en), .rd_data_end (rd_data_end), .rd_data_offset (rd_data_offset), .wr_data_addr (wr_data_addr), .wr_data_en (wr_data_en), .wr_data_offset (wr_data_offset), .bank_mach_next (bank_mach_next), .init_calib_complete (init_calib_complete), .init_wrcal_complete (init_wrcal_complete), .app_sr_req (app_sr_req_i), .app_sr_active (app_sr_active_i), .app_ref_req (app_ref_req_i), .app_ref_ack (app_ref_ack_i), .app_zq_req (app_zq_req_i), .app_zq_ack (app_zq_ack_i), .device_temp (device_temp), .psen (psen), .psincdec (psincdec), .psdone (psdone), .fi_xor_we (fi_xor_we), .fi_xor_wrdata (fi_xor_wrdata), .dbg_idel_up_all (dbg_idel_up_all), .dbg_idel_down_all (dbg_idel_down_all), .dbg_idel_up_cpt (dbg_idel_up_cpt), .dbg_idel_down_cpt (dbg_idel_down_cpt), .dbg_sel_idel_cpt (dbg_sel_idel_cpt), .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), .dbg_calib_top (dbg_calib_top), .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), .dbg_phy_rdlvl (dbg_phy_rdlvl), .dbg_phy_wrcal (dbg_phy_wrcal), .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt), .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), .dbg_rddata (dbg_rddata), .dbg_rdlvl_done (dbg_rdlvl_done), .dbg_rdlvl_err (dbg_rdlvl_err), .dbg_rdlvl_start (dbg_rdlvl_start), .dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl), .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), .dbg_wrlvl_done (dbg_wrlvl_done), .dbg_wrlvl_err (dbg_wrlvl_err), .dbg_wrlvl_start (dbg_wrlvl_start), .dbg_sel_pi_incdec (dbg_sel_pi_incdec), .dbg_sel_po_incdec (dbg_sel_po_incdec), .dbg_byte_sel (dbg_byte_sel), .dbg_pi_f_inc (dbg_pi_f_inc), .dbg_pi_f_dec (dbg_pi_f_dec), .dbg_po_f_inc (dbg_po_f_inc), .dbg_po_f_stg23_sel (dbg_po_f_stg23_sel), .dbg_po_f_dec (dbg_po_f_dec), .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), .dbg_rddata_valid (dbg_rddata_valid), .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), .dbg_phy_wrlvl (dbg_phy_wrlvl), .dbg_pi_counter_read_val (dbg_pi_counter_read_val), .dbg_po_counter_read_val (dbg_po_counter_read_val), .ref_dll_lock (ref_dll_lock), .rst_phaser_ref (rst_phaser_ref), .iddr_rst (iddr_rst), .dbg_rd_data_offset (dbg_rd_data_offset), .dbg_phy_init (dbg_phy_init), .dbg_prbs_rdlvl (dbg_prbs_rdlvl), .dbg_dqs_found_cal (dbg_dqs_found_cal), .dbg_pi_phaselock_start (dbg_pi_phaselock_start), .dbg_pi_phaselocked_done (dbg_pi_phaselocked_done), .dbg_pi_phaselock_err (dbg_pi_phaselock_err), .dbg_pi_dqsfound_start (dbg_pi_dqsfound_start), .dbg_pi_dqsfound_done (dbg_pi_dqsfound_done), .dbg_pi_dqsfound_err (dbg_pi_dqsfound_err), .dbg_wrcal_start (dbg_wrcal_start), .dbg_wrcal_done (dbg_wrcal_done), .dbg_wrcal_err (dbg_wrcal_err), .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes), .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes), .dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1), .dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2), .dbg_data_offset (dbg_data_offset), .dbg_data_offset_1 (dbg_data_offset_1), .dbg_data_offset_2 (dbg_data_offset_2), .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal), .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data), .dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start), .dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done), .prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r), .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps), .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps) ); mig_7series_v2_3_ui_top # ( .TCQ (TCQ), .APP_DATA_WIDTH (APP_DATA_WIDTH), .APP_MASK_WIDTH (APP_MASK_WIDTH), .BANK_WIDTH (BANK_WIDTH), .COL_WIDTH (COL_WIDTH), .CWL (CWL), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .ECC (ECC), .ECC_TEST (ECC_TEST), .nCK_PER_CLK (nCK_PER_CLK), .ORDERING (ORDERING), .RANKS (RANKS), .RANK_WIDTH (RANK_WIDTH), .ROW_WIDTH (ROW_WIDTH), .MEM_ADDR_ORDER (MEM_ADDR_ORDER) ) u_ui_top ( .wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]), .wr_data (wr_data[APP_DATA_WIDTH-1:0]), .use_addr (use_addr), .size (size), .row (row), .raw_not_ecc (raw_not_ecc), .rank (rank), .hi_priority (hi_priority), .data_buf_addr (data_buf_addr), .col (col), .cmd (cmd), .bank (bank), .app_wdf_rdy (app_wdf_rdy), .app_rdy (app_rdy), .app_rd_data_valid (app_rd_data_valid), .app_rd_data_end (app_rd_data_end), .app_rd_data (app_rd_data), .app_ecc_multiple_err (app_ecc_multiple_err), .correct_en (correct_en), .wr_data_offset (wr_data_offset), .wr_data_en (wr_data_en), .wr_data_addr (wr_data_addr), .rst (reset), .rd_data_offset (rd_data_offset), .rd_data_end (rd_data_end), .rd_data_en (rd_data_en), .rd_data_addr (rd_data_addr), .rd_data (rd_data[APP_DATA_WIDTH-1:0]), .ecc_multiple (ecc_multiple), .clk (clk), .app_wdf_wren (app_wdf_wren), .app_wdf_mask (app_wdf_mask), .app_wdf_end (app_wdf_end), .app_wdf_data (app_wdf_data), .app_sz (1'b1), .app_raw_not_ecc (app_raw_not_ecc), .app_hi_pri (app_hi_pri), .app_en (app_en), .app_cmd (app_cmd), .app_addr (app_addr), .accept_ns (accept_ns), .accept (accept), .app_correct_en (app_correct_en_i), .app_sr_req (app_sr_req), .sr_req (app_sr_req_i), .sr_active (app_sr_active_i), .app_sr_active (app_sr_active), .app_ref_req (app_ref_req), .ref_req (app_ref_req_i), .ref_ack (app_ref_ack_i), .app_ref_ack (app_ref_ack), .app_zq_req (app_zq_req), .zq_req (app_zq_req_i), .zq_ack (app_zq_ack_i), .app_zq_ack (app_zq_ack) ); endmodule

//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v2_3_poc_cc.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 20 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: Phaser out characterization and control. Logic to interface with //Chipscope and control. Intended to support real time observation. Largely //not generated for production implementations. //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_poc_cc # (parameter TCQ = 100, parameter CCENABLE = 0, parameter PCT_SAMPS_SOLID = 95, parameter SAMPCNTRWIDTH = 8, parameter SAMPLES = 128, parameter TAPCNTRWIDTH = 7) (/*AUTOARG*/ // Outputs samples, samps_solid_thresh, poc_error, // Inputs tap, samps_hi_held, psen, clk, rst, ktap_at_right_edge, ktap_at_left_edge, mmcm_lbclk_edge_aligned, mmcm_edge_detect_done, fall_lead_right, fall_trail_right, rise_lead_right, rise_trail_right, fall_lead_left, fall_trail_left, rise_lead_left, rise_trail_left, fall_lead_center, fall_trail_center, rise_lead_center, rise_trail_center ); // Remember SAMPLES is whole number counting. Zero corresponds to one sample. localparam integer SAMPS_SOLID_THRESH = (SAMPLES+1) * PCT_SAMPS_SOLID * 0.01; output [SAMPCNTRWIDTH:0] samples, samps_solid_thresh; input [TAPCNTRWIDTH-1:0] tap; input [SAMPCNTRWIDTH:0] samps_hi_held; input psen; input clk, rst; input ktap_at_right_edge, ktap_at_left_edge; input mmcm_lbclk_edge_aligned; wire reset_aligned_cnt = rst || ktap_at_right_edge || ktap_at_left_edge || mmcm_lbclk_edge_aligned; input mmcm_edge_detect_done; reg mmcm_edge_detect_done_r; always @(posedge clk) mmcm_edge_detect_done_r <= #TCQ mmcm_edge_detect_done; wire done = mmcm_edge_detect_done && ~mmcm_edge_detect_done_r; reg [6:0] aligned_cnt_r; wire [6:0] aligned_cnt_ns = reset_aligned_cnt ? 7'b0 : aligned_cnt_r + {6'b0, done}; always @(posedge clk) aligned_cnt_r <= #TCQ aligned_cnt_ns; reg poc_error_r; wire poc_error_ns = ~rst && (aligned_cnt_r[6] || poc_error_r); always @(posedge clk) poc_error_r <= #TCQ poc_error_ns; output poc_error; assign poc_error = poc_error_r; input [TAPCNTRWIDTH-1:0] fall_lead_right, fall_trail_right, rise_lead_right, rise_trail_right; input [TAPCNTRWIDTH-1:0] fall_lead_left, fall_trail_left, rise_lead_left, rise_trail_left; input [TAPCNTRWIDTH-1:0] fall_lead_center, fall_trail_center, rise_lead_center, rise_trail_center; generate if (CCENABLE == 0) begin : no_characterization assign samples = SAMPLES[SAMPCNTRWIDTH:0]; assign samps_solid_thresh = SAMPS_SOLID_THRESH[SAMPCNTRWIDTH:0]; end else begin : characterization end endgenerate endmodule // mig_7series_v2_3_poc_cc

//***************************************************************************** // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version:%version // \ \ Application: MIG // / / Filename: mig_7series_v2_3_poc_cc.v // /___/ /\ Date Last Modified: $$ // \ \ / \ Date Created:Tue 20 Jan 2014 // \___\/\___\ // //Device: Virtex-7 //Design Name: DDR3 SDRAM //Purpose: Phaser out characterization and control. Logic to interface with //Chipscope and control. Intended to support real time observation. Largely //not generated for production implementations. //Reference: //Revision History: //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_poc_cc # (parameter TCQ = 100, parameter CCENABLE = 0, parameter PCT_SAMPS_SOLID = 95, parameter SAMPCNTRWIDTH = 8, parameter SAMPLES = 128, parameter TAPCNTRWIDTH = 7) (/*AUTOARG*/ // Outputs samples, samps_solid_thresh, poc_error, // Inputs tap, samps_hi_held, psen, clk, rst, ktap_at_right_edge, ktap_at_left_edge, mmcm_lbclk_edge_aligned, mmcm_edge_detect_done, fall_lead_right, fall_trail_right, rise_lead_right, rise_trail_right, fall_lead_left, fall_trail_left, rise_lead_left, rise_trail_left, fall_lead_center, fall_trail_center, rise_lead_center, rise_trail_center ); // Remember SAMPLES is whole number counting. Zero corresponds to one sample. localparam integer SAMPS_SOLID_THRESH = (SAMPLES+1) * PCT_SAMPS_SOLID * 0.01; output [SAMPCNTRWIDTH:0] samples, samps_solid_thresh; input [TAPCNTRWIDTH-1:0] tap; input [SAMPCNTRWIDTH:0] samps_hi_held; input psen; input clk, rst; input ktap_at_right_edge, ktap_at_left_edge; input mmcm_lbclk_edge_aligned; wire reset_aligned_cnt = rst || ktap_at_right_edge || ktap_at_left_edge || mmcm_lbclk_edge_aligned; input mmcm_edge_detect_done; reg mmcm_edge_detect_done_r; always @(posedge clk) mmcm_edge_detect_done_r <= #TCQ mmcm_edge_detect_done; wire done = mmcm_edge_detect_done && ~mmcm_edge_detect_done_r; reg [6:0] aligned_cnt_r; wire [6:0] aligned_cnt_ns = reset_aligned_cnt ? 7'b0 : aligned_cnt_r + {6'b0, done}; always @(posedge clk) aligned_cnt_r <= #TCQ aligned_cnt_ns; reg poc_error_r; wire poc_error_ns = ~rst && (aligned_cnt_r[6] || poc_error_r); always @(posedge clk) poc_error_r <= #TCQ poc_error_ns; output poc_error; assign poc_error = poc_error_r; input [TAPCNTRWIDTH-1:0] fall_lead_right, fall_trail_right, rise_lead_right, rise_trail_right; input [TAPCNTRWIDTH-1:0] fall_lead_left, fall_trail_left, rise_lead_left, rise_trail_left; input [TAPCNTRWIDTH-1:0] fall_lead_center, fall_trail_center, rise_lead_center, rise_trail_center; generate if (CCENABLE == 0) begin : no_characterization assign samples = SAMPLES[SAMPCNTRWIDTH:0]; assign samps_solid_thresh = SAMPS_SOLID_THRESH[SAMPCNTRWIDTH:0]; end else begin : characterization end endgenerate endmodule // mig_7series_v2_3_poc_cc

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : mig_7series_v2_3_tempmon.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Jul 25 2012 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Monitors chip temperature via the XADC and adjusts the // stage 2 tap values as appropriate. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_tempmon # ( parameter TCQ = 100, // Register delay (sim only) parameter TEMP_MON_CONTROL = "INTERNAL", // XADC or user temperature source parameter XADC_CLK_PERIOD = 5000, // pS (default to 200 MHz refclk) parameter tTEMPSAMPLE = 10000000 // ps (10 us) ) ( input clk, // Fabric clock input xadc_clk, input rst, // System reset input [11:0] device_temp_i, // User device temperature output [11:0] device_temp // Sampled temperature ); //*************************************************************************** // Function cdiv // Description: // This function performs ceiling division (divide and round-up) // Inputs: // num: integer to be divided // div: divisor // Outputs: // cdiv: result of ceiling division (num/div, rounded up) //*************************************************************************** function integer cdiv (input integer num, input integer div); begin // perform division, then add 1 if and only if remainder is non-zero cdiv = (num/div) + (((num%div)>0) ? 1 : 0); end endfunction // cdiv //*************************************************************************** // Function clogb2 // Description: // This function performs binary logarithm and rounds up // Inputs: // size: integer to perform binary log upon // Outputs: // clogb2: result of binary logarithm, rounded up //*************************************************************************** function integer clogb2 (input integer size); begin size = size - 1; // increment clogb2 from 1 for each bit in size for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1) size = size >> 1; end endfunction // clogb2 // Synchronization registers (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r1; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r2; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r3 /* synthesis syn_srlstyle="registers" */; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r4; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r5; // Output register (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_r; wire [11:0] device_temp_lcl; reg [3:0] sync_cntr = 4'b0000; reg device_temp_sync_r4_neq_r3; // (* ASYNC_REG = "TRUE" *) reg rst_r1; // (* ASYNC_REG = "TRUE" *) reg rst_r2; // // Synchronization rst to XADC clock domain // always @(posedge xadc_clk) begin // rst_r1 <= rst; // rst_r2 <= rst_r1; // end // Synchronization counter always @(posedge clk) begin device_temp_sync_r1 <= #TCQ device_temp_lcl; device_temp_sync_r2 <= #TCQ device_temp_sync_r1; device_temp_sync_r3 <= #TCQ device_temp_sync_r2; device_temp_sync_r4 <= #TCQ device_temp_sync_r3; device_temp_sync_r5 <= #TCQ device_temp_sync_r4; device_temp_sync_r4_neq_r3 <= #TCQ (device_temp_sync_r4 != device_temp_sync_r3) ? 1'b1 : 1'b0; end always @(posedge clk) if(rst || (device_temp_sync_r4_neq_r3)) sync_cntr <= #TCQ 4'b0000; else if(~&sync_cntr) sync_cntr <= #TCQ sync_cntr + 4'b0001; always @(posedge clk) if(&sync_cntr) device_temp_r <= #TCQ device_temp_sync_r5; assign device_temp = device_temp_r; generate if(TEMP_MON_CONTROL == "EXTERNAL") begin : user_supplied_temperature assign device_temp_lcl = device_temp_i; end else begin : xadc_supplied_temperature // calculate polling timer width and limit localparam nTEMPSAMP = cdiv(tTEMPSAMPLE, XADC_CLK_PERIOD); localparam nTEMPSAMP_CLKS = nTEMPSAMP; localparam nTEMPSAMP_CLKS_M6 = nTEMPSAMP - 6; localparam nTEMPSAMP_CNTR_WIDTH = clogb2(nTEMPSAMP_CLKS); // Temperature sampler FSM encoding localparam INIT_IDLE = 2'b00; localparam REQUEST_READ_TEMP = 2'b01; localparam WAIT_FOR_READ = 2'b10; localparam READ = 2'b11; // polling timer and tick reg [nTEMPSAMP_CNTR_WIDTH-1:0] sample_timer = {nTEMPSAMP_CNTR_WIDTH{1'b0}}; reg sample_timer_en = 1'b0; reg sample_timer_clr = 1'b0; reg sample_en = 1'b0; // Temperature sampler state reg [2:0] tempmon_state = INIT_IDLE; reg [2:0] tempmon_next_state = INIT_IDLE; // XADC interfacing reg xadc_den = 1'b0; wire xadc_drdy; wire [15:0] xadc_do; reg xadc_drdy_r = 1'b0; reg [15:0] xadc_do_r = 1'b0; // Temperature storage reg [11:0] temperature = 12'b0; // Reset sync (* ASYNC_REG = "TRUE" *) reg rst_r1; (* ASYNC_REG = "TRUE" *) reg rst_r2; // Synchronization rst to XADC clock domain always @(posedge xadc_clk) begin rst_r1 <= rst; rst_r2 <= rst_r1; end // XADC polling interval timer always @ (posedge xadc_clk) if(rst_r2 || sample_timer_clr) sample_timer <= #TCQ {nTEMPSAMP_CNTR_WIDTH{1'b0}}; else if(sample_timer_en) sample_timer <= #TCQ sample_timer + 1'b1; // XADC sampler state transition always @(posedge xadc_clk) if(rst_r2) tempmon_state <= #TCQ INIT_IDLE; else tempmon_state <= #TCQ tempmon_next_state; // Sample enable always @(posedge xadc_clk) sample_en <= #TCQ (sample_timer == nTEMPSAMP_CLKS_M6) ? 1'b1 : 1'b0; // XADC sampler next state transition always @(tempmon_state or sample_en or xadc_drdy_r) begin tempmon_next_state = tempmon_state; case(tempmon_state) INIT_IDLE: if(sample_en) tempmon_next_state = REQUEST_READ_TEMP; REQUEST_READ_TEMP: tempmon_next_state = WAIT_FOR_READ; WAIT_FOR_READ: if(xadc_drdy_r) tempmon_next_state = READ; READ: tempmon_next_state = INIT_IDLE; default: tempmon_next_state = INIT_IDLE; endcase end // Sample timer clear always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) sample_timer_clr <= #TCQ 1'b0; else if(tempmon_state == REQUEST_READ_TEMP) sample_timer_clr <= #TCQ 1'b1; // Sample timer enable always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == REQUEST_READ_TEMP)) sample_timer_en <= #TCQ 1'b0; else if((tempmon_state == INIT_IDLE) || (tempmon_state == READ)) sample_timer_en <= #TCQ 1'b1; // XADC enable always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) xadc_den <= #TCQ 1'b0; else if(tempmon_state == REQUEST_READ_TEMP) xadc_den <= #TCQ 1'b1; // Register XADC outputs always @(posedge xadc_clk) if(rst_r2) begin xadc_drdy_r <= #TCQ 1'b0; xadc_do_r <= #TCQ 16'b0; end else begin xadc_drdy_r <= #TCQ xadc_drdy; xadc_do_r <= #TCQ xadc_do; end // Store current read value always @(posedge xadc_clk) if(rst_r2) temperature <= #TCQ 12'b0; else if(tempmon_state == READ) temperature <= #TCQ xadc_do_r[15:4]; assign device_temp_lcl = temperature; // XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter // 7 Series // Xilinx HDL Libraries Guide, version 14.1 XADC #( // INIT_40 - INIT_42: XADC configuration registers .INIT_40(16'h1000), // config reg 0 .INIT_41(16'h2fff), // config reg 1 .INIT_42(16'h0800), // config reg 2 // INIT_48 - INIT_4F: Sequence Registers .INIT_48(16'h0101), // Sequencer channel selection .INIT_49(16'h0000), // Sequencer channel selection .INIT_4A(16'h0100), // Sequencer Average selection .INIT_4B(16'h0000), // Sequencer Average selection .INIT_4C(16'h0000), // Sequencer Bipolar selection .INIT_4D(16'h0000), // Sequencer Bipolar selection .INIT_4E(16'h0000), // Sequencer Acq time selection .INIT_4F(16'h0000), // Sequencer Acq time selection // INIT_50 - INIT_58, INIT5C: Alarm Limit Registers .INIT_50(16'hb5ed), // Temp alarm trigger .INIT_51(16'h57e4), // Vccint upper alarm limit .INIT_52(16'ha147), // Vccaux upper alarm limit .INIT_53(16'hca33), // Temp alarm OT upper .INIT_54(16'ha93a), // Temp alarm reset .INIT_55(16'h52c6), // Vccint lower alarm limit .INIT_56(16'h9555), // Vccaux lower alarm limit .INIT_57(16'hae4e), // Temp alarm OT reset .INIT_58(16'h5999), // VBRAM upper alarm limit .INIT_5C(16'h5111), // VBRAM lower alarm limit // Simulation attributes: Set for proepr simulation behavior .SIM_DEVICE("7SERIES") // Select target device (values) ) XADC_inst ( // ALARMS: 8-bit (each) output: ALM, OT .ALM(), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram .OT(), // 1-bit output: Over-Temperature alarm // Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports .DO(xadc_do), // 16-bit output: DRP output data bus .DRDY(xadc_drdy), // 1-bit output: DRP data ready // STATUS: 1-bit (each) output: XADC status ports .BUSY(), // 1-bit output: ADC busy output .CHANNEL(), // 5-bit output: Channel selection outputs .EOC(), // 1-bit output: End of Conversion .EOS(), // 1-bit output: End of Sequence .JTAGBUSY(), // 1-bit output: JTAG DRP transaction in progress output .JTAGLOCKED(), // 1-bit output: JTAG requested DRP port lock .JTAGMODIFIED(), // 1-bit output: JTAG Write to the DRP has occurred .MUXADDR(), // 5-bit output: External MUX channel decode // Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0] .VAUXN(16'b0), // 16-bit input: N-side auxiliary analog input .VAUXP(16'b0), // 16-bit input: P-side auxiliary analog input // CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs .CONVST(1'b0), // 1-bit input: Convert start input .CONVSTCLK(1'b0), // 1-bit input: Convert start input .RESET(1'b0), // 1-bit input: Active-high reset // Dedicated Analog Input Pair: 1-bit (each) input: VP/VN .VN(1'b0), // 1-bit input: N-side analog input .VP(1'b0), // 1-bit input: P-side analog input // Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports .DADDR(7'b0), // 7-bit input: DRP address bus .DCLK(xadc_clk), // 1-bit input: DRP clock .DEN(xadc_den), // 1-bit input: DRP enable signal .DI(16'b0), // 16-bit input: DRP input data bus .DWE(1'b0) // 1-bit input: DRP write enable ); // End of XADC_inst instantiation end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : mig_7series_v2_3_tempmon.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Jul 25 2012 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Monitors chip temperature via the XADC and adjusts the // stage 2 tap values as appropriate. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_tempmon # ( parameter TCQ = 100, // Register delay (sim only) parameter TEMP_MON_CONTROL = "INTERNAL", // XADC or user temperature source parameter XADC_CLK_PERIOD = 5000, // pS (default to 200 MHz refclk) parameter tTEMPSAMPLE = 10000000 // ps (10 us) ) ( input clk, // Fabric clock input xadc_clk, input rst, // System reset input [11:0] device_temp_i, // User device temperature output [11:0] device_temp // Sampled temperature ); //*************************************************************************** // Function cdiv // Description: // This function performs ceiling division (divide and round-up) // Inputs: // num: integer to be divided // div: divisor // Outputs: // cdiv: result of ceiling division (num/div, rounded up) //*************************************************************************** function integer cdiv (input integer num, input integer div); begin // perform division, then add 1 if and only if remainder is non-zero cdiv = (num/div) + (((num%div)>0) ? 1 : 0); end endfunction // cdiv //*************************************************************************** // Function clogb2 // Description: // This function performs binary logarithm and rounds up // Inputs: // size: integer to perform binary log upon // Outputs: // clogb2: result of binary logarithm, rounded up //*************************************************************************** function integer clogb2 (input integer size); begin size = size - 1; // increment clogb2 from 1 for each bit in size for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1) size = size >> 1; end endfunction // clogb2 // Synchronization registers (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r1; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r2; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r3 /* synthesis syn_srlstyle="registers" */; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r4; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r5; // Output register (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_r; wire [11:0] device_temp_lcl; reg [3:0] sync_cntr = 4'b0000; reg device_temp_sync_r4_neq_r3; // (* ASYNC_REG = "TRUE" *) reg rst_r1; // (* ASYNC_REG = "TRUE" *) reg rst_r2; // // Synchronization rst to XADC clock domain // always @(posedge xadc_clk) begin // rst_r1 <= rst; // rst_r2 <= rst_r1; // end // Synchronization counter always @(posedge clk) begin device_temp_sync_r1 <= #TCQ device_temp_lcl; device_temp_sync_r2 <= #TCQ device_temp_sync_r1; device_temp_sync_r3 <= #TCQ device_temp_sync_r2; device_temp_sync_r4 <= #TCQ device_temp_sync_r3; device_temp_sync_r5 <= #TCQ device_temp_sync_r4; device_temp_sync_r4_neq_r3 <= #TCQ (device_temp_sync_r4 != device_temp_sync_r3) ? 1'b1 : 1'b0; end always @(posedge clk) if(rst || (device_temp_sync_r4_neq_r3)) sync_cntr <= #TCQ 4'b0000; else if(~&sync_cntr) sync_cntr <= #TCQ sync_cntr + 4'b0001; always @(posedge clk) if(&sync_cntr) device_temp_r <= #TCQ device_temp_sync_r5; assign device_temp = device_temp_r; generate if(TEMP_MON_CONTROL == "EXTERNAL") begin : user_supplied_temperature assign device_temp_lcl = device_temp_i; end else begin : xadc_supplied_temperature // calculate polling timer width and limit localparam nTEMPSAMP = cdiv(tTEMPSAMPLE, XADC_CLK_PERIOD); localparam nTEMPSAMP_CLKS = nTEMPSAMP; localparam nTEMPSAMP_CLKS_M6 = nTEMPSAMP - 6; localparam nTEMPSAMP_CNTR_WIDTH = clogb2(nTEMPSAMP_CLKS); // Temperature sampler FSM encoding localparam INIT_IDLE = 2'b00; localparam REQUEST_READ_TEMP = 2'b01; localparam WAIT_FOR_READ = 2'b10; localparam READ = 2'b11; // polling timer and tick reg [nTEMPSAMP_CNTR_WIDTH-1:0] sample_timer = {nTEMPSAMP_CNTR_WIDTH{1'b0}}; reg sample_timer_en = 1'b0; reg sample_timer_clr = 1'b0; reg sample_en = 1'b0; // Temperature sampler state reg [2:0] tempmon_state = INIT_IDLE; reg [2:0] tempmon_next_state = INIT_IDLE; // XADC interfacing reg xadc_den = 1'b0; wire xadc_drdy; wire [15:0] xadc_do; reg xadc_drdy_r = 1'b0; reg [15:0] xadc_do_r = 1'b0; // Temperature storage reg [11:0] temperature = 12'b0; // Reset sync (* ASYNC_REG = "TRUE" *) reg rst_r1; (* ASYNC_REG = "TRUE" *) reg rst_r2; // Synchronization rst to XADC clock domain always @(posedge xadc_clk) begin rst_r1 <= rst; rst_r2 <= rst_r1; end // XADC polling interval timer always @ (posedge xadc_clk) if(rst_r2 || sample_timer_clr) sample_timer <= #TCQ {nTEMPSAMP_CNTR_WIDTH{1'b0}}; else if(sample_timer_en) sample_timer <= #TCQ sample_timer + 1'b1; // XADC sampler state transition always @(posedge xadc_clk) if(rst_r2) tempmon_state <= #TCQ INIT_IDLE; else tempmon_state <= #TCQ tempmon_next_state; // Sample enable always @(posedge xadc_clk) sample_en <= #TCQ (sample_timer == nTEMPSAMP_CLKS_M6) ? 1'b1 : 1'b0; // XADC sampler next state transition always @(tempmon_state or sample_en or xadc_drdy_r) begin tempmon_next_state = tempmon_state; case(tempmon_state) INIT_IDLE: if(sample_en) tempmon_next_state = REQUEST_READ_TEMP; REQUEST_READ_TEMP: tempmon_next_state = WAIT_FOR_READ; WAIT_FOR_READ: if(xadc_drdy_r) tempmon_next_state = READ; READ: tempmon_next_state = INIT_IDLE; default: tempmon_next_state = INIT_IDLE; endcase end // Sample timer clear always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) sample_timer_clr <= #TCQ 1'b0; else if(tempmon_state == REQUEST_READ_TEMP) sample_timer_clr <= #TCQ 1'b1; // Sample timer enable always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == REQUEST_READ_TEMP)) sample_timer_en <= #TCQ 1'b0; else if((tempmon_state == INIT_IDLE) || (tempmon_state == READ)) sample_timer_en <= #TCQ 1'b1; // XADC enable always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) xadc_den <= #TCQ 1'b0; else if(tempmon_state == REQUEST_READ_TEMP) xadc_den <= #TCQ 1'b1; // Register XADC outputs always @(posedge xadc_clk) if(rst_r2) begin xadc_drdy_r <= #TCQ 1'b0; xadc_do_r <= #TCQ 16'b0; end else begin xadc_drdy_r <= #TCQ xadc_drdy; xadc_do_r <= #TCQ xadc_do; end // Store current read value always @(posedge xadc_clk) if(rst_r2) temperature <= #TCQ 12'b0; else if(tempmon_state == READ) temperature <= #TCQ xadc_do_r[15:4]; assign device_temp_lcl = temperature; // XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter // 7 Series // Xilinx HDL Libraries Guide, version 14.1 XADC #( // INIT_40 - INIT_42: XADC configuration registers .INIT_40(16'h1000), // config reg 0 .INIT_41(16'h2fff), // config reg 1 .INIT_42(16'h0800), // config reg 2 // INIT_48 - INIT_4F: Sequence Registers .INIT_48(16'h0101), // Sequencer channel selection .INIT_49(16'h0000), // Sequencer channel selection .INIT_4A(16'h0100), // Sequencer Average selection .INIT_4B(16'h0000), // Sequencer Average selection .INIT_4C(16'h0000), // Sequencer Bipolar selection .INIT_4D(16'h0000), // Sequencer Bipolar selection .INIT_4E(16'h0000), // Sequencer Acq time selection .INIT_4F(16'h0000), // Sequencer Acq time selection // INIT_50 - INIT_58, INIT5C: Alarm Limit Registers .INIT_50(16'hb5ed), // Temp alarm trigger .INIT_51(16'h57e4), // Vccint upper alarm limit .INIT_52(16'ha147), // Vccaux upper alarm limit .INIT_53(16'hca33), // Temp alarm OT upper .INIT_54(16'ha93a), // Temp alarm reset .INIT_55(16'h52c6), // Vccint lower alarm limit .INIT_56(16'h9555), // Vccaux lower alarm limit .INIT_57(16'hae4e), // Temp alarm OT reset .INIT_58(16'h5999), // VBRAM upper alarm limit .INIT_5C(16'h5111), // VBRAM lower alarm limit // Simulation attributes: Set for proepr simulation behavior .SIM_DEVICE("7SERIES") // Select target device (values) ) XADC_inst ( // ALARMS: 8-bit (each) output: ALM, OT .ALM(), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram .OT(), // 1-bit output: Over-Temperature alarm // Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports .DO(xadc_do), // 16-bit output: DRP output data bus .DRDY(xadc_drdy), // 1-bit output: DRP data ready // STATUS: 1-bit (each) output: XADC status ports .BUSY(), // 1-bit output: ADC busy output .CHANNEL(), // 5-bit output: Channel selection outputs .EOC(), // 1-bit output: End of Conversion .EOS(), // 1-bit output: End of Sequence .JTAGBUSY(), // 1-bit output: JTAG DRP transaction in progress output .JTAGLOCKED(), // 1-bit output: JTAG requested DRP port lock .JTAGMODIFIED(), // 1-bit output: JTAG Write to the DRP has occurred .MUXADDR(), // 5-bit output: External MUX channel decode // Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0] .VAUXN(16'b0), // 16-bit input: N-side auxiliary analog input .VAUXP(16'b0), // 16-bit input: P-side auxiliary analog input // CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs .CONVST(1'b0), // 1-bit input: Convert start input .CONVSTCLK(1'b0), // 1-bit input: Convert start input .RESET(1'b0), // 1-bit input: Active-high reset // Dedicated Analog Input Pair: 1-bit (each) input: VP/VN .VN(1'b0), // 1-bit input: N-side analog input .VP(1'b0), // 1-bit input: P-side analog input // Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports .DADDR(7'b0), // 7-bit input: DRP address bus .DCLK(xadc_clk), // 1-bit input: DRP clock .DEN(xadc_den), // 1-bit input: DRP enable signal .DI(16'b0), // 16-bit input: DRP input data bus .DWE(1'b0) // 1-bit input: DRP write enable ); // End of XADC_inst instantiation end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : mig_7series_v2_3_tempmon.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Jul 25 2012 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Monitors chip temperature via the XADC and adjusts the // stage 2 tap values as appropriate. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_tempmon # ( parameter TCQ = 100, // Register delay (sim only) parameter TEMP_MON_CONTROL = "INTERNAL", // XADC or user temperature source parameter XADC_CLK_PERIOD = 5000, // pS (default to 200 MHz refclk) parameter tTEMPSAMPLE = 10000000 // ps (10 us) ) ( input clk, // Fabric clock input xadc_clk, input rst, // System reset input [11:0] device_temp_i, // User device temperature output [11:0] device_temp // Sampled temperature ); //*************************************************************************** // Function cdiv // Description: // This function performs ceiling division (divide and round-up) // Inputs: // num: integer to be divided // div: divisor // Outputs: // cdiv: result of ceiling division (num/div, rounded up) //*************************************************************************** function integer cdiv (input integer num, input integer div); begin // perform division, then add 1 if and only if remainder is non-zero cdiv = (num/div) + (((num%div)>0) ? 1 : 0); end endfunction // cdiv //*************************************************************************** // Function clogb2 // Description: // This function performs binary logarithm and rounds up // Inputs: // size: integer to perform binary log upon // Outputs: // clogb2: result of binary logarithm, rounded up //*************************************************************************** function integer clogb2 (input integer size); begin size = size - 1; // increment clogb2 from 1 for each bit in size for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1) size = size >> 1; end endfunction // clogb2 // Synchronization registers (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r1; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r2; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r3 /* synthesis syn_srlstyle="registers" */; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r4; (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r5; // Output register (* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_r; wire [11:0] device_temp_lcl; reg [3:0] sync_cntr = 4'b0000; reg device_temp_sync_r4_neq_r3; // (* ASYNC_REG = "TRUE" *) reg rst_r1; // (* ASYNC_REG = "TRUE" *) reg rst_r2; // // Synchronization rst to XADC clock domain // always @(posedge xadc_clk) begin // rst_r1 <= rst; // rst_r2 <= rst_r1; // end // Synchronization counter always @(posedge clk) begin device_temp_sync_r1 <= #TCQ device_temp_lcl; device_temp_sync_r2 <= #TCQ device_temp_sync_r1; device_temp_sync_r3 <= #TCQ device_temp_sync_r2; device_temp_sync_r4 <= #TCQ device_temp_sync_r3; device_temp_sync_r5 <= #TCQ device_temp_sync_r4; device_temp_sync_r4_neq_r3 <= #TCQ (device_temp_sync_r4 != device_temp_sync_r3) ? 1'b1 : 1'b0; end always @(posedge clk) if(rst || (device_temp_sync_r4_neq_r3)) sync_cntr <= #TCQ 4'b0000; else if(~&sync_cntr) sync_cntr <= #TCQ sync_cntr + 4'b0001; always @(posedge clk) if(&sync_cntr) device_temp_r <= #TCQ device_temp_sync_r5; assign device_temp = device_temp_r; generate if(TEMP_MON_CONTROL == "EXTERNAL") begin : user_supplied_temperature assign device_temp_lcl = device_temp_i; end else begin : xadc_supplied_temperature // calculate polling timer width and limit localparam nTEMPSAMP = cdiv(tTEMPSAMPLE, XADC_CLK_PERIOD); localparam nTEMPSAMP_CLKS = nTEMPSAMP; localparam nTEMPSAMP_CLKS_M6 = nTEMPSAMP - 6; localparam nTEMPSAMP_CNTR_WIDTH = clogb2(nTEMPSAMP_CLKS); // Temperature sampler FSM encoding localparam INIT_IDLE = 2'b00; localparam REQUEST_READ_TEMP = 2'b01; localparam WAIT_FOR_READ = 2'b10; localparam READ = 2'b11; // polling timer and tick reg [nTEMPSAMP_CNTR_WIDTH-1:0] sample_timer = {nTEMPSAMP_CNTR_WIDTH{1'b0}}; reg sample_timer_en = 1'b0; reg sample_timer_clr = 1'b0; reg sample_en = 1'b0; // Temperature sampler state reg [2:0] tempmon_state = INIT_IDLE; reg [2:0] tempmon_next_state = INIT_IDLE; // XADC interfacing reg xadc_den = 1'b0; wire xadc_drdy; wire [15:0] xadc_do; reg xadc_drdy_r = 1'b0; reg [15:0] xadc_do_r = 1'b0; // Temperature storage reg [11:0] temperature = 12'b0; // Reset sync (* ASYNC_REG = "TRUE" *) reg rst_r1; (* ASYNC_REG = "TRUE" *) reg rst_r2; // Synchronization rst to XADC clock domain always @(posedge xadc_clk) begin rst_r1 <= rst; rst_r2 <= rst_r1; end // XADC polling interval timer always @ (posedge xadc_clk) if(rst_r2 || sample_timer_clr) sample_timer <= #TCQ {nTEMPSAMP_CNTR_WIDTH{1'b0}}; else if(sample_timer_en) sample_timer <= #TCQ sample_timer + 1'b1; // XADC sampler state transition always @(posedge xadc_clk) if(rst_r2) tempmon_state <= #TCQ INIT_IDLE; else tempmon_state <= #TCQ tempmon_next_state; // Sample enable always @(posedge xadc_clk) sample_en <= #TCQ (sample_timer == nTEMPSAMP_CLKS_M6) ? 1'b1 : 1'b0; // XADC sampler next state transition always @(tempmon_state or sample_en or xadc_drdy_r) begin tempmon_next_state = tempmon_state; case(tempmon_state) INIT_IDLE: if(sample_en) tempmon_next_state = REQUEST_READ_TEMP; REQUEST_READ_TEMP: tempmon_next_state = WAIT_FOR_READ; WAIT_FOR_READ: if(xadc_drdy_r) tempmon_next_state = READ; READ: tempmon_next_state = INIT_IDLE; default: tempmon_next_state = INIT_IDLE; endcase end // Sample timer clear always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) sample_timer_clr <= #TCQ 1'b0; else if(tempmon_state == REQUEST_READ_TEMP) sample_timer_clr <= #TCQ 1'b1; // Sample timer enable always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == REQUEST_READ_TEMP)) sample_timer_en <= #TCQ 1'b0; else if((tempmon_state == INIT_IDLE) || (tempmon_state == READ)) sample_timer_en <= #TCQ 1'b1; // XADC enable always @(posedge xadc_clk) if(rst_r2 || (tempmon_state == WAIT_FOR_READ)) xadc_den <= #TCQ 1'b0; else if(tempmon_state == REQUEST_READ_TEMP) xadc_den <= #TCQ 1'b1; // Register XADC outputs always @(posedge xadc_clk) if(rst_r2) begin xadc_drdy_r <= #TCQ 1'b0; xadc_do_r <= #TCQ 16'b0; end else begin xadc_drdy_r <= #TCQ xadc_drdy; xadc_do_r <= #TCQ xadc_do; end // Store current read value always @(posedge xadc_clk) if(rst_r2) temperature <= #TCQ 12'b0; else if(tempmon_state == READ) temperature <= #TCQ xadc_do_r[15:4]; assign device_temp_lcl = temperature; // XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter // 7 Series // Xilinx HDL Libraries Guide, version 14.1 XADC #( // INIT_40 - INIT_42: XADC configuration registers .INIT_40(16'h1000), // config reg 0 .INIT_41(16'h2fff), // config reg 1 .INIT_42(16'h0800), // config reg 2 // INIT_48 - INIT_4F: Sequence Registers .INIT_48(16'h0101), // Sequencer channel selection .INIT_49(16'h0000), // Sequencer channel selection .INIT_4A(16'h0100), // Sequencer Average selection .INIT_4B(16'h0000), // Sequencer Average selection .INIT_4C(16'h0000), // Sequencer Bipolar selection .INIT_4D(16'h0000), // Sequencer Bipolar selection .INIT_4E(16'h0000), // Sequencer Acq time selection .INIT_4F(16'h0000), // Sequencer Acq time selection // INIT_50 - INIT_58, INIT5C: Alarm Limit Registers .INIT_50(16'hb5ed), // Temp alarm trigger .INIT_51(16'h57e4), // Vccint upper alarm limit .INIT_52(16'ha147), // Vccaux upper alarm limit .INIT_53(16'hca33), // Temp alarm OT upper .INIT_54(16'ha93a), // Temp alarm reset .INIT_55(16'h52c6), // Vccint lower alarm limit .INIT_56(16'h9555), // Vccaux lower alarm limit .INIT_57(16'hae4e), // Temp alarm OT reset .INIT_58(16'h5999), // VBRAM upper alarm limit .INIT_5C(16'h5111), // VBRAM lower alarm limit // Simulation attributes: Set for proepr simulation behavior .SIM_DEVICE("7SERIES") // Select target device (values) ) XADC_inst ( // ALARMS: 8-bit (each) output: ALM, OT .ALM(), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram .OT(), // 1-bit output: Over-Temperature alarm // Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports .DO(xadc_do), // 16-bit output: DRP output data bus .DRDY(xadc_drdy), // 1-bit output: DRP data ready // STATUS: 1-bit (each) output: XADC status ports .BUSY(), // 1-bit output: ADC busy output .CHANNEL(), // 5-bit output: Channel selection outputs .EOC(), // 1-bit output: End of Conversion .EOS(), // 1-bit output: End of Sequence .JTAGBUSY(), // 1-bit output: JTAG DRP transaction in progress output .JTAGLOCKED(), // 1-bit output: JTAG requested DRP port lock .JTAGMODIFIED(), // 1-bit output: JTAG Write to the DRP has occurred .MUXADDR(), // 5-bit output: External MUX channel decode // Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0] .VAUXN(16'b0), // 16-bit input: N-side auxiliary analog input .VAUXP(16'b0), // 16-bit input: P-side auxiliary analog input // CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs .CONVST(1'b0), // 1-bit input: Convert start input .CONVSTCLK(1'b0), // 1-bit input: Convert start input .RESET(1'b0), // 1-bit input: Active-high reset // Dedicated Analog Input Pair: 1-bit (each) input: VP/VN .VN(1'b0), // 1-bit input: N-side analog input .VP(1'b0), // 1-bit input: P-side analog input // Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports .DADDR(7'b0), // 7-bit input: DRP address bus .DCLK(xadc_clk), // 1-bit input: DRP clock .DEN(xadc_den), // 1-bit input: DRP enable signal .DI(16'b0), // 16-bit input: DRP input data bus .DWE(1'b0) // 1-bit input: DRP write enable ); // End of XADC_inst instantiation end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_init.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Memory initialization and overall master state control during // initialization and calibration. Specifically, the following functions // are performed: // 1. Memory initialization (initial AR, mode register programming, etc.) // 2. Initiating write leveling // 3. Generate training pattern writes for read leveling. Generate // memory readback for read leveling. // This module has an interface for providing control/address and write // data to the PHY Control Block during initialization/calibration. // Once initialization and calibration are complete, control is passed to the MC. // //Reference: //Revision History: // //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_init.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ **$Date: 2011/06/02 08:35:09 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_init.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_init # ( parameter tCK = 1500, // DDRx SDRAM clock period parameter TCQ = 100, parameter nCK_PER_CLK = 4, // # of memory clocks per CLK parameter CLK_PERIOD = 3000, // Logic (internal) clk period (in ps) parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA // 1 - ODT output from FPGA parameter DDR3_VDD_OP_VOLT = "150", // Voltage mode used for DDR3 // 150 - 1.50 V // 135 - 1.35 V // 125 - 1.25 V parameter VREF = "EXTERNAL", // Internal or external Vref parameter PRBS_WIDTH = 8, // PRBS sequence = 2^PRBS_WIDTH parameter BANK_WIDTH = 2, parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank parameter COL_WIDTH = 10, parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for // component I/F with CS_WIDTH=1, // nCS_PER_RANK=# of components parameter DQ_WIDTH = 64, parameter DQS_WIDTH = 8, parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter ROW_WIDTH = 14, parameter CS_WIDTH = 1, parameter RANKS = 1, // # of memory ranks in the interface parameter CKE_WIDTH = 1, // # of cke outputs parameter DRAM_TYPE = "DDR3", parameter REG_CTRL = "ON", parameter ADDR_CMD_MODE= "1T", // calibration Address parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address parameter CALIB_COL_ADD = 12'h000, // Calibration column address parameter CALIB_BA_ADD = 3'h0, // Calibration bank address // DRAM mode settings parameter AL = "0", // Additive Latency option parameter BURST_MODE = "8", // Burst length parameter BURST_TYPE = "SEQ", // Burst type // parameter nAL = 0, // Additive latency (in clk cyc) parameter nCL = 5, // Read CAS latency (in clk cyc) parameter nCWL = 5, // Write CAS latency (in clk cyc) parameter tRFC = 110000, // Refresh-to-command delay (in ps) parameter REFRESH_TIMER = 1553, // Refresh interval in fabrci cycles between 8 posted refreshes parameter REFRESH_TIMER_WIDTH = 8, parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option parameter RTT_NOM = "60", // Nominal ODT termination value parameter RTT_WR = "60", // Write ODT termination value parameter WRLVL = "ON", // Enable write leveling // parameter PHASE_DETECT = "ON", // Enable read phase detector parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter nSLOTS = 1, // Number of DIMM SLOTs in the system parameter SIM_INIT_OPTION = "NONE", // "NONE", "SKIP_PU_DLY", "SKIP_INIT" parameter SIM_CAL_OPTION = "NONE", // "NONE", "FAST_CAL", "SKIP_CAL" parameter CKE_ODT_AUX = "FALSE", parameter PRE_REV3ES = "OFF", // Enable TG error detection during calibration parameter TEST_AL = "0", // Internal use for ICM verification parameter FIXED_VICTIM = "TRUE", parameter BYPASS_COMPLEX_OCAL = "FALSE" ) ( input clk, input rst, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o, input delay_incdec_done, input ck_addr_cmd_delay_done, input pi_phase_locked_all, input pi_dqs_found_done, input dqsfound_retry, input dqs_found_prech_req, output reg pi_phaselock_start, output pi_phase_locked_err, output pi_calib_done, input phy_if_empty, // Read/write calibration interface input wrlvl_done, input wrlvl_rank_done, input wrlvl_byte_done, input wrlvl_byte_redo, input wrlvl_final, output reg wrlvl_final_if_rst, input oclkdelay_calib_done, input oclk_prech_req, input oclk_calib_resume, input lim_done, input lim_wr_req, output reg oclkdelay_calib_start, //complex oclkdelay calibration input complex_oclkdelay_calib_done, input complex_oclk_prech_req, input complex_oclk_calib_resume, output reg complex_oclkdelay_calib_start, input [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt, // same as oclkdelay_calib_cnt output reg complex_ocal_num_samples_inc, input complex_ocal_num_samples_done_r, input [2:0] complex_ocal_rd_victim_sel, output reg complex_ocal_reset_rd_addr, input complex_ocal_ref_req, output reg complex_ocal_ref_done, input done_dqs_tap_inc, input [5:0] rd_data_offset_0, input [5:0] rd_data_offset_1, input [5:0] rd_data_offset_2, input [6*RANKS-1:0] rd_data_offset_ranks_0, input [6*RANKS-1:0] rd_data_offset_ranks_1, input [6*RANKS-1:0] rd_data_offset_ranks_2, input pi_dqs_found_rank_done, input wrcal_done, input wrcal_prech_req, input wrcal_read_req, input wrcal_act_req, input temp_wrcal_done, input [7:0] slot_0_present, input [7:0] slot_1_present, output reg wl_sm_start, output reg wr_lvl_start, output reg wrcal_start, output reg wrcal_rd_wait, output reg wrcal_sanity_chk, output reg tg_timer_done, output reg no_rst_tg_mc, input rdlvl_stg1_done, input rdlvl_stg1_rank_done, output reg rdlvl_stg1_start, output reg pi_dqs_found_start, output reg detect_pi_found_dqs, // rdlvl stage 1 precharge requested after each DQS input rdlvl_prech_req, input rdlvl_last_byte_done, input wrcal_resume, input wrcal_sanity_chk_done, // MPR read leveling input mpr_rdlvl_done, input mpr_rnk_done, input mpr_last_byte_done, output reg mpr_rdlvl_start, output reg mpr_end_if_reset, // PRBS Read Leveling input prbs_rdlvl_done, input prbs_last_byte_done, input prbs_rdlvl_prech_req, input complex_victim_inc, input [2:0] rd_victim_sel, input [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt, output reg [2:0] victim_sel, output reg [DQS_CNT_WIDTH:0]victim_byte_cnt, output reg prbs_rdlvl_start, output reg prbs_gen_clk_en, output reg prbs_gen_oclk_clk_en, output reg complex_sample_cnt_inc, output reg complex_sample_cnt_inc_ocal, output reg complex_wr_done, // Signals shared btw multiple calibration stages output reg prech_done, // Data select / status output reg init_calib_complete, // Signal to mask memory model error for Invalid latching edge output reg calib_writes, // PHY address/control // 2 commands to PHY Control Block per div 2 clock in 2:1 mode // 4 commands to PHY Control Block per div 4 clock in 4:1 mode output reg [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address, output reg [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank, output reg [nCK_PER_CLK-1:0] phy_ras_n, output reg [nCK_PER_CLK-1:0] phy_cas_n, output reg [nCK_PER_CLK-1:0] phy_we_n, output reg phy_reset_n, output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n, // Hard PHY Interface signals input phy_ctl_ready, input phy_ctl_full, input phy_cmd_full, input phy_data_full, output reg calib_ctl_wren, output reg calib_cmd_wren, output reg [1:0] calib_seq, output reg write_calib, output reg read_calib, // PHY_Ctl_Wd output reg [2:0] calib_cmd, // calib_aux_out used for CKE and ODT output reg [3:0] calib_aux_out, output reg [1:0] calib_odt , output reg [nCK_PER_CLK-1:0] calib_cke , output [1:0] calib_rank_cnt, output reg [1:0] calib_cas_slot, output reg [5:0] calib_data_offset_0, output reg [5:0] calib_data_offset_1, output reg [5:0] calib_data_offset_2, // PHY OUT_FIFO output reg calib_wrdata_en, output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata, // PHY Read output phy_rddata_en, output phy_rddata_valid, output [255:0] dbg_phy_init, input read_pause, input reset_rd_addr, //OCAL centering calibration input oclkdelay_center_calib_start, input oclk_center_write_resume, input oclkdelay_center_calib_done ); //***************************************************************************** // Assertions to be added //***************************************************************************** // The phy_ctl_full signal must never be asserted in synchronous mode of // operation either 4:1 or 2:1 // // The RANKS parameter must never be set to '0' by the user // valid values: 1 to 4 // //***************************************************************************** //*************************************************************************** // Number of Read level stage 1 writes limited to a SDRAM row // The address of Read Level stage 1 reads must also be limited // to a single SDRAM row // (2^COL_WIDTH)/BURST_MODE = (2^10)/8 = 128 localparam NUM_STG1_WR_RD = (BURST_MODE == "8") ? 4 : (BURST_MODE == "4") ? 8 : 4; localparam ADDR_INC = (BURST_MODE == "8") ? 8 : (BURST_MODE == "4") ? 4 : 8; // In a 2 slot dual rank per system RTT_NOM values // for Rank2 and Rank3 default to 40 ohms localparam RTT_NOM2 = "40"; localparam RTT_NOM3 = "40"; localparam RTT_NOM_int = (USE_ODT_PORT == 1) ? RTT_NOM : RTT_WR; // Specifically for use with half-frequency controller (nCK_PER_CLK=2) // = 1 if burst length = 4, = 0 if burst length = 8. Determines how // often row command needs to be issued during read-leveling // For DDR3 the burst length is fixed during calibration localparam BURST4_FLAG = (DRAM_TYPE == "DDR3")? 1'b0 : (BURST_MODE == "8") ? 1'b0 : ((BURST_MODE == "4") ? 1'b1 : 1'b0); //*************************************************************************** // Counter values used to determine bus timing // NOTE on all counter terminal counts - these can/should be one less than // the actual delay to take into account extra clock cycle delay in // generating the corresponding "done" signal //*************************************************************************** localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK; // Calculate initial delay required in number of CLK clock cycles // to delay initially. The counter is clocked by [CLK/1024] - which // is approximately division by 1000 - note that the formulas below will // result in more than the minimum wait time because of this approximation. // NOTE: For DDR3 JEDEC specifies to delay reset // by 200us, and CKE by an additional 500us after power-up // For DDR2 CKE is delayed by 200us after power up. localparam DDR3_RESET_DELAY_NS = 200000; localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS; localparam DDR2_CKE_DELAY_NS = 200000; localparam PWRON_RESET_DELAY_CNT = ((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD); localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == "DDR3") ? (((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) : (((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)); // FOR DDR2 -1 taken out. With -1 not getting 200us. The equation // needs to be reworked. localparam DDR2_INIT_PRE_DELAY_PS = 400000; localparam DDR2_INIT_PRE_CNT = ((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1; // Calculate tXPR time: reset from CKE HIGH to valid command after power-up // tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock // cycles because this counter actually starts up before CKE is asserted // to memory. localparam TXPR_DELAY_CNT = (5*CLK_MEM_PERIOD > tRFC+10000) ? (((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+11 : (((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+11; // tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV localparam TDLLK_TZQINIT_DELAY_CNT = 255; // TWR values in ns. Both DDR2 and DDR3 have the same value. // 15000ns/tCK localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ? (15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD; // time to wait between consecutive commands in PHY_INIT - this is a // generic number, and must be large enough to account for worst case // timing parameter (tRFC - refresh-to-active) across all memory speed // grades and operating frequencies. Expressed in clk // (Divided by 4 or Divided by 2) clock cycles. localparam CNTNEXT_CMD = 7'b1111111; // Counter values to keep track of which MR register to load during init // Set value of INIT_CNT_MR_DONE to equal value of counter for last mode // register configured during initialization. // NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init localparam INIT_CNT_MR2 = 2'b00; localparam INIT_CNT_MR3 = 2'b01; localparam INIT_CNT_MR1 = 2'b10; localparam INIT_CNT_MR0 = 2'b11; localparam INIT_CNT_MR_DONE = 2'b11; // Register chip programmable values for DDR3 // The register chip for the registered DIMM needs to be programmed // before the initialization of the registered DIMM. // Address for the control word is in : DBA2, DA2, DA1, DA0 // Data for the control word is in: DBA1 DBA0, DA4, DA3 // The values will be stored in the local param in the following format // {DBA[2:0], DA[4:0]} // RC0 is global features control word. Address == 000 localparam REG_RC0 = 8'b00000000; // RC1 Clock driver enable control word. Enables or disables the four // output clocks in the register chip. For single rank and dual rank // two clocks will be enabled and for quad rank all the four clocks // will be enabled. Address == 000. Data = 0110 for single and dual rank. // = 0000 for quad rank localparam REG_RC1 = 8'b00000001; // RC2 timing control word. Set in 1T timing mode // Address = 010. Data = 0000 localparam REG_RC2 = 8'b00000010; // RC3 timing control word. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC3 = (RANKS >= 2) ? 8'b00101011 : 8'b00000011; // RC4 timing control work. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC4 = (RANKS >= 2) ? 8'b00101100 : 8'b00000100; // RC5 timing control work. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC5 = (RANKS >= 2) ? 8'b00101101 : 8'b00000101; // RC10 timing control work. Setting the data to 0000 localparam [3:0] FREQUENCY_ENCODING = (tCK >= 1072 && tCK < 1250) ? 4'b0100 : (tCK >= 1250 && tCK < 1500) ? 4'b0011 : (tCK >= 1500 && tCK < 1875) ? 4'b0010 : (tCK >= 1875 && tCK < 2500) ? 4'b0001 : 4'b0000; localparam REG_RC10 = {1'b1,FREQUENCY_ENCODING,3'b010}; localparam VREF_ENCODING = (VREF == "INTERNAL") ? 1'b1 : 1'b0; localparam [3:0] DDR3_VOLTAGE_ENCODING = (DDR3_VDD_OP_VOLT == "125") ? {1'b0,VREF_ENCODING,2'b10} : (DDR3_VDD_OP_VOLT == "135") ? {1'b0,VREF_ENCODING,2'b01} : {1'b0,VREF_ENCODING,2'b00} ; localparam REG_RC11 = {1'b1,DDR3_VOLTAGE_ENCODING,3'b011}; // For non-zero AL values localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; // Adding the register dimm latency to write latency localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; // Count value to generate pi_phase_locked_err signal localparam PHASELOCKED_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 16383 : 1000; // Timeout interval for detecting error with Traffic Generator localparam [13:0] TG_TIMER_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 14'h3FFF : 14'h0001; //bit num per DQS localparam DQ_PER_DQS = DQ_WIDTH/DQS_WIDTH; //COMPLEX_ROW_CNT_BYTE localparam COMPLEX_ROW_CNT_BYTE = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS*2: 2; localparam COMPLEX_RD = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS : 1; // Master state machine encoding localparam INIT_IDLE = 7'b0000000; //0 localparam INIT_WAIT_CKE_EXIT = 7'b0000001; //1 localparam INIT_LOAD_MR = 7'b0000010; //2 localparam INIT_LOAD_MR_WAIT = 7'b0000011; //3 localparam INIT_ZQCL = 7'b0000100; //4 localparam INIT_WAIT_DLLK_ZQINIT = 7'b0000101; //5 localparam INIT_WRLVL_START = 7'b0000110; //6 localparam INIT_WRLVL_WAIT = 7'b0000111; //7 localparam INIT_WRLVL_LOAD_MR = 7'b0001000; //8 localparam INIT_WRLVL_LOAD_MR_WAIT = 7'b0001001; //9 localparam INIT_WRLVL_LOAD_MR2 = 7'b0001010; //A localparam INIT_WRLVL_LOAD_MR2_WAIT = 7'b0001011; //B localparam INIT_RDLVL_ACT = 7'b0001100; //C localparam INIT_RDLVL_ACT_WAIT = 7'b0001101; //D localparam INIT_RDLVL_STG1_WRITE = 7'b0001110; //E localparam INIT_RDLVL_STG1_WRITE_READ = 7'b0001111; //F localparam INIT_RDLVL_STG1_READ = 7'b0010000; //10 localparam INIT_RDLVL_STG2_READ = 7'b0010001; //11 localparam INIT_RDLVL_STG2_READ_WAIT = 7'b0010010; //12 localparam INIT_PRECHARGE_PREWAIT = 7'b0010011; //13 localparam INIT_PRECHARGE = 7'b0010100; //14 localparam INIT_PRECHARGE_WAIT = 7'b0010101; //15 localparam INIT_DONE = 7'b0010110; //16 localparam INIT_DDR2_PRECHARGE = 7'b0010111; //17 localparam INIT_DDR2_PRECHARGE_WAIT = 7'b0011000; //18 localparam INIT_REFRESH = 7'b0011001; //19 localparam INIT_REFRESH_WAIT = 7'b0011010; //1A localparam INIT_REG_WRITE = 7'b0011011; //1B localparam INIT_REG_WRITE_WAIT = 7'b0011100; //1C localparam INIT_DDR2_MULTI_RANK = 7'b0011101; //1D localparam INIT_DDR2_MULTI_RANK_WAIT = 7'b0011110; //1E localparam INIT_WRCAL_ACT = 7'b0011111; //1F localparam INIT_WRCAL_ACT_WAIT = 7'b0100000; //20 localparam INIT_WRCAL_WRITE = 7'b0100001; //21 localparam INIT_WRCAL_WRITE_READ = 7'b0100010; //22 localparam INIT_WRCAL_READ = 7'b0100011; //23 localparam INIT_WRCAL_READ_WAIT = 7'b0100100; //24 localparam INIT_WRCAL_MULT_READS = 7'b0100101; //25 localparam INIT_PI_PHASELOCK_READS = 7'b0100110; //26 localparam INIT_MPR_RDEN = 7'b0100111; //27 localparam INIT_MPR_WAIT = 7'b0101000; //28 localparam INIT_MPR_READ = 7'b0101001; //29 localparam INIT_MPR_DISABLE_PREWAIT = 7'b0101010; //2A localparam INIT_MPR_DISABLE = 7'b0101011; //2B localparam INIT_MPR_DISABLE_WAIT = 7'b0101100; //2C localparam INIT_OCLKDELAY_ACT = 7'b0101101; //2D localparam INIT_OCLKDELAY_ACT_WAIT = 7'b0101110; //2E localparam INIT_OCLKDELAY_WRITE = 7'b0101111; //2F localparam INIT_OCLKDELAY_WRITE_WAIT = 7'b0110000; //30 localparam INIT_OCLKDELAY_READ = 7'b0110001; //31 localparam INIT_OCLKDELAY_READ_WAIT = 7'b0110010; //32 localparam INIT_REFRESH_RNK2_WAIT = 7'b0110011; //33 localparam INIT_RDLVL_COMPLEX_PRECHARGE = 7'b0110100; //34 localparam INIT_RDLVL_COMPLEX_PRECHARGE_WAIT = 7'b0110101; //35 localparam INIT_RDLVL_COMPLEX_ACT = 7'b0110110; //36 localparam INIT_RDLVL_COMPLEX_ACT_WAIT = 7'b0110111; //37 localparam INIT_RDLVL_COMPLEX_READ = 7'b0111000; //38 localparam INIT_RDLVL_COMPLEX_READ_WAIT = 7'b0111001; //39 localparam INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT = 7'b0111010; //3A localparam INIT_OCAL_COMPLEX_ACT = 7'b0111011; //3B localparam INIT_OCAL_COMPLEX_ACT_WAIT = 7'b0111100; //3C localparam INIT_OCAL_COMPLEX_WRITE_WAIT = 7'b0111101; //3D localparam INIT_OCAL_COMPLEX_RESUME_WAIT = 7'b0111110; //3E localparam INIT_OCAL_CENTER_ACT = 7'b0111111; //3F localparam INIT_OCAL_CENTER_WRITE = 7'b1000000; //40 localparam INIT_OCAL_CENTER_WRITE_WAIT = 7'b1000001; //41 localparam INIT_OCAL_CENTER_ACT_WAIT = 7'b1000010; //42 integer i, j, k, l, m, n, p, q; reg pi_dqs_found_all_r; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r1; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r2; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r3; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r4; reg pi_calib_rank_done_r; reg [13:0] pi_phaselock_timer; reg stg1_wr_done; reg rnk_ref_cnt; reg pi_dqs_found_done_r1; reg pi_dqs_found_rank_done_r; reg read_calib_int; reg read_calib_r; reg pi_calib_done_r; reg pi_calib_done_r1; reg burst_addr_r; reg [1:0] chip_cnt_r; reg [6:0] cnt_cmd_r; reg cnt_cmd_done_r; reg cnt_cmd_done_m7_r; reg [7:0] cnt_dllk_zqinit_r; reg cnt_dllk_zqinit_done_r; reg cnt_init_af_done_r; reg [1:0] cnt_init_af_r; reg [1:0] cnt_init_data_r; reg [1:0] cnt_init_mr_r; reg cnt_init_mr_done_r; reg cnt_init_pre_wait_done_r; reg [7:0] cnt_init_pre_wait_r; reg [9:0] cnt_pwron_ce_r; reg cnt_pwron_cke_done_r; reg cnt_pwron_cke_done_r1; reg [8:0] cnt_pwron_r; reg cnt_pwron_reset_done_r; reg cnt_txpr_done_r; reg [7:0] cnt_txpr_r; reg ddr2_pre_flag_r; reg ddr2_refresh_flag_r; reg ddr3_lm_done_r; reg [4:0] enable_wrlvl_cnt; reg init_complete_r; reg init_complete_r1; reg init_complete_r2; (* keep = "true" *) reg init_complete_r_timing; (* keep = "true" *) reg init_complete_r1_timing; reg [6:0] init_next_state; reg [6:0] init_state_r; reg [6:0] init_state_r1; wire [15:0] load_mr0; wire [15:0] load_mr1; wire [15:0] load_mr2; wire [15:0] load_mr3; reg mem_init_done_r; reg [1:0] mr2_r [0:3]; reg [2:0] mr1_r [0:3]; reg new_burst_r; reg [15:0] wrcal_start_dly_r; wire wrcal_start_pre; reg wrcal_resume_r; // Only one ODT signal per rank in PHY Control Block reg [nCK_PER_CLK-1:0] phy_tmp_odt_r; reg [nCK_PER_CLK-1:0] phy_tmp_odt_r1; reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r; reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_int_cs_n; wire prech_done_pre; reg [15:0] prech_done_dly_r; reg prech_pending_r; reg prech_req_posedge_r; reg prech_req_r; reg pwron_ce_r; reg first_rdlvl_pat_r; reg first_wrcal_pat_r; reg phy_wrdata_en; reg phy_wrdata_en_r1; reg [1:0] wrdata_pat_cnt; reg [1:0] wrcal_pat_cnt; reg [ROW_WIDTH-1:0] address_w; reg [BANK_WIDTH-1:0] bank_w; reg rdlvl_stg1_done_r1; reg rdlvl_stg1_start_int; reg [15:0] rdlvl_start_dly0_r; reg rdlvl_start_pre; reg rdlvl_last_byte_done_r; wire rdlvl_rd; wire rdlvl_wr; reg rdlvl_wr_r; wire rdlvl_wr_rd; reg [3:0] reg_ctrl_cnt_r; reg [1:0] tmp_mr2_r [0:3]; reg [2:0] tmp_mr1_r [0:3]; reg wrlvl_done_r; reg wrlvl_done_r1; reg wrlvl_rank_done_r1; reg wrlvl_rank_done_r2; reg wrlvl_rank_done_r3; reg wrlvl_rank_done_r4; reg wrlvl_rank_done_r5; reg wrlvl_rank_done_r6; reg wrlvl_rank_done_r7; reg [2:0] wrlvl_rank_cntr; reg wrlvl_odt_ctl; reg wrlvl_odt; reg wrlvl_active; reg wrlvl_active_r1; reg [2:0] num_reads; reg temp_wrcal_done_r; reg temp_lmr_done; reg extend_cal_pat; reg [13:0] tg_timer; reg tg_timer_go; reg cnt_wrcal_rd; reg [3:0] cnt_wait; reg [7:0] wrcal_reads; reg [8:0] stg1_wr_rd_cnt; reg phy_data_full_r; reg wr_level_dqs_asrt; reg wr_level_dqs_asrt_r1; reg [1:0] dqs_asrt_cnt; reg [3:0] num_refresh; wire oclkdelay_calib_start_pre; reg [15:0] oclkdelay_start_dly_r; reg [3:0] oclk_wr_cnt; reg [3:0] wrcal_wr_cnt; reg wrlvl_final_r; reg prbs_rdlvl_done_r1; reg prbs_rdlvl_done_r2; reg prbs_rdlvl_done_r3; reg prbs_last_byte_done_r; reg phy_if_empty_r; reg prbs_pat_resume_int; reg complex_row0_wr_done; reg complex_row1_wr_done; reg complex_row0_rd_done; reg complex_row1_rd_done; reg complex_row0_rd_done_r1; reg [3:0] complex_wait_cnt; reg [3:0] complex_num_reads; reg [3:0] complex_num_reads_dec; reg [ROW_WIDTH-1:0] complex_address; reg wr_victim_inc; reg [2:0] wr_victim_sel; reg [DQS_CNT_WIDTH:0] wr_byte_cnt; reg [7:0] complex_row_cnt; reg complex_sample_cnt_inc_r1; reg complex_sample_cnt_inc_r2; reg complex_odt_ext; reg complex_ocal_odt_ext; reg wrcal_final_chk; wire prech_req; reg read_pause_r1; reg read_pause_r2; wire read_pause_ext; reg reset_rd_addr_r1; reg complex_rdlvl_int_ref_req; reg ext_int_ref_req; //complex OCLK delay calibration reg [7:0] complex_row_cnt_ocal; reg [4:0] complex_num_writes; reg [4:0] complex_num_writes_dec; reg complex_oclkdelay_calib_start_int; reg complex_oclkdelay_calib_start_r1; reg complex_oclkdelay_calib_start_r2; reg complex_oclkdelay_calib_done_r1; // reg [DQS_CNT_WIDTH:0] wr_byte_cnt_ocal; reg [2:0] wr_victim_sel_ocal; reg complex_row1_rd_done_r1; //time for switch to write reg [2:0] complex_row1_rd_cnt; //row1 read number for the byte (8 (16 rows) row1) reg complex_byte_rd_done; //read for the byte is done reg complex_byte_rd_done_r1; // reg complex_row_change; //every 16 rows of read, it is set to "0" for write reg ocal_num_samples_inc; //1 read/write is done reg complex_ocal_wr_start; //indicate complex ocal write is started. used for prbs rd addr gen reg prbs_rdlvl_done_pulse; //rising edge for prbs_rdlvl_done. used for pipelining reg prech_done_r1, prech_done_r2, prech_done_r3; reg mask_lim_done; reg complex_mask_lim_done; reg oclkdelay_calib_start_int; reg [REFRESH_TIMER_WIDTH-1:0] oclkdelay_ref_cnt; reg oclkdelay_int_ref_req; reg [3:0] ocal_act_wait_cnt; reg oclk_calib_resume_level; reg ocal_last_byte_done; wire mmcm_wr; //MMCM centering write. no CS will be set wire exit_ocal_complex_resume_wait = init_state_r == INIT_OCAL_COMPLEX_RESUME_WAIT && complex_oclk_calib_resume; //*************************************************************************** // Debug //*************************************************************************** //synthesis translate_off always @(posedge mem_init_done_r) begin if (!rst) $display ("PHY_INIT: Memory Initialization completed at %t", $time); end always @(posedge wrlvl_done) begin if (!rst && (WRLVL == "ON")) $display ("PHY_INIT: Write Leveling completed at %t", $time); end always @(posedge rdlvl_stg1_done) begin if (!rst) $display ("PHY_INIT: Read Leveling Stage 1 completed at %t", $time); end always @(posedge mpr_rdlvl_done) begin if (!rst) $display ("PHY_INIT: MPR Read Leveling completed at %t", $time); end always @(posedge oclkdelay_calib_done) begin if (!rst) $display ("PHY_INIT: OCLKDELAY calibration completed at %t", $time); end always @(posedge pi_calib_done_r1) begin if (!rst) $display ("PHY_INIT: Phaser_In Phase Locked at %t", $time); end always @(posedge pi_dqs_found_done) begin if (!rst) $display ("PHY_INIT: Phaser_In DQSFOUND completed at %t", $time); end always @(posedge wrcal_done) begin if (!rst && (WRLVL == "ON")) $display ("PHY_INIT: Write Calibration completed at %t", $time); end always@(posedge prbs_rdlvl_done)begin if(!rst) $display("PHY_INIT : PRBS/PER_BIT calibration completed at %t",$time); end always@(posedge complex_oclkdelay_calib_done)begin if(!rst) $display("PHY_INIT : COMPLEX OCLKDELAY calibration completed at %t",$time); end always@(posedge oclkdelay_center_calib_done)begin if(!rst) $display("PHY_INIT : OCLKDELAY CENTER CALIB calibration completed at %t",$time); end //synthesis translate_on assign dbg_phy_init[5:0] = init_state_r; assign dbg_phy_init[6+:8] = complex_row_cnt; assign dbg_phy_init[14+:3] = victim_sel; assign dbg_phy_init[17+:4] = victim_byte_cnt; assign dbg_phy_init[21+:9] = stg1_wr_rd_cnt[8:0]; assign dbg_phy_init[30+:15] = complex_address; assign dbg_phy_init[(30+15)+:15] = phy_address[14:0]; assign dbg_phy_init[60] =prbs_rdlvl_prech_req ; assign dbg_phy_init[61] =prech_req_posedge_r ; //*************************************************************************** // DQS count to be sent to hard PHY during Phaser_IN Phase Locking stage //*************************************************************************** // assign pi_phaselock_calib_cnt = dqs_cnt_r; assign pi_calib_done = pi_calib_done_r1; assign read_pause_ext = read_pause | read_pause_r2; //detect rising edge of prbs_rdlvl_done to reset all control sighals always @ (posedge clk) begin prbs_rdlvl_done_pulse <= #TCQ prbs_rdlvl_done & ~prbs_rdlvl_done_r1; end always @ (posedge clk) begin read_pause_r1 <= #TCQ read_pause; read_pause_r2 <= #TCQ read_pause_r1; end always @(posedge clk) begin if (rst) wrcal_final_chk <= #TCQ 1'b0; else if ((init_next_state == INIT_WRCAL_ACT) && wrcal_done && (DRAM_TYPE == "DDR3")) wrcal_final_chk <= #TCQ 1'b1; end always @(posedge clk) begin rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done; prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done; prbs_rdlvl_done_r2 <= #TCQ prbs_rdlvl_done_r1; prbs_rdlvl_done_r3 <= #TCQ prbs_rdlvl_done_r2; wrcal_resume_r <= #TCQ wrcal_resume; wrcal_sanity_chk <= #TCQ wrcal_final_chk; end always @(posedge clk) begin if (rst) mpr_end_if_reset <= #TCQ 1'b0; else if (mpr_last_byte_done && (num_refresh != 'd0)) mpr_end_if_reset <= #TCQ 1'b1; else mpr_end_if_reset <= #TCQ 1'b0; end // Siganl to mask memory model error for Invalid latching edge always @(posedge clk) if (rst) calib_writes <= #TCQ 1'b0; else if ((init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ)) calib_writes <= #TCQ 1'b1; else calib_writes <= #TCQ 1'b0; always @(posedge clk) if (rst) wrcal_rd_wait <= #TCQ 1'b0; else if (init_state_r == INIT_WRCAL_READ_WAIT) wrcal_rd_wait <= #TCQ 1'b1; else wrcal_rd_wait <= #TCQ 1'b0; //*************************************************************************** // Signal PHY completion when calibration is finished // Signal assertion is delayed by four clock cycles to account for the // multi cycle path constraint to (phy_init_data_sel) signal. //*************************************************************************** always @(posedge clk) if (rst) begin init_complete_r <= #TCQ 1'b0; init_complete_r_timing <= #TCQ 1'b0; init_complete_r1 <= #TCQ 1'b0; init_complete_r1_timing <= #TCQ 1'b0; init_complete_r2 <= #TCQ 1'b0; init_calib_complete <= #TCQ 1'b0; end else begin if (init_state_r == INIT_DONE) begin init_complete_r <= #TCQ 1'b1; init_complete_r_timing <= #TCQ 1'b1; end init_complete_r1 <= #TCQ init_complete_r; init_complete_r1_timing <= #TCQ init_complete_r_timing; init_complete_r2 <= #TCQ init_complete_r1; init_calib_complete <= #TCQ init_complete_r2; end always @ (posedge clk) if (rst) complex_oclkdelay_calib_done_r1 <= #TCQ 1'b0; else complex_oclkdelay_calib_done_r1 <= #TCQ complex_oclkdelay_calib_done; //reset read address for starting complex ocaldealy calib always @ (posedge clk) begin complex_ocal_reset_rd_addr <= #TCQ ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd9)) || (prbs_last_byte_done && ~prbs_last_byte_done_r); end //first write for complex oclkdealy calib always @ (posedge clk) begin if (rst) complex_ocal_wr_start <= #TCQ 'b0; else complex_ocal_wr_start <= #TCQ complex_ocal_reset_rd_addr? 1'b1 : complex_ocal_wr_start; end //ocal stg3 centering start // always @ (posedge clk) // if(rst) oclkdelay_center_calib_start <= #TCQ 1'b0; // else // oclkdelay_center_calib_start <= #TCQ ((init_state_r == INIT_OCAL_CENTER_ACT) && lim_done)? 1'b1: oclkdelay_center_calib_start; //*************************************************************************** // Instantiate FF for the phy_init_data_sel signal. A multi cycle path // constraint will be assigned to this signal. This signal will only be // used within the PHY //*************************************************************************** // FDRSE u_ff_phy_init_data_sel // ( // .Q (phy_init_data_sel), // .C (clk), // .CE (1'b1), // .D (init_complete_r), // .R (1'b0), // .S (1'b0) // ) /* synthesis syn_preserve=1 */ // /* synthesis syn_replicate = 0 */; //*************************************************************************** // Mode register programming //*************************************************************************** //***************************************************************** // DDR3 Load mode reg0 // Mode Register (MR0): // [15:13] - unused - 000 // [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit), // 1 (DLL maintained) // [11:9] - write recovery for Auto Precharge (tWR/tCK = 6) // [8] - DLL reset - 0 or 1 // [7] - Test Mode - 0 (normal) // [6:4],[2] - CAS latency - CAS_LAT // [3] - Burst Type - BURST_TYPE // [1:0] - Burst Length - BURST_LEN // DDR2 Load mode register // Mode Register (MR): // [15:14] - unused - 00 // [13] - reserved - 0 // [12] - Power-down mode - 0 (normal) // [11:9] - write recovery - write recovery for Auto Precharge // (tWR/tCK = 6) // [8] - DLL reset - 0 or 1 // [7] - Test Mode - 0 (normal) // [6:4] - CAS latency - CAS_LAT // [3] - Burst Type - BURST_TYPE // [2:0] - Burst Length - BURST_LEN //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr0_DDR3 assign load_mr0[1:0] = (BURST_MODE == "8") ? 2'b00 : (BURST_MODE == "OTF") ? 2'b01 : (BURST_MODE == "4") ? 2'b10 : 2'b11; assign load_mr0[2] = (nCL >= 12) ? 1'b1 : 1'b0; // LSb of CAS latency assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; assign load_mr0[6:4] = ((nCL == 5) || (nCL == 13)) ? 3'b001 : ((nCL == 6) || (nCL == 14)) ? 3'b010 : (nCL == 7) ? 3'b011 : (nCL == 8) ? 3'b100 : (nCL == 9) ? 3'b101 : (nCL == 10) ? 3'b110 : (nCL == 11) ? 3'b111 : (nCL == 12) ? 3'b000 : 3'b111; assign load_mr0[7] = 1'b0; assign load_mr0[8] = 1'b1; // Reset DLL (init only) assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 : (TWR_CYC == 6) ? 3'b010 : (TWR_CYC == 7) ? 3'b011 : (TWR_CYC == 8) ? 3'b100 : (TWR_CYC == 9) ? 3'b101 : (TWR_CYC == 10) ? 3'b101 : (TWR_CYC == 11) ? 3'b110 : (TWR_CYC == 12) ? 3'b110 : (TWR_CYC == 13) ? 3'b111 : (TWR_CYC == 14) ? 3'b111 : (TWR_CYC == 15) ? 3'b000 : (TWR_CYC == 16) ? 3'b000 : 3'b010; assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit' assign load_mr0[15:13] = 3'b000; end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr0_DDR2 // block: gen assign load_mr0[2:0] = (BURST_MODE == "8") ? 3'b011 : (BURST_MODE == "4") ? 3'b010 : 3'b111; assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; assign load_mr0[6:4] = (nCL == 3) ? 3'b011 : (nCL == 4) ? 3'b100 : (nCL == 5) ? 3'b101 : (nCL == 6) ? 3'b110 : 3'b111; assign load_mr0[7] = 1'b0; assign load_mr0[8] = 1'b1; // Reset DLL (init only) assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 : (TWR_CYC == 3) ? 3'b010 : (TWR_CYC == 4) ? 3'b011 : (TWR_CYC == 5) ? 3'b100 : (TWR_CYC == 6) ? 3'b101 : 3'b010; assign load_mr0[15:12]= 4'b0000; // Reserved end endgenerate //***************************************************************** // DDR3 Load mode reg1 // Mode Register (MR1): // [15:13] - unused - 00 // [12] - output enable - 0 (enabled for DQ, DQS, DQS#) // [11] - TDQS enable - 0 (TDQS disabled and DM enabled) // [10] - reserved - 0 (must be '0') // [9] - RTT[2] - 0 // [8] - reserved - 0 (must be '0') // [7] - write leveling - 0 (disabled), 1 (enabled) // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) // [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7) // [4:3] - Additive CAS - ADDITIVE_CAS // [2] - RTT[0] // [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7) // [0] - DLL enable - 0 (normal) // DDR2 ext mode register // Extended Mode Register (MR): // [15:14] - unused - 00 // [13] - reserved - 0 // [12] - output enable - 0 (enabled) // [11] - RDQS enable - 0 (disabled) // [10] - DQS# enable - 0 (enabled) // [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init) // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) // [5:3] - Additive CAS - ADDITIVE_CAS // [2] - RTT[0] // [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced) // [0] - DLL enable - 0 (normal) //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr1_DDR3 assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b0 : 1'b1; assign load_mr1[2] = ((RTT_NOM_int == "30") || (RTT_NOM_int == "40") || (RTT_NOM_int == "60")) ? 1'b1 : 1'b0; assign load_mr1[4:3] = (AL == "0") ? 2'b00 : (AL == "CL-1") ? 2'b01 : (AL == "CL-2") ? 2'b10 : 2'b11; assign load_mr1[5] = 1'b0; assign load_mr1[6] = ((RTT_NOM_int == "40") || (RTT_NOM_int == "120")) ? 1'b1 : 1'b0; assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence assign load_mr1[8] = 1'b0; assign load_mr1[9] = ((RTT_NOM_int == "20") || (RTT_NOM_int == "30")) ? 1'b1 : 1'b0; assign load_mr1[10] = 1'b0; assign load_mr1[15:11] = 5'b00000; end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr1_DDR2 assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b1 : 1'b0; assign load_mr1[2] = ((RTT_NOM_int == "75") || (RTT_NOM_int == "50")) ? 1'b1 : 1'b0; assign load_mr1[5:3] = (AL == "0") ? 3'b000 : (AL == "1") ? 3'b001 : (AL == "2") ? 3'b010 : (AL == "3") ? 3'b011 : (AL == "4") ? 3'b100 : 3'b111; assign load_mr1[6] = ((RTT_NOM_int == "50") || (RTT_NOM_int == "150")) ? 1'b1 : 1'b0; assign load_mr1[9:7] = 3'b000; assign load_mr1[10] = (DDR2_DQSN_ENABLE == "YES") ? 1'b0 : 1'b1; assign load_mr1[15:11] = 5'b00000; end endgenerate //***************************************************************** // DDR3 Load mode reg2 // Mode Register (MR2): // [15:11] - unused - 00 // [10:9] - RTT_WR - 00 (Dynamic ODT off) // [8] - reserved - 0 (must be '0') // [7] - self-refresh temperature range - // 0 (normal), 1 (extended) // [6] - Auto Self-Refresh - 0 (manual), 1(auto) // [5:3] - CAS Write Latency (CWL) - // 000 (5 for 400 MHz device), // 001 (6 for 400 MHz to 533 MHz devices), // 010 (7 for 533 MHz to 667 MHz devices), // 011 (8 for 667 MHz to 800 MHz) // [2:0] - Partial Array Self-Refresh (Optional) - // 000 (full array) // Not used for DDR2 //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr2_DDR3 assign load_mr2[2:0] = 3'b000; assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 : (nCWL == 6) ? 3'b001 : (nCWL == 7) ? 3'b010 : (nCWL == 8) ? 3'b011 : (nCWL == 9) ? 3'b100 : (nCWL == 10) ? 3'b101 : (nCWL == 11) ? 3'b110 : 3'b111; assign load_mr2[6] = 1'b0; assign load_mr2[7] = 1'b0; assign load_mr2[8] = 1'b0; // Dynamic ODT disabled assign load_mr2[10:9] = 2'b00; assign load_mr2[15:11] = 5'b00000; end else begin: gen_load_mr2_DDR2 assign load_mr2[15:0] = 16'd0; end endgenerate //***************************************************************** // DDR3 Load mode reg3 // Mode Register (MR3): // [15:3] - unused - All zeros // [2] - MPR Operation - 0(normal operation), 1(data flow from MPR) // [1:0] - MPR location - 00 (Predefined pattern) //***************************************************************** assign load_mr3[1:0] = 2'b00; assign load_mr3[2] = 1'b0; assign load_mr3[15:3] = 13'b0000000000000; // For multi-rank systems the rank being accessed during writes in // Read Leveling must be sent to phy_write for the bitslip logic assign calib_rank_cnt = chip_cnt_r; //*************************************************************************** // Logic to begin initial calibration, and to handle precharge requests // during read-leveling (to avoid tRAS violations if individual read // levelling calibration stages take more than max{tRAS) to complete). //*************************************************************************** // Assert when readback for each stage of read-leveling begins. However, // note this indicates only when the read command is issued and when // Phaser_IN has phase aligned FREQ_REF clock to read DQS. It does not // indicate when the read data is present on the bus (when this happens // after the read command is issued depends on CAS LATENCY) - there will // need to be some delay before valid data is present on the bus. // assign rdlvl_start_pre = (init_state_r == INIT_PI_PHASELOCK_READS); // Assert when read back for oclkdelay calibration begins assign oclkdelay_calib_start_pre = (init_state_r == INIT_OCAL_CENTER_ACT); //(init_state_r == INIT_OCLKDELAY_READ); // Assert when read back for write calibration begins assign wrcal_start_pre = (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS); // Common precharge signal done signal - pulses only when there has been // a precharge issued as a result of a PRECH_REQ pulse. Note also a common // PRECH_DONE signal is used for all blocks assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || ((rdlvl_last_byte_done_r || prbs_last_byte_done_r) && (init_state_r == INIT_RDLVL_ACT_WAIT) && cnt_cmd_done_r) || (dqs_found_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || (init_state_r == INIT_MPR_RDEN) || ((init_state_r == INIT_WRCAL_ACT_WAIT) && cnt_cmd_done_r) || (init_state_r == INIT_OCAL_CENTER_ACT) || ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && complex_oclkdelay_calib_start_r1) || ((init_state_r == INIT_OCLKDELAY_ACT_WAIT) && cnt_cmd_done_r) || ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) && prbs_last_byte_done_r) || //prbs_rdlvl_done (wrlvl_final && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r && ~oclkdelay_calib_done)) && prech_pending_r && !prech_req_posedge_r); always @(posedge clk) if (rst) pi_phaselock_start <= #TCQ 1'b0; else if (init_state_r == INIT_PI_PHASELOCK_READS) pi_phaselock_start <= #TCQ 1'b1; // Delay start of each calibration by 16 clock cycles to ensure that when // calibration logic begins, read data is already appearing on the bus. // Each circuit should synthesize using an SRL16. Assume that reset is // long enough to clear contents of SRL16. always @(posedge clk) begin rdlvl_last_byte_done_r <= #TCQ rdlvl_last_byte_done; prbs_last_byte_done_r <= #TCQ prbs_last_byte_done; rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0], rdlvl_start_pre}; wrcal_start_dly_r <= #TCQ {wrcal_start_dly_r[14:0], wrcal_start_pre}; oclkdelay_start_dly_r <= #TCQ {oclkdelay_start_dly_r[14:0], oclkdelay_calib_start_pre}; prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0], prech_done_pre}; end always @(posedge clk) if (rst) oclkdelay_calib_start_int <= #TCQ 1'b0; else if (oclkdelay_start_dly_r[5]) oclkdelay_calib_start_int <= #TCQ 1'b1; always @(posedge clk) begin if (rst) ocal_last_byte_done <= #TCQ 1'b0; else if ((complex_oclkdelay_calib_cnt == DQS_WIDTH-1) && oclkdelay_center_calib_done) ocal_last_byte_done <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || (init_state_r == INIT_REFRESH) || prbs_rdlvl_done || ocal_last_byte_done || oclkdelay_center_calib_done) oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; else if (oclkdelay_calib_start_int) begin if (oclkdelay_ref_cnt > 'd0) oclkdelay_ref_cnt <= #TCQ oclkdelay_ref_cnt - 1; else oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; end end always @(posedge clk) begin if (rst || (init_state_r == INIT_OCAL_CENTER_ACT) || oclkdelay_calib_done || ocal_last_byte_done || oclkdelay_center_calib_done) oclkdelay_int_ref_req <= #TCQ 1'b0; else if (oclkdelay_ref_cnt == 'd1) oclkdelay_int_ref_req <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) ocal_act_wait_cnt <= #TCQ 'd0; else if ((init_state_r == INIT_OCAL_CENTER_ACT_WAIT) && ocal_act_wait_cnt < 'd15) ocal_act_wait_cnt <= #TCQ ocal_act_wait_cnt + 1; else ocal_act_wait_cnt <= #TCQ 'd0; end always @(posedge clk) begin if (rst || (init_state_r == INIT_OCLKDELAY_READ)) oclk_calib_resume_level <= #TCQ 1'b0; else if (oclk_calib_resume) oclk_calib_resume_level <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_ACT_WAIT) || prbs_rdlvl_done) complex_rdlvl_int_ref_req <= #TCQ 1'b0; else if (oclkdelay_ref_cnt == 'd1) // complex_rdlvl_int_ref_req <= #TCQ 1'b1; complex_rdlvl_int_ref_req <= #TCQ 1'b0; //temporary fix for read issue end always @(posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_COMPLEX_READ)) ext_int_ref_req <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_ACT_WAIT) && complex_rdlvl_int_ref_req) ext_int_ref_req <= #TCQ 1'b1; end always @(posedge clk) begin prech_done <= #TCQ prech_done_dly_r[15]; prech_done_r1 <= #TCQ prech_done_dly_r[15]; prech_done_r2 <= #TCQ prech_done_r1; prech_done_r3 <= #TCQ prech_done_r2; end always @(posedge clk) if (rst) mpr_rdlvl_start <= #TCQ 1'b0; else if (pi_dqs_found_done && (init_state_r == INIT_MPR_READ)) mpr_rdlvl_start <= #TCQ 1'b1; always @(posedge clk) phy_if_empty_r <= #TCQ phy_if_empty; always @(posedge clk) if (rst || ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || prbs_rdlvl_done) prbs_gen_clk_en <= #TCQ 1'b0; else if ((~phy_if_empty_r && rdlvl_stg1_done_r1 && ~prbs_rdlvl_done) || ((init_state_r == INIT_RDLVL_ACT_WAIT) && rdlvl_stg1_done_r1 && (cnt_cmd_r == 'd127)) || ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && rdlvl_stg1_done_r1 && (complex_wait_cnt == 'd14)) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || ((init_state_r == INIT_PRECHARGE_PREWAIT) && prbs_rdlvl_start)) prbs_gen_clk_en <= #TCQ 1'b1; //Enable for complex oclkdelay - used in prbs gen always @(posedge clk) if (rst || ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || complex_oclkdelay_calib_done || (complex_wait_cnt == 'd15 && complex_num_writes == 1 && complex_ocal_wr_start) || ( init_state_r == INIT_RDLVL_STG1_WRITE && complex_num_writes_dec == 'd2) || ~complex_ocal_wr_start || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT ) || (init_state_r != INIT_OCAL_COMPLEX_RESUME_WAIT && init_state_r1 == INIT_OCAL_COMPLEX_RESUME_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_ACT)) prbs_gen_oclk_clk_en <= #TCQ 1'b0; else if ((~phy_if_empty_r && ~complex_oclkdelay_calib_done && prbs_rdlvl_done_r1) || // changed for new algo 3/26 ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd14)) || ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14)) || exit_ocal_complex_resume_wait || ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && ~stg1_wr_done && ~complex_row1_wr_done && ~complex_ocal_num_samples_done_r && (complex_wait_cnt == 'd14)) || (init_state_r == INIT_RDLVL_COMPLEX_READ) ) prbs_gen_oclk_clk_en <= #TCQ 1'b1; generate if (RANKS < 2) begin always @(posedge clk) if (rst) begin rdlvl_stg1_start <= #TCQ 1'b0; rdlvl_stg1_start_int <= #TCQ 1'b0; rdlvl_start_pre <= #TCQ 1'b0; prbs_rdlvl_start <= #TCQ 1'b0; end else begin if (pi_dqs_found_done && cnt_cmd_done_r && (init_state_r == INIT_RDLVL_ACT_WAIT)) rdlvl_stg1_start_int <= #TCQ 1'b1; if (pi_dqs_found_done && (init_state_r == INIT_RDLVL_STG1_READ))begin rdlvl_start_pre <= #TCQ 1'b1; rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; end if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_READ) && (WRLVL == "ON")) begin prbs_rdlvl_start <= #TCQ 1'b1; end end end else begin always @(posedge clk) if (rst || rdlvl_stg1_rank_done) begin rdlvl_stg1_start <= #TCQ 1'b0; rdlvl_stg1_start_int <= #TCQ 1'b0; rdlvl_start_pre <= #TCQ 1'b0; prbs_rdlvl_start <= #TCQ 1'b0; end else begin if (pi_dqs_found_done && cnt_cmd_done_r && (init_state_r == INIT_RDLVL_ACT_WAIT)) rdlvl_stg1_start_int <= #TCQ 1'b1; if (pi_dqs_found_done && (init_state_r == INIT_RDLVL_STG1_READ))begin rdlvl_start_pre <= #TCQ 1'b1; rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; end if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_READ) && (WRLVL == "ON")) begin prbs_rdlvl_start <= #TCQ 1'b1; end end end endgenerate always @(posedge clk) begin if (rst || dqsfound_retry || wrlvl_byte_redo) begin pi_dqs_found_start <= #TCQ 1'b0; wrcal_start <= #TCQ 1'b0; end else begin if (!pi_dqs_found_done && init_state_r == INIT_RDLVL_STG2_READ) pi_dqs_found_start <= #TCQ 1'b1; if (wrcal_start_dly_r[5]) wrcal_start <= #TCQ 1'b1; end end // else: !if(rst) always @(posedge clk) if (rst) oclkdelay_calib_start <= #TCQ 1'b0; else if (oclkdelay_start_dly_r[5]) oclkdelay_calib_start <= #TCQ 1'b1; always @(posedge clk) if (rst) pi_dqs_found_done_r1 <= #TCQ 1'b0; else pi_dqs_found_done_r1 <= #TCQ pi_dqs_found_done; always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final; // Reset IN_FIFO after final write leveling to make sure the FIFO // pointers are initialized always @(posedge clk) if (rst || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_REFRESH)) wrlvl_final_if_rst <= #TCQ 1'b0; else if (wrlvl_done_r && //(wrlvl_final_r && wrlvl_done_r && (init_state_r == INIT_WRLVL_LOAD_MR2)) wrlvl_final_if_rst <= #TCQ 1'b1; // Constantly enable DQS while write leveling is enabled in the memory // This is more to get rid of warnings in simulation, can later change // this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted always @(posedge clk) if (rst || ((init_state_r1 != INIT_WRLVL_START) && (init_state_r == INIT_WRLVL_START))) wrlvl_odt_ctl <= #TCQ 1'b0; else if (wrlvl_rank_done && ~wrlvl_rank_done_r1) wrlvl_odt_ctl <= #TCQ 1'b1; generate if (nCK_PER_CLK == 4) begin: en_cnt_div4 always @ (posedge clk) if (rst) enable_wrlvl_cnt <= #TCQ 5'd0; else if ((init_state_r == INIT_WRLVL_START) || (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) enable_wrlvl_cnt <= #TCQ 5'd12; else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; // ODT stays asserted as long as write_calib // signal is asserted always @(posedge clk) if (rst || wrlvl_odt_ctl) wrlvl_odt <= #TCQ 1'b0; else if (enable_wrlvl_cnt == 5'd1) wrlvl_odt <= #TCQ 1'b1; end else begin: en_cnt_div2 always @ (posedge clk) if (rst) enable_wrlvl_cnt <= #TCQ 5'd0; else if ((init_state_r == INIT_WRLVL_START) || (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) enable_wrlvl_cnt <= #TCQ 5'd21; else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; // ODT stays asserted as long as write_calib // signal is asserted always @(posedge clk) if (rst || wrlvl_odt_ctl) wrlvl_odt <= #TCQ 1'b0; else if (enable_wrlvl_cnt == 5'd1) wrlvl_odt <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst || wrlvl_rank_done || done_dqs_tap_inc) wrlvl_active <= #TCQ 1'b0; else if ((enable_wrlvl_cnt == 5'd1) && wrlvl_odt && !wrlvl_active) wrlvl_active <= #TCQ 1'b1; // signal used to assert DQS for write leveling. // the DQS will be asserted once every 16 clock cycles. always @(posedge clk)begin if(rst || (enable_wrlvl_cnt != 5'd1)) begin wr_level_dqs_asrt <= #TCQ 1'd0; end else if ((enable_wrlvl_cnt == 5'd1) && (wrlvl_active_r1)) begin wr_level_dqs_asrt <= #TCQ 1'd1; end end always @ (posedge clk) begin if (rst || (wrlvl_done_r && ~wrlvl_done_r1)) dqs_asrt_cnt <= #TCQ 2'd0; else if (wr_level_dqs_asrt && dqs_asrt_cnt != 2'd3) dqs_asrt_cnt <= #TCQ (dqs_asrt_cnt + 1); end always @ (posedge clk) begin if (rst || ~wrlvl_active) wr_lvl_start <= #TCQ 1'd0; else if (dqs_asrt_cnt == 2'd3) wr_lvl_start <= #TCQ 1'd1; end always @(posedge clk) begin if (rst) wl_sm_start <= #TCQ 1'b0; else wl_sm_start <= #TCQ wr_level_dqs_asrt_r1; end always @(posedge clk) begin wrlvl_active_r1 <= #TCQ wrlvl_active; wr_level_dqs_asrt_r1 <= #TCQ wr_level_dqs_asrt; wrlvl_done_r <= #TCQ wrlvl_done; wrlvl_done_r1 <= #TCQ wrlvl_done_r; wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done; wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1; wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2; wrlvl_rank_done_r4 <= #TCQ wrlvl_rank_done_r3; wrlvl_rank_done_r5 <= #TCQ wrlvl_rank_done_r4; wrlvl_rank_done_r6 <= #TCQ wrlvl_rank_done_r5; wrlvl_rank_done_r7 <= #TCQ wrlvl_rank_done_r6; end always @ (posedge clk) begin //if (rst) wrlvl_rank_cntr <= #TCQ 3'd0; //else if (wrlvl_rank_done) // wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1; end //***************************************************************** // Precharge request logic - those calibration logic blocks // that require greater than tRAS(max) to finish must break up // their calibration into smaller units of time, with precharges // issued in between. This is done using the XXX_PRECH_REQ and // PRECH_DONE handshaking between PHY_INIT and those blocks //***************************************************************** // Shared request from multiple sources assign prech_req = oclk_prech_req | rdlvl_prech_req | wrcal_prech_req | prbs_rdlvl_prech_req | (dqs_found_prech_req & (init_state_r == INIT_RDLVL_STG2_READ_WAIT)); // Handshaking logic to force precharge during read leveling, and to // notify read leveling logic when precharge has been initiated and // it's okay to proceed with leveling again always @(posedge clk) if (rst) begin prech_req_r <= #TCQ 1'b0; prech_req_posedge_r <= #TCQ 1'b0; prech_pending_r <= #TCQ 1'b0; end else begin prech_req_r <= #TCQ prech_req; prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r; if (prech_req_posedge_r) prech_pending_r <= #TCQ 1'b1; // Clear after we've finished with the precharge and have // returned to issuing read leveling calibration reads else if (prech_done_pre) prech_pending_r <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || prech_done_r3) mask_lim_done <= #TCQ 1'b0; else if (prech_pending_r) mask_lim_done <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || prbs_rdlvl_done_r3) complex_mask_lim_done <= #TCQ 1'b0; else if (~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) complex_mask_lim_done <= #TCQ 1'b1; end //Complex oclkdelay calibrration //*************************************************************************** // Various timing counters //*************************************************************************** //***************************************************************** // Generic delay for various states that require it (e.g. for turnaround // between read and write). Make this a sufficiently large number of clock // cycles to cover all possible frequencies and memory components) // Requirements for this counter: // 1. Greater than tMRD // 2. tRFC (refresh-active) for DDR2 // 3. (list the other requirements, slacker...) //***************************************************************** always @(posedge clk) begin case (init_state_r) INIT_LOAD_MR_WAIT, INIT_WRLVL_LOAD_MR_WAIT, INIT_WRLVL_LOAD_MR2_WAIT, INIT_MPR_WAIT, INIT_MPR_DISABLE_PREWAIT, INIT_MPR_DISABLE_WAIT, INIT_OCLKDELAY_ACT_WAIT, INIT_OCLKDELAY_WRITE_WAIT, INIT_RDLVL_ACT_WAIT, INIT_RDLVL_STG1_WRITE_READ, INIT_RDLVL_STG2_READ_WAIT, INIT_WRCAL_ACT_WAIT, INIT_WRCAL_WRITE_READ, INIT_WRCAL_READ_WAIT, INIT_PRECHARGE_PREWAIT, INIT_PRECHARGE_WAIT, INIT_DDR2_PRECHARGE_WAIT, INIT_REG_WRITE_WAIT, INIT_REFRESH_WAIT, INIT_REFRESH_RNK2_WAIT: begin if (phy_ctl_full || phy_cmd_full) cnt_cmd_r <= #TCQ cnt_cmd_r; else cnt_cmd_r <= #TCQ cnt_cmd_r + 1; end INIT_WRLVL_WAIT: cnt_cmd_r <= #TCQ 'b0; default: cnt_cmd_r <= #TCQ 'b0; endcase end // pulse when count reaches terminal count always @(posedge clk) cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD); // For ODT deassertion - hold throughout post read/write wait stage, but // deassert before next command. The post read/write stage is very long, so // we simply address the longest case here plus some margin. always @(posedge clk) cnt_cmd_done_m7_r <= #TCQ (cnt_cmd_r == (CNTNEXT_CMD - 7)); //************************************************************************ // Added to support PO fine delay inc when TG errors always @(posedge clk) begin case (init_state_r) INIT_WRCAL_READ_WAIT: begin if (phy_ctl_full || phy_cmd_full) cnt_wait <= #TCQ cnt_wait; else cnt_wait <= #TCQ cnt_wait + 1; end default: cnt_wait <= #TCQ 'b0; endcase end always @(posedge clk) cnt_wrcal_rd <= #TCQ (cnt_wait == 'd4); always @(posedge clk) begin if (rst || ~temp_wrcal_done) temp_lmr_done <= #TCQ 1'b0; else if (temp_wrcal_done && (init_state_r == INIT_LOAD_MR)) temp_lmr_done <= #TCQ 1'b1; end always @(posedge clk) temp_wrcal_done_r <= #TCQ temp_wrcal_done; always @(posedge clk) if (rst) begin tg_timer_go <= #TCQ 1'b0; end else if ((PRE_REV3ES == "ON") && temp_wrcal_done && temp_lmr_done && (init_state_r == INIT_WRCAL_READ_WAIT)) begin tg_timer_go <= #TCQ 1'b1; end else begin tg_timer_go <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || (temp_wrcal_done && ~temp_wrcal_done_r) || (init_state_r == INIT_PRECHARGE_PREWAIT)) tg_timer <= #TCQ 'd0; else if ((pi_phaselock_timer == PHASELOCKED_TIMEOUT) && tg_timer_go && (tg_timer != TG_TIMER_TIMEOUT)) tg_timer <= #TCQ tg_timer + 1; end always @(posedge clk) begin if (rst) tg_timer_done <= #TCQ 1'b0; else if (tg_timer == TG_TIMER_TIMEOUT) tg_timer_done <= #TCQ 1'b1; else tg_timer_done <= #TCQ 1'b0; end always @(posedge clk) begin if (rst) no_rst_tg_mc <= #TCQ 1'b0; else if ((init_state_r == INIT_WRCAL_ACT) && wrcal_read_req) no_rst_tg_mc <= #TCQ 1'b1; else no_rst_tg_mc <= #TCQ 1'b0; end //************************************************************************ always @(posedge clk) begin if (rst) detect_pi_found_dqs <= #TCQ 1'b0; else if ((cnt_cmd_r == 7'b0111111) && (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) detect_pi_found_dqs <= #TCQ 1'b1; else detect_pi_found_dqs <= #TCQ 1'b0; end //***************************************************************** // Initial delay after power-on for RESET, CKE // NOTE: Could reduce power consumption by turning off these counters // after initial power-up (at expense of more logic) // NOTE: Likely can combine multiple counters into single counter //***************************************************************** // Create divided by 1024 version of clock always @(posedge clk) if (rst) begin cnt_pwron_ce_r <= #TCQ 10'h000; pwron_ce_r <= #TCQ 1'b0; end else begin cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1; pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF); end // "Main" power-on counter - ticks every CLKDIV/1024 cycles always @(posedge clk) if (rst) cnt_pwron_r <= #TCQ 'b0; else if (pwron_ce_r) cnt_pwron_r <= #TCQ cnt_pwron_r + 1; always @(posedge clk) if (rst || ~phy_ctl_ready) begin cnt_pwron_reset_done_r <= #TCQ 1'b0; cnt_pwron_cke_done_r <= #TCQ 1'b0; end else begin // skip power-up count for simulation purposes only if ((SIM_INIT_OPTION == "SKIP_PU_DLY") || (SIM_INIT_OPTION == "SKIP_INIT")) begin cnt_pwron_reset_done_r <= #TCQ 1'b1; cnt_pwron_cke_done_r <= #TCQ 1'b1; end else begin // otherwise, create latched version of done signal for RESET, CKE if (DRAM_TYPE == "DDR3") begin if (!cnt_pwron_reset_done_r) cnt_pwron_reset_done_r <= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT); if (!cnt_pwron_cke_done_r) cnt_pwron_cke_done_r <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); end else begin // DDR2 cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed if (!cnt_pwron_cke_done_r) cnt_pwron_cke_done_r <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); end end end // else: !if(rst || ~phy_ctl_ready) always @(posedge clk) cnt_pwron_cke_done_r1 <= #TCQ cnt_pwron_cke_done_r; // Keep RESET asserted and CKE deasserted until after power-on delay always @(posedge clk or posedge rst) begin if (rst) phy_reset_n <= #TCQ 1'b0; else phy_reset_n <= #TCQ cnt_pwron_reset_done_r; // phy_cke <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}}; end //***************************************************************** // Counter for tXPR (pronouned "Tax-Payer") - wait time after // CKE deassertion before first MRS command can be asserted //***************************************************************** always @(posedge clk) if (!cnt_pwron_cke_done_r) begin cnt_txpr_r <= #TCQ 'b0; cnt_txpr_done_r <= #TCQ 1'b0; end else begin cnt_txpr_r <= #TCQ cnt_txpr_r + 1; if (!cnt_txpr_done_r) cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT); end //***************************************************************** // Counter for the initial 400ns wait for issuing precharge all // command after CKE assertion. Only for DDR2. //***************************************************************** always @(posedge clk) if (!cnt_pwron_cke_done_r) begin cnt_init_pre_wait_r <= #TCQ 'b0; cnt_init_pre_wait_done_r <= #TCQ 1'b0; end else begin cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1; if (!cnt_init_pre_wait_done_r) cnt_init_pre_wait_done_r <= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT); end //***************************************************************** // Wait for both DLL to lock (tDLLK) and ZQ calibration to finish // (tZQINIT). Both take the same amount of time (512*tCK) //***************************************************************** always @(posedge clk) if (init_state_r == INIT_ZQCL) begin cnt_dllk_zqinit_r <= #TCQ 'b0; cnt_dllk_zqinit_done_r <= #TCQ 1'b0; end else if (~(phy_ctl_full || phy_cmd_full)) begin cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1; if (!cnt_dllk_zqinit_done_r) cnt_dllk_zqinit_done_r <= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT); end //***************************************************************** // Keep track of which MRS counter needs to be programmed during // memory initialization // The counter and the done signal are reset an additional time // for DDR2. The same signals are used for the additional DDR2 // initialization sequence. //***************************************************************** always @(posedge clk) if ((init_state_r == INIT_IDLE)|| ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))) begin cnt_init_mr_r <= #TCQ 'b0; cnt_init_mr_done_r <= #TCQ 1'b0; end else if (init_state_r == INIT_LOAD_MR) begin cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1; cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE); end //***************************************************************** // Flag to tell if the first precharge for DDR2 init sequence is // done //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) ddr2_pre_flag_r<= #TCQ 'b0; else if (init_state_r == INIT_LOAD_MR) ddr2_pre_flag_r<= #TCQ 1'b1; // reset the flag for multi rank case else if ((ddr2_refresh_flag_r) && (init_state_r == INIT_LOAD_MR_WAIT)&& (cnt_cmd_done_r) && (cnt_init_mr_done_r)) ddr2_pre_flag_r <= #TCQ 'b0; //***************************************************************** // Flag to tell if the refresh stat for DDR2 init sequence is // reached //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) ddr2_refresh_flag_r<= #TCQ 'b0; else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r)) // reset the flag for multi rank case ddr2_refresh_flag_r<= #TCQ 1'b1; else if ((ddr2_refresh_flag_r) && (init_state_r == INIT_LOAD_MR_WAIT)&& (cnt_cmd_done_r) && (cnt_init_mr_done_r)) ddr2_refresh_flag_r <= #TCQ 'b0; //***************************************************************** // Keep track of the number of auto refreshes for DDR2 // initialization. The spec asks for a minimum of two refreshes. // Four refreshes are performed here. The two extra refreshes is to // account for the 200 clock cycle wait between step h and l. // Without the two extra refreshes we would have to have a // wait state. //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) begin cnt_init_af_r <= #TCQ 'b0; cnt_init_af_done_r <= #TCQ 1'b0; end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))begin cnt_init_af_r <= #TCQ cnt_init_af_r + 1; cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11); end //***************************************************************** // Keep track of the register control word programming for // DDR3 RDIMM //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) reg_ctrl_cnt_r <= #TCQ 'b0; else if (init_state_r == INIT_REG_WRITE) reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1; generate if (RANKS < 2) begin: one_rank always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || (complex_byte_rd_done) || prbs_rdlvl_done_pulse ) stg1_wr_done <= #TCQ 1'b0; else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) stg1_wr_done <= #TCQ 1'b1; end else begin: two_ranks always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || (complex_byte_rd_done) || prbs_rdlvl_done_pulse || (rdlvl_stg1_rank_done )) stg1_wr_done <= #TCQ 1'b0; else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) stg1_wr_done <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst) rnk_ref_cnt <= #TCQ 1'b0; else if (stg1_wr_done && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r) rnk_ref_cnt <= #TCQ ~rnk_ref_cnt; always @(posedge clk) if (rst || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r ==INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT)) num_refresh <= #TCQ 'd0; else if ((init_state_r == INIT_REFRESH) && (~pi_dqs_found_done || ((DRAM_TYPE == "DDR3") && ~oclkdelay_calib_done) || (rdlvl_stg1_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done))) num_refresh <= #TCQ num_refresh + 1; //*************************************************************************** // Initialization state machine //*************************************************************************** //***************************************************************** // Next-state logic //***************************************************************** always @(posedge clk) if (rst)begin init_state_r <= #TCQ INIT_IDLE; init_state_r1 <= #TCQ INIT_IDLE; end else begin init_state_r <= #TCQ init_next_state; init_state_r1 <= #TCQ init_state_r; end always @(*) begin init_next_state = init_state_r; (* full_case, parallel_case *) case (init_state_r) //******************************************************* // DRAM initialization //******************************************************* // Initial state - wait for: // 1. Power-on delays to pass // 2. PHY Control Block to assert phy_ctl_ready // 3. PHY Control FIFO must not be FULL // 4. Read path initialization to finish INIT_IDLE: if (cnt_pwron_cke_done_r && phy_ctl_ready && ck_addr_cmd_delay_done && delay_incdec_done && ~(phy_ctl_full || phy_cmd_full) ) begin // If skipping memory initialization (simulation only) if (SIM_INIT_OPTION == "SKIP_INIT") //if (WRLVL == "ON") // Proceed to write leveling // init_next_state = INIT_WRLVL_START; //else //if (SIM_CAL_OPTION != "SKIP_CAL") // Proceed to Phaser_In phase lock init_next_state = INIT_RDLVL_ACT; // else // Skip read leveling //init_next_state = INIT_DONE; else init_next_state = INIT_WAIT_CKE_EXIT; end // Wait minimum of Reset CKE exit time (tXPR = max(tXS, INIT_WAIT_CKE_EXIT: if ((cnt_txpr_done_r) && (DRAM_TYPE == "DDR3") && ~(phy_ctl_full || phy_cmd_full)) begin if((REG_CTRL == "ON") && ((nCS_PER_RANK > 1) || (RANKS > 1))) //register write for reg dimm. Some register chips // have the register chip in a pre-programmed state // in that case the nCS_PER_RANK == 1 && RANKS == 1 init_next_state = INIT_REG_WRITE; else // Load mode register - this state is repeated multiple times init_next_state = INIT_LOAD_MR; end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == "DDR2") && ~(phy_ctl_full || phy_cmd_full)) // DDR2 start with a precharge all command init_next_state = INIT_DDR2_PRECHARGE; INIT_REG_WRITE: init_next_state = INIT_REG_WRITE_WAIT; INIT_REG_WRITE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if(reg_ctrl_cnt_r == 4'd8) init_next_state = INIT_LOAD_MR; else init_next_state = INIT_REG_WRITE; end INIT_LOAD_MR: init_next_state = INIT_LOAD_MR_WAIT; // After loading MR, wait at least tMRD INIT_LOAD_MR_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin // If finished loading all mode registers, proceed to next step if (prbs_rdlvl_done && pi_dqs_found_done && rdlvl_stg1_done) // for ddr3 when the correct burst length is writtern at end init_next_state = INIT_PRECHARGE; else if (~wrcal_done && temp_lmr_done) init_next_state = INIT_PRECHARGE_PREWAIT; else if (cnt_init_mr_done_r)begin if(DRAM_TYPE == "DDR3") init_next_state = INIT_ZQCL; else begin //DDR2 if(ddr2_refresh_flag_r)begin // memory initialization per rank for multi-rank case if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) init_next_state = INIT_DDR2_MULTI_RANK; else init_next_state = INIT_RDLVL_ACT; // ddr2 initialization done.load mode state after refresh end else init_next_state = INIT_DDR2_PRECHARGE; end end else init_next_state = INIT_LOAD_MR; end // DDR2 multi rank transition state INIT_DDR2_MULTI_RANK: init_next_state = INIT_DDR2_MULTI_RANK_WAIT; INIT_DDR2_MULTI_RANK_WAIT: init_next_state = INIT_DDR2_PRECHARGE; // Initial ZQ calibration INIT_ZQCL: init_next_state = INIT_WAIT_DLLK_ZQINIT; // Wait until both DLL have locked, and ZQ calibration done INIT_WAIT_DLLK_ZQINIT: if (cnt_dllk_zqinit_done_r && ~(phy_ctl_full || phy_cmd_full)) // memory initialization per rank for multi-rank case if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) init_next_state = INIT_LOAD_MR; //else if (WRLVL == "ON") // init_next_state = INIT_WRLVL_START; else // skip write-leveling (e.g. for DDR2 interface) init_next_state = INIT_RDLVL_ACT; // Initial precharge for DDR2 INIT_DDR2_PRECHARGE: init_next_state = INIT_DDR2_PRECHARGE_WAIT; INIT_DDR2_PRECHARGE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if (ddr2_pre_flag_r) init_next_state = INIT_REFRESH; else // from precharge state initially go to load mode init_next_state = INIT_LOAD_MR; end INIT_REFRESH: if ((RANKS == 2) && (chip_cnt_r == RANKS - 1)) init_next_state = INIT_REFRESH_RNK2_WAIT; else init_next_state = INIT_REFRESH_WAIT; INIT_REFRESH_RNK2_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_PRECHARGE; INIT_REFRESH_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin if(cnt_init_af_done_r && (~mem_init_done_r)) // go to lm state as part of DDR2 init sequence init_next_state = INIT_LOAD_MR; // Go to state to issue back-to-back writes during limit check and centering else if (~oclkdelay_calib_done && (mpr_last_byte_done || mpr_rdlvl_done) && (DRAM_TYPE == "DDR3")) begin if (num_refresh == 'd8) init_next_state = INIT_OCAL_CENTER_ACT; else init_next_state = INIT_REFRESH; end else if(rdlvl_stg1_done && oclkdelay_center_calib_done && complex_oclkdelay_calib_done && ~wrlvl_done_r1 && (WRLVL == "ON")) init_next_state = INIT_WRLVL_START; else if (pi_dqs_found_done && ~wrlvl_done_r1 && ~wrlvl_final && ~wrlvl_byte_redo && (WRLVL == "ON")) init_next_state = INIT_WRLVL_START; else if ((((prbs_last_byte_done_r || prbs_rdlvl_done) && ~complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON")) //&& rdlvl_stg1_done // changed for new algo 3/26 && mem_init_done_r) begin if (num_refresh == 'd8) begin if (BYPASS_COMPLEX_OCAL == "FALSE") init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else init_next_state = INIT_WRCAL_ACT; end else init_next_state = INIT_REFRESH; end else if (~pi_dqs_found_done || (rdlvl_stg1_done && ~prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)) begin if (num_refresh == 'd8) init_next_state = INIT_RDLVL_ACT; else init_next_state = INIT_REFRESH; end else if ((~wrcal_done && wrlvl_byte_redo)&& (DRAM_TYPE == "DDR3") && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRLVL_LOAD_MR2; else if (((prbs_rdlvl_done && rdlvl_stg1_done && complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON")) && mem_init_done_r && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRCAL_ACT; else if (pi_dqs_found_done && (DRAM_TYPE == "DDR3") && ~(mpr_last_byte_done || mpr_rdlvl_done)) begin if (num_refresh == 'd8) init_next_state = INIT_MPR_RDEN; else init_next_state = INIT_REFRESH; end else if (((oclkdelay_calib_done && wrlvl_final && ~wrlvl_done_r1) || // changed for new algo 3/25 (~wrcal_done && wrlvl_byte_redo)) && (DRAM_TYPE == "DDR3")) init_next_state = INIT_WRLVL_LOAD_MR2; else if ((~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) && pi_dqs_found_done) init_next_state = INIT_WRCAL_ACT; else if (mem_init_done_r) begin if (RANKS < 2) init_next_state = INIT_RDLVL_ACT; else if (stg1_wr_done && ~rnk_ref_cnt && ~rdlvl_stg1_done) init_next_state = INIT_PRECHARGE; else init_next_state = INIT_RDLVL_ACT; end else // to DDR2 init state as part of DDR2 init sequence init_next_state = INIT_REFRESH; end //****************************************************** // Write Leveling //******************************************************* // Enable write leveling in MR1 and start write leveling // for current rank INIT_WRLVL_START: init_next_state = INIT_WRLVL_WAIT; // Wait for both MR load and write leveling to complete // (write leveling should take much longer than MR load..) INIT_WRLVL_WAIT: if (wrlvl_rank_done_r7 && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRLVL_LOAD_MR; // Disable write leveling in MR1 for current rank INIT_WRLVL_LOAD_MR: init_next_state = INIT_WRLVL_LOAD_MR_WAIT; INIT_WRLVL_LOAD_MR_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRLVL_LOAD_MR2; // Load MR2 to set ODT: Dynamic ODT for single rank case // And ODTs for multi-rank case as well INIT_WRLVL_LOAD_MR2: init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; // Wait tMRD before proceeding INIT_WRLVL_LOAD_MR2_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin //if (wrlvl_byte_done) // init_next_state = INIT_PRECHARGE_PREWAIT; // else if ((RANKS == 2) && wrlvl_rank_done_r2) // init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; if (~wrlvl_done_r1) init_next_state = INIT_WRLVL_START; else if (SIM_CAL_OPTION == "SKIP_CAL") // If skip rdlvl, then we're done init_next_state = INIT_DONE; else // Otherwise, proceed to read leveling //init_next_state = INIT_RDLVL_ACT; init_next_state = INIT_PRECHARGE_PREWAIT; end //******************************************************* // Read Leveling //******************************************************* // single row activate. All subsequent read leveling writes and // read will take place in this row INIT_RDLVL_ACT: init_next_state = INIT_RDLVL_ACT_WAIT; // hang out for awhile before issuing subsequent column commands // it's also possible to reach this state at various points // during read leveling - determine what the current stage is INIT_RDLVL_ACT_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin // Just finished an activate. Now either write, read, or precharge // depending on where we are in the training sequence if (!pi_calib_done_r1) init_next_state = INIT_PI_PHASELOCK_READS; else if (!pi_dqs_found_done) // (!pi_dqs_found_start || pi_dqs_found_rank_done)) init_next_state = INIT_RDLVL_STG2_READ; else if (~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) init_next_state = INIT_WRCAL_ACT_WAIT; else if ((!rdlvl_stg1_done && ~stg1_wr_done && ~rdlvl_last_byte_done) || (!prbs_rdlvl_done && ~stg1_wr_done && ~prbs_last_byte_done)) begin // Added to avoid rdlvl_stg1 write data pattern at the start of PRBS rdlvl if (!prbs_rdlvl_done && ~stg1_wr_done && rdlvl_last_byte_done) init_next_state = INIT_RDLVL_ACT_WAIT; else init_next_state = INIT_RDLVL_STG1_WRITE; end else if ((!rdlvl_stg1_done && rdlvl_stg1_start_int) || !prbs_rdlvl_done) begin if (rdlvl_last_byte_done || prbs_last_byte_done) // Added to avoid extra reads at the end of read leveling init_next_state = INIT_RDLVL_ACT_WAIT; else begin // Case 2: If in stage 1, and just precharged after training // previous byte, then continue reading if (rdlvl_stg1_done) init_next_state = INIT_RDLVL_STG1_WRITE_READ; else init_next_state = INIT_RDLVL_STG1_READ; end end else if ((prbs_rdlvl_done && rdlvl_stg1_done && (RANKS == 1)) && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRCAL_ACT_WAIT; else // Otherwise, if we're finished with calibration, then precharge // the row - silly, because we just opened it - possible to take // this out by adding logic to avoid the ACT in first place. Make // sure that cnt_cmd_done will handle tRAS(min) init_next_state = INIT_PRECHARGE_PREWAIT; end //************************************************** // Back-to-back reads for Phaser_IN Phase locking // DQS to FREQ_REF clock //************************************************** INIT_PI_PHASELOCK_READS: if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) init_next_state = INIT_PRECHARGE_PREWAIT; //********************************************* // Stage 1 read-leveling (write and continuous read) //********************************************* // Write training pattern for stage 1 // PRBS pattern of TBD length INIT_RDLVL_STG1_WRITE: // 4:1 DDR3 BL8 will require all 8 words in 1 DIV4 clock cycle // 2:1 DDR2/DDR3 BL8 will require 2 DIV2 clock cycles for 8 words // 2:1 DDR2 BL4 will require 1 DIV2 clock cycle for 4 words // An entire row worth of writes issued before proceeding to reads // The number of write is (2^column width)/burst length to accomodate // PRBS pattern for window detection. //VCCO/VCCAUX write is not done if ((complex_num_writes_dec == 1) && ~complex_row0_wr_done && prbs_rdlvl_done && rdlvl_stg1_done_r1) init_next_state = INIT_OCAL_COMPLEX_WRITE_WAIT; //back to back write from row1 else if (stg1_wr_rd_cnt == 9'd1) begin if (rdlvl_stg1_done_r1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else init_next_state = INIT_RDLVL_STG1_WRITE_READ; end INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT: if(read_pause_ext) begin init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; end else begin if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) //At the end of the byte, it goes to REFRESH init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE; end INIT_RDLVL_COMPLEX_PRECHARGE: init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; INIT_RDLVL_COMPLEX_PRECHARGE_WAIT: if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) begin if (prbs_rdlvl_done || prbs_last_byte_done_r) begin // changed for new algo 3/26 // added condition to ensure that limit starts after rdlvl_stg1_done is asserted in the bypass complex rdlvl mode if ((~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) || ~lim_done) init_next_state = INIT_OCAL_CENTER_ACT; //INIT_OCAL_COMPLEX_ACT; // changed for new algo 3/26 else if (lim_done && complex_oclkdelay_calib_start_r2) init_next_state = INIT_RDLVL_COMPLEX_ACT; else init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; end else init_next_state = INIT_RDLVL_COMPLEX_ACT; end INIT_RDLVL_COMPLEX_ACT: init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT; INIT_RDLVL_COMPLEX_ACT_WAIT: if (complex_rdlvl_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) begin if (oclkdelay_center_calib_start) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; else if (stg1_wr_done) init_next_state = INIT_RDLVL_COMPLEX_READ; else if (~complex_row1_wr_done) if (complex_oclkdelay_calib_start_int && complex_ocal_num_samples_done_r) //WAIT for resume signal for write init_next_state = INIT_OCAL_COMPLEX_RESUME_WAIT; else init_next_state = INIT_RDLVL_STG1_WRITE; else init_next_state = INIT_RDLVL_STG1_WRITE_READ; end // Write-read turnaround INIT_RDLVL_STG1_WRITE_READ: if (reset_rd_addr_r1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin if (rdlvl_stg1_done_r1) init_next_state = INIT_RDLVL_COMPLEX_READ; else init_next_state = INIT_RDLVL_STG1_READ; end // Continuous read, where interruptible by precharge request from // calibration logic. Also precharges when stage 1 is complete // No precharges when reads provided to Phaser_IN for phase locking // FREQ_REF to read DQS since data integrity is not important. INIT_RDLVL_STG1_READ: if (rdlvl_stg1_rank_done || (rdlvl_stg1_done && ~rdlvl_stg1_done_r1) || prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; INIT_RDLVL_COMPLEX_READ: if (prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; //For non-back-to-back reads from row0 (VCCO and VCCAUX pattern) else if (~prbs_rdlvl_done && (complex_num_reads_dec == 1) && ~complex_row0_rd_done) init_next_state = INIT_RDLVL_COMPLEX_READ_WAIT; //For back-to-back reads from row1 (ISI pattern) else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; INIT_RDLVL_COMPLEX_READ_WAIT: if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) init_next_state = INIT_RDLVL_COMPLEX_READ; //********************************************* // DQSFOUND calibration (set of 4 reads with gaps) //********************************************* // Read of training data. Note that Stage 2 is not a constant read, // instead there is a large gap between each set of back-to-back reads INIT_RDLVL_STG2_READ: // 4 read commands issued back-to-back if (num_reads == 'b1) init_next_state = INIT_RDLVL_STG2_READ_WAIT; // Wait before issuing the next set of reads. If a precharge request // comes in then handle - this can occur after stage 2 calibration is // completed for a DQS group INIT_RDLVL_STG2_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if (pi_dqs_found_rank_done || pi_dqs_found_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; else if (cnt_cmd_done_r) init_next_state = INIT_RDLVL_STG2_READ; end //****************************************************************** // MPR Read Leveling for DDR3 OCLK_DELAYED calibration //****************************************************************** // Issue Load Mode Register 3 command with A[2]=1, A[1:0]=2'b00 // to enable Multi Purpose Register (MPR) Read INIT_MPR_RDEN: init_next_state = INIT_MPR_WAIT; //Wait tMRD, tMOD INIT_MPR_WAIT: if (cnt_cmd_done_r) begin init_next_state = INIT_MPR_READ; end // Issue back-to-back read commands to read from MPR with // Address bus 0x0000 for BL=8. DQ[0] will output the pre-defined // MPR pattern of 01010101 (Rise0 = 1'b0, Fall0 = 1'b1 ...) INIT_MPR_READ: if (mpr_rdlvl_done || mpr_rnk_done || rdlvl_prech_req) init_next_state = INIT_MPR_DISABLE_PREWAIT; INIT_MPR_DISABLE_PREWAIT: if (cnt_cmd_done_r) init_next_state = INIT_MPR_DISABLE; // Issue Load Mode Register 3 command with A[2]=0 to disable // MPR read INIT_MPR_DISABLE: init_next_state = INIT_MPR_DISABLE_WAIT; INIT_MPR_DISABLE_WAIT: init_next_state = INIT_PRECHARGE_PREWAIT; //*********************************************************************** // OCLKDELAY Calibration //*********************************************************************** // This calibration requires single write followed by single read to // determine the Phaser_Out stage 3 delay required to center write DQS // in write DQ valid window. // Single Row Activate command before issuing Write command INIT_OCLKDELAY_ACT: init_next_state = INIT_OCLKDELAY_ACT_WAIT; INIT_OCLKDELAY_ACT_WAIT: if (cnt_cmd_done_r && ~oclk_prech_req) init_next_state = INIT_OCLKDELAY_WRITE; else if (oclkdelay_calib_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; INIT_OCLKDELAY_WRITE: if (oclk_wr_cnt == 4'd1) init_next_state = INIT_OCLKDELAY_WRITE_WAIT; INIT_OCLKDELAY_WRITE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if (oclkdelay_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else init_next_state = INIT_OCLKDELAY_READ; end INIT_OCLKDELAY_READ: init_next_state = INIT_OCLKDELAY_READ_WAIT; INIT_OCLKDELAY_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if ((oclk_calib_resume_level || oclk_calib_resume) && ~oclkdelay_int_ref_req) init_next_state = INIT_OCLKDELAY_WRITE; else if (oclkdelay_calib_done || prech_req_posedge_r || wrlvl_final || oclkdelay_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else if (oclkdelay_center_calib_start) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; end //********************************************* // Write calibration //********************************************* // single row activate INIT_WRCAL_ACT: init_next_state = INIT_WRCAL_ACT_WAIT; // hang out for awhile before issuing subsequent column command INIT_WRCAL_ACT_WAIT: if (cnt_cmd_done_r && ~wrcal_prech_req) init_next_state = INIT_WRCAL_WRITE; else if (wrcal_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; // Write training pattern for write calibration INIT_WRCAL_WRITE: // Once we've issued enough commands for 8 words - proceed to reads //if (burst_addr_r == 1'b1) if (wrcal_wr_cnt == 4'd1) init_next_state = INIT_WRCAL_WRITE_READ; // Write-read turnaround INIT_WRCAL_WRITE_READ: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRCAL_READ; else if (dqsfound_retry) init_next_state = INIT_RDLVL_STG2_READ_WAIT; INIT_WRCAL_READ: if (burst_addr_r == 1'b1) init_next_state = INIT_WRCAL_READ_WAIT; INIT_WRCAL_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if (wrcal_resume_r) begin if (wrcal_final_chk) init_next_state = INIT_WRCAL_READ; else init_next_state = INIT_WRCAL_WRITE; end else if (wrcal_done || prech_req_posedge_r || wrcal_act_req || // Added to support PO fine delay inc when TG errors wrlvl_byte_redo || (temp_wrcal_done && ~temp_lmr_done)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (dqsfound_retry) init_next_state = INIT_RDLVL_STG2_READ_WAIT; else if (wrcal_read_req && cnt_wrcal_rd) init_next_state = INIT_WRCAL_MULT_READS; end INIT_WRCAL_MULT_READS: // multiple read commands issued back-to-back if (wrcal_reads == 'b1) init_next_state = INIT_WRCAL_READ_WAIT; //********************************************* // Handling of precharge during and in between read-level stages //********************************************* // Make sure we aren't violating any timing specs by precharging // immediately INIT_PRECHARGE_PREWAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_PRECHARGE; // Initiate precharge INIT_PRECHARGE: init_next_state = INIT_PRECHARGE_WAIT; INIT_PRECHARGE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if ((wrcal_sanity_chk_done && (DRAM_TYPE == "DDR3")) || (rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && (DRAM_TYPE == "DDR2"))) init_next_state = INIT_DONE; else if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && complex_oclkdelay_calib_done && wrlvl_done_r1 && ((ddr3_lm_done_r) || (DRAM_TYPE == "DDR2"))) init_next_state = INIT_WRCAL_ACT; else if ((wrcal_done || (WRLVL == "OFF") || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) && (rdlvl_stg1_done || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) && prbs_rdlvl_done && complex_oclkdelay_calib_done && wrlvl_done_r1 &rdlvl_stg1_done && pi_dqs_found_done) begin // after all calibration program the correct burst length init_next_state = INIT_LOAD_MR; // Added to support PO fine delay inc when TG errors end else if (~wrcal_done && temp_wrcal_done && temp_lmr_done) init_next_state = INIT_WRCAL_READ_WAIT; else if (rdlvl_stg1_done && pi_dqs_found_done && (WRLVL == "ON")) // If read leveling finished, proceed to write calibration init_next_state = INIT_REFRESH; else // Otherwise, open row for read-leveling purposes init_next_state = INIT_REFRESH; end //******************************************************* // COMPLEX OCLK calibration - for fragmented write //******************************************************* INIT_OCAL_COMPLEX_ACT: init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; INIT_OCAL_COMPLEX_ACT_WAIT: if (complex_wait_cnt =='d15) init_next_state = INIT_RDLVL_STG1_WRITE; INIT_OCAL_COMPLEX_WRITE_WAIT: if (prech_req_posedge_r || (complex_oclkdelay_calib_done && ~complex_oclkdelay_calib_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) init_next_state = INIT_RDLVL_STG1_WRITE; //wait for all srg2/stg3 tap movement is done and go back to write again INIT_OCAL_COMPLEX_RESUME_WAIT: if (complex_oclk_calib_resume) init_next_state = INIT_RDLVL_STG1_WRITE; else if (complex_oclkdelay_calib_done || complex_ocal_ref_req ) init_next_state = INIT_PRECHARGE_PREWAIT; //******************************************************* // OCAL STG3 Centering calibration //******************************************************* INIT_OCAL_CENTER_ACT: init_next_state = INIT_OCAL_CENTER_ACT_WAIT; INIT_OCAL_CENTER_ACT_WAIT: if (ocal_act_wait_cnt == 'd15) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; INIT_OCAL_CENTER_WRITE: if(!oclk_center_write_resume && !lim_wr_req) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; INIT_OCAL_CENTER_WRITE_WAIT: //if (oclkdelay_center_calib_done || prech_req_posedge_r) if (prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && oclkdelay_calib_done && ~oclkdelay_center_calib_start) init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && ~oclkdelay_center_calib_start) init_next_state = INIT_OCLKDELAY_READ_WAIT; else if (oclk_center_write_resume || lim_wr_req) init_next_state = INIT_OCAL_CENTER_WRITE; //******************************************************* // Initialization/Calibration done. Take a long rest, relax //******************************************************* INIT_DONE: init_next_state = INIT_DONE; endcase end //***************************************************************** // Initialization done signal - asserted before leveling starts //***************************************************************** always @(posedge clk) if (rst) mem_init_done_r <= #TCQ 1'b0; else if ((!cnt_dllk_zqinit_done_r && (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) && (chip_cnt_r == RANKS-1) && (DRAM_TYPE == "DDR3")) || ( (init_state_r == INIT_LOAD_MR_WAIT) && (ddr2_refresh_flag_r) && (chip_cnt_r == RANKS-1) && (cnt_init_mr_done_r) && (DRAM_TYPE == "DDR2"))) mem_init_done_r <= #TCQ 1'b1; //***************************************************************** // Write Calibration signal to PHY Control Block - asserted before // Write Leveling starts //***************************************************************** //generate //if (RANKS < 2) begin: ranks_one always @(posedge clk) begin if (rst || (done_dqs_tap_inc && (init_state_r == INIT_WRLVL_LOAD_MR2))) write_calib <= #TCQ 1'b0; else if (wrlvl_active_r1) write_calib <= #TCQ 1'b1; end //end else begin: ranks_two // always @(posedge clk) begin // if (rst || // ((init_state_r1 == INIT_WRLVL_LOAD_MR_WAIT) && // ((wrlvl_rank_done_r2 && (chip_cnt_r == RANKS-1)) || // (SIM_CAL_OPTION == "FAST_CAL")))) // write_calib <= #TCQ 1'b0; // else if (wrlvl_active_r1) // write_calib <= #TCQ 1'b1; // end //end //endgenerate //***************************************************************** // Read Calibration signal to PHY Control Block - asserted after // Write Leveling during PHASER_IN phase locking stage. // Must be de-asserted before Read Leveling //***************************************************************** always @(posedge clk) begin if (rst || pi_calib_done_r1) read_calib_int <= #TCQ 1'b0; else if (~pi_calib_done_r1 && (init_state_r == INIT_RDLVL_ACT_WAIT) && (cnt_cmd_r == CNTNEXT_CMD)) read_calib_int <= #TCQ 1'b1; end always @(posedge clk) read_calib_r <= #TCQ read_calib_int; always @(posedge clk) begin if (rst || pi_calib_done_r1) read_calib <= #TCQ 1'b0; else if (~pi_calib_done_r1 && (init_state_r == INIT_PI_PHASELOCK_READS)) read_calib <= #TCQ 1'b1; end always @(posedge clk) if (rst) pi_calib_done_r <= #TCQ 1'b0; else if (pi_calib_rank_done_r)// && (chip_cnt_r == RANKS-1)) pi_calib_done_r <= #TCQ 1'b1; always @(posedge clk) if (rst) pi_calib_rank_done_r <= #TCQ 1'b0; else if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) pi_calib_rank_done_r <= #TCQ 1'b1; else pi_calib_rank_done_r <= #TCQ 1'b0; always @(posedge clk) begin if (rst || ((PRE_REV3ES == "ON") && temp_wrcal_done && ~temp_wrcal_done_r)) pi_phaselock_timer <= #TCQ 'd0; else if (((init_state_r == INIT_PI_PHASELOCK_READS) && (pi_phaselock_timer != PHASELOCKED_TIMEOUT)) || tg_timer_go) pi_phaselock_timer <= #TCQ pi_phaselock_timer + 1; else pi_phaselock_timer <= #TCQ pi_phaselock_timer; end assign pi_phase_locked_err = (pi_phaselock_timer == PHASELOCKED_TIMEOUT) ? 1'b1 : 1'b0; //***************************************************************** // DDR3 final burst length programming done. For DDR3 during // calibration the burst length is fixed to BL8. After calibration // the correct burst length is programmed. //***************************************************************** always @(posedge clk) if (rst) ddr3_lm_done_r <= #TCQ 1'b0; else if ((init_state_r == INIT_LOAD_MR_WAIT) && (chip_cnt_r == RANKS-1) && wrcal_done) ddr3_lm_done_r <= #TCQ 1'b1; always @(posedge clk) begin pi_dqs_found_rank_done_r <= #TCQ pi_dqs_found_rank_done; pi_phase_locked_all_r1 <= #TCQ pi_phase_locked_all; pi_phase_locked_all_r2 <= #TCQ pi_phase_locked_all_r1; pi_phase_locked_all_r3 <= #TCQ pi_phase_locked_all_r2; pi_phase_locked_all_r4 <= #TCQ pi_phase_locked_all_r3; pi_dqs_found_all_r <= #TCQ pi_dqs_found_done; pi_calib_done_r1 <= #TCQ pi_calib_done_r; end //*************************************************************************** // Logic for deep memory (multi-rank) configurations //*************************************************************************** // For DDR3 asserted when generate if (RANKS < 2) begin: single_rank always @(posedge clk) chip_cnt_r <= #TCQ 2'b00; end else begin: dual_rank always @(posedge clk) if (rst || // Set chip_cnt_r to 2'b00 after both Ranks are read leveled (rdlvl_stg1_done && prbs_rdlvl_done && ~wrcal_done) || // Set chip_cnt_r to 2'b00 after both Ranks are write leveled (wrlvl_done_r && (init_state_r==INIT_WRLVL_LOAD_MR2_WAIT)))begin chip_cnt_r <= #TCQ 2'b00; end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) && (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT)) && (DRAM_TYPE == "DDR3")) || ((init_state_r==INIT_REFRESH_RNK2_WAIT) && (cnt_cmd_r=='d36)) || //mpr_rnk_done || //(rdlvl_stg1_rank_done && ~rdlvl_last_byte_done) || //(stg1_wr_done && (init_state_r == INIT_REFRESH) && //~(rnk_ref_cnt && rdlvl_last_byte_done)) || // Increment chip_cnt_r to issue Refresh to second rank (~pi_dqs_found_all_r && (init_state_r==INIT_PRECHARGE_PREWAIT) && (cnt_cmd_r=='d36)) || // Increment chip_cnt_r when DQSFOUND done for the Rank (pi_dqs_found_rank_done && ~pi_dqs_found_rank_done_r) || ((init_state_r == INIT_LOAD_MR_WAIT)&& cnt_cmd_done_r && wrcal_done) || ((init_state_r == INIT_DDR2_MULTI_RANK) && (DRAM_TYPE == "DDR2"))) begin if ((~mem_init_done_r || ~rdlvl_stg1_done || ~pi_dqs_found_done || // condition to increment chip_cnt during // final burst length programming for DDR3 ~pi_calib_done_r || wrcal_done) //~mpr_rdlvl_done || && (chip_cnt_r != RANKS-1)) chip_cnt_r <= #TCQ chip_cnt_r + 1; else chip_cnt_r <= #TCQ 2'b00; end end endgenerate // verilint STARC-2.2.3.3 off generate if ((REG_CTRL == "ON") && (RANKS == 1)) begin: DDR3_RDIMM_1rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[0] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end end else if (RANKS == 1) begin: DDR3_1rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (n = 0; n < nCS_PER_RANK; n = n + 1) begin phy_int_cs_n[n] <= #TCQ 1'b0; end end else begin //odd CWL for (p = nCS_PER_RANK; p < 2*nCS_PER_RANK; p = p + 1) begin phy_int_cs_n[p] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end end else if ((REG_CTRL == "ON") && (RANKS == 2)) begin: DDR3_2rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; case (chip_cnt_r) 2'b00:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[0] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end 2'b01:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[1] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1+1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end endcase end end end else if (RANKS == 2) begin: DDR3_2rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; case (chip_cnt_r) 2'b00:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (n = 0; n < nCS_PER_RANK; n = n + 1) begin phy_int_cs_n[n] <= #TCQ 1'b0; end end else begin // odd CWL for (p = CS_WIDTH*nCS_PER_RANK; p < (CS_WIDTH*nCS_PER_RANK + nCS_PER_RANK); p = p + 1) begin phy_int_cs_n[p] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end 2'b01:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (q = nCS_PER_RANK; q < (2 * nCS_PER_RANK); q = q + 1) begin phy_int_cs_n[q] <= #TCQ 1'b0; end end else begin // odd CWL for (m = (nCS_PER_RANK*CS_WIDTH + nCS_PER_RANK); m < (nCS_PER_RANK*CS_WIDTH + 2*nCS_PER_RANK); m = m + 1) begin phy_int_cs_n[m] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end endcase end end // always @ (posedge clk) end // verilint STARC-2.2.3.3 on // commented out for now. Need it for DDR2 2T timing /* end else begin: DDR2 always @(posedge clk) if (rst) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end else begin if (init_state_r == INIT_REG_WRITE) begin // All ranks selected simultaneously phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}}; end else if ((wrlvl_odt) || (init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH)) begin phy_int_cs_n[0] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end // else: !if(rst) end // block: DDR2 */ endgenerate assign phy_cs_n = phy_int_cs_n; //*************************************************************************** // Write/read burst logic for calibration //*************************************************************************** assign rdlvl_wr = (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE); assign rdlvl_rd = (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_MPR_READ) || (init_state_r == INIT_WRCAL_MULT_READS); assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd; assign mmcm_wr = (init_state_r == INIT_OCAL_CENTER_WRITE); //used to de-assert cs_n during centering // assign mmcm_wr = 'b0; // (init_state_r == INIT_OCAL_CENTER_WRITE); //*************************************************************************** // Address generation and logic to count # of writes/reads issued during // certain stages of calibration //*************************************************************************** // Column address generation logic: // Keep track of the current column address - since all bursts are in // increments of 8 only during calibration, we need to keep track of // addresses [COL_WIDTH-1:3], lower order address bits will always = 0 always @(posedge clk) if (rst || wrcal_done) burst_addr_r <= #TCQ 1'b0; else if ((init_state_r == INIT_WRCAL_ACT_WAIT) || (init_state_r == INIT_OCLKDELAY_ACT_WAIT) || (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS) || (init_state_r == INIT_WRCAL_READ_WAIT)) burst_addr_r <= #TCQ 1'b1; else if (rdlvl_wr_rd && new_burst_r) burst_addr_r <= #TCQ ~burst_addr_r; else burst_addr_r <= #TCQ 1'b0; // Read Level Stage 1 requires writes to the entire row since // a PRBS pattern is being written. This counter keeps track // of the number of writes which depends on the column width // The (stg1_wr_rd_cnt==9'd0) condition was added so the col // address wraps around during stage1 reads always @(posedge clk) if (rst || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && ~rdlvl_stg1_done)) stg1_wr_rd_cnt <= #TCQ NUM_STG1_WR_RD; else if (rdlvl_last_byte_done || (stg1_wr_rd_cnt == 9'd1) || (prbs_rdlvl_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || (init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) ) begin if (~complex_row0_wr_done || wr_victim_inc || (complex_row1_wr_done && (~complex_row0_rd_done || (complex_row0_rd_done && complex_row1_rd_done)))) stg1_wr_rd_cnt <= #TCQ 'd127; else stg1_wr_rd_cnt <= #TCQ prbs_rdlvl_done?'d30 :'d22; end else if (((init_state_r == INIT_RDLVL_STG1_WRITE) && new_burst_r && ~phy_data_full) ||((init_state_r == INIT_RDLVL_COMPLEX_READ) && rdlvl_stg1_done)) stg1_wr_rd_cnt <= #TCQ stg1_wr_rd_cnt - 1; always @(posedge clk) if (rst) wr_victim_inc <= #TCQ 1'b0; else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2) && ~stg1_wr_done) wr_victim_inc <= #TCQ 1'b1; else wr_victim_inc <= #TCQ 1'b0; always @(posedge clk) reset_rd_addr_r1 <= #TCQ reset_rd_addr; generate if (FIXED_VICTIM == "FALSE") begin: row_cnt_victim_rotate always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt == DQ_WIDTH*2-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) complex_row_cnt <= #TCQ 'd0; else if ((((stg1_wr_rd_cnt == 'd22) && ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (complex_rdlvl_int_ref_req && (init_state_r == INIT_REFRESH_WAIT) && (cnt_cmd_r == 'd127)))) || complex_victim_inc || (complex_sample_cnt_inc_r2 && ~complex_victim_inc) || wr_victim_inc || reset_rd_addr_r1)) begin // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 if ((complex_row_cnt < DQ_WIDTH*2-1) && ~stg1_wr_done) complex_row_cnt <= #TCQ complex_row_cnt + 1; // During reads row count requires different conditions for increments else if (stg1_wr_done) begin if (reset_rd_addr_r1) complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16; // When looping multiple times in the same victim bit in a byte else if (complex_sample_cnt_inc_r2 && ~complex_victim_inc) complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16 + rd_victim_sel*2; // When looping through victim bits within a byte else if (complex_row_cnt < pi_stg2_prbs_rdlvl_cnt*16+15) complex_row_cnt <= #TCQ complex_row_cnt + 1; // When the number of samples is done and tap is incremented within a byte else complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16; end end end else begin: row_cnt_victim_fixed always @(posedge clk) if (rst || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) complex_row_cnt <= #TCQ 'd0; else if ((stg1_wr_rd_cnt == 'd22) && (((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) && (complex_wait_cnt == 'd15)) || complex_rdlvl_int_ref_req)) complex_row_cnt <= #TCQ 'd1; else complex_row_cnt <= #TCQ 'd0; end endgenerate //row count always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done_pulse || complex_byte_rd_done) complex_row_cnt_ocal <= #TCQ 'd0; else if ( prbs_rdlvl_done && (((stg1_wr_rd_cnt == 'd30) && (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE)) || (complex_sample_cnt_inc_r2) || wr_victim_inc)) begin // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 if (complex_row_cnt_ocal < COMPLEX_ROW_CNT_BYTE-1) begin complex_row_cnt_ocal <= #TCQ complex_row_cnt_ocal + 1; end end always @(posedge clk) if (rst) complex_odt_ext <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE)) complex_odt_ext <= #TCQ 1'b0; else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd1) && (init_state_r == INIT_RDLVL_STG1_WRITE)) complex_odt_ext <= #TCQ 1'b1; always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt == DQ_WIDTH*2-1))) begin wr_victim_sel <= #TCQ 'd0; wr_byte_cnt <= #TCQ 'd0; end else if (rdlvl_stg1_done_r1 && wr_victim_inc) begin wr_victim_sel <= #TCQ wr_victim_sel + 1; if (wr_victim_sel == 'd7) wr_byte_cnt <= #TCQ wr_byte_cnt + 1; end always @(posedge clk) if (rst) begin wr_victim_sel_ocal <= #TCQ 'd0; end else if (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) begin wr_victim_sel_ocal <= #TCQ 'd0; end else if (prbs_rdlvl_done && wr_victim_inc) begin wr_victim_sel_ocal <= #TCQ wr_victim_sel_ocal + 1; end always @(posedge clk) if (rst) begin victim_sel <= #TCQ 'd0; victim_byte_cnt <= #TCQ 'd0; end else if ((~stg1_wr_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_wr_done)) begin victim_sel <= #TCQ prbs_rdlvl_done? wr_victim_sel_ocal: wr_victim_sel; victim_byte_cnt <= #TCQ prbs_rdlvl_done? complex_oclkdelay_calib_cnt:wr_byte_cnt; end else begin if( (init_state_r == INIT_RDLVL_COMPLEX_ACT) || reset_rd_addr) victim_sel <= #TCQ prbs_rdlvl_done? complex_ocal_rd_victim_sel:rd_victim_sel; victim_byte_cnt <= #TCQ prbs_rdlvl_done? complex_oclkdelay_calib_cnt:pi_stg2_prbs_rdlvl_cnt; end generate if (FIXED_VICTIM == "FALSE") begin: wr_done_victim_rotate always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt < DQ_WIDTH*2-1) && ~prbs_rdlvl_done) || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done || prbs_rdlvl_done_pulse) begin complex_row0_wr_done <= #TCQ 1'b0; end else if ( rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd2)) begin complex_row0_wr_done <= #TCQ 1'b1; end always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt < DQ_WIDTH*2-1) && ~prbs_rdlvl_done) || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done || prbs_rdlvl_done_pulse) begin complex_row1_wr_done <= #TCQ 1'b0; end else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2)) begin complex_row1_wr_done <= #TCQ 1'b1; end end else begin: wr_done_victim_fixed always @(posedge clk) if (rst || prbs_rdlvl_done_pulse || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done ) begin complex_row0_wr_done <= #TCQ 1'b0; end else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd2)) begin complex_row0_wr_done <= #TCQ 1'b1; end always @(posedge clk) if (rst || prbs_rdlvl_done_pulse || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done ) begin complex_row1_wr_done <= #TCQ 1'b0; end else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2)) begin complex_row1_wr_done <= #TCQ 1'b1; end end endgenerate always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row0_rd_done <= #TCQ 1'b0; else if (complex_sample_cnt_inc) complex_row0_rd_done <= #TCQ 1'b0; else if ( (prbs_rdlvl_start || complex_oclkdelay_calib_start_int) && (stg1_wr_rd_cnt == 9'd2) && complex_row0_wr_done && complex_row1_wr_done) complex_row0_rd_done <= #TCQ 1'b1; always @(posedge clk) complex_row0_rd_done_r1 <= #TCQ complex_row0_rd_done; always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row1_rd_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE)) complex_row1_rd_done <= #TCQ 1'b0; else if (complex_row0_rd_done && (stg1_wr_rd_cnt == 9'd2)) complex_row1_rd_done <= #TCQ 1'b1; always @(posedge clk) complex_row1_rd_done_r1 <= #TCQ complex_row1_rd_done; //calculate row rd num for complex_oclkdelay_calib //once it reached to 8 always @ (posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row1_rd_cnt <= #TCQ 'd0; else complex_row1_rd_cnt <= #TCQ (complex_row1_rd_done & ~complex_row1_rd_done_r1) ? ((complex_row1_rd_cnt == (COMPLEX_RD-1))? 0:complex_row1_rd_cnt + 'd1) : complex_row1_rd_cnt; //For write, reset rd_done for the byte always @ (posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_STG1_WRITE) || prbs_rdlvl_done_pulse) complex_byte_rd_done <= #TCQ 'b0; else if (prbs_rdlvl_done && (complex_row1_rd_cnt == (COMPLEX_RD-1)) && (complex_row1_rd_done & ~complex_row1_rd_done_r1)) complex_byte_rd_done <= #TCQ 'b1; end always @ (posedge clk) begin complex_byte_rd_done_r1 <= #TCQ complex_byte_rd_done; complex_ocal_num_samples_inc <= #TCQ (complex_byte_rd_done & ~complex_byte_rd_done_r1); end generate if (RANKS < 2) begin: one_rank_complex always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || ( complex_oclkdelay_calib_done && (init_state_r == INIT_RDLVL_STG1_WRITE )) || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT) || prbs_rdlvl_done_pulse ) complex_wr_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; else if ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; end else begin: dual_rank_complex always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || ( complex_oclkdelay_calib_done && (init_state_r == INIT_RDLVL_STG1_WRITE )) || (rdlvl_stg1_rank_done ) || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT) || prbs_rdlvl_done_pulse ) complex_wr_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; else if ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst) complex_wait_cnt <= #TCQ 'd0; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && complex_wait_cnt < 'd15) complex_wait_cnt <= #TCQ complex_wait_cnt + 1; else complex_wait_cnt <= #TCQ 'd0; always @(posedge clk) if (rst) begin complex_num_reads <= #TCQ 'd1; end else if ((((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd14)) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && ext_int_ref_req && (cnt_cmd_r == 'd127))) && ~complex_row0_rd_done) begin if (stg1_wr_rd_cnt > 'd85) begin if (complex_num_reads < 'd6) complex_num_reads <= #TCQ complex_num_reads + 1; else complex_num_reads <= #TCQ 'd1; // Initila value for VCCAUX pattern is 3, 7, and 12 end else if (stg1_wr_rd_cnt > 'd73) begin if (stg1_wr_rd_cnt == 'd85) complex_num_reads <= #TCQ 'd3; else if (complex_num_reads < 'd5) complex_num_reads <= #TCQ complex_num_reads + 1; end else if (stg1_wr_rd_cnt > 'd39) begin if (stg1_wr_rd_cnt == 'd73) complex_num_reads <= #TCQ 'd7; else if (complex_num_reads < 'd10) complex_num_reads <= #TCQ complex_num_reads + 1; end else begin if (stg1_wr_rd_cnt == 'd39) complex_num_reads <= #TCQ 'd12; else if (complex_num_reads < 'd14) complex_num_reads <= #TCQ complex_num_reads + 1; end // Initialize to 1 at the start of reads or after precharge and activate end else if ((((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && ~ext_int_ref_req) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && (stg1_wr_rd_cnt == 'd22))) complex_num_reads <= #TCQ 'd1; always @(posedge clk) if (rst) complex_num_reads_dec <= #TCQ 'd1; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) complex_num_reads_dec <= #TCQ complex_num_reads; else if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (complex_num_reads_dec > 'd0)) complex_num_reads_dec <= #TCQ complex_num_reads_dec - 1; always @(posedge clk) if (rst) complex_address <= #TCQ 'd0; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ_WAIT)) || ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (init_state_r1 != INIT_OCAL_COMPLEX_WRITE_WAIT))) complex_address <= #TCQ phy_address[COL_WIDTH-1:0]; always @ (posedge clk) if (rst) complex_oclkdelay_calib_start_int <= #TCQ 'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && prbs_last_byte_done_r) // changed for new algo 3/26 complex_oclkdelay_calib_start_int <= #TCQ 'b1; always @(posedge clk) begin complex_oclkdelay_calib_start_r1 <= #TCQ complex_oclkdelay_calib_start_int; complex_oclkdelay_calib_start_r2 <= #TCQ complex_oclkdelay_calib_start_r1; end always @ (posedge clk) if (rst) complex_oclkdelay_calib_start <= #TCQ 'b0; else if (complex_oclkdelay_calib_start_int && (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT) && prbs_rdlvl_done) // changed for new algo 3/26 complex_oclkdelay_calib_start <= #TCQ 'b1; //packet fragmentation for complex oclkdealy calib write always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) begin complex_num_writes <= #TCQ 'd1; end else if ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14) && ~complex_row0_wr_done) begin if (stg1_wr_rd_cnt > 'd85) begin if (complex_num_writes < 'd6) complex_num_writes <= #TCQ complex_num_writes + 1; else complex_num_writes <= #TCQ 'd1; // Initila value for VCCAUX pattern is 3, 7, and 12 end else if (stg1_wr_rd_cnt > 'd73) begin if (stg1_wr_rd_cnt == 'd85) complex_num_writes <= #TCQ 'd3; else if (complex_num_writes < 'd5) complex_num_writes <= #TCQ complex_num_writes + 1; end else if (stg1_wr_rd_cnt > 'd39) begin if (stg1_wr_rd_cnt == 'd73) complex_num_writes <= #TCQ 'd7; else if (complex_num_writes < 'd10) complex_num_writes <= #TCQ complex_num_writes + 1; end else begin if (stg1_wr_rd_cnt == 'd39) complex_num_writes <= #TCQ 'd12; else if (complex_num_writes < 'd14) complex_num_writes <= #TCQ complex_num_writes + 1; end // Initialize to 1 at the start of write or after precharge and activate end else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row0_wr_done) complex_num_writes <= #TCQ 'd30; else if (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) complex_num_writes <= #TCQ 'd1; always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_num_writes_dec <= #TCQ 'd1; else if (((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) complex_num_writes_dec <= #TCQ complex_num_writes; else if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (complex_num_writes_dec > 'd0)) complex_num_writes_dec <= #TCQ complex_num_writes_dec - 1; always @(posedge clk) if (rst) complex_sample_cnt_inc_ocal <= #TCQ 1'b0; else if ((stg1_wr_rd_cnt == 9'd1) && complex_byte_rd_done && prbs_rdlvl_done) complex_sample_cnt_inc_ocal <= #TCQ 1'b1; else complex_sample_cnt_inc_ocal <= #TCQ 1'b0; always @(posedge clk) if (rst) complex_sample_cnt_inc <= #TCQ 1'b0; else if ((stg1_wr_rd_cnt == 9'd1) && complex_row1_rd_done) complex_sample_cnt_inc <= #TCQ 1'b1; else complex_sample_cnt_inc <= #TCQ 1'b0; always @(posedge clk) begin complex_sample_cnt_inc_r1 <= #TCQ complex_sample_cnt_inc; complex_sample_cnt_inc_r2 <= #TCQ complex_sample_cnt_inc_r1; end //complex refresh req always @ (posedge clk) begin if(rst || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_ACT)) ) complex_ocal_ref_done <= #TCQ 1'b1; else if (init_state_r == INIT_RDLVL_STG1_WRITE) complex_ocal_ref_done <= #TCQ 1'b0; end //complex ocal odt extention always @(posedge clk) if (rst) complex_ocal_odt_ext <= #TCQ 1'b0; else if (((init_state_r == INIT_PRECHARGE_PREWAIT) && cnt_cmd_done_m7_r) || (init_state_r == INIT_OCLKDELAY_READ_WAIT)) complex_ocal_odt_ext <= #TCQ 1'b0; else if ((init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT)) complex_ocal_odt_ext <= #TCQ 1'b1; // OCLKDELAY calibration requires multiple writes because // write can be up to 2 cycles early since OCLKDELAY tap // can go down to 0 always @(posedge clk) if (rst || (init_state_r == INIT_OCLKDELAY_WRITE_WAIT) || (oclk_wr_cnt == 4'd0)) oclk_wr_cnt <= #TCQ NUM_STG1_WR_RD; else if ((init_state_r == INIT_OCLKDELAY_WRITE) && new_burst_r && ~phy_data_full) oclk_wr_cnt <= #TCQ oclk_wr_cnt - 1; // Write calibration requires multiple writes because // write can be up to 2 cycles early due to new write // leveling algorithm to avoid late writes always @(posedge clk) if (rst || (init_state_r == INIT_WRCAL_WRITE_READ) || (wrcal_wr_cnt == 4'd0)) wrcal_wr_cnt <= #TCQ NUM_STG1_WR_RD; else if ((init_state_r == INIT_WRCAL_WRITE) && new_burst_r && ~phy_data_full) wrcal_wr_cnt <= #TCQ wrcal_wr_cnt - 1; generate if(nCK_PER_CLK == 4) begin:back_to_back_reads_4_1 // 4 back-to-back reads with gaps for // read data_offset calibration (rdlvl stage 2) always @(posedge clk) if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) num_reads <= #TCQ 3'b000; else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) num_reads <= #TCQ num_reads - 1; else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || phy_cmd_full && new_burst_r) num_reads <= #TCQ 3'b011; end else if(nCK_PER_CLK == 2) begin: back_to_back_reads_2_1 // 4 back-to-back reads with gaps for // read data_offset calibration (rdlvl stage 2) always @(posedge clk) if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) num_reads <= #TCQ 3'b000; else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) num_reads <= #TCQ num_reads - 1; else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || phy_cmd_full && new_burst_r) num_reads <= #TCQ 3'b111; end endgenerate // back-to-back reads during write calibration always @(posedge clk) if (rst ||(init_state_r == INIT_WRCAL_READ_WAIT)) wrcal_reads <= #TCQ 2'b00; else if ((wrcal_reads > 2'b00) && ~(phy_ctl_full || phy_cmd_full)) wrcal_reads <= #TCQ wrcal_reads - 1; else if ((init_state_r == INIT_WRCAL_MULT_READS) || phy_ctl_full || phy_cmd_full && new_burst_r) wrcal_reads <= #TCQ 'd255; // determine how often to issue row command during read leveling writes // and reads always @(posedge clk) if (rdlvl_wr_rd) begin // 2:1 mode - every other command issued is a data command // 4:1 mode - every command issued is a data command if (nCK_PER_CLK == 2) begin if (!phy_ctl_full) new_burst_r <= #TCQ ~new_burst_r; end else new_burst_r <= #TCQ 1'b1; end else new_burst_r <= #TCQ 1'b1; // indicate when a write is occurring. PHY_WRDATA_EN must be asserted // simultaneous with the corresponding command/address for CWL = 5,6 always @(posedge clk) begin rdlvl_wr_r <= #TCQ rdlvl_wr; calib_wrdata_en <= #TCQ phy_wrdata_en; end always @(posedge clk) begin if (rst || wrcal_done) extend_cal_pat <= #TCQ 1'b0; else if (temp_lmr_done && (PRE_REV3ES == "ON")) extend_cal_pat <= #TCQ 1'b1; end generate if ((nCK_PER_CLK == 4) || (BURST_MODE == "4")) begin: wrdqen_div4 // Write data enable asserted for one DIV4 clock cycle // Only BL8 supported with DIV4. DDR2 BL4 will use DIV2. always @(*) begin if (~phy_data_full && ((init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_WRCAL_WRITE))) phy_wrdata_en = 1'b1; else phy_wrdata_en = 1'b0; end end else begin: wrdqen_div2 // block: wrdqen_div4 always @(*) if((rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full) | phy_wrdata_en_r1) phy_wrdata_en = 1'b1; else phy_wrdata_en = 1'b0; always @(posedge clk) phy_wrdata_en_r1 <= #TCQ rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full; always @(posedge clk) begin if (!phy_wrdata_en & first_rdlvl_pat_r) wrdata_pat_cnt <= #TCQ 2'b00; else if (wrdata_pat_cnt == 2'b11) wrdata_pat_cnt <= #TCQ 2'b10; else wrdata_pat_cnt <= #TCQ wrdata_pat_cnt + 1; end always @(posedge clk) begin if (!phy_wrdata_en & first_wrcal_pat_r) wrcal_pat_cnt <= #TCQ 2'b00; else if (extend_cal_pat && (wrcal_pat_cnt == 2'b01)) wrcal_pat_cnt <= #TCQ 2'b00; else if (wrcal_pat_cnt == 2'b11) wrcal_pat_cnt <= #TCQ 2'b10; else wrcal_pat_cnt <= #TCQ wrcal_pat_cnt + 1; end end endgenerate // indicate when a write is occurring. PHY_RDDATA_EN must be asserted // simultaneous with the corresponding command/address. PHY_RDDATA_EN // is used during read-leveling to determine read latency assign phy_rddata_en = ~phy_if_empty; // Read data valid generation for MC and User Interface after calibration is // complete assign phy_rddata_valid = init_complete_r1_timing ? phy_rddata_en : 1'b0; //*************************************************************************** // Generate training data written at start of each read-leveling stage // For every stage of read leveling, 8 words are written into memory // The format is as follows (shown as {rise,fall}): // Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0 // Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 //*************************************************************************** always @(posedge clk) if ((init_state_r == INIT_IDLE) || (init_state_r == INIT_RDLVL_STG1_WRITE)) cnt_init_data_r <= #TCQ 2'b00; else if (phy_wrdata_en) cnt_init_data_r <= #TCQ cnt_init_data_r + 1; else if (init_state_r == INIT_WRCAL_WRITE) cnt_init_data_r <= #TCQ 2'b10; // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling always @(posedge clk) if (rst || rdlvl_stg1_rank_done) first_rdlvl_pat_r <= #TCQ 1'b1; else if (phy_wrdata_en && (init_state_r == INIT_RDLVL_STG1_WRITE)) first_rdlvl_pat_r <= #TCQ 1'b0; always @(posedge clk) if (rst || wrcal_resume || (init_state_r == INIT_WRCAL_ACT_WAIT)) first_wrcal_pat_r <= #TCQ 1'b1; else if (phy_wrdata_en && (init_state_r == INIT_WRCAL_WRITE)) first_wrcal_pat_r <= #TCQ 1'b0; generate if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 2)) begin: wrdq_div2_2to1_rdlvl_first always @(posedge clk) if (~oclkdelay_calib_done) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}}; else if (!rdlvl_stg1_done) begin // The 16 words for stage 1 write data in 2:1 mode is written // over 4 consecutive controller clock cycles. Note that write // data follows phy_wrdata_en by one clock cycle case (wrdata_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}}, {DQ_WIDTH/4{4'h9}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end endcase end else if (!prbs_rdlvl_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ end else if (!wrcal_done) begin case (wrcal_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h5}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, {DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h4}}}; end endcase end end else if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 4)) begin: wrdq_div2_4to1_rdlvl_first always @(posedge clk) if (~oclkdelay_calib_done) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; else if (!rdlvl_stg1_done && ~phy_data_full) // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling if (first_rdlvl_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; else // For all others, change the first two words written in order // to differentiate the "early write" and "on-time write" // readback patterns during read leveling phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; else if (~(prbs_rdlvl_done || prbs_last_byte_done_r) && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ else if (!wrcal_done) if (first_wrcal_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (nCK_PER_CLK == 4) begin: wrdq_div1_4to1_wrcal_first always @(posedge clk) if ((~oclkdelay_calib_done) && (DRAM_TYPE == "DDR3")) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; else if ((!wrcal_done)&& (DRAM_TYPE == "DDR3")) begin if (extend_cal_pat) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else if (first_wrcal_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (!rdlvl_stg1_done && ~phy_data_full) begin // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling if (first_rdlvl_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; else // For all others, change the first two words written in order // to differentiate the "early write" and "on-time write" // readback patterns during read leveling phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (!prbs_rdlvl_done && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ else if (!complex_oclkdelay_calib_done && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; end else begin: wrdq_div1_2to1_wrcal_first always @(posedge clk) if ((~oclkdelay_calib_done)&& (DRAM_TYPE == "DDR3")) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}}; else if ((!wrcal_done) && (DRAM_TYPE == "DDR3"))begin case (wrcal_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h5}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, {DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h4}}}; end endcase end else if (!rdlvl_stg1_done) begin // The 16 words for stage 1 write data in 2:1 mode is written // over 4 consecutive controller clock cycles. Note that write // data follows phy_wrdata_en by one clock cycle case (wrdata_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}}, {DQ_WIDTH/4{4'h9}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end endcase end else if (!prbs_rdlvl_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ end else if (!complex_oclkdelay_calib_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; end end endgenerate //*************************************************************************** // Memory control/address //*************************************************************************** // Phases [2] and [3] are always deasserted for 4:1 mode generate if (nCK_PER_CLK == 4) begin: gen_div4_ca_tieoff always @(posedge clk) begin phy_ras_n[3:2] <= #TCQ 3'b11; phy_cas_n[3:2] <= #TCQ 3'b11; phy_we_n[3:2] <= #TCQ 3'b11; end end endgenerate // Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging // (4) auto refresh // verilint STARC-2.7.3.3b off generate if (!(CWL_M % 2)) begin: even_cwl always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT))begin phy_ras_n[0] <= #TCQ 1'b0; phy_ras_n[1] <= #TCQ 1'b1; end else begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b1; end end // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command // (3) auto refresh always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_REFRESH) || (rdlvl_wr_rd && new_burst_r))begin phy_cas_n[0] <= #TCQ 1'b0; phy_cas_n[1] <= #TCQ 1'b1; end else begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b1; end end // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only // occur during read leveling), (3) Issuing ZQ Long Calib command, // (4) Precharge always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE)|| (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (rdlvl_wr && new_burst_r))begin phy_we_n[0] <= #TCQ 1'b0; phy_we_n[1] <= #TCQ 1'b1; end else begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b1; end end end else begin: odd_cwl always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_REFRESH))begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b0; end else begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b1; end end // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command // (3) auto refresh always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_REFRESH) || (rdlvl_wr_rd && new_burst_r))begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b0; end else begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b1; end end // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only // occur during read leveling), (3) Issuing ZQ Long Calib command, // (4) Precharge always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE)|| (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (rdlvl_wr && new_burst_r))begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b0; end else begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b1; end end end endgenerate // verilint STARC-2.7.3.3b on // Assign calib_cmd for the command field in PHY_Ctl_Word always @(posedge clk) begin if (wr_level_dqs_asrt) begin // Request to toggle DQS during write leveling calib_cmd <= #TCQ 3'b001; if (CWL_M % 2) begin // odd write latency calib_data_offset_0 <= #TCQ CWL_M + 3; calib_data_offset_1 <= #TCQ CWL_M + 3; calib_data_offset_2 <= #TCQ CWL_M + 3; calib_cas_slot <= #TCQ 2'b01; end else begin // even write latency calib_data_offset_0 <= #TCQ CWL_M + 2; calib_data_offset_1 <= #TCQ CWL_M + 2; calib_data_offset_2 <= #TCQ CWL_M + 2; calib_cas_slot <= #TCQ 2'b00; end end else if (rdlvl_wr && new_burst_r) begin // Write Command calib_cmd <= #TCQ 3'b001; if (CWL_M % 2) begin // odd write latency calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_cas_slot <= #TCQ 2'b01; end else begin // even write latency calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_cas_slot <= #TCQ 2'b00; end end else if (rdlvl_rd && new_burst_r) begin // Read Command calib_cmd <= #TCQ 3'b011; if (CWL_M % 2) calib_cas_slot <= #TCQ 2'b01; else calib_cas_slot <= #TCQ 2'b00; if (~pi_calib_done_r1) begin calib_data_offset_0 <= #TCQ 6'd0; calib_data_offset_1 <= #TCQ 6'd0; calib_data_offset_2 <= #TCQ 6'd0; end else if (~pi_dqs_found_done_r1) begin calib_data_offset_0 <= #TCQ rd_data_offset_0; calib_data_offset_1 <= #TCQ rd_data_offset_1; calib_data_offset_2 <= #TCQ rd_data_offset_2; end else begin calib_data_offset_0 <= #TCQ rd_data_offset_ranks_0[6*chip_cnt_r+:6]; calib_data_offset_1 <= #TCQ rd_data_offset_ranks_1[6*chip_cnt_r+:6]; calib_data_offset_2 <= #TCQ rd_data_offset_ranks_2[6*chip_cnt_r+:6]; end end else begin // Non-Data Commands like NOP, MRS, ZQ Long Cal, Precharge, // Active, Refresh calib_cmd <= #TCQ 3'b100; calib_data_offset_0 <= #TCQ 6'd0; calib_data_offset_1 <= #TCQ 6'd0; calib_data_offset_2 <= #TCQ 6'd0; if (CWL_M % 2) calib_cas_slot <= #TCQ 2'b01; else calib_cas_slot <= #TCQ 2'b00; end end // Write Enable to PHY_Control FIFO always asserted // No danger of this FIFO being Full with 4:1 sync clock ratio // This is also the write enable to the command OUT_FIFO always @(posedge clk) begin if (rst) begin calib_ctl_wren <= #TCQ 1'b0; calib_cmd_wren <= #TCQ 1'b0; calib_seq <= #TCQ 2'b00; end else if (cnt_pwron_cke_done_r && phy_ctl_ready && ~(phy_ctl_full || phy_cmd_full )) begin calib_ctl_wren <= #TCQ 1'b1; calib_cmd_wren <= #TCQ 1'b1; calib_seq <= #TCQ calib_seq + 1; end else begin calib_ctl_wren <= #TCQ 1'b0; calib_cmd_wren <= #TCQ 1'b0; calib_seq <= #TCQ calib_seq; end end generate genvar rnk_i; for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk always @(posedge clk) begin if (rst) begin mr2_r[rnk_i] <= #TCQ 2'b00; mr1_r[rnk_i] <= #TCQ 3'b000; end else begin mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i]; mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i]; end end end endgenerate // ODT assignment based on slot config and slot present // For single slot systems slot_1_present input will be ignored // Assuming component interfaces to be single slot systems generate if (nSLOTS == 1) begin: gen_single_slot_odt always @(posedge clk) begin if (rst) begin tmp_mr2_r[1] <= #TCQ 2'b00; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; tmp_mr1_r[1] <= #TCQ 3'b000; tmp_mr1_r[2] <= #TCQ 3'b000; tmp_mr1_r[3] <= #TCQ 3'b000; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; phy_tmp_odt_r <= #TCQ 4'b0000; phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; end else begin case ({slot_0_present[0],slot_0_present[1], slot_0_present[2],slot_0_present[3]}) // Single slot configuration with quad rank // Assuming same behavior as single slot dual rank for now // DDR2 does not have quad rank parts 4'b1111: begin if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 RTT_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 RTT_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end phy_tmp_odt_r <= #TCQ 4'b0001; // Chip Select assignments phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) ) +: nCS_PER_RANK] <= #TCQ 'b0; end // Single slot configuration with single rank 4'b1000: begin phy_tmp_odt_r <= #TCQ 4'b0001; if ((REG_CTRL == "ON") && (nCS_PER_RANK > 1)) begin phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0; end else begin phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; end if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && ((cnt_init_mr_r == 2'd0) || (USE_ODT_PORT == 1)))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 RTT_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 RTT_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Single slot configuration with dual rank 4'b1100: begin phy_tmp_odt_r <= #TCQ 4'b0001; // Chip Select assignments phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) ) +: nCS_PER_RANK] <= #TCQ 'b0; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end default: begin phy_tmp_odt_r <= #TCQ 4'b0001; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end endcase end end end else if (nSLOTS == 2) begin: gen_dual_slot_odt always @ (posedge clk) begin if (rst) begin tmp_mr2_r[1] <= #TCQ 2'b00; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; tmp_mr1_r[1] <= #TCQ 3'b000; tmp_mr1_r[2] <= #TCQ 3'b000; tmp_mr1_r[3] <= #TCQ 3'b000; phy_tmp_odt_r <= #TCQ 4'b0000; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; end else begin case ({slot_0_present[0],slot_0_present[1], slot_1_present[0],slot_1_present[1]}) // Two slot configuration, one slot present, single rank 4'b10_00: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end 4'b00_10: begin //Rank1 ODT enabled if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank1 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank1 Rtt_NOM defaults to 120 ohms tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Two slot configuration, one slot present, dual rank 4'b00_11: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end 4'b11_00: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank1 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Two slot configuration, one rank per slot 4'b10_10: begin if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r == 2'b00)begin phy_tmp_odt_r <= #TCQ 4'b0010; //bit0 for rank0 end else begin phy_tmp_odt_r <= #TCQ 4'b0001; //bit0 for rank0 end end else begin if((init_state_r == INIT_WRLVL_WAIT) || (init_next_state == INIT_RDLVL_STG1_WRITE) || (init_next_state == INIT_WRCAL_WRITE) || (init_next_state == INIT_OCAL_CENTER_WRITE) || (init_next_state == INIT_OCLKDELAY_WRITE)) phy_tmp_odt_r <= #TCQ 4'b0011; // bit0 for rank0/1 (write) else if ((init_next_state == INIT_PI_PHASELOCK_READS) || (init_next_state == INIT_MPR_READ) || (init_next_state == INIT_RDLVL_STG1_READ) || (init_next_state == INIT_RDLVL_COMPLEX_READ) || (init_next_state == INIT_RDLVL_STG2_READ) || (init_next_state == INIT_OCLKDELAY_READ) || (init_next_state == INIT_WRCAL_READ) || (init_next_state == INIT_WRCAL_MULT_READS)) phy_tmp_odt_r <= #TCQ 4'b0010; // bit0 for rank1 (rank 0 rd) end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_WR == "60") ? 3'b001 : (RTT_WR == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; end end // Two Slots - One slot with dual rank and other with single rank 4'b10_11: begin //Rank3 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[1] <= #TCQ 3'b000; end //Slot1 Rank1 or Rank3 is being written if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r == 2'b00)begin phy_tmp_odt_r <= #TCQ 4'b0010; end else begin phy_tmp_odt_r <= #TCQ 4'b0001; end end else begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0011; //Slot0 Rank0 is being written end else begin phy_tmp_odt_r <= #TCQ 4'b0101; // ODT for ranks 0 and 2 aserted end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))begin if (chip_cnt_r == 2'b00) begin phy_tmp_odt_r <= #TCQ 4'b0100; end else begin phy_tmp_odt_r <= #TCQ 4'b0001; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end // Two Slots - One slot with dual rank and other with single rank 4'b11_10: begin //Rank2 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : (RTT_NOM2 == "120") ? 3'b010 : (RTT_NOM2 == "20") ? 3'b100 : (RTT_NOM2 == "30") ? 3'b101 : (RTT_NOM2 == "40") ? 3'b011: 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011: 3'b000; //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r[1] == 1'b1)begin phy_tmp_odt_r <= #TCQ 4'b0001; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; // rank 2 ODT asserted end end else begin if (// wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin if (chip_cnt_r[1] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0110; end else begin phy_tmp_odt_r <= #TCQ 4'b0101; end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS)) begin if (chip_cnt_r[1] == 1'b1) begin phy_tmp_odt_r[(1*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ 4'b0010; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end // Two Slots - two ranks per slot 4'b11_11: begin //Rank2 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : (RTT_NOM2 == "120") ? 3'b010 : (RTT_NOM2 == "20") ? 3'b100 : (RTT_NOM2 == "30") ? 3'b101 : (RTT_NOM2 == "40") ? 3'b011 : 3'b000; //Rank3 Rtt_NOM tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 : (RTT_NOM3 == "120") ? 3'b010 : (RTT_NOM3 == "20") ? 3'b100 : (RTT_NOM3 == "30") ? 3'b101 : (RTT_NOM3 == "40") ? 3'b011 : 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[1] <= #TCQ 3'b000; //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r[1] == 1'b1)begin phy_tmp_odt_r <= #TCQ 4'b0001; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; end end else begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin //Slot1 Rank1 or Rank3 is being written if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0110; //Slot0 Rank0 or Rank2 is being written end else begin phy_tmp_odt_r <= #TCQ 4'b1001; end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))begin //Slot1 Rank1 or Rank3 is being read if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0100; //Slot0 Rank0 or Rank2 is being read end else begin phy_tmp_odt_r <= #TCQ 4'b1000; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end default: begin phy_tmp_odt_r <= #TCQ 4'b1111; // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "60") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; end end endcase end end end endgenerate // PHY only supports two ranks. // calib_aux_out[0] is CKE for rank 0 and calib_aux_out[1] is ODT for rank 0 // calib_aux_out[2] is CKE for rank 1 and calib_aux_out[3] is ODT for rank 1 generate if(CKE_ODT_AUX == "FALSE") begin if ((nSLOTS == 1) && (RANKS < 2)) begin always @(posedge clk) if (rst) begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || wrlvl_rank_done || wrlvl_rank_done_r1 || (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt ) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || complex_odt_ext || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_OCAL_CENTER_WRITE) || complex_ocal_odt_ext || (init_state_r == INIT_OCLKDELAY_WRITE)|| (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin // Quad rank in a single slot calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end end end else if ((nSLOTS == 1) && (RANKS <= 2)) begin always @(posedge clk) if (rst) begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt)|| (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || complex_odt_ext || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_OCAL_CENTER_WRITE) || complex_ocal_odt_ext || (init_state_r == INIT_OCLKDELAY_WRITE)|| (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin // Dual rank in a single slot calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end end end else if ((nSLOTS == 2) && (RANKS == 2)) begin always @(posedge clk) if (rst)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if (((DRAM_TYPE == "DDR2") && (RTT_NOM == "DISABLED")) || ((DRAM_TYPE == "DDR3") && (RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // Quad rank in a single slot if (nCK_PER_CLK == 2) begin calib_odt[0] <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; calib_odt[1] <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end // Turn on for idle rank during read if dynamic ODT is enabled in DDR3 end else if(((DRAM_TYPE == "DDR3") && (RTT_WR != "OFF")) && ((init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_MPR_READ) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))) begin if (nCK_PER_CLK == 2) begin calib_odt[0] <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; calib_odt[1] <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end // disable well before next command and before disabling write leveling end else if(cnt_cmd_done_m7_r || (init_state_r == INIT_WRLVL_WAIT && ~wrlvl_odt)) calib_odt <= #TCQ 2'b00; end end end else begin//USE AUX OUTPUT for routing CKE and ODT. if ((nSLOTS == 1) && (RANKS < 2)) begin always @(posedge clk) if (rst) begin calib_aux_out <= #TCQ 4'b0000; end else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done || wrlvl_rank_done_r1 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Quad rank in a single slot calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end else if ((nSLOTS == 1) && (RANKS <= 2)) begin always @(posedge clk) if (rst) begin calib_aux_out <= #TCQ 4'b0000; end else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Dual rank in a single slot calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end else if ((nSLOTS == 2) && (RANKS == 2)) begin always @(posedge clk) if (rst) calib_aux_out <= #TCQ 4'b0000; else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Quad rank in a single slot if (nCK_PER_CLK == 2) begin calib_aux_out[1] <= #TCQ (!calib_aux_out[1]) ? phy_tmp_odt_r[0] : 1'b0; calib_aux_out[3] <= #TCQ (!calib_aux_out[3]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end end endgenerate //***************************************************************** // memory address during init //***************************************************************** always @(posedge clk) phy_data_full_r <= #TCQ phy_data_full; // verilint STARC-2.7.3.3b off always @(*)begin // Bus 0 for address/bank never used address_w = 'b0; bank_w = 'b0; if ((init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_DDR2_PRECHARGE)) begin // Set A10=1 for ZQ long calibration or Precharge All address_w = 'b0; address_w[10] = 1'b1; bank_w = 'b0; end else if (init_state_r == INIT_WRLVL_START) begin // Enable wrlvl in MR1 bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; address_w[7] = 1'b1; end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin // Finished with write leveling, disable wrlvl in MR1 // For single rank disable Rtt_Nom bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin // Set RTT_WR in MR2 after write leveling disabled bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; address_w[10:9] = mr2_r[chip_cnt_r]; end else if (init_state_r == INIT_MPR_READ) begin address_w = 'b0; bank_w = 'b0; end else if (init_state_r == INIT_MPR_RDEN) begin // Enable MPR read with LMR3 and A2=1 bank_w[BANK_WIDTH-1:0] = 'd3; address_w = {ROW_WIDTH{1'b0}}; address_w[2] = 1'b1; end else if (init_state_r == INIT_MPR_DISABLE) begin // Disable MPR read with LMR3 and A2=0 bank_w[BANK_WIDTH-1:0] = 'd3; address_w = {ROW_WIDTH{1'b0}}; end else if ((init_state_r == INIT_REG_WRITE)& (DRAM_TYPE == "DDR3"))begin // bank_w is assigned a 3 bit value. In some // DDR2 cases there will be only two bank bits. //Qualifying the condition with DDR3 bank_w = 'b0; address_w = 'b0; case (reg_ctrl_cnt_r) 4'h1:begin address_w[4:0] = REG_RC1[4:0]; bank_w = REG_RC1[7:5]; end 4'h2: address_w[4:0] = REG_RC2[4:0]; 4'h3: begin address_w[4:0] = REG_RC3[4:0]; bank_w = REG_RC3[7:5]; end 4'h4: begin address_w[4:0] = REG_RC4[4:0]; bank_w = REG_RC4[7:5]; end 4'h5: begin address_w[4:0] = REG_RC5[4:0]; bank_w = REG_RC5[7:5]; end 4'h6: begin address_w[4:0] = REG_RC10[4:0]; bank_w = REG_RC10[7:5]; end 4'h7: begin address_w[4:0] = REG_RC11[4:0]; bank_w = REG_RC11[7:5]; end default: address_w[4:0] = REG_RC0[4:0]; endcase end else if (init_state_r == INIT_LOAD_MR) begin // If loading mode register, look at cnt_init_mr to determine // which MR is currently being programmed address_w = 'b0; bank_w = 'b0; if(DRAM_TYPE == "DDR3")begin if(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done)begin // end of the calibration programming correct // burst length if (TEST_AL == "0") begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //Don't reset DLL end else begin // programming correct AL value bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; if (TEST_AL == "CL-1") address_w[4:3]= 2'b01; // AL="CL-1" else address_w[4:3]= 2'b10; // AL="CL-2" end end else begin case (cnt_init_mr_r) INIT_CNT_MR2: begin bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; address_w[10:9] = mr2_r[chip_cnt_r]; end INIT_CNT_MR3: begin bank_w[1:0] = 2'b11; address_w = load_mr3[ROW_WIDTH-1:0]; end INIT_CNT_MR1: begin bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; end INIT_CNT_MR0: begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; // fixing it to BL8 for calibration address_w[1:0] = 2'b00; end default: begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end endcase end end else begin // DDR2 case (cnt_init_mr_r) INIT_CNT_MR2: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //MRS command without resetting DLL end end INIT_CNT_MR3: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b11; address_w = load_mr3[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //MRS command without resetting DLL. Repeted again // because there is an extra state. end end INIT_CNT_MR1: begin bank_w[1:0] = 2'b01; if(~ddr2_refresh_flag_r)begin address_w = load_mr1[ROW_WIDTH-1:0]; end else begin // second set of lm commands address_w = load_mr1[ROW_WIDTH-1:0]; address_w[9:7] = 3'b111; //OCD default state end end INIT_CNT_MR0: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin // always disable odt for rank 1 and rank 3 as per SPEC address_w[2] = 'b0; address_w[6] = 'b0; end //OCD exit end end default: begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end endcase end end else if ( ~prbs_rdlvl_done && ((init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin // Writing and reading PRBS pattern for read leveling stage 1 // Need to support burst length 4 or 8. PRBS pattern will be // written to entire row and read back from the same row repeatedly bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (((stg1_wr_rd_cnt == NUM_STG1_WR_RD) && ~rdlvl_stg1_done) || (stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd22) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; end else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ) )// || // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; else address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end //need to add address for complex oclkdelay calib end else if (prbs_rdlvl_done && ((init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if ((stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd30) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; end else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (init_state_r1 != INIT_RDLVL_STG1_WRITE) ) // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; else address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end end else if ((init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_READ)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (oclk_wr_cnt == NUM_STG1_WR_RD) address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((oclk_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end else if ((init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_READ)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (wrcal_wr_cnt == NUM_STG1_WR_RD) address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((wrcal_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end else if ((init_state_r == INIT_WRCAL_MULT_READS) || (init_state_r == INIT_RDLVL_STG2_READ)) begin // when writing or reading back training pattern for read leveling stage2 // need to support burst length of 4 or 8. This may mean issuing // multiple commands to cover the entire range of addresses accessed // during read leveling. // Hard coding A[12] to 1 so that it will always be burst length of 8 // for DDR3. Does not have any effect on DDR2. bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; address_w[COL_WIDTH-1:0] = {CALIB_COL_ADD[COL_WIDTH-1:3],burst_addr_r, 3'b000}; address_w[12] = 1'b1; end else if ((init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_OCLKDELAY_ACT)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; //if (stg1_wr_rd_cnt == 'd22) // address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0] + 1; //else address_w = prbs_rdlvl_done ? CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt_ocal : CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt; end else begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end end // verilint STARC-2.7.3.3b on // registring before sending out generate genvar r,s; if ((DRAM_TYPE != "DDR3") || (CA_MIRROR != "ON")) begin: gen_no_mirror for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: div_clk_loop always @(posedge clk) begin phy_address[(r*ROW_WIDTH) +: ROW_WIDTH] <= #TCQ address_w; phy_bank[(r*BANK_WIDTH) +: BANK_WIDTH] <= #TCQ bank_w; end end end else begin: gen_mirror // Control/addressing mirroring (optional for DDR3 dual rank DIMMs) // Mirror for the 2nd rank only. Logic needs to be enhanced to account // for multiple slots, currently only supports one slot, 2-rank config for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_ba_div_clk_loop for (s = 0; s < BANK_WIDTH; s = s + 1) begin: gen_ba always @(posedge clk) if (chip_cnt_r == 2'b00) begin phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[s]; end else begin phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[(s == 0) ? 1 : ((s == 1) ? 0 : s)]; end end end for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_addr_div_clk_loop for (s = 0; s < ROW_WIDTH; s = s + 1) begin: gen_addr always @(posedge clk) if (chip_cnt_r == 2'b00) begin phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[s]; end else begin phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[ (s == 3) ? 4 : ((s == 4) ? 3 : ((s == 5) ? 6 : ((s == 6) ? 5 : ((s == 7) ? 8 : ((s == 8) ? 7 : s)))))]; end end end end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_init.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Memory initialization and overall master state control during // initialization and calibration. Specifically, the following functions // are performed: // 1. Memory initialization (initial AR, mode register programming, etc.) // 2. Initiating write leveling // 3. Generate training pattern writes for read leveling. Generate // memory readback for read leveling. // This module has an interface for providing control/address and write // data to the PHY Control Block during initialization/calibration. // Once initialization and calibration are complete, control is passed to the MC. // //Reference: //Revision History: // //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_init.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ **$Date: 2011/06/02 08:35:09 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_init.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_init # ( parameter tCK = 1500, // DDRx SDRAM clock period parameter TCQ = 100, parameter nCK_PER_CLK = 4, // # of memory clocks per CLK parameter CLK_PERIOD = 3000, // Logic (internal) clk period (in ps) parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA // 1 - ODT output from FPGA parameter DDR3_VDD_OP_VOLT = "150", // Voltage mode used for DDR3 // 150 - 1.50 V // 135 - 1.35 V // 125 - 1.25 V parameter VREF = "EXTERNAL", // Internal or external Vref parameter PRBS_WIDTH = 8, // PRBS sequence = 2^PRBS_WIDTH parameter BANK_WIDTH = 2, parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank parameter COL_WIDTH = 10, parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for // component I/F with CS_WIDTH=1, // nCS_PER_RANK=# of components parameter DQ_WIDTH = 64, parameter DQS_WIDTH = 8, parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter ROW_WIDTH = 14, parameter CS_WIDTH = 1, parameter RANKS = 1, // # of memory ranks in the interface parameter CKE_WIDTH = 1, // # of cke outputs parameter DRAM_TYPE = "DDR3", parameter REG_CTRL = "ON", parameter ADDR_CMD_MODE= "1T", // calibration Address parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address parameter CALIB_COL_ADD = 12'h000, // Calibration column address parameter CALIB_BA_ADD = 3'h0, // Calibration bank address // DRAM mode settings parameter AL = "0", // Additive Latency option parameter BURST_MODE = "8", // Burst length parameter BURST_TYPE = "SEQ", // Burst type // parameter nAL = 0, // Additive latency (in clk cyc) parameter nCL = 5, // Read CAS latency (in clk cyc) parameter nCWL = 5, // Write CAS latency (in clk cyc) parameter tRFC = 110000, // Refresh-to-command delay (in ps) parameter REFRESH_TIMER = 1553, // Refresh interval in fabrci cycles between 8 posted refreshes parameter REFRESH_TIMER_WIDTH = 8, parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option parameter RTT_NOM = "60", // Nominal ODT termination value parameter RTT_WR = "60", // Write ODT termination value parameter WRLVL = "ON", // Enable write leveling // parameter PHASE_DETECT = "ON", // Enable read phase detector parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter nSLOTS = 1, // Number of DIMM SLOTs in the system parameter SIM_INIT_OPTION = "NONE", // "NONE", "SKIP_PU_DLY", "SKIP_INIT" parameter SIM_CAL_OPTION = "NONE", // "NONE", "FAST_CAL", "SKIP_CAL" parameter CKE_ODT_AUX = "FALSE", parameter PRE_REV3ES = "OFF", // Enable TG error detection during calibration parameter TEST_AL = "0", // Internal use for ICM verification parameter FIXED_VICTIM = "TRUE", parameter BYPASS_COMPLEX_OCAL = "FALSE" ) ( input clk, input rst, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o, input delay_incdec_done, input ck_addr_cmd_delay_done, input pi_phase_locked_all, input pi_dqs_found_done, input dqsfound_retry, input dqs_found_prech_req, output reg pi_phaselock_start, output pi_phase_locked_err, output pi_calib_done, input phy_if_empty, // Read/write calibration interface input wrlvl_done, input wrlvl_rank_done, input wrlvl_byte_done, input wrlvl_byte_redo, input wrlvl_final, output reg wrlvl_final_if_rst, input oclkdelay_calib_done, input oclk_prech_req, input oclk_calib_resume, input lim_done, input lim_wr_req, output reg oclkdelay_calib_start, //complex oclkdelay calibration input complex_oclkdelay_calib_done, input complex_oclk_prech_req, input complex_oclk_calib_resume, output reg complex_oclkdelay_calib_start, input [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt, // same as oclkdelay_calib_cnt output reg complex_ocal_num_samples_inc, input complex_ocal_num_samples_done_r, input [2:0] complex_ocal_rd_victim_sel, output reg complex_ocal_reset_rd_addr, input complex_ocal_ref_req, output reg complex_ocal_ref_done, input done_dqs_tap_inc, input [5:0] rd_data_offset_0, input [5:0] rd_data_offset_1, input [5:0] rd_data_offset_2, input [6*RANKS-1:0] rd_data_offset_ranks_0, input [6*RANKS-1:0] rd_data_offset_ranks_1, input [6*RANKS-1:0] rd_data_offset_ranks_2, input pi_dqs_found_rank_done, input wrcal_done, input wrcal_prech_req, input wrcal_read_req, input wrcal_act_req, input temp_wrcal_done, input [7:0] slot_0_present, input [7:0] slot_1_present, output reg wl_sm_start, output reg wr_lvl_start, output reg wrcal_start, output reg wrcal_rd_wait, output reg wrcal_sanity_chk, output reg tg_timer_done, output reg no_rst_tg_mc, input rdlvl_stg1_done, input rdlvl_stg1_rank_done, output reg rdlvl_stg1_start, output reg pi_dqs_found_start, output reg detect_pi_found_dqs, // rdlvl stage 1 precharge requested after each DQS input rdlvl_prech_req, input rdlvl_last_byte_done, input wrcal_resume, input wrcal_sanity_chk_done, // MPR read leveling input mpr_rdlvl_done, input mpr_rnk_done, input mpr_last_byte_done, output reg mpr_rdlvl_start, output reg mpr_end_if_reset, // PRBS Read Leveling input prbs_rdlvl_done, input prbs_last_byte_done, input prbs_rdlvl_prech_req, input complex_victim_inc, input [2:0] rd_victim_sel, input [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt, output reg [2:0] victim_sel, output reg [DQS_CNT_WIDTH:0]victim_byte_cnt, output reg prbs_rdlvl_start, output reg prbs_gen_clk_en, output reg prbs_gen_oclk_clk_en, output reg complex_sample_cnt_inc, output reg complex_sample_cnt_inc_ocal, output reg complex_wr_done, // Signals shared btw multiple calibration stages output reg prech_done, // Data select / status output reg init_calib_complete, // Signal to mask memory model error for Invalid latching edge output reg calib_writes, // PHY address/control // 2 commands to PHY Control Block per div 2 clock in 2:1 mode // 4 commands to PHY Control Block per div 4 clock in 4:1 mode output reg [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address, output reg [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank, output reg [nCK_PER_CLK-1:0] phy_ras_n, output reg [nCK_PER_CLK-1:0] phy_cas_n, output reg [nCK_PER_CLK-1:0] phy_we_n, output reg phy_reset_n, output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n, // Hard PHY Interface signals input phy_ctl_ready, input phy_ctl_full, input phy_cmd_full, input phy_data_full, output reg calib_ctl_wren, output reg calib_cmd_wren, output reg [1:0] calib_seq, output reg write_calib, output reg read_calib, // PHY_Ctl_Wd output reg [2:0] calib_cmd, // calib_aux_out used for CKE and ODT output reg [3:0] calib_aux_out, output reg [1:0] calib_odt , output reg [nCK_PER_CLK-1:0] calib_cke , output [1:0] calib_rank_cnt, output reg [1:0] calib_cas_slot, output reg [5:0] calib_data_offset_0, output reg [5:0] calib_data_offset_1, output reg [5:0] calib_data_offset_2, // PHY OUT_FIFO output reg calib_wrdata_en, output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata, // PHY Read output phy_rddata_en, output phy_rddata_valid, output [255:0] dbg_phy_init, input read_pause, input reset_rd_addr, //OCAL centering calibration input oclkdelay_center_calib_start, input oclk_center_write_resume, input oclkdelay_center_calib_done ); //***************************************************************************** // Assertions to be added //***************************************************************************** // The phy_ctl_full signal must never be asserted in synchronous mode of // operation either 4:1 or 2:1 // // The RANKS parameter must never be set to '0' by the user // valid values: 1 to 4 // //***************************************************************************** //*************************************************************************** // Number of Read level stage 1 writes limited to a SDRAM row // The address of Read Level stage 1 reads must also be limited // to a single SDRAM row // (2^COL_WIDTH)/BURST_MODE = (2^10)/8 = 128 localparam NUM_STG1_WR_RD = (BURST_MODE == "8") ? 4 : (BURST_MODE == "4") ? 8 : 4; localparam ADDR_INC = (BURST_MODE == "8") ? 8 : (BURST_MODE == "4") ? 4 : 8; // In a 2 slot dual rank per system RTT_NOM values // for Rank2 and Rank3 default to 40 ohms localparam RTT_NOM2 = "40"; localparam RTT_NOM3 = "40"; localparam RTT_NOM_int = (USE_ODT_PORT == 1) ? RTT_NOM : RTT_WR; // Specifically for use with half-frequency controller (nCK_PER_CLK=2) // = 1 if burst length = 4, = 0 if burst length = 8. Determines how // often row command needs to be issued during read-leveling // For DDR3 the burst length is fixed during calibration localparam BURST4_FLAG = (DRAM_TYPE == "DDR3")? 1'b0 : (BURST_MODE == "8") ? 1'b0 : ((BURST_MODE == "4") ? 1'b1 : 1'b0); //*************************************************************************** // Counter values used to determine bus timing // NOTE on all counter terminal counts - these can/should be one less than // the actual delay to take into account extra clock cycle delay in // generating the corresponding "done" signal //*************************************************************************** localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK; // Calculate initial delay required in number of CLK clock cycles // to delay initially. The counter is clocked by [CLK/1024] - which // is approximately division by 1000 - note that the formulas below will // result in more than the minimum wait time because of this approximation. // NOTE: For DDR3 JEDEC specifies to delay reset // by 200us, and CKE by an additional 500us after power-up // For DDR2 CKE is delayed by 200us after power up. localparam DDR3_RESET_DELAY_NS = 200000; localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS; localparam DDR2_CKE_DELAY_NS = 200000; localparam PWRON_RESET_DELAY_CNT = ((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD); localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == "DDR3") ? (((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) : (((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)); // FOR DDR2 -1 taken out. With -1 not getting 200us. The equation // needs to be reworked. localparam DDR2_INIT_PRE_DELAY_PS = 400000; localparam DDR2_INIT_PRE_CNT = ((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1; // Calculate tXPR time: reset from CKE HIGH to valid command after power-up // tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock // cycles because this counter actually starts up before CKE is asserted // to memory. localparam TXPR_DELAY_CNT = (5*CLK_MEM_PERIOD > tRFC+10000) ? (((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+11 : (((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+11; // tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV localparam TDLLK_TZQINIT_DELAY_CNT = 255; // TWR values in ns. Both DDR2 and DDR3 have the same value. // 15000ns/tCK localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ? (15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD; // time to wait between consecutive commands in PHY_INIT - this is a // generic number, and must be large enough to account for worst case // timing parameter (tRFC - refresh-to-active) across all memory speed // grades and operating frequencies. Expressed in clk // (Divided by 4 or Divided by 2) clock cycles. localparam CNTNEXT_CMD = 7'b1111111; // Counter values to keep track of which MR register to load during init // Set value of INIT_CNT_MR_DONE to equal value of counter for last mode // register configured during initialization. // NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init localparam INIT_CNT_MR2 = 2'b00; localparam INIT_CNT_MR3 = 2'b01; localparam INIT_CNT_MR1 = 2'b10; localparam INIT_CNT_MR0 = 2'b11; localparam INIT_CNT_MR_DONE = 2'b11; // Register chip programmable values for DDR3 // The register chip for the registered DIMM needs to be programmed // before the initialization of the registered DIMM. // Address for the control word is in : DBA2, DA2, DA1, DA0 // Data for the control word is in: DBA1 DBA0, DA4, DA3 // The values will be stored in the local param in the following format // {DBA[2:0], DA[4:0]} // RC0 is global features control word. Address == 000 localparam REG_RC0 = 8'b00000000; // RC1 Clock driver enable control word. Enables or disables the four // output clocks in the register chip. For single rank and dual rank // two clocks will be enabled and for quad rank all the four clocks // will be enabled. Address == 000. Data = 0110 for single and dual rank. // = 0000 for quad rank localparam REG_RC1 = 8'b00000001; // RC2 timing control word. Set in 1T timing mode // Address = 010. Data = 0000 localparam REG_RC2 = 8'b00000010; // RC3 timing control word. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC3 = (RANKS >= 2) ? 8'b00101011 : 8'b00000011; // RC4 timing control work. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC4 = (RANKS >= 2) ? 8'b00101100 : 8'b00000100; // RC5 timing control work. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC5 = (RANKS >= 2) ? 8'b00101101 : 8'b00000101; // RC10 timing control work. Setting the data to 0000 localparam [3:0] FREQUENCY_ENCODING = (tCK >= 1072 && tCK < 1250) ? 4'b0100 : (tCK >= 1250 && tCK < 1500) ? 4'b0011 : (tCK >= 1500 && tCK < 1875) ? 4'b0010 : (tCK >= 1875 && tCK < 2500) ? 4'b0001 : 4'b0000; localparam REG_RC10 = {1'b1,FREQUENCY_ENCODING,3'b010}; localparam VREF_ENCODING = (VREF == "INTERNAL") ? 1'b1 : 1'b0; localparam [3:0] DDR3_VOLTAGE_ENCODING = (DDR3_VDD_OP_VOLT == "125") ? {1'b0,VREF_ENCODING,2'b10} : (DDR3_VDD_OP_VOLT == "135") ? {1'b0,VREF_ENCODING,2'b01} : {1'b0,VREF_ENCODING,2'b00} ; localparam REG_RC11 = {1'b1,DDR3_VOLTAGE_ENCODING,3'b011}; // For non-zero AL values localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; // Adding the register dimm latency to write latency localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; // Count value to generate pi_phase_locked_err signal localparam PHASELOCKED_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 16383 : 1000; // Timeout interval for detecting error with Traffic Generator localparam [13:0] TG_TIMER_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 14'h3FFF : 14'h0001; //bit num per DQS localparam DQ_PER_DQS = DQ_WIDTH/DQS_WIDTH; //COMPLEX_ROW_CNT_BYTE localparam COMPLEX_ROW_CNT_BYTE = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS*2: 2; localparam COMPLEX_RD = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS : 1; // Master state machine encoding localparam INIT_IDLE = 7'b0000000; //0 localparam INIT_WAIT_CKE_EXIT = 7'b0000001; //1 localparam INIT_LOAD_MR = 7'b0000010; //2 localparam INIT_LOAD_MR_WAIT = 7'b0000011; //3 localparam INIT_ZQCL = 7'b0000100; //4 localparam INIT_WAIT_DLLK_ZQINIT = 7'b0000101; //5 localparam INIT_WRLVL_START = 7'b0000110; //6 localparam INIT_WRLVL_WAIT = 7'b0000111; //7 localparam INIT_WRLVL_LOAD_MR = 7'b0001000; //8 localparam INIT_WRLVL_LOAD_MR_WAIT = 7'b0001001; //9 localparam INIT_WRLVL_LOAD_MR2 = 7'b0001010; //A localparam INIT_WRLVL_LOAD_MR2_WAIT = 7'b0001011; //B localparam INIT_RDLVL_ACT = 7'b0001100; //C localparam INIT_RDLVL_ACT_WAIT = 7'b0001101; //D localparam INIT_RDLVL_STG1_WRITE = 7'b0001110; //E localparam INIT_RDLVL_STG1_WRITE_READ = 7'b0001111; //F localparam INIT_RDLVL_STG1_READ = 7'b0010000; //10 localparam INIT_RDLVL_STG2_READ = 7'b0010001; //11 localparam INIT_RDLVL_STG2_READ_WAIT = 7'b0010010; //12 localparam INIT_PRECHARGE_PREWAIT = 7'b0010011; //13 localparam INIT_PRECHARGE = 7'b0010100; //14 localparam INIT_PRECHARGE_WAIT = 7'b0010101; //15 localparam INIT_DONE = 7'b0010110; //16 localparam INIT_DDR2_PRECHARGE = 7'b0010111; //17 localparam INIT_DDR2_PRECHARGE_WAIT = 7'b0011000; //18 localparam INIT_REFRESH = 7'b0011001; //19 localparam INIT_REFRESH_WAIT = 7'b0011010; //1A localparam INIT_REG_WRITE = 7'b0011011; //1B localparam INIT_REG_WRITE_WAIT = 7'b0011100; //1C localparam INIT_DDR2_MULTI_RANK = 7'b0011101; //1D localparam INIT_DDR2_MULTI_RANK_WAIT = 7'b0011110; //1E localparam INIT_WRCAL_ACT = 7'b0011111; //1F localparam INIT_WRCAL_ACT_WAIT = 7'b0100000; //20 localparam INIT_WRCAL_WRITE = 7'b0100001; //21 localparam INIT_WRCAL_WRITE_READ = 7'b0100010; //22 localparam INIT_WRCAL_READ = 7'b0100011; //23 localparam INIT_WRCAL_READ_WAIT = 7'b0100100; //24 localparam INIT_WRCAL_MULT_READS = 7'b0100101; //25 localparam INIT_PI_PHASELOCK_READS = 7'b0100110; //26 localparam INIT_MPR_RDEN = 7'b0100111; //27 localparam INIT_MPR_WAIT = 7'b0101000; //28 localparam INIT_MPR_READ = 7'b0101001; //29 localparam INIT_MPR_DISABLE_PREWAIT = 7'b0101010; //2A localparam INIT_MPR_DISABLE = 7'b0101011; //2B localparam INIT_MPR_DISABLE_WAIT = 7'b0101100; //2C localparam INIT_OCLKDELAY_ACT = 7'b0101101; //2D localparam INIT_OCLKDELAY_ACT_WAIT = 7'b0101110; //2E localparam INIT_OCLKDELAY_WRITE = 7'b0101111; //2F localparam INIT_OCLKDELAY_WRITE_WAIT = 7'b0110000; //30 localparam INIT_OCLKDELAY_READ = 7'b0110001; //31 localparam INIT_OCLKDELAY_READ_WAIT = 7'b0110010; //32 localparam INIT_REFRESH_RNK2_WAIT = 7'b0110011; //33 localparam INIT_RDLVL_COMPLEX_PRECHARGE = 7'b0110100; //34 localparam INIT_RDLVL_COMPLEX_PRECHARGE_WAIT = 7'b0110101; //35 localparam INIT_RDLVL_COMPLEX_ACT = 7'b0110110; //36 localparam INIT_RDLVL_COMPLEX_ACT_WAIT = 7'b0110111; //37 localparam INIT_RDLVL_COMPLEX_READ = 7'b0111000; //38 localparam INIT_RDLVL_COMPLEX_READ_WAIT = 7'b0111001; //39 localparam INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT = 7'b0111010; //3A localparam INIT_OCAL_COMPLEX_ACT = 7'b0111011; //3B localparam INIT_OCAL_COMPLEX_ACT_WAIT = 7'b0111100; //3C localparam INIT_OCAL_COMPLEX_WRITE_WAIT = 7'b0111101; //3D localparam INIT_OCAL_COMPLEX_RESUME_WAIT = 7'b0111110; //3E localparam INIT_OCAL_CENTER_ACT = 7'b0111111; //3F localparam INIT_OCAL_CENTER_WRITE = 7'b1000000; //40 localparam INIT_OCAL_CENTER_WRITE_WAIT = 7'b1000001; //41 localparam INIT_OCAL_CENTER_ACT_WAIT = 7'b1000010; //42 integer i, j, k, l, m, n, p, q; reg pi_dqs_found_all_r; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r1; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r2; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r3; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r4; reg pi_calib_rank_done_r; reg [13:0] pi_phaselock_timer; reg stg1_wr_done; reg rnk_ref_cnt; reg pi_dqs_found_done_r1; reg pi_dqs_found_rank_done_r; reg read_calib_int; reg read_calib_r; reg pi_calib_done_r; reg pi_calib_done_r1; reg burst_addr_r; reg [1:0] chip_cnt_r; reg [6:0] cnt_cmd_r; reg cnt_cmd_done_r; reg cnt_cmd_done_m7_r; reg [7:0] cnt_dllk_zqinit_r; reg cnt_dllk_zqinit_done_r; reg cnt_init_af_done_r; reg [1:0] cnt_init_af_r; reg [1:0] cnt_init_data_r; reg [1:0] cnt_init_mr_r; reg cnt_init_mr_done_r; reg cnt_init_pre_wait_done_r; reg [7:0] cnt_init_pre_wait_r; reg [9:0] cnt_pwron_ce_r; reg cnt_pwron_cke_done_r; reg cnt_pwron_cke_done_r1; reg [8:0] cnt_pwron_r; reg cnt_pwron_reset_done_r; reg cnt_txpr_done_r; reg [7:0] cnt_txpr_r; reg ddr2_pre_flag_r; reg ddr2_refresh_flag_r; reg ddr3_lm_done_r; reg [4:0] enable_wrlvl_cnt; reg init_complete_r; reg init_complete_r1; reg init_complete_r2; (* keep = "true" *) reg init_complete_r_timing; (* keep = "true" *) reg init_complete_r1_timing; reg [6:0] init_next_state; reg [6:0] init_state_r; reg [6:0] init_state_r1; wire [15:0] load_mr0; wire [15:0] load_mr1; wire [15:0] load_mr2; wire [15:0] load_mr3; reg mem_init_done_r; reg [1:0] mr2_r [0:3]; reg [2:0] mr1_r [0:3]; reg new_burst_r; reg [15:0] wrcal_start_dly_r; wire wrcal_start_pre; reg wrcal_resume_r; // Only one ODT signal per rank in PHY Control Block reg [nCK_PER_CLK-1:0] phy_tmp_odt_r; reg [nCK_PER_CLK-1:0] phy_tmp_odt_r1; reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r; reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_int_cs_n; wire prech_done_pre; reg [15:0] prech_done_dly_r; reg prech_pending_r; reg prech_req_posedge_r; reg prech_req_r; reg pwron_ce_r; reg first_rdlvl_pat_r; reg first_wrcal_pat_r; reg phy_wrdata_en; reg phy_wrdata_en_r1; reg [1:0] wrdata_pat_cnt; reg [1:0] wrcal_pat_cnt; reg [ROW_WIDTH-1:0] address_w; reg [BANK_WIDTH-1:0] bank_w; reg rdlvl_stg1_done_r1; reg rdlvl_stg1_start_int; reg [15:0] rdlvl_start_dly0_r; reg rdlvl_start_pre; reg rdlvl_last_byte_done_r; wire rdlvl_rd; wire rdlvl_wr; reg rdlvl_wr_r; wire rdlvl_wr_rd; reg [3:0] reg_ctrl_cnt_r; reg [1:0] tmp_mr2_r [0:3]; reg [2:0] tmp_mr1_r [0:3]; reg wrlvl_done_r; reg wrlvl_done_r1; reg wrlvl_rank_done_r1; reg wrlvl_rank_done_r2; reg wrlvl_rank_done_r3; reg wrlvl_rank_done_r4; reg wrlvl_rank_done_r5; reg wrlvl_rank_done_r6; reg wrlvl_rank_done_r7; reg [2:0] wrlvl_rank_cntr; reg wrlvl_odt_ctl; reg wrlvl_odt; reg wrlvl_active; reg wrlvl_active_r1; reg [2:0] num_reads; reg temp_wrcal_done_r; reg temp_lmr_done; reg extend_cal_pat; reg [13:0] tg_timer; reg tg_timer_go; reg cnt_wrcal_rd; reg [3:0] cnt_wait; reg [7:0] wrcal_reads; reg [8:0] stg1_wr_rd_cnt; reg phy_data_full_r; reg wr_level_dqs_asrt; reg wr_level_dqs_asrt_r1; reg [1:0] dqs_asrt_cnt; reg [3:0] num_refresh; wire oclkdelay_calib_start_pre; reg [15:0] oclkdelay_start_dly_r; reg [3:0] oclk_wr_cnt; reg [3:0] wrcal_wr_cnt; reg wrlvl_final_r; reg prbs_rdlvl_done_r1; reg prbs_rdlvl_done_r2; reg prbs_rdlvl_done_r3; reg prbs_last_byte_done_r; reg phy_if_empty_r; reg prbs_pat_resume_int; reg complex_row0_wr_done; reg complex_row1_wr_done; reg complex_row0_rd_done; reg complex_row1_rd_done; reg complex_row0_rd_done_r1; reg [3:0] complex_wait_cnt; reg [3:0] complex_num_reads; reg [3:0] complex_num_reads_dec; reg [ROW_WIDTH-1:0] complex_address; reg wr_victim_inc; reg [2:0] wr_victim_sel; reg [DQS_CNT_WIDTH:0] wr_byte_cnt; reg [7:0] complex_row_cnt; reg complex_sample_cnt_inc_r1; reg complex_sample_cnt_inc_r2; reg complex_odt_ext; reg complex_ocal_odt_ext; reg wrcal_final_chk; wire prech_req; reg read_pause_r1; reg read_pause_r2; wire read_pause_ext; reg reset_rd_addr_r1; reg complex_rdlvl_int_ref_req; reg ext_int_ref_req; //complex OCLK delay calibration reg [7:0] complex_row_cnt_ocal; reg [4:0] complex_num_writes; reg [4:0] complex_num_writes_dec; reg complex_oclkdelay_calib_start_int; reg complex_oclkdelay_calib_start_r1; reg complex_oclkdelay_calib_start_r2; reg complex_oclkdelay_calib_done_r1; // reg [DQS_CNT_WIDTH:0] wr_byte_cnt_ocal; reg [2:0] wr_victim_sel_ocal; reg complex_row1_rd_done_r1; //time for switch to write reg [2:0] complex_row1_rd_cnt; //row1 read number for the byte (8 (16 rows) row1) reg complex_byte_rd_done; //read for the byte is done reg complex_byte_rd_done_r1; // reg complex_row_change; //every 16 rows of read, it is set to "0" for write reg ocal_num_samples_inc; //1 read/write is done reg complex_ocal_wr_start; //indicate complex ocal write is started. used for prbs rd addr gen reg prbs_rdlvl_done_pulse; //rising edge for prbs_rdlvl_done. used for pipelining reg prech_done_r1, prech_done_r2, prech_done_r3; reg mask_lim_done; reg complex_mask_lim_done; reg oclkdelay_calib_start_int; reg [REFRESH_TIMER_WIDTH-1:0] oclkdelay_ref_cnt; reg oclkdelay_int_ref_req; reg [3:0] ocal_act_wait_cnt; reg oclk_calib_resume_level; reg ocal_last_byte_done; wire mmcm_wr; //MMCM centering write. no CS will be set wire exit_ocal_complex_resume_wait = init_state_r == INIT_OCAL_COMPLEX_RESUME_WAIT && complex_oclk_calib_resume; //*************************************************************************** // Debug //*************************************************************************** //synthesis translate_off always @(posedge mem_init_done_r) begin if (!rst) $display ("PHY_INIT: Memory Initialization completed at %t", $time); end always @(posedge wrlvl_done) begin if (!rst && (WRLVL == "ON")) $display ("PHY_INIT: Write Leveling completed at %t", $time); end always @(posedge rdlvl_stg1_done) begin if (!rst) $display ("PHY_INIT: Read Leveling Stage 1 completed at %t", $time); end always @(posedge mpr_rdlvl_done) begin if (!rst) $display ("PHY_INIT: MPR Read Leveling completed at %t", $time); end always @(posedge oclkdelay_calib_done) begin if (!rst) $display ("PHY_INIT: OCLKDELAY calibration completed at %t", $time); end always @(posedge pi_calib_done_r1) begin if (!rst) $display ("PHY_INIT: Phaser_In Phase Locked at %t", $time); end always @(posedge pi_dqs_found_done) begin if (!rst) $display ("PHY_INIT: Phaser_In DQSFOUND completed at %t", $time); end always @(posedge wrcal_done) begin if (!rst && (WRLVL == "ON")) $display ("PHY_INIT: Write Calibration completed at %t", $time); end always@(posedge prbs_rdlvl_done)begin if(!rst) $display("PHY_INIT : PRBS/PER_BIT calibration completed at %t",$time); end always@(posedge complex_oclkdelay_calib_done)begin if(!rst) $display("PHY_INIT : COMPLEX OCLKDELAY calibration completed at %t",$time); end always@(posedge oclkdelay_center_calib_done)begin if(!rst) $display("PHY_INIT : OCLKDELAY CENTER CALIB calibration completed at %t",$time); end //synthesis translate_on assign dbg_phy_init[5:0] = init_state_r; assign dbg_phy_init[6+:8] = complex_row_cnt; assign dbg_phy_init[14+:3] = victim_sel; assign dbg_phy_init[17+:4] = victim_byte_cnt; assign dbg_phy_init[21+:9] = stg1_wr_rd_cnt[8:0]; assign dbg_phy_init[30+:15] = complex_address; assign dbg_phy_init[(30+15)+:15] = phy_address[14:0]; assign dbg_phy_init[60] =prbs_rdlvl_prech_req ; assign dbg_phy_init[61] =prech_req_posedge_r ; //*************************************************************************** // DQS count to be sent to hard PHY during Phaser_IN Phase Locking stage //*************************************************************************** // assign pi_phaselock_calib_cnt = dqs_cnt_r; assign pi_calib_done = pi_calib_done_r1; assign read_pause_ext = read_pause | read_pause_r2; //detect rising edge of prbs_rdlvl_done to reset all control sighals always @ (posedge clk) begin prbs_rdlvl_done_pulse <= #TCQ prbs_rdlvl_done & ~prbs_rdlvl_done_r1; end always @ (posedge clk) begin read_pause_r1 <= #TCQ read_pause; read_pause_r2 <= #TCQ read_pause_r1; end always @(posedge clk) begin if (rst) wrcal_final_chk <= #TCQ 1'b0; else if ((init_next_state == INIT_WRCAL_ACT) && wrcal_done && (DRAM_TYPE == "DDR3")) wrcal_final_chk <= #TCQ 1'b1; end always @(posedge clk) begin rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done; prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done; prbs_rdlvl_done_r2 <= #TCQ prbs_rdlvl_done_r1; prbs_rdlvl_done_r3 <= #TCQ prbs_rdlvl_done_r2; wrcal_resume_r <= #TCQ wrcal_resume; wrcal_sanity_chk <= #TCQ wrcal_final_chk; end always @(posedge clk) begin if (rst) mpr_end_if_reset <= #TCQ 1'b0; else if (mpr_last_byte_done && (num_refresh != 'd0)) mpr_end_if_reset <= #TCQ 1'b1; else mpr_end_if_reset <= #TCQ 1'b0; end // Siganl to mask memory model error for Invalid latching edge always @(posedge clk) if (rst) calib_writes <= #TCQ 1'b0; else if ((init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ)) calib_writes <= #TCQ 1'b1; else calib_writes <= #TCQ 1'b0; always @(posedge clk) if (rst) wrcal_rd_wait <= #TCQ 1'b0; else if (init_state_r == INIT_WRCAL_READ_WAIT) wrcal_rd_wait <= #TCQ 1'b1; else wrcal_rd_wait <= #TCQ 1'b0; //*************************************************************************** // Signal PHY completion when calibration is finished // Signal assertion is delayed by four clock cycles to account for the // multi cycle path constraint to (phy_init_data_sel) signal. //*************************************************************************** always @(posedge clk) if (rst) begin init_complete_r <= #TCQ 1'b0; init_complete_r_timing <= #TCQ 1'b0; init_complete_r1 <= #TCQ 1'b0; init_complete_r1_timing <= #TCQ 1'b0; init_complete_r2 <= #TCQ 1'b0; init_calib_complete <= #TCQ 1'b0; end else begin if (init_state_r == INIT_DONE) begin init_complete_r <= #TCQ 1'b1; init_complete_r_timing <= #TCQ 1'b1; end init_complete_r1 <= #TCQ init_complete_r; init_complete_r1_timing <= #TCQ init_complete_r_timing; init_complete_r2 <= #TCQ init_complete_r1; init_calib_complete <= #TCQ init_complete_r2; end always @ (posedge clk) if (rst) complex_oclkdelay_calib_done_r1 <= #TCQ 1'b0; else complex_oclkdelay_calib_done_r1 <= #TCQ complex_oclkdelay_calib_done; //reset read address for starting complex ocaldealy calib always @ (posedge clk) begin complex_ocal_reset_rd_addr <= #TCQ ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd9)) || (prbs_last_byte_done && ~prbs_last_byte_done_r); end //first write for complex oclkdealy calib always @ (posedge clk) begin if (rst) complex_ocal_wr_start <= #TCQ 'b0; else complex_ocal_wr_start <= #TCQ complex_ocal_reset_rd_addr? 1'b1 : complex_ocal_wr_start; end //ocal stg3 centering start // always @ (posedge clk) // if(rst) oclkdelay_center_calib_start <= #TCQ 1'b0; // else // oclkdelay_center_calib_start <= #TCQ ((init_state_r == INIT_OCAL_CENTER_ACT) && lim_done)? 1'b1: oclkdelay_center_calib_start; //*************************************************************************** // Instantiate FF for the phy_init_data_sel signal. A multi cycle path // constraint will be assigned to this signal. This signal will only be // used within the PHY //*************************************************************************** // FDRSE u_ff_phy_init_data_sel // ( // .Q (phy_init_data_sel), // .C (clk), // .CE (1'b1), // .D (init_complete_r), // .R (1'b0), // .S (1'b0) // ) /* synthesis syn_preserve=1 */ // /* synthesis syn_replicate = 0 */; //*************************************************************************** // Mode register programming //*************************************************************************** //***************************************************************** // DDR3 Load mode reg0 // Mode Register (MR0): // [15:13] - unused - 000 // [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit), // 1 (DLL maintained) // [11:9] - write recovery for Auto Precharge (tWR/tCK = 6) // [8] - DLL reset - 0 or 1 // [7] - Test Mode - 0 (normal) // [6:4],[2] - CAS latency - CAS_LAT // [3] - Burst Type - BURST_TYPE // [1:0] - Burst Length - BURST_LEN // DDR2 Load mode register // Mode Register (MR): // [15:14] - unused - 00 // [13] - reserved - 0 // [12] - Power-down mode - 0 (normal) // [11:9] - write recovery - write recovery for Auto Precharge // (tWR/tCK = 6) // [8] - DLL reset - 0 or 1 // [7] - Test Mode - 0 (normal) // [6:4] - CAS latency - CAS_LAT // [3] - Burst Type - BURST_TYPE // [2:0] - Burst Length - BURST_LEN //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr0_DDR3 assign load_mr0[1:0] = (BURST_MODE == "8") ? 2'b00 : (BURST_MODE == "OTF") ? 2'b01 : (BURST_MODE == "4") ? 2'b10 : 2'b11; assign load_mr0[2] = (nCL >= 12) ? 1'b1 : 1'b0; // LSb of CAS latency assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; assign load_mr0[6:4] = ((nCL == 5) || (nCL == 13)) ? 3'b001 : ((nCL == 6) || (nCL == 14)) ? 3'b010 : (nCL == 7) ? 3'b011 : (nCL == 8) ? 3'b100 : (nCL == 9) ? 3'b101 : (nCL == 10) ? 3'b110 : (nCL == 11) ? 3'b111 : (nCL == 12) ? 3'b000 : 3'b111; assign load_mr0[7] = 1'b0; assign load_mr0[8] = 1'b1; // Reset DLL (init only) assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 : (TWR_CYC == 6) ? 3'b010 : (TWR_CYC == 7) ? 3'b011 : (TWR_CYC == 8) ? 3'b100 : (TWR_CYC == 9) ? 3'b101 : (TWR_CYC == 10) ? 3'b101 : (TWR_CYC == 11) ? 3'b110 : (TWR_CYC == 12) ? 3'b110 : (TWR_CYC == 13) ? 3'b111 : (TWR_CYC == 14) ? 3'b111 : (TWR_CYC == 15) ? 3'b000 : (TWR_CYC == 16) ? 3'b000 : 3'b010; assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit' assign load_mr0[15:13] = 3'b000; end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr0_DDR2 // block: gen assign load_mr0[2:0] = (BURST_MODE == "8") ? 3'b011 : (BURST_MODE == "4") ? 3'b010 : 3'b111; assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; assign load_mr0[6:4] = (nCL == 3) ? 3'b011 : (nCL == 4) ? 3'b100 : (nCL == 5) ? 3'b101 : (nCL == 6) ? 3'b110 : 3'b111; assign load_mr0[7] = 1'b0; assign load_mr0[8] = 1'b1; // Reset DLL (init only) assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 : (TWR_CYC == 3) ? 3'b010 : (TWR_CYC == 4) ? 3'b011 : (TWR_CYC == 5) ? 3'b100 : (TWR_CYC == 6) ? 3'b101 : 3'b010; assign load_mr0[15:12]= 4'b0000; // Reserved end endgenerate //***************************************************************** // DDR3 Load mode reg1 // Mode Register (MR1): // [15:13] - unused - 00 // [12] - output enable - 0 (enabled for DQ, DQS, DQS#) // [11] - TDQS enable - 0 (TDQS disabled and DM enabled) // [10] - reserved - 0 (must be '0') // [9] - RTT[2] - 0 // [8] - reserved - 0 (must be '0') // [7] - write leveling - 0 (disabled), 1 (enabled) // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) // [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7) // [4:3] - Additive CAS - ADDITIVE_CAS // [2] - RTT[0] // [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7) // [0] - DLL enable - 0 (normal) // DDR2 ext mode register // Extended Mode Register (MR): // [15:14] - unused - 00 // [13] - reserved - 0 // [12] - output enable - 0 (enabled) // [11] - RDQS enable - 0 (disabled) // [10] - DQS# enable - 0 (enabled) // [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init) // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) // [5:3] - Additive CAS - ADDITIVE_CAS // [2] - RTT[0] // [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced) // [0] - DLL enable - 0 (normal) //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr1_DDR3 assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b0 : 1'b1; assign load_mr1[2] = ((RTT_NOM_int == "30") || (RTT_NOM_int == "40") || (RTT_NOM_int == "60")) ? 1'b1 : 1'b0; assign load_mr1[4:3] = (AL == "0") ? 2'b00 : (AL == "CL-1") ? 2'b01 : (AL == "CL-2") ? 2'b10 : 2'b11; assign load_mr1[5] = 1'b0; assign load_mr1[6] = ((RTT_NOM_int == "40") || (RTT_NOM_int == "120")) ? 1'b1 : 1'b0; assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence assign load_mr1[8] = 1'b0; assign load_mr1[9] = ((RTT_NOM_int == "20") || (RTT_NOM_int == "30")) ? 1'b1 : 1'b0; assign load_mr1[10] = 1'b0; assign load_mr1[15:11] = 5'b00000; end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr1_DDR2 assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b1 : 1'b0; assign load_mr1[2] = ((RTT_NOM_int == "75") || (RTT_NOM_int == "50")) ? 1'b1 : 1'b0; assign load_mr1[5:3] = (AL == "0") ? 3'b000 : (AL == "1") ? 3'b001 : (AL == "2") ? 3'b010 : (AL == "3") ? 3'b011 : (AL == "4") ? 3'b100 : 3'b111; assign load_mr1[6] = ((RTT_NOM_int == "50") || (RTT_NOM_int == "150")) ? 1'b1 : 1'b0; assign load_mr1[9:7] = 3'b000; assign load_mr1[10] = (DDR2_DQSN_ENABLE == "YES") ? 1'b0 : 1'b1; assign load_mr1[15:11] = 5'b00000; end endgenerate //***************************************************************** // DDR3 Load mode reg2 // Mode Register (MR2): // [15:11] - unused - 00 // [10:9] - RTT_WR - 00 (Dynamic ODT off) // [8] - reserved - 0 (must be '0') // [7] - self-refresh temperature range - // 0 (normal), 1 (extended) // [6] - Auto Self-Refresh - 0 (manual), 1(auto) // [5:3] - CAS Write Latency (CWL) - // 000 (5 for 400 MHz device), // 001 (6 for 400 MHz to 533 MHz devices), // 010 (7 for 533 MHz to 667 MHz devices), // 011 (8 for 667 MHz to 800 MHz) // [2:0] - Partial Array Self-Refresh (Optional) - // 000 (full array) // Not used for DDR2 //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr2_DDR3 assign load_mr2[2:0] = 3'b000; assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 : (nCWL == 6) ? 3'b001 : (nCWL == 7) ? 3'b010 : (nCWL == 8) ? 3'b011 : (nCWL == 9) ? 3'b100 : (nCWL == 10) ? 3'b101 : (nCWL == 11) ? 3'b110 : 3'b111; assign load_mr2[6] = 1'b0; assign load_mr2[7] = 1'b0; assign load_mr2[8] = 1'b0; // Dynamic ODT disabled assign load_mr2[10:9] = 2'b00; assign load_mr2[15:11] = 5'b00000; end else begin: gen_load_mr2_DDR2 assign load_mr2[15:0] = 16'd0; end endgenerate //***************************************************************** // DDR3 Load mode reg3 // Mode Register (MR3): // [15:3] - unused - All zeros // [2] - MPR Operation - 0(normal operation), 1(data flow from MPR) // [1:0] - MPR location - 00 (Predefined pattern) //***************************************************************** assign load_mr3[1:0] = 2'b00; assign load_mr3[2] = 1'b0; assign load_mr3[15:3] = 13'b0000000000000; // For multi-rank systems the rank being accessed during writes in // Read Leveling must be sent to phy_write for the bitslip logic assign calib_rank_cnt = chip_cnt_r; //*************************************************************************** // Logic to begin initial calibration, and to handle precharge requests // during read-leveling (to avoid tRAS violations if individual read // levelling calibration stages take more than max{tRAS) to complete). //*************************************************************************** // Assert when readback for each stage of read-leveling begins. However, // note this indicates only when the read command is issued and when // Phaser_IN has phase aligned FREQ_REF clock to read DQS. It does not // indicate when the read data is present on the bus (when this happens // after the read command is issued depends on CAS LATENCY) - there will // need to be some delay before valid data is present on the bus. // assign rdlvl_start_pre = (init_state_r == INIT_PI_PHASELOCK_READS); // Assert when read back for oclkdelay calibration begins assign oclkdelay_calib_start_pre = (init_state_r == INIT_OCAL_CENTER_ACT); //(init_state_r == INIT_OCLKDELAY_READ); // Assert when read back for write calibration begins assign wrcal_start_pre = (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS); // Common precharge signal done signal - pulses only when there has been // a precharge issued as a result of a PRECH_REQ pulse. Note also a common // PRECH_DONE signal is used for all blocks assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || ((rdlvl_last_byte_done_r || prbs_last_byte_done_r) && (init_state_r == INIT_RDLVL_ACT_WAIT) && cnt_cmd_done_r) || (dqs_found_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || (init_state_r == INIT_MPR_RDEN) || ((init_state_r == INIT_WRCAL_ACT_WAIT) && cnt_cmd_done_r) || (init_state_r == INIT_OCAL_CENTER_ACT) || ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && complex_oclkdelay_calib_start_r1) || ((init_state_r == INIT_OCLKDELAY_ACT_WAIT) && cnt_cmd_done_r) || ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) && prbs_last_byte_done_r) || //prbs_rdlvl_done (wrlvl_final && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r && ~oclkdelay_calib_done)) && prech_pending_r && !prech_req_posedge_r); always @(posedge clk) if (rst) pi_phaselock_start <= #TCQ 1'b0; else if (init_state_r == INIT_PI_PHASELOCK_READS) pi_phaselock_start <= #TCQ 1'b1; // Delay start of each calibration by 16 clock cycles to ensure that when // calibration logic begins, read data is already appearing on the bus. // Each circuit should synthesize using an SRL16. Assume that reset is // long enough to clear contents of SRL16. always @(posedge clk) begin rdlvl_last_byte_done_r <= #TCQ rdlvl_last_byte_done; prbs_last_byte_done_r <= #TCQ prbs_last_byte_done; rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0], rdlvl_start_pre}; wrcal_start_dly_r <= #TCQ {wrcal_start_dly_r[14:0], wrcal_start_pre}; oclkdelay_start_dly_r <= #TCQ {oclkdelay_start_dly_r[14:0], oclkdelay_calib_start_pre}; prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0], prech_done_pre}; end always @(posedge clk) if (rst) oclkdelay_calib_start_int <= #TCQ 1'b0; else if (oclkdelay_start_dly_r[5]) oclkdelay_calib_start_int <= #TCQ 1'b1; always @(posedge clk) begin if (rst) ocal_last_byte_done <= #TCQ 1'b0; else if ((complex_oclkdelay_calib_cnt == DQS_WIDTH-1) && oclkdelay_center_calib_done) ocal_last_byte_done <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || (init_state_r == INIT_REFRESH) || prbs_rdlvl_done || ocal_last_byte_done || oclkdelay_center_calib_done) oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; else if (oclkdelay_calib_start_int) begin if (oclkdelay_ref_cnt > 'd0) oclkdelay_ref_cnt <= #TCQ oclkdelay_ref_cnt - 1; else oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; end end always @(posedge clk) begin if (rst || (init_state_r == INIT_OCAL_CENTER_ACT) || oclkdelay_calib_done || ocal_last_byte_done || oclkdelay_center_calib_done) oclkdelay_int_ref_req <= #TCQ 1'b0; else if (oclkdelay_ref_cnt == 'd1) oclkdelay_int_ref_req <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) ocal_act_wait_cnt <= #TCQ 'd0; else if ((init_state_r == INIT_OCAL_CENTER_ACT_WAIT) && ocal_act_wait_cnt < 'd15) ocal_act_wait_cnt <= #TCQ ocal_act_wait_cnt + 1; else ocal_act_wait_cnt <= #TCQ 'd0; end always @(posedge clk) begin if (rst || (init_state_r == INIT_OCLKDELAY_READ)) oclk_calib_resume_level <= #TCQ 1'b0; else if (oclk_calib_resume) oclk_calib_resume_level <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_ACT_WAIT) || prbs_rdlvl_done) complex_rdlvl_int_ref_req <= #TCQ 1'b0; else if (oclkdelay_ref_cnt == 'd1) // complex_rdlvl_int_ref_req <= #TCQ 1'b1; complex_rdlvl_int_ref_req <= #TCQ 1'b0; //temporary fix for read issue end always @(posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_COMPLEX_READ)) ext_int_ref_req <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_ACT_WAIT) && complex_rdlvl_int_ref_req) ext_int_ref_req <= #TCQ 1'b1; end always @(posedge clk) begin prech_done <= #TCQ prech_done_dly_r[15]; prech_done_r1 <= #TCQ prech_done_dly_r[15]; prech_done_r2 <= #TCQ prech_done_r1; prech_done_r3 <= #TCQ prech_done_r2; end always @(posedge clk) if (rst) mpr_rdlvl_start <= #TCQ 1'b0; else if (pi_dqs_found_done && (init_state_r == INIT_MPR_READ)) mpr_rdlvl_start <= #TCQ 1'b1; always @(posedge clk) phy_if_empty_r <= #TCQ phy_if_empty; always @(posedge clk) if (rst || ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || prbs_rdlvl_done) prbs_gen_clk_en <= #TCQ 1'b0; else if ((~phy_if_empty_r && rdlvl_stg1_done_r1 && ~prbs_rdlvl_done) || ((init_state_r == INIT_RDLVL_ACT_WAIT) && rdlvl_stg1_done_r1 && (cnt_cmd_r == 'd127)) || ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && rdlvl_stg1_done_r1 && (complex_wait_cnt == 'd14)) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || ((init_state_r == INIT_PRECHARGE_PREWAIT) && prbs_rdlvl_start)) prbs_gen_clk_en <= #TCQ 1'b1; //Enable for complex oclkdelay - used in prbs gen always @(posedge clk) if (rst || ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || complex_oclkdelay_calib_done || (complex_wait_cnt == 'd15 && complex_num_writes == 1 && complex_ocal_wr_start) || ( init_state_r == INIT_RDLVL_STG1_WRITE && complex_num_writes_dec == 'd2) || ~complex_ocal_wr_start || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT ) || (init_state_r != INIT_OCAL_COMPLEX_RESUME_WAIT && init_state_r1 == INIT_OCAL_COMPLEX_RESUME_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_ACT)) prbs_gen_oclk_clk_en <= #TCQ 1'b0; else if ((~phy_if_empty_r && ~complex_oclkdelay_calib_done && prbs_rdlvl_done_r1) || // changed for new algo 3/26 ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd14)) || ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14)) || exit_ocal_complex_resume_wait || ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && ~stg1_wr_done && ~complex_row1_wr_done && ~complex_ocal_num_samples_done_r && (complex_wait_cnt == 'd14)) || (init_state_r == INIT_RDLVL_COMPLEX_READ) ) prbs_gen_oclk_clk_en <= #TCQ 1'b1; generate if (RANKS < 2) begin always @(posedge clk) if (rst) begin rdlvl_stg1_start <= #TCQ 1'b0; rdlvl_stg1_start_int <= #TCQ 1'b0; rdlvl_start_pre <= #TCQ 1'b0; prbs_rdlvl_start <= #TCQ 1'b0; end else begin if (pi_dqs_found_done && cnt_cmd_done_r && (init_state_r == INIT_RDLVL_ACT_WAIT)) rdlvl_stg1_start_int <= #TCQ 1'b1; if (pi_dqs_found_done && (init_state_r == INIT_RDLVL_STG1_READ))begin rdlvl_start_pre <= #TCQ 1'b1; rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; end if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_READ) && (WRLVL == "ON")) begin prbs_rdlvl_start <= #TCQ 1'b1; end end end else begin always @(posedge clk) if (rst || rdlvl_stg1_rank_done) begin rdlvl_stg1_start <= #TCQ 1'b0; rdlvl_stg1_start_int <= #TCQ 1'b0; rdlvl_start_pre <= #TCQ 1'b0; prbs_rdlvl_start <= #TCQ 1'b0; end else begin if (pi_dqs_found_done && cnt_cmd_done_r && (init_state_r == INIT_RDLVL_ACT_WAIT)) rdlvl_stg1_start_int <= #TCQ 1'b1; if (pi_dqs_found_done && (init_state_r == INIT_RDLVL_STG1_READ))begin rdlvl_start_pre <= #TCQ 1'b1; rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; end if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_READ) && (WRLVL == "ON")) begin prbs_rdlvl_start <= #TCQ 1'b1; end end end endgenerate always @(posedge clk) begin if (rst || dqsfound_retry || wrlvl_byte_redo) begin pi_dqs_found_start <= #TCQ 1'b0; wrcal_start <= #TCQ 1'b0; end else begin if (!pi_dqs_found_done && init_state_r == INIT_RDLVL_STG2_READ) pi_dqs_found_start <= #TCQ 1'b1; if (wrcal_start_dly_r[5]) wrcal_start <= #TCQ 1'b1; end end // else: !if(rst) always @(posedge clk) if (rst) oclkdelay_calib_start <= #TCQ 1'b0; else if (oclkdelay_start_dly_r[5]) oclkdelay_calib_start <= #TCQ 1'b1; always @(posedge clk) if (rst) pi_dqs_found_done_r1 <= #TCQ 1'b0; else pi_dqs_found_done_r1 <= #TCQ pi_dqs_found_done; always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final; // Reset IN_FIFO after final write leveling to make sure the FIFO // pointers are initialized always @(posedge clk) if (rst || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_REFRESH)) wrlvl_final_if_rst <= #TCQ 1'b0; else if (wrlvl_done_r && //(wrlvl_final_r && wrlvl_done_r && (init_state_r == INIT_WRLVL_LOAD_MR2)) wrlvl_final_if_rst <= #TCQ 1'b1; // Constantly enable DQS while write leveling is enabled in the memory // This is more to get rid of warnings in simulation, can later change // this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted always @(posedge clk) if (rst || ((init_state_r1 != INIT_WRLVL_START) && (init_state_r == INIT_WRLVL_START))) wrlvl_odt_ctl <= #TCQ 1'b0; else if (wrlvl_rank_done && ~wrlvl_rank_done_r1) wrlvl_odt_ctl <= #TCQ 1'b1; generate if (nCK_PER_CLK == 4) begin: en_cnt_div4 always @ (posedge clk) if (rst) enable_wrlvl_cnt <= #TCQ 5'd0; else if ((init_state_r == INIT_WRLVL_START) || (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) enable_wrlvl_cnt <= #TCQ 5'd12; else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; // ODT stays asserted as long as write_calib // signal is asserted always @(posedge clk) if (rst || wrlvl_odt_ctl) wrlvl_odt <= #TCQ 1'b0; else if (enable_wrlvl_cnt == 5'd1) wrlvl_odt <= #TCQ 1'b1; end else begin: en_cnt_div2 always @ (posedge clk) if (rst) enable_wrlvl_cnt <= #TCQ 5'd0; else if ((init_state_r == INIT_WRLVL_START) || (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) enable_wrlvl_cnt <= #TCQ 5'd21; else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; // ODT stays asserted as long as write_calib // signal is asserted always @(posedge clk) if (rst || wrlvl_odt_ctl) wrlvl_odt <= #TCQ 1'b0; else if (enable_wrlvl_cnt == 5'd1) wrlvl_odt <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst || wrlvl_rank_done || done_dqs_tap_inc) wrlvl_active <= #TCQ 1'b0; else if ((enable_wrlvl_cnt == 5'd1) && wrlvl_odt && !wrlvl_active) wrlvl_active <= #TCQ 1'b1; // signal used to assert DQS for write leveling. // the DQS will be asserted once every 16 clock cycles. always @(posedge clk)begin if(rst || (enable_wrlvl_cnt != 5'd1)) begin wr_level_dqs_asrt <= #TCQ 1'd0; end else if ((enable_wrlvl_cnt == 5'd1) && (wrlvl_active_r1)) begin wr_level_dqs_asrt <= #TCQ 1'd1; end end always @ (posedge clk) begin if (rst || (wrlvl_done_r && ~wrlvl_done_r1)) dqs_asrt_cnt <= #TCQ 2'd0; else if (wr_level_dqs_asrt && dqs_asrt_cnt != 2'd3) dqs_asrt_cnt <= #TCQ (dqs_asrt_cnt + 1); end always @ (posedge clk) begin if (rst || ~wrlvl_active) wr_lvl_start <= #TCQ 1'd0; else if (dqs_asrt_cnt == 2'd3) wr_lvl_start <= #TCQ 1'd1; end always @(posedge clk) begin if (rst) wl_sm_start <= #TCQ 1'b0; else wl_sm_start <= #TCQ wr_level_dqs_asrt_r1; end always @(posedge clk) begin wrlvl_active_r1 <= #TCQ wrlvl_active; wr_level_dqs_asrt_r1 <= #TCQ wr_level_dqs_asrt; wrlvl_done_r <= #TCQ wrlvl_done; wrlvl_done_r1 <= #TCQ wrlvl_done_r; wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done; wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1; wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2; wrlvl_rank_done_r4 <= #TCQ wrlvl_rank_done_r3; wrlvl_rank_done_r5 <= #TCQ wrlvl_rank_done_r4; wrlvl_rank_done_r6 <= #TCQ wrlvl_rank_done_r5; wrlvl_rank_done_r7 <= #TCQ wrlvl_rank_done_r6; end always @ (posedge clk) begin //if (rst) wrlvl_rank_cntr <= #TCQ 3'd0; //else if (wrlvl_rank_done) // wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1; end //***************************************************************** // Precharge request logic - those calibration logic blocks // that require greater than tRAS(max) to finish must break up // their calibration into smaller units of time, with precharges // issued in between. This is done using the XXX_PRECH_REQ and // PRECH_DONE handshaking between PHY_INIT and those blocks //***************************************************************** // Shared request from multiple sources assign prech_req = oclk_prech_req | rdlvl_prech_req | wrcal_prech_req | prbs_rdlvl_prech_req | (dqs_found_prech_req & (init_state_r == INIT_RDLVL_STG2_READ_WAIT)); // Handshaking logic to force precharge during read leveling, and to // notify read leveling logic when precharge has been initiated and // it's okay to proceed with leveling again always @(posedge clk) if (rst) begin prech_req_r <= #TCQ 1'b0; prech_req_posedge_r <= #TCQ 1'b0; prech_pending_r <= #TCQ 1'b0; end else begin prech_req_r <= #TCQ prech_req; prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r; if (prech_req_posedge_r) prech_pending_r <= #TCQ 1'b1; // Clear after we've finished with the precharge and have // returned to issuing read leveling calibration reads else if (prech_done_pre) prech_pending_r <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || prech_done_r3) mask_lim_done <= #TCQ 1'b0; else if (prech_pending_r) mask_lim_done <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || prbs_rdlvl_done_r3) complex_mask_lim_done <= #TCQ 1'b0; else if (~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) complex_mask_lim_done <= #TCQ 1'b1; end //Complex oclkdelay calibrration //*************************************************************************** // Various timing counters //*************************************************************************** //***************************************************************** // Generic delay for various states that require it (e.g. for turnaround // between read and write). Make this a sufficiently large number of clock // cycles to cover all possible frequencies and memory components) // Requirements for this counter: // 1. Greater than tMRD // 2. tRFC (refresh-active) for DDR2 // 3. (list the other requirements, slacker...) //***************************************************************** always @(posedge clk) begin case (init_state_r) INIT_LOAD_MR_WAIT, INIT_WRLVL_LOAD_MR_WAIT, INIT_WRLVL_LOAD_MR2_WAIT, INIT_MPR_WAIT, INIT_MPR_DISABLE_PREWAIT, INIT_MPR_DISABLE_WAIT, INIT_OCLKDELAY_ACT_WAIT, INIT_OCLKDELAY_WRITE_WAIT, INIT_RDLVL_ACT_WAIT, INIT_RDLVL_STG1_WRITE_READ, INIT_RDLVL_STG2_READ_WAIT, INIT_WRCAL_ACT_WAIT, INIT_WRCAL_WRITE_READ, INIT_WRCAL_READ_WAIT, INIT_PRECHARGE_PREWAIT, INIT_PRECHARGE_WAIT, INIT_DDR2_PRECHARGE_WAIT, INIT_REG_WRITE_WAIT, INIT_REFRESH_WAIT, INIT_REFRESH_RNK2_WAIT: begin if (phy_ctl_full || phy_cmd_full) cnt_cmd_r <= #TCQ cnt_cmd_r; else cnt_cmd_r <= #TCQ cnt_cmd_r + 1; end INIT_WRLVL_WAIT: cnt_cmd_r <= #TCQ 'b0; default: cnt_cmd_r <= #TCQ 'b0; endcase end // pulse when count reaches terminal count always @(posedge clk) cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD); // For ODT deassertion - hold throughout post read/write wait stage, but // deassert before next command. The post read/write stage is very long, so // we simply address the longest case here plus some margin. always @(posedge clk) cnt_cmd_done_m7_r <= #TCQ (cnt_cmd_r == (CNTNEXT_CMD - 7)); //************************************************************************ // Added to support PO fine delay inc when TG errors always @(posedge clk) begin case (init_state_r) INIT_WRCAL_READ_WAIT: begin if (phy_ctl_full || phy_cmd_full) cnt_wait <= #TCQ cnt_wait; else cnt_wait <= #TCQ cnt_wait + 1; end default: cnt_wait <= #TCQ 'b0; endcase end always @(posedge clk) cnt_wrcal_rd <= #TCQ (cnt_wait == 'd4); always @(posedge clk) begin if (rst || ~temp_wrcal_done) temp_lmr_done <= #TCQ 1'b0; else if (temp_wrcal_done && (init_state_r == INIT_LOAD_MR)) temp_lmr_done <= #TCQ 1'b1; end always @(posedge clk) temp_wrcal_done_r <= #TCQ temp_wrcal_done; always @(posedge clk) if (rst) begin tg_timer_go <= #TCQ 1'b0; end else if ((PRE_REV3ES == "ON") && temp_wrcal_done && temp_lmr_done && (init_state_r == INIT_WRCAL_READ_WAIT)) begin tg_timer_go <= #TCQ 1'b1; end else begin tg_timer_go <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || (temp_wrcal_done && ~temp_wrcal_done_r) || (init_state_r == INIT_PRECHARGE_PREWAIT)) tg_timer <= #TCQ 'd0; else if ((pi_phaselock_timer == PHASELOCKED_TIMEOUT) && tg_timer_go && (tg_timer != TG_TIMER_TIMEOUT)) tg_timer <= #TCQ tg_timer + 1; end always @(posedge clk) begin if (rst) tg_timer_done <= #TCQ 1'b0; else if (tg_timer == TG_TIMER_TIMEOUT) tg_timer_done <= #TCQ 1'b1; else tg_timer_done <= #TCQ 1'b0; end always @(posedge clk) begin if (rst) no_rst_tg_mc <= #TCQ 1'b0; else if ((init_state_r == INIT_WRCAL_ACT) && wrcal_read_req) no_rst_tg_mc <= #TCQ 1'b1; else no_rst_tg_mc <= #TCQ 1'b0; end //************************************************************************ always @(posedge clk) begin if (rst) detect_pi_found_dqs <= #TCQ 1'b0; else if ((cnt_cmd_r == 7'b0111111) && (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) detect_pi_found_dqs <= #TCQ 1'b1; else detect_pi_found_dqs <= #TCQ 1'b0; end //***************************************************************** // Initial delay after power-on for RESET, CKE // NOTE: Could reduce power consumption by turning off these counters // after initial power-up (at expense of more logic) // NOTE: Likely can combine multiple counters into single counter //***************************************************************** // Create divided by 1024 version of clock always @(posedge clk) if (rst) begin cnt_pwron_ce_r <= #TCQ 10'h000; pwron_ce_r <= #TCQ 1'b0; end else begin cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1; pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF); end // "Main" power-on counter - ticks every CLKDIV/1024 cycles always @(posedge clk) if (rst) cnt_pwron_r <= #TCQ 'b0; else if (pwron_ce_r) cnt_pwron_r <= #TCQ cnt_pwron_r + 1; always @(posedge clk) if (rst || ~phy_ctl_ready) begin cnt_pwron_reset_done_r <= #TCQ 1'b0; cnt_pwron_cke_done_r <= #TCQ 1'b0; end else begin // skip power-up count for simulation purposes only if ((SIM_INIT_OPTION == "SKIP_PU_DLY") || (SIM_INIT_OPTION == "SKIP_INIT")) begin cnt_pwron_reset_done_r <= #TCQ 1'b1; cnt_pwron_cke_done_r <= #TCQ 1'b1; end else begin // otherwise, create latched version of done signal for RESET, CKE if (DRAM_TYPE == "DDR3") begin if (!cnt_pwron_reset_done_r) cnt_pwron_reset_done_r <= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT); if (!cnt_pwron_cke_done_r) cnt_pwron_cke_done_r <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); end else begin // DDR2 cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed if (!cnt_pwron_cke_done_r) cnt_pwron_cke_done_r <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); end end end // else: !if(rst || ~phy_ctl_ready) always @(posedge clk) cnt_pwron_cke_done_r1 <= #TCQ cnt_pwron_cke_done_r; // Keep RESET asserted and CKE deasserted until after power-on delay always @(posedge clk or posedge rst) begin if (rst) phy_reset_n <= #TCQ 1'b0; else phy_reset_n <= #TCQ cnt_pwron_reset_done_r; // phy_cke <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}}; end //***************************************************************** // Counter for tXPR (pronouned "Tax-Payer") - wait time after // CKE deassertion before first MRS command can be asserted //***************************************************************** always @(posedge clk) if (!cnt_pwron_cke_done_r) begin cnt_txpr_r <= #TCQ 'b0; cnt_txpr_done_r <= #TCQ 1'b0; end else begin cnt_txpr_r <= #TCQ cnt_txpr_r + 1; if (!cnt_txpr_done_r) cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT); end //***************************************************************** // Counter for the initial 400ns wait for issuing precharge all // command after CKE assertion. Only for DDR2. //***************************************************************** always @(posedge clk) if (!cnt_pwron_cke_done_r) begin cnt_init_pre_wait_r <= #TCQ 'b0; cnt_init_pre_wait_done_r <= #TCQ 1'b0; end else begin cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1; if (!cnt_init_pre_wait_done_r) cnt_init_pre_wait_done_r <= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT); end //***************************************************************** // Wait for both DLL to lock (tDLLK) and ZQ calibration to finish // (tZQINIT). Both take the same amount of time (512*tCK) //***************************************************************** always @(posedge clk) if (init_state_r == INIT_ZQCL) begin cnt_dllk_zqinit_r <= #TCQ 'b0; cnt_dllk_zqinit_done_r <= #TCQ 1'b0; end else if (~(phy_ctl_full || phy_cmd_full)) begin cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1; if (!cnt_dllk_zqinit_done_r) cnt_dllk_zqinit_done_r <= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT); end //***************************************************************** // Keep track of which MRS counter needs to be programmed during // memory initialization // The counter and the done signal are reset an additional time // for DDR2. The same signals are used for the additional DDR2 // initialization sequence. //***************************************************************** always @(posedge clk) if ((init_state_r == INIT_IDLE)|| ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))) begin cnt_init_mr_r <= #TCQ 'b0; cnt_init_mr_done_r <= #TCQ 1'b0; end else if (init_state_r == INIT_LOAD_MR) begin cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1; cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE); end //***************************************************************** // Flag to tell if the first precharge for DDR2 init sequence is // done //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) ddr2_pre_flag_r<= #TCQ 'b0; else if (init_state_r == INIT_LOAD_MR) ddr2_pre_flag_r<= #TCQ 1'b1; // reset the flag for multi rank case else if ((ddr2_refresh_flag_r) && (init_state_r == INIT_LOAD_MR_WAIT)&& (cnt_cmd_done_r) && (cnt_init_mr_done_r)) ddr2_pre_flag_r <= #TCQ 'b0; //***************************************************************** // Flag to tell if the refresh stat for DDR2 init sequence is // reached //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) ddr2_refresh_flag_r<= #TCQ 'b0; else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r)) // reset the flag for multi rank case ddr2_refresh_flag_r<= #TCQ 1'b1; else if ((ddr2_refresh_flag_r) && (init_state_r == INIT_LOAD_MR_WAIT)&& (cnt_cmd_done_r) && (cnt_init_mr_done_r)) ddr2_refresh_flag_r <= #TCQ 'b0; //***************************************************************** // Keep track of the number of auto refreshes for DDR2 // initialization. The spec asks for a minimum of two refreshes. // Four refreshes are performed here. The two extra refreshes is to // account for the 200 clock cycle wait between step h and l. // Without the two extra refreshes we would have to have a // wait state. //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) begin cnt_init_af_r <= #TCQ 'b0; cnt_init_af_done_r <= #TCQ 1'b0; end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))begin cnt_init_af_r <= #TCQ cnt_init_af_r + 1; cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11); end //***************************************************************** // Keep track of the register control word programming for // DDR3 RDIMM //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) reg_ctrl_cnt_r <= #TCQ 'b0; else if (init_state_r == INIT_REG_WRITE) reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1; generate if (RANKS < 2) begin: one_rank always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || (complex_byte_rd_done) || prbs_rdlvl_done_pulse ) stg1_wr_done <= #TCQ 1'b0; else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) stg1_wr_done <= #TCQ 1'b1; end else begin: two_ranks always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || (complex_byte_rd_done) || prbs_rdlvl_done_pulse || (rdlvl_stg1_rank_done )) stg1_wr_done <= #TCQ 1'b0; else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) stg1_wr_done <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst) rnk_ref_cnt <= #TCQ 1'b0; else if (stg1_wr_done && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r) rnk_ref_cnt <= #TCQ ~rnk_ref_cnt; always @(posedge clk) if (rst || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r ==INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT)) num_refresh <= #TCQ 'd0; else if ((init_state_r == INIT_REFRESH) && (~pi_dqs_found_done || ((DRAM_TYPE == "DDR3") && ~oclkdelay_calib_done) || (rdlvl_stg1_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done))) num_refresh <= #TCQ num_refresh + 1; //*************************************************************************** // Initialization state machine //*************************************************************************** //***************************************************************** // Next-state logic //***************************************************************** always @(posedge clk) if (rst)begin init_state_r <= #TCQ INIT_IDLE; init_state_r1 <= #TCQ INIT_IDLE; end else begin init_state_r <= #TCQ init_next_state; init_state_r1 <= #TCQ init_state_r; end always @(*) begin init_next_state = init_state_r; (* full_case, parallel_case *) case (init_state_r) //******************************************************* // DRAM initialization //******************************************************* // Initial state - wait for: // 1. Power-on delays to pass // 2. PHY Control Block to assert phy_ctl_ready // 3. PHY Control FIFO must not be FULL // 4. Read path initialization to finish INIT_IDLE: if (cnt_pwron_cke_done_r && phy_ctl_ready && ck_addr_cmd_delay_done && delay_incdec_done && ~(phy_ctl_full || phy_cmd_full) ) begin // If skipping memory initialization (simulation only) if (SIM_INIT_OPTION == "SKIP_INIT") //if (WRLVL == "ON") // Proceed to write leveling // init_next_state = INIT_WRLVL_START; //else //if (SIM_CAL_OPTION != "SKIP_CAL") // Proceed to Phaser_In phase lock init_next_state = INIT_RDLVL_ACT; // else // Skip read leveling //init_next_state = INIT_DONE; else init_next_state = INIT_WAIT_CKE_EXIT; end // Wait minimum of Reset CKE exit time (tXPR = max(tXS, INIT_WAIT_CKE_EXIT: if ((cnt_txpr_done_r) && (DRAM_TYPE == "DDR3") && ~(phy_ctl_full || phy_cmd_full)) begin if((REG_CTRL == "ON") && ((nCS_PER_RANK > 1) || (RANKS > 1))) //register write for reg dimm. Some register chips // have the register chip in a pre-programmed state // in that case the nCS_PER_RANK == 1 && RANKS == 1 init_next_state = INIT_REG_WRITE; else // Load mode register - this state is repeated multiple times init_next_state = INIT_LOAD_MR; end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == "DDR2") && ~(phy_ctl_full || phy_cmd_full)) // DDR2 start with a precharge all command init_next_state = INIT_DDR2_PRECHARGE; INIT_REG_WRITE: init_next_state = INIT_REG_WRITE_WAIT; INIT_REG_WRITE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if(reg_ctrl_cnt_r == 4'd8) init_next_state = INIT_LOAD_MR; else init_next_state = INIT_REG_WRITE; end INIT_LOAD_MR: init_next_state = INIT_LOAD_MR_WAIT; // After loading MR, wait at least tMRD INIT_LOAD_MR_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin // If finished loading all mode registers, proceed to next step if (prbs_rdlvl_done && pi_dqs_found_done && rdlvl_stg1_done) // for ddr3 when the correct burst length is writtern at end init_next_state = INIT_PRECHARGE; else if (~wrcal_done && temp_lmr_done) init_next_state = INIT_PRECHARGE_PREWAIT; else if (cnt_init_mr_done_r)begin if(DRAM_TYPE == "DDR3") init_next_state = INIT_ZQCL; else begin //DDR2 if(ddr2_refresh_flag_r)begin // memory initialization per rank for multi-rank case if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) init_next_state = INIT_DDR2_MULTI_RANK; else init_next_state = INIT_RDLVL_ACT; // ddr2 initialization done.load mode state after refresh end else init_next_state = INIT_DDR2_PRECHARGE; end end else init_next_state = INIT_LOAD_MR; end // DDR2 multi rank transition state INIT_DDR2_MULTI_RANK: init_next_state = INIT_DDR2_MULTI_RANK_WAIT; INIT_DDR2_MULTI_RANK_WAIT: init_next_state = INIT_DDR2_PRECHARGE; // Initial ZQ calibration INIT_ZQCL: init_next_state = INIT_WAIT_DLLK_ZQINIT; // Wait until both DLL have locked, and ZQ calibration done INIT_WAIT_DLLK_ZQINIT: if (cnt_dllk_zqinit_done_r && ~(phy_ctl_full || phy_cmd_full)) // memory initialization per rank for multi-rank case if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) init_next_state = INIT_LOAD_MR; //else if (WRLVL == "ON") // init_next_state = INIT_WRLVL_START; else // skip write-leveling (e.g. for DDR2 interface) init_next_state = INIT_RDLVL_ACT; // Initial precharge for DDR2 INIT_DDR2_PRECHARGE: init_next_state = INIT_DDR2_PRECHARGE_WAIT; INIT_DDR2_PRECHARGE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if (ddr2_pre_flag_r) init_next_state = INIT_REFRESH; else // from precharge state initially go to load mode init_next_state = INIT_LOAD_MR; end INIT_REFRESH: if ((RANKS == 2) && (chip_cnt_r == RANKS - 1)) init_next_state = INIT_REFRESH_RNK2_WAIT; else init_next_state = INIT_REFRESH_WAIT; INIT_REFRESH_RNK2_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_PRECHARGE; INIT_REFRESH_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin if(cnt_init_af_done_r && (~mem_init_done_r)) // go to lm state as part of DDR2 init sequence init_next_state = INIT_LOAD_MR; // Go to state to issue back-to-back writes during limit check and centering else if (~oclkdelay_calib_done && (mpr_last_byte_done || mpr_rdlvl_done) && (DRAM_TYPE == "DDR3")) begin if (num_refresh == 'd8) init_next_state = INIT_OCAL_CENTER_ACT; else init_next_state = INIT_REFRESH; end else if(rdlvl_stg1_done && oclkdelay_center_calib_done && complex_oclkdelay_calib_done && ~wrlvl_done_r1 && (WRLVL == "ON")) init_next_state = INIT_WRLVL_START; else if (pi_dqs_found_done && ~wrlvl_done_r1 && ~wrlvl_final && ~wrlvl_byte_redo && (WRLVL == "ON")) init_next_state = INIT_WRLVL_START; else if ((((prbs_last_byte_done_r || prbs_rdlvl_done) && ~complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON")) //&& rdlvl_stg1_done // changed for new algo 3/26 && mem_init_done_r) begin if (num_refresh == 'd8) begin if (BYPASS_COMPLEX_OCAL == "FALSE") init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else init_next_state = INIT_WRCAL_ACT; end else init_next_state = INIT_REFRESH; end else if (~pi_dqs_found_done || (rdlvl_stg1_done && ~prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)) begin if (num_refresh == 'd8) init_next_state = INIT_RDLVL_ACT; else init_next_state = INIT_REFRESH; end else if ((~wrcal_done && wrlvl_byte_redo)&& (DRAM_TYPE == "DDR3") && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRLVL_LOAD_MR2; else if (((prbs_rdlvl_done && rdlvl_stg1_done && complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON")) && mem_init_done_r && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRCAL_ACT; else if (pi_dqs_found_done && (DRAM_TYPE == "DDR3") && ~(mpr_last_byte_done || mpr_rdlvl_done)) begin if (num_refresh == 'd8) init_next_state = INIT_MPR_RDEN; else init_next_state = INIT_REFRESH; end else if (((oclkdelay_calib_done && wrlvl_final && ~wrlvl_done_r1) || // changed for new algo 3/25 (~wrcal_done && wrlvl_byte_redo)) && (DRAM_TYPE == "DDR3")) init_next_state = INIT_WRLVL_LOAD_MR2; else if ((~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) && pi_dqs_found_done) init_next_state = INIT_WRCAL_ACT; else if (mem_init_done_r) begin if (RANKS < 2) init_next_state = INIT_RDLVL_ACT; else if (stg1_wr_done && ~rnk_ref_cnt && ~rdlvl_stg1_done) init_next_state = INIT_PRECHARGE; else init_next_state = INIT_RDLVL_ACT; end else // to DDR2 init state as part of DDR2 init sequence init_next_state = INIT_REFRESH; end //****************************************************** // Write Leveling //******************************************************* // Enable write leveling in MR1 and start write leveling // for current rank INIT_WRLVL_START: init_next_state = INIT_WRLVL_WAIT; // Wait for both MR load and write leveling to complete // (write leveling should take much longer than MR load..) INIT_WRLVL_WAIT: if (wrlvl_rank_done_r7 && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRLVL_LOAD_MR; // Disable write leveling in MR1 for current rank INIT_WRLVL_LOAD_MR: init_next_state = INIT_WRLVL_LOAD_MR_WAIT; INIT_WRLVL_LOAD_MR_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRLVL_LOAD_MR2; // Load MR2 to set ODT: Dynamic ODT for single rank case // And ODTs for multi-rank case as well INIT_WRLVL_LOAD_MR2: init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; // Wait tMRD before proceeding INIT_WRLVL_LOAD_MR2_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin //if (wrlvl_byte_done) // init_next_state = INIT_PRECHARGE_PREWAIT; // else if ((RANKS == 2) && wrlvl_rank_done_r2) // init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; if (~wrlvl_done_r1) init_next_state = INIT_WRLVL_START; else if (SIM_CAL_OPTION == "SKIP_CAL") // If skip rdlvl, then we're done init_next_state = INIT_DONE; else // Otherwise, proceed to read leveling //init_next_state = INIT_RDLVL_ACT; init_next_state = INIT_PRECHARGE_PREWAIT; end //******************************************************* // Read Leveling //******************************************************* // single row activate. All subsequent read leveling writes and // read will take place in this row INIT_RDLVL_ACT: init_next_state = INIT_RDLVL_ACT_WAIT; // hang out for awhile before issuing subsequent column commands // it's also possible to reach this state at various points // during read leveling - determine what the current stage is INIT_RDLVL_ACT_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin // Just finished an activate. Now either write, read, or precharge // depending on where we are in the training sequence if (!pi_calib_done_r1) init_next_state = INIT_PI_PHASELOCK_READS; else if (!pi_dqs_found_done) // (!pi_dqs_found_start || pi_dqs_found_rank_done)) init_next_state = INIT_RDLVL_STG2_READ; else if (~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) init_next_state = INIT_WRCAL_ACT_WAIT; else if ((!rdlvl_stg1_done && ~stg1_wr_done && ~rdlvl_last_byte_done) || (!prbs_rdlvl_done && ~stg1_wr_done && ~prbs_last_byte_done)) begin // Added to avoid rdlvl_stg1 write data pattern at the start of PRBS rdlvl if (!prbs_rdlvl_done && ~stg1_wr_done && rdlvl_last_byte_done) init_next_state = INIT_RDLVL_ACT_WAIT; else init_next_state = INIT_RDLVL_STG1_WRITE; end else if ((!rdlvl_stg1_done && rdlvl_stg1_start_int) || !prbs_rdlvl_done) begin if (rdlvl_last_byte_done || prbs_last_byte_done) // Added to avoid extra reads at the end of read leveling init_next_state = INIT_RDLVL_ACT_WAIT; else begin // Case 2: If in stage 1, and just precharged after training // previous byte, then continue reading if (rdlvl_stg1_done) init_next_state = INIT_RDLVL_STG1_WRITE_READ; else init_next_state = INIT_RDLVL_STG1_READ; end end else if ((prbs_rdlvl_done && rdlvl_stg1_done && (RANKS == 1)) && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRCAL_ACT_WAIT; else // Otherwise, if we're finished with calibration, then precharge // the row - silly, because we just opened it - possible to take // this out by adding logic to avoid the ACT in first place. Make // sure that cnt_cmd_done will handle tRAS(min) init_next_state = INIT_PRECHARGE_PREWAIT; end //************************************************** // Back-to-back reads for Phaser_IN Phase locking // DQS to FREQ_REF clock //************************************************** INIT_PI_PHASELOCK_READS: if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) init_next_state = INIT_PRECHARGE_PREWAIT; //********************************************* // Stage 1 read-leveling (write and continuous read) //********************************************* // Write training pattern for stage 1 // PRBS pattern of TBD length INIT_RDLVL_STG1_WRITE: // 4:1 DDR3 BL8 will require all 8 words in 1 DIV4 clock cycle // 2:1 DDR2/DDR3 BL8 will require 2 DIV2 clock cycles for 8 words // 2:1 DDR2 BL4 will require 1 DIV2 clock cycle for 4 words // An entire row worth of writes issued before proceeding to reads // The number of write is (2^column width)/burst length to accomodate // PRBS pattern for window detection. //VCCO/VCCAUX write is not done if ((complex_num_writes_dec == 1) && ~complex_row0_wr_done && prbs_rdlvl_done && rdlvl_stg1_done_r1) init_next_state = INIT_OCAL_COMPLEX_WRITE_WAIT; //back to back write from row1 else if (stg1_wr_rd_cnt == 9'd1) begin if (rdlvl_stg1_done_r1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else init_next_state = INIT_RDLVL_STG1_WRITE_READ; end INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT: if(read_pause_ext) begin init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; end else begin if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) //At the end of the byte, it goes to REFRESH init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE; end INIT_RDLVL_COMPLEX_PRECHARGE: init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; INIT_RDLVL_COMPLEX_PRECHARGE_WAIT: if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) begin if (prbs_rdlvl_done || prbs_last_byte_done_r) begin // changed for new algo 3/26 // added condition to ensure that limit starts after rdlvl_stg1_done is asserted in the bypass complex rdlvl mode if ((~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) || ~lim_done) init_next_state = INIT_OCAL_CENTER_ACT; //INIT_OCAL_COMPLEX_ACT; // changed for new algo 3/26 else if (lim_done && complex_oclkdelay_calib_start_r2) init_next_state = INIT_RDLVL_COMPLEX_ACT; else init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; end else init_next_state = INIT_RDLVL_COMPLEX_ACT; end INIT_RDLVL_COMPLEX_ACT: init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT; INIT_RDLVL_COMPLEX_ACT_WAIT: if (complex_rdlvl_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) begin if (oclkdelay_center_calib_start) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; else if (stg1_wr_done) init_next_state = INIT_RDLVL_COMPLEX_READ; else if (~complex_row1_wr_done) if (complex_oclkdelay_calib_start_int && complex_ocal_num_samples_done_r) //WAIT for resume signal for write init_next_state = INIT_OCAL_COMPLEX_RESUME_WAIT; else init_next_state = INIT_RDLVL_STG1_WRITE; else init_next_state = INIT_RDLVL_STG1_WRITE_READ; end // Write-read turnaround INIT_RDLVL_STG1_WRITE_READ: if (reset_rd_addr_r1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin if (rdlvl_stg1_done_r1) init_next_state = INIT_RDLVL_COMPLEX_READ; else init_next_state = INIT_RDLVL_STG1_READ; end // Continuous read, where interruptible by precharge request from // calibration logic. Also precharges when stage 1 is complete // No precharges when reads provided to Phaser_IN for phase locking // FREQ_REF to read DQS since data integrity is not important. INIT_RDLVL_STG1_READ: if (rdlvl_stg1_rank_done || (rdlvl_stg1_done && ~rdlvl_stg1_done_r1) || prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; INIT_RDLVL_COMPLEX_READ: if (prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; //For non-back-to-back reads from row0 (VCCO and VCCAUX pattern) else if (~prbs_rdlvl_done && (complex_num_reads_dec == 1) && ~complex_row0_rd_done) init_next_state = INIT_RDLVL_COMPLEX_READ_WAIT; //For back-to-back reads from row1 (ISI pattern) else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; INIT_RDLVL_COMPLEX_READ_WAIT: if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) init_next_state = INIT_RDLVL_COMPLEX_READ; //********************************************* // DQSFOUND calibration (set of 4 reads with gaps) //********************************************* // Read of training data. Note that Stage 2 is not a constant read, // instead there is a large gap between each set of back-to-back reads INIT_RDLVL_STG2_READ: // 4 read commands issued back-to-back if (num_reads == 'b1) init_next_state = INIT_RDLVL_STG2_READ_WAIT; // Wait before issuing the next set of reads. If a precharge request // comes in then handle - this can occur after stage 2 calibration is // completed for a DQS group INIT_RDLVL_STG2_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if (pi_dqs_found_rank_done || pi_dqs_found_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; else if (cnt_cmd_done_r) init_next_state = INIT_RDLVL_STG2_READ; end //****************************************************************** // MPR Read Leveling for DDR3 OCLK_DELAYED calibration //****************************************************************** // Issue Load Mode Register 3 command with A[2]=1, A[1:0]=2'b00 // to enable Multi Purpose Register (MPR) Read INIT_MPR_RDEN: init_next_state = INIT_MPR_WAIT; //Wait tMRD, tMOD INIT_MPR_WAIT: if (cnt_cmd_done_r) begin init_next_state = INIT_MPR_READ; end // Issue back-to-back read commands to read from MPR with // Address bus 0x0000 for BL=8. DQ[0] will output the pre-defined // MPR pattern of 01010101 (Rise0 = 1'b0, Fall0 = 1'b1 ...) INIT_MPR_READ: if (mpr_rdlvl_done || mpr_rnk_done || rdlvl_prech_req) init_next_state = INIT_MPR_DISABLE_PREWAIT; INIT_MPR_DISABLE_PREWAIT: if (cnt_cmd_done_r) init_next_state = INIT_MPR_DISABLE; // Issue Load Mode Register 3 command with A[2]=0 to disable // MPR read INIT_MPR_DISABLE: init_next_state = INIT_MPR_DISABLE_WAIT; INIT_MPR_DISABLE_WAIT: init_next_state = INIT_PRECHARGE_PREWAIT; //*********************************************************************** // OCLKDELAY Calibration //*********************************************************************** // This calibration requires single write followed by single read to // determine the Phaser_Out stage 3 delay required to center write DQS // in write DQ valid window. // Single Row Activate command before issuing Write command INIT_OCLKDELAY_ACT: init_next_state = INIT_OCLKDELAY_ACT_WAIT; INIT_OCLKDELAY_ACT_WAIT: if (cnt_cmd_done_r && ~oclk_prech_req) init_next_state = INIT_OCLKDELAY_WRITE; else if (oclkdelay_calib_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; INIT_OCLKDELAY_WRITE: if (oclk_wr_cnt == 4'd1) init_next_state = INIT_OCLKDELAY_WRITE_WAIT; INIT_OCLKDELAY_WRITE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if (oclkdelay_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else init_next_state = INIT_OCLKDELAY_READ; end INIT_OCLKDELAY_READ: init_next_state = INIT_OCLKDELAY_READ_WAIT; INIT_OCLKDELAY_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if ((oclk_calib_resume_level || oclk_calib_resume) && ~oclkdelay_int_ref_req) init_next_state = INIT_OCLKDELAY_WRITE; else if (oclkdelay_calib_done || prech_req_posedge_r || wrlvl_final || oclkdelay_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else if (oclkdelay_center_calib_start) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; end //********************************************* // Write calibration //********************************************* // single row activate INIT_WRCAL_ACT: init_next_state = INIT_WRCAL_ACT_WAIT; // hang out for awhile before issuing subsequent column command INIT_WRCAL_ACT_WAIT: if (cnt_cmd_done_r && ~wrcal_prech_req) init_next_state = INIT_WRCAL_WRITE; else if (wrcal_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; // Write training pattern for write calibration INIT_WRCAL_WRITE: // Once we've issued enough commands for 8 words - proceed to reads //if (burst_addr_r == 1'b1) if (wrcal_wr_cnt == 4'd1) init_next_state = INIT_WRCAL_WRITE_READ; // Write-read turnaround INIT_WRCAL_WRITE_READ: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRCAL_READ; else if (dqsfound_retry) init_next_state = INIT_RDLVL_STG2_READ_WAIT; INIT_WRCAL_READ: if (burst_addr_r == 1'b1) init_next_state = INIT_WRCAL_READ_WAIT; INIT_WRCAL_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if (wrcal_resume_r) begin if (wrcal_final_chk) init_next_state = INIT_WRCAL_READ; else init_next_state = INIT_WRCAL_WRITE; end else if (wrcal_done || prech_req_posedge_r || wrcal_act_req || // Added to support PO fine delay inc when TG errors wrlvl_byte_redo || (temp_wrcal_done && ~temp_lmr_done)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (dqsfound_retry) init_next_state = INIT_RDLVL_STG2_READ_WAIT; else if (wrcal_read_req && cnt_wrcal_rd) init_next_state = INIT_WRCAL_MULT_READS; end INIT_WRCAL_MULT_READS: // multiple read commands issued back-to-back if (wrcal_reads == 'b1) init_next_state = INIT_WRCAL_READ_WAIT; //********************************************* // Handling of precharge during and in between read-level stages //********************************************* // Make sure we aren't violating any timing specs by precharging // immediately INIT_PRECHARGE_PREWAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_PRECHARGE; // Initiate precharge INIT_PRECHARGE: init_next_state = INIT_PRECHARGE_WAIT; INIT_PRECHARGE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if ((wrcal_sanity_chk_done && (DRAM_TYPE == "DDR3")) || (rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && (DRAM_TYPE == "DDR2"))) init_next_state = INIT_DONE; else if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && complex_oclkdelay_calib_done && wrlvl_done_r1 && ((ddr3_lm_done_r) || (DRAM_TYPE == "DDR2"))) init_next_state = INIT_WRCAL_ACT; else if ((wrcal_done || (WRLVL == "OFF") || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) && (rdlvl_stg1_done || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) && prbs_rdlvl_done && complex_oclkdelay_calib_done && wrlvl_done_r1 &rdlvl_stg1_done && pi_dqs_found_done) begin // after all calibration program the correct burst length init_next_state = INIT_LOAD_MR; // Added to support PO fine delay inc when TG errors end else if (~wrcal_done && temp_wrcal_done && temp_lmr_done) init_next_state = INIT_WRCAL_READ_WAIT; else if (rdlvl_stg1_done && pi_dqs_found_done && (WRLVL == "ON")) // If read leveling finished, proceed to write calibration init_next_state = INIT_REFRESH; else // Otherwise, open row for read-leveling purposes init_next_state = INIT_REFRESH; end //******************************************************* // COMPLEX OCLK calibration - for fragmented write //******************************************************* INIT_OCAL_COMPLEX_ACT: init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; INIT_OCAL_COMPLEX_ACT_WAIT: if (complex_wait_cnt =='d15) init_next_state = INIT_RDLVL_STG1_WRITE; INIT_OCAL_COMPLEX_WRITE_WAIT: if (prech_req_posedge_r || (complex_oclkdelay_calib_done && ~complex_oclkdelay_calib_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) init_next_state = INIT_RDLVL_STG1_WRITE; //wait for all srg2/stg3 tap movement is done and go back to write again INIT_OCAL_COMPLEX_RESUME_WAIT: if (complex_oclk_calib_resume) init_next_state = INIT_RDLVL_STG1_WRITE; else if (complex_oclkdelay_calib_done || complex_ocal_ref_req ) init_next_state = INIT_PRECHARGE_PREWAIT; //******************************************************* // OCAL STG3 Centering calibration //******************************************************* INIT_OCAL_CENTER_ACT: init_next_state = INIT_OCAL_CENTER_ACT_WAIT; INIT_OCAL_CENTER_ACT_WAIT: if (ocal_act_wait_cnt == 'd15) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; INIT_OCAL_CENTER_WRITE: if(!oclk_center_write_resume && !lim_wr_req) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; INIT_OCAL_CENTER_WRITE_WAIT: //if (oclkdelay_center_calib_done || prech_req_posedge_r) if (prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && oclkdelay_calib_done && ~oclkdelay_center_calib_start) init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && ~oclkdelay_center_calib_start) init_next_state = INIT_OCLKDELAY_READ_WAIT; else if (oclk_center_write_resume || lim_wr_req) init_next_state = INIT_OCAL_CENTER_WRITE; //******************************************************* // Initialization/Calibration done. Take a long rest, relax //******************************************************* INIT_DONE: init_next_state = INIT_DONE; endcase end //***************************************************************** // Initialization done signal - asserted before leveling starts //***************************************************************** always @(posedge clk) if (rst) mem_init_done_r <= #TCQ 1'b0; else if ((!cnt_dllk_zqinit_done_r && (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) && (chip_cnt_r == RANKS-1) && (DRAM_TYPE == "DDR3")) || ( (init_state_r == INIT_LOAD_MR_WAIT) && (ddr2_refresh_flag_r) && (chip_cnt_r == RANKS-1) && (cnt_init_mr_done_r) && (DRAM_TYPE == "DDR2"))) mem_init_done_r <= #TCQ 1'b1; //***************************************************************** // Write Calibration signal to PHY Control Block - asserted before // Write Leveling starts //***************************************************************** //generate //if (RANKS < 2) begin: ranks_one always @(posedge clk) begin if (rst || (done_dqs_tap_inc && (init_state_r == INIT_WRLVL_LOAD_MR2))) write_calib <= #TCQ 1'b0; else if (wrlvl_active_r1) write_calib <= #TCQ 1'b1; end //end else begin: ranks_two // always @(posedge clk) begin // if (rst || // ((init_state_r1 == INIT_WRLVL_LOAD_MR_WAIT) && // ((wrlvl_rank_done_r2 && (chip_cnt_r == RANKS-1)) || // (SIM_CAL_OPTION == "FAST_CAL")))) // write_calib <= #TCQ 1'b0; // else if (wrlvl_active_r1) // write_calib <= #TCQ 1'b1; // end //end //endgenerate //***************************************************************** // Read Calibration signal to PHY Control Block - asserted after // Write Leveling during PHASER_IN phase locking stage. // Must be de-asserted before Read Leveling //***************************************************************** always @(posedge clk) begin if (rst || pi_calib_done_r1) read_calib_int <= #TCQ 1'b0; else if (~pi_calib_done_r1 && (init_state_r == INIT_RDLVL_ACT_WAIT) && (cnt_cmd_r == CNTNEXT_CMD)) read_calib_int <= #TCQ 1'b1; end always @(posedge clk) read_calib_r <= #TCQ read_calib_int; always @(posedge clk) begin if (rst || pi_calib_done_r1) read_calib <= #TCQ 1'b0; else if (~pi_calib_done_r1 && (init_state_r == INIT_PI_PHASELOCK_READS)) read_calib <= #TCQ 1'b1; end always @(posedge clk) if (rst) pi_calib_done_r <= #TCQ 1'b0; else if (pi_calib_rank_done_r)// && (chip_cnt_r == RANKS-1)) pi_calib_done_r <= #TCQ 1'b1; always @(posedge clk) if (rst) pi_calib_rank_done_r <= #TCQ 1'b0; else if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) pi_calib_rank_done_r <= #TCQ 1'b1; else pi_calib_rank_done_r <= #TCQ 1'b0; always @(posedge clk) begin if (rst || ((PRE_REV3ES == "ON") && temp_wrcal_done && ~temp_wrcal_done_r)) pi_phaselock_timer <= #TCQ 'd0; else if (((init_state_r == INIT_PI_PHASELOCK_READS) && (pi_phaselock_timer != PHASELOCKED_TIMEOUT)) || tg_timer_go) pi_phaselock_timer <= #TCQ pi_phaselock_timer + 1; else pi_phaselock_timer <= #TCQ pi_phaselock_timer; end assign pi_phase_locked_err = (pi_phaselock_timer == PHASELOCKED_TIMEOUT) ? 1'b1 : 1'b0; //***************************************************************** // DDR3 final burst length programming done. For DDR3 during // calibration the burst length is fixed to BL8. After calibration // the correct burst length is programmed. //***************************************************************** always @(posedge clk) if (rst) ddr3_lm_done_r <= #TCQ 1'b0; else if ((init_state_r == INIT_LOAD_MR_WAIT) && (chip_cnt_r == RANKS-1) && wrcal_done) ddr3_lm_done_r <= #TCQ 1'b1; always @(posedge clk) begin pi_dqs_found_rank_done_r <= #TCQ pi_dqs_found_rank_done; pi_phase_locked_all_r1 <= #TCQ pi_phase_locked_all; pi_phase_locked_all_r2 <= #TCQ pi_phase_locked_all_r1; pi_phase_locked_all_r3 <= #TCQ pi_phase_locked_all_r2; pi_phase_locked_all_r4 <= #TCQ pi_phase_locked_all_r3; pi_dqs_found_all_r <= #TCQ pi_dqs_found_done; pi_calib_done_r1 <= #TCQ pi_calib_done_r; end //*************************************************************************** // Logic for deep memory (multi-rank) configurations //*************************************************************************** // For DDR3 asserted when generate if (RANKS < 2) begin: single_rank always @(posedge clk) chip_cnt_r <= #TCQ 2'b00; end else begin: dual_rank always @(posedge clk) if (rst || // Set chip_cnt_r to 2'b00 after both Ranks are read leveled (rdlvl_stg1_done && prbs_rdlvl_done && ~wrcal_done) || // Set chip_cnt_r to 2'b00 after both Ranks are write leveled (wrlvl_done_r && (init_state_r==INIT_WRLVL_LOAD_MR2_WAIT)))begin chip_cnt_r <= #TCQ 2'b00; end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) && (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT)) && (DRAM_TYPE == "DDR3")) || ((init_state_r==INIT_REFRESH_RNK2_WAIT) && (cnt_cmd_r=='d36)) || //mpr_rnk_done || //(rdlvl_stg1_rank_done && ~rdlvl_last_byte_done) || //(stg1_wr_done && (init_state_r == INIT_REFRESH) && //~(rnk_ref_cnt && rdlvl_last_byte_done)) || // Increment chip_cnt_r to issue Refresh to second rank (~pi_dqs_found_all_r && (init_state_r==INIT_PRECHARGE_PREWAIT) && (cnt_cmd_r=='d36)) || // Increment chip_cnt_r when DQSFOUND done for the Rank (pi_dqs_found_rank_done && ~pi_dqs_found_rank_done_r) || ((init_state_r == INIT_LOAD_MR_WAIT)&& cnt_cmd_done_r && wrcal_done) || ((init_state_r == INIT_DDR2_MULTI_RANK) && (DRAM_TYPE == "DDR2"))) begin if ((~mem_init_done_r || ~rdlvl_stg1_done || ~pi_dqs_found_done || // condition to increment chip_cnt during // final burst length programming for DDR3 ~pi_calib_done_r || wrcal_done) //~mpr_rdlvl_done || && (chip_cnt_r != RANKS-1)) chip_cnt_r <= #TCQ chip_cnt_r + 1; else chip_cnt_r <= #TCQ 2'b00; end end endgenerate // verilint STARC-2.2.3.3 off generate if ((REG_CTRL == "ON") && (RANKS == 1)) begin: DDR3_RDIMM_1rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[0] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end end else if (RANKS == 1) begin: DDR3_1rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (n = 0; n < nCS_PER_RANK; n = n + 1) begin phy_int_cs_n[n] <= #TCQ 1'b0; end end else begin //odd CWL for (p = nCS_PER_RANK; p < 2*nCS_PER_RANK; p = p + 1) begin phy_int_cs_n[p] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end end else if ((REG_CTRL == "ON") && (RANKS == 2)) begin: DDR3_2rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; case (chip_cnt_r) 2'b00:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[0] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end 2'b01:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[1] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1+1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end endcase end end end else if (RANKS == 2) begin: DDR3_2rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; case (chip_cnt_r) 2'b00:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (n = 0; n < nCS_PER_RANK; n = n + 1) begin phy_int_cs_n[n] <= #TCQ 1'b0; end end else begin // odd CWL for (p = CS_WIDTH*nCS_PER_RANK; p < (CS_WIDTH*nCS_PER_RANK + nCS_PER_RANK); p = p + 1) begin phy_int_cs_n[p] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end 2'b01:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (q = nCS_PER_RANK; q < (2 * nCS_PER_RANK); q = q + 1) begin phy_int_cs_n[q] <= #TCQ 1'b0; end end else begin // odd CWL for (m = (nCS_PER_RANK*CS_WIDTH + nCS_PER_RANK); m < (nCS_PER_RANK*CS_WIDTH + 2*nCS_PER_RANK); m = m + 1) begin phy_int_cs_n[m] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end endcase end end // always @ (posedge clk) end // verilint STARC-2.2.3.3 on // commented out for now. Need it for DDR2 2T timing /* end else begin: DDR2 always @(posedge clk) if (rst) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end else begin if (init_state_r == INIT_REG_WRITE) begin // All ranks selected simultaneously phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}}; end else if ((wrlvl_odt) || (init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH)) begin phy_int_cs_n[0] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end // else: !if(rst) end // block: DDR2 */ endgenerate assign phy_cs_n = phy_int_cs_n; //*************************************************************************** // Write/read burst logic for calibration //*************************************************************************** assign rdlvl_wr = (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE); assign rdlvl_rd = (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_MPR_READ) || (init_state_r == INIT_WRCAL_MULT_READS); assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd; assign mmcm_wr = (init_state_r == INIT_OCAL_CENTER_WRITE); //used to de-assert cs_n during centering // assign mmcm_wr = 'b0; // (init_state_r == INIT_OCAL_CENTER_WRITE); //*************************************************************************** // Address generation and logic to count # of writes/reads issued during // certain stages of calibration //*************************************************************************** // Column address generation logic: // Keep track of the current column address - since all bursts are in // increments of 8 only during calibration, we need to keep track of // addresses [COL_WIDTH-1:3], lower order address bits will always = 0 always @(posedge clk) if (rst || wrcal_done) burst_addr_r <= #TCQ 1'b0; else if ((init_state_r == INIT_WRCAL_ACT_WAIT) || (init_state_r == INIT_OCLKDELAY_ACT_WAIT) || (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS) || (init_state_r == INIT_WRCAL_READ_WAIT)) burst_addr_r <= #TCQ 1'b1; else if (rdlvl_wr_rd && new_burst_r) burst_addr_r <= #TCQ ~burst_addr_r; else burst_addr_r <= #TCQ 1'b0; // Read Level Stage 1 requires writes to the entire row since // a PRBS pattern is being written. This counter keeps track // of the number of writes which depends on the column width // The (stg1_wr_rd_cnt==9'd0) condition was added so the col // address wraps around during stage1 reads always @(posedge clk) if (rst || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && ~rdlvl_stg1_done)) stg1_wr_rd_cnt <= #TCQ NUM_STG1_WR_RD; else if (rdlvl_last_byte_done || (stg1_wr_rd_cnt == 9'd1) || (prbs_rdlvl_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || (init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) ) begin if (~complex_row0_wr_done || wr_victim_inc || (complex_row1_wr_done && (~complex_row0_rd_done || (complex_row0_rd_done && complex_row1_rd_done)))) stg1_wr_rd_cnt <= #TCQ 'd127; else stg1_wr_rd_cnt <= #TCQ prbs_rdlvl_done?'d30 :'d22; end else if (((init_state_r == INIT_RDLVL_STG1_WRITE) && new_burst_r && ~phy_data_full) ||((init_state_r == INIT_RDLVL_COMPLEX_READ) && rdlvl_stg1_done)) stg1_wr_rd_cnt <= #TCQ stg1_wr_rd_cnt - 1; always @(posedge clk) if (rst) wr_victim_inc <= #TCQ 1'b0; else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2) && ~stg1_wr_done) wr_victim_inc <= #TCQ 1'b1; else wr_victim_inc <= #TCQ 1'b0; always @(posedge clk) reset_rd_addr_r1 <= #TCQ reset_rd_addr; generate if (FIXED_VICTIM == "FALSE") begin: row_cnt_victim_rotate always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt == DQ_WIDTH*2-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) complex_row_cnt <= #TCQ 'd0; else if ((((stg1_wr_rd_cnt == 'd22) && ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (complex_rdlvl_int_ref_req && (init_state_r == INIT_REFRESH_WAIT) && (cnt_cmd_r == 'd127)))) || complex_victim_inc || (complex_sample_cnt_inc_r2 && ~complex_victim_inc) || wr_victim_inc || reset_rd_addr_r1)) begin // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 if ((complex_row_cnt < DQ_WIDTH*2-1) && ~stg1_wr_done) complex_row_cnt <= #TCQ complex_row_cnt + 1; // During reads row count requires different conditions for increments else if (stg1_wr_done) begin if (reset_rd_addr_r1) complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16; // When looping multiple times in the same victim bit in a byte else if (complex_sample_cnt_inc_r2 && ~complex_victim_inc) complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16 + rd_victim_sel*2; // When looping through victim bits within a byte else if (complex_row_cnt < pi_stg2_prbs_rdlvl_cnt*16+15) complex_row_cnt <= #TCQ complex_row_cnt + 1; // When the number of samples is done and tap is incremented within a byte else complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16; end end end else begin: row_cnt_victim_fixed always @(posedge clk) if (rst || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) complex_row_cnt <= #TCQ 'd0; else if ((stg1_wr_rd_cnt == 'd22) && (((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) && (complex_wait_cnt == 'd15)) || complex_rdlvl_int_ref_req)) complex_row_cnt <= #TCQ 'd1; else complex_row_cnt <= #TCQ 'd0; end endgenerate //row count always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done_pulse || complex_byte_rd_done) complex_row_cnt_ocal <= #TCQ 'd0; else if ( prbs_rdlvl_done && (((stg1_wr_rd_cnt == 'd30) && (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE)) || (complex_sample_cnt_inc_r2) || wr_victim_inc)) begin // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 if (complex_row_cnt_ocal < COMPLEX_ROW_CNT_BYTE-1) begin complex_row_cnt_ocal <= #TCQ complex_row_cnt_ocal + 1; end end always @(posedge clk) if (rst) complex_odt_ext <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE)) complex_odt_ext <= #TCQ 1'b0; else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd1) && (init_state_r == INIT_RDLVL_STG1_WRITE)) complex_odt_ext <= #TCQ 1'b1; always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt == DQ_WIDTH*2-1))) begin wr_victim_sel <= #TCQ 'd0; wr_byte_cnt <= #TCQ 'd0; end else if (rdlvl_stg1_done_r1 && wr_victim_inc) begin wr_victim_sel <= #TCQ wr_victim_sel + 1; if (wr_victim_sel == 'd7) wr_byte_cnt <= #TCQ wr_byte_cnt + 1; end always @(posedge clk) if (rst) begin wr_victim_sel_ocal <= #TCQ 'd0; end else if (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) begin wr_victim_sel_ocal <= #TCQ 'd0; end else if (prbs_rdlvl_done && wr_victim_inc) begin wr_victim_sel_ocal <= #TCQ wr_victim_sel_ocal + 1; end always @(posedge clk) if (rst) begin victim_sel <= #TCQ 'd0; victim_byte_cnt <= #TCQ 'd0; end else if ((~stg1_wr_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_wr_done)) begin victim_sel <= #TCQ prbs_rdlvl_done? wr_victim_sel_ocal: wr_victim_sel; victim_byte_cnt <= #TCQ prbs_rdlvl_done? complex_oclkdelay_calib_cnt:wr_byte_cnt; end else begin if( (init_state_r == INIT_RDLVL_COMPLEX_ACT) || reset_rd_addr) victim_sel <= #TCQ prbs_rdlvl_done? complex_ocal_rd_victim_sel:rd_victim_sel; victim_byte_cnt <= #TCQ prbs_rdlvl_done? complex_oclkdelay_calib_cnt:pi_stg2_prbs_rdlvl_cnt; end generate if (FIXED_VICTIM == "FALSE") begin: wr_done_victim_rotate always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt < DQ_WIDTH*2-1) && ~prbs_rdlvl_done) || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done || prbs_rdlvl_done_pulse) begin complex_row0_wr_done <= #TCQ 1'b0; end else if ( rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd2)) begin complex_row0_wr_done <= #TCQ 1'b1; end always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt < DQ_WIDTH*2-1) && ~prbs_rdlvl_done) || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done || prbs_rdlvl_done_pulse) begin complex_row1_wr_done <= #TCQ 1'b0; end else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2)) begin complex_row1_wr_done <= #TCQ 1'b1; end end else begin: wr_done_victim_fixed always @(posedge clk) if (rst || prbs_rdlvl_done_pulse || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done ) begin complex_row0_wr_done <= #TCQ 1'b0; end else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd2)) begin complex_row0_wr_done <= #TCQ 1'b1; end always @(posedge clk) if (rst || prbs_rdlvl_done_pulse || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done ) begin complex_row1_wr_done <= #TCQ 1'b0; end else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2)) begin complex_row1_wr_done <= #TCQ 1'b1; end end endgenerate always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row0_rd_done <= #TCQ 1'b0; else if (complex_sample_cnt_inc) complex_row0_rd_done <= #TCQ 1'b0; else if ( (prbs_rdlvl_start || complex_oclkdelay_calib_start_int) && (stg1_wr_rd_cnt == 9'd2) && complex_row0_wr_done && complex_row1_wr_done) complex_row0_rd_done <= #TCQ 1'b1; always @(posedge clk) complex_row0_rd_done_r1 <= #TCQ complex_row0_rd_done; always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row1_rd_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE)) complex_row1_rd_done <= #TCQ 1'b0; else if (complex_row0_rd_done && (stg1_wr_rd_cnt == 9'd2)) complex_row1_rd_done <= #TCQ 1'b1; always @(posedge clk) complex_row1_rd_done_r1 <= #TCQ complex_row1_rd_done; //calculate row rd num for complex_oclkdelay_calib //once it reached to 8 always @ (posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row1_rd_cnt <= #TCQ 'd0; else complex_row1_rd_cnt <= #TCQ (complex_row1_rd_done & ~complex_row1_rd_done_r1) ? ((complex_row1_rd_cnt == (COMPLEX_RD-1))? 0:complex_row1_rd_cnt + 'd1) : complex_row1_rd_cnt; //For write, reset rd_done for the byte always @ (posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_STG1_WRITE) || prbs_rdlvl_done_pulse) complex_byte_rd_done <= #TCQ 'b0; else if (prbs_rdlvl_done && (complex_row1_rd_cnt == (COMPLEX_RD-1)) && (complex_row1_rd_done & ~complex_row1_rd_done_r1)) complex_byte_rd_done <= #TCQ 'b1; end always @ (posedge clk) begin complex_byte_rd_done_r1 <= #TCQ complex_byte_rd_done; complex_ocal_num_samples_inc <= #TCQ (complex_byte_rd_done & ~complex_byte_rd_done_r1); end generate if (RANKS < 2) begin: one_rank_complex always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || ( complex_oclkdelay_calib_done && (init_state_r == INIT_RDLVL_STG1_WRITE )) || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT) || prbs_rdlvl_done_pulse ) complex_wr_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; else if ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; end else begin: dual_rank_complex always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || ( complex_oclkdelay_calib_done && (init_state_r == INIT_RDLVL_STG1_WRITE )) || (rdlvl_stg1_rank_done ) || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT) || prbs_rdlvl_done_pulse ) complex_wr_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; else if ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst) complex_wait_cnt <= #TCQ 'd0; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && complex_wait_cnt < 'd15) complex_wait_cnt <= #TCQ complex_wait_cnt + 1; else complex_wait_cnt <= #TCQ 'd0; always @(posedge clk) if (rst) begin complex_num_reads <= #TCQ 'd1; end else if ((((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd14)) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && ext_int_ref_req && (cnt_cmd_r == 'd127))) && ~complex_row0_rd_done) begin if (stg1_wr_rd_cnt > 'd85) begin if (complex_num_reads < 'd6) complex_num_reads <= #TCQ complex_num_reads + 1; else complex_num_reads <= #TCQ 'd1; // Initila value for VCCAUX pattern is 3, 7, and 12 end else if (stg1_wr_rd_cnt > 'd73) begin if (stg1_wr_rd_cnt == 'd85) complex_num_reads <= #TCQ 'd3; else if (complex_num_reads < 'd5) complex_num_reads <= #TCQ complex_num_reads + 1; end else if (stg1_wr_rd_cnt > 'd39) begin if (stg1_wr_rd_cnt == 'd73) complex_num_reads <= #TCQ 'd7; else if (complex_num_reads < 'd10) complex_num_reads <= #TCQ complex_num_reads + 1; end else begin if (stg1_wr_rd_cnt == 'd39) complex_num_reads <= #TCQ 'd12; else if (complex_num_reads < 'd14) complex_num_reads <= #TCQ complex_num_reads + 1; end // Initialize to 1 at the start of reads or after precharge and activate end else if ((((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && ~ext_int_ref_req) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && (stg1_wr_rd_cnt == 'd22))) complex_num_reads <= #TCQ 'd1; always @(posedge clk) if (rst) complex_num_reads_dec <= #TCQ 'd1; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) complex_num_reads_dec <= #TCQ complex_num_reads; else if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (complex_num_reads_dec > 'd0)) complex_num_reads_dec <= #TCQ complex_num_reads_dec - 1; always @(posedge clk) if (rst) complex_address <= #TCQ 'd0; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ_WAIT)) || ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (init_state_r1 != INIT_OCAL_COMPLEX_WRITE_WAIT))) complex_address <= #TCQ phy_address[COL_WIDTH-1:0]; always @ (posedge clk) if (rst) complex_oclkdelay_calib_start_int <= #TCQ 'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && prbs_last_byte_done_r) // changed for new algo 3/26 complex_oclkdelay_calib_start_int <= #TCQ 'b1; always @(posedge clk) begin complex_oclkdelay_calib_start_r1 <= #TCQ complex_oclkdelay_calib_start_int; complex_oclkdelay_calib_start_r2 <= #TCQ complex_oclkdelay_calib_start_r1; end always @ (posedge clk) if (rst) complex_oclkdelay_calib_start <= #TCQ 'b0; else if (complex_oclkdelay_calib_start_int && (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT) && prbs_rdlvl_done) // changed for new algo 3/26 complex_oclkdelay_calib_start <= #TCQ 'b1; //packet fragmentation for complex oclkdealy calib write always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) begin complex_num_writes <= #TCQ 'd1; end else if ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14) && ~complex_row0_wr_done) begin if (stg1_wr_rd_cnt > 'd85) begin if (complex_num_writes < 'd6) complex_num_writes <= #TCQ complex_num_writes + 1; else complex_num_writes <= #TCQ 'd1; // Initila value for VCCAUX pattern is 3, 7, and 12 end else if (stg1_wr_rd_cnt > 'd73) begin if (stg1_wr_rd_cnt == 'd85) complex_num_writes <= #TCQ 'd3; else if (complex_num_writes < 'd5) complex_num_writes <= #TCQ complex_num_writes + 1; end else if (stg1_wr_rd_cnt > 'd39) begin if (stg1_wr_rd_cnt == 'd73) complex_num_writes <= #TCQ 'd7; else if (complex_num_writes < 'd10) complex_num_writes <= #TCQ complex_num_writes + 1; end else begin if (stg1_wr_rd_cnt == 'd39) complex_num_writes <= #TCQ 'd12; else if (complex_num_writes < 'd14) complex_num_writes <= #TCQ complex_num_writes + 1; end // Initialize to 1 at the start of write or after precharge and activate end else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row0_wr_done) complex_num_writes <= #TCQ 'd30; else if (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) complex_num_writes <= #TCQ 'd1; always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_num_writes_dec <= #TCQ 'd1; else if (((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) complex_num_writes_dec <= #TCQ complex_num_writes; else if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (complex_num_writes_dec > 'd0)) complex_num_writes_dec <= #TCQ complex_num_writes_dec - 1; always @(posedge clk) if (rst) complex_sample_cnt_inc_ocal <= #TCQ 1'b0; else if ((stg1_wr_rd_cnt == 9'd1) && complex_byte_rd_done && prbs_rdlvl_done) complex_sample_cnt_inc_ocal <= #TCQ 1'b1; else complex_sample_cnt_inc_ocal <= #TCQ 1'b0; always @(posedge clk) if (rst) complex_sample_cnt_inc <= #TCQ 1'b0; else if ((stg1_wr_rd_cnt == 9'd1) && complex_row1_rd_done) complex_sample_cnt_inc <= #TCQ 1'b1; else complex_sample_cnt_inc <= #TCQ 1'b0; always @(posedge clk) begin complex_sample_cnt_inc_r1 <= #TCQ complex_sample_cnt_inc; complex_sample_cnt_inc_r2 <= #TCQ complex_sample_cnt_inc_r1; end //complex refresh req always @ (posedge clk) begin if(rst || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_ACT)) ) complex_ocal_ref_done <= #TCQ 1'b1; else if (init_state_r == INIT_RDLVL_STG1_WRITE) complex_ocal_ref_done <= #TCQ 1'b0; end //complex ocal odt extention always @(posedge clk) if (rst) complex_ocal_odt_ext <= #TCQ 1'b0; else if (((init_state_r == INIT_PRECHARGE_PREWAIT) && cnt_cmd_done_m7_r) || (init_state_r == INIT_OCLKDELAY_READ_WAIT)) complex_ocal_odt_ext <= #TCQ 1'b0; else if ((init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT)) complex_ocal_odt_ext <= #TCQ 1'b1; // OCLKDELAY calibration requires multiple writes because // write can be up to 2 cycles early since OCLKDELAY tap // can go down to 0 always @(posedge clk) if (rst || (init_state_r == INIT_OCLKDELAY_WRITE_WAIT) || (oclk_wr_cnt == 4'd0)) oclk_wr_cnt <= #TCQ NUM_STG1_WR_RD; else if ((init_state_r == INIT_OCLKDELAY_WRITE) && new_burst_r && ~phy_data_full) oclk_wr_cnt <= #TCQ oclk_wr_cnt - 1; // Write calibration requires multiple writes because // write can be up to 2 cycles early due to new write // leveling algorithm to avoid late writes always @(posedge clk) if (rst || (init_state_r == INIT_WRCAL_WRITE_READ) || (wrcal_wr_cnt == 4'd0)) wrcal_wr_cnt <= #TCQ NUM_STG1_WR_RD; else if ((init_state_r == INIT_WRCAL_WRITE) && new_burst_r && ~phy_data_full) wrcal_wr_cnt <= #TCQ wrcal_wr_cnt - 1; generate if(nCK_PER_CLK == 4) begin:back_to_back_reads_4_1 // 4 back-to-back reads with gaps for // read data_offset calibration (rdlvl stage 2) always @(posedge clk) if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) num_reads <= #TCQ 3'b000; else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) num_reads <= #TCQ num_reads - 1; else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || phy_cmd_full && new_burst_r) num_reads <= #TCQ 3'b011; end else if(nCK_PER_CLK == 2) begin: back_to_back_reads_2_1 // 4 back-to-back reads with gaps for // read data_offset calibration (rdlvl stage 2) always @(posedge clk) if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) num_reads <= #TCQ 3'b000; else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) num_reads <= #TCQ num_reads - 1; else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || phy_cmd_full && new_burst_r) num_reads <= #TCQ 3'b111; end endgenerate // back-to-back reads during write calibration always @(posedge clk) if (rst ||(init_state_r == INIT_WRCAL_READ_WAIT)) wrcal_reads <= #TCQ 2'b00; else if ((wrcal_reads > 2'b00) && ~(phy_ctl_full || phy_cmd_full)) wrcal_reads <= #TCQ wrcal_reads - 1; else if ((init_state_r == INIT_WRCAL_MULT_READS) || phy_ctl_full || phy_cmd_full && new_burst_r) wrcal_reads <= #TCQ 'd255; // determine how often to issue row command during read leveling writes // and reads always @(posedge clk) if (rdlvl_wr_rd) begin // 2:1 mode - every other command issued is a data command // 4:1 mode - every command issued is a data command if (nCK_PER_CLK == 2) begin if (!phy_ctl_full) new_burst_r <= #TCQ ~new_burst_r; end else new_burst_r <= #TCQ 1'b1; end else new_burst_r <= #TCQ 1'b1; // indicate when a write is occurring. PHY_WRDATA_EN must be asserted // simultaneous with the corresponding command/address for CWL = 5,6 always @(posedge clk) begin rdlvl_wr_r <= #TCQ rdlvl_wr; calib_wrdata_en <= #TCQ phy_wrdata_en; end always @(posedge clk) begin if (rst || wrcal_done) extend_cal_pat <= #TCQ 1'b0; else if (temp_lmr_done && (PRE_REV3ES == "ON")) extend_cal_pat <= #TCQ 1'b1; end generate if ((nCK_PER_CLK == 4) || (BURST_MODE == "4")) begin: wrdqen_div4 // Write data enable asserted for one DIV4 clock cycle // Only BL8 supported with DIV4. DDR2 BL4 will use DIV2. always @(*) begin if (~phy_data_full && ((init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_WRCAL_WRITE))) phy_wrdata_en = 1'b1; else phy_wrdata_en = 1'b0; end end else begin: wrdqen_div2 // block: wrdqen_div4 always @(*) if((rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full) | phy_wrdata_en_r1) phy_wrdata_en = 1'b1; else phy_wrdata_en = 1'b0; always @(posedge clk) phy_wrdata_en_r1 <= #TCQ rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full; always @(posedge clk) begin if (!phy_wrdata_en & first_rdlvl_pat_r) wrdata_pat_cnt <= #TCQ 2'b00; else if (wrdata_pat_cnt == 2'b11) wrdata_pat_cnt <= #TCQ 2'b10; else wrdata_pat_cnt <= #TCQ wrdata_pat_cnt + 1; end always @(posedge clk) begin if (!phy_wrdata_en & first_wrcal_pat_r) wrcal_pat_cnt <= #TCQ 2'b00; else if (extend_cal_pat && (wrcal_pat_cnt == 2'b01)) wrcal_pat_cnt <= #TCQ 2'b00; else if (wrcal_pat_cnt == 2'b11) wrcal_pat_cnt <= #TCQ 2'b10; else wrcal_pat_cnt <= #TCQ wrcal_pat_cnt + 1; end end endgenerate // indicate when a write is occurring. PHY_RDDATA_EN must be asserted // simultaneous with the corresponding command/address. PHY_RDDATA_EN // is used during read-leveling to determine read latency assign phy_rddata_en = ~phy_if_empty; // Read data valid generation for MC and User Interface after calibration is // complete assign phy_rddata_valid = init_complete_r1_timing ? phy_rddata_en : 1'b0; //*************************************************************************** // Generate training data written at start of each read-leveling stage // For every stage of read leveling, 8 words are written into memory // The format is as follows (shown as {rise,fall}): // Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0 // Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 //*************************************************************************** always @(posedge clk) if ((init_state_r == INIT_IDLE) || (init_state_r == INIT_RDLVL_STG1_WRITE)) cnt_init_data_r <= #TCQ 2'b00; else if (phy_wrdata_en) cnt_init_data_r <= #TCQ cnt_init_data_r + 1; else if (init_state_r == INIT_WRCAL_WRITE) cnt_init_data_r <= #TCQ 2'b10; // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling always @(posedge clk) if (rst || rdlvl_stg1_rank_done) first_rdlvl_pat_r <= #TCQ 1'b1; else if (phy_wrdata_en && (init_state_r == INIT_RDLVL_STG1_WRITE)) first_rdlvl_pat_r <= #TCQ 1'b0; always @(posedge clk) if (rst || wrcal_resume || (init_state_r == INIT_WRCAL_ACT_WAIT)) first_wrcal_pat_r <= #TCQ 1'b1; else if (phy_wrdata_en && (init_state_r == INIT_WRCAL_WRITE)) first_wrcal_pat_r <= #TCQ 1'b0; generate if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 2)) begin: wrdq_div2_2to1_rdlvl_first always @(posedge clk) if (~oclkdelay_calib_done) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}}; else if (!rdlvl_stg1_done) begin // The 16 words for stage 1 write data in 2:1 mode is written // over 4 consecutive controller clock cycles. Note that write // data follows phy_wrdata_en by one clock cycle case (wrdata_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}}, {DQ_WIDTH/4{4'h9}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end endcase end else if (!prbs_rdlvl_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ end else if (!wrcal_done) begin case (wrcal_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h5}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, {DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h4}}}; end endcase end end else if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 4)) begin: wrdq_div2_4to1_rdlvl_first always @(posedge clk) if (~oclkdelay_calib_done) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; else if (!rdlvl_stg1_done && ~phy_data_full) // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling if (first_rdlvl_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; else // For all others, change the first two words written in order // to differentiate the "early write" and "on-time write" // readback patterns during read leveling phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; else if (~(prbs_rdlvl_done || prbs_last_byte_done_r) && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ else if (!wrcal_done) if (first_wrcal_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (nCK_PER_CLK == 4) begin: wrdq_div1_4to1_wrcal_first always @(posedge clk) if ((~oclkdelay_calib_done) && (DRAM_TYPE == "DDR3")) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; else if ((!wrcal_done)&& (DRAM_TYPE == "DDR3")) begin if (extend_cal_pat) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else if (first_wrcal_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (!rdlvl_stg1_done && ~phy_data_full) begin // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling if (first_rdlvl_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; else // For all others, change the first two words written in order // to differentiate the "early write" and "on-time write" // readback patterns during read leveling phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (!prbs_rdlvl_done && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ else if (!complex_oclkdelay_calib_done && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; end else begin: wrdq_div1_2to1_wrcal_first always @(posedge clk) if ((~oclkdelay_calib_done)&& (DRAM_TYPE == "DDR3")) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}}; else if ((!wrcal_done) && (DRAM_TYPE == "DDR3"))begin case (wrcal_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h5}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, {DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h4}}}; end endcase end else if (!rdlvl_stg1_done) begin // The 16 words for stage 1 write data in 2:1 mode is written // over 4 consecutive controller clock cycles. Note that write // data follows phy_wrdata_en by one clock cycle case (wrdata_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}}, {DQ_WIDTH/4{4'h9}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end endcase end else if (!prbs_rdlvl_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ end else if (!complex_oclkdelay_calib_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; end end endgenerate //*************************************************************************** // Memory control/address //*************************************************************************** // Phases [2] and [3] are always deasserted for 4:1 mode generate if (nCK_PER_CLK == 4) begin: gen_div4_ca_tieoff always @(posedge clk) begin phy_ras_n[3:2] <= #TCQ 3'b11; phy_cas_n[3:2] <= #TCQ 3'b11; phy_we_n[3:2] <= #TCQ 3'b11; end end endgenerate // Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging // (4) auto refresh // verilint STARC-2.7.3.3b off generate if (!(CWL_M % 2)) begin: even_cwl always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT))begin phy_ras_n[0] <= #TCQ 1'b0; phy_ras_n[1] <= #TCQ 1'b1; end else begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b1; end end // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command // (3) auto refresh always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_REFRESH) || (rdlvl_wr_rd && new_burst_r))begin phy_cas_n[0] <= #TCQ 1'b0; phy_cas_n[1] <= #TCQ 1'b1; end else begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b1; end end // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only // occur during read leveling), (3) Issuing ZQ Long Calib command, // (4) Precharge always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE)|| (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (rdlvl_wr && new_burst_r))begin phy_we_n[0] <= #TCQ 1'b0; phy_we_n[1] <= #TCQ 1'b1; end else begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b1; end end end else begin: odd_cwl always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_REFRESH))begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b0; end else begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b1; end end // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command // (3) auto refresh always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_REFRESH) || (rdlvl_wr_rd && new_burst_r))begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b0; end else begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b1; end end // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only // occur during read leveling), (3) Issuing ZQ Long Calib command, // (4) Precharge always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE)|| (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (rdlvl_wr && new_burst_r))begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b0; end else begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b1; end end end endgenerate // verilint STARC-2.7.3.3b on // Assign calib_cmd for the command field in PHY_Ctl_Word always @(posedge clk) begin if (wr_level_dqs_asrt) begin // Request to toggle DQS during write leveling calib_cmd <= #TCQ 3'b001; if (CWL_M % 2) begin // odd write latency calib_data_offset_0 <= #TCQ CWL_M + 3; calib_data_offset_1 <= #TCQ CWL_M + 3; calib_data_offset_2 <= #TCQ CWL_M + 3; calib_cas_slot <= #TCQ 2'b01; end else begin // even write latency calib_data_offset_0 <= #TCQ CWL_M + 2; calib_data_offset_1 <= #TCQ CWL_M + 2; calib_data_offset_2 <= #TCQ CWL_M + 2; calib_cas_slot <= #TCQ 2'b00; end end else if (rdlvl_wr && new_burst_r) begin // Write Command calib_cmd <= #TCQ 3'b001; if (CWL_M % 2) begin // odd write latency calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_cas_slot <= #TCQ 2'b01; end else begin // even write latency calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_cas_slot <= #TCQ 2'b00; end end else if (rdlvl_rd && new_burst_r) begin // Read Command calib_cmd <= #TCQ 3'b011; if (CWL_M % 2) calib_cas_slot <= #TCQ 2'b01; else calib_cas_slot <= #TCQ 2'b00; if (~pi_calib_done_r1) begin calib_data_offset_0 <= #TCQ 6'd0; calib_data_offset_1 <= #TCQ 6'd0; calib_data_offset_2 <= #TCQ 6'd0; end else if (~pi_dqs_found_done_r1) begin calib_data_offset_0 <= #TCQ rd_data_offset_0; calib_data_offset_1 <= #TCQ rd_data_offset_1; calib_data_offset_2 <= #TCQ rd_data_offset_2; end else begin calib_data_offset_0 <= #TCQ rd_data_offset_ranks_0[6*chip_cnt_r+:6]; calib_data_offset_1 <= #TCQ rd_data_offset_ranks_1[6*chip_cnt_r+:6]; calib_data_offset_2 <= #TCQ rd_data_offset_ranks_2[6*chip_cnt_r+:6]; end end else begin // Non-Data Commands like NOP, MRS, ZQ Long Cal, Precharge, // Active, Refresh calib_cmd <= #TCQ 3'b100; calib_data_offset_0 <= #TCQ 6'd0; calib_data_offset_1 <= #TCQ 6'd0; calib_data_offset_2 <= #TCQ 6'd0; if (CWL_M % 2) calib_cas_slot <= #TCQ 2'b01; else calib_cas_slot <= #TCQ 2'b00; end end // Write Enable to PHY_Control FIFO always asserted // No danger of this FIFO being Full with 4:1 sync clock ratio // This is also the write enable to the command OUT_FIFO always @(posedge clk) begin if (rst) begin calib_ctl_wren <= #TCQ 1'b0; calib_cmd_wren <= #TCQ 1'b0; calib_seq <= #TCQ 2'b00; end else if (cnt_pwron_cke_done_r && phy_ctl_ready && ~(phy_ctl_full || phy_cmd_full )) begin calib_ctl_wren <= #TCQ 1'b1; calib_cmd_wren <= #TCQ 1'b1; calib_seq <= #TCQ calib_seq + 1; end else begin calib_ctl_wren <= #TCQ 1'b0; calib_cmd_wren <= #TCQ 1'b0; calib_seq <= #TCQ calib_seq; end end generate genvar rnk_i; for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk always @(posedge clk) begin if (rst) begin mr2_r[rnk_i] <= #TCQ 2'b00; mr1_r[rnk_i] <= #TCQ 3'b000; end else begin mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i]; mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i]; end end end endgenerate // ODT assignment based on slot config and slot present // For single slot systems slot_1_present input will be ignored // Assuming component interfaces to be single slot systems generate if (nSLOTS == 1) begin: gen_single_slot_odt always @(posedge clk) begin if (rst) begin tmp_mr2_r[1] <= #TCQ 2'b00; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; tmp_mr1_r[1] <= #TCQ 3'b000; tmp_mr1_r[2] <= #TCQ 3'b000; tmp_mr1_r[3] <= #TCQ 3'b000; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; phy_tmp_odt_r <= #TCQ 4'b0000; phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; end else begin case ({slot_0_present[0],slot_0_present[1], slot_0_present[2],slot_0_present[3]}) // Single slot configuration with quad rank // Assuming same behavior as single slot dual rank for now // DDR2 does not have quad rank parts 4'b1111: begin if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 RTT_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 RTT_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end phy_tmp_odt_r <= #TCQ 4'b0001; // Chip Select assignments phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) ) +: nCS_PER_RANK] <= #TCQ 'b0; end // Single slot configuration with single rank 4'b1000: begin phy_tmp_odt_r <= #TCQ 4'b0001; if ((REG_CTRL == "ON") && (nCS_PER_RANK > 1)) begin phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0; end else begin phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; end if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && ((cnt_init_mr_r == 2'd0) || (USE_ODT_PORT == 1)))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 RTT_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 RTT_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Single slot configuration with dual rank 4'b1100: begin phy_tmp_odt_r <= #TCQ 4'b0001; // Chip Select assignments phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) ) +: nCS_PER_RANK] <= #TCQ 'b0; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end default: begin phy_tmp_odt_r <= #TCQ 4'b0001; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end endcase end end end else if (nSLOTS == 2) begin: gen_dual_slot_odt always @ (posedge clk) begin if (rst) begin tmp_mr2_r[1] <= #TCQ 2'b00; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; tmp_mr1_r[1] <= #TCQ 3'b000; tmp_mr1_r[2] <= #TCQ 3'b000; tmp_mr1_r[3] <= #TCQ 3'b000; phy_tmp_odt_r <= #TCQ 4'b0000; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; end else begin case ({slot_0_present[0],slot_0_present[1], slot_1_present[0],slot_1_present[1]}) // Two slot configuration, one slot present, single rank 4'b10_00: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end 4'b00_10: begin //Rank1 ODT enabled if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank1 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank1 Rtt_NOM defaults to 120 ohms tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Two slot configuration, one slot present, dual rank 4'b00_11: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end 4'b11_00: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank1 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Two slot configuration, one rank per slot 4'b10_10: begin if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r == 2'b00)begin phy_tmp_odt_r <= #TCQ 4'b0010; //bit0 for rank0 end else begin phy_tmp_odt_r <= #TCQ 4'b0001; //bit0 for rank0 end end else begin if((init_state_r == INIT_WRLVL_WAIT) || (init_next_state == INIT_RDLVL_STG1_WRITE) || (init_next_state == INIT_WRCAL_WRITE) || (init_next_state == INIT_OCAL_CENTER_WRITE) || (init_next_state == INIT_OCLKDELAY_WRITE)) phy_tmp_odt_r <= #TCQ 4'b0011; // bit0 for rank0/1 (write) else if ((init_next_state == INIT_PI_PHASELOCK_READS) || (init_next_state == INIT_MPR_READ) || (init_next_state == INIT_RDLVL_STG1_READ) || (init_next_state == INIT_RDLVL_COMPLEX_READ) || (init_next_state == INIT_RDLVL_STG2_READ) || (init_next_state == INIT_OCLKDELAY_READ) || (init_next_state == INIT_WRCAL_READ) || (init_next_state == INIT_WRCAL_MULT_READS)) phy_tmp_odt_r <= #TCQ 4'b0010; // bit0 for rank1 (rank 0 rd) end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_WR == "60") ? 3'b001 : (RTT_WR == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; end end // Two Slots - One slot with dual rank and other with single rank 4'b10_11: begin //Rank3 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[1] <= #TCQ 3'b000; end //Slot1 Rank1 or Rank3 is being written if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r == 2'b00)begin phy_tmp_odt_r <= #TCQ 4'b0010; end else begin phy_tmp_odt_r <= #TCQ 4'b0001; end end else begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0011; //Slot0 Rank0 is being written end else begin phy_tmp_odt_r <= #TCQ 4'b0101; // ODT for ranks 0 and 2 aserted end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))begin if (chip_cnt_r == 2'b00) begin phy_tmp_odt_r <= #TCQ 4'b0100; end else begin phy_tmp_odt_r <= #TCQ 4'b0001; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end // Two Slots - One slot with dual rank and other with single rank 4'b11_10: begin //Rank2 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : (RTT_NOM2 == "120") ? 3'b010 : (RTT_NOM2 == "20") ? 3'b100 : (RTT_NOM2 == "30") ? 3'b101 : (RTT_NOM2 == "40") ? 3'b011: 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011: 3'b000; //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r[1] == 1'b1)begin phy_tmp_odt_r <= #TCQ 4'b0001; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; // rank 2 ODT asserted end end else begin if (// wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin if (chip_cnt_r[1] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0110; end else begin phy_tmp_odt_r <= #TCQ 4'b0101; end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS)) begin if (chip_cnt_r[1] == 1'b1) begin phy_tmp_odt_r[(1*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ 4'b0010; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end // Two Slots - two ranks per slot 4'b11_11: begin //Rank2 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : (RTT_NOM2 == "120") ? 3'b010 : (RTT_NOM2 == "20") ? 3'b100 : (RTT_NOM2 == "30") ? 3'b101 : (RTT_NOM2 == "40") ? 3'b011 : 3'b000; //Rank3 Rtt_NOM tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 : (RTT_NOM3 == "120") ? 3'b010 : (RTT_NOM3 == "20") ? 3'b100 : (RTT_NOM3 == "30") ? 3'b101 : (RTT_NOM3 == "40") ? 3'b011 : 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[1] <= #TCQ 3'b000; //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r[1] == 1'b1)begin phy_tmp_odt_r <= #TCQ 4'b0001; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; end end else begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin //Slot1 Rank1 or Rank3 is being written if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0110; //Slot0 Rank0 or Rank2 is being written end else begin phy_tmp_odt_r <= #TCQ 4'b1001; end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))begin //Slot1 Rank1 or Rank3 is being read if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0100; //Slot0 Rank0 or Rank2 is being read end else begin phy_tmp_odt_r <= #TCQ 4'b1000; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end default: begin phy_tmp_odt_r <= #TCQ 4'b1111; // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "60") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; end end endcase end end end endgenerate // PHY only supports two ranks. // calib_aux_out[0] is CKE for rank 0 and calib_aux_out[1] is ODT for rank 0 // calib_aux_out[2] is CKE for rank 1 and calib_aux_out[3] is ODT for rank 1 generate if(CKE_ODT_AUX == "FALSE") begin if ((nSLOTS == 1) && (RANKS < 2)) begin always @(posedge clk) if (rst) begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || wrlvl_rank_done || wrlvl_rank_done_r1 || (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt ) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || complex_odt_ext || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_OCAL_CENTER_WRITE) || complex_ocal_odt_ext || (init_state_r == INIT_OCLKDELAY_WRITE)|| (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin // Quad rank in a single slot calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end end end else if ((nSLOTS == 1) && (RANKS <= 2)) begin always @(posedge clk) if (rst) begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt)|| (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || complex_odt_ext || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_OCAL_CENTER_WRITE) || complex_ocal_odt_ext || (init_state_r == INIT_OCLKDELAY_WRITE)|| (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin // Dual rank in a single slot calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end end end else if ((nSLOTS == 2) && (RANKS == 2)) begin always @(posedge clk) if (rst)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if (((DRAM_TYPE == "DDR2") && (RTT_NOM == "DISABLED")) || ((DRAM_TYPE == "DDR3") && (RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // Quad rank in a single slot if (nCK_PER_CLK == 2) begin calib_odt[0] <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; calib_odt[1] <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end // Turn on for idle rank during read if dynamic ODT is enabled in DDR3 end else if(((DRAM_TYPE == "DDR3") && (RTT_WR != "OFF")) && ((init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_MPR_READ) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))) begin if (nCK_PER_CLK == 2) begin calib_odt[0] <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; calib_odt[1] <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end // disable well before next command and before disabling write leveling end else if(cnt_cmd_done_m7_r || (init_state_r == INIT_WRLVL_WAIT && ~wrlvl_odt)) calib_odt <= #TCQ 2'b00; end end end else begin//USE AUX OUTPUT for routing CKE and ODT. if ((nSLOTS == 1) && (RANKS < 2)) begin always @(posedge clk) if (rst) begin calib_aux_out <= #TCQ 4'b0000; end else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done || wrlvl_rank_done_r1 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Quad rank in a single slot calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end else if ((nSLOTS == 1) && (RANKS <= 2)) begin always @(posedge clk) if (rst) begin calib_aux_out <= #TCQ 4'b0000; end else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Dual rank in a single slot calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end else if ((nSLOTS == 2) && (RANKS == 2)) begin always @(posedge clk) if (rst) calib_aux_out <= #TCQ 4'b0000; else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Quad rank in a single slot if (nCK_PER_CLK == 2) begin calib_aux_out[1] <= #TCQ (!calib_aux_out[1]) ? phy_tmp_odt_r[0] : 1'b0; calib_aux_out[3] <= #TCQ (!calib_aux_out[3]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end end endgenerate //***************************************************************** // memory address during init //***************************************************************** always @(posedge clk) phy_data_full_r <= #TCQ phy_data_full; // verilint STARC-2.7.3.3b off always @(*)begin // Bus 0 for address/bank never used address_w = 'b0; bank_w = 'b0; if ((init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_DDR2_PRECHARGE)) begin // Set A10=1 for ZQ long calibration or Precharge All address_w = 'b0; address_w[10] = 1'b1; bank_w = 'b0; end else if (init_state_r == INIT_WRLVL_START) begin // Enable wrlvl in MR1 bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; address_w[7] = 1'b1; end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin // Finished with write leveling, disable wrlvl in MR1 // For single rank disable Rtt_Nom bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin // Set RTT_WR in MR2 after write leveling disabled bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; address_w[10:9] = mr2_r[chip_cnt_r]; end else if (init_state_r == INIT_MPR_READ) begin address_w = 'b0; bank_w = 'b0; end else if (init_state_r == INIT_MPR_RDEN) begin // Enable MPR read with LMR3 and A2=1 bank_w[BANK_WIDTH-1:0] = 'd3; address_w = {ROW_WIDTH{1'b0}}; address_w[2] = 1'b1; end else if (init_state_r == INIT_MPR_DISABLE) begin // Disable MPR read with LMR3 and A2=0 bank_w[BANK_WIDTH-1:0] = 'd3; address_w = {ROW_WIDTH{1'b0}}; end else if ((init_state_r == INIT_REG_WRITE)& (DRAM_TYPE == "DDR3"))begin // bank_w is assigned a 3 bit value. In some // DDR2 cases there will be only two bank bits. //Qualifying the condition with DDR3 bank_w = 'b0; address_w = 'b0; case (reg_ctrl_cnt_r) 4'h1:begin address_w[4:0] = REG_RC1[4:0]; bank_w = REG_RC1[7:5]; end 4'h2: address_w[4:0] = REG_RC2[4:0]; 4'h3: begin address_w[4:0] = REG_RC3[4:0]; bank_w = REG_RC3[7:5]; end 4'h4: begin address_w[4:0] = REG_RC4[4:0]; bank_w = REG_RC4[7:5]; end 4'h5: begin address_w[4:0] = REG_RC5[4:0]; bank_w = REG_RC5[7:5]; end 4'h6: begin address_w[4:0] = REG_RC10[4:0]; bank_w = REG_RC10[7:5]; end 4'h7: begin address_w[4:0] = REG_RC11[4:0]; bank_w = REG_RC11[7:5]; end default: address_w[4:0] = REG_RC0[4:0]; endcase end else if (init_state_r == INIT_LOAD_MR) begin // If loading mode register, look at cnt_init_mr to determine // which MR is currently being programmed address_w = 'b0; bank_w = 'b0; if(DRAM_TYPE == "DDR3")begin if(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done)begin // end of the calibration programming correct // burst length if (TEST_AL == "0") begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //Don't reset DLL end else begin // programming correct AL value bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; if (TEST_AL == "CL-1") address_w[4:3]= 2'b01; // AL="CL-1" else address_w[4:3]= 2'b10; // AL="CL-2" end end else begin case (cnt_init_mr_r) INIT_CNT_MR2: begin bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; address_w[10:9] = mr2_r[chip_cnt_r]; end INIT_CNT_MR3: begin bank_w[1:0] = 2'b11; address_w = load_mr3[ROW_WIDTH-1:0]; end INIT_CNT_MR1: begin bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; end INIT_CNT_MR0: begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; // fixing it to BL8 for calibration address_w[1:0] = 2'b00; end default: begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end endcase end end else begin // DDR2 case (cnt_init_mr_r) INIT_CNT_MR2: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //MRS command without resetting DLL end end INIT_CNT_MR3: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b11; address_w = load_mr3[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //MRS command without resetting DLL. Repeted again // because there is an extra state. end end INIT_CNT_MR1: begin bank_w[1:0] = 2'b01; if(~ddr2_refresh_flag_r)begin address_w = load_mr1[ROW_WIDTH-1:0]; end else begin // second set of lm commands address_w = load_mr1[ROW_WIDTH-1:0]; address_w[9:7] = 3'b111; //OCD default state end end INIT_CNT_MR0: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin // always disable odt for rank 1 and rank 3 as per SPEC address_w[2] = 'b0; address_w[6] = 'b0; end //OCD exit end end default: begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end endcase end end else if ( ~prbs_rdlvl_done && ((init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin // Writing and reading PRBS pattern for read leveling stage 1 // Need to support burst length 4 or 8. PRBS pattern will be // written to entire row and read back from the same row repeatedly bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (((stg1_wr_rd_cnt == NUM_STG1_WR_RD) && ~rdlvl_stg1_done) || (stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd22) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; end else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ) )// || // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; else address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end //need to add address for complex oclkdelay calib end else if (prbs_rdlvl_done && ((init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if ((stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd30) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; end else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (init_state_r1 != INIT_RDLVL_STG1_WRITE) ) // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; else address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end end else if ((init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_READ)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (oclk_wr_cnt == NUM_STG1_WR_RD) address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((oclk_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end else if ((init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_READ)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (wrcal_wr_cnt == NUM_STG1_WR_RD) address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((wrcal_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end else if ((init_state_r == INIT_WRCAL_MULT_READS) || (init_state_r == INIT_RDLVL_STG2_READ)) begin // when writing or reading back training pattern for read leveling stage2 // need to support burst length of 4 or 8. This may mean issuing // multiple commands to cover the entire range of addresses accessed // during read leveling. // Hard coding A[12] to 1 so that it will always be burst length of 8 // for DDR3. Does not have any effect on DDR2. bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; address_w[COL_WIDTH-1:0] = {CALIB_COL_ADD[COL_WIDTH-1:3],burst_addr_r, 3'b000}; address_w[12] = 1'b1; end else if ((init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_OCLKDELAY_ACT)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; //if (stg1_wr_rd_cnt == 'd22) // address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0] + 1; //else address_w = prbs_rdlvl_done ? CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt_ocal : CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt; end else begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end end // verilint STARC-2.7.3.3b on // registring before sending out generate genvar r,s; if ((DRAM_TYPE != "DDR3") || (CA_MIRROR != "ON")) begin: gen_no_mirror for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: div_clk_loop always @(posedge clk) begin phy_address[(r*ROW_WIDTH) +: ROW_WIDTH] <= #TCQ address_w; phy_bank[(r*BANK_WIDTH) +: BANK_WIDTH] <= #TCQ bank_w; end end end else begin: gen_mirror // Control/addressing mirroring (optional for DDR3 dual rank DIMMs) // Mirror for the 2nd rank only. Logic needs to be enhanced to account // for multiple slots, currently only supports one slot, 2-rank config for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_ba_div_clk_loop for (s = 0; s < BANK_WIDTH; s = s + 1) begin: gen_ba always @(posedge clk) if (chip_cnt_r == 2'b00) begin phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[s]; end else begin phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[(s == 0) ? 1 : ((s == 1) ? 0 : s)]; end end end for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_addr_div_clk_loop for (s = 0; s < ROW_WIDTH; s = s + 1) begin: gen_addr always @(posedge clk) if (chip_cnt_r == 2'b00) begin phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[s]; end else begin phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[ (s == 3) ? 4 : ((s == 4) ? 3 : ((s == 5) ? 6 : ((s == 6) ? 5 : ((s == 7) ? 8 : ((s == 8) ? 7 : s)))))]; end end end end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_init.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Memory initialization and overall master state control during // initialization and calibration. Specifically, the following functions // are performed: // 1. Memory initialization (initial AR, mode register programming, etc.) // 2. Initiating write leveling // 3. Generate training pattern writes for read leveling. Generate // memory readback for read leveling. // This module has an interface for providing control/address and write // data to the PHY Control Block during initialization/calibration. // Once initialization and calibration are complete, control is passed to the MC. // //Reference: //Revision History: // //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_init.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ **$Date: 2011/06/02 08:35:09 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_init.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_init # ( parameter tCK = 1500, // DDRx SDRAM clock period parameter TCQ = 100, parameter nCK_PER_CLK = 4, // # of memory clocks per CLK parameter CLK_PERIOD = 3000, // Logic (internal) clk period (in ps) parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA // 1 - ODT output from FPGA parameter DDR3_VDD_OP_VOLT = "150", // Voltage mode used for DDR3 // 150 - 1.50 V // 135 - 1.35 V // 125 - 1.25 V parameter VREF = "EXTERNAL", // Internal or external Vref parameter PRBS_WIDTH = 8, // PRBS sequence = 2^PRBS_WIDTH parameter BANK_WIDTH = 2, parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank parameter COL_WIDTH = 10, parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for // component I/F with CS_WIDTH=1, // nCS_PER_RANK=# of components parameter DQ_WIDTH = 64, parameter DQS_WIDTH = 8, parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter ROW_WIDTH = 14, parameter CS_WIDTH = 1, parameter RANKS = 1, // # of memory ranks in the interface parameter CKE_WIDTH = 1, // # of cke outputs parameter DRAM_TYPE = "DDR3", parameter REG_CTRL = "ON", parameter ADDR_CMD_MODE= "1T", // calibration Address parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address parameter CALIB_COL_ADD = 12'h000, // Calibration column address parameter CALIB_BA_ADD = 3'h0, // Calibration bank address // DRAM mode settings parameter AL = "0", // Additive Latency option parameter BURST_MODE = "8", // Burst length parameter BURST_TYPE = "SEQ", // Burst type // parameter nAL = 0, // Additive latency (in clk cyc) parameter nCL = 5, // Read CAS latency (in clk cyc) parameter nCWL = 5, // Write CAS latency (in clk cyc) parameter tRFC = 110000, // Refresh-to-command delay (in ps) parameter REFRESH_TIMER = 1553, // Refresh interval in fabrci cycles between 8 posted refreshes parameter REFRESH_TIMER_WIDTH = 8, parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option parameter RTT_NOM = "60", // Nominal ODT termination value parameter RTT_WR = "60", // Write ODT termination value parameter WRLVL = "ON", // Enable write leveling // parameter PHASE_DETECT = "ON", // Enable read phase detector parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter nSLOTS = 1, // Number of DIMM SLOTs in the system parameter SIM_INIT_OPTION = "NONE", // "NONE", "SKIP_PU_DLY", "SKIP_INIT" parameter SIM_CAL_OPTION = "NONE", // "NONE", "FAST_CAL", "SKIP_CAL" parameter CKE_ODT_AUX = "FALSE", parameter PRE_REV3ES = "OFF", // Enable TG error detection during calibration parameter TEST_AL = "0", // Internal use for ICM verification parameter FIXED_VICTIM = "TRUE", parameter BYPASS_COMPLEX_OCAL = "FALSE" ) ( input clk, input rst, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o, input delay_incdec_done, input ck_addr_cmd_delay_done, input pi_phase_locked_all, input pi_dqs_found_done, input dqsfound_retry, input dqs_found_prech_req, output reg pi_phaselock_start, output pi_phase_locked_err, output pi_calib_done, input phy_if_empty, // Read/write calibration interface input wrlvl_done, input wrlvl_rank_done, input wrlvl_byte_done, input wrlvl_byte_redo, input wrlvl_final, output reg wrlvl_final_if_rst, input oclkdelay_calib_done, input oclk_prech_req, input oclk_calib_resume, input lim_done, input lim_wr_req, output reg oclkdelay_calib_start, //complex oclkdelay calibration input complex_oclkdelay_calib_done, input complex_oclk_prech_req, input complex_oclk_calib_resume, output reg complex_oclkdelay_calib_start, input [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt, // same as oclkdelay_calib_cnt output reg complex_ocal_num_samples_inc, input complex_ocal_num_samples_done_r, input [2:0] complex_ocal_rd_victim_sel, output reg complex_ocal_reset_rd_addr, input complex_ocal_ref_req, output reg complex_ocal_ref_done, input done_dqs_tap_inc, input [5:0] rd_data_offset_0, input [5:0] rd_data_offset_1, input [5:0] rd_data_offset_2, input [6*RANKS-1:0] rd_data_offset_ranks_0, input [6*RANKS-1:0] rd_data_offset_ranks_1, input [6*RANKS-1:0] rd_data_offset_ranks_2, input pi_dqs_found_rank_done, input wrcal_done, input wrcal_prech_req, input wrcal_read_req, input wrcal_act_req, input temp_wrcal_done, input [7:0] slot_0_present, input [7:0] slot_1_present, output reg wl_sm_start, output reg wr_lvl_start, output reg wrcal_start, output reg wrcal_rd_wait, output reg wrcal_sanity_chk, output reg tg_timer_done, output reg no_rst_tg_mc, input rdlvl_stg1_done, input rdlvl_stg1_rank_done, output reg rdlvl_stg1_start, output reg pi_dqs_found_start, output reg detect_pi_found_dqs, // rdlvl stage 1 precharge requested after each DQS input rdlvl_prech_req, input rdlvl_last_byte_done, input wrcal_resume, input wrcal_sanity_chk_done, // MPR read leveling input mpr_rdlvl_done, input mpr_rnk_done, input mpr_last_byte_done, output reg mpr_rdlvl_start, output reg mpr_end_if_reset, // PRBS Read Leveling input prbs_rdlvl_done, input prbs_last_byte_done, input prbs_rdlvl_prech_req, input complex_victim_inc, input [2:0] rd_victim_sel, input [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt, output reg [2:0] victim_sel, output reg [DQS_CNT_WIDTH:0]victim_byte_cnt, output reg prbs_rdlvl_start, output reg prbs_gen_clk_en, output reg prbs_gen_oclk_clk_en, output reg complex_sample_cnt_inc, output reg complex_sample_cnt_inc_ocal, output reg complex_wr_done, // Signals shared btw multiple calibration stages output reg prech_done, // Data select / status output reg init_calib_complete, // Signal to mask memory model error for Invalid latching edge output reg calib_writes, // PHY address/control // 2 commands to PHY Control Block per div 2 clock in 2:1 mode // 4 commands to PHY Control Block per div 4 clock in 4:1 mode output reg [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address, output reg [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank, output reg [nCK_PER_CLK-1:0] phy_ras_n, output reg [nCK_PER_CLK-1:0] phy_cas_n, output reg [nCK_PER_CLK-1:0] phy_we_n, output reg phy_reset_n, output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n, // Hard PHY Interface signals input phy_ctl_ready, input phy_ctl_full, input phy_cmd_full, input phy_data_full, output reg calib_ctl_wren, output reg calib_cmd_wren, output reg [1:0] calib_seq, output reg write_calib, output reg read_calib, // PHY_Ctl_Wd output reg [2:0] calib_cmd, // calib_aux_out used for CKE and ODT output reg [3:0] calib_aux_out, output reg [1:0] calib_odt , output reg [nCK_PER_CLK-1:0] calib_cke , output [1:0] calib_rank_cnt, output reg [1:0] calib_cas_slot, output reg [5:0] calib_data_offset_0, output reg [5:0] calib_data_offset_1, output reg [5:0] calib_data_offset_2, // PHY OUT_FIFO output reg calib_wrdata_en, output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata, // PHY Read output phy_rddata_en, output phy_rddata_valid, output [255:0] dbg_phy_init, input read_pause, input reset_rd_addr, //OCAL centering calibration input oclkdelay_center_calib_start, input oclk_center_write_resume, input oclkdelay_center_calib_done ); //***************************************************************************** // Assertions to be added //***************************************************************************** // The phy_ctl_full signal must never be asserted in synchronous mode of // operation either 4:1 or 2:1 // // The RANKS parameter must never be set to '0' by the user // valid values: 1 to 4 // //***************************************************************************** //*************************************************************************** // Number of Read level stage 1 writes limited to a SDRAM row // The address of Read Level stage 1 reads must also be limited // to a single SDRAM row // (2^COL_WIDTH)/BURST_MODE = (2^10)/8 = 128 localparam NUM_STG1_WR_RD = (BURST_MODE == "8") ? 4 : (BURST_MODE == "4") ? 8 : 4; localparam ADDR_INC = (BURST_MODE == "8") ? 8 : (BURST_MODE == "4") ? 4 : 8; // In a 2 slot dual rank per system RTT_NOM values // for Rank2 and Rank3 default to 40 ohms localparam RTT_NOM2 = "40"; localparam RTT_NOM3 = "40"; localparam RTT_NOM_int = (USE_ODT_PORT == 1) ? RTT_NOM : RTT_WR; // Specifically for use with half-frequency controller (nCK_PER_CLK=2) // = 1 if burst length = 4, = 0 if burst length = 8. Determines how // often row command needs to be issued during read-leveling // For DDR3 the burst length is fixed during calibration localparam BURST4_FLAG = (DRAM_TYPE == "DDR3")? 1'b0 : (BURST_MODE == "8") ? 1'b0 : ((BURST_MODE == "4") ? 1'b1 : 1'b0); //*************************************************************************** // Counter values used to determine bus timing // NOTE on all counter terminal counts - these can/should be one less than // the actual delay to take into account extra clock cycle delay in // generating the corresponding "done" signal //*************************************************************************** localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK; // Calculate initial delay required in number of CLK clock cycles // to delay initially. The counter is clocked by [CLK/1024] - which // is approximately division by 1000 - note that the formulas below will // result in more than the minimum wait time because of this approximation. // NOTE: For DDR3 JEDEC specifies to delay reset // by 200us, and CKE by an additional 500us after power-up // For DDR2 CKE is delayed by 200us after power up. localparam DDR3_RESET_DELAY_NS = 200000; localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS; localparam DDR2_CKE_DELAY_NS = 200000; localparam PWRON_RESET_DELAY_CNT = ((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD); localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == "DDR3") ? (((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) : (((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)); // FOR DDR2 -1 taken out. With -1 not getting 200us. The equation // needs to be reworked. localparam DDR2_INIT_PRE_DELAY_PS = 400000; localparam DDR2_INIT_PRE_CNT = ((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1; // Calculate tXPR time: reset from CKE HIGH to valid command after power-up // tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock // cycles because this counter actually starts up before CKE is asserted // to memory. localparam TXPR_DELAY_CNT = (5*CLK_MEM_PERIOD > tRFC+10000) ? (((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+11 : (((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+11; // tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV localparam TDLLK_TZQINIT_DELAY_CNT = 255; // TWR values in ns. Both DDR2 and DDR3 have the same value. // 15000ns/tCK localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ? (15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD; // time to wait between consecutive commands in PHY_INIT - this is a // generic number, and must be large enough to account for worst case // timing parameter (tRFC - refresh-to-active) across all memory speed // grades and operating frequencies. Expressed in clk // (Divided by 4 or Divided by 2) clock cycles. localparam CNTNEXT_CMD = 7'b1111111; // Counter values to keep track of which MR register to load during init // Set value of INIT_CNT_MR_DONE to equal value of counter for last mode // register configured during initialization. // NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init localparam INIT_CNT_MR2 = 2'b00; localparam INIT_CNT_MR3 = 2'b01; localparam INIT_CNT_MR1 = 2'b10; localparam INIT_CNT_MR0 = 2'b11; localparam INIT_CNT_MR_DONE = 2'b11; // Register chip programmable values for DDR3 // The register chip for the registered DIMM needs to be programmed // before the initialization of the registered DIMM. // Address for the control word is in : DBA2, DA2, DA1, DA0 // Data for the control word is in: DBA1 DBA0, DA4, DA3 // The values will be stored in the local param in the following format // {DBA[2:0], DA[4:0]} // RC0 is global features control word. Address == 000 localparam REG_RC0 = 8'b00000000; // RC1 Clock driver enable control word. Enables or disables the four // output clocks in the register chip. For single rank and dual rank // two clocks will be enabled and for quad rank all the four clocks // will be enabled. Address == 000. Data = 0110 for single and dual rank. // = 0000 for quad rank localparam REG_RC1 = 8'b00000001; // RC2 timing control word. Set in 1T timing mode // Address = 010. Data = 0000 localparam REG_RC2 = 8'b00000010; // RC3 timing control word. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC3 = (RANKS >= 2) ? 8'b00101011 : 8'b00000011; // RC4 timing control work. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC4 = (RANKS >= 2) ? 8'b00101100 : 8'b00000100; // RC5 timing control work. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC5 = (RANKS >= 2) ? 8'b00101101 : 8'b00000101; // RC10 timing control work. Setting the data to 0000 localparam [3:0] FREQUENCY_ENCODING = (tCK >= 1072 && tCK < 1250) ? 4'b0100 : (tCK >= 1250 && tCK < 1500) ? 4'b0011 : (tCK >= 1500 && tCK < 1875) ? 4'b0010 : (tCK >= 1875 && tCK < 2500) ? 4'b0001 : 4'b0000; localparam REG_RC10 = {1'b1,FREQUENCY_ENCODING,3'b010}; localparam VREF_ENCODING = (VREF == "INTERNAL") ? 1'b1 : 1'b0; localparam [3:0] DDR3_VOLTAGE_ENCODING = (DDR3_VDD_OP_VOLT == "125") ? {1'b0,VREF_ENCODING,2'b10} : (DDR3_VDD_OP_VOLT == "135") ? {1'b0,VREF_ENCODING,2'b01} : {1'b0,VREF_ENCODING,2'b00} ; localparam REG_RC11 = {1'b1,DDR3_VOLTAGE_ENCODING,3'b011}; // For non-zero AL values localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; // Adding the register dimm latency to write latency localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; // Count value to generate pi_phase_locked_err signal localparam PHASELOCKED_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 16383 : 1000; // Timeout interval for detecting error with Traffic Generator localparam [13:0] TG_TIMER_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 14'h3FFF : 14'h0001; //bit num per DQS localparam DQ_PER_DQS = DQ_WIDTH/DQS_WIDTH; //COMPLEX_ROW_CNT_BYTE localparam COMPLEX_ROW_CNT_BYTE = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS*2: 2; localparam COMPLEX_RD = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS : 1; // Master state machine encoding localparam INIT_IDLE = 7'b0000000; //0 localparam INIT_WAIT_CKE_EXIT = 7'b0000001; //1 localparam INIT_LOAD_MR = 7'b0000010; //2 localparam INIT_LOAD_MR_WAIT = 7'b0000011; //3 localparam INIT_ZQCL = 7'b0000100; //4 localparam INIT_WAIT_DLLK_ZQINIT = 7'b0000101; //5 localparam INIT_WRLVL_START = 7'b0000110; //6 localparam INIT_WRLVL_WAIT = 7'b0000111; //7 localparam INIT_WRLVL_LOAD_MR = 7'b0001000; //8 localparam INIT_WRLVL_LOAD_MR_WAIT = 7'b0001001; //9 localparam INIT_WRLVL_LOAD_MR2 = 7'b0001010; //A localparam INIT_WRLVL_LOAD_MR2_WAIT = 7'b0001011; //B localparam INIT_RDLVL_ACT = 7'b0001100; //C localparam INIT_RDLVL_ACT_WAIT = 7'b0001101; //D localparam INIT_RDLVL_STG1_WRITE = 7'b0001110; //E localparam INIT_RDLVL_STG1_WRITE_READ = 7'b0001111; //F localparam INIT_RDLVL_STG1_READ = 7'b0010000; //10 localparam INIT_RDLVL_STG2_READ = 7'b0010001; //11 localparam INIT_RDLVL_STG2_READ_WAIT = 7'b0010010; //12 localparam INIT_PRECHARGE_PREWAIT = 7'b0010011; //13 localparam INIT_PRECHARGE = 7'b0010100; //14 localparam INIT_PRECHARGE_WAIT = 7'b0010101; //15 localparam INIT_DONE = 7'b0010110; //16 localparam INIT_DDR2_PRECHARGE = 7'b0010111; //17 localparam INIT_DDR2_PRECHARGE_WAIT = 7'b0011000; //18 localparam INIT_REFRESH = 7'b0011001; //19 localparam INIT_REFRESH_WAIT = 7'b0011010; //1A localparam INIT_REG_WRITE = 7'b0011011; //1B localparam INIT_REG_WRITE_WAIT = 7'b0011100; //1C localparam INIT_DDR2_MULTI_RANK = 7'b0011101; //1D localparam INIT_DDR2_MULTI_RANK_WAIT = 7'b0011110; //1E localparam INIT_WRCAL_ACT = 7'b0011111; //1F localparam INIT_WRCAL_ACT_WAIT = 7'b0100000; //20 localparam INIT_WRCAL_WRITE = 7'b0100001; //21 localparam INIT_WRCAL_WRITE_READ = 7'b0100010; //22 localparam INIT_WRCAL_READ = 7'b0100011; //23 localparam INIT_WRCAL_READ_WAIT = 7'b0100100; //24 localparam INIT_WRCAL_MULT_READS = 7'b0100101; //25 localparam INIT_PI_PHASELOCK_READS = 7'b0100110; //26 localparam INIT_MPR_RDEN = 7'b0100111; //27 localparam INIT_MPR_WAIT = 7'b0101000; //28 localparam INIT_MPR_READ = 7'b0101001; //29 localparam INIT_MPR_DISABLE_PREWAIT = 7'b0101010; //2A localparam INIT_MPR_DISABLE = 7'b0101011; //2B localparam INIT_MPR_DISABLE_WAIT = 7'b0101100; //2C localparam INIT_OCLKDELAY_ACT = 7'b0101101; //2D localparam INIT_OCLKDELAY_ACT_WAIT = 7'b0101110; //2E localparam INIT_OCLKDELAY_WRITE = 7'b0101111; //2F localparam INIT_OCLKDELAY_WRITE_WAIT = 7'b0110000; //30 localparam INIT_OCLKDELAY_READ = 7'b0110001; //31 localparam INIT_OCLKDELAY_READ_WAIT = 7'b0110010; //32 localparam INIT_REFRESH_RNK2_WAIT = 7'b0110011; //33 localparam INIT_RDLVL_COMPLEX_PRECHARGE = 7'b0110100; //34 localparam INIT_RDLVL_COMPLEX_PRECHARGE_WAIT = 7'b0110101; //35 localparam INIT_RDLVL_COMPLEX_ACT = 7'b0110110; //36 localparam INIT_RDLVL_COMPLEX_ACT_WAIT = 7'b0110111; //37 localparam INIT_RDLVL_COMPLEX_READ = 7'b0111000; //38 localparam INIT_RDLVL_COMPLEX_READ_WAIT = 7'b0111001; //39 localparam INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT = 7'b0111010; //3A localparam INIT_OCAL_COMPLEX_ACT = 7'b0111011; //3B localparam INIT_OCAL_COMPLEX_ACT_WAIT = 7'b0111100; //3C localparam INIT_OCAL_COMPLEX_WRITE_WAIT = 7'b0111101; //3D localparam INIT_OCAL_COMPLEX_RESUME_WAIT = 7'b0111110; //3E localparam INIT_OCAL_CENTER_ACT = 7'b0111111; //3F localparam INIT_OCAL_CENTER_WRITE = 7'b1000000; //40 localparam INIT_OCAL_CENTER_WRITE_WAIT = 7'b1000001; //41 localparam INIT_OCAL_CENTER_ACT_WAIT = 7'b1000010; //42 integer i, j, k, l, m, n, p, q; reg pi_dqs_found_all_r; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r1; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r2; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r3; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r4; reg pi_calib_rank_done_r; reg [13:0] pi_phaselock_timer; reg stg1_wr_done; reg rnk_ref_cnt; reg pi_dqs_found_done_r1; reg pi_dqs_found_rank_done_r; reg read_calib_int; reg read_calib_r; reg pi_calib_done_r; reg pi_calib_done_r1; reg burst_addr_r; reg [1:0] chip_cnt_r; reg [6:0] cnt_cmd_r; reg cnt_cmd_done_r; reg cnt_cmd_done_m7_r; reg [7:0] cnt_dllk_zqinit_r; reg cnt_dllk_zqinit_done_r; reg cnt_init_af_done_r; reg [1:0] cnt_init_af_r; reg [1:0] cnt_init_data_r; reg [1:0] cnt_init_mr_r; reg cnt_init_mr_done_r; reg cnt_init_pre_wait_done_r; reg [7:0] cnt_init_pre_wait_r; reg [9:0] cnt_pwron_ce_r; reg cnt_pwron_cke_done_r; reg cnt_pwron_cke_done_r1; reg [8:0] cnt_pwron_r; reg cnt_pwron_reset_done_r; reg cnt_txpr_done_r; reg [7:0] cnt_txpr_r; reg ddr2_pre_flag_r; reg ddr2_refresh_flag_r; reg ddr3_lm_done_r; reg [4:0] enable_wrlvl_cnt; reg init_complete_r; reg init_complete_r1; reg init_complete_r2; (* keep = "true" *) reg init_complete_r_timing; (* keep = "true" *) reg init_complete_r1_timing; reg [6:0] init_next_state; reg [6:0] init_state_r; reg [6:0] init_state_r1; wire [15:0] load_mr0; wire [15:0] load_mr1; wire [15:0] load_mr2; wire [15:0] load_mr3; reg mem_init_done_r; reg [1:0] mr2_r [0:3]; reg [2:0] mr1_r [0:3]; reg new_burst_r; reg [15:0] wrcal_start_dly_r; wire wrcal_start_pre; reg wrcal_resume_r; // Only one ODT signal per rank in PHY Control Block reg [nCK_PER_CLK-1:0] phy_tmp_odt_r; reg [nCK_PER_CLK-1:0] phy_tmp_odt_r1; reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r; reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_int_cs_n; wire prech_done_pre; reg [15:0] prech_done_dly_r; reg prech_pending_r; reg prech_req_posedge_r; reg prech_req_r; reg pwron_ce_r; reg first_rdlvl_pat_r; reg first_wrcal_pat_r; reg phy_wrdata_en; reg phy_wrdata_en_r1; reg [1:0] wrdata_pat_cnt; reg [1:0] wrcal_pat_cnt; reg [ROW_WIDTH-1:0] address_w; reg [BANK_WIDTH-1:0] bank_w; reg rdlvl_stg1_done_r1; reg rdlvl_stg1_start_int; reg [15:0] rdlvl_start_dly0_r; reg rdlvl_start_pre; reg rdlvl_last_byte_done_r; wire rdlvl_rd; wire rdlvl_wr; reg rdlvl_wr_r; wire rdlvl_wr_rd; reg [3:0] reg_ctrl_cnt_r; reg [1:0] tmp_mr2_r [0:3]; reg [2:0] tmp_mr1_r [0:3]; reg wrlvl_done_r; reg wrlvl_done_r1; reg wrlvl_rank_done_r1; reg wrlvl_rank_done_r2; reg wrlvl_rank_done_r3; reg wrlvl_rank_done_r4; reg wrlvl_rank_done_r5; reg wrlvl_rank_done_r6; reg wrlvl_rank_done_r7; reg [2:0] wrlvl_rank_cntr; reg wrlvl_odt_ctl; reg wrlvl_odt; reg wrlvl_active; reg wrlvl_active_r1; reg [2:0] num_reads; reg temp_wrcal_done_r; reg temp_lmr_done; reg extend_cal_pat; reg [13:0] tg_timer; reg tg_timer_go; reg cnt_wrcal_rd; reg [3:0] cnt_wait; reg [7:0] wrcal_reads; reg [8:0] stg1_wr_rd_cnt; reg phy_data_full_r; reg wr_level_dqs_asrt; reg wr_level_dqs_asrt_r1; reg [1:0] dqs_asrt_cnt; reg [3:0] num_refresh; wire oclkdelay_calib_start_pre; reg [15:0] oclkdelay_start_dly_r; reg [3:0] oclk_wr_cnt; reg [3:0] wrcal_wr_cnt; reg wrlvl_final_r; reg prbs_rdlvl_done_r1; reg prbs_rdlvl_done_r2; reg prbs_rdlvl_done_r3; reg prbs_last_byte_done_r; reg phy_if_empty_r; reg prbs_pat_resume_int; reg complex_row0_wr_done; reg complex_row1_wr_done; reg complex_row0_rd_done; reg complex_row1_rd_done; reg complex_row0_rd_done_r1; reg [3:0] complex_wait_cnt; reg [3:0] complex_num_reads; reg [3:0] complex_num_reads_dec; reg [ROW_WIDTH-1:0] complex_address; reg wr_victim_inc; reg [2:0] wr_victim_sel; reg [DQS_CNT_WIDTH:0] wr_byte_cnt; reg [7:0] complex_row_cnt; reg complex_sample_cnt_inc_r1; reg complex_sample_cnt_inc_r2; reg complex_odt_ext; reg complex_ocal_odt_ext; reg wrcal_final_chk; wire prech_req; reg read_pause_r1; reg read_pause_r2; wire read_pause_ext; reg reset_rd_addr_r1; reg complex_rdlvl_int_ref_req; reg ext_int_ref_req; //complex OCLK delay calibration reg [7:0] complex_row_cnt_ocal; reg [4:0] complex_num_writes; reg [4:0] complex_num_writes_dec; reg complex_oclkdelay_calib_start_int; reg complex_oclkdelay_calib_start_r1; reg complex_oclkdelay_calib_start_r2; reg complex_oclkdelay_calib_done_r1; // reg [DQS_CNT_WIDTH:0] wr_byte_cnt_ocal; reg [2:0] wr_victim_sel_ocal; reg complex_row1_rd_done_r1; //time for switch to write reg [2:0] complex_row1_rd_cnt; //row1 read number for the byte (8 (16 rows) row1) reg complex_byte_rd_done; //read for the byte is done reg complex_byte_rd_done_r1; // reg complex_row_change; //every 16 rows of read, it is set to "0" for write reg ocal_num_samples_inc; //1 read/write is done reg complex_ocal_wr_start; //indicate complex ocal write is started. used for prbs rd addr gen reg prbs_rdlvl_done_pulse; //rising edge for prbs_rdlvl_done. used for pipelining reg prech_done_r1, prech_done_r2, prech_done_r3; reg mask_lim_done; reg complex_mask_lim_done; reg oclkdelay_calib_start_int; reg [REFRESH_TIMER_WIDTH-1:0] oclkdelay_ref_cnt; reg oclkdelay_int_ref_req; reg [3:0] ocal_act_wait_cnt; reg oclk_calib_resume_level; reg ocal_last_byte_done; wire mmcm_wr; //MMCM centering write. no CS will be set wire exit_ocal_complex_resume_wait = init_state_r == INIT_OCAL_COMPLEX_RESUME_WAIT && complex_oclk_calib_resume; //*************************************************************************** // Debug //*************************************************************************** //synthesis translate_off always @(posedge mem_init_done_r) begin if (!rst) $display ("PHY_INIT: Memory Initialization completed at %t", $time); end always @(posedge wrlvl_done) begin if (!rst && (WRLVL == "ON")) $display ("PHY_INIT: Write Leveling completed at %t", $time); end always @(posedge rdlvl_stg1_done) begin if (!rst) $display ("PHY_INIT: Read Leveling Stage 1 completed at %t", $time); end always @(posedge mpr_rdlvl_done) begin if (!rst) $display ("PHY_INIT: MPR Read Leveling completed at %t", $time); end always @(posedge oclkdelay_calib_done) begin if (!rst) $display ("PHY_INIT: OCLKDELAY calibration completed at %t", $time); end always @(posedge pi_calib_done_r1) begin if (!rst) $display ("PHY_INIT: Phaser_In Phase Locked at %t", $time); end always @(posedge pi_dqs_found_done) begin if (!rst) $display ("PHY_INIT: Phaser_In DQSFOUND completed at %t", $time); end always @(posedge wrcal_done) begin if (!rst && (WRLVL == "ON")) $display ("PHY_INIT: Write Calibration completed at %t", $time); end always@(posedge prbs_rdlvl_done)begin if(!rst) $display("PHY_INIT : PRBS/PER_BIT calibration completed at %t",$time); end always@(posedge complex_oclkdelay_calib_done)begin if(!rst) $display("PHY_INIT : COMPLEX OCLKDELAY calibration completed at %t",$time); end always@(posedge oclkdelay_center_calib_done)begin if(!rst) $display("PHY_INIT : OCLKDELAY CENTER CALIB calibration completed at %t",$time); end //synthesis translate_on assign dbg_phy_init[5:0] = init_state_r; assign dbg_phy_init[6+:8] = complex_row_cnt; assign dbg_phy_init[14+:3] = victim_sel; assign dbg_phy_init[17+:4] = victim_byte_cnt; assign dbg_phy_init[21+:9] = stg1_wr_rd_cnt[8:0]; assign dbg_phy_init[30+:15] = complex_address; assign dbg_phy_init[(30+15)+:15] = phy_address[14:0]; assign dbg_phy_init[60] =prbs_rdlvl_prech_req ; assign dbg_phy_init[61] =prech_req_posedge_r ; //*************************************************************************** // DQS count to be sent to hard PHY during Phaser_IN Phase Locking stage //*************************************************************************** // assign pi_phaselock_calib_cnt = dqs_cnt_r; assign pi_calib_done = pi_calib_done_r1; assign read_pause_ext = read_pause | read_pause_r2; //detect rising edge of prbs_rdlvl_done to reset all control sighals always @ (posedge clk) begin prbs_rdlvl_done_pulse <= #TCQ prbs_rdlvl_done & ~prbs_rdlvl_done_r1; end always @ (posedge clk) begin read_pause_r1 <= #TCQ read_pause; read_pause_r2 <= #TCQ read_pause_r1; end always @(posedge clk) begin if (rst) wrcal_final_chk <= #TCQ 1'b0; else if ((init_next_state == INIT_WRCAL_ACT) && wrcal_done && (DRAM_TYPE == "DDR3")) wrcal_final_chk <= #TCQ 1'b1; end always @(posedge clk) begin rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done; prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done; prbs_rdlvl_done_r2 <= #TCQ prbs_rdlvl_done_r1; prbs_rdlvl_done_r3 <= #TCQ prbs_rdlvl_done_r2; wrcal_resume_r <= #TCQ wrcal_resume; wrcal_sanity_chk <= #TCQ wrcal_final_chk; end always @(posedge clk) begin if (rst) mpr_end_if_reset <= #TCQ 1'b0; else if (mpr_last_byte_done && (num_refresh != 'd0)) mpr_end_if_reset <= #TCQ 1'b1; else mpr_end_if_reset <= #TCQ 1'b0; end // Siganl to mask memory model error for Invalid latching edge always @(posedge clk) if (rst) calib_writes <= #TCQ 1'b0; else if ((init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ)) calib_writes <= #TCQ 1'b1; else calib_writes <= #TCQ 1'b0; always @(posedge clk) if (rst) wrcal_rd_wait <= #TCQ 1'b0; else if (init_state_r == INIT_WRCAL_READ_WAIT) wrcal_rd_wait <= #TCQ 1'b1; else wrcal_rd_wait <= #TCQ 1'b0; //*************************************************************************** // Signal PHY completion when calibration is finished // Signal assertion is delayed by four clock cycles to account for the // multi cycle path constraint to (phy_init_data_sel) signal. //*************************************************************************** always @(posedge clk) if (rst) begin init_complete_r <= #TCQ 1'b0; init_complete_r_timing <= #TCQ 1'b0; init_complete_r1 <= #TCQ 1'b0; init_complete_r1_timing <= #TCQ 1'b0; init_complete_r2 <= #TCQ 1'b0; init_calib_complete <= #TCQ 1'b0; end else begin if (init_state_r == INIT_DONE) begin init_complete_r <= #TCQ 1'b1; init_complete_r_timing <= #TCQ 1'b1; end init_complete_r1 <= #TCQ init_complete_r; init_complete_r1_timing <= #TCQ init_complete_r_timing; init_complete_r2 <= #TCQ init_complete_r1; init_calib_complete <= #TCQ init_complete_r2; end always @ (posedge clk) if (rst) complex_oclkdelay_calib_done_r1 <= #TCQ 1'b0; else complex_oclkdelay_calib_done_r1 <= #TCQ complex_oclkdelay_calib_done; //reset read address for starting complex ocaldealy calib always @ (posedge clk) begin complex_ocal_reset_rd_addr <= #TCQ ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd9)) || (prbs_last_byte_done && ~prbs_last_byte_done_r); end //first write for complex oclkdealy calib always @ (posedge clk) begin if (rst) complex_ocal_wr_start <= #TCQ 'b0; else complex_ocal_wr_start <= #TCQ complex_ocal_reset_rd_addr? 1'b1 : complex_ocal_wr_start; end //ocal stg3 centering start // always @ (posedge clk) // if(rst) oclkdelay_center_calib_start <= #TCQ 1'b0; // else // oclkdelay_center_calib_start <= #TCQ ((init_state_r == INIT_OCAL_CENTER_ACT) && lim_done)? 1'b1: oclkdelay_center_calib_start; //*************************************************************************** // Instantiate FF for the phy_init_data_sel signal. A multi cycle path // constraint will be assigned to this signal. This signal will only be // used within the PHY //*************************************************************************** // FDRSE u_ff_phy_init_data_sel // ( // .Q (phy_init_data_sel), // .C (clk), // .CE (1'b1), // .D (init_complete_r), // .R (1'b0), // .S (1'b0) // ) /* synthesis syn_preserve=1 */ // /* synthesis syn_replicate = 0 */; //*************************************************************************** // Mode register programming //*************************************************************************** //***************************************************************** // DDR3 Load mode reg0 // Mode Register (MR0): // [15:13] - unused - 000 // [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit), // 1 (DLL maintained) // [11:9] - write recovery for Auto Precharge (tWR/tCK = 6) // [8] - DLL reset - 0 or 1 // [7] - Test Mode - 0 (normal) // [6:4],[2] - CAS latency - CAS_LAT // [3] - Burst Type - BURST_TYPE // [1:0] - Burst Length - BURST_LEN // DDR2 Load mode register // Mode Register (MR): // [15:14] - unused - 00 // [13] - reserved - 0 // [12] - Power-down mode - 0 (normal) // [11:9] - write recovery - write recovery for Auto Precharge // (tWR/tCK = 6) // [8] - DLL reset - 0 or 1 // [7] - Test Mode - 0 (normal) // [6:4] - CAS latency - CAS_LAT // [3] - Burst Type - BURST_TYPE // [2:0] - Burst Length - BURST_LEN //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr0_DDR3 assign load_mr0[1:0] = (BURST_MODE == "8") ? 2'b00 : (BURST_MODE == "OTF") ? 2'b01 : (BURST_MODE == "4") ? 2'b10 : 2'b11; assign load_mr0[2] = (nCL >= 12) ? 1'b1 : 1'b0; // LSb of CAS latency assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; assign load_mr0[6:4] = ((nCL == 5) || (nCL == 13)) ? 3'b001 : ((nCL == 6) || (nCL == 14)) ? 3'b010 : (nCL == 7) ? 3'b011 : (nCL == 8) ? 3'b100 : (nCL == 9) ? 3'b101 : (nCL == 10) ? 3'b110 : (nCL == 11) ? 3'b111 : (nCL == 12) ? 3'b000 : 3'b111; assign load_mr0[7] = 1'b0; assign load_mr0[8] = 1'b1; // Reset DLL (init only) assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 : (TWR_CYC == 6) ? 3'b010 : (TWR_CYC == 7) ? 3'b011 : (TWR_CYC == 8) ? 3'b100 : (TWR_CYC == 9) ? 3'b101 : (TWR_CYC == 10) ? 3'b101 : (TWR_CYC == 11) ? 3'b110 : (TWR_CYC == 12) ? 3'b110 : (TWR_CYC == 13) ? 3'b111 : (TWR_CYC == 14) ? 3'b111 : (TWR_CYC == 15) ? 3'b000 : (TWR_CYC == 16) ? 3'b000 : 3'b010; assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit' assign load_mr0[15:13] = 3'b000; end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr0_DDR2 // block: gen assign load_mr0[2:0] = (BURST_MODE == "8") ? 3'b011 : (BURST_MODE == "4") ? 3'b010 : 3'b111; assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; assign load_mr0[6:4] = (nCL == 3) ? 3'b011 : (nCL == 4) ? 3'b100 : (nCL == 5) ? 3'b101 : (nCL == 6) ? 3'b110 : 3'b111; assign load_mr0[7] = 1'b0; assign load_mr0[8] = 1'b1; // Reset DLL (init only) assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 : (TWR_CYC == 3) ? 3'b010 : (TWR_CYC == 4) ? 3'b011 : (TWR_CYC == 5) ? 3'b100 : (TWR_CYC == 6) ? 3'b101 : 3'b010; assign load_mr0[15:12]= 4'b0000; // Reserved end endgenerate //***************************************************************** // DDR3 Load mode reg1 // Mode Register (MR1): // [15:13] - unused - 00 // [12] - output enable - 0 (enabled for DQ, DQS, DQS#) // [11] - TDQS enable - 0 (TDQS disabled and DM enabled) // [10] - reserved - 0 (must be '0') // [9] - RTT[2] - 0 // [8] - reserved - 0 (must be '0') // [7] - write leveling - 0 (disabled), 1 (enabled) // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) // [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7) // [4:3] - Additive CAS - ADDITIVE_CAS // [2] - RTT[0] // [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7) // [0] - DLL enable - 0 (normal) // DDR2 ext mode register // Extended Mode Register (MR): // [15:14] - unused - 00 // [13] - reserved - 0 // [12] - output enable - 0 (enabled) // [11] - RDQS enable - 0 (disabled) // [10] - DQS# enable - 0 (enabled) // [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init) // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) // [5:3] - Additive CAS - ADDITIVE_CAS // [2] - RTT[0] // [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced) // [0] - DLL enable - 0 (normal) //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr1_DDR3 assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b0 : 1'b1; assign load_mr1[2] = ((RTT_NOM_int == "30") || (RTT_NOM_int == "40") || (RTT_NOM_int == "60")) ? 1'b1 : 1'b0; assign load_mr1[4:3] = (AL == "0") ? 2'b00 : (AL == "CL-1") ? 2'b01 : (AL == "CL-2") ? 2'b10 : 2'b11; assign load_mr1[5] = 1'b0; assign load_mr1[6] = ((RTT_NOM_int == "40") || (RTT_NOM_int == "120")) ? 1'b1 : 1'b0; assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence assign load_mr1[8] = 1'b0; assign load_mr1[9] = ((RTT_NOM_int == "20") || (RTT_NOM_int == "30")) ? 1'b1 : 1'b0; assign load_mr1[10] = 1'b0; assign load_mr1[15:11] = 5'b00000; end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr1_DDR2 assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b1 : 1'b0; assign load_mr1[2] = ((RTT_NOM_int == "75") || (RTT_NOM_int == "50")) ? 1'b1 : 1'b0; assign load_mr1[5:3] = (AL == "0") ? 3'b000 : (AL == "1") ? 3'b001 : (AL == "2") ? 3'b010 : (AL == "3") ? 3'b011 : (AL == "4") ? 3'b100 : 3'b111; assign load_mr1[6] = ((RTT_NOM_int == "50") || (RTT_NOM_int == "150")) ? 1'b1 : 1'b0; assign load_mr1[9:7] = 3'b000; assign load_mr1[10] = (DDR2_DQSN_ENABLE == "YES") ? 1'b0 : 1'b1; assign load_mr1[15:11] = 5'b00000; end endgenerate //***************************************************************** // DDR3 Load mode reg2 // Mode Register (MR2): // [15:11] - unused - 00 // [10:9] - RTT_WR - 00 (Dynamic ODT off) // [8] - reserved - 0 (must be '0') // [7] - self-refresh temperature range - // 0 (normal), 1 (extended) // [6] - Auto Self-Refresh - 0 (manual), 1(auto) // [5:3] - CAS Write Latency (CWL) - // 000 (5 for 400 MHz device), // 001 (6 for 400 MHz to 533 MHz devices), // 010 (7 for 533 MHz to 667 MHz devices), // 011 (8 for 667 MHz to 800 MHz) // [2:0] - Partial Array Self-Refresh (Optional) - // 000 (full array) // Not used for DDR2 //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr2_DDR3 assign load_mr2[2:0] = 3'b000; assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 : (nCWL == 6) ? 3'b001 : (nCWL == 7) ? 3'b010 : (nCWL == 8) ? 3'b011 : (nCWL == 9) ? 3'b100 : (nCWL == 10) ? 3'b101 : (nCWL == 11) ? 3'b110 : 3'b111; assign load_mr2[6] = 1'b0; assign load_mr2[7] = 1'b0; assign load_mr2[8] = 1'b0; // Dynamic ODT disabled assign load_mr2[10:9] = 2'b00; assign load_mr2[15:11] = 5'b00000; end else begin: gen_load_mr2_DDR2 assign load_mr2[15:0] = 16'd0; end endgenerate //***************************************************************** // DDR3 Load mode reg3 // Mode Register (MR3): // [15:3] - unused - All zeros // [2] - MPR Operation - 0(normal operation), 1(data flow from MPR) // [1:0] - MPR location - 00 (Predefined pattern) //***************************************************************** assign load_mr3[1:0] = 2'b00; assign load_mr3[2] = 1'b0; assign load_mr3[15:3] = 13'b0000000000000; // For multi-rank systems the rank being accessed during writes in // Read Leveling must be sent to phy_write for the bitslip logic assign calib_rank_cnt = chip_cnt_r; //*************************************************************************** // Logic to begin initial calibration, and to handle precharge requests // during read-leveling (to avoid tRAS violations if individual read // levelling calibration stages take more than max{tRAS) to complete). //*************************************************************************** // Assert when readback for each stage of read-leveling begins. However, // note this indicates only when the read command is issued and when // Phaser_IN has phase aligned FREQ_REF clock to read DQS. It does not // indicate when the read data is present on the bus (when this happens // after the read command is issued depends on CAS LATENCY) - there will // need to be some delay before valid data is present on the bus. // assign rdlvl_start_pre = (init_state_r == INIT_PI_PHASELOCK_READS); // Assert when read back for oclkdelay calibration begins assign oclkdelay_calib_start_pre = (init_state_r == INIT_OCAL_CENTER_ACT); //(init_state_r == INIT_OCLKDELAY_READ); // Assert when read back for write calibration begins assign wrcal_start_pre = (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS); // Common precharge signal done signal - pulses only when there has been // a precharge issued as a result of a PRECH_REQ pulse. Note also a common // PRECH_DONE signal is used for all blocks assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || ((rdlvl_last_byte_done_r || prbs_last_byte_done_r) && (init_state_r == INIT_RDLVL_ACT_WAIT) && cnt_cmd_done_r) || (dqs_found_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || (init_state_r == INIT_MPR_RDEN) || ((init_state_r == INIT_WRCAL_ACT_WAIT) && cnt_cmd_done_r) || (init_state_r == INIT_OCAL_CENTER_ACT) || ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && complex_oclkdelay_calib_start_r1) || ((init_state_r == INIT_OCLKDELAY_ACT_WAIT) && cnt_cmd_done_r) || ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) && prbs_last_byte_done_r) || //prbs_rdlvl_done (wrlvl_final && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r && ~oclkdelay_calib_done)) && prech_pending_r && !prech_req_posedge_r); always @(posedge clk) if (rst) pi_phaselock_start <= #TCQ 1'b0; else if (init_state_r == INIT_PI_PHASELOCK_READS) pi_phaselock_start <= #TCQ 1'b1; // Delay start of each calibration by 16 clock cycles to ensure that when // calibration logic begins, read data is already appearing on the bus. // Each circuit should synthesize using an SRL16. Assume that reset is // long enough to clear contents of SRL16. always @(posedge clk) begin rdlvl_last_byte_done_r <= #TCQ rdlvl_last_byte_done; prbs_last_byte_done_r <= #TCQ prbs_last_byte_done; rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0], rdlvl_start_pre}; wrcal_start_dly_r <= #TCQ {wrcal_start_dly_r[14:0], wrcal_start_pre}; oclkdelay_start_dly_r <= #TCQ {oclkdelay_start_dly_r[14:0], oclkdelay_calib_start_pre}; prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0], prech_done_pre}; end always @(posedge clk) if (rst) oclkdelay_calib_start_int <= #TCQ 1'b0; else if (oclkdelay_start_dly_r[5]) oclkdelay_calib_start_int <= #TCQ 1'b1; always @(posedge clk) begin if (rst) ocal_last_byte_done <= #TCQ 1'b0; else if ((complex_oclkdelay_calib_cnt == DQS_WIDTH-1) && oclkdelay_center_calib_done) ocal_last_byte_done <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || (init_state_r == INIT_REFRESH) || prbs_rdlvl_done || ocal_last_byte_done || oclkdelay_center_calib_done) oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; else if (oclkdelay_calib_start_int) begin if (oclkdelay_ref_cnt > 'd0) oclkdelay_ref_cnt <= #TCQ oclkdelay_ref_cnt - 1; else oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; end end always @(posedge clk) begin if (rst || (init_state_r == INIT_OCAL_CENTER_ACT) || oclkdelay_calib_done || ocal_last_byte_done || oclkdelay_center_calib_done) oclkdelay_int_ref_req <= #TCQ 1'b0; else if (oclkdelay_ref_cnt == 'd1) oclkdelay_int_ref_req <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) ocal_act_wait_cnt <= #TCQ 'd0; else if ((init_state_r == INIT_OCAL_CENTER_ACT_WAIT) && ocal_act_wait_cnt < 'd15) ocal_act_wait_cnt <= #TCQ ocal_act_wait_cnt + 1; else ocal_act_wait_cnt <= #TCQ 'd0; end always @(posedge clk) begin if (rst || (init_state_r == INIT_OCLKDELAY_READ)) oclk_calib_resume_level <= #TCQ 1'b0; else if (oclk_calib_resume) oclk_calib_resume_level <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_ACT_WAIT) || prbs_rdlvl_done) complex_rdlvl_int_ref_req <= #TCQ 1'b0; else if (oclkdelay_ref_cnt == 'd1) // complex_rdlvl_int_ref_req <= #TCQ 1'b1; complex_rdlvl_int_ref_req <= #TCQ 1'b0; //temporary fix for read issue end always @(posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_COMPLEX_READ)) ext_int_ref_req <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_ACT_WAIT) && complex_rdlvl_int_ref_req) ext_int_ref_req <= #TCQ 1'b1; end always @(posedge clk) begin prech_done <= #TCQ prech_done_dly_r[15]; prech_done_r1 <= #TCQ prech_done_dly_r[15]; prech_done_r2 <= #TCQ prech_done_r1; prech_done_r3 <= #TCQ prech_done_r2; end always @(posedge clk) if (rst) mpr_rdlvl_start <= #TCQ 1'b0; else if (pi_dqs_found_done && (init_state_r == INIT_MPR_READ)) mpr_rdlvl_start <= #TCQ 1'b1; always @(posedge clk) phy_if_empty_r <= #TCQ phy_if_empty; always @(posedge clk) if (rst || ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || prbs_rdlvl_done) prbs_gen_clk_en <= #TCQ 1'b0; else if ((~phy_if_empty_r && rdlvl_stg1_done_r1 && ~prbs_rdlvl_done) || ((init_state_r == INIT_RDLVL_ACT_WAIT) && rdlvl_stg1_done_r1 && (cnt_cmd_r == 'd127)) || ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && rdlvl_stg1_done_r1 && (complex_wait_cnt == 'd14)) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || ((init_state_r == INIT_PRECHARGE_PREWAIT) && prbs_rdlvl_start)) prbs_gen_clk_en <= #TCQ 1'b1; //Enable for complex oclkdelay - used in prbs gen always @(posedge clk) if (rst || ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || complex_oclkdelay_calib_done || (complex_wait_cnt == 'd15 && complex_num_writes == 1 && complex_ocal_wr_start) || ( init_state_r == INIT_RDLVL_STG1_WRITE && complex_num_writes_dec == 'd2) || ~complex_ocal_wr_start || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT ) || (init_state_r != INIT_OCAL_COMPLEX_RESUME_WAIT && init_state_r1 == INIT_OCAL_COMPLEX_RESUME_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_ACT)) prbs_gen_oclk_clk_en <= #TCQ 1'b0; else if ((~phy_if_empty_r && ~complex_oclkdelay_calib_done && prbs_rdlvl_done_r1) || // changed for new algo 3/26 ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd14)) || ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14)) || exit_ocal_complex_resume_wait || ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && ~stg1_wr_done && ~complex_row1_wr_done && ~complex_ocal_num_samples_done_r && (complex_wait_cnt == 'd14)) || (init_state_r == INIT_RDLVL_COMPLEX_READ) ) prbs_gen_oclk_clk_en <= #TCQ 1'b1; generate if (RANKS < 2) begin always @(posedge clk) if (rst) begin rdlvl_stg1_start <= #TCQ 1'b0; rdlvl_stg1_start_int <= #TCQ 1'b0; rdlvl_start_pre <= #TCQ 1'b0; prbs_rdlvl_start <= #TCQ 1'b0; end else begin if (pi_dqs_found_done && cnt_cmd_done_r && (init_state_r == INIT_RDLVL_ACT_WAIT)) rdlvl_stg1_start_int <= #TCQ 1'b1; if (pi_dqs_found_done && (init_state_r == INIT_RDLVL_STG1_READ))begin rdlvl_start_pre <= #TCQ 1'b1; rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; end if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_READ) && (WRLVL == "ON")) begin prbs_rdlvl_start <= #TCQ 1'b1; end end end else begin always @(posedge clk) if (rst || rdlvl_stg1_rank_done) begin rdlvl_stg1_start <= #TCQ 1'b0; rdlvl_stg1_start_int <= #TCQ 1'b0; rdlvl_start_pre <= #TCQ 1'b0; prbs_rdlvl_start <= #TCQ 1'b0; end else begin if (pi_dqs_found_done && cnt_cmd_done_r && (init_state_r == INIT_RDLVL_ACT_WAIT)) rdlvl_stg1_start_int <= #TCQ 1'b1; if (pi_dqs_found_done && (init_state_r == INIT_RDLVL_STG1_READ))begin rdlvl_start_pre <= #TCQ 1'b1; rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; end if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_READ) && (WRLVL == "ON")) begin prbs_rdlvl_start <= #TCQ 1'b1; end end end endgenerate always @(posedge clk) begin if (rst || dqsfound_retry || wrlvl_byte_redo) begin pi_dqs_found_start <= #TCQ 1'b0; wrcal_start <= #TCQ 1'b0; end else begin if (!pi_dqs_found_done && init_state_r == INIT_RDLVL_STG2_READ) pi_dqs_found_start <= #TCQ 1'b1; if (wrcal_start_dly_r[5]) wrcal_start <= #TCQ 1'b1; end end // else: !if(rst) always @(posedge clk) if (rst) oclkdelay_calib_start <= #TCQ 1'b0; else if (oclkdelay_start_dly_r[5]) oclkdelay_calib_start <= #TCQ 1'b1; always @(posedge clk) if (rst) pi_dqs_found_done_r1 <= #TCQ 1'b0; else pi_dqs_found_done_r1 <= #TCQ pi_dqs_found_done; always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final; // Reset IN_FIFO after final write leveling to make sure the FIFO // pointers are initialized always @(posedge clk) if (rst || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_REFRESH)) wrlvl_final_if_rst <= #TCQ 1'b0; else if (wrlvl_done_r && //(wrlvl_final_r && wrlvl_done_r && (init_state_r == INIT_WRLVL_LOAD_MR2)) wrlvl_final_if_rst <= #TCQ 1'b1; // Constantly enable DQS while write leveling is enabled in the memory // This is more to get rid of warnings in simulation, can later change // this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted always @(posedge clk) if (rst || ((init_state_r1 != INIT_WRLVL_START) && (init_state_r == INIT_WRLVL_START))) wrlvl_odt_ctl <= #TCQ 1'b0; else if (wrlvl_rank_done && ~wrlvl_rank_done_r1) wrlvl_odt_ctl <= #TCQ 1'b1; generate if (nCK_PER_CLK == 4) begin: en_cnt_div4 always @ (posedge clk) if (rst) enable_wrlvl_cnt <= #TCQ 5'd0; else if ((init_state_r == INIT_WRLVL_START) || (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) enable_wrlvl_cnt <= #TCQ 5'd12; else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; // ODT stays asserted as long as write_calib // signal is asserted always @(posedge clk) if (rst || wrlvl_odt_ctl) wrlvl_odt <= #TCQ 1'b0; else if (enable_wrlvl_cnt == 5'd1) wrlvl_odt <= #TCQ 1'b1; end else begin: en_cnt_div2 always @ (posedge clk) if (rst) enable_wrlvl_cnt <= #TCQ 5'd0; else if ((init_state_r == INIT_WRLVL_START) || (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) enable_wrlvl_cnt <= #TCQ 5'd21; else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; // ODT stays asserted as long as write_calib // signal is asserted always @(posedge clk) if (rst || wrlvl_odt_ctl) wrlvl_odt <= #TCQ 1'b0; else if (enable_wrlvl_cnt == 5'd1) wrlvl_odt <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst || wrlvl_rank_done || done_dqs_tap_inc) wrlvl_active <= #TCQ 1'b0; else if ((enable_wrlvl_cnt == 5'd1) && wrlvl_odt && !wrlvl_active) wrlvl_active <= #TCQ 1'b1; // signal used to assert DQS for write leveling. // the DQS will be asserted once every 16 clock cycles. always @(posedge clk)begin if(rst || (enable_wrlvl_cnt != 5'd1)) begin wr_level_dqs_asrt <= #TCQ 1'd0; end else if ((enable_wrlvl_cnt == 5'd1) && (wrlvl_active_r1)) begin wr_level_dqs_asrt <= #TCQ 1'd1; end end always @ (posedge clk) begin if (rst || (wrlvl_done_r && ~wrlvl_done_r1)) dqs_asrt_cnt <= #TCQ 2'd0; else if (wr_level_dqs_asrt && dqs_asrt_cnt != 2'd3) dqs_asrt_cnt <= #TCQ (dqs_asrt_cnt + 1); end always @ (posedge clk) begin if (rst || ~wrlvl_active) wr_lvl_start <= #TCQ 1'd0; else if (dqs_asrt_cnt == 2'd3) wr_lvl_start <= #TCQ 1'd1; end always @(posedge clk) begin if (rst) wl_sm_start <= #TCQ 1'b0; else wl_sm_start <= #TCQ wr_level_dqs_asrt_r1; end always @(posedge clk) begin wrlvl_active_r1 <= #TCQ wrlvl_active; wr_level_dqs_asrt_r1 <= #TCQ wr_level_dqs_asrt; wrlvl_done_r <= #TCQ wrlvl_done; wrlvl_done_r1 <= #TCQ wrlvl_done_r; wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done; wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1; wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2; wrlvl_rank_done_r4 <= #TCQ wrlvl_rank_done_r3; wrlvl_rank_done_r5 <= #TCQ wrlvl_rank_done_r4; wrlvl_rank_done_r6 <= #TCQ wrlvl_rank_done_r5; wrlvl_rank_done_r7 <= #TCQ wrlvl_rank_done_r6; end always @ (posedge clk) begin //if (rst) wrlvl_rank_cntr <= #TCQ 3'd0; //else if (wrlvl_rank_done) // wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1; end //***************************************************************** // Precharge request logic - those calibration logic blocks // that require greater than tRAS(max) to finish must break up // their calibration into smaller units of time, with precharges // issued in between. This is done using the XXX_PRECH_REQ and // PRECH_DONE handshaking between PHY_INIT and those blocks //***************************************************************** // Shared request from multiple sources assign prech_req = oclk_prech_req | rdlvl_prech_req | wrcal_prech_req | prbs_rdlvl_prech_req | (dqs_found_prech_req & (init_state_r == INIT_RDLVL_STG2_READ_WAIT)); // Handshaking logic to force precharge during read leveling, and to // notify read leveling logic when precharge has been initiated and // it's okay to proceed with leveling again always @(posedge clk) if (rst) begin prech_req_r <= #TCQ 1'b0; prech_req_posedge_r <= #TCQ 1'b0; prech_pending_r <= #TCQ 1'b0; end else begin prech_req_r <= #TCQ prech_req; prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r; if (prech_req_posedge_r) prech_pending_r <= #TCQ 1'b1; // Clear after we've finished with the precharge and have // returned to issuing read leveling calibration reads else if (prech_done_pre) prech_pending_r <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || prech_done_r3) mask_lim_done <= #TCQ 1'b0; else if (prech_pending_r) mask_lim_done <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || prbs_rdlvl_done_r3) complex_mask_lim_done <= #TCQ 1'b0; else if (~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) complex_mask_lim_done <= #TCQ 1'b1; end //Complex oclkdelay calibrration //*************************************************************************** // Various timing counters //*************************************************************************** //***************************************************************** // Generic delay for various states that require it (e.g. for turnaround // between read and write). Make this a sufficiently large number of clock // cycles to cover all possible frequencies and memory components) // Requirements for this counter: // 1. Greater than tMRD // 2. tRFC (refresh-active) for DDR2 // 3. (list the other requirements, slacker...) //***************************************************************** always @(posedge clk) begin case (init_state_r) INIT_LOAD_MR_WAIT, INIT_WRLVL_LOAD_MR_WAIT, INIT_WRLVL_LOAD_MR2_WAIT, INIT_MPR_WAIT, INIT_MPR_DISABLE_PREWAIT, INIT_MPR_DISABLE_WAIT, INIT_OCLKDELAY_ACT_WAIT, INIT_OCLKDELAY_WRITE_WAIT, INIT_RDLVL_ACT_WAIT, INIT_RDLVL_STG1_WRITE_READ, INIT_RDLVL_STG2_READ_WAIT, INIT_WRCAL_ACT_WAIT, INIT_WRCAL_WRITE_READ, INIT_WRCAL_READ_WAIT, INIT_PRECHARGE_PREWAIT, INIT_PRECHARGE_WAIT, INIT_DDR2_PRECHARGE_WAIT, INIT_REG_WRITE_WAIT, INIT_REFRESH_WAIT, INIT_REFRESH_RNK2_WAIT: begin if (phy_ctl_full || phy_cmd_full) cnt_cmd_r <= #TCQ cnt_cmd_r; else cnt_cmd_r <= #TCQ cnt_cmd_r + 1; end INIT_WRLVL_WAIT: cnt_cmd_r <= #TCQ 'b0; default: cnt_cmd_r <= #TCQ 'b0; endcase end // pulse when count reaches terminal count always @(posedge clk) cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD); // For ODT deassertion - hold throughout post read/write wait stage, but // deassert before next command. The post read/write stage is very long, so // we simply address the longest case here plus some margin. always @(posedge clk) cnt_cmd_done_m7_r <= #TCQ (cnt_cmd_r == (CNTNEXT_CMD - 7)); //************************************************************************ // Added to support PO fine delay inc when TG errors always @(posedge clk) begin case (init_state_r) INIT_WRCAL_READ_WAIT: begin if (phy_ctl_full || phy_cmd_full) cnt_wait <= #TCQ cnt_wait; else cnt_wait <= #TCQ cnt_wait + 1; end default: cnt_wait <= #TCQ 'b0; endcase end always @(posedge clk) cnt_wrcal_rd <= #TCQ (cnt_wait == 'd4); always @(posedge clk) begin if (rst || ~temp_wrcal_done) temp_lmr_done <= #TCQ 1'b0; else if (temp_wrcal_done && (init_state_r == INIT_LOAD_MR)) temp_lmr_done <= #TCQ 1'b1; end always @(posedge clk) temp_wrcal_done_r <= #TCQ temp_wrcal_done; always @(posedge clk) if (rst) begin tg_timer_go <= #TCQ 1'b0; end else if ((PRE_REV3ES == "ON") && temp_wrcal_done && temp_lmr_done && (init_state_r == INIT_WRCAL_READ_WAIT)) begin tg_timer_go <= #TCQ 1'b1; end else begin tg_timer_go <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || (temp_wrcal_done && ~temp_wrcal_done_r) || (init_state_r == INIT_PRECHARGE_PREWAIT)) tg_timer <= #TCQ 'd0; else if ((pi_phaselock_timer == PHASELOCKED_TIMEOUT) && tg_timer_go && (tg_timer != TG_TIMER_TIMEOUT)) tg_timer <= #TCQ tg_timer + 1; end always @(posedge clk) begin if (rst) tg_timer_done <= #TCQ 1'b0; else if (tg_timer == TG_TIMER_TIMEOUT) tg_timer_done <= #TCQ 1'b1; else tg_timer_done <= #TCQ 1'b0; end always @(posedge clk) begin if (rst) no_rst_tg_mc <= #TCQ 1'b0; else if ((init_state_r == INIT_WRCAL_ACT) && wrcal_read_req) no_rst_tg_mc <= #TCQ 1'b1; else no_rst_tg_mc <= #TCQ 1'b0; end //************************************************************************ always @(posedge clk) begin if (rst) detect_pi_found_dqs <= #TCQ 1'b0; else if ((cnt_cmd_r == 7'b0111111) && (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) detect_pi_found_dqs <= #TCQ 1'b1; else detect_pi_found_dqs <= #TCQ 1'b0; end //***************************************************************** // Initial delay after power-on for RESET, CKE // NOTE: Could reduce power consumption by turning off these counters // after initial power-up (at expense of more logic) // NOTE: Likely can combine multiple counters into single counter //***************************************************************** // Create divided by 1024 version of clock always @(posedge clk) if (rst) begin cnt_pwron_ce_r <= #TCQ 10'h000; pwron_ce_r <= #TCQ 1'b0; end else begin cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1; pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF); end // "Main" power-on counter - ticks every CLKDIV/1024 cycles always @(posedge clk) if (rst) cnt_pwron_r <= #TCQ 'b0; else if (pwron_ce_r) cnt_pwron_r <= #TCQ cnt_pwron_r + 1; always @(posedge clk) if (rst || ~phy_ctl_ready) begin cnt_pwron_reset_done_r <= #TCQ 1'b0; cnt_pwron_cke_done_r <= #TCQ 1'b0; end else begin // skip power-up count for simulation purposes only if ((SIM_INIT_OPTION == "SKIP_PU_DLY") || (SIM_INIT_OPTION == "SKIP_INIT")) begin cnt_pwron_reset_done_r <= #TCQ 1'b1; cnt_pwron_cke_done_r <= #TCQ 1'b1; end else begin // otherwise, create latched version of done signal for RESET, CKE if (DRAM_TYPE == "DDR3") begin if (!cnt_pwron_reset_done_r) cnt_pwron_reset_done_r <= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT); if (!cnt_pwron_cke_done_r) cnt_pwron_cke_done_r <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); end else begin // DDR2 cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed if (!cnt_pwron_cke_done_r) cnt_pwron_cke_done_r <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); end end end // else: !if(rst || ~phy_ctl_ready) always @(posedge clk) cnt_pwron_cke_done_r1 <= #TCQ cnt_pwron_cke_done_r; // Keep RESET asserted and CKE deasserted until after power-on delay always @(posedge clk or posedge rst) begin if (rst) phy_reset_n <= #TCQ 1'b0; else phy_reset_n <= #TCQ cnt_pwron_reset_done_r; // phy_cke <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}}; end //***************************************************************** // Counter for tXPR (pronouned "Tax-Payer") - wait time after // CKE deassertion before first MRS command can be asserted //***************************************************************** always @(posedge clk) if (!cnt_pwron_cke_done_r) begin cnt_txpr_r <= #TCQ 'b0; cnt_txpr_done_r <= #TCQ 1'b0; end else begin cnt_txpr_r <= #TCQ cnt_txpr_r + 1; if (!cnt_txpr_done_r) cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT); end //***************************************************************** // Counter for the initial 400ns wait for issuing precharge all // command after CKE assertion. Only for DDR2. //***************************************************************** always @(posedge clk) if (!cnt_pwron_cke_done_r) begin cnt_init_pre_wait_r <= #TCQ 'b0; cnt_init_pre_wait_done_r <= #TCQ 1'b0; end else begin cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1; if (!cnt_init_pre_wait_done_r) cnt_init_pre_wait_done_r <= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT); end //***************************************************************** // Wait for both DLL to lock (tDLLK) and ZQ calibration to finish // (tZQINIT). Both take the same amount of time (512*tCK) //***************************************************************** always @(posedge clk) if (init_state_r == INIT_ZQCL) begin cnt_dllk_zqinit_r <= #TCQ 'b0; cnt_dllk_zqinit_done_r <= #TCQ 1'b0; end else if (~(phy_ctl_full || phy_cmd_full)) begin cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1; if (!cnt_dllk_zqinit_done_r) cnt_dllk_zqinit_done_r <= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT); end //***************************************************************** // Keep track of which MRS counter needs to be programmed during // memory initialization // The counter and the done signal are reset an additional time // for DDR2. The same signals are used for the additional DDR2 // initialization sequence. //***************************************************************** always @(posedge clk) if ((init_state_r == INIT_IDLE)|| ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))) begin cnt_init_mr_r <= #TCQ 'b0; cnt_init_mr_done_r <= #TCQ 1'b0; end else if (init_state_r == INIT_LOAD_MR) begin cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1; cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE); end //***************************************************************** // Flag to tell if the first precharge for DDR2 init sequence is // done //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) ddr2_pre_flag_r<= #TCQ 'b0; else if (init_state_r == INIT_LOAD_MR) ddr2_pre_flag_r<= #TCQ 1'b1; // reset the flag for multi rank case else if ((ddr2_refresh_flag_r) && (init_state_r == INIT_LOAD_MR_WAIT)&& (cnt_cmd_done_r) && (cnt_init_mr_done_r)) ddr2_pre_flag_r <= #TCQ 'b0; //***************************************************************** // Flag to tell if the refresh stat for DDR2 init sequence is // reached //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) ddr2_refresh_flag_r<= #TCQ 'b0; else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r)) // reset the flag for multi rank case ddr2_refresh_flag_r<= #TCQ 1'b1; else if ((ddr2_refresh_flag_r) && (init_state_r == INIT_LOAD_MR_WAIT)&& (cnt_cmd_done_r) && (cnt_init_mr_done_r)) ddr2_refresh_flag_r <= #TCQ 'b0; //***************************************************************** // Keep track of the number of auto refreshes for DDR2 // initialization. The spec asks for a minimum of two refreshes. // Four refreshes are performed here. The two extra refreshes is to // account for the 200 clock cycle wait between step h and l. // Without the two extra refreshes we would have to have a // wait state. //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) begin cnt_init_af_r <= #TCQ 'b0; cnt_init_af_done_r <= #TCQ 1'b0; end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))begin cnt_init_af_r <= #TCQ cnt_init_af_r + 1; cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11); end //***************************************************************** // Keep track of the register control word programming for // DDR3 RDIMM //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) reg_ctrl_cnt_r <= #TCQ 'b0; else if (init_state_r == INIT_REG_WRITE) reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1; generate if (RANKS < 2) begin: one_rank always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || (complex_byte_rd_done) || prbs_rdlvl_done_pulse ) stg1_wr_done <= #TCQ 1'b0; else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) stg1_wr_done <= #TCQ 1'b1; end else begin: two_ranks always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || (complex_byte_rd_done) || prbs_rdlvl_done_pulse || (rdlvl_stg1_rank_done )) stg1_wr_done <= #TCQ 1'b0; else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) stg1_wr_done <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst) rnk_ref_cnt <= #TCQ 1'b0; else if (stg1_wr_done && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r) rnk_ref_cnt <= #TCQ ~rnk_ref_cnt; always @(posedge clk) if (rst || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r ==INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT)) num_refresh <= #TCQ 'd0; else if ((init_state_r == INIT_REFRESH) && (~pi_dqs_found_done || ((DRAM_TYPE == "DDR3") && ~oclkdelay_calib_done) || (rdlvl_stg1_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done))) num_refresh <= #TCQ num_refresh + 1; //*************************************************************************** // Initialization state machine //*************************************************************************** //***************************************************************** // Next-state logic //***************************************************************** always @(posedge clk) if (rst)begin init_state_r <= #TCQ INIT_IDLE; init_state_r1 <= #TCQ INIT_IDLE; end else begin init_state_r <= #TCQ init_next_state; init_state_r1 <= #TCQ init_state_r; end always @(*) begin init_next_state = init_state_r; (* full_case, parallel_case *) case (init_state_r) //******************************************************* // DRAM initialization //******************************************************* // Initial state - wait for: // 1. Power-on delays to pass // 2. PHY Control Block to assert phy_ctl_ready // 3. PHY Control FIFO must not be FULL // 4. Read path initialization to finish INIT_IDLE: if (cnt_pwron_cke_done_r && phy_ctl_ready && ck_addr_cmd_delay_done && delay_incdec_done && ~(phy_ctl_full || phy_cmd_full) ) begin // If skipping memory initialization (simulation only) if (SIM_INIT_OPTION == "SKIP_INIT") //if (WRLVL == "ON") // Proceed to write leveling // init_next_state = INIT_WRLVL_START; //else //if (SIM_CAL_OPTION != "SKIP_CAL") // Proceed to Phaser_In phase lock init_next_state = INIT_RDLVL_ACT; // else // Skip read leveling //init_next_state = INIT_DONE; else init_next_state = INIT_WAIT_CKE_EXIT; end // Wait minimum of Reset CKE exit time (tXPR = max(tXS, INIT_WAIT_CKE_EXIT: if ((cnt_txpr_done_r) && (DRAM_TYPE == "DDR3") && ~(phy_ctl_full || phy_cmd_full)) begin if((REG_CTRL == "ON") && ((nCS_PER_RANK > 1) || (RANKS > 1))) //register write for reg dimm. Some register chips // have the register chip in a pre-programmed state // in that case the nCS_PER_RANK == 1 && RANKS == 1 init_next_state = INIT_REG_WRITE; else // Load mode register - this state is repeated multiple times init_next_state = INIT_LOAD_MR; end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == "DDR2") && ~(phy_ctl_full || phy_cmd_full)) // DDR2 start with a precharge all command init_next_state = INIT_DDR2_PRECHARGE; INIT_REG_WRITE: init_next_state = INIT_REG_WRITE_WAIT; INIT_REG_WRITE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if(reg_ctrl_cnt_r == 4'd8) init_next_state = INIT_LOAD_MR; else init_next_state = INIT_REG_WRITE; end INIT_LOAD_MR: init_next_state = INIT_LOAD_MR_WAIT; // After loading MR, wait at least tMRD INIT_LOAD_MR_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin // If finished loading all mode registers, proceed to next step if (prbs_rdlvl_done && pi_dqs_found_done && rdlvl_stg1_done) // for ddr3 when the correct burst length is writtern at end init_next_state = INIT_PRECHARGE; else if (~wrcal_done && temp_lmr_done) init_next_state = INIT_PRECHARGE_PREWAIT; else if (cnt_init_mr_done_r)begin if(DRAM_TYPE == "DDR3") init_next_state = INIT_ZQCL; else begin //DDR2 if(ddr2_refresh_flag_r)begin // memory initialization per rank for multi-rank case if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) init_next_state = INIT_DDR2_MULTI_RANK; else init_next_state = INIT_RDLVL_ACT; // ddr2 initialization done.load mode state after refresh end else init_next_state = INIT_DDR2_PRECHARGE; end end else init_next_state = INIT_LOAD_MR; end // DDR2 multi rank transition state INIT_DDR2_MULTI_RANK: init_next_state = INIT_DDR2_MULTI_RANK_WAIT; INIT_DDR2_MULTI_RANK_WAIT: init_next_state = INIT_DDR2_PRECHARGE; // Initial ZQ calibration INIT_ZQCL: init_next_state = INIT_WAIT_DLLK_ZQINIT; // Wait until both DLL have locked, and ZQ calibration done INIT_WAIT_DLLK_ZQINIT: if (cnt_dllk_zqinit_done_r && ~(phy_ctl_full || phy_cmd_full)) // memory initialization per rank for multi-rank case if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) init_next_state = INIT_LOAD_MR; //else if (WRLVL == "ON") // init_next_state = INIT_WRLVL_START; else // skip write-leveling (e.g. for DDR2 interface) init_next_state = INIT_RDLVL_ACT; // Initial precharge for DDR2 INIT_DDR2_PRECHARGE: init_next_state = INIT_DDR2_PRECHARGE_WAIT; INIT_DDR2_PRECHARGE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if (ddr2_pre_flag_r) init_next_state = INIT_REFRESH; else // from precharge state initially go to load mode init_next_state = INIT_LOAD_MR; end INIT_REFRESH: if ((RANKS == 2) && (chip_cnt_r == RANKS - 1)) init_next_state = INIT_REFRESH_RNK2_WAIT; else init_next_state = INIT_REFRESH_WAIT; INIT_REFRESH_RNK2_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_PRECHARGE; INIT_REFRESH_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin if(cnt_init_af_done_r && (~mem_init_done_r)) // go to lm state as part of DDR2 init sequence init_next_state = INIT_LOAD_MR; // Go to state to issue back-to-back writes during limit check and centering else if (~oclkdelay_calib_done && (mpr_last_byte_done || mpr_rdlvl_done) && (DRAM_TYPE == "DDR3")) begin if (num_refresh == 'd8) init_next_state = INIT_OCAL_CENTER_ACT; else init_next_state = INIT_REFRESH; end else if(rdlvl_stg1_done && oclkdelay_center_calib_done && complex_oclkdelay_calib_done && ~wrlvl_done_r1 && (WRLVL == "ON")) init_next_state = INIT_WRLVL_START; else if (pi_dqs_found_done && ~wrlvl_done_r1 && ~wrlvl_final && ~wrlvl_byte_redo && (WRLVL == "ON")) init_next_state = INIT_WRLVL_START; else if ((((prbs_last_byte_done_r || prbs_rdlvl_done) && ~complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON")) //&& rdlvl_stg1_done // changed for new algo 3/26 && mem_init_done_r) begin if (num_refresh == 'd8) begin if (BYPASS_COMPLEX_OCAL == "FALSE") init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else init_next_state = INIT_WRCAL_ACT; end else init_next_state = INIT_REFRESH; end else if (~pi_dqs_found_done || (rdlvl_stg1_done && ~prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)) begin if (num_refresh == 'd8) init_next_state = INIT_RDLVL_ACT; else init_next_state = INIT_REFRESH; end else if ((~wrcal_done && wrlvl_byte_redo)&& (DRAM_TYPE == "DDR3") && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRLVL_LOAD_MR2; else if (((prbs_rdlvl_done && rdlvl_stg1_done && complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON")) && mem_init_done_r && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRCAL_ACT; else if (pi_dqs_found_done && (DRAM_TYPE == "DDR3") && ~(mpr_last_byte_done || mpr_rdlvl_done)) begin if (num_refresh == 'd8) init_next_state = INIT_MPR_RDEN; else init_next_state = INIT_REFRESH; end else if (((oclkdelay_calib_done && wrlvl_final && ~wrlvl_done_r1) || // changed for new algo 3/25 (~wrcal_done && wrlvl_byte_redo)) && (DRAM_TYPE == "DDR3")) init_next_state = INIT_WRLVL_LOAD_MR2; else if ((~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) && pi_dqs_found_done) init_next_state = INIT_WRCAL_ACT; else if (mem_init_done_r) begin if (RANKS < 2) init_next_state = INIT_RDLVL_ACT; else if (stg1_wr_done && ~rnk_ref_cnt && ~rdlvl_stg1_done) init_next_state = INIT_PRECHARGE; else init_next_state = INIT_RDLVL_ACT; end else // to DDR2 init state as part of DDR2 init sequence init_next_state = INIT_REFRESH; end //****************************************************** // Write Leveling //******************************************************* // Enable write leveling in MR1 and start write leveling // for current rank INIT_WRLVL_START: init_next_state = INIT_WRLVL_WAIT; // Wait for both MR load and write leveling to complete // (write leveling should take much longer than MR load..) INIT_WRLVL_WAIT: if (wrlvl_rank_done_r7 && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRLVL_LOAD_MR; // Disable write leveling in MR1 for current rank INIT_WRLVL_LOAD_MR: init_next_state = INIT_WRLVL_LOAD_MR_WAIT; INIT_WRLVL_LOAD_MR_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRLVL_LOAD_MR2; // Load MR2 to set ODT: Dynamic ODT for single rank case // And ODTs for multi-rank case as well INIT_WRLVL_LOAD_MR2: init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; // Wait tMRD before proceeding INIT_WRLVL_LOAD_MR2_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin //if (wrlvl_byte_done) // init_next_state = INIT_PRECHARGE_PREWAIT; // else if ((RANKS == 2) && wrlvl_rank_done_r2) // init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; if (~wrlvl_done_r1) init_next_state = INIT_WRLVL_START; else if (SIM_CAL_OPTION == "SKIP_CAL") // If skip rdlvl, then we're done init_next_state = INIT_DONE; else // Otherwise, proceed to read leveling //init_next_state = INIT_RDLVL_ACT; init_next_state = INIT_PRECHARGE_PREWAIT; end //******************************************************* // Read Leveling //******************************************************* // single row activate. All subsequent read leveling writes and // read will take place in this row INIT_RDLVL_ACT: init_next_state = INIT_RDLVL_ACT_WAIT; // hang out for awhile before issuing subsequent column commands // it's also possible to reach this state at various points // during read leveling - determine what the current stage is INIT_RDLVL_ACT_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin // Just finished an activate. Now either write, read, or precharge // depending on where we are in the training sequence if (!pi_calib_done_r1) init_next_state = INIT_PI_PHASELOCK_READS; else if (!pi_dqs_found_done) // (!pi_dqs_found_start || pi_dqs_found_rank_done)) init_next_state = INIT_RDLVL_STG2_READ; else if (~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) init_next_state = INIT_WRCAL_ACT_WAIT; else if ((!rdlvl_stg1_done && ~stg1_wr_done && ~rdlvl_last_byte_done) || (!prbs_rdlvl_done && ~stg1_wr_done && ~prbs_last_byte_done)) begin // Added to avoid rdlvl_stg1 write data pattern at the start of PRBS rdlvl if (!prbs_rdlvl_done && ~stg1_wr_done && rdlvl_last_byte_done) init_next_state = INIT_RDLVL_ACT_WAIT; else init_next_state = INIT_RDLVL_STG1_WRITE; end else if ((!rdlvl_stg1_done && rdlvl_stg1_start_int) || !prbs_rdlvl_done) begin if (rdlvl_last_byte_done || prbs_last_byte_done) // Added to avoid extra reads at the end of read leveling init_next_state = INIT_RDLVL_ACT_WAIT; else begin // Case 2: If in stage 1, and just precharged after training // previous byte, then continue reading if (rdlvl_stg1_done) init_next_state = INIT_RDLVL_STG1_WRITE_READ; else init_next_state = INIT_RDLVL_STG1_READ; end end else if ((prbs_rdlvl_done && rdlvl_stg1_done && (RANKS == 1)) && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRCAL_ACT_WAIT; else // Otherwise, if we're finished with calibration, then precharge // the row - silly, because we just opened it - possible to take // this out by adding logic to avoid the ACT in first place. Make // sure that cnt_cmd_done will handle tRAS(min) init_next_state = INIT_PRECHARGE_PREWAIT; end //************************************************** // Back-to-back reads for Phaser_IN Phase locking // DQS to FREQ_REF clock //************************************************** INIT_PI_PHASELOCK_READS: if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) init_next_state = INIT_PRECHARGE_PREWAIT; //********************************************* // Stage 1 read-leveling (write and continuous read) //********************************************* // Write training pattern for stage 1 // PRBS pattern of TBD length INIT_RDLVL_STG1_WRITE: // 4:1 DDR3 BL8 will require all 8 words in 1 DIV4 clock cycle // 2:1 DDR2/DDR3 BL8 will require 2 DIV2 clock cycles for 8 words // 2:1 DDR2 BL4 will require 1 DIV2 clock cycle for 4 words // An entire row worth of writes issued before proceeding to reads // The number of write is (2^column width)/burst length to accomodate // PRBS pattern for window detection. //VCCO/VCCAUX write is not done if ((complex_num_writes_dec == 1) && ~complex_row0_wr_done && prbs_rdlvl_done && rdlvl_stg1_done_r1) init_next_state = INIT_OCAL_COMPLEX_WRITE_WAIT; //back to back write from row1 else if (stg1_wr_rd_cnt == 9'd1) begin if (rdlvl_stg1_done_r1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else init_next_state = INIT_RDLVL_STG1_WRITE_READ; end INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT: if(read_pause_ext) begin init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; end else begin if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) //At the end of the byte, it goes to REFRESH init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE; end INIT_RDLVL_COMPLEX_PRECHARGE: init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; INIT_RDLVL_COMPLEX_PRECHARGE_WAIT: if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) begin if (prbs_rdlvl_done || prbs_last_byte_done_r) begin // changed for new algo 3/26 // added condition to ensure that limit starts after rdlvl_stg1_done is asserted in the bypass complex rdlvl mode if ((~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) || ~lim_done) init_next_state = INIT_OCAL_CENTER_ACT; //INIT_OCAL_COMPLEX_ACT; // changed for new algo 3/26 else if (lim_done && complex_oclkdelay_calib_start_r2) init_next_state = INIT_RDLVL_COMPLEX_ACT; else init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; end else init_next_state = INIT_RDLVL_COMPLEX_ACT; end INIT_RDLVL_COMPLEX_ACT: init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT; INIT_RDLVL_COMPLEX_ACT_WAIT: if (complex_rdlvl_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) begin if (oclkdelay_center_calib_start) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; else if (stg1_wr_done) init_next_state = INIT_RDLVL_COMPLEX_READ; else if (~complex_row1_wr_done) if (complex_oclkdelay_calib_start_int && complex_ocal_num_samples_done_r) //WAIT for resume signal for write init_next_state = INIT_OCAL_COMPLEX_RESUME_WAIT; else init_next_state = INIT_RDLVL_STG1_WRITE; else init_next_state = INIT_RDLVL_STG1_WRITE_READ; end // Write-read turnaround INIT_RDLVL_STG1_WRITE_READ: if (reset_rd_addr_r1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin if (rdlvl_stg1_done_r1) init_next_state = INIT_RDLVL_COMPLEX_READ; else init_next_state = INIT_RDLVL_STG1_READ; end // Continuous read, where interruptible by precharge request from // calibration logic. Also precharges when stage 1 is complete // No precharges when reads provided to Phaser_IN for phase locking // FREQ_REF to read DQS since data integrity is not important. INIT_RDLVL_STG1_READ: if (rdlvl_stg1_rank_done || (rdlvl_stg1_done && ~rdlvl_stg1_done_r1) || prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; INIT_RDLVL_COMPLEX_READ: if (prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; //For non-back-to-back reads from row0 (VCCO and VCCAUX pattern) else if (~prbs_rdlvl_done && (complex_num_reads_dec == 1) && ~complex_row0_rd_done) init_next_state = INIT_RDLVL_COMPLEX_READ_WAIT; //For back-to-back reads from row1 (ISI pattern) else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; INIT_RDLVL_COMPLEX_READ_WAIT: if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) init_next_state = INIT_RDLVL_COMPLEX_READ; //********************************************* // DQSFOUND calibration (set of 4 reads with gaps) //********************************************* // Read of training data. Note that Stage 2 is not a constant read, // instead there is a large gap between each set of back-to-back reads INIT_RDLVL_STG2_READ: // 4 read commands issued back-to-back if (num_reads == 'b1) init_next_state = INIT_RDLVL_STG2_READ_WAIT; // Wait before issuing the next set of reads. If a precharge request // comes in then handle - this can occur after stage 2 calibration is // completed for a DQS group INIT_RDLVL_STG2_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if (pi_dqs_found_rank_done || pi_dqs_found_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; else if (cnt_cmd_done_r) init_next_state = INIT_RDLVL_STG2_READ; end //****************************************************************** // MPR Read Leveling for DDR3 OCLK_DELAYED calibration //****************************************************************** // Issue Load Mode Register 3 command with A[2]=1, A[1:0]=2'b00 // to enable Multi Purpose Register (MPR) Read INIT_MPR_RDEN: init_next_state = INIT_MPR_WAIT; //Wait tMRD, tMOD INIT_MPR_WAIT: if (cnt_cmd_done_r) begin init_next_state = INIT_MPR_READ; end // Issue back-to-back read commands to read from MPR with // Address bus 0x0000 for BL=8. DQ[0] will output the pre-defined // MPR pattern of 01010101 (Rise0 = 1'b0, Fall0 = 1'b1 ...) INIT_MPR_READ: if (mpr_rdlvl_done || mpr_rnk_done || rdlvl_prech_req) init_next_state = INIT_MPR_DISABLE_PREWAIT; INIT_MPR_DISABLE_PREWAIT: if (cnt_cmd_done_r) init_next_state = INIT_MPR_DISABLE; // Issue Load Mode Register 3 command with A[2]=0 to disable // MPR read INIT_MPR_DISABLE: init_next_state = INIT_MPR_DISABLE_WAIT; INIT_MPR_DISABLE_WAIT: init_next_state = INIT_PRECHARGE_PREWAIT; //*********************************************************************** // OCLKDELAY Calibration //*********************************************************************** // This calibration requires single write followed by single read to // determine the Phaser_Out stage 3 delay required to center write DQS // in write DQ valid window. // Single Row Activate command before issuing Write command INIT_OCLKDELAY_ACT: init_next_state = INIT_OCLKDELAY_ACT_WAIT; INIT_OCLKDELAY_ACT_WAIT: if (cnt_cmd_done_r && ~oclk_prech_req) init_next_state = INIT_OCLKDELAY_WRITE; else if (oclkdelay_calib_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; INIT_OCLKDELAY_WRITE: if (oclk_wr_cnt == 4'd1) init_next_state = INIT_OCLKDELAY_WRITE_WAIT; INIT_OCLKDELAY_WRITE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if (oclkdelay_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else init_next_state = INIT_OCLKDELAY_READ; end INIT_OCLKDELAY_READ: init_next_state = INIT_OCLKDELAY_READ_WAIT; INIT_OCLKDELAY_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if ((oclk_calib_resume_level || oclk_calib_resume) && ~oclkdelay_int_ref_req) init_next_state = INIT_OCLKDELAY_WRITE; else if (oclkdelay_calib_done || prech_req_posedge_r || wrlvl_final || oclkdelay_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else if (oclkdelay_center_calib_start) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; end //********************************************* // Write calibration //********************************************* // single row activate INIT_WRCAL_ACT: init_next_state = INIT_WRCAL_ACT_WAIT; // hang out for awhile before issuing subsequent column command INIT_WRCAL_ACT_WAIT: if (cnt_cmd_done_r && ~wrcal_prech_req) init_next_state = INIT_WRCAL_WRITE; else if (wrcal_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; // Write training pattern for write calibration INIT_WRCAL_WRITE: // Once we've issued enough commands for 8 words - proceed to reads //if (burst_addr_r == 1'b1) if (wrcal_wr_cnt == 4'd1) init_next_state = INIT_WRCAL_WRITE_READ; // Write-read turnaround INIT_WRCAL_WRITE_READ: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRCAL_READ; else if (dqsfound_retry) init_next_state = INIT_RDLVL_STG2_READ_WAIT; INIT_WRCAL_READ: if (burst_addr_r == 1'b1) init_next_state = INIT_WRCAL_READ_WAIT; INIT_WRCAL_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if (wrcal_resume_r) begin if (wrcal_final_chk) init_next_state = INIT_WRCAL_READ; else init_next_state = INIT_WRCAL_WRITE; end else if (wrcal_done || prech_req_posedge_r || wrcal_act_req || // Added to support PO fine delay inc when TG errors wrlvl_byte_redo || (temp_wrcal_done && ~temp_lmr_done)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (dqsfound_retry) init_next_state = INIT_RDLVL_STG2_READ_WAIT; else if (wrcal_read_req && cnt_wrcal_rd) init_next_state = INIT_WRCAL_MULT_READS; end INIT_WRCAL_MULT_READS: // multiple read commands issued back-to-back if (wrcal_reads == 'b1) init_next_state = INIT_WRCAL_READ_WAIT; //********************************************* // Handling of precharge during and in between read-level stages //********************************************* // Make sure we aren't violating any timing specs by precharging // immediately INIT_PRECHARGE_PREWAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_PRECHARGE; // Initiate precharge INIT_PRECHARGE: init_next_state = INIT_PRECHARGE_WAIT; INIT_PRECHARGE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if ((wrcal_sanity_chk_done && (DRAM_TYPE == "DDR3")) || (rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && (DRAM_TYPE == "DDR2"))) init_next_state = INIT_DONE; else if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && complex_oclkdelay_calib_done && wrlvl_done_r1 && ((ddr3_lm_done_r) || (DRAM_TYPE == "DDR2"))) init_next_state = INIT_WRCAL_ACT; else if ((wrcal_done || (WRLVL == "OFF") || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) && (rdlvl_stg1_done || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) && prbs_rdlvl_done && complex_oclkdelay_calib_done && wrlvl_done_r1 &rdlvl_stg1_done && pi_dqs_found_done) begin // after all calibration program the correct burst length init_next_state = INIT_LOAD_MR; // Added to support PO fine delay inc when TG errors end else if (~wrcal_done && temp_wrcal_done && temp_lmr_done) init_next_state = INIT_WRCAL_READ_WAIT; else if (rdlvl_stg1_done && pi_dqs_found_done && (WRLVL == "ON")) // If read leveling finished, proceed to write calibration init_next_state = INIT_REFRESH; else // Otherwise, open row for read-leveling purposes init_next_state = INIT_REFRESH; end //******************************************************* // COMPLEX OCLK calibration - for fragmented write //******************************************************* INIT_OCAL_COMPLEX_ACT: init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; INIT_OCAL_COMPLEX_ACT_WAIT: if (complex_wait_cnt =='d15) init_next_state = INIT_RDLVL_STG1_WRITE; INIT_OCAL_COMPLEX_WRITE_WAIT: if (prech_req_posedge_r || (complex_oclkdelay_calib_done && ~complex_oclkdelay_calib_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) init_next_state = INIT_RDLVL_STG1_WRITE; //wait for all srg2/stg3 tap movement is done and go back to write again INIT_OCAL_COMPLEX_RESUME_WAIT: if (complex_oclk_calib_resume) init_next_state = INIT_RDLVL_STG1_WRITE; else if (complex_oclkdelay_calib_done || complex_ocal_ref_req ) init_next_state = INIT_PRECHARGE_PREWAIT; //******************************************************* // OCAL STG3 Centering calibration //******************************************************* INIT_OCAL_CENTER_ACT: init_next_state = INIT_OCAL_CENTER_ACT_WAIT; INIT_OCAL_CENTER_ACT_WAIT: if (ocal_act_wait_cnt == 'd15) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; INIT_OCAL_CENTER_WRITE: if(!oclk_center_write_resume && !lim_wr_req) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; INIT_OCAL_CENTER_WRITE_WAIT: //if (oclkdelay_center_calib_done || prech_req_posedge_r) if (prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && oclkdelay_calib_done && ~oclkdelay_center_calib_start) init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && ~oclkdelay_center_calib_start) init_next_state = INIT_OCLKDELAY_READ_WAIT; else if (oclk_center_write_resume || lim_wr_req) init_next_state = INIT_OCAL_CENTER_WRITE; //******************************************************* // Initialization/Calibration done. Take a long rest, relax //******************************************************* INIT_DONE: init_next_state = INIT_DONE; endcase end //***************************************************************** // Initialization done signal - asserted before leveling starts //***************************************************************** always @(posedge clk) if (rst) mem_init_done_r <= #TCQ 1'b0; else if ((!cnt_dllk_zqinit_done_r && (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) && (chip_cnt_r == RANKS-1) && (DRAM_TYPE == "DDR3")) || ( (init_state_r == INIT_LOAD_MR_WAIT) && (ddr2_refresh_flag_r) && (chip_cnt_r == RANKS-1) && (cnt_init_mr_done_r) && (DRAM_TYPE == "DDR2"))) mem_init_done_r <= #TCQ 1'b1; //***************************************************************** // Write Calibration signal to PHY Control Block - asserted before // Write Leveling starts //***************************************************************** //generate //if (RANKS < 2) begin: ranks_one always @(posedge clk) begin if (rst || (done_dqs_tap_inc && (init_state_r == INIT_WRLVL_LOAD_MR2))) write_calib <= #TCQ 1'b0; else if (wrlvl_active_r1) write_calib <= #TCQ 1'b1; end //end else begin: ranks_two // always @(posedge clk) begin // if (rst || // ((init_state_r1 == INIT_WRLVL_LOAD_MR_WAIT) && // ((wrlvl_rank_done_r2 && (chip_cnt_r == RANKS-1)) || // (SIM_CAL_OPTION == "FAST_CAL")))) // write_calib <= #TCQ 1'b0; // else if (wrlvl_active_r1) // write_calib <= #TCQ 1'b1; // end //end //endgenerate //***************************************************************** // Read Calibration signal to PHY Control Block - asserted after // Write Leveling during PHASER_IN phase locking stage. // Must be de-asserted before Read Leveling //***************************************************************** always @(posedge clk) begin if (rst || pi_calib_done_r1) read_calib_int <= #TCQ 1'b0; else if (~pi_calib_done_r1 && (init_state_r == INIT_RDLVL_ACT_WAIT) && (cnt_cmd_r == CNTNEXT_CMD)) read_calib_int <= #TCQ 1'b1; end always @(posedge clk) read_calib_r <= #TCQ read_calib_int; always @(posedge clk) begin if (rst || pi_calib_done_r1) read_calib <= #TCQ 1'b0; else if (~pi_calib_done_r1 && (init_state_r == INIT_PI_PHASELOCK_READS)) read_calib <= #TCQ 1'b1; end always @(posedge clk) if (rst) pi_calib_done_r <= #TCQ 1'b0; else if (pi_calib_rank_done_r)// && (chip_cnt_r == RANKS-1)) pi_calib_done_r <= #TCQ 1'b1; always @(posedge clk) if (rst) pi_calib_rank_done_r <= #TCQ 1'b0; else if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) pi_calib_rank_done_r <= #TCQ 1'b1; else pi_calib_rank_done_r <= #TCQ 1'b0; always @(posedge clk) begin if (rst || ((PRE_REV3ES == "ON") && temp_wrcal_done && ~temp_wrcal_done_r)) pi_phaselock_timer <= #TCQ 'd0; else if (((init_state_r == INIT_PI_PHASELOCK_READS) && (pi_phaselock_timer != PHASELOCKED_TIMEOUT)) || tg_timer_go) pi_phaselock_timer <= #TCQ pi_phaselock_timer + 1; else pi_phaselock_timer <= #TCQ pi_phaselock_timer; end assign pi_phase_locked_err = (pi_phaselock_timer == PHASELOCKED_TIMEOUT) ? 1'b1 : 1'b0; //***************************************************************** // DDR3 final burst length programming done. For DDR3 during // calibration the burst length is fixed to BL8. After calibration // the correct burst length is programmed. //***************************************************************** always @(posedge clk) if (rst) ddr3_lm_done_r <= #TCQ 1'b0; else if ((init_state_r == INIT_LOAD_MR_WAIT) && (chip_cnt_r == RANKS-1) && wrcal_done) ddr3_lm_done_r <= #TCQ 1'b1; always @(posedge clk) begin pi_dqs_found_rank_done_r <= #TCQ pi_dqs_found_rank_done; pi_phase_locked_all_r1 <= #TCQ pi_phase_locked_all; pi_phase_locked_all_r2 <= #TCQ pi_phase_locked_all_r1; pi_phase_locked_all_r3 <= #TCQ pi_phase_locked_all_r2; pi_phase_locked_all_r4 <= #TCQ pi_phase_locked_all_r3; pi_dqs_found_all_r <= #TCQ pi_dqs_found_done; pi_calib_done_r1 <= #TCQ pi_calib_done_r; end //*************************************************************************** // Logic for deep memory (multi-rank) configurations //*************************************************************************** // For DDR3 asserted when generate if (RANKS < 2) begin: single_rank always @(posedge clk) chip_cnt_r <= #TCQ 2'b00; end else begin: dual_rank always @(posedge clk) if (rst || // Set chip_cnt_r to 2'b00 after both Ranks are read leveled (rdlvl_stg1_done && prbs_rdlvl_done && ~wrcal_done) || // Set chip_cnt_r to 2'b00 after both Ranks are write leveled (wrlvl_done_r && (init_state_r==INIT_WRLVL_LOAD_MR2_WAIT)))begin chip_cnt_r <= #TCQ 2'b00; end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) && (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT)) && (DRAM_TYPE == "DDR3")) || ((init_state_r==INIT_REFRESH_RNK2_WAIT) && (cnt_cmd_r=='d36)) || //mpr_rnk_done || //(rdlvl_stg1_rank_done && ~rdlvl_last_byte_done) || //(stg1_wr_done && (init_state_r == INIT_REFRESH) && //~(rnk_ref_cnt && rdlvl_last_byte_done)) || // Increment chip_cnt_r to issue Refresh to second rank (~pi_dqs_found_all_r && (init_state_r==INIT_PRECHARGE_PREWAIT) && (cnt_cmd_r=='d36)) || // Increment chip_cnt_r when DQSFOUND done for the Rank (pi_dqs_found_rank_done && ~pi_dqs_found_rank_done_r) || ((init_state_r == INIT_LOAD_MR_WAIT)&& cnt_cmd_done_r && wrcal_done) || ((init_state_r == INIT_DDR2_MULTI_RANK) && (DRAM_TYPE == "DDR2"))) begin if ((~mem_init_done_r || ~rdlvl_stg1_done || ~pi_dqs_found_done || // condition to increment chip_cnt during // final burst length programming for DDR3 ~pi_calib_done_r || wrcal_done) //~mpr_rdlvl_done || && (chip_cnt_r != RANKS-1)) chip_cnt_r <= #TCQ chip_cnt_r + 1; else chip_cnt_r <= #TCQ 2'b00; end end endgenerate // verilint STARC-2.2.3.3 off generate if ((REG_CTRL == "ON") && (RANKS == 1)) begin: DDR3_RDIMM_1rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[0] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end end else if (RANKS == 1) begin: DDR3_1rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (n = 0; n < nCS_PER_RANK; n = n + 1) begin phy_int_cs_n[n] <= #TCQ 1'b0; end end else begin //odd CWL for (p = nCS_PER_RANK; p < 2*nCS_PER_RANK; p = p + 1) begin phy_int_cs_n[p] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end end else if ((REG_CTRL == "ON") && (RANKS == 2)) begin: DDR3_2rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; case (chip_cnt_r) 2'b00:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[0] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end 2'b01:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[1] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1+1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end endcase end end end else if (RANKS == 2) begin: DDR3_2rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; case (chip_cnt_r) 2'b00:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (n = 0; n < nCS_PER_RANK; n = n + 1) begin phy_int_cs_n[n] <= #TCQ 1'b0; end end else begin // odd CWL for (p = CS_WIDTH*nCS_PER_RANK; p < (CS_WIDTH*nCS_PER_RANK + nCS_PER_RANK); p = p + 1) begin phy_int_cs_n[p] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end 2'b01:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (q = nCS_PER_RANK; q < (2 * nCS_PER_RANK); q = q + 1) begin phy_int_cs_n[q] <= #TCQ 1'b0; end end else begin // odd CWL for (m = (nCS_PER_RANK*CS_WIDTH + nCS_PER_RANK); m < (nCS_PER_RANK*CS_WIDTH + 2*nCS_PER_RANK); m = m + 1) begin phy_int_cs_n[m] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end endcase end end // always @ (posedge clk) end // verilint STARC-2.2.3.3 on // commented out for now. Need it for DDR2 2T timing /* end else begin: DDR2 always @(posedge clk) if (rst) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end else begin if (init_state_r == INIT_REG_WRITE) begin // All ranks selected simultaneously phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}}; end else if ((wrlvl_odt) || (init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH)) begin phy_int_cs_n[0] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end // else: !if(rst) end // block: DDR2 */ endgenerate assign phy_cs_n = phy_int_cs_n; //*************************************************************************** // Write/read burst logic for calibration //*************************************************************************** assign rdlvl_wr = (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE); assign rdlvl_rd = (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_MPR_READ) || (init_state_r == INIT_WRCAL_MULT_READS); assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd; assign mmcm_wr = (init_state_r == INIT_OCAL_CENTER_WRITE); //used to de-assert cs_n during centering // assign mmcm_wr = 'b0; // (init_state_r == INIT_OCAL_CENTER_WRITE); //*************************************************************************** // Address generation and logic to count # of writes/reads issued during // certain stages of calibration //*************************************************************************** // Column address generation logic: // Keep track of the current column address - since all bursts are in // increments of 8 only during calibration, we need to keep track of // addresses [COL_WIDTH-1:3], lower order address bits will always = 0 always @(posedge clk) if (rst || wrcal_done) burst_addr_r <= #TCQ 1'b0; else if ((init_state_r == INIT_WRCAL_ACT_WAIT) || (init_state_r == INIT_OCLKDELAY_ACT_WAIT) || (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS) || (init_state_r == INIT_WRCAL_READ_WAIT)) burst_addr_r <= #TCQ 1'b1; else if (rdlvl_wr_rd && new_burst_r) burst_addr_r <= #TCQ ~burst_addr_r; else burst_addr_r <= #TCQ 1'b0; // Read Level Stage 1 requires writes to the entire row since // a PRBS pattern is being written. This counter keeps track // of the number of writes which depends on the column width // The (stg1_wr_rd_cnt==9'd0) condition was added so the col // address wraps around during stage1 reads always @(posedge clk) if (rst || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && ~rdlvl_stg1_done)) stg1_wr_rd_cnt <= #TCQ NUM_STG1_WR_RD; else if (rdlvl_last_byte_done || (stg1_wr_rd_cnt == 9'd1) || (prbs_rdlvl_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || (init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) ) begin if (~complex_row0_wr_done || wr_victim_inc || (complex_row1_wr_done && (~complex_row0_rd_done || (complex_row0_rd_done && complex_row1_rd_done)))) stg1_wr_rd_cnt <= #TCQ 'd127; else stg1_wr_rd_cnt <= #TCQ prbs_rdlvl_done?'d30 :'d22; end else if (((init_state_r == INIT_RDLVL_STG1_WRITE) && new_burst_r && ~phy_data_full) ||((init_state_r == INIT_RDLVL_COMPLEX_READ) && rdlvl_stg1_done)) stg1_wr_rd_cnt <= #TCQ stg1_wr_rd_cnt - 1; always @(posedge clk) if (rst) wr_victim_inc <= #TCQ 1'b0; else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2) && ~stg1_wr_done) wr_victim_inc <= #TCQ 1'b1; else wr_victim_inc <= #TCQ 1'b0; always @(posedge clk) reset_rd_addr_r1 <= #TCQ reset_rd_addr; generate if (FIXED_VICTIM == "FALSE") begin: row_cnt_victim_rotate always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt == DQ_WIDTH*2-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) complex_row_cnt <= #TCQ 'd0; else if ((((stg1_wr_rd_cnt == 'd22) && ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (complex_rdlvl_int_ref_req && (init_state_r == INIT_REFRESH_WAIT) && (cnt_cmd_r == 'd127)))) || complex_victim_inc || (complex_sample_cnt_inc_r2 && ~complex_victim_inc) || wr_victim_inc || reset_rd_addr_r1)) begin // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 if ((complex_row_cnt < DQ_WIDTH*2-1) && ~stg1_wr_done) complex_row_cnt <= #TCQ complex_row_cnt + 1; // During reads row count requires different conditions for increments else if (stg1_wr_done) begin if (reset_rd_addr_r1) complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16; // When looping multiple times in the same victim bit in a byte else if (complex_sample_cnt_inc_r2 && ~complex_victim_inc) complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16 + rd_victim_sel*2; // When looping through victim bits within a byte else if (complex_row_cnt < pi_stg2_prbs_rdlvl_cnt*16+15) complex_row_cnt <= #TCQ complex_row_cnt + 1; // When the number of samples is done and tap is incremented within a byte else complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16; end end end else begin: row_cnt_victim_fixed always @(posedge clk) if (rst || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) complex_row_cnt <= #TCQ 'd0; else if ((stg1_wr_rd_cnt == 'd22) && (((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) && (complex_wait_cnt == 'd15)) || complex_rdlvl_int_ref_req)) complex_row_cnt <= #TCQ 'd1; else complex_row_cnt <= #TCQ 'd0; end endgenerate //row count always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done_pulse || complex_byte_rd_done) complex_row_cnt_ocal <= #TCQ 'd0; else if ( prbs_rdlvl_done && (((stg1_wr_rd_cnt == 'd30) && (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE)) || (complex_sample_cnt_inc_r2) || wr_victim_inc)) begin // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 if (complex_row_cnt_ocal < COMPLEX_ROW_CNT_BYTE-1) begin complex_row_cnt_ocal <= #TCQ complex_row_cnt_ocal + 1; end end always @(posedge clk) if (rst) complex_odt_ext <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE)) complex_odt_ext <= #TCQ 1'b0; else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd1) && (init_state_r == INIT_RDLVL_STG1_WRITE)) complex_odt_ext <= #TCQ 1'b1; always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt == DQ_WIDTH*2-1))) begin wr_victim_sel <= #TCQ 'd0; wr_byte_cnt <= #TCQ 'd0; end else if (rdlvl_stg1_done_r1 && wr_victim_inc) begin wr_victim_sel <= #TCQ wr_victim_sel + 1; if (wr_victim_sel == 'd7) wr_byte_cnt <= #TCQ wr_byte_cnt + 1; end always @(posedge clk) if (rst) begin wr_victim_sel_ocal <= #TCQ 'd0; end else if (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) begin wr_victim_sel_ocal <= #TCQ 'd0; end else if (prbs_rdlvl_done && wr_victim_inc) begin wr_victim_sel_ocal <= #TCQ wr_victim_sel_ocal + 1; end always @(posedge clk) if (rst) begin victim_sel <= #TCQ 'd0; victim_byte_cnt <= #TCQ 'd0; end else if ((~stg1_wr_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_wr_done)) begin victim_sel <= #TCQ prbs_rdlvl_done? wr_victim_sel_ocal: wr_victim_sel; victim_byte_cnt <= #TCQ prbs_rdlvl_done? complex_oclkdelay_calib_cnt:wr_byte_cnt; end else begin if( (init_state_r == INIT_RDLVL_COMPLEX_ACT) || reset_rd_addr) victim_sel <= #TCQ prbs_rdlvl_done? complex_ocal_rd_victim_sel:rd_victim_sel; victim_byte_cnt <= #TCQ prbs_rdlvl_done? complex_oclkdelay_calib_cnt:pi_stg2_prbs_rdlvl_cnt; end generate if (FIXED_VICTIM == "FALSE") begin: wr_done_victim_rotate always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt < DQ_WIDTH*2-1) && ~prbs_rdlvl_done) || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done || prbs_rdlvl_done_pulse) begin complex_row0_wr_done <= #TCQ 1'b0; end else if ( rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd2)) begin complex_row0_wr_done <= #TCQ 1'b1; end always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt < DQ_WIDTH*2-1) && ~prbs_rdlvl_done) || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done || prbs_rdlvl_done_pulse) begin complex_row1_wr_done <= #TCQ 1'b0; end else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2)) begin complex_row1_wr_done <= #TCQ 1'b1; end end else begin: wr_done_victim_fixed always @(posedge clk) if (rst || prbs_rdlvl_done_pulse || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done ) begin complex_row0_wr_done <= #TCQ 1'b0; end else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd2)) begin complex_row0_wr_done <= #TCQ 1'b1; end always @(posedge clk) if (rst || prbs_rdlvl_done_pulse || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done ) begin complex_row1_wr_done <= #TCQ 1'b0; end else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2)) begin complex_row1_wr_done <= #TCQ 1'b1; end end endgenerate always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row0_rd_done <= #TCQ 1'b0; else if (complex_sample_cnt_inc) complex_row0_rd_done <= #TCQ 1'b0; else if ( (prbs_rdlvl_start || complex_oclkdelay_calib_start_int) && (stg1_wr_rd_cnt == 9'd2) && complex_row0_wr_done && complex_row1_wr_done) complex_row0_rd_done <= #TCQ 1'b1; always @(posedge clk) complex_row0_rd_done_r1 <= #TCQ complex_row0_rd_done; always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row1_rd_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE)) complex_row1_rd_done <= #TCQ 1'b0; else if (complex_row0_rd_done && (stg1_wr_rd_cnt == 9'd2)) complex_row1_rd_done <= #TCQ 1'b1; always @(posedge clk) complex_row1_rd_done_r1 <= #TCQ complex_row1_rd_done; //calculate row rd num for complex_oclkdelay_calib //once it reached to 8 always @ (posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row1_rd_cnt <= #TCQ 'd0; else complex_row1_rd_cnt <= #TCQ (complex_row1_rd_done & ~complex_row1_rd_done_r1) ? ((complex_row1_rd_cnt == (COMPLEX_RD-1))? 0:complex_row1_rd_cnt + 'd1) : complex_row1_rd_cnt; //For write, reset rd_done for the byte always @ (posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_STG1_WRITE) || prbs_rdlvl_done_pulse) complex_byte_rd_done <= #TCQ 'b0; else if (prbs_rdlvl_done && (complex_row1_rd_cnt == (COMPLEX_RD-1)) && (complex_row1_rd_done & ~complex_row1_rd_done_r1)) complex_byte_rd_done <= #TCQ 'b1; end always @ (posedge clk) begin complex_byte_rd_done_r1 <= #TCQ complex_byte_rd_done; complex_ocal_num_samples_inc <= #TCQ (complex_byte_rd_done & ~complex_byte_rd_done_r1); end generate if (RANKS < 2) begin: one_rank_complex always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || ( complex_oclkdelay_calib_done && (init_state_r == INIT_RDLVL_STG1_WRITE )) || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT) || prbs_rdlvl_done_pulse ) complex_wr_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; else if ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; end else begin: dual_rank_complex always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || ( complex_oclkdelay_calib_done && (init_state_r == INIT_RDLVL_STG1_WRITE )) || (rdlvl_stg1_rank_done ) || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT) || prbs_rdlvl_done_pulse ) complex_wr_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; else if ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst) complex_wait_cnt <= #TCQ 'd0; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && complex_wait_cnt < 'd15) complex_wait_cnt <= #TCQ complex_wait_cnt + 1; else complex_wait_cnt <= #TCQ 'd0; always @(posedge clk) if (rst) begin complex_num_reads <= #TCQ 'd1; end else if ((((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd14)) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && ext_int_ref_req && (cnt_cmd_r == 'd127))) && ~complex_row0_rd_done) begin if (stg1_wr_rd_cnt > 'd85) begin if (complex_num_reads < 'd6) complex_num_reads <= #TCQ complex_num_reads + 1; else complex_num_reads <= #TCQ 'd1; // Initila value for VCCAUX pattern is 3, 7, and 12 end else if (stg1_wr_rd_cnt > 'd73) begin if (stg1_wr_rd_cnt == 'd85) complex_num_reads <= #TCQ 'd3; else if (complex_num_reads < 'd5) complex_num_reads <= #TCQ complex_num_reads + 1; end else if (stg1_wr_rd_cnt > 'd39) begin if (stg1_wr_rd_cnt == 'd73) complex_num_reads <= #TCQ 'd7; else if (complex_num_reads < 'd10) complex_num_reads <= #TCQ complex_num_reads + 1; end else begin if (stg1_wr_rd_cnt == 'd39) complex_num_reads <= #TCQ 'd12; else if (complex_num_reads < 'd14) complex_num_reads <= #TCQ complex_num_reads + 1; end // Initialize to 1 at the start of reads or after precharge and activate end else if ((((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && ~ext_int_ref_req) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && (stg1_wr_rd_cnt == 'd22))) complex_num_reads <= #TCQ 'd1; always @(posedge clk) if (rst) complex_num_reads_dec <= #TCQ 'd1; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) complex_num_reads_dec <= #TCQ complex_num_reads; else if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (complex_num_reads_dec > 'd0)) complex_num_reads_dec <= #TCQ complex_num_reads_dec - 1; always @(posedge clk) if (rst) complex_address <= #TCQ 'd0; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ_WAIT)) || ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (init_state_r1 != INIT_OCAL_COMPLEX_WRITE_WAIT))) complex_address <= #TCQ phy_address[COL_WIDTH-1:0]; always @ (posedge clk) if (rst) complex_oclkdelay_calib_start_int <= #TCQ 'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && prbs_last_byte_done_r) // changed for new algo 3/26 complex_oclkdelay_calib_start_int <= #TCQ 'b1; always @(posedge clk) begin complex_oclkdelay_calib_start_r1 <= #TCQ complex_oclkdelay_calib_start_int; complex_oclkdelay_calib_start_r2 <= #TCQ complex_oclkdelay_calib_start_r1; end always @ (posedge clk) if (rst) complex_oclkdelay_calib_start <= #TCQ 'b0; else if (complex_oclkdelay_calib_start_int && (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT) && prbs_rdlvl_done) // changed for new algo 3/26 complex_oclkdelay_calib_start <= #TCQ 'b1; //packet fragmentation for complex oclkdealy calib write always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) begin complex_num_writes <= #TCQ 'd1; end else if ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14) && ~complex_row0_wr_done) begin if (stg1_wr_rd_cnt > 'd85) begin if (complex_num_writes < 'd6) complex_num_writes <= #TCQ complex_num_writes + 1; else complex_num_writes <= #TCQ 'd1; // Initila value for VCCAUX pattern is 3, 7, and 12 end else if (stg1_wr_rd_cnt > 'd73) begin if (stg1_wr_rd_cnt == 'd85) complex_num_writes <= #TCQ 'd3; else if (complex_num_writes < 'd5) complex_num_writes <= #TCQ complex_num_writes + 1; end else if (stg1_wr_rd_cnt > 'd39) begin if (stg1_wr_rd_cnt == 'd73) complex_num_writes <= #TCQ 'd7; else if (complex_num_writes < 'd10) complex_num_writes <= #TCQ complex_num_writes + 1; end else begin if (stg1_wr_rd_cnt == 'd39) complex_num_writes <= #TCQ 'd12; else if (complex_num_writes < 'd14) complex_num_writes <= #TCQ complex_num_writes + 1; end // Initialize to 1 at the start of write or after precharge and activate end else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row0_wr_done) complex_num_writes <= #TCQ 'd30; else if (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) complex_num_writes <= #TCQ 'd1; always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_num_writes_dec <= #TCQ 'd1; else if (((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) complex_num_writes_dec <= #TCQ complex_num_writes; else if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (complex_num_writes_dec > 'd0)) complex_num_writes_dec <= #TCQ complex_num_writes_dec - 1; always @(posedge clk) if (rst) complex_sample_cnt_inc_ocal <= #TCQ 1'b0; else if ((stg1_wr_rd_cnt == 9'd1) && complex_byte_rd_done && prbs_rdlvl_done) complex_sample_cnt_inc_ocal <= #TCQ 1'b1; else complex_sample_cnt_inc_ocal <= #TCQ 1'b0; always @(posedge clk) if (rst) complex_sample_cnt_inc <= #TCQ 1'b0; else if ((stg1_wr_rd_cnt == 9'd1) && complex_row1_rd_done) complex_sample_cnt_inc <= #TCQ 1'b1; else complex_sample_cnt_inc <= #TCQ 1'b0; always @(posedge clk) begin complex_sample_cnt_inc_r1 <= #TCQ complex_sample_cnt_inc; complex_sample_cnt_inc_r2 <= #TCQ complex_sample_cnt_inc_r1; end //complex refresh req always @ (posedge clk) begin if(rst || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_ACT)) ) complex_ocal_ref_done <= #TCQ 1'b1; else if (init_state_r == INIT_RDLVL_STG1_WRITE) complex_ocal_ref_done <= #TCQ 1'b0; end //complex ocal odt extention always @(posedge clk) if (rst) complex_ocal_odt_ext <= #TCQ 1'b0; else if (((init_state_r == INIT_PRECHARGE_PREWAIT) && cnt_cmd_done_m7_r) || (init_state_r == INIT_OCLKDELAY_READ_WAIT)) complex_ocal_odt_ext <= #TCQ 1'b0; else if ((init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT)) complex_ocal_odt_ext <= #TCQ 1'b1; // OCLKDELAY calibration requires multiple writes because // write can be up to 2 cycles early since OCLKDELAY tap // can go down to 0 always @(posedge clk) if (rst || (init_state_r == INIT_OCLKDELAY_WRITE_WAIT) || (oclk_wr_cnt == 4'd0)) oclk_wr_cnt <= #TCQ NUM_STG1_WR_RD; else if ((init_state_r == INIT_OCLKDELAY_WRITE) && new_burst_r && ~phy_data_full) oclk_wr_cnt <= #TCQ oclk_wr_cnt - 1; // Write calibration requires multiple writes because // write can be up to 2 cycles early due to new write // leveling algorithm to avoid late writes always @(posedge clk) if (rst || (init_state_r == INIT_WRCAL_WRITE_READ) || (wrcal_wr_cnt == 4'd0)) wrcal_wr_cnt <= #TCQ NUM_STG1_WR_RD; else if ((init_state_r == INIT_WRCAL_WRITE) && new_burst_r && ~phy_data_full) wrcal_wr_cnt <= #TCQ wrcal_wr_cnt - 1; generate if(nCK_PER_CLK == 4) begin:back_to_back_reads_4_1 // 4 back-to-back reads with gaps for // read data_offset calibration (rdlvl stage 2) always @(posedge clk) if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) num_reads <= #TCQ 3'b000; else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) num_reads <= #TCQ num_reads - 1; else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || phy_cmd_full && new_burst_r) num_reads <= #TCQ 3'b011; end else if(nCK_PER_CLK == 2) begin: back_to_back_reads_2_1 // 4 back-to-back reads with gaps for // read data_offset calibration (rdlvl stage 2) always @(posedge clk) if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) num_reads <= #TCQ 3'b000; else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) num_reads <= #TCQ num_reads - 1; else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || phy_cmd_full && new_burst_r) num_reads <= #TCQ 3'b111; end endgenerate // back-to-back reads during write calibration always @(posedge clk) if (rst ||(init_state_r == INIT_WRCAL_READ_WAIT)) wrcal_reads <= #TCQ 2'b00; else if ((wrcal_reads > 2'b00) && ~(phy_ctl_full || phy_cmd_full)) wrcal_reads <= #TCQ wrcal_reads - 1; else if ((init_state_r == INIT_WRCAL_MULT_READS) || phy_ctl_full || phy_cmd_full && new_burst_r) wrcal_reads <= #TCQ 'd255; // determine how often to issue row command during read leveling writes // and reads always @(posedge clk) if (rdlvl_wr_rd) begin // 2:1 mode - every other command issued is a data command // 4:1 mode - every command issued is a data command if (nCK_PER_CLK == 2) begin if (!phy_ctl_full) new_burst_r <= #TCQ ~new_burst_r; end else new_burst_r <= #TCQ 1'b1; end else new_burst_r <= #TCQ 1'b1; // indicate when a write is occurring. PHY_WRDATA_EN must be asserted // simultaneous with the corresponding command/address for CWL = 5,6 always @(posedge clk) begin rdlvl_wr_r <= #TCQ rdlvl_wr; calib_wrdata_en <= #TCQ phy_wrdata_en; end always @(posedge clk) begin if (rst || wrcal_done) extend_cal_pat <= #TCQ 1'b0; else if (temp_lmr_done && (PRE_REV3ES == "ON")) extend_cal_pat <= #TCQ 1'b1; end generate if ((nCK_PER_CLK == 4) || (BURST_MODE == "4")) begin: wrdqen_div4 // Write data enable asserted for one DIV4 clock cycle // Only BL8 supported with DIV4. DDR2 BL4 will use DIV2. always @(*) begin if (~phy_data_full && ((init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_WRCAL_WRITE))) phy_wrdata_en = 1'b1; else phy_wrdata_en = 1'b0; end end else begin: wrdqen_div2 // block: wrdqen_div4 always @(*) if((rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full) | phy_wrdata_en_r1) phy_wrdata_en = 1'b1; else phy_wrdata_en = 1'b0; always @(posedge clk) phy_wrdata_en_r1 <= #TCQ rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full; always @(posedge clk) begin if (!phy_wrdata_en & first_rdlvl_pat_r) wrdata_pat_cnt <= #TCQ 2'b00; else if (wrdata_pat_cnt == 2'b11) wrdata_pat_cnt <= #TCQ 2'b10; else wrdata_pat_cnt <= #TCQ wrdata_pat_cnt + 1; end always @(posedge clk) begin if (!phy_wrdata_en & first_wrcal_pat_r) wrcal_pat_cnt <= #TCQ 2'b00; else if (extend_cal_pat && (wrcal_pat_cnt == 2'b01)) wrcal_pat_cnt <= #TCQ 2'b00; else if (wrcal_pat_cnt == 2'b11) wrcal_pat_cnt <= #TCQ 2'b10; else wrcal_pat_cnt <= #TCQ wrcal_pat_cnt + 1; end end endgenerate // indicate when a write is occurring. PHY_RDDATA_EN must be asserted // simultaneous with the corresponding command/address. PHY_RDDATA_EN // is used during read-leveling to determine read latency assign phy_rddata_en = ~phy_if_empty; // Read data valid generation for MC and User Interface after calibration is // complete assign phy_rddata_valid = init_complete_r1_timing ? phy_rddata_en : 1'b0; //*************************************************************************** // Generate training data written at start of each read-leveling stage // For every stage of read leveling, 8 words are written into memory // The format is as follows (shown as {rise,fall}): // Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0 // Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 //*************************************************************************** always @(posedge clk) if ((init_state_r == INIT_IDLE) || (init_state_r == INIT_RDLVL_STG1_WRITE)) cnt_init_data_r <= #TCQ 2'b00; else if (phy_wrdata_en) cnt_init_data_r <= #TCQ cnt_init_data_r + 1; else if (init_state_r == INIT_WRCAL_WRITE) cnt_init_data_r <= #TCQ 2'b10; // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling always @(posedge clk) if (rst || rdlvl_stg1_rank_done) first_rdlvl_pat_r <= #TCQ 1'b1; else if (phy_wrdata_en && (init_state_r == INIT_RDLVL_STG1_WRITE)) first_rdlvl_pat_r <= #TCQ 1'b0; always @(posedge clk) if (rst || wrcal_resume || (init_state_r == INIT_WRCAL_ACT_WAIT)) first_wrcal_pat_r <= #TCQ 1'b1; else if (phy_wrdata_en && (init_state_r == INIT_WRCAL_WRITE)) first_wrcal_pat_r <= #TCQ 1'b0; generate if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 2)) begin: wrdq_div2_2to1_rdlvl_first always @(posedge clk) if (~oclkdelay_calib_done) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}}; else if (!rdlvl_stg1_done) begin // The 16 words for stage 1 write data in 2:1 mode is written // over 4 consecutive controller clock cycles. Note that write // data follows phy_wrdata_en by one clock cycle case (wrdata_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}}, {DQ_WIDTH/4{4'h9}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end endcase end else if (!prbs_rdlvl_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ end else if (!wrcal_done) begin case (wrcal_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h5}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, {DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h4}}}; end endcase end end else if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 4)) begin: wrdq_div2_4to1_rdlvl_first always @(posedge clk) if (~oclkdelay_calib_done) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; else if (!rdlvl_stg1_done && ~phy_data_full) // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling if (first_rdlvl_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; else // For all others, change the first two words written in order // to differentiate the "early write" and "on-time write" // readback patterns during read leveling phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; else if (~(prbs_rdlvl_done || prbs_last_byte_done_r) && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ else if (!wrcal_done) if (first_wrcal_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (nCK_PER_CLK == 4) begin: wrdq_div1_4to1_wrcal_first always @(posedge clk) if ((~oclkdelay_calib_done) && (DRAM_TYPE == "DDR3")) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; else if ((!wrcal_done)&& (DRAM_TYPE == "DDR3")) begin if (extend_cal_pat) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else if (first_wrcal_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (!rdlvl_stg1_done && ~phy_data_full) begin // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling if (first_rdlvl_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; else // For all others, change the first two words written in order // to differentiate the "early write" and "on-time write" // readback patterns during read leveling phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (!prbs_rdlvl_done && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ else if (!complex_oclkdelay_calib_done && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; end else begin: wrdq_div1_2to1_wrcal_first always @(posedge clk) if ((~oclkdelay_calib_done)&& (DRAM_TYPE == "DDR3")) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}}; else if ((!wrcal_done) && (DRAM_TYPE == "DDR3"))begin case (wrcal_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h5}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, {DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h4}}}; end endcase end else if (!rdlvl_stg1_done) begin // The 16 words for stage 1 write data in 2:1 mode is written // over 4 consecutive controller clock cycles. Note that write // data follows phy_wrdata_en by one clock cycle case (wrdata_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}}, {DQ_WIDTH/4{4'h9}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end endcase end else if (!prbs_rdlvl_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ end else if (!complex_oclkdelay_calib_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; end end endgenerate //*************************************************************************** // Memory control/address //*************************************************************************** // Phases [2] and [3] are always deasserted for 4:1 mode generate if (nCK_PER_CLK == 4) begin: gen_div4_ca_tieoff always @(posedge clk) begin phy_ras_n[3:2] <= #TCQ 3'b11; phy_cas_n[3:2] <= #TCQ 3'b11; phy_we_n[3:2] <= #TCQ 3'b11; end end endgenerate // Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging // (4) auto refresh // verilint STARC-2.7.3.3b off generate if (!(CWL_M % 2)) begin: even_cwl always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT))begin phy_ras_n[0] <= #TCQ 1'b0; phy_ras_n[1] <= #TCQ 1'b1; end else begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b1; end end // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command // (3) auto refresh always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_REFRESH) || (rdlvl_wr_rd && new_burst_r))begin phy_cas_n[0] <= #TCQ 1'b0; phy_cas_n[1] <= #TCQ 1'b1; end else begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b1; end end // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only // occur during read leveling), (3) Issuing ZQ Long Calib command, // (4) Precharge always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE)|| (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (rdlvl_wr && new_burst_r))begin phy_we_n[0] <= #TCQ 1'b0; phy_we_n[1] <= #TCQ 1'b1; end else begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b1; end end end else begin: odd_cwl always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_REFRESH))begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b0; end else begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b1; end end // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command // (3) auto refresh always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_REFRESH) || (rdlvl_wr_rd && new_burst_r))begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b0; end else begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b1; end end // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only // occur during read leveling), (3) Issuing ZQ Long Calib command, // (4) Precharge always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE)|| (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (rdlvl_wr && new_burst_r))begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b0; end else begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b1; end end end endgenerate // verilint STARC-2.7.3.3b on // Assign calib_cmd for the command field in PHY_Ctl_Word always @(posedge clk) begin if (wr_level_dqs_asrt) begin // Request to toggle DQS during write leveling calib_cmd <= #TCQ 3'b001; if (CWL_M % 2) begin // odd write latency calib_data_offset_0 <= #TCQ CWL_M + 3; calib_data_offset_1 <= #TCQ CWL_M + 3; calib_data_offset_2 <= #TCQ CWL_M + 3; calib_cas_slot <= #TCQ 2'b01; end else begin // even write latency calib_data_offset_0 <= #TCQ CWL_M + 2; calib_data_offset_1 <= #TCQ CWL_M + 2; calib_data_offset_2 <= #TCQ CWL_M + 2; calib_cas_slot <= #TCQ 2'b00; end end else if (rdlvl_wr && new_burst_r) begin // Write Command calib_cmd <= #TCQ 3'b001; if (CWL_M % 2) begin // odd write latency calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_cas_slot <= #TCQ 2'b01; end else begin // even write latency calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_cas_slot <= #TCQ 2'b00; end end else if (rdlvl_rd && new_burst_r) begin // Read Command calib_cmd <= #TCQ 3'b011; if (CWL_M % 2) calib_cas_slot <= #TCQ 2'b01; else calib_cas_slot <= #TCQ 2'b00; if (~pi_calib_done_r1) begin calib_data_offset_0 <= #TCQ 6'd0; calib_data_offset_1 <= #TCQ 6'd0; calib_data_offset_2 <= #TCQ 6'd0; end else if (~pi_dqs_found_done_r1) begin calib_data_offset_0 <= #TCQ rd_data_offset_0; calib_data_offset_1 <= #TCQ rd_data_offset_1; calib_data_offset_2 <= #TCQ rd_data_offset_2; end else begin calib_data_offset_0 <= #TCQ rd_data_offset_ranks_0[6*chip_cnt_r+:6]; calib_data_offset_1 <= #TCQ rd_data_offset_ranks_1[6*chip_cnt_r+:6]; calib_data_offset_2 <= #TCQ rd_data_offset_ranks_2[6*chip_cnt_r+:6]; end end else begin // Non-Data Commands like NOP, MRS, ZQ Long Cal, Precharge, // Active, Refresh calib_cmd <= #TCQ 3'b100; calib_data_offset_0 <= #TCQ 6'd0; calib_data_offset_1 <= #TCQ 6'd0; calib_data_offset_2 <= #TCQ 6'd0; if (CWL_M % 2) calib_cas_slot <= #TCQ 2'b01; else calib_cas_slot <= #TCQ 2'b00; end end // Write Enable to PHY_Control FIFO always asserted // No danger of this FIFO being Full with 4:1 sync clock ratio // This is also the write enable to the command OUT_FIFO always @(posedge clk) begin if (rst) begin calib_ctl_wren <= #TCQ 1'b0; calib_cmd_wren <= #TCQ 1'b0; calib_seq <= #TCQ 2'b00; end else if (cnt_pwron_cke_done_r && phy_ctl_ready && ~(phy_ctl_full || phy_cmd_full )) begin calib_ctl_wren <= #TCQ 1'b1; calib_cmd_wren <= #TCQ 1'b1; calib_seq <= #TCQ calib_seq + 1; end else begin calib_ctl_wren <= #TCQ 1'b0; calib_cmd_wren <= #TCQ 1'b0; calib_seq <= #TCQ calib_seq; end end generate genvar rnk_i; for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk always @(posedge clk) begin if (rst) begin mr2_r[rnk_i] <= #TCQ 2'b00; mr1_r[rnk_i] <= #TCQ 3'b000; end else begin mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i]; mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i]; end end end endgenerate // ODT assignment based on slot config and slot present // For single slot systems slot_1_present input will be ignored // Assuming component interfaces to be single slot systems generate if (nSLOTS == 1) begin: gen_single_slot_odt always @(posedge clk) begin if (rst) begin tmp_mr2_r[1] <= #TCQ 2'b00; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; tmp_mr1_r[1] <= #TCQ 3'b000; tmp_mr1_r[2] <= #TCQ 3'b000; tmp_mr1_r[3] <= #TCQ 3'b000; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; phy_tmp_odt_r <= #TCQ 4'b0000; phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; end else begin case ({slot_0_present[0],slot_0_present[1], slot_0_present[2],slot_0_present[3]}) // Single slot configuration with quad rank // Assuming same behavior as single slot dual rank for now // DDR2 does not have quad rank parts 4'b1111: begin if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 RTT_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 RTT_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end phy_tmp_odt_r <= #TCQ 4'b0001; // Chip Select assignments phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) ) +: nCS_PER_RANK] <= #TCQ 'b0; end // Single slot configuration with single rank 4'b1000: begin phy_tmp_odt_r <= #TCQ 4'b0001; if ((REG_CTRL == "ON") && (nCS_PER_RANK > 1)) begin phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0; end else begin phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; end if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && ((cnt_init_mr_r == 2'd0) || (USE_ODT_PORT == 1)))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 RTT_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 RTT_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Single slot configuration with dual rank 4'b1100: begin phy_tmp_odt_r <= #TCQ 4'b0001; // Chip Select assignments phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) ) +: nCS_PER_RANK] <= #TCQ 'b0; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end default: begin phy_tmp_odt_r <= #TCQ 4'b0001; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end endcase end end end else if (nSLOTS == 2) begin: gen_dual_slot_odt always @ (posedge clk) begin if (rst) begin tmp_mr2_r[1] <= #TCQ 2'b00; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; tmp_mr1_r[1] <= #TCQ 3'b000; tmp_mr1_r[2] <= #TCQ 3'b000; tmp_mr1_r[3] <= #TCQ 3'b000; phy_tmp_odt_r <= #TCQ 4'b0000; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; end else begin case ({slot_0_present[0],slot_0_present[1], slot_1_present[0],slot_1_present[1]}) // Two slot configuration, one slot present, single rank 4'b10_00: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end 4'b00_10: begin //Rank1 ODT enabled if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank1 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank1 Rtt_NOM defaults to 120 ohms tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Two slot configuration, one slot present, dual rank 4'b00_11: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end 4'b11_00: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank1 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Two slot configuration, one rank per slot 4'b10_10: begin if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r == 2'b00)begin phy_tmp_odt_r <= #TCQ 4'b0010; //bit0 for rank0 end else begin phy_tmp_odt_r <= #TCQ 4'b0001; //bit0 for rank0 end end else begin if((init_state_r == INIT_WRLVL_WAIT) || (init_next_state == INIT_RDLVL_STG1_WRITE) || (init_next_state == INIT_WRCAL_WRITE) || (init_next_state == INIT_OCAL_CENTER_WRITE) || (init_next_state == INIT_OCLKDELAY_WRITE)) phy_tmp_odt_r <= #TCQ 4'b0011; // bit0 for rank0/1 (write) else if ((init_next_state == INIT_PI_PHASELOCK_READS) || (init_next_state == INIT_MPR_READ) || (init_next_state == INIT_RDLVL_STG1_READ) || (init_next_state == INIT_RDLVL_COMPLEX_READ) || (init_next_state == INIT_RDLVL_STG2_READ) || (init_next_state == INIT_OCLKDELAY_READ) || (init_next_state == INIT_WRCAL_READ) || (init_next_state == INIT_WRCAL_MULT_READS)) phy_tmp_odt_r <= #TCQ 4'b0010; // bit0 for rank1 (rank 0 rd) end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_WR == "60") ? 3'b001 : (RTT_WR == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; end end // Two Slots - One slot with dual rank and other with single rank 4'b10_11: begin //Rank3 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[1] <= #TCQ 3'b000; end //Slot1 Rank1 or Rank3 is being written if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r == 2'b00)begin phy_tmp_odt_r <= #TCQ 4'b0010; end else begin phy_tmp_odt_r <= #TCQ 4'b0001; end end else begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0011; //Slot0 Rank0 is being written end else begin phy_tmp_odt_r <= #TCQ 4'b0101; // ODT for ranks 0 and 2 aserted end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))begin if (chip_cnt_r == 2'b00) begin phy_tmp_odt_r <= #TCQ 4'b0100; end else begin phy_tmp_odt_r <= #TCQ 4'b0001; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end // Two Slots - One slot with dual rank and other with single rank 4'b11_10: begin //Rank2 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : (RTT_NOM2 == "120") ? 3'b010 : (RTT_NOM2 == "20") ? 3'b100 : (RTT_NOM2 == "30") ? 3'b101 : (RTT_NOM2 == "40") ? 3'b011: 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011: 3'b000; //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r[1] == 1'b1)begin phy_tmp_odt_r <= #TCQ 4'b0001; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; // rank 2 ODT asserted end end else begin if (// wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin if (chip_cnt_r[1] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0110; end else begin phy_tmp_odt_r <= #TCQ 4'b0101; end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS)) begin if (chip_cnt_r[1] == 1'b1) begin phy_tmp_odt_r[(1*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ 4'b0010; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end // Two Slots - two ranks per slot 4'b11_11: begin //Rank2 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : (RTT_NOM2 == "120") ? 3'b010 : (RTT_NOM2 == "20") ? 3'b100 : (RTT_NOM2 == "30") ? 3'b101 : (RTT_NOM2 == "40") ? 3'b011 : 3'b000; //Rank3 Rtt_NOM tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 : (RTT_NOM3 == "120") ? 3'b010 : (RTT_NOM3 == "20") ? 3'b100 : (RTT_NOM3 == "30") ? 3'b101 : (RTT_NOM3 == "40") ? 3'b011 : 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[1] <= #TCQ 3'b000; //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r[1] == 1'b1)begin phy_tmp_odt_r <= #TCQ 4'b0001; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; end end else begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin //Slot1 Rank1 or Rank3 is being written if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0110; //Slot0 Rank0 or Rank2 is being written end else begin phy_tmp_odt_r <= #TCQ 4'b1001; end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))begin //Slot1 Rank1 or Rank3 is being read if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0100; //Slot0 Rank0 or Rank2 is being read end else begin phy_tmp_odt_r <= #TCQ 4'b1000; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end default: begin phy_tmp_odt_r <= #TCQ 4'b1111; // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "60") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; end end endcase end end end endgenerate // PHY only supports two ranks. // calib_aux_out[0] is CKE for rank 0 and calib_aux_out[1] is ODT for rank 0 // calib_aux_out[2] is CKE for rank 1 and calib_aux_out[3] is ODT for rank 1 generate if(CKE_ODT_AUX == "FALSE") begin if ((nSLOTS == 1) && (RANKS < 2)) begin always @(posedge clk) if (rst) begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || wrlvl_rank_done || wrlvl_rank_done_r1 || (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt ) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || complex_odt_ext || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_OCAL_CENTER_WRITE) || complex_ocal_odt_ext || (init_state_r == INIT_OCLKDELAY_WRITE)|| (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin // Quad rank in a single slot calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end end end else if ((nSLOTS == 1) && (RANKS <= 2)) begin always @(posedge clk) if (rst) begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt)|| (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || complex_odt_ext || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_OCAL_CENTER_WRITE) || complex_ocal_odt_ext || (init_state_r == INIT_OCLKDELAY_WRITE)|| (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin // Dual rank in a single slot calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end end end else if ((nSLOTS == 2) && (RANKS == 2)) begin always @(posedge clk) if (rst)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if (((DRAM_TYPE == "DDR2") && (RTT_NOM == "DISABLED")) || ((DRAM_TYPE == "DDR3") && (RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // Quad rank in a single slot if (nCK_PER_CLK == 2) begin calib_odt[0] <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; calib_odt[1] <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end // Turn on for idle rank during read if dynamic ODT is enabled in DDR3 end else if(((DRAM_TYPE == "DDR3") && (RTT_WR != "OFF")) && ((init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_MPR_READ) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))) begin if (nCK_PER_CLK == 2) begin calib_odt[0] <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; calib_odt[1] <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end // disable well before next command and before disabling write leveling end else if(cnt_cmd_done_m7_r || (init_state_r == INIT_WRLVL_WAIT && ~wrlvl_odt)) calib_odt <= #TCQ 2'b00; end end end else begin//USE AUX OUTPUT for routing CKE and ODT. if ((nSLOTS == 1) && (RANKS < 2)) begin always @(posedge clk) if (rst) begin calib_aux_out <= #TCQ 4'b0000; end else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done || wrlvl_rank_done_r1 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Quad rank in a single slot calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end else if ((nSLOTS == 1) && (RANKS <= 2)) begin always @(posedge clk) if (rst) begin calib_aux_out <= #TCQ 4'b0000; end else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Dual rank in a single slot calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end else if ((nSLOTS == 2) && (RANKS == 2)) begin always @(posedge clk) if (rst) calib_aux_out <= #TCQ 4'b0000; else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Quad rank in a single slot if (nCK_PER_CLK == 2) begin calib_aux_out[1] <= #TCQ (!calib_aux_out[1]) ? phy_tmp_odt_r[0] : 1'b0; calib_aux_out[3] <= #TCQ (!calib_aux_out[3]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end end endgenerate //***************************************************************** // memory address during init //***************************************************************** always @(posedge clk) phy_data_full_r <= #TCQ phy_data_full; // verilint STARC-2.7.3.3b off always @(*)begin // Bus 0 for address/bank never used address_w = 'b0; bank_w = 'b0; if ((init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_DDR2_PRECHARGE)) begin // Set A10=1 for ZQ long calibration or Precharge All address_w = 'b0; address_w[10] = 1'b1; bank_w = 'b0; end else if (init_state_r == INIT_WRLVL_START) begin // Enable wrlvl in MR1 bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; address_w[7] = 1'b1; end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin // Finished with write leveling, disable wrlvl in MR1 // For single rank disable Rtt_Nom bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin // Set RTT_WR in MR2 after write leveling disabled bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; address_w[10:9] = mr2_r[chip_cnt_r]; end else if (init_state_r == INIT_MPR_READ) begin address_w = 'b0; bank_w = 'b0; end else if (init_state_r == INIT_MPR_RDEN) begin // Enable MPR read with LMR3 and A2=1 bank_w[BANK_WIDTH-1:0] = 'd3; address_w = {ROW_WIDTH{1'b0}}; address_w[2] = 1'b1; end else if (init_state_r == INIT_MPR_DISABLE) begin // Disable MPR read with LMR3 and A2=0 bank_w[BANK_WIDTH-1:0] = 'd3; address_w = {ROW_WIDTH{1'b0}}; end else if ((init_state_r == INIT_REG_WRITE)& (DRAM_TYPE == "DDR3"))begin // bank_w is assigned a 3 bit value. In some // DDR2 cases there will be only two bank bits. //Qualifying the condition with DDR3 bank_w = 'b0; address_w = 'b0; case (reg_ctrl_cnt_r) 4'h1:begin address_w[4:0] = REG_RC1[4:0]; bank_w = REG_RC1[7:5]; end 4'h2: address_w[4:0] = REG_RC2[4:0]; 4'h3: begin address_w[4:0] = REG_RC3[4:0]; bank_w = REG_RC3[7:5]; end 4'h4: begin address_w[4:0] = REG_RC4[4:0]; bank_w = REG_RC4[7:5]; end 4'h5: begin address_w[4:0] = REG_RC5[4:0]; bank_w = REG_RC5[7:5]; end 4'h6: begin address_w[4:0] = REG_RC10[4:0]; bank_w = REG_RC10[7:5]; end 4'h7: begin address_w[4:0] = REG_RC11[4:0]; bank_w = REG_RC11[7:5]; end default: address_w[4:0] = REG_RC0[4:0]; endcase end else if (init_state_r == INIT_LOAD_MR) begin // If loading mode register, look at cnt_init_mr to determine // which MR is currently being programmed address_w = 'b0; bank_w = 'b0; if(DRAM_TYPE == "DDR3")begin if(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done)begin // end of the calibration programming correct // burst length if (TEST_AL == "0") begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //Don't reset DLL end else begin // programming correct AL value bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; if (TEST_AL == "CL-1") address_w[4:3]= 2'b01; // AL="CL-1" else address_w[4:3]= 2'b10; // AL="CL-2" end end else begin case (cnt_init_mr_r) INIT_CNT_MR2: begin bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; address_w[10:9] = mr2_r[chip_cnt_r]; end INIT_CNT_MR3: begin bank_w[1:0] = 2'b11; address_w = load_mr3[ROW_WIDTH-1:0]; end INIT_CNT_MR1: begin bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; end INIT_CNT_MR0: begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; // fixing it to BL8 for calibration address_w[1:0] = 2'b00; end default: begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end endcase end end else begin // DDR2 case (cnt_init_mr_r) INIT_CNT_MR2: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //MRS command without resetting DLL end end INIT_CNT_MR3: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b11; address_w = load_mr3[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //MRS command without resetting DLL. Repeted again // because there is an extra state. end end INIT_CNT_MR1: begin bank_w[1:0] = 2'b01; if(~ddr2_refresh_flag_r)begin address_w = load_mr1[ROW_WIDTH-1:0]; end else begin // second set of lm commands address_w = load_mr1[ROW_WIDTH-1:0]; address_w[9:7] = 3'b111; //OCD default state end end INIT_CNT_MR0: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin // always disable odt for rank 1 and rank 3 as per SPEC address_w[2] = 'b0; address_w[6] = 'b0; end //OCD exit end end default: begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end endcase end end else if ( ~prbs_rdlvl_done && ((init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin // Writing and reading PRBS pattern for read leveling stage 1 // Need to support burst length 4 or 8. PRBS pattern will be // written to entire row and read back from the same row repeatedly bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (((stg1_wr_rd_cnt == NUM_STG1_WR_RD) && ~rdlvl_stg1_done) || (stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd22) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; end else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ) )// || // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; else address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end //need to add address for complex oclkdelay calib end else if (prbs_rdlvl_done && ((init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if ((stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd30) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; end else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (init_state_r1 != INIT_RDLVL_STG1_WRITE) ) // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; else address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end end else if ((init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_READ)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (oclk_wr_cnt == NUM_STG1_WR_RD) address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((oclk_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end else if ((init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_READ)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (wrcal_wr_cnt == NUM_STG1_WR_RD) address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((wrcal_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end else if ((init_state_r == INIT_WRCAL_MULT_READS) || (init_state_r == INIT_RDLVL_STG2_READ)) begin // when writing or reading back training pattern for read leveling stage2 // need to support burst length of 4 or 8. This may mean issuing // multiple commands to cover the entire range of addresses accessed // during read leveling. // Hard coding A[12] to 1 so that it will always be burst length of 8 // for DDR3. Does not have any effect on DDR2. bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; address_w[COL_WIDTH-1:0] = {CALIB_COL_ADD[COL_WIDTH-1:3],burst_addr_r, 3'b000}; address_w[12] = 1'b1; end else if ((init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_OCLKDELAY_ACT)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; //if (stg1_wr_rd_cnt == 'd22) // address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0] + 1; //else address_w = prbs_rdlvl_done ? CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt_ocal : CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt; end else begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end end // verilint STARC-2.7.3.3b on // registring before sending out generate genvar r,s; if ((DRAM_TYPE != "DDR3") || (CA_MIRROR != "ON")) begin: gen_no_mirror for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: div_clk_loop always @(posedge clk) begin phy_address[(r*ROW_WIDTH) +: ROW_WIDTH] <= #TCQ address_w; phy_bank[(r*BANK_WIDTH) +: BANK_WIDTH] <= #TCQ bank_w; end end end else begin: gen_mirror // Control/addressing mirroring (optional for DDR3 dual rank DIMMs) // Mirror for the 2nd rank only. Logic needs to be enhanced to account // for multiple slots, currently only supports one slot, 2-rank config for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_ba_div_clk_loop for (s = 0; s < BANK_WIDTH; s = s + 1) begin: gen_ba always @(posedge clk) if (chip_cnt_r == 2'b00) begin phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[s]; end else begin phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[(s == 0) ? 1 : ((s == 1) ? 0 : s)]; end end end for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_addr_div_clk_loop for (s = 0; s < ROW_WIDTH; s = s + 1) begin: gen_addr always @(posedge clk) if (chip_cnt_r == 2'b00) begin phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[s]; end else begin phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[ (s == 3) ? 4 : ((s == 4) ? 3 : ((s == 5) ? 6 : ((s == 6) ? 5 : ((s == 7) ? 8 : ((s == 8) ? 7 : s)))))]; end end end end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_init.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Memory initialization and overall master state control during // initialization and calibration. Specifically, the following functions // are performed: // 1. Memory initialization (initial AR, mode register programming, etc.) // 2. Initiating write leveling // 3. Generate training pattern writes for read leveling. Generate // memory readback for read leveling. // This module has an interface for providing control/address and write // data to the PHY Control Block during initialization/calibration. // Once initialization and calibration are complete, control is passed to the MC. // //Reference: //Revision History: // //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_init.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ **$Date: 2011/06/02 08:35:09 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_init.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_init # ( parameter tCK = 1500, // DDRx SDRAM clock period parameter TCQ = 100, parameter nCK_PER_CLK = 4, // # of memory clocks per CLK parameter CLK_PERIOD = 3000, // Logic (internal) clk period (in ps) parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA // 1 - ODT output from FPGA parameter DDR3_VDD_OP_VOLT = "150", // Voltage mode used for DDR3 // 150 - 1.50 V // 135 - 1.35 V // 125 - 1.25 V parameter VREF = "EXTERNAL", // Internal or external Vref parameter PRBS_WIDTH = 8, // PRBS sequence = 2^PRBS_WIDTH parameter BANK_WIDTH = 2, parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank parameter COL_WIDTH = 10, parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for // component I/F with CS_WIDTH=1, // nCS_PER_RANK=# of components parameter DQ_WIDTH = 64, parameter DQS_WIDTH = 8, parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter ROW_WIDTH = 14, parameter CS_WIDTH = 1, parameter RANKS = 1, // # of memory ranks in the interface parameter CKE_WIDTH = 1, // # of cke outputs parameter DRAM_TYPE = "DDR3", parameter REG_CTRL = "ON", parameter ADDR_CMD_MODE= "1T", // calibration Address parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address parameter CALIB_COL_ADD = 12'h000, // Calibration column address parameter CALIB_BA_ADD = 3'h0, // Calibration bank address // DRAM mode settings parameter AL = "0", // Additive Latency option parameter BURST_MODE = "8", // Burst length parameter BURST_TYPE = "SEQ", // Burst type // parameter nAL = 0, // Additive latency (in clk cyc) parameter nCL = 5, // Read CAS latency (in clk cyc) parameter nCWL = 5, // Write CAS latency (in clk cyc) parameter tRFC = 110000, // Refresh-to-command delay (in ps) parameter REFRESH_TIMER = 1553, // Refresh interval in fabrci cycles between 8 posted refreshes parameter REFRESH_TIMER_WIDTH = 8, parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option parameter RTT_NOM = "60", // Nominal ODT termination value parameter RTT_WR = "60", // Write ODT termination value parameter WRLVL = "ON", // Enable write leveling // parameter PHASE_DETECT = "ON", // Enable read phase detector parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter nSLOTS = 1, // Number of DIMM SLOTs in the system parameter SIM_INIT_OPTION = "NONE", // "NONE", "SKIP_PU_DLY", "SKIP_INIT" parameter SIM_CAL_OPTION = "NONE", // "NONE", "FAST_CAL", "SKIP_CAL" parameter CKE_ODT_AUX = "FALSE", parameter PRE_REV3ES = "OFF", // Enable TG error detection during calibration parameter TEST_AL = "0", // Internal use for ICM verification parameter FIXED_VICTIM = "TRUE", parameter BYPASS_COMPLEX_OCAL = "FALSE" ) ( input clk, input rst, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o, input delay_incdec_done, input ck_addr_cmd_delay_done, input pi_phase_locked_all, input pi_dqs_found_done, input dqsfound_retry, input dqs_found_prech_req, output reg pi_phaselock_start, output pi_phase_locked_err, output pi_calib_done, input phy_if_empty, // Read/write calibration interface input wrlvl_done, input wrlvl_rank_done, input wrlvl_byte_done, input wrlvl_byte_redo, input wrlvl_final, output reg wrlvl_final_if_rst, input oclkdelay_calib_done, input oclk_prech_req, input oclk_calib_resume, input lim_done, input lim_wr_req, output reg oclkdelay_calib_start, //complex oclkdelay calibration input complex_oclkdelay_calib_done, input complex_oclk_prech_req, input complex_oclk_calib_resume, output reg complex_oclkdelay_calib_start, input [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt, // same as oclkdelay_calib_cnt output reg complex_ocal_num_samples_inc, input complex_ocal_num_samples_done_r, input [2:0] complex_ocal_rd_victim_sel, output reg complex_ocal_reset_rd_addr, input complex_ocal_ref_req, output reg complex_ocal_ref_done, input done_dqs_tap_inc, input [5:0] rd_data_offset_0, input [5:0] rd_data_offset_1, input [5:0] rd_data_offset_2, input [6*RANKS-1:0] rd_data_offset_ranks_0, input [6*RANKS-1:0] rd_data_offset_ranks_1, input [6*RANKS-1:0] rd_data_offset_ranks_2, input pi_dqs_found_rank_done, input wrcal_done, input wrcal_prech_req, input wrcal_read_req, input wrcal_act_req, input temp_wrcal_done, input [7:0] slot_0_present, input [7:0] slot_1_present, output reg wl_sm_start, output reg wr_lvl_start, output reg wrcal_start, output reg wrcal_rd_wait, output reg wrcal_sanity_chk, output reg tg_timer_done, output reg no_rst_tg_mc, input rdlvl_stg1_done, input rdlvl_stg1_rank_done, output reg rdlvl_stg1_start, output reg pi_dqs_found_start, output reg detect_pi_found_dqs, // rdlvl stage 1 precharge requested after each DQS input rdlvl_prech_req, input rdlvl_last_byte_done, input wrcal_resume, input wrcal_sanity_chk_done, // MPR read leveling input mpr_rdlvl_done, input mpr_rnk_done, input mpr_last_byte_done, output reg mpr_rdlvl_start, output reg mpr_end_if_reset, // PRBS Read Leveling input prbs_rdlvl_done, input prbs_last_byte_done, input prbs_rdlvl_prech_req, input complex_victim_inc, input [2:0] rd_victim_sel, input [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt, output reg [2:0] victim_sel, output reg [DQS_CNT_WIDTH:0]victim_byte_cnt, output reg prbs_rdlvl_start, output reg prbs_gen_clk_en, output reg prbs_gen_oclk_clk_en, output reg complex_sample_cnt_inc, output reg complex_sample_cnt_inc_ocal, output reg complex_wr_done, // Signals shared btw multiple calibration stages output reg prech_done, // Data select / status output reg init_calib_complete, // Signal to mask memory model error for Invalid latching edge output reg calib_writes, // PHY address/control // 2 commands to PHY Control Block per div 2 clock in 2:1 mode // 4 commands to PHY Control Block per div 4 clock in 4:1 mode output reg [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address, output reg [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank, output reg [nCK_PER_CLK-1:0] phy_ras_n, output reg [nCK_PER_CLK-1:0] phy_cas_n, output reg [nCK_PER_CLK-1:0] phy_we_n, output reg phy_reset_n, output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n, // Hard PHY Interface signals input phy_ctl_ready, input phy_ctl_full, input phy_cmd_full, input phy_data_full, output reg calib_ctl_wren, output reg calib_cmd_wren, output reg [1:0] calib_seq, output reg write_calib, output reg read_calib, // PHY_Ctl_Wd output reg [2:0] calib_cmd, // calib_aux_out used for CKE and ODT output reg [3:0] calib_aux_out, output reg [1:0] calib_odt , output reg [nCK_PER_CLK-1:0] calib_cke , output [1:0] calib_rank_cnt, output reg [1:0] calib_cas_slot, output reg [5:0] calib_data_offset_0, output reg [5:0] calib_data_offset_1, output reg [5:0] calib_data_offset_2, // PHY OUT_FIFO output reg calib_wrdata_en, output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata, // PHY Read output phy_rddata_en, output phy_rddata_valid, output [255:0] dbg_phy_init, input read_pause, input reset_rd_addr, //OCAL centering calibration input oclkdelay_center_calib_start, input oclk_center_write_resume, input oclkdelay_center_calib_done ); //***************************************************************************** // Assertions to be added //***************************************************************************** // The phy_ctl_full signal must never be asserted in synchronous mode of // operation either 4:1 or 2:1 // // The RANKS parameter must never be set to '0' by the user // valid values: 1 to 4 // //***************************************************************************** //*************************************************************************** // Number of Read level stage 1 writes limited to a SDRAM row // The address of Read Level stage 1 reads must also be limited // to a single SDRAM row // (2^COL_WIDTH)/BURST_MODE = (2^10)/8 = 128 localparam NUM_STG1_WR_RD = (BURST_MODE == "8") ? 4 : (BURST_MODE == "4") ? 8 : 4; localparam ADDR_INC = (BURST_MODE == "8") ? 8 : (BURST_MODE == "4") ? 4 : 8; // In a 2 slot dual rank per system RTT_NOM values // for Rank2 and Rank3 default to 40 ohms localparam RTT_NOM2 = "40"; localparam RTT_NOM3 = "40"; localparam RTT_NOM_int = (USE_ODT_PORT == 1) ? RTT_NOM : RTT_WR; // Specifically for use with half-frequency controller (nCK_PER_CLK=2) // = 1 if burst length = 4, = 0 if burst length = 8. Determines how // often row command needs to be issued during read-leveling // For DDR3 the burst length is fixed during calibration localparam BURST4_FLAG = (DRAM_TYPE == "DDR3")? 1'b0 : (BURST_MODE == "8") ? 1'b0 : ((BURST_MODE == "4") ? 1'b1 : 1'b0); //*************************************************************************** // Counter values used to determine bus timing // NOTE on all counter terminal counts - these can/should be one less than // the actual delay to take into account extra clock cycle delay in // generating the corresponding "done" signal //*************************************************************************** localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK; // Calculate initial delay required in number of CLK clock cycles // to delay initially. The counter is clocked by [CLK/1024] - which // is approximately division by 1000 - note that the formulas below will // result in more than the minimum wait time because of this approximation. // NOTE: For DDR3 JEDEC specifies to delay reset // by 200us, and CKE by an additional 500us after power-up // For DDR2 CKE is delayed by 200us after power up. localparam DDR3_RESET_DELAY_NS = 200000; localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS; localparam DDR2_CKE_DELAY_NS = 200000; localparam PWRON_RESET_DELAY_CNT = ((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD); localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == "DDR3") ? (((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) : (((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)); // FOR DDR2 -1 taken out. With -1 not getting 200us. The equation // needs to be reworked. localparam DDR2_INIT_PRE_DELAY_PS = 400000; localparam DDR2_INIT_PRE_CNT = ((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1; // Calculate tXPR time: reset from CKE HIGH to valid command after power-up // tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock // cycles because this counter actually starts up before CKE is asserted // to memory. localparam TXPR_DELAY_CNT = (5*CLK_MEM_PERIOD > tRFC+10000) ? (((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+11 : (((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+11; // tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV localparam TDLLK_TZQINIT_DELAY_CNT = 255; // TWR values in ns. Both DDR2 and DDR3 have the same value. // 15000ns/tCK localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ? (15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD; // time to wait between consecutive commands in PHY_INIT - this is a // generic number, and must be large enough to account for worst case // timing parameter (tRFC - refresh-to-active) across all memory speed // grades and operating frequencies. Expressed in clk // (Divided by 4 or Divided by 2) clock cycles. localparam CNTNEXT_CMD = 7'b1111111; // Counter values to keep track of which MR register to load during init // Set value of INIT_CNT_MR_DONE to equal value of counter for last mode // register configured during initialization. // NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init localparam INIT_CNT_MR2 = 2'b00; localparam INIT_CNT_MR3 = 2'b01; localparam INIT_CNT_MR1 = 2'b10; localparam INIT_CNT_MR0 = 2'b11; localparam INIT_CNT_MR_DONE = 2'b11; // Register chip programmable values for DDR3 // The register chip for the registered DIMM needs to be programmed // before the initialization of the registered DIMM. // Address for the control word is in : DBA2, DA2, DA1, DA0 // Data for the control word is in: DBA1 DBA0, DA4, DA3 // The values will be stored in the local param in the following format // {DBA[2:0], DA[4:0]} // RC0 is global features control word. Address == 000 localparam REG_RC0 = 8'b00000000; // RC1 Clock driver enable control word. Enables or disables the four // output clocks in the register chip. For single rank and dual rank // two clocks will be enabled and for quad rank all the four clocks // will be enabled. Address == 000. Data = 0110 for single and dual rank. // = 0000 for quad rank localparam REG_RC1 = 8'b00000001; // RC2 timing control word. Set in 1T timing mode // Address = 010. Data = 0000 localparam REG_RC2 = 8'b00000010; // RC3 timing control word. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC3 = (RANKS >= 2) ? 8'b00101011 : 8'b00000011; // RC4 timing control work. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC4 = (RANKS >= 2) ? 8'b00101100 : 8'b00000100; // RC5 timing control work. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC5 = (RANKS >= 2) ? 8'b00101101 : 8'b00000101; // RC10 timing control work. Setting the data to 0000 localparam [3:0] FREQUENCY_ENCODING = (tCK >= 1072 && tCK < 1250) ? 4'b0100 : (tCK >= 1250 && tCK < 1500) ? 4'b0011 : (tCK >= 1500 && tCK < 1875) ? 4'b0010 : (tCK >= 1875 && tCK < 2500) ? 4'b0001 : 4'b0000; localparam REG_RC10 = {1'b1,FREQUENCY_ENCODING,3'b010}; localparam VREF_ENCODING = (VREF == "INTERNAL") ? 1'b1 : 1'b0; localparam [3:0] DDR3_VOLTAGE_ENCODING = (DDR3_VDD_OP_VOLT == "125") ? {1'b0,VREF_ENCODING,2'b10} : (DDR3_VDD_OP_VOLT == "135") ? {1'b0,VREF_ENCODING,2'b01} : {1'b0,VREF_ENCODING,2'b00} ; localparam REG_RC11 = {1'b1,DDR3_VOLTAGE_ENCODING,3'b011}; // For non-zero AL values localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; // Adding the register dimm latency to write latency localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; // Count value to generate pi_phase_locked_err signal localparam PHASELOCKED_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 16383 : 1000; // Timeout interval for detecting error with Traffic Generator localparam [13:0] TG_TIMER_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 14'h3FFF : 14'h0001; //bit num per DQS localparam DQ_PER_DQS = DQ_WIDTH/DQS_WIDTH; //COMPLEX_ROW_CNT_BYTE localparam COMPLEX_ROW_CNT_BYTE = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS*2: 2; localparam COMPLEX_RD = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS : 1; // Master state machine encoding localparam INIT_IDLE = 7'b0000000; //0 localparam INIT_WAIT_CKE_EXIT = 7'b0000001; //1 localparam INIT_LOAD_MR = 7'b0000010; //2 localparam INIT_LOAD_MR_WAIT = 7'b0000011; //3 localparam INIT_ZQCL = 7'b0000100; //4 localparam INIT_WAIT_DLLK_ZQINIT = 7'b0000101; //5 localparam INIT_WRLVL_START = 7'b0000110; //6 localparam INIT_WRLVL_WAIT = 7'b0000111; //7 localparam INIT_WRLVL_LOAD_MR = 7'b0001000; //8 localparam INIT_WRLVL_LOAD_MR_WAIT = 7'b0001001; //9 localparam INIT_WRLVL_LOAD_MR2 = 7'b0001010; //A localparam INIT_WRLVL_LOAD_MR2_WAIT = 7'b0001011; //B localparam INIT_RDLVL_ACT = 7'b0001100; //C localparam INIT_RDLVL_ACT_WAIT = 7'b0001101; //D localparam INIT_RDLVL_STG1_WRITE = 7'b0001110; //E localparam INIT_RDLVL_STG1_WRITE_READ = 7'b0001111; //F localparam INIT_RDLVL_STG1_READ = 7'b0010000; //10 localparam INIT_RDLVL_STG2_READ = 7'b0010001; //11 localparam INIT_RDLVL_STG2_READ_WAIT = 7'b0010010; //12 localparam INIT_PRECHARGE_PREWAIT = 7'b0010011; //13 localparam INIT_PRECHARGE = 7'b0010100; //14 localparam INIT_PRECHARGE_WAIT = 7'b0010101; //15 localparam INIT_DONE = 7'b0010110; //16 localparam INIT_DDR2_PRECHARGE = 7'b0010111; //17 localparam INIT_DDR2_PRECHARGE_WAIT = 7'b0011000; //18 localparam INIT_REFRESH = 7'b0011001; //19 localparam INIT_REFRESH_WAIT = 7'b0011010; //1A localparam INIT_REG_WRITE = 7'b0011011; //1B localparam INIT_REG_WRITE_WAIT = 7'b0011100; //1C localparam INIT_DDR2_MULTI_RANK = 7'b0011101; //1D localparam INIT_DDR2_MULTI_RANK_WAIT = 7'b0011110; //1E localparam INIT_WRCAL_ACT = 7'b0011111; //1F localparam INIT_WRCAL_ACT_WAIT = 7'b0100000; //20 localparam INIT_WRCAL_WRITE = 7'b0100001; //21 localparam INIT_WRCAL_WRITE_READ = 7'b0100010; //22 localparam INIT_WRCAL_READ = 7'b0100011; //23 localparam INIT_WRCAL_READ_WAIT = 7'b0100100; //24 localparam INIT_WRCAL_MULT_READS = 7'b0100101; //25 localparam INIT_PI_PHASELOCK_READS = 7'b0100110; //26 localparam INIT_MPR_RDEN = 7'b0100111; //27 localparam INIT_MPR_WAIT = 7'b0101000; //28 localparam INIT_MPR_READ = 7'b0101001; //29 localparam INIT_MPR_DISABLE_PREWAIT = 7'b0101010; //2A localparam INIT_MPR_DISABLE = 7'b0101011; //2B localparam INIT_MPR_DISABLE_WAIT = 7'b0101100; //2C localparam INIT_OCLKDELAY_ACT = 7'b0101101; //2D localparam INIT_OCLKDELAY_ACT_WAIT = 7'b0101110; //2E localparam INIT_OCLKDELAY_WRITE = 7'b0101111; //2F localparam INIT_OCLKDELAY_WRITE_WAIT = 7'b0110000; //30 localparam INIT_OCLKDELAY_READ = 7'b0110001; //31 localparam INIT_OCLKDELAY_READ_WAIT = 7'b0110010; //32 localparam INIT_REFRESH_RNK2_WAIT = 7'b0110011; //33 localparam INIT_RDLVL_COMPLEX_PRECHARGE = 7'b0110100; //34 localparam INIT_RDLVL_COMPLEX_PRECHARGE_WAIT = 7'b0110101; //35 localparam INIT_RDLVL_COMPLEX_ACT = 7'b0110110; //36 localparam INIT_RDLVL_COMPLEX_ACT_WAIT = 7'b0110111; //37 localparam INIT_RDLVL_COMPLEX_READ = 7'b0111000; //38 localparam INIT_RDLVL_COMPLEX_READ_WAIT = 7'b0111001; //39 localparam INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT = 7'b0111010; //3A localparam INIT_OCAL_COMPLEX_ACT = 7'b0111011; //3B localparam INIT_OCAL_COMPLEX_ACT_WAIT = 7'b0111100; //3C localparam INIT_OCAL_COMPLEX_WRITE_WAIT = 7'b0111101; //3D localparam INIT_OCAL_COMPLEX_RESUME_WAIT = 7'b0111110; //3E localparam INIT_OCAL_CENTER_ACT = 7'b0111111; //3F localparam INIT_OCAL_CENTER_WRITE = 7'b1000000; //40 localparam INIT_OCAL_CENTER_WRITE_WAIT = 7'b1000001; //41 localparam INIT_OCAL_CENTER_ACT_WAIT = 7'b1000010; //42 integer i, j, k, l, m, n, p, q; reg pi_dqs_found_all_r; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r1; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r2; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r3; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r4; reg pi_calib_rank_done_r; reg [13:0] pi_phaselock_timer; reg stg1_wr_done; reg rnk_ref_cnt; reg pi_dqs_found_done_r1; reg pi_dqs_found_rank_done_r; reg read_calib_int; reg read_calib_r; reg pi_calib_done_r; reg pi_calib_done_r1; reg burst_addr_r; reg [1:0] chip_cnt_r; reg [6:0] cnt_cmd_r; reg cnt_cmd_done_r; reg cnt_cmd_done_m7_r; reg [7:0] cnt_dllk_zqinit_r; reg cnt_dllk_zqinit_done_r; reg cnt_init_af_done_r; reg [1:0] cnt_init_af_r; reg [1:0] cnt_init_data_r; reg [1:0] cnt_init_mr_r; reg cnt_init_mr_done_r; reg cnt_init_pre_wait_done_r; reg [7:0] cnt_init_pre_wait_r; reg [9:0] cnt_pwron_ce_r; reg cnt_pwron_cke_done_r; reg cnt_pwron_cke_done_r1; reg [8:0] cnt_pwron_r; reg cnt_pwron_reset_done_r; reg cnt_txpr_done_r; reg [7:0] cnt_txpr_r; reg ddr2_pre_flag_r; reg ddr2_refresh_flag_r; reg ddr3_lm_done_r; reg [4:0] enable_wrlvl_cnt; reg init_complete_r; reg init_complete_r1; reg init_complete_r2; (* keep = "true" *) reg init_complete_r_timing; (* keep = "true" *) reg init_complete_r1_timing; reg [6:0] init_next_state; reg [6:0] init_state_r; reg [6:0] init_state_r1; wire [15:0] load_mr0; wire [15:0] load_mr1; wire [15:0] load_mr2; wire [15:0] load_mr3; reg mem_init_done_r; reg [1:0] mr2_r [0:3]; reg [2:0] mr1_r [0:3]; reg new_burst_r; reg [15:0] wrcal_start_dly_r; wire wrcal_start_pre; reg wrcal_resume_r; // Only one ODT signal per rank in PHY Control Block reg [nCK_PER_CLK-1:0] phy_tmp_odt_r; reg [nCK_PER_CLK-1:0] phy_tmp_odt_r1; reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r; reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_int_cs_n; wire prech_done_pre; reg [15:0] prech_done_dly_r; reg prech_pending_r; reg prech_req_posedge_r; reg prech_req_r; reg pwron_ce_r; reg first_rdlvl_pat_r; reg first_wrcal_pat_r; reg phy_wrdata_en; reg phy_wrdata_en_r1; reg [1:0] wrdata_pat_cnt; reg [1:0] wrcal_pat_cnt; reg [ROW_WIDTH-1:0] address_w; reg [BANK_WIDTH-1:0] bank_w; reg rdlvl_stg1_done_r1; reg rdlvl_stg1_start_int; reg [15:0] rdlvl_start_dly0_r; reg rdlvl_start_pre; reg rdlvl_last_byte_done_r; wire rdlvl_rd; wire rdlvl_wr; reg rdlvl_wr_r; wire rdlvl_wr_rd; reg [3:0] reg_ctrl_cnt_r; reg [1:0] tmp_mr2_r [0:3]; reg [2:0] tmp_mr1_r [0:3]; reg wrlvl_done_r; reg wrlvl_done_r1; reg wrlvl_rank_done_r1; reg wrlvl_rank_done_r2; reg wrlvl_rank_done_r3; reg wrlvl_rank_done_r4; reg wrlvl_rank_done_r5; reg wrlvl_rank_done_r6; reg wrlvl_rank_done_r7; reg [2:0] wrlvl_rank_cntr; reg wrlvl_odt_ctl; reg wrlvl_odt; reg wrlvl_active; reg wrlvl_active_r1; reg [2:0] num_reads; reg temp_wrcal_done_r; reg temp_lmr_done; reg extend_cal_pat; reg [13:0] tg_timer; reg tg_timer_go; reg cnt_wrcal_rd; reg [3:0] cnt_wait; reg [7:0] wrcal_reads; reg [8:0] stg1_wr_rd_cnt; reg phy_data_full_r; reg wr_level_dqs_asrt; reg wr_level_dqs_asrt_r1; reg [1:0] dqs_asrt_cnt; reg [3:0] num_refresh; wire oclkdelay_calib_start_pre; reg [15:0] oclkdelay_start_dly_r; reg [3:0] oclk_wr_cnt; reg [3:0] wrcal_wr_cnt; reg wrlvl_final_r; reg prbs_rdlvl_done_r1; reg prbs_rdlvl_done_r2; reg prbs_rdlvl_done_r3; reg prbs_last_byte_done_r; reg phy_if_empty_r; reg prbs_pat_resume_int; reg complex_row0_wr_done; reg complex_row1_wr_done; reg complex_row0_rd_done; reg complex_row1_rd_done; reg complex_row0_rd_done_r1; reg [3:0] complex_wait_cnt; reg [3:0] complex_num_reads; reg [3:0] complex_num_reads_dec; reg [ROW_WIDTH-1:0] complex_address; reg wr_victim_inc; reg [2:0] wr_victim_sel; reg [DQS_CNT_WIDTH:0] wr_byte_cnt; reg [7:0] complex_row_cnt; reg complex_sample_cnt_inc_r1; reg complex_sample_cnt_inc_r2; reg complex_odt_ext; reg complex_ocal_odt_ext; reg wrcal_final_chk; wire prech_req; reg read_pause_r1; reg read_pause_r2; wire read_pause_ext; reg reset_rd_addr_r1; reg complex_rdlvl_int_ref_req; reg ext_int_ref_req; //complex OCLK delay calibration reg [7:0] complex_row_cnt_ocal; reg [4:0] complex_num_writes; reg [4:0] complex_num_writes_dec; reg complex_oclkdelay_calib_start_int; reg complex_oclkdelay_calib_start_r1; reg complex_oclkdelay_calib_start_r2; reg complex_oclkdelay_calib_done_r1; // reg [DQS_CNT_WIDTH:0] wr_byte_cnt_ocal; reg [2:0] wr_victim_sel_ocal; reg complex_row1_rd_done_r1; //time for switch to write reg [2:0] complex_row1_rd_cnt; //row1 read number for the byte (8 (16 rows) row1) reg complex_byte_rd_done; //read for the byte is done reg complex_byte_rd_done_r1; // reg complex_row_change; //every 16 rows of read, it is set to "0" for write reg ocal_num_samples_inc; //1 read/write is done reg complex_ocal_wr_start; //indicate complex ocal write is started. used for prbs rd addr gen reg prbs_rdlvl_done_pulse; //rising edge for prbs_rdlvl_done. used for pipelining reg prech_done_r1, prech_done_r2, prech_done_r3; reg mask_lim_done; reg complex_mask_lim_done; reg oclkdelay_calib_start_int; reg [REFRESH_TIMER_WIDTH-1:0] oclkdelay_ref_cnt; reg oclkdelay_int_ref_req; reg [3:0] ocal_act_wait_cnt; reg oclk_calib_resume_level; reg ocal_last_byte_done; wire mmcm_wr; //MMCM centering write. no CS will be set wire exit_ocal_complex_resume_wait = init_state_r == INIT_OCAL_COMPLEX_RESUME_WAIT && complex_oclk_calib_resume; //*************************************************************************** // Debug //*************************************************************************** //synthesis translate_off always @(posedge mem_init_done_r) begin if (!rst) $display ("PHY_INIT: Memory Initialization completed at %t", $time); end always @(posedge wrlvl_done) begin if (!rst && (WRLVL == "ON")) $display ("PHY_INIT: Write Leveling completed at %t", $time); end always @(posedge rdlvl_stg1_done) begin if (!rst) $display ("PHY_INIT: Read Leveling Stage 1 completed at %t", $time); end always @(posedge mpr_rdlvl_done) begin if (!rst) $display ("PHY_INIT: MPR Read Leveling completed at %t", $time); end always @(posedge oclkdelay_calib_done) begin if (!rst) $display ("PHY_INIT: OCLKDELAY calibration completed at %t", $time); end always @(posedge pi_calib_done_r1) begin if (!rst) $display ("PHY_INIT: Phaser_In Phase Locked at %t", $time); end always @(posedge pi_dqs_found_done) begin if (!rst) $display ("PHY_INIT: Phaser_In DQSFOUND completed at %t", $time); end always @(posedge wrcal_done) begin if (!rst && (WRLVL == "ON")) $display ("PHY_INIT: Write Calibration completed at %t", $time); end always@(posedge prbs_rdlvl_done)begin if(!rst) $display("PHY_INIT : PRBS/PER_BIT calibration completed at %t",$time); end always@(posedge complex_oclkdelay_calib_done)begin if(!rst) $display("PHY_INIT : COMPLEX OCLKDELAY calibration completed at %t",$time); end always@(posedge oclkdelay_center_calib_done)begin if(!rst) $display("PHY_INIT : OCLKDELAY CENTER CALIB calibration completed at %t",$time); end //synthesis translate_on assign dbg_phy_init[5:0] = init_state_r; assign dbg_phy_init[6+:8] = complex_row_cnt; assign dbg_phy_init[14+:3] = victim_sel; assign dbg_phy_init[17+:4] = victim_byte_cnt; assign dbg_phy_init[21+:9] = stg1_wr_rd_cnt[8:0]; assign dbg_phy_init[30+:15] = complex_address; assign dbg_phy_init[(30+15)+:15] = phy_address[14:0]; assign dbg_phy_init[60] =prbs_rdlvl_prech_req ; assign dbg_phy_init[61] =prech_req_posedge_r ; //*************************************************************************** // DQS count to be sent to hard PHY during Phaser_IN Phase Locking stage //*************************************************************************** // assign pi_phaselock_calib_cnt = dqs_cnt_r; assign pi_calib_done = pi_calib_done_r1; assign read_pause_ext = read_pause | read_pause_r2; //detect rising edge of prbs_rdlvl_done to reset all control sighals always @ (posedge clk) begin prbs_rdlvl_done_pulse <= #TCQ prbs_rdlvl_done & ~prbs_rdlvl_done_r1; end always @ (posedge clk) begin read_pause_r1 <= #TCQ read_pause; read_pause_r2 <= #TCQ read_pause_r1; end always @(posedge clk) begin if (rst) wrcal_final_chk <= #TCQ 1'b0; else if ((init_next_state == INIT_WRCAL_ACT) && wrcal_done && (DRAM_TYPE == "DDR3")) wrcal_final_chk <= #TCQ 1'b1; end always @(posedge clk) begin rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done; prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done; prbs_rdlvl_done_r2 <= #TCQ prbs_rdlvl_done_r1; prbs_rdlvl_done_r3 <= #TCQ prbs_rdlvl_done_r2; wrcal_resume_r <= #TCQ wrcal_resume; wrcal_sanity_chk <= #TCQ wrcal_final_chk; end always @(posedge clk) begin if (rst) mpr_end_if_reset <= #TCQ 1'b0; else if (mpr_last_byte_done && (num_refresh != 'd0)) mpr_end_if_reset <= #TCQ 1'b1; else mpr_end_if_reset <= #TCQ 1'b0; end // Siganl to mask memory model error for Invalid latching edge always @(posedge clk) if (rst) calib_writes <= #TCQ 1'b0; else if ((init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ)) calib_writes <= #TCQ 1'b1; else calib_writes <= #TCQ 1'b0; always @(posedge clk) if (rst) wrcal_rd_wait <= #TCQ 1'b0; else if (init_state_r == INIT_WRCAL_READ_WAIT) wrcal_rd_wait <= #TCQ 1'b1; else wrcal_rd_wait <= #TCQ 1'b0; //*************************************************************************** // Signal PHY completion when calibration is finished // Signal assertion is delayed by four clock cycles to account for the // multi cycle path constraint to (phy_init_data_sel) signal. //*************************************************************************** always @(posedge clk) if (rst) begin init_complete_r <= #TCQ 1'b0; init_complete_r_timing <= #TCQ 1'b0; init_complete_r1 <= #TCQ 1'b0; init_complete_r1_timing <= #TCQ 1'b0; init_complete_r2 <= #TCQ 1'b0; init_calib_complete <= #TCQ 1'b0; end else begin if (init_state_r == INIT_DONE) begin init_complete_r <= #TCQ 1'b1; init_complete_r_timing <= #TCQ 1'b1; end init_complete_r1 <= #TCQ init_complete_r; init_complete_r1_timing <= #TCQ init_complete_r_timing; init_complete_r2 <= #TCQ init_complete_r1; init_calib_complete <= #TCQ init_complete_r2; end always @ (posedge clk) if (rst) complex_oclkdelay_calib_done_r1 <= #TCQ 1'b0; else complex_oclkdelay_calib_done_r1 <= #TCQ complex_oclkdelay_calib_done; //reset read address for starting complex ocaldealy calib always @ (posedge clk) begin complex_ocal_reset_rd_addr <= #TCQ ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd9)) || (prbs_last_byte_done && ~prbs_last_byte_done_r); end //first write for complex oclkdealy calib always @ (posedge clk) begin if (rst) complex_ocal_wr_start <= #TCQ 'b0; else complex_ocal_wr_start <= #TCQ complex_ocal_reset_rd_addr? 1'b1 : complex_ocal_wr_start; end //ocal stg3 centering start // always @ (posedge clk) // if(rst) oclkdelay_center_calib_start <= #TCQ 1'b0; // else // oclkdelay_center_calib_start <= #TCQ ((init_state_r == INIT_OCAL_CENTER_ACT) && lim_done)? 1'b1: oclkdelay_center_calib_start; //*************************************************************************** // Instantiate FF for the phy_init_data_sel signal. A multi cycle path // constraint will be assigned to this signal. This signal will only be // used within the PHY //*************************************************************************** // FDRSE u_ff_phy_init_data_sel // ( // .Q (phy_init_data_sel), // .C (clk), // .CE (1'b1), // .D (init_complete_r), // .R (1'b0), // .S (1'b0) // ) /* synthesis syn_preserve=1 */ // /* synthesis syn_replicate = 0 */; //*************************************************************************** // Mode register programming //*************************************************************************** //***************************************************************** // DDR3 Load mode reg0 // Mode Register (MR0): // [15:13] - unused - 000 // [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit), // 1 (DLL maintained) // [11:9] - write recovery for Auto Precharge (tWR/tCK = 6) // [8] - DLL reset - 0 or 1 // [7] - Test Mode - 0 (normal) // [6:4],[2] - CAS latency - CAS_LAT // [3] - Burst Type - BURST_TYPE // [1:0] - Burst Length - BURST_LEN // DDR2 Load mode register // Mode Register (MR): // [15:14] - unused - 00 // [13] - reserved - 0 // [12] - Power-down mode - 0 (normal) // [11:9] - write recovery - write recovery for Auto Precharge // (tWR/tCK = 6) // [8] - DLL reset - 0 or 1 // [7] - Test Mode - 0 (normal) // [6:4] - CAS latency - CAS_LAT // [3] - Burst Type - BURST_TYPE // [2:0] - Burst Length - BURST_LEN //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr0_DDR3 assign load_mr0[1:0] = (BURST_MODE == "8") ? 2'b00 : (BURST_MODE == "OTF") ? 2'b01 : (BURST_MODE == "4") ? 2'b10 : 2'b11; assign load_mr0[2] = (nCL >= 12) ? 1'b1 : 1'b0; // LSb of CAS latency assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; assign load_mr0[6:4] = ((nCL == 5) || (nCL == 13)) ? 3'b001 : ((nCL == 6) || (nCL == 14)) ? 3'b010 : (nCL == 7) ? 3'b011 : (nCL == 8) ? 3'b100 : (nCL == 9) ? 3'b101 : (nCL == 10) ? 3'b110 : (nCL == 11) ? 3'b111 : (nCL == 12) ? 3'b000 : 3'b111; assign load_mr0[7] = 1'b0; assign load_mr0[8] = 1'b1; // Reset DLL (init only) assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 : (TWR_CYC == 6) ? 3'b010 : (TWR_CYC == 7) ? 3'b011 : (TWR_CYC == 8) ? 3'b100 : (TWR_CYC == 9) ? 3'b101 : (TWR_CYC == 10) ? 3'b101 : (TWR_CYC == 11) ? 3'b110 : (TWR_CYC == 12) ? 3'b110 : (TWR_CYC == 13) ? 3'b111 : (TWR_CYC == 14) ? 3'b111 : (TWR_CYC == 15) ? 3'b000 : (TWR_CYC == 16) ? 3'b000 : 3'b010; assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit' assign load_mr0[15:13] = 3'b000; end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr0_DDR2 // block: gen assign load_mr0[2:0] = (BURST_MODE == "8") ? 3'b011 : (BURST_MODE == "4") ? 3'b010 : 3'b111; assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; assign load_mr0[6:4] = (nCL == 3) ? 3'b011 : (nCL == 4) ? 3'b100 : (nCL == 5) ? 3'b101 : (nCL == 6) ? 3'b110 : 3'b111; assign load_mr0[7] = 1'b0; assign load_mr0[8] = 1'b1; // Reset DLL (init only) assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 : (TWR_CYC == 3) ? 3'b010 : (TWR_CYC == 4) ? 3'b011 : (TWR_CYC == 5) ? 3'b100 : (TWR_CYC == 6) ? 3'b101 : 3'b010; assign load_mr0[15:12]= 4'b0000; // Reserved end endgenerate //***************************************************************** // DDR3 Load mode reg1 // Mode Register (MR1): // [15:13] - unused - 00 // [12] - output enable - 0 (enabled for DQ, DQS, DQS#) // [11] - TDQS enable - 0 (TDQS disabled and DM enabled) // [10] - reserved - 0 (must be '0') // [9] - RTT[2] - 0 // [8] - reserved - 0 (must be '0') // [7] - write leveling - 0 (disabled), 1 (enabled) // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) // [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7) // [4:3] - Additive CAS - ADDITIVE_CAS // [2] - RTT[0] // [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7) // [0] - DLL enable - 0 (normal) // DDR2 ext mode register // Extended Mode Register (MR): // [15:14] - unused - 00 // [13] - reserved - 0 // [12] - output enable - 0 (enabled) // [11] - RDQS enable - 0 (disabled) // [10] - DQS# enable - 0 (enabled) // [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init) // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) // [5:3] - Additive CAS - ADDITIVE_CAS // [2] - RTT[0] // [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced) // [0] - DLL enable - 0 (normal) //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr1_DDR3 assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b0 : 1'b1; assign load_mr1[2] = ((RTT_NOM_int == "30") || (RTT_NOM_int == "40") || (RTT_NOM_int == "60")) ? 1'b1 : 1'b0; assign load_mr1[4:3] = (AL == "0") ? 2'b00 : (AL == "CL-1") ? 2'b01 : (AL == "CL-2") ? 2'b10 : 2'b11; assign load_mr1[5] = 1'b0; assign load_mr1[6] = ((RTT_NOM_int == "40") || (RTT_NOM_int == "120")) ? 1'b1 : 1'b0; assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence assign load_mr1[8] = 1'b0; assign load_mr1[9] = ((RTT_NOM_int == "20") || (RTT_NOM_int == "30")) ? 1'b1 : 1'b0; assign load_mr1[10] = 1'b0; assign load_mr1[15:11] = 5'b00000; end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr1_DDR2 assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b1 : 1'b0; assign load_mr1[2] = ((RTT_NOM_int == "75") || (RTT_NOM_int == "50")) ? 1'b1 : 1'b0; assign load_mr1[5:3] = (AL == "0") ? 3'b000 : (AL == "1") ? 3'b001 : (AL == "2") ? 3'b010 : (AL == "3") ? 3'b011 : (AL == "4") ? 3'b100 : 3'b111; assign load_mr1[6] = ((RTT_NOM_int == "50") || (RTT_NOM_int == "150")) ? 1'b1 : 1'b0; assign load_mr1[9:7] = 3'b000; assign load_mr1[10] = (DDR2_DQSN_ENABLE == "YES") ? 1'b0 : 1'b1; assign load_mr1[15:11] = 5'b00000; end endgenerate //***************************************************************** // DDR3 Load mode reg2 // Mode Register (MR2): // [15:11] - unused - 00 // [10:9] - RTT_WR - 00 (Dynamic ODT off) // [8] - reserved - 0 (must be '0') // [7] - self-refresh temperature range - // 0 (normal), 1 (extended) // [6] - Auto Self-Refresh - 0 (manual), 1(auto) // [5:3] - CAS Write Latency (CWL) - // 000 (5 for 400 MHz device), // 001 (6 for 400 MHz to 533 MHz devices), // 010 (7 for 533 MHz to 667 MHz devices), // 011 (8 for 667 MHz to 800 MHz) // [2:0] - Partial Array Self-Refresh (Optional) - // 000 (full array) // Not used for DDR2 //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr2_DDR3 assign load_mr2[2:0] = 3'b000; assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 : (nCWL == 6) ? 3'b001 : (nCWL == 7) ? 3'b010 : (nCWL == 8) ? 3'b011 : (nCWL == 9) ? 3'b100 : (nCWL == 10) ? 3'b101 : (nCWL == 11) ? 3'b110 : 3'b111; assign load_mr2[6] = 1'b0; assign load_mr2[7] = 1'b0; assign load_mr2[8] = 1'b0; // Dynamic ODT disabled assign load_mr2[10:9] = 2'b00; assign load_mr2[15:11] = 5'b00000; end else begin: gen_load_mr2_DDR2 assign load_mr2[15:0] = 16'd0; end endgenerate //***************************************************************** // DDR3 Load mode reg3 // Mode Register (MR3): // [15:3] - unused - All zeros // [2] - MPR Operation - 0(normal operation), 1(data flow from MPR) // [1:0] - MPR location - 00 (Predefined pattern) //***************************************************************** assign load_mr3[1:0] = 2'b00; assign load_mr3[2] = 1'b0; assign load_mr3[15:3] = 13'b0000000000000; // For multi-rank systems the rank being accessed during writes in // Read Leveling must be sent to phy_write for the bitslip logic assign calib_rank_cnt = chip_cnt_r; //*************************************************************************** // Logic to begin initial calibration, and to handle precharge requests // during read-leveling (to avoid tRAS violations if individual read // levelling calibration stages take more than max{tRAS) to complete). //*************************************************************************** // Assert when readback for each stage of read-leveling begins. However, // note this indicates only when the read command is issued and when // Phaser_IN has phase aligned FREQ_REF clock to read DQS. It does not // indicate when the read data is present on the bus (when this happens // after the read command is issued depends on CAS LATENCY) - there will // need to be some delay before valid data is present on the bus. // assign rdlvl_start_pre = (init_state_r == INIT_PI_PHASELOCK_READS); // Assert when read back for oclkdelay calibration begins assign oclkdelay_calib_start_pre = (init_state_r == INIT_OCAL_CENTER_ACT); //(init_state_r == INIT_OCLKDELAY_READ); // Assert when read back for write calibration begins assign wrcal_start_pre = (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS); // Common precharge signal done signal - pulses only when there has been // a precharge issued as a result of a PRECH_REQ pulse. Note also a common // PRECH_DONE signal is used for all blocks assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || ((rdlvl_last_byte_done_r || prbs_last_byte_done_r) && (init_state_r == INIT_RDLVL_ACT_WAIT) && cnt_cmd_done_r) || (dqs_found_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || (init_state_r == INIT_MPR_RDEN) || ((init_state_r == INIT_WRCAL_ACT_WAIT) && cnt_cmd_done_r) || (init_state_r == INIT_OCAL_CENTER_ACT) || ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && complex_oclkdelay_calib_start_r1) || ((init_state_r == INIT_OCLKDELAY_ACT_WAIT) && cnt_cmd_done_r) || ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) && prbs_last_byte_done_r) || //prbs_rdlvl_done (wrlvl_final && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r && ~oclkdelay_calib_done)) && prech_pending_r && !prech_req_posedge_r); always @(posedge clk) if (rst) pi_phaselock_start <= #TCQ 1'b0; else if (init_state_r == INIT_PI_PHASELOCK_READS) pi_phaselock_start <= #TCQ 1'b1; // Delay start of each calibration by 16 clock cycles to ensure that when // calibration logic begins, read data is already appearing on the bus. // Each circuit should synthesize using an SRL16. Assume that reset is // long enough to clear contents of SRL16. always @(posedge clk) begin rdlvl_last_byte_done_r <= #TCQ rdlvl_last_byte_done; prbs_last_byte_done_r <= #TCQ prbs_last_byte_done; rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0], rdlvl_start_pre}; wrcal_start_dly_r <= #TCQ {wrcal_start_dly_r[14:0], wrcal_start_pre}; oclkdelay_start_dly_r <= #TCQ {oclkdelay_start_dly_r[14:0], oclkdelay_calib_start_pre}; prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0], prech_done_pre}; end always @(posedge clk) if (rst) oclkdelay_calib_start_int <= #TCQ 1'b0; else if (oclkdelay_start_dly_r[5]) oclkdelay_calib_start_int <= #TCQ 1'b1; always @(posedge clk) begin if (rst) ocal_last_byte_done <= #TCQ 1'b0; else if ((complex_oclkdelay_calib_cnt == DQS_WIDTH-1) && oclkdelay_center_calib_done) ocal_last_byte_done <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || (init_state_r == INIT_REFRESH) || prbs_rdlvl_done || ocal_last_byte_done || oclkdelay_center_calib_done) oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; else if (oclkdelay_calib_start_int) begin if (oclkdelay_ref_cnt > 'd0) oclkdelay_ref_cnt <= #TCQ oclkdelay_ref_cnt - 1; else oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; end end always @(posedge clk) begin if (rst || (init_state_r == INIT_OCAL_CENTER_ACT) || oclkdelay_calib_done || ocal_last_byte_done || oclkdelay_center_calib_done) oclkdelay_int_ref_req <= #TCQ 1'b0; else if (oclkdelay_ref_cnt == 'd1) oclkdelay_int_ref_req <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) ocal_act_wait_cnt <= #TCQ 'd0; else if ((init_state_r == INIT_OCAL_CENTER_ACT_WAIT) && ocal_act_wait_cnt < 'd15) ocal_act_wait_cnt <= #TCQ ocal_act_wait_cnt + 1; else ocal_act_wait_cnt <= #TCQ 'd0; end always @(posedge clk) begin if (rst || (init_state_r == INIT_OCLKDELAY_READ)) oclk_calib_resume_level <= #TCQ 1'b0; else if (oclk_calib_resume) oclk_calib_resume_level <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_ACT_WAIT) || prbs_rdlvl_done) complex_rdlvl_int_ref_req <= #TCQ 1'b0; else if (oclkdelay_ref_cnt == 'd1) // complex_rdlvl_int_ref_req <= #TCQ 1'b1; complex_rdlvl_int_ref_req <= #TCQ 1'b0; //temporary fix for read issue end always @(posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_COMPLEX_READ)) ext_int_ref_req <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_ACT_WAIT) && complex_rdlvl_int_ref_req) ext_int_ref_req <= #TCQ 1'b1; end always @(posedge clk) begin prech_done <= #TCQ prech_done_dly_r[15]; prech_done_r1 <= #TCQ prech_done_dly_r[15]; prech_done_r2 <= #TCQ prech_done_r1; prech_done_r3 <= #TCQ prech_done_r2; end always @(posedge clk) if (rst) mpr_rdlvl_start <= #TCQ 1'b0; else if (pi_dqs_found_done && (init_state_r == INIT_MPR_READ)) mpr_rdlvl_start <= #TCQ 1'b1; always @(posedge clk) phy_if_empty_r <= #TCQ phy_if_empty; always @(posedge clk) if (rst || ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || prbs_rdlvl_done) prbs_gen_clk_en <= #TCQ 1'b0; else if ((~phy_if_empty_r && rdlvl_stg1_done_r1 && ~prbs_rdlvl_done) || ((init_state_r == INIT_RDLVL_ACT_WAIT) && rdlvl_stg1_done_r1 && (cnt_cmd_r == 'd127)) || ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && rdlvl_stg1_done_r1 && (complex_wait_cnt == 'd14)) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || ((init_state_r == INIT_PRECHARGE_PREWAIT) && prbs_rdlvl_start)) prbs_gen_clk_en <= #TCQ 1'b1; //Enable for complex oclkdelay - used in prbs gen always @(posedge clk) if (rst || ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || complex_oclkdelay_calib_done || (complex_wait_cnt == 'd15 && complex_num_writes == 1 && complex_ocal_wr_start) || ( init_state_r == INIT_RDLVL_STG1_WRITE && complex_num_writes_dec == 'd2) || ~complex_ocal_wr_start || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT ) || (init_state_r != INIT_OCAL_COMPLEX_RESUME_WAIT && init_state_r1 == INIT_OCAL_COMPLEX_RESUME_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_ACT)) prbs_gen_oclk_clk_en <= #TCQ 1'b0; else if ((~phy_if_empty_r && ~complex_oclkdelay_calib_done && prbs_rdlvl_done_r1) || // changed for new algo 3/26 ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd14)) || ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14)) || exit_ocal_complex_resume_wait || ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && ~stg1_wr_done && ~complex_row1_wr_done && ~complex_ocal_num_samples_done_r && (complex_wait_cnt == 'd14)) || (init_state_r == INIT_RDLVL_COMPLEX_READ) ) prbs_gen_oclk_clk_en <= #TCQ 1'b1; generate if (RANKS < 2) begin always @(posedge clk) if (rst) begin rdlvl_stg1_start <= #TCQ 1'b0; rdlvl_stg1_start_int <= #TCQ 1'b0; rdlvl_start_pre <= #TCQ 1'b0; prbs_rdlvl_start <= #TCQ 1'b0; end else begin if (pi_dqs_found_done && cnt_cmd_done_r && (init_state_r == INIT_RDLVL_ACT_WAIT)) rdlvl_stg1_start_int <= #TCQ 1'b1; if (pi_dqs_found_done && (init_state_r == INIT_RDLVL_STG1_READ))begin rdlvl_start_pre <= #TCQ 1'b1; rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; end if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_READ) && (WRLVL == "ON")) begin prbs_rdlvl_start <= #TCQ 1'b1; end end end else begin always @(posedge clk) if (rst || rdlvl_stg1_rank_done) begin rdlvl_stg1_start <= #TCQ 1'b0; rdlvl_stg1_start_int <= #TCQ 1'b0; rdlvl_start_pre <= #TCQ 1'b0; prbs_rdlvl_start <= #TCQ 1'b0; end else begin if (pi_dqs_found_done && cnt_cmd_done_r && (init_state_r == INIT_RDLVL_ACT_WAIT)) rdlvl_stg1_start_int <= #TCQ 1'b1; if (pi_dqs_found_done && (init_state_r == INIT_RDLVL_STG1_READ))begin rdlvl_start_pre <= #TCQ 1'b1; rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; end if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_READ) && (WRLVL == "ON")) begin prbs_rdlvl_start <= #TCQ 1'b1; end end end endgenerate always @(posedge clk) begin if (rst || dqsfound_retry || wrlvl_byte_redo) begin pi_dqs_found_start <= #TCQ 1'b0; wrcal_start <= #TCQ 1'b0; end else begin if (!pi_dqs_found_done && init_state_r == INIT_RDLVL_STG2_READ) pi_dqs_found_start <= #TCQ 1'b1; if (wrcal_start_dly_r[5]) wrcal_start <= #TCQ 1'b1; end end // else: !if(rst) always @(posedge clk) if (rst) oclkdelay_calib_start <= #TCQ 1'b0; else if (oclkdelay_start_dly_r[5]) oclkdelay_calib_start <= #TCQ 1'b1; always @(posedge clk) if (rst) pi_dqs_found_done_r1 <= #TCQ 1'b0; else pi_dqs_found_done_r1 <= #TCQ pi_dqs_found_done; always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final; // Reset IN_FIFO after final write leveling to make sure the FIFO // pointers are initialized always @(posedge clk) if (rst || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_REFRESH)) wrlvl_final_if_rst <= #TCQ 1'b0; else if (wrlvl_done_r && //(wrlvl_final_r && wrlvl_done_r && (init_state_r == INIT_WRLVL_LOAD_MR2)) wrlvl_final_if_rst <= #TCQ 1'b1; // Constantly enable DQS while write leveling is enabled in the memory // This is more to get rid of warnings in simulation, can later change // this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted always @(posedge clk) if (rst || ((init_state_r1 != INIT_WRLVL_START) && (init_state_r == INIT_WRLVL_START))) wrlvl_odt_ctl <= #TCQ 1'b0; else if (wrlvl_rank_done && ~wrlvl_rank_done_r1) wrlvl_odt_ctl <= #TCQ 1'b1; generate if (nCK_PER_CLK == 4) begin: en_cnt_div4 always @ (posedge clk) if (rst) enable_wrlvl_cnt <= #TCQ 5'd0; else if ((init_state_r == INIT_WRLVL_START) || (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) enable_wrlvl_cnt <= #TCQ 5'd12; else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; // ODT stays asserted as long as write_calib // signal is asserted always @(posedge clk) if (rst || wrlvl_odt_ctl) wrlvl_odt <= #TCQ 1'b0; else if (enable_wrlvl_cnt == 5'd1) wrlvl_odt <= #TCQ 1'b1; end else begin: en_cnt_div2 always @ (posedge clk) if (rst) enable_wrlvl_cnt <= #TCQ 5'd0; else if ((init_state_r == INIT_WRLVL_START) || (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) enable_wrlvl_cnt <= #TCQ 5'd21; else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; // ODT stays asserted as long as write_calib // signal is asserted always @(posedge clk) if (rst || wrlvl_odt_ctl) wrlvl_odt <= #TCQ 1'b0; else if (enable_wrlvl_cnt == 5'd1) wrlvl_odt <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst || wrlvl_rank_done || done_dqs_tap_inc) wrlvl_active <= #TCQ 1'b0; else if ((enable_wrlvl_cnt == 5'd1) && wrlvl_odt && !wrlvl_active) wrlvl_active <= #TCQ 1'b1; // signal used to assert DQS for write leveling. // the DQS will be asserted once every 16 clock cycles. always @(posedge clk)begin if(rst || (enable_wrlvl_cnt != 5'd1)) begin wr_level_dqs_asrt <= #TCQ 1'd0; end else if ((enable_wrlvl_cnt == 5'd1) && (wrlvl_active_r1)) begin wr_level_dqs_asrt <= #TCQ 1'd1; end end always @ (posedge clk) begin if (rst || (wrlvl_done_r && ~wrlvl_done_r1)) dqs_asrt_cnt <= #TCQ 2'd0; else if (wr_level_dqs_asrt && dqs_asrt_cnt != 2'd3) dqs_asrt_cnt <= #TCQ (dqs_asrt_cnt + 1); end always @ (posedge clk) begin if (rst || ~wrlvl_active) wr_lvl_start <= #TCQ 1'd0; else if (dqs_asrt_cnt == 2'd3) wr_lvl_start <= #TCQ 1'd1; end always @(posedge clk) begin if (rst) wl_sm_start <= #TCQ 1'b0; else wl_sm_start <= #TCQ wr_level_dqs_asrt_r1; end always @(posedge clk) begin wrlvl_active_r1 <= #TCQ wrlvl_active; wr_level_dqs_asrt_r1 <= #TCQ wr_level_dqs_asrt; wrlvl_done_r <= #TCQ wrlvl_done; wrlvl_done_r1 <= #TCQ wrlvl_done_r; wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done; wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1; wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2; wrlvl_rank_done_r4 <= #TCQ wrlvl_rank_done_r3; wrlvl_rank_done_r5 <= #TCQ wrlvl_rank_done_r4; wrlvl_rank_done_r6 <= #TCQ wrlvl_rank_done_r5; wrlvl_rank_done_r7 <= #TCQ wrlvl_rank_done_r6; end always @ (posedge clk) begin //if (rst) wrlvl_rank_cntr <= #TCQ 3'd0; //else if (wrlvl_rank_done) // wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1; end //***************************************************************** // Precharge request logic - those calibration logic blocks // that require greater than tRAS(max) to finish must break up // their calibration into smaller units of time, with precharges // issued in between. This is done using the XXX_PRECH_REQ and // PRECH_DONE handshaking between PHY_INIT and those blocks //***************************************************************** // Shared request from multiple sources assign prech_req = oclk_prech_req | rdlvl_prech_req | wrcal_prech_req | prbs_rdlvl_prech_req | (dqs_found_prech_req & (init_state_r == INIT_RDLVL_STG2_READ_WAIT)); // Handshaking logic to force precharge during read leveling, and to // notify read leveling logic when precharge has been initiated and // it's okay to proceed with leveling again always @(posedge clk) if (rst) begin prech_req_r <= #TCQ 1'b0; prech_req_posedge_r <= #TCQ 1'b0; prech_pending_r <= #TCQ 1'b0; end else begin prech_req_r <= #TCQ prech_req; prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r; if (prech_req_posedge_r) prech_pending_r <= #TCQ 1'b1; // Clear after we've finished with the precharge and have // returned to issuing read leveling calibration reads else if (prech_done_pre) prech_pending_r <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || prech_done_r3) mask_lim_done <= #TCQ 1'b0; else if (prech_pending_r) mask_lim_done <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || prbs_rdlvl_done_r3) complex_mask_lim_done <= #TCQ 1'b0; else if (~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) complex_mask_lim_done <= #TCQ 1'b1; end //Complex oclkdelay calibrration //*************************************************************************** // Various timing counters //*************************************************************************** //***************************************************************** // Generic delay for various states that require it (e.g. for turnaround // between read and write). Make this a sufficiently large number of clock // cycles to cover all possible frequencies and memory components) // Requirements for this counter: // 1. Greater than tMRD // 2. tRFC (refresh-active) for DDR2 // 3. (list the other requirements, slacker...) //***************************************************************** always @(posedge clk) begin case (init_state_r) INIT_LOAD_MR_WAIT, INIT_WRLVL_LOAD_MR_WAIT, INIT_WRLVL_LOAD_MR2_WAIT, INIT_MPR_WAIT, INIT_MPR_DISABLE_PREWAIT, INIT_MPR_DISABLE_WAIT, INIT_OCLKDELAY_ACT_WAIT, INIT_OCLKDELAY_WRITE_WAIT, INIT_RDLVL_ACT_WAIT, INIT_RDLVL_STG1_WRITE_READ, INIT_RDLVL_STG2_READ_WAIT, INIT_WRCAL_ACT_WAIT, INIT_WRCAL_WRITE_READ, INIT_WRCAL_READ_WAIT, INIT_PRECHARGE_PREWAIT, INIT_PRECHARGE_WAIT, INIT_DDR2_PRECHARGE_WAIT, INIT_REG_WRITE_WAIT, INIT_REFRESH_WAIT, INIT_REFRESH_RNK2_WAIT: begin if (phy_ctl_full || phy_cmd_full) cnt_cmd_r <= #TCQ cnt_cmd_r; else cnt_cmd_r <= #TCQ cnt_cmd_r + 1; end INIT_WRLVL_WAIT: cnt_cmd_r <= #TCQ 'b0; default: cnt_cmd_r <= #TCQ 'b0; endcase end // pulse when count reaches terminal count always @(posedge clk) cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD); // For ODT deassertion - hold throughout post read/write wait stage, but // deassert before next command. The post read/write stage is very long, so // we simply address the longest case here plus some margin. always @(posedge clk) cnt_cmd_done_m7_r <= #TCQ (cnt_cmd_r == (CNTNEXT_CMD - 7)); //************************************************************************ // Added to support PO fine delay inc when TG errors always @(posedge clk) begin case (init_state_r) INIT_WRCAL_READ_WAIT: begin if (phy_ctl_full || phy_cmd_full) cnt_wait <= #TCQ cnt_wait; else cnt_wait <= #TCQ cnt_wait + 1; end default: cnt_wait <= #TCQ 'b0; endcase end always @(posedge clk) cnt_wrcal_rd <= #TCQ (cnt_wait == 'd4); always @(posedge clk) begin if (rst || ~temp_wrcal_done) temp_lmr_done <= #TCQ 1'b0; else if (temp_wrcal_done && (init_state_r == INIT_LOAD_MR)) temp_lmr_done <= #TCQ 1'b1; end always @(posedge clk) temp_wrcal_done_r <= #TCQ temp_wrcal_done; always @(posedge clk) if (rst) begin tg_timer_go <= #TCQ 1'b0; end else if ((PRE_REV3ES == "ON") && temp_wrcal_done && temp_lmr_done && (init_state_r == INIT_WRCAL_READ_WAIT)) begin tg_timer_go <= #TCQ 1'b1; end else begin tg_timer_go <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || (temp_wrcal_done && ~temp_wrcal_done_r) || (init_state_r == INIT_PRECHARGE_PREWAIT)) tg_timer <= #TCQ 'd0; else if ((pi_phaselock_timer == PHASELOCKED_TIMEOUT) && tg_timer_go && (tg_timer != TG_TIMER_TIMEOUT)) tg_timer <= #TCQ tg_timer + 1; end always @(posedge clk) begin if (rst) tg_timer_done <= #TCQ 1'b0; else if (tg_timer == TG_TIMER_TIMEOUT) tg_timer_done <= #TCQ 1'b1; else tg_timer_done <= #TCQ 1'b0; end always @(posedge clk) begin if (rst) no_rst_tg_mc <= #TCQ 1'b0; else if ((init_state_r == INIT_WRCAL_ACT) && wrcal_read_req) no_rst_tg_mc <= #TCQ 1'b1; else no_rst_tg_mc <= #TCQ 1'b0; end //************************************************************************ always @(posedge clk) begin if (rst) detect_pi_found_dqs <= #TCQ 1'b0; else if ((cnt_cmd_r == 7'b0111111) && (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) detect_pi_found_dqs <= #TCQ 1'b1; else detect_pi_found_dqs <= #TCQ 1'b0; end //***************************************************************** // Initial delay after power-on for RESET, CKE // NOTE: Could reduce power consumption by turning off these counters // after initial power-up (at expense of more logic) // NOTE: Likely can combine multiple counters into single counter //***************************************************************** // Create divided by 1024 version of clock always @(posedge clk) if (rst) begin cnt_pwron_ce_r <= #TCQ 10'h000; pwron_ce_r <= #TCQ 1'b0; end else begin cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1; pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF); end // "Main" power-on counter - ticks every CLKDIV/1024 cycles always @(posedge clk) if (rst) cnt_pwron_r <= #TCQ 'b0; else if (pwron_ce_r) cnt_pwron_r <= #TCQ cnt_pwron_r + 1; always @(posedge clk) if (rst || ~phy_ctl_ready) begin cnt_pwron_reset_done_r <= #TCQ 1'b0; cnt_pwron_cke_done_r <= #TCQ 1'b0; end else begin // skip power-up count for simulation purposes only if ((SIM_INIT_OPTION == "SKIP_PU_DLY") || (SIM_INIT_OPTION == "SKIP_INIT")) begin cnt_pwron_reset_done_r <= #TCQ 1'b1; cnt_pwron_cke_done_r <= #TCQ 1'b1; end else begin // otherwise, create latched version of done signal for RESET, CKE if (DRAM_TYPE == "DDR3") begin if (!cnt_pwron_reset_done_r) cnt_pwron_reset_done_r <= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT); if (!cnt_pwron_cke_done_r) cnt_pwron_cke_done_r <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); end else begin // DDR2 cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed if (!cnt_pwron_cke_done_r) cnt_pwron_cke_done_r <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); end end end // else: !if(rst || ~phy_ctl_ready) always @(posedge clk) cnt_pwron_cke_done_r1 <= #TCQ cnt_pwron_cke_done_r; // Keep RESET asserted and CKE deasserted until after power-on delay always @(posedge clk or posedge rst) begin if (rst) phy_reset_n <= #TCQ 1'b0; else phy_reset_n <= #TCQ cnt_pwron_reset_done_r; // phy_cke <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}}; end //***************************************************************** // Counter for tXPR (pronouned "Tax-Payer") - wait time after // CKE deassertion before first MRS command can be asserted //***************************************************************** always @(posedge clk) if (!cnt_pwron_cke_done_r) begin cnt_txpr_r <= #TCQ 'b0; cnt_txpr_done_r <= #TCQ 1'b0; end else begin cnt_txpr_r <= #TCQ cnt_txpr_r + 1; if (!cnt_txpr_done_r) cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT); end //***************************************************************** // Counter for the initial 400ns wait for issuing precharge all // command after CKE assertion. Only for DDR2. //***************************************************************** always @(posedge clk) if (!cnt_pwron_cke_done_r) begin cnt_init_pre_wait_r <= #TCQ 'b0; cnt_init_pre_wait_done_r <= #TCQ 1'b0; end else begin cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1; if (!cnt_init_pre_wait_done_r) cnt_init_pre_wait_done_r <= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT); end //***************************************************************** // Wait for both DLL to lock (tDLLK) and ZQ calibration to finish // (tZQINIT). Both take the same amount of time (512*tCK) //***************************************************************** always @(posedge clk) if (init_state_r == INIT_ZQCL) begin cnt_dllk_zqinit_r <= #TCQ 'b0; cnt_dllk_zqinit_done_r <= #TCQ 1'b0; end else if (~(phy_ctl_full || phy_cmd_full)) begin cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1; if (!cnt_dllk_zqinit_done_r) cnt_dllk_zqinit_done_r <= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT); end //***************************************************************** // Keep track of which MRS counter needs to be programmed during // memory initialization // The counter and the done signal are reset an additional time // for DDR2. The same signals are used for the additional DDR2 // initialization sequence. //***************************************************************** always @(posedge clk) if ((init_state_r == INIT_IDLE)|| ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))) begin cnt_init_mr_r <= #TCQ 'b0; cnt_init_mr_done_r <= #TCQ 1'b0; end else if (init_state_r == INIT_LOAD_MR) begin cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1; cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE); end //***************************************************************** // Flag to tell if the first precharge for DDR2 init sequence is // done //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) ddr2_pre_flag_r<= #TCQ 'b0; else if (init_state_r == INIT_LOAD_MR) ddr2_pre_flag_r<= #TCQ 1'b1; // reset the flag for multi rank case else if ((ddr2_refresh_flag_r) && (init_state_r == INIT_LOAD_MR_WAIT)&& (cnt_cmd_done_r) && (cnt_init_mr_done_r)) ddr2_pre_flag_r <= #TCQ 'b0; //***************************************************************** // Flag to tell if the refresh stat for DDR2 init sequence is // reached //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) ddr2_refresh_flag_r<= #TCQ 'b0; else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r)) // reset the flag for multi rank case ddr2_refresh_flag_r<= #TCQ 1'b1; else if ((ddr2_refresh_flag_r) && (init_state_r == INIT_LOAD_MR_WAIT)&& (cnt_cmd_done_r) && (cnt_init_mr_done_r)) ddr2_refresh_flag_r <= #TCQ 'b0; //***************************************************************** // Keep track of the number of auto refreshes for DDR2 // initialization. The spec asks for a minimum of two refreshes. // Four refreshes are performed here. The two extra refreshes is to // account for the 200 clock cycle wait between step h and l. // Without the two extra refreshes we would have to have a // wait state. //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) begin cnt_init_af_r <= #TCQ 'b0; cnt_init_af_done_r <= #TCQ 1'b0; end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))begin cnt_init_af_r <= #TCQ cnt_init_af_r + 1; cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11); end //***************************************************************** // Keep track of the register control word programming for // DDR3 RDIMM //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) reg_ctrl_cnt_r <= #TCQ 'b0; else if (init_state_r == INIT_REG_WRITE) reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1; generate if (RANKS < 2) begin: one_rank always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || (complex_byte_rd_done) || prbs_rdlvl_done_pulse ) stg1_wr_done <= #TCQ 1'b0; else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) stg1_wr_done <= #TCQ 1'b1; end else begin: two_ranks always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || (complex_byte_rd_done) || prbs_rdlvl_done_pulse || (rdlvl_stg1_rank_done )) stg1_wr_done <= #TCQ 1'b0; else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) stg1_wr_done <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst) rnk_ref_cnt <= #TCQ 1'b0; else if (stg1_wr_done && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r) rnk_ref_cnt <= #TCQ ~rnk_ref_cnt; always @(posedge clk) if (rst || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r ==INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT)) num_refresh <= #TCQ 'd0; else if ((init_state_r == INIT_REFRESH) && (~pi_dqs_found_done || ((DRAM_TYPE == "DDR3") && ~oclkdelay_calib_done) || (rdlvl_stg1_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done))) num_refresh <= #TCQ num_refresh + 1; //*************************************************************************** // Initialization state machine //*************************************************************************** //***************************************************************** // Next-state logic //***************************************************************** always @(posedge clk) if (rst)begin init_state_r <= #TCQ INIT_IDLE; init_state_r1 <= #TCQ INIT_IDLE; end else begin init_state_r <= #TCQ init_next_state; init_state_r1 <= #TCQ init_state_r; end always @(*) begin init_next_state = init_state_r; (* full_case, parallel_case *) case (init_state_r) //******************************************************* // DRAM initialization //******************************************************* // Initial state - wait for: // 1. Power-on delays to pass // 2. PHY Control Block to assert phy_ctl_ready // 3. PHY Control FIFO must not be FULL // 4. Read path initialization to finish INIT_IDLE: if (cnt_pwron_cke_done_r && phy_ctl_ready && ck_addr_cmd_delay_done && delay_incdec_done && ~(phy_ctl_full || phy_cmd_full) ) begin // If skipping memory initialization (simulation only) if (SIM_INIT_OPTION == "SKIP_INIT") //if (WRLVL == "ON") // Proceed to write leveling // init_next_state = INIT_WRLVL_START; //else //if (SIM_CAL_OPTION != "SKIP_CAL") // Proceed to Phaser_In phase lock init_next_state = INIT_RDLVL_ACT; // else // Skip read leveling //init_next_state = INIT_DONE; else init_next_state = INIT_WAIT_CKE_EXIT; end // Wait minimum of Reset CKE exit time (tXPR = max(tXS, INIT_WAIT_CKE_EXIT: if ((cnt_txpr_done_r) && (DRAM_TYPE == "DDR3") && ~(phy_ctl_full || phy_cmd_full)) begin if((REG_CTRL == "ON") && ((nCS_PER_RANK > 1) || (RANKS > 1))) //register write for reg dimm. Some register chips // have the register chip in a pre-programmed state // in that case the nCS_PER_RANK == 1 && RANKS == 1 init_next_state = INIT_REG_WRITE; else // Load mode register - this state is repeated multiple times init_next_state = INIT_LOAD_MR; end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == "DDR2") && ~(phy_ctl_full || phy_cmd_full)) // DDR2 start with a precharge all command init_next_state = INIT_DDR2_PRECHARGE; INIT_REG_WRITE: init_next_state = INIT_REG_WRITE_WAIT; INIT_REG_WRITE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if(reg_ctrl_cnt_r == 4'd8) init_next_state = INIT_LOAD_MR; else init_next_state = INIT_REG_WRITE; end INIT_LOAD_MR: init_next_state = INIT_LOAD_MR_WAIT; // After loading MR, wait at least tMRD INIT_LOAD_MR_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin // If finished loading all mode registers, proceed to next step if (prbs_rdlvl_done && pi_dqs_found_done && rdlvl_stg1_done) // for ddr3 when the correct burst length is writtern at end init_next_state = INIT_PRECHARGE; else if (~wrcal_done && temp_lmr_done) init_next_state = INIT_PRECHARGE_PREWAIT; else if (cnt_init_mr_done_r)begin if(DRAM_TYPE == "DDR3") init_next_state = INIT_ZQCL; else begin //DDR2 if(ddr2_refresh_flag_r)begin // memory initialization per rank for multi-rank case if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) init_next_state = INIT_DDR2_MULTI_RANK; else init_next_state = INIT_RDLVL_ACT; // ddr2 initialization done.load mode state after refresh end else init_next_state = INIT_DDR2_PRECHARGE; end end else init_next_state = INIT_LOAD_MR; end // DDR2 multi rank transition state INIT_DDR2_MULTI_RANK: init_next_state = INIT_DDR2_MULTI_RANK_WAIT; INIT_DDR2_MULTI_RANK_WAIT: init_next_state = INIT_DDR2_PRECHARGE; // Initial ZQ calibration INIT_ZQCL: init_next_state = INIT_WAIT_DLLK_ZQINIT; // Wait until both DLL have locked, and ZQ calibration done INIT_WAIT_DLLK_ZQINIT: if (cnt_dllk_zqinit_done_r && ~(phy_ctl_full || phy_cmd_full)) // memory initialization per rank for multi-rank case if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) init_next_state = INIT_LOAD_MR; //else if (WRLVL == "ON") // init_next_state = INIT_WRLVL_START; else // skip write-leveling (e.g. for DDR2 interface) init_next_state = INIT_RDLVL_ACT; // Initial precharge for DDR2 INIT_DDR2_PRECHARGE: init_next_state = INIT_DDR2_PRECHARGE_WAIT; INIT_DDR2_PRECHARGE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if (ddr2_pre_flag_r) init_next_state = INIT_REFRESH; else // from precharge state initially go to load mode init_next_state = INIT_LOAD_MR; end INIT_REFRESH: if ((RANKS == 2) && (chip_cnt_r == RANKS - 1)) init_next_state = INIT_REFRESH_RNK2_WAIT; else init_next_state = INIT_REFRESH_WAIT; INIT_REFRESH_RNK2_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_PRECHARGE; INIT_REFRESH_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin if(cnt_init_af_done_r && (~mem_init_done_r)) // go to lm state as part of DDR2 init sequence init_next_state = INIT_LOAD_MR; // Go to state to issue back-to-back writes during limit check and centering else if (~oclkdelay_calib_done && (mpr_last_byte_done || mpr_rdlvl_done) && (DRAM_TYPE == "DDR3")) begin if (num_refresh == 'd8) init_next_state = INIT_OCAL_CENTER_ACT; else init_next_state = INIT_REFRESH; end else if(rdlvl_stg1_done && oclkdelay_center_calib_done && complex_oclkdelay_calib_done && ~wrlvl_done_r1 && (WRLVL == "ON")) init_next_state = INIT_WRLVL_START; else if (pi_dqs_found_done && ~wrlvl_done_r1 && ~wrlvl_final && ~wrlvl_byte_redo && (WRLVL == "ON")) init_next_state = INIT_WRLVL_START; else if ((((prbs_last_byte_done_r || prbs_rdlvl_done) && ~complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON")) //&& rdlvl_stg1_done // changed for new algo 3/26 && mem_init_done_r) begin if (num_refresh == 'd8) begin if (BYPASS_COMPLEX_OCAL == "FALSE") init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else init_next_state = INIT_WRCAL_ACT; end else init_next_state = INIT_REFRESH; end else if (~pi_dqs_found_done || (rdlvl_stg1_done && ~prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)) begin if (num_refresh == 'd8) init_next_state = INIT_RDLVL_ACT; else init_next_state = INIT_REFRESH; end else if ((~wrcal_done && wrlvl_byte_redo)&& (DRAM_TYPE == "DDR3") && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRLVL_LOAD_MR2; else if (((prbs_rdlvl_done && rdlvl_stg1_done && complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON")) && mem_init_done_r && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRCAL_ACT; else if (pi_dqs_found_done && (DRAM_TYPE == "DDR3") && ~(mpr_last_byte_done || mpr_rdlvl_done)) begin if (num_refresh == 'd8) init_next_state = INIT_MPR_RDEN; else init_next_state = INIT_REFRESH; end else if (((oclkdelay_calib_done && wrlvl_final && ~wrlvl_done_r1) || // changed for new algo 3/25 (~wrcal_done && wrlvl_byte_redo)) && (DRAM_TYPE == "DDR3")) init_next_state = INIT_WRLVL_LOAD_MR2; else if ((~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) && pi_dqs_found_done) init_next_state = INIT_WRCAL_ACT; else if (mem_init_done_r) begin if (RANKS < 2) init_next_state = INIT_RDLVL_ACT; else if (stg1_wr_done && ~rnk_ref_cnt && ~rdlvl_stg1_done) init_next_state = INIT_PRECHARGE; else init_next_state = INIT_RDLVL_ACT; end else // to DDR2 init state as part of DDR2 init sequence init_next_state = INIT_REFRESH; end //****************************************************** // Write Leveling //******************************************************* // Enable write leveling in MR1 and start write leveling // for current rank INIT_WRLVL_START: init_next_state = INIT_WRLVL_WAIT; // Wait for both MR load and write leveling to complete // (write leveling should take much longer than MR load..) INIT_WRLVL_WAIT: if (wrlvl_rank_done_r7 && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRLVL_LOAD_MR; // Disable write leveling in MR1 for current rank INIT_WRLVL_LOAD_MR: init_next_state = INIT_WRLVL_LOAD_MR_WAIT; INIT_WRLVL_LOAD_MR_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRLVL_LOAD_MR2; // Load MR2 to set ODT: Dynamic ODT for single rank case // And ODTs for multi-rank case as well INIT_WRLVL_LOAD_MR2: init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; // Wait tMRD before proceeding INIT_WRLVL_LOAD_MR2_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin //if (wrlvl_byte_done) // init_next_state = INIT_PRECHARGE_PREWAIT; // else if ((RANKS == 2) && wrlvl_rank_done_r2) // init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; if (~wrlvl_done_r1) init_next_state = INIT_WRLVL_START; else if (SIM_CAL_OPTION == "SKIP_CAL") // If skip rdlvl, then we're done init_next_state = INIT_DONE; else // Otherwise, proceed to read leveling //init_next_state = INIT_RDLVL_ACT; init_next_state = INIT_PRECHARGE_PREWAIT; end //******************************************************* // Read Leveling //******************************************************* // single row activate. All subsequent read leveling writes and // read will take place in this row INIT_RDLVL_ACT: init_next_state = INIT_RDLVL_ACT_WAIT; // hang out for awhile before issuing subsequent column commands // it's also possible to reach this state at various points // during read leveling - determine what the current stage is INIT_RDLVL_ACT_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin // Just finished an activate. Now either write, read, or precharge // depending on where we are in the training sequence if (!pi_calib_done_r1) init_next_state = INIT_PI_PHASELOCK_READS; else if (!pi_dqs_found_done) // (!pi_dqs_found_start || pi_dqs_found_rank_done)) init_next_state = INIT_RDLVL_STG2_READ; else if (~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) init_next_state = INIT_WRCAL_ACT_WAIT; else if ((!rdlvl_stg1_done && ~stg1_wr_done && ~rdlvl_last_byte_done) || (!prbs_rdlvl_done && ~stg1_wr_done && ~prbs_last_byte_done)) begin // Added to avoid rdlvl_stg1 write data pattern at the start of PRBS rdlvl if (!prbs_rdlvl_done && ~stg1_wr_done && rdlvl_last_byte_done) init_next_state = INIT_RDLVL_ACT_WAIT; else init_next_state = INIT_RDLVL_STG1_WRITE; end else if ((!rdlvl_stg1_done && rdlvl_stg1_start_int) || !prbs_rdlvl_done) begin if (rdlvl_last_byte_done || prbs_last_byte_done) // Added to avoid extra reads at the end of read leveling init_next_state = INIT_RDLVL_ACT_WAIT; else begin // Case 2: If in stage 1, and just precharged after training // previous byte, then continue reading if (rdlvl_stg1_done) init_next_state = INIT_RDLVL_STG1_WRITE_READ; else init_next_state = INIT_RDLVL_STG1_READ; end end else if ((prbs_rdlvl_done && rdlvl_stg1_done && (RANKS == 1)) && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRCAL_ACT_WAIT; else // Otherwise, if we're finished with calibration, then precharge // the row - silly, because we just opened it - possible to take // this out by adding logic to avoid the ACT in first place. Make // sure that cnt_cmd_done will handle tRAS(min) init_next_state = INIT_PRECHARGE_PREWAIT; end //************************************************** // Back-to-back reads for Phaser_IN Phase locking // DQS to FREQ_REF clock //************************************************** INIT_PI_PHASELOCK_READS: if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) init_next_state = INIT_PRECHARGE_PREWAIT; //********************************************* // Stage 1 read-leveling (write and continuous read) //********************************************* // Write training pattern for stage 1 // PRBS pattern of TBD length INIT_RDLVL_STG1_WRITE: // 4:1 DDR3 BL8 will require all 8 words in 1 DIV4 clock cycle // 2:1 DDR2/DDR3 BL8 will require 2 DIV2 clock cycles for 8 words // 2:1 DDR2 BL4 will require 1 DIV2 clock cycle for 4 words // An entire row worth of writes issued before proceeding to reads // The number of write is (2^column width)/burst length to accomodate // PRBS pattern for window detection. //VCCO/VCCAUX write is not done if ((complex_num_writes_dec == 1) && ~complex_row0_wr_done && prbs_rdlvl_done && rdlvl_stg1_done_r1) init_next_state = INIT_OCAL_COMPLEX_WRITE_WAIT; //back to back write from row1 else if (stg1_wr_rd_cnt == 9'd1) begin if (rdlvl_stg1_done_r1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else init_next_state = INIT_RDLVL_STG1_WRITE_READ; end INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT: if(read_pause_ext) begin init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; end else begin if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) //At the end of the byte, it goes to REFRESH init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE; end INIT_RDLVL_COMPLEX_PRECHARGE: init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; INIT_RDLVL_COMPLEX_PRECHARGE_WAIT: if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) begin if (prbs_rdlvl_done || prbs_last_byte_done_r) begin // changed for new algo 3/26 // added condition to ensure that limit starts after rdlvl_stg1_done is asserted in the bypass complex rdlvl mode if ((~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) || ~lim_done) init_next_state = INIT_OCAL_CENTER_ACT; //INIT_OCAL_COMPLEX_ACT; // changed for new algo 3/26 else if (lim_done && complex_oclkdelay_calib_start_r2) init_next_state = INIT_RDLVL_COMPLEX_ACT; else init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; end else init_next_state = INIT_RDLVL_COMPLEX_ACT; end INIT_RDLVL_COMPLEX_ACT: init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT; INIT_RDLVL_COMPLEX_ACT_WAIT: if (complex_rdlvl_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) begin if (oclkdelay_center_calib_start) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; else if (stg1_wr_done) init_next_state = INIT_RDLVL_COMPLEX_READ; else if (~complex_row1_wr_done) if (complex_oclkdelay_calib_start_int && complex_ocal_num_samples_done_r) //WAIT for resume signal for write init_next_state = INIT_OCAL_COMPLEX_RESUME_WAIT; else init_next_state = INIT_RDLVL_STG1_WRITE; else init_next_state = INIT_RDLVL_STG1_WRITE_READ; end // Write-read turnaround INIT_RDLVL_STG1_WRITE_READ: if (reset_rd_addr_r1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin if (rdlvl_stg1_done_r1) init_next_state = INIT_RDLVL_COMPLEX_READ; else init_next_state = INIT_RDLVL_STG1_READ; end // Continuous read, where interruptible by precharge request from // calibration logic. Also precharges when stage 1 is complete // No precharges when reads provided to Phaser_IN for phase locking // FREQ_REF to read DQS since data integrity is not important. INIT_RDLVL_STG1_READ: if (rdlvl_stg1_rank_done || (rdlvl_stg1_done && ~rdlvl_stg1_done_r1) || prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; INIT_RDLVL_COMPLEX_READ: if (prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; //For non-back-to-back reads from row0 (VCCO and VCCAUX pattern) else if (~prbs_rdlvl_done && (complex_num_reads_dec == 1) && ~complex_row0_rd_done) init_next_state = INIT_RDLVL_COMPLEX_READ_WAIT; //For back-to-back reads from row1 (ISI pattern) else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; INIT_RDLVL_COMPLEX_READ_WAIT: if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) init_next_state = INIT_RDLVL_COMPLEX_READ; //********************************************* // DQSFOUND calibration (set of 4 reads with gaps) //********************************************* // Read of training data. Note that Stage 2 is not a constant read, // instead there is a large gap between each set of back-to-back reads INIT_RDLVL_STG2_READ: // 4 read commands issued back-to-back if (num_reads == 'b1) init_next_state = INIT_RDLVL_STG2_READ_WAIT; // Wait before issuing the next set of reads. If a precharge request // comes in then handle - this can occur after stage 2 calibration is // completed for a DQS group INIT_RDLVL_STG2_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if (pi_dqs_found_rank_done || pi_dqs_found_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; else if (cnt_cmd_done_r) init_next_state = INIT_RDLVL_STG2_READ; end //****************************************************************** // MPR Read Leveling for DDR3 OCLK_DELAYED calibration //****************************************************************** // Issue Load Mode Register 3 command with A[2]=1, A[1:0]=2'b00 // to enable Multi Purpose Register (MPR) Read INIT_MPR_RDEN: init_next_state = INIT_MPR_WAIT; //Wait tMRD, tMOD INIT_MPR_WAIT: if (cnt_cmd_done_r) begin init_next_state = INIT_MPR_READ; end // Issue back-to-back read commands to read from MPR with // Address bus 0x0000 for BL=8. DQ[0] will output the pre-defined // MPR pattern of 01010101 (Rise0 = 1'b0, Fall0 = 1'b1 ...) INIT_MPR_READ: if (mpr_rdlvl_done || mpr_rnk_done || rdlvl_prech_req) init_next_state = INIT_MPR_DISABLE_PREWAIT; INIT_MPR_DISABLE_PREWAIT: if (cnt_cmd_done_r) init_next_state = INIT_MPR_DISABLE; // Issue Load Mode Register 3 command with A[2]=0 to disable // MPR read INIT_MPR_DISABLE: init_next_state = INIT_MPR_DISABLE_WAIT; INIT_MPR_DISABLE_WAIT: init_next_state = INIT_PRECHARGE_PREWAIT; //*********************************************************************** // OCLKDELAY Calibration //*********************************************************************** // This calibration requires single write followed by single read to // determine the Phaser_Out stage 3 delay required to center write DQS // in write DQ valid window. // Single Row Activate command before issuing Write command INIT_OCLKDELAY_ACT: init_next_state = INIT_OCLKDELAY_ACT_WAIT; INIT_OCLKDELAY_ACT_WAIT: if (cnt_cmd_done_r && ~oclk_prech_req) init_next_state = INIT_OCLKDELAY_WRITE; else if (oclkdelay_calib_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; INIT_OCLKDELAY_WRITE: if (oclk_wr_cnt == 4'd1) init_next_state = INIT_OCLKDELAY_WRITE_WAIT; INIT_OCLKDELAY_WRITE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if (oclkdelay_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else init_next_state = INIT_OCLKDELAY_READ; end INIT_OCLKDELAY_READ: init_next_state = INIT_OCLKDELAY_READ_WAIT; INIT_OCLKDELAY_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if ((oclk_calib_resume_level || oclk_calib_resume) && ~oclkdelay_int_ref_req) init_next_state = INIT_OCLKDELAY_WRITE; else if (oclkdelay_calib_done || prech_req_posedge_r || wrlvl_final || oclkdelay_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else if (oclkdelay_center_calib_start) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; end //********************************************* // Write calibration //********************************************* // single row activate INIT_WRCAL_ACT: init_next_state = INIT_WRCAL_ACT_WAIT; // hang out for awhile before issuing subsequent column command INIT_WRCAL_ACT_WAIT: if (cnt_cmd_done_r && ~wrcal_prech_req) init_next_state = INIT_WRCAL_WRITE; else if (wrcal_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; // Write training pattern for write calibration INIT_WRCAL_WRITE: // Once we've issued enough commands for 8 words - proceed to reads //if (burst_addr_r == 1'b1) if (wrcal_wr_cnt == 4'd1) init_next_state = INIT_WRCAL_WRITE_READ; // Write-read turnaround INIT_WRCAL_WRITE_READ: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRCAL_READ; else if (dqsfound_retry) init_next_state = INIT_RDLVL_STG2_READ_WAIT; INIT_WRCAL_READ: if (burst_addr_r == 1'b1) init_next_state = INIT_WRCAL_READ_WAIT; INIT_WRCAL_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if (wrcal_resume_r) begin if (wrcal_final_chk) init_next_state = INIT_WRCAL_READ; else init_next_state = INIT_WRCAL_WRITE; end else if (wrcal_done || prech_req_posedge_r || wrcal_act_req || // Added to support PO fine delay inc when TG errors wrlvl_byte_redo || (temp_wrcal_done && ~temp_lmr_done)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (dqsfound_retry) init_next_state = INIT_RDLVL_STG2_READ_WAIT; else if (wrcal_read_req && cnt_wrcal_rd) init_next_state = INIT_WRCAL_MULT_READS; end INIT_WRCAL_MULT_READS: // multiple read commands issued back-to-back if (wrcal_reads == 'b1) init_next_state = INIT_WRCAL_READ_WAIT; //********************************************* // Handling of precharge during and in between read-level stages //********************************************* // Make sure we aren't violating any timing specs by precharging // immediately INIT_PRECHARGE_PREWAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_PRECHARGE; // Initiate precharge INIT_PRECHARGE: init_next_state = INIT_PRECHARGE_WAIT; INIT_PRECHARGE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if ((wrcal_sanity_chk_done && (DRAM_TYPE == "DDR3")) || (rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && (DRAM_TYPE == "DDR2"))) init_next_state = INIT_DONE; else if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && complex_oclkdelay_calib_done && wrlvl_done_r1 && ((ddr3_lm_done_r) || (DRAM_TYPE == "DDR2"))) init_next_state = INIT_WRCAL_ACT; else if ((wrcal_done || (WRLVL == "OFF") || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) && (rdlvl_stg1_done || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) && prbs_rdlvl_done && complex_oclkdelay_calib_done && wrlvl_done_r1 &rdlvl_stg1_done && pi_dqs_found_done) begin // after all calibration program the correct burst length init_next_state = INIT_LOAD_MR; // Added to support PO fine delay inc when TG errors end else if (~wrcal_done && temp_wrcal_done && temp_lmr_done) init_next_state = INIT_WRCAL_READ_WAIT; else if (rdlvl_stg1_done && pi_dqs_found_done && (WRLVL == "ON")) // If read leveling finished, proceed to write calibration init_next_state = INIT_REFRESH; else // Otherwise, open row for read-leveling purposes init_next_state = INIT_REFRESH; end //******************************************************* // COMPLEX OCLK calibration - for fragmented write //******************************************************* INIT_OCAL_COMPLEX_ACT: init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; INIT_OCAL_COMPLEX_ACT_WAIT: if (complex_wait_cnt =='d15) init_next_state = INIT_RDLVL_STG1_WRITE; INIT_OCAL_COMPLEX_WRITE_WAIT: if (prech_req_posedge_r || (complex_oclkdelay_calib_done && ~complex_oclkdelay_calib_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) init_next_state = INIT_RDLVL_STG1_WRITE; //wait for all srg2/stg3 tap movement is done and go back to write again INIT_OCAL_COMPLEX_RESUME_WAIT: if (complex_oclk_calib_resume) init_next_state = INIT_RDLVL_STG1_WRITE; else if (complex_oclkdelay_calib_done || complex_ocal_ref_req ) init_next_state = INIT_PRECHARGE_PREWAIT; //******************************************************* // OCAL STG3 Centering calibration //******************************************************* INIT_OCAL_CENTER_ACT: init_next_state = INIT_OCAL_CENTER_ACT_WAIT; INIT_OCAL_CENTER_ACT_WAIT: if (ocal_act_wait_cnt == 'd15) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; INIT_OCAL_CENTER_WRITE: if(!oclk_center_write_resume && !lim_wr_req) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; INIT_OCAL_CENTER_WRITE_WAIT: //if (oclkdelay_center_calib_done || prech_req_posedge_r) if (prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && oclkdelay_calib_done && ~oclkdelay_center_calib_start) init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && ~oclkdelay_center_calib_start) init_next_state = INIT_OCLKDELAY_READ_WAIT; else if (oclk_center_write_resume || lim_wr_req) init_next_state = INIT_OCAL_CENTER_WRITE; //******************************************************* // Initialization/Calibration done. Take a long rest, relax //******************************************************* INIT_DONE: init_next_state = INIT_DONE; endcase end //***************************************************************** // Initialization done signal - asserted before leveling starts //***************************************************************** always @(posedge clk) if (rst) mem_init_done_r <= #TCQ 1'b0; else if ((!cnt_dllk_zqinit_done_r && (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) && (chip_cnt_r == RANKS-1) && (DRAM_TYPE == "DDR3")) || ( (init_state_r == INIT_LOAD_MR_WAIT) && (ddr2_refresh_flag_r) && (chip_cnt_r == RANKS-1) && (cnt_init_mr_done_r) && (DRAM_TYPE == "DDR2"))) mem_init_done_r <= #TCQ 1'b1; //***************************************************************** // Write Calibration signal to PHY Control Block - asserted before // Write Leveling starts //***************************************************************** //generate //if (RANKS < 2) begin: ranks_one always @(posedge clk) begin if (rst || (done_dqs_tap_inc && (init_state_r == INIT_WRLVL_LOAD_MR2))) write_calib <= #TCQ 1'b0; else if (wrlvl_active_r1) write_calib <= #TCQ 1'b1; end //end else begin: ranks_two // always @(posedge clk) begin // if (rst || // ((init_state_r1 == INIT_WRLVL_LOAD_MR_WAIT) && // ((wrlvl_rank_done_r2 && (chip_cnt_r == RANKS-1)) || // (SIM_CAL_OPTION == "FAST_CAL")))) // write_calib <= #TCQ 1'b0; // else if (wrlvl_active_r1) // write_calib <= #TCQ 1'b1; // end //end //endgenerate //***************************************************************** // Read Calibration signal to PHY Control Block - asserted after // Write Leveling during PHASER_IN phase locking stage. // Must be de-asserted before Read Leveling //***************************************************************** always @(posedge clk) begin if (rst || pi_calib_done_r1) read_calib_int <= #TCQ 1'b0; else if (~pi_calib_done_r1 && (init_state_r == INIT_RDLVL_ACT_WAIT) && (cnt_cmd_r == CNTNEXT_CMD)) read_calib_int <= #TCQ 1'b1; end always @(posedge clk) read_calib_r <= #TCQ read_calib_int; always @(posedge clk) begin if (rst || pi_calib_done_r1) read_calib <= #TCQ 1'b0; else if (~pi_calib_done_r1 && (init_state_r == INIT_PI_PHASELOCK_READS)) read_calib <= #TCQ 1'b1; end always @(posedge clk) if (rst) pi_calib_done_r <= #TCQ 1'b0; else if (pi_calib_rank_done_r)// && (chip_cnt_r == RANKS-1)) pi_calib_done_r <= #TCQ 1'b1; always @(posedge clk) if (rst) pi_calib_rank_done_r <= #TCQ 1'b0; else if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) pi_calib_rank_done_r <= #TCQ 1'b1; else pi_calib_rank_done_r <= #TCQ 1'b0; always @(posedge clk) begin if (rst || ((PRE_REV3ES == "ON") && temp_wrcal_done && ~temp_wrcal_done_r)) pi_phaselock_timer <= #TCQ 'd0; else if (((init_state_r == INIT_PI_PHASELOCK_READS) && (pi_phaselock_timer != PHASELOCKED_TIMEOUT)) || tg_timer_go) pi_phaselock_timer <= #TCQ pi_phaselock_timer + 1; else pi_phaselock_timer <= #TCQ pi_phaselock_timer; end assign pi_phase_locked_err = (pi_phaselock_timer == PHASELOCKED_TIMEOUT) ? 1'b1 : 1'b0; //***************************************************************** // DDR3 final burst length programming done. For DDR3 during // calibration the burst length is fixed to BL8. After calibration // the correct burst length is programmed. //***************************************************************** always @(posedge clk) if (rst) ddr3_lm_done_r <= #TCQ 1'b0; else if ((init_state_r == INIT_LOAD_MR_WAIT) && (chip_cnt_r == RANKS-1) && wrcal_done) ddr3_lm_done_r <= #TCQ 1'b1; always @(posedge clk) begin pi_dqs_found_rank_done_r <= #TCQ pi_dqs_found_rank_done; pi_phase_locked_all_r1 <= #TCQ pi_phase_locked_all; pi_phase_locked_all_r2 <= #TCQ pi_phase_locked_all_r1; pi_phase_locked_all_r3 <= #TCQ pi_phase_locked_all_r2; pi_phase_locked_all_r4 <= #TCQ pi_phase_locked_all_r3; pi_dqs_found_all_r <= #TCQ pi_dqs_found_done; pi_calib_done_r1 <= #TCQ pi_calib_done_r; end //*************************************************************************** // Logic for deep memory (multi-rank) configurations //*************************************************************************** // For DDR3 asserted when generate if (RANKS < 2) begin: single_rank always @(posedge clk) chip_cnt_r <= #TCQ 2'b00; end else begin: dual_rank always @(posedge clk) if (rst || // Set chip_cnt_r to 2'b00 after both Ranks are read leveled (rdlvl_stg1_done && prbs_rdlvl_done && ~wrcal_done) || // Set chip_cnt_r to 2'b00 after both Ranks are write leveled (wrlvl_done_r && (init_state_r==INIT_WRLVL_LOAD_MR2_WAIT)))begin chip_cnt_r <= #TCQ 2'b00; end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) && (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT)) && (DRAM_TYPE == "DDR3")) || ((init_state_r==INIT_REFRESH_RNK2_WAIT) && (cnt_cmd_r=='d36)) || //mpr_rnk_done || //(rdlvl_stg1_rank_done && ~rdlvl_last_byte_done) || //(stg1_wr_done && (init_state_r == INIT_REFRESH) && //~(rnk_ref_cnt && rdlvl_last_byte_done)) || // Increment chip_cnt_r to issue Refresh to second rank (~pi_dqs_found_all_r && (init_state_r==INIT_PRECHARGE_PREWAIT) && (cnt_cmd_r=='d36)) || // Increment chip_cnt_r when DQSFOUND done for the Rank (pi_dqs_found_rank_done && ~pi_dqs_found_rank_done_r) || ((init_state_r == INIT_LOAD_MR_WAIT)&& cnt_cmd_done_r && wrcal_done) || ((init_state_r == INIT_DDR2_MULTI_RANK) && (DRAM_TYPE == "DDR2"))) begin if ((~mem_init_done_r || ~rdlvl_stg1_done || ~pi_dqs_found_done || // condition to increment chip_cnt during // final burst length programming for DDR3 ~pi_calib_done_r || wrcal_done) //~mpr_rdlvl_done || && (chip_cnt_r != RANKS-1)) chip_cnt_r <= #TCQ chip_cnt_r + 1; else chip_cnt_r <= #TCQ 2'b00; end end endgenerate // verilint STARC-2.2.3.3 off generate if ((REG_CTRL == "ON") && (RANKS == 1)) begin: DDR3_RDIMM_1rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[0] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end end else if (RANKS == 1) begin: DDR3_1rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (n = 0; n < nCS_PER_RANK; n = n + 1) begin phy_int_cs_n[n] <= #TCQ 1'b0; end end else begin //odd CWL for (p = nCS_PER_RANK; p < 2*nCS_PER_RANK; p = p + 1) begin phy_int_cs_n[p] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end end else if ((REG_CTRL == "ON") && (RANKS == 2)) begin: DDR3_2rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; case (chip_cnt_r) 2'b00:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[0] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end 2'b01:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[1] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1+1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end endcase end end end else if (RANKS == 2) begin: DDR3_2rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; case (chip_cnt_r) 2'b00:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (n = 0; n < nCS_PER_RANK; n = n + 1) begin phy_int_cs_n[n] <= #TCQ 1'b0; end end else begin // odd CWL for (p = CS_WIDTH*nCS_PER_RANK; p < (CS_WIDTH*nCS_PER_RANK + nCS_PER_RANK); p = p + 1) begin phy_int_cs_n[p] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end 2'b01:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (q = nCS_PER_RANK; q < (2 * nCS_PER_RANK); q = q + 1) begin phy_int_cs_n[q] <= #TCQ 1'b0; end end else begin // odd CWL for (m = (nCS_PER_RANK*CS_WIDTH + nCS_PER_RANK); m < (nCS_PER_RANK*CS_WIDTH + 2*nCS_PER_RANK); m = m + 1) begin phy_int_cs_n[m] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end endcase end end // always @ (posedge clk) end // verilint STARC-2.2.3.3 on // commented out for now. Need it for DDR2 2T timing /* end else begin: DDR2 always @(posedge clk) if (rst) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end else begin if (init_state_r == INIT_REG_WRITE) begin // All ranks selected simultaneously phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}}; end else if ((wrlvl_odt) || (init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH)) begin phy_int_cs_n[0] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end // else: !if(rst) end // block: DDR2 */ endgenerate assign phy_cs_n = phy_int_cs_n; //*************************************************************************** // Write/read burst logic for calibration //*************************************************************************** assign rdlvl_wr = (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE); assign rdlvl_rd = (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_MPR_READ) || (init_state_r == INIT_WRCAL_MULT_READS); assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd; assign mmcm_wr = (init_state_r == INIT_OCAL_CENTER_WRITE); //used to de-assert cs_n during centering // assign mmcm_wr = 'b0; // (init_state_r == INIT_OCAL_CENTER_WRITE); //*************************************************************************** // Address generation and logic to count # of writes/reads issued during // certain stages of calibration //*************************************************************************** // Column address generation logic: // Keep track of the current column address - since all bursts are in // increments of 8 only during calibration, we need to keep track of // addresses [COL_WIDTH-1:3], lower order address bits will always = 0 always @(posedge clk) if (rst || wrcal_done) burst_addr_r <= #TCQ 1'b0; else if ((init_state_r == INIT_WRCAL_ACT_WAIT) || (init_state_r == INIT_OCLKDELAY_ACT_WAIT) || (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS) || (init_state_r == INIT_WRCAL_READ_WAIT)) burst_addr_r <= #TCQ 1'b1; else if (rdlvl_wr_rd && new_burst_r) burst_addr_r <= #TCQ ~burst_addr_r; else burst_addr_r <= #TCQ 1'b0; // Read Level Stage 1 requires writes to the entire row since // a PRBS pattern is being written. This counter keeps track // of the number of writes which depends on the column width // The (stg1_wr_rd_cnt==9'd0) condition was added so the col // address wraps around during stage1 reads always @(posedge clk) if (rst || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && ~rdlvl_stg1_done)) stg1_wr_rd_cnt <= #TCQ NUM_STG1_WR_RD; else if (rdlvl_last_byte_done || (stg1_wr_rd_cnt == 9'd1) || (prbs_rdlvl_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || (init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) ) begin if (~complex_row0_wr_done || wr_victim_inc || (complex_row1_wr_done && (~complex_row0_rd_done || (complex_row0_rd_done && complex_row1_rd_done)))) stg1_wr_rd_cnt <= #TCQ 'd127; else stg1_wr_rd_cnt <= #TCQ prbs_rdlvl_done?'d30 :'d22; end else if (((init_state_r == INIT_RDLVL_STG1_WRITE) && new_burst_r && ~phy_data_full) ||((init_state_r == INIT_RDLVL_COMPLEX_READ) && rdlvl_stg1_done)) stg1_wr_rd_cnt <= #TCQ stg1_wr_rd_cnt - 1; always @(posedge clk) if (rst) wr_victim_inc <= #TCQ 1'b0; else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2) && ~stg1_wr_done) wr_victim_inc <= #TCQ 1'b1; else wr_victim_inc <= #TCQ 1'b0; always @(posedge clk) reset_rd_addr_r1 <= #TCQ reset_rd_addr; generate if (FIXED_VICTIM == "FALSE") begin: row_cnt_victim_rotate always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt == DQ_WIDTH*2-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) complex_row_cnt <= #TCQ 'd0; else if ((((stg1_wr_rd_cnt == 'd22) && ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (complex_rdlvl_int_ref_req && (init_state_r == INIT_REFRESH_WAIT) && (cnt_cmd_r == 'd127)))) || complex_victim_inc || (complex_sample_cnt_inc_r2 && ~complex_victim_inc) || wr_victim_inc || reset_rd_addr_r1)) begin // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 if ((complex_row_cnt < DQ_WIDTH*2-1) && ~stg1_wr_done) complex_row_cnt <= #TCQ complex_row_cnt + 1; // During reads row count requires different conditions for increments else if (stg1_wr_done) begin if (reset_rd_addr_r1) complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16; // When looping multiple times in the same victim bit in a byte else if (complex_sample_cnt_inc_r2 && ~complex_victim_inc) complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16 + rd_victim_sel*2; // When looping through victim bits within a byte else if (complex_row_cnt < pi_stg2_prbs_rdlvl_cnt*16+15) complex_row_cnt <= #TCQ complex_row_cnt + 1; // When the number of samples is done and tap is incremented within a byte else complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16; end end end else begin: row_cnt_victim_fixed always @(posedge clk) if (rst || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) complex_row_cnt <= #TCQ 'd0; else if ((stg1_wr_rd_cnt == 'd22) && (((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) && (complex_wait_cnt == 'd15)) || complex_rdlvl_int_ref_req)) complex_row_cnt <= #TCQ 'd1; else complex_row_cnt <= #TCQ 'd0; end endgenerate //row count always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done_pulse || complex_byte_rd_done) complex_row_cnt_ocal <= #TCQ 'd0; else if ( prbs_rdlvl_done && (((stg1_wr_rd_cnt == 'd30) && (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE)) || (complex_sample_cnt_inc_r2) || wr_victim_inc)) begin // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 if (complex_row_cnt_ocal < COMPLEX_ROW_CNT_BYTE-1) begin complex_row_cnt_ocal <= #TCQ complex_row_cnt_ocal + 1; end end always @(posedge clk) if (rst) complex_odt_ext <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE)) complex_odt_ext <= #TCQ 1'b0; else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd1) && (init_state_r == INIT_RDLVL_STG1_WRITE)) complex_odt_ext <= #TCQ 1'b1; always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt == DQ_WIDTH*2-1))) begin wr_victim_sel <= #TCQ 'd0; wr_byte_cnt <= #TCQ 'd0; end else if (rdlvl_stg1_done_r1 && wr_victim_inc) begin wr_victim_sel <= #TCQ wr_victim_sel + 1; if (wr_victim_sel == 'd7) wr_byte_cnt <= #TCQ wr_byte_cnt + 1; end always @(posedge clk) if (rst) begin wr_victim_sel_ocal <= #TCQ 'd0; end else if (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) begin wr_victim_sel_ocal <= #TCQ 'd0; end else if (prbs_rdlvl_done && wr_victim_inc) begin wr_victim_sel_ocal <= #TCQ wr_victim_sel_ocal + 1; end always @(posedge clk) if (rst) begin victim_sel <= #TCQ 'd0; victim_byte_cnt <= #TCQ 'd0; end else if ((~stg1_wr_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_wr_done)) begin victim_sel <= #TCQ prbs_rdlvl_done? wr_victim_sel_ocal: wr_victim_sel; victim_byte_cnt <= #TCQ prbs_rdlvl_done? complex_oclkdelay_calib_cnt:wr_byte_cnt; end else begin if( (init_state_r == INIT_RDLVL_COMPLEX_ACT) || reset_rd_addr) victim_sel <= #TCQ prbs_rdlvl_done? complex_ocal_rd_victim_sel:rd_victim_sel; victim_byte_cnt <= #TCQ prbs_rdlvl_done? complex_oclkdelay_calib_cnt:pi_stg2_prbs_rdlvl_cnt; end generate if (FIXED_VICTIM == "FALSE") begin: wr_done_victim_rotate always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt < DQ_WIDTH*2-1) && ~prbs_rdlvl_done) || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done || prbs_rdlvl_done_pulse) begin complex_row0_wr_done <= #TCQ 1'b0; end else if ( rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd2)) begin complex_row0_wr_done <= #TCQ 1'b1; end always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt < DQ_WIDTH*2-1) && ~prbs_rdlvl_done) || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done || prbs_rdlvl_done_pulse) begin complex_row1_wr_done <= #TCQ 1'b0; end else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2)) begin complex_row1_wr_done <= #TCQ 1'b1; end end else begin: wr_done_victim_fixed always @(posedge clk) if (rst || prbs_rdlvl_done_pulse || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done ) begin complex_row0_wr_done <= #TCQ 1'b0; end else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd2)) begin complex_row0_wr_done <= #TCQ 1'b1; end always @(posedge clk) if (rst || prbs_rdlvl_done_pulse || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done ) begin complex_row1_wr_done <= #TCQ 1'b0; end else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2)) begin complex_row1_wr_done <= #TCQ 1'b1; end end endgenerate always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row0_rd_done <= #TCQ 1'b0; else if (complex_sample_cnt_inc) complex_row0_rd_done <= #TCQ 1'b0; else if ( (prbs_rdlvl_start || complex_oclkdelay_calib_start_int) && (stg1_wr_rd_cnt == 9'd2) && complex_row0_wr_done && complex_row1_wr_done) complex_row0_rd_done <= #TCQ 1'b1; always @(posedge clk) complex_row0_rd_done_r1 <= #TCQ complex_row0_rd_done; always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row1_rd_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE)) complex_row1_rd_done <= #TCQ 1'b0; else if (complex_row0_rd_done && (stg1_wr_rd_cnt == 9'd2)) complex_row1_rd_done <= #TCQ 1'b1; always @(posedge clk) complex_row1_rd_done_r1 <= #TCQ complex_row1_rd_done; //calculate row rd num for complex_oclkdelay_calib //once it reached to 8 always @ (posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row1_rd_cnt <= #TCQ 'd0; else complex_row1_rd_cnt <= #TCQ (complex_row1_rd_done & ~complex_row1_rd_done_r1) ? ((complex_row1_rd_cnt == (COMPLEX_RD-1))? 0:complex_row1_rd_cnt + 'd1) : complex_row1_rd_cnt; //For write, reset rd_done for the byte always @ (posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_STG1_WRITE) || prbs_rdlvl_done_pulse) complex_byte_rd_done <= #TCQ 'b0; else if (prbs_rdlvl_done && (complex_row1_rd_cnt == (COMPLEX_RD-1)) && (complex_row1_rd_done & ~complex_row1_rd_done_r1)) complex_byte_rd_done <= #TCQ 'b1; end always @ (posedge clk) begin complex_byte_rd_done_r1 <= #TCQ complex_byte_rd_done; complex_ocal_num_samples_inc <= #TCQ (complex_byte_rd_done & ~complex_byte_rd_done_r1); end generate if (RANKS < 2) begin: one_rank_complex always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || ( complex_oclkdelay_calib_done && (init_state_r == INIT_RDLVL_STG1_WRITE )) || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT) || prbs_rdlvl_done_pulse ) complex_wr_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; else if ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; end else begin: dual_rank_complex always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || ( complex_oclkdelay_calib_done && (init_state_r == INIT_RDLVL_STG1_WRITE )) || (rdlvl_stg1_rank_done ) || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT) || prbs_rdlvl_done_pulse ) complex_wr_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; else if ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst) complex_wait_cnt <= #TCQ 'd0; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && complex_wait_cnt < 'd15) complex_wait_cnt <= #TCQ complex_wait_cnt + 1; else complex_wait_cnt <= #TCQ 'd0; always @(posedge clk) if (rst) begin complex_num_reads <= #TCQ 'd1; end else if ((((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd14)) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && ext_int_ref_req && (cnt_cmd_r == 'd127))) && ~complex_row0_rd_done) begin if (stg1_wr_rd_cnt > 'd85) begin if (complex_num_reads < 'd6) complex_num_reads <= #TCQ complex_num_reads + 1; else complex_num_reads <= #TCQ 'd1; // Initila value for VCCAUX pattern is 3, 7, and 12 end else if (stg1_wr_rd_cnt > 'd73) begin if (stg1_wr_rd_cnt == 'd85) complex_num_reads <= #TCQ 'd3; else if (complex_num_reads < 'd5) complex_num_reads <= #TCQ complex_num_reads + 1; end else if (stg1_wr_rd_cnt > 'd39) begin if (stg1_wr_rd_cnt == 'd73) complex_num_reads <= #TCQ 'd7; else if (complex_num_reads < 'd10) complex_num_reads <= #TCQ complex_num_reads + 1; end else begin if (stg1_wr_rd_cnt == 'd39) complex_num_reads <= #TCQ 'd12; else if (complex_num_reads < 'd14) complex_num_reads <= #TCQ complex_num_reads + 1; end // Initialize to 1 at the start of reads or after precharge and activate end else if ((((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && ~ext_int_ref_req) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && (stg1_wr_rd_cnt == 'd22))) complex_num_reads <= #TCQ 'd1; always @(posedge clk) if (rst) complex_num_reads_dec <= #TCQ 'd1; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) complex_num_reads_dec <= #TCQ complex_num_reads; else if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (complex_num_reads_dec > 'd0)) complex_num_reads_dec <= #TCQ complex_num_reads_dec - 1; always @(posedge clk) if (rst) complex_address <= #TCQ 'd0; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ_WAIT)) || ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (init_state_r1 != INIT_OCAL_COMPLEX_WRITE_WAIT))) complex_address <= #TCQ phy_address[COL_WIDTH-1:0]; always @ (posedge clk) if (rst) complex_oclkdelay_calib_start_int <= #TCQ 'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && prbs_last_byte_done_r) // changed for new algo 3/26 complex_oclkdelay_calib_start_int <= #TCQ 'b1; always @(posedge clk) begin complex_oclkdelay_calib_start_r1 <= #TCQ complex_oclkdelay_calib_start_int; complex_oclkdelay_calib_start_r2 <= #TCQ complex_oclkdelay_calib_start_r1; end always @ (posedge clk) if (rst) complex_oclkdelay_calib_start <= #TCQ 'b0; else if (complex_oclkdelay_calib_start_int && (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT) && prbs_rdlvl_done) // changed for new algo 3/26 complex_oclkdelay_calib_start <= #TCQ 'b1; //packet fragmentation for complex oclkdealy calib write always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) begin complex_num_writes <= #TCQ 'd1; end else if ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14) && ~complex_row0_wr_done) begin if (stg1_wr_rd_cnt > 'd85) begin if (complex_num_writes < 'd6) complex_num_writes <= #TCQ complex_num_writes + 1; else complex_num_writes <= #TCQ 'd1; // Initila value for VCCAUX pattern is 3, 7, and 12 end else if (stg1_wr_rd_cnt > 'd73) begin if (stg1_wr_rd_cnt == 'd85) complex_num_writes <= #TCQ 'd3; else if (complex_num_writes < 'd5) complex_num_writes <= #TCQ complex_num_writes + 1; end else if (stg1_wr_rd_cnt > 'd39) begin if (stg1_wr_rd_cnt == 'd73) complex_num_writes <= #TCQ 'd7; else if (complex_num_writes < 'd10) complex_num_writes <= #TCQ complex_num_writes + 1; end else begin if (stg1_wr_rd_cnt == 'd39) complex_num_writes <= #TCQ 'd12; else if (complex_num_writes < 'd14) complex_num_writes <= #TCQ complex_num_writes + 1; end // Initialize to 1 at the start of write or after precharge and activate end else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row0_wr_done) complex_num_writes <= #TCQ 'd30; else if (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) complex_num_writes <= #TCQ 'd1; always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_num_writes_dec <= #TCQ 'd1; else if (((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) complex_num_writes_dec <= #TCQ complex_num_writes; else if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (complex_num_writes_dec > 'd0)) complex_num_writes_dec <= #TCQ complex_num_writes_dec - 1; always @(posedge clk) if (rst) complex_sample_cnt_inc_ocal <= #TCQ 1'b0; else if ((stg1_wr_rd_cnt == 9'd1) && complex_byte_rd_done && prbs_rdlvl_done) complex_sample_cnt_inc_ocal <= #TCQ 1'b1; else complex_sample_cnt_inc_ocal <= #TCQ 1'b0; always @(posedge clk) if (rst) complex_sample_cnt_inc <= #TCQ 1'b0; else if ((stg1_wr_rd_cnt == 9'd1) && complex_row1_rd_done) complex_sample_cnt_inc <= #TCQ 1'b1; else complex_sample_cnt_inc <= #TCQ 1'b0; always @(posedge clk) begin complex_sample_cnt_inc_r1 <= #TCQ complex_sample_cnt_inc; complex_sample_cnt_inc_r2 <= #TCQ complex_sample_cnt_inc_r1; end //complex refresh req always @ (posedge clk) begin if(rst || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_ACT)) ) complex_ocal_ref_done <= #TCQ 1'b1; else if (init_state_r == INIT_RDLVL_STG1_WRITE) complex_ocal_ref_done <= #TCQ 1'b0; end //complex ocal odt extention always @(posedge clk) if (rst) complex_ocal_odt_ext <= #TCQ 1'b0; else if (((init_state_r == INIT_PRECHARGE_PREWAIT) && cnt_cmd_done_m7_r) || (init_state_r == INIT_OCLKDELAY_READ_WAIT)) complex_ocal_odt_ext <= #TCQ 1'b0; else if ((init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT)) complex_ocal_odt_ext <= #TCQ 1'b1; // OCLKDELAY calibration requires multiple writes because // write can be up to 2 cycles early since OCLKDELAY tap // can go down to 0 always @(posedge clk) if (rst || (init_state_r == INIT_OCLKDELAY_WRITE_WAIT) || (oclk_wr_cnt == 4'd0)) oclk_wr_cnt <= #TCQ NUM_STG1_WR_RD; else if ((init_state_r == INIT_OCLKDELAY_WRITE) && new_burst_r && ~phy_data_full) oclk_wr_cnt <= #TCQ oclk_wr_cnt - 1; // Write calibration requires multiple writes because // write can be up to 2 cycles early due to new write // leveling algorithm to avoid late writes always @(posedge clk) if (rst || (init_state_r == INIT_WRCAL_WRITE_READ) || (wrcal_wr_cnt == 4'd0)) wrcal_wr_cnt <= #TCQ NUM_STG1_WR_RD; else if ((init_state_r == INIT_WRCAL_WRITE) && new_burst_r && ~phy_data_full) wrcal_wr_cnt <= #TCQ wrcal_wr_cnt - 1; generate if(nCK_PER_CLK == 4) begin:back_to_back_reads_4_1 // 4 back-to-back reads with gaps for // read data_offset calibration (rdlvl stage 2) always @(posedge clk) if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) num_reads <= #TCQ 3'b000; else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) num_reads <= #TCQ num_reads - 1; else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || phy_cmd_full && new_burst_r) num_reads <= #TCQ 3'b011; end else if(nCK_PER_CLK == 2) begin: back_to_back_reads_2_1 // 4 back-to-back reads with gaps for // read data_offset calibration (rdlvl stage 2) always @(posedge clk) if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) num_reads <= #TCQ 3'b000; else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) num_reads <= #TCQ num_reads - 1; else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || phy_cmd_full && new_burst_r) num_reads <= #TCQ 3'b111; end endgenerate // back-to-back reads during write calibration always @(posedge clk) if (rst ||(init_state_r == INIT_WRCAL_READ_WAIT)) wrcal_reads <= #TCQ 2'b00; else if ((wrcal_reads > 2'b00) && ~(phy_ctl_full || phy_cmd_full)) wrcal_reads <= #TCQ wrcal_reads - 1; else if ((init_state_r == INIT_WRCAL_MULT_READS) || phy_ctl_full || phy_cmd_full && new_burst_r) wrcal_reads <= #TCQ 'd255; // determine how often to issue row command during read leveling writes // and reads always @(posedge clk) if (rdlvl_wr_rd) begin // 2:1 mode - every other command issued is a data command // 4:1 mode - every command issued is a data command if (nCK_PER_CLK == 2) begin if (!phy_ctl_full) new_burst_r <= #TCQ ~new_burst_r; end else new_burst_r <= #TCQ 1'b1; end else new_burst_r <= #TCQ 1'b1; // indicate when a write is occurring. PHY_WRDATA_EN must be asserted // simultaneous with the corresponding command/address for CWL = 5,6 always @(posedge clk) begin rdlvl_wr_r <= #TCQ rdlvl_wr; calib_wrdata_en <= #TCQ phy_wrdata_en; end always @(posedge clk) begin if (rst || wrcal_done) extend_cal_pat <= #TCQ 1'b0; else if (temp_lmr_done && (PRE_REV3ES == "ON")) extend_cal_pat <= #TCQ 1'b1; end generate if ((nCK_PER_CLK == 4) || (BURST_MODE == "4")) begin: wrdqen_div4 // Write data enable asserted for one DIV4 clock cycle // Only BL8 supported with DIV4. DDR2 BL4 will use DIV2. always @(*) begin if (~phy_data_full && ((init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_WRCAL_WRITE))) phy_wrdata_en = 1'b1; else phy_wrdata_en = 1'b0; end end else begin: wrdqen_div2 // block: wrdqen_div4 always @(*) if((rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full) | phy_wrdata_en_r1) phy_wrdata_en = 1'b1; else phy_wrdata_en = 1'b0; always @(posedge clk) phy_wrdata_en_r1 <= #TCQ rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full; always @(posedge clk) begin if (!phy_wrdata_en & first_rdlvl_pat_r) wrdata_pat_cnt <= #TCQ 2'b00; else if (wrdata_pat_cnt == 2'b11) wrdata_pat_cnt <= #TCQ 2'b10; else wrdata_pat_cnt <= #TCQ wrdata_pat_cnt + 1; end always @(posedge clk) begin if (!phy_wrdata_en & first_wrcal_pat_r) wrcal_pat_cnt <= #TCQ 2'b00; else if (extend_cal_pat && (wrcal_pat_cnt == 2'b01)) wrcal_pat_cnt <= #TCQ 2'b00; else if (wrcal_pat_cnt == 2'b11) wrcal_pat_cnt <= #TCQ 2'b10; else wrcal_pat_cnt <= #TCQ wrcal_pat_cnt + 1; end end endgenerate // indicate when a write is occurring. PHY_RDDATA_EN must be asserted // simultaneous with the corresponding command/address. PHY_RDDATA_EN // is used during read-leveling to determine read latency assign phy_rddata_en = ~phy_if_empty; // Read data valid generation for MC and User Interface after calibration is // complete assign phy_rddata_valid = init_complete_r1_timing ? phy_rddata_en : 1'b0; //*************************************************************************** // Generate training data written at start of each read-leveling stage // For every stage of read leveling, 8 words are written into memory // The format is as follows (shown as {rise,fall}): // Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0 // Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 //*************************************************************************** always @(posedge clk) if ((init_state_r == INIT_IDLE) || (init_state_r == INIT_RDLVL_STG1_WRITE)) cnt_init_data_r <= #TCQ 2'b00; else if (phy_wrdata_en) cnt_init_data_r <= #TCQ cnt_init_data_r + 1; else if (init_state_r == INIT_WRCAL_WRITE) cnt_init_data_r <= #TCQ 2'b10; // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling always @(posedge clk) if (rst || rdlvl_stg1_rank_done) first_rdlvl_pat_r <= #TCQ 1'b1; else if (phy_wrdata_en && (init_state_r == INIT_RDLVL_STG1_WRITE)) first_rdlvl_pat_r <= #TCQ 1'b0; always @(posedge clk) if (rst || wrcal_resume || (init_state_r == INIT_WRCAL_ACT_WAIT)) first_wrcal_pat_r <= #TCQ 1'b1; else if (phy_wrdata_en && (init_state_r == INIT_WRCAL_WRITE)) first_wrcal_pat_r <= #TCQ 1'b0; generate if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 2)) begin: wrdq_div2_2to1_rdlvl_first always @(posedge clk) if (~oclkdelay_calib_done) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}}; else if (!rdlvl_stg1_done) begin // The 16 words for stage 1 write data in 2:1 mode is written // over 4 consecutive controller clock cycles. Note that write // data follows phy_wrdata_en by one clock cycle case (wrdata_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}}, {DQ_WIDTH/4{4'h9}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end endcase end else if (!prbs_rdlvl_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ end else if (!wrcal_done) begin case (wrcal_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h5}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, {DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h4}}}; end endcase end end else if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 4)) begin: wrdq_div2_4to1_rdlvl_first always @(posedge clk) if (~oclkdelay_calib_done) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; else if (!rdlvl_stg1_done && ~phy_data_full) // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling if (first_rdlvl_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; else // For all others, change the first two words written in order // to differentiate the "early write" and "on-time write" // readback patterns during read leveling phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; else if (~(prbs_rdlvl_done || prbs_last_byte_done_r) && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ else if (!wrcal_done) if (first_wrcal_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (nCK_PER_CLK == 4) begin: wrdq_div1_4to1_wrcal_first always @(posedge clk) if ((~oclkdelay_calib_done) && (DRAM_TYPE == "DDR3")) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; else if ((!wrcal_done)&& (DRAM_TYPE == "DDR3")) begin if (extend_cal_pat) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else if (first_wrcal_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (!rdlvl_stg1_done && ~phy_data_full) begin // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling if (first_rdlvl_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; else // For all others, change the first two words written in order // to differentiate the "early write" and "on-time write" // readback patterns during read leveling phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (!prbs_rdlvl_done && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ else if (!complex_oclkdelay_calib_done && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; end else begin: wrdq_div1_2to1_wrcal_first always @(posedge clk) if ((~oclkdelay_calib_done)&& (DRAM_TYPE == "DDR3")) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}}; else if ((!wrcal_done) && (DRAM_TYPE == "DDR3"))begin case (wrcal_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h5}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, {DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h4}}}; end endcase end else if (!rdlvl_stg1_done) begin // The 16 words for stage 1 write data in 2:1 mode is written // over 4 consecutive controller clock cycles. Note that write // data follows phy_wrdata_en by one clock cycle case (wrdata_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}}, {DQ_WIDTH/4{4'h9}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end endcase end else if (!prbs_rdlvl_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ end else if (!complex_oclkdelay_calib_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; end end endgenerate //*************************************************************************** // Memory control/address //*************************************************************************** // Phases [2] and [3] are always deasserted for 4:1 mode generate if (nCK_PER_CLK == 4) begin: gen_div4_ca_tieoff always @(posedge clk) begin phy_ras_n[3:2] <= #TCQ 3'b11; phy_cas_n[3:2] <= #TCQ 3'b11; phy_we_n[3:2] <= #TCQ 3'b11; end end endgenerate // Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging // (4) auto refresh // verilint STARC-2.7.3.3b off generate if (!(CWL_M % 2)) begin: even_cwl always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT))begin phy_ras_n[0] <= #TCQ 1'b0; phy_ras_n[1] <= #TCQ 1'b1; end else begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b1; end end // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command // (3) auto refresh always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_REFRESH) || (rdlvl_wr_rd && new_burst_r))begin phy_cas_n[0] <= #TCQ 1'b0; phy_cas_n[1] <= #TCQ 1'b1; end else begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b1; end end // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only // occur during read leveling), (3) Issuing ZQ Long Calib command, // (4) Precharge always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE)|| (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (rdlvl_wr && new_burst_r))begin phy_we_n[0] <= #TCQ 1'b0; phy_we_n[1] <= #TCQ 1'b1; end else begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b1; end end end else begin: odd_cwl always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_REFRESH))begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b0; end else begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b1; end end // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command // (3) auto refresh always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_REFRESH) || (rdlvl_wr_rd && new_burst_r))begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b0; end else begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b1; end end // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only // occur during read leveling), (3) Issuing ZQ Long Calib command, // (4) Precharge always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE)|| (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (rdlvl_wr && new_burst_r))begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b0; end else begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b1; end end end endgenerate // verilint STARC-2.7.3.3b on // Assign calib_cmd for the command field in PHY_Ctl_Word always @(posedge clk) begin if (wr_level_dqs_asrt) begin // Request to toggle DQS during write leveling calib_cmd <= #TCQ 3'b001; if (CWL_M % 2) begin // odd write latency calib_data_offset_0 <= #TCQ CWL_M + 3; calib_data_offset_1 <= #TCQ CWL_M + 3; calib_data_offset_2 <= #TCQ CWL_M + 3; calib_cas_slot <= #TCQ 2'b01; end else begin // even write latency calib_data_offset_0 <= #TCQ CWL_M + 2; calib_data_offset_1 <= #TCQ CWL_M + 2; calib_data_offset_2 <= #TCQ CWL_M + 2; calib_cas_slot <= #TCQ 2'b00; end end else if (rdlvl_wr && new_burst_r) begin // Write Command calib_cmd <= #TCQ 3'b001; if (CWL_M % 2) begin // odd write latency calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_cas_slot <= #TCQ 2'b01; end else begin // even write latency calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_cas_slot <= #TCQ 2'b00; end end else if (rdlvl_rd && new_burst_r) begin // Read Command calib_cmd <= #TCQ 3'b011; if (CWL_M % 2) calib_cas_slot <= #TCQ 2'b01; else calib_cas_slot <= #TCQ 2'b00; if (~pi_calib_done_r1) begin calib_data_offset_0 <= #TCQ 6'd0; calib_data_offset_1 <= #TCQ 6'd0; calib_data_offset_2 <= #TCQ 6'd0; end else if (~pi_dqs_found_done_r1) begin calib_data_offset_0 <= #TCQ rd_data_offset_0; calib_data_offset_1 <= #TCQ rd_data_offset_1; calib_data_offset_2 <= #TCQ rd_data_offset_2; end else begin calib_data_offset_0 <= #TCQ rd_data_offset_ranks_0[6*chip_cnt_r+:6]; calib_data_offset_1 <= #TCQ rd_data_offset_ranks_1[6*chip_cnt_r+:6]; calib_data_offset_2 <= #TCQ rd_data_offset_ranks_2[6*chip_cnt_r+:6]; end end else begin // Non-Data Commands like NOP, MRS, ZQ Long Cal, Precharge, // Active, Refresh calib_cmd <= #TCQ 3'b100; calib_data_offset_0 <= #TCQ 6'd0; calib_data_offset_1 <= #TCQ 6'd0; calib_data_offset_2 <= #TCQ 6'd0; if (CWL_M % 2) calib_cas_slot <= #TCQ 2'b01; else calib_cas_slot <= #TCQ 2'b00; end end // Write Enable to PHY_Control FIFO always asserted // No danger of this FIFO being Full with 4:1 sync clock ratio // This is also the write enable to the command OUT_FIFO always @(posedge clk) begin if (rst) begin calib_ctl_wren <= #TCQ 1'b0; calib_cmd_wren <= #TCQ 1'b0; calib_seq <= #TCQ 2'b00; end else if (cnt_pwron_cke_done_r && phy_ctl_ready && ~(phy_ctl_full || phy_cmd_full )) begin calib_ctl_wren <= #TCQ 1'b1; calib_cmd_wren <= #TCQ 1'b1; calib_seq <= #TCQ calib_seq + 1; end else begin calib_ctl_wren <= #TCQ 1'b0; calib_cmd_wren <= #TCQ 1'b0; calib_seq <= #TCQ calib_seq; end end generate genvar rnk_i; for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk always @(posedge clk) begin if (rst) begin mr2_r[rnk_i] <= #TCQ 2'b00; mr1_r[rnk_i] <= #TCQ 3'b000; end else begin mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i]; mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i]; end end end endgenerate // ODT assignment based on slot config and slot present // For single slot systems slot_1_present input will be ignored // Assuming component interfaces to be single slot systems generate if (nSLOTS == 1) begin: gen_single_slot_odt always @(posedge clk) begin if (rst) begin tmp_mr2_r[1] <= #TCQ 2'b00; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; tmp_mr1_r[1] <= #TCQ 3'b000; tmp_mr1_r[2] <= #TCQ 3'b000; tmp_mr1_r[3] <= #TCQ 3'b000; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; phy_tmp_odt_r <= #TCQ 4'b0000; phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; end else begin case ({slot_0_present[0],slot_0_present[1], slot_0_present[2],slot_0_present[3]}) // Single slot configuration with quad rank // Assuming same behavior as single slot dual rank for now // DDR2 does not have quad rank parts 4'b1111: begin if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 RTT_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 RTT_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end phy_tmp_odt_r <= #TCQ 4'b0001; // Chip Select assignments phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) ) +: nCS_PER_RANK] <= #TCQ 'b0; end // Single slot configuration with single rank 4'b1000: begin phy_tmp_odt_r <= #TCQ 4'b0001; if ((REG_CTRL == "ON") && (nCS_PER_RANK > 1)) begin phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0; end else begin phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; end if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && ((cnt_init_mr_r == 2'd0) || (USE_ODT_PORT == 1)))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 RTT_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 RTT_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Single slot configuration with dual rank 4'b1100: begin phy_tmp_odt_r <= #TCQ 4'b0001; // Chip Select assignments phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) ) +: nCS_PER_RANK] <= #TCQ 'b0; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end default: begin phy_tmp_odt_r <= #TCQ 4'b0001; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end endcase end end end else if (nSLOTS == 2) begin: gen_dual_slot_odt always @ (posedge clk) begin if (rst) begin tmp_mr2_r[1] <= #TCQ 2'b00; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; tmp_mr1_r[1] <= #TCQ 3'b000; tmp_mr1_r[2] <= #TCQ 3'b000; tmp_mr1_r[3] <= #TCQ 3'b000; phy_tmp_odt_r <= #TCQ 4'b0000; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; end else begin case ({slot_0_present[0],slot_0_present[1], slot_1_present[0],slot_1_present[1]}) // Two slot configuration, one slot present, single rank 4'b10_00: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end 4'b00_10: begin //Rank1 ODT enabled if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank1 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank1 Rtt_NOM defaults to 120 ohms tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Two slot configuration, one slot present, dual rank 4'b00_11: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end 4'b11_00: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank1 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Two slot configuration, one rank per slot 4'b10_10: begin if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r == 2'b00)begin phy_tmp_odt_r <= #TCQ 4'b0010; //bit0 for rank0 end else begin phy_tmp_odt_r <= #TCQ 4'b0001; //bit0 for rank0 end end else begin if((init_state_r == INIT_WRLVL_WAIT) || (init_next_state == INIT_RDLVL_STG1_WRITE) || (init_next_state == INIT_WRCAL_WRITE) || (init_next_state == INIT_OCAL_CENTER_WRITE) || (init_next_state == INIT_OCLKDELAY_WRITE)) phy_tmp_odt_r <= #TCQ 4'b0011; // bit0 for rank0/1 (write) else if ((init_next_state == INIT_PI_PHASELOCK_READS) || (init_next_state == INIT_MPR_READ) || (init_next_state == INIT_RDLVL_STG1_READ) || (init_next_state == INIT_RDLVL_COMPLEX_READ) || (init_next_state == INIT_RDLVL_STG2_READ) || (init_next_state == INIT_OCLKDELAY_READ) || (init_next_state == INIT_WRCAL_READ) || (init_next_state == INIT_WRCAL_MULT_READS)) phy_tmp_odt_r <= #TCQ 4'b0010; // bit0 for rank1 (rank 0 rd) end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_WR == "60") ? 3'b001 : (RTT_WR == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; end end // Two Slots - One slot with dual rank and other with single rank 4'b10_11: begin //Rank3 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[1] <= #TCQ 3'b000; end //Slot1 Rank1 or Rank3 is being written if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r == 2'b00)begin phy_tmp_odt_r <= #TCQ 4'b0010; end else begin phy_tmp_odt_r <= #TCQ 4'b0001; end end else begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0011; //Slot0 Rank0 is being written end else begin phy_tmp_odt_r <= #TCQ 4'b0101; // ODT for ranks 0 and 2 aserted end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))begin if (chip_cnt_r == 2'b00) begin phy_tmp_odt_r <= #TCQ 4'b0100; end else begin phy_tmp_odt_r <= #TCQ 4'b0001; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end // Two Slots - One slot with dual rank and other with single rank 4'b11_10: begin //Rank2 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : (RTT_NOM2 == "120") ? 3'b010 : (RTT_NOM2 == "20") ? 3'b100 : (RTT_NOM2 == "30") ? 3'b101 : (RTT_NOM2 == "40") ? 3'b011: 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011: 3'b000; //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r[1] == 1'b1)begin phy_tmp_odt_r <= #TCQ 4'b0001; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; // rank 2 ODT asserted end end else begin if (// wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin if (chip_cnt_r[1] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0110; end else begin phy_tmp_odt_r <= #TCQ 4'b0101; end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS)) begin if (chip_cnt_r[1] == 1'b1) begin phy_tmp_odt_r[(1*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ 4'b0010; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end // Two Slots - two ranks per slot 4'b11_11: begin //Rank2 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : (RTT_NOM2 == "120") ? 3'b010 : (RTT_NOM2 == "20") ? 3'b100 : (RTT_NOM2 == "30") ? 3'b101 : (RTT_NOM2 == "40") ? 3'b011 : 3'b000; //Rank3 Rtt_NOM tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 : (RTT_NOM3 == "120") ? 3'b010 : (RTT_NOM3 == "20") ? 3'b100 : (RTT_NOM3 == "30") ? 3'b101 : (RTT_NOM3 == "40") ? 3'b011 : 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[1] <= #TCQ 3'b000; //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r[1] == 1'b1)begin phy_tmp_odt_r <= #TCQ 4'b0001; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; end end else begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin //Slot1 Rank1 or Rank3 is being written if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0110; //Slot0 Rank0 or Rank2 is being written end else begin phy_tmp_odt_r <= #TCQ 4'b1001; end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))begin //Slot1 Rank1 or Rank3 is being read if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0100; //Slot0 Rank0 or Rank2 is being read end else begin phy_tmp_odt_r <= #TCQ 4'b1000; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end default: begin phy_tmp_odt_r <= #TCQ 4'b1111; // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "60") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; end end endcase end end end endgenerate // PHY only supports two ranks. // calib_aux_out[0] is CKE for rank 0 and calib_aux_out[1] is ODT for rank 0 // calib_aux_out[2] is CKE for rank 1 and calib_aux_out[3] is ODT for rank 1 generate if(CKE_ODT_AUX == "FALSE") begin if ((nSLOTS == 1) && (RANKS < 2)) begin always @(posedge clk) if (rst) begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || wrlvl_rank_done || wrlvl_rank_done_r1 || (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt ) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || complex_odt_ext || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_OCAL_CENTER_WRITE) || complex_ocal_odt_ext || (init_state_r == INIT_OCLKDELAY_WRITE)|| (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin // Quad rank in a single slot calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end end end else if ((nSLOTS == 1) && (RANKS <= 2)) begin always @(posedge clk) if (rst) begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt)|| (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || complex_odt_ext || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_OCAL_CENTER_WRITE) || complex_ocal_odt_ext || (init_state_r == INIT_OCLKDELAY_WRITE)|| (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin // Dual rank in a single slot calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end end end else if ((nSLOTS == 2) && (RANKS == 2)) begin always @(posedge clk) if (rst)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if (((DRAM_TYPE == "DDR2") && (RTT_NOM == "DISABLED")) || ((DRAM_TYPE == "DDR3") && (RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // Quad rank in a single slot if (nCK_PER_CLK == 2) begin calib_odt[0] <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; calib_odt[1] <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end // Turn on for idle rank during read if dynamic ODT is enabled in DDR3 end else if(((DRAM_TYPE == "DDR3") && (RTT_WR != "OFF")) && ((init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_MPR_READ) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))) begin if (nCK_PER_CLK == 2) begin calib_odt[0] <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; calib_odt[1] <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end // disable well before next command and before disabling write leveling end else if(cnt_cmd_done_m7_r || (init_state_r == INIT_WRLVL_WAIT && ~wrlvl_odt)) calib_odt <= #TCQ 2'b00; end end end else begin//USE AUX OUTPUT for routing CKE and ODT. if ((nSLOTS == 1) && (RANKS < 2)) begin always @(posedge clk) if (rst) begin calib_aux_out <= #TCQ 4'b0000; end else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done || wrlvl_rank_done_r1 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Quad rank in a single slot calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end else if ((nSLOTS == 1) && (RANKS <= 2)) begin always @(posedge clk) if (rst) begin calib_aux_out <= #TCQ 4'b0000; end else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Dual rank in a single slot calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end else if ((nSLOTS == 2) && (RANKS == 2)) begin always @(posedge clk) if (rst) calib_aux_out <= #TCQ 4'b0000; else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Quad rank in a single slot if (nCK_PER_CLK == 2) begin calib_aux_out[1] <= #TCQ (!calib_aux_out[1]) ? phy_tmp_odt_r[0] : 1'b0; calib_aux_out[3] <= #TCQ (!calib_aux_out[3]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end end endgenerate //***************************************************************** // memory address during init //***************************************************************** always @(posedge clk) phy_data_full_r <= #TCQ phy_data_full; // verilint STARC-2.7.3.3b off always @(*)begin // Bus 0 for address/bank never used address_w = 'b0; bank_w = 'b0; if ((init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_DDR2_PRECHARGE)) begin // Set A10=1 for ZQ long calibration or Precharge All address_w = 'b0; address_w[10] = 1'b1; bank_w = 'b0; end else if (init_state_r == INIT_WRLVL_START) begin // Enable wrlvl in MR1 bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; address_w[7] = 1'b1; end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin // Finished with write leveling, disable wrlvl in MR1 // For single rank disable Rtt_Nom bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin // Set RTT_WR in MR2 after write leveling disabled bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; address_w[10:9] = mr2_r[chip_cnt_r]; end else if (init_state_r == INIT_MPR_READ) begin address_w = 'b0; bank_w = 'b0; end else if (init_state_r == INIT_MPR_RDEN) begin // Enable MPR read with LMR3 and A2=1 bank_w[BANK_WIDTH-1:0] = 'd3; address_w = {ROW_WIDTH{1'b0}}; address_w[2] = 1'b1; end else if (init_state_r == INIT_MPR_DISABLE) begin // Disable MPR read with LMR3 and A2=0 bank_w[BANK_WIDTH-1:0] = 'd3; address_w = {ROW_WIDTH{1'b0}}; end else if ((init_state_r == INIT_REG_WRITE)& (DRAM_TYPE == "DDR3"))begin // bank_w is assigned a 3 bit value. In some // DDR2 cases there will be only two bank bits. //Qualifying the condition with DDR3 bank_w = 'b0; address_w = 'b0; case (reg_ctrl_cnt_r) 4'h1:begin address_w[4:0] = REG_RC1[4:0]; bank_w = REG_RC1[7:5]; end 4'h2: address_w[4:0] = REG_RC2[4:0]; 4'h3: begin address_w[4:0] = REG_RC3[4:0]; bank_w = REG_RC3[7:5]; end 4'h4: begin address_w[4:0] = REG_RC4[4:0]; bank_w = REG_RC4[7:5]; end 4'h5: begin address_w[4:0] = REG_RC5[4:0]; bank_w = REG_RC5[7:5]; end 4'h6: begin address_w[4:0] = REG_RC10[4:0]; bank_w = REG_RC10[7:5]; end 4'h7: begin address_w[4:0] = REG_RC11[4:0]; bank_w = REG_RC11[7:5]; end default: address_w[4:0] = REG_RC0[4:0]; endcase end else if (init_state_r == INIT_LOAD_MR) begin // If loading mode register, look at cnt_init_mr to determine // which MR is currently being programmed address_w = 'b0; bank_w = 'b0; if(DRAM_TYPE == "DDR3")begin if(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done)begin // end of the calibration programming correct // burst length if (TEST_AL == "0") begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //Don't reset DLL end else begin // programming correct AL value bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; if (TEST_AL == "CL-1") address_w[4:3]= 2'b01; // AL="CL-1" else address_w[4:3]= 2'b10; // AL="CL-2" end end else begin case (cnt_init_mr_r) INIT_CNT_MR2: begin bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; address_w[10:9] = mr2_r[chip_cnt_r]; end INIT_CNT_MR3: begin bank_w[1:0] = 2'b11; address_w = load_mr3[ROW_WIDTH-1:0]; end INIT_CNT_MR1: begin bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; end INIT_CNT_MR0: begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; // fixing it to BL8 for calibration address_w[1:0] = 2'b00; end default: begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end endcase end end else begin // DDR2 case (cnt_init_mr_r) INIT_CNT_MR2: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //MRS command without resetting DLL end end INIT_CNT_MR3: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b11; address_w = load_mr3[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //MRS command without resetting DLL. Repeted again // because there is an extra state. end end INIT_CNT_MR1: begin bank_w[1:0] = 2'b01; if(~ddr2_refresh_flag_r)begin address_w = load_mr1[ROW_WIDTH-1:0]; end else begin // second set of lm commands address_w = load_mr1[ROW_WIDTH-1:0]; address_w[9:7] = 3'b111; //OCD default state end end INIT_CNT_MR0: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin // always disable odt for rank 1 and rank 3 as per SPEC address_w[2] = 'b0; address_w[6] = 'b0; end //OCD exit end end default: begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end endcase end end else if ( ~prbs_rdlvl_done && ((init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin // Writing and reading PRBS pattern for read leveling stage 1 // Need to support burst length 4 or 8. PRBS pattern will be // written to entire row and read back from the same row repeatedly bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (((stg1_wr_rd_cnt == NUM_STG1_WR_RD) && ~rdlvl_stg1_done) || (stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd22) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; end else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ) )// || // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; else address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end //need to add address for complex oclkdelay calib end else if (prbs_rdlvl_done && ((init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if ((stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd30) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; end else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (init_state_r1 != INIT_RDLVL_STG1_WRITE) ) // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; else address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end end else if ((init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_READ)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (oclk_wr_cnt == NUM_STG1_WR_RD) address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((oclk_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end else if ((init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_READ)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (wrcal_wr_cnt == NUM_STG1_WR_RD) address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((wrcal_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end else if ((init_state_r == INIT_WRCAL_MULT_READS) || (init_state_r == INIT_RDLVL_STG2_READ)) begin // when writing or reading back training pattern for read leveling stage2 // need to support burst length of 4 or 8. This may mean issuing // multiple commands to cover the entire range of addresses accessed // during read leveling. // Hard coding A[12] to 1 so that it will always be burst length of 8 // for DDR3. Does not have any effect on DDR2. bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; address_w[COL_WIDTH-1:0] = {CALIB_COL_ADD[COL_WIDTH-1:3],burst_addr_r, 3'b000}; address_w[12] = 1'b1; end else if ((init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_OCLKDELAY_ACT)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; //if (stg1_wr_rd_cnt == 'd22) // address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0] + 1; //else address_w = prbs_rdlvl_done ? CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt_ocal : CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt; end else begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end end // verilint STARC-2.7.3.3b on // registring before sending out generate genvar r,s; if ((DRAM_TYPE != "DDR3") || (CA_MIRROR != "ON")) begin: gen_no_mirror for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: div_clk_loop always @(posedge clk) begin phy_address[(r*ROW_WIDTH) +: ROW_WIDTH] <= #TCQ address_w; phy_bank[(r*BANK_WIDTH) +: BANK_WIDTH] <= #TCQ bank_w; end end end else begin: gen_mirror // Control/addressing mirroring (optional for DDR3 dual rank DIMMs) // Mirror for the 2nd rank only. Logic needs to be enhanced to account // for multiple slots, currently only supports one slot, 2-rank config for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_ba_div_clk_loop for (s = 0; s < BANK_WIDTH; s = s + 1) begin: gen_ba always @(posedge clk) if (chip_cnt_r == 2'b00) begin phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[s]; end else begin phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[(s == 0) ? 1 : ((s == 1) ? 0 : s)]; end end end for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_addr_div_clk_loop for (s = 0; s < ROW_WIDTH; s = s + 1) begin: gen_addr always @(posedge clk) if (chip_cnt_r == 2'b00) begin phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[s]; end else begin phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[ (s == 3) ? 4 : ((s == 4) ? 3 : ((s == 5) ? 6 : ((s == 6) ? 5 : ((s == 7) ? 8 : ((s == 8) ? 7 : s)))))]; end end end end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_phy_init.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $ // \ \ / \ Date Created: // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // Memory initialization and overall master state control during // initialization and calibration. Specifically, the following functions // are performed: // 1. Memory initialization (initial AR, mode register programming, etc.) // 2. Initiating write leveling // 3. Generate training pattern writes for read leveling. Generate // memory readback for read leveling. // This module has an interface for providing control/address and write // data to the PHY Control Block during initialization/calibration. // Once initialization and calibration are complete, control is passed to the MC. // //Reference: //Revision History: // //***************************************************************************** /****************************************************************************** **$Id: ddr_phy_init.v,v 1.1 2011/06/02 08:35:09 mishra Exp $ **$Date: 2011/06/02 08:35:09 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_init.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_phy_init # ( parameter tCK = 1500, // DDRx SDRAM clock period parameter TCQ = 100, parameter nCK_PER_CLK = 4, // # of memory clocks per CLK parameter CLK_PERIOD = 3000, // Logic (internal) clk period (in ps) parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA // 1 - ODT output from FPGA parameter DDR3_VDD_OP_VOLT = "150", // Voltage mode used for DDR3 // 150 - 1.50 V // 135 - 1.35 V // 125 - 1.25 V parameter VREF = "EXTERNAL", // Internal or external Vref parameter PRBS_WIDTH = 8, // PRBS sequence = 2^PRBS_WIDTH parameter BANK_WIDTH = 2, parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank parameter COL_WIDTH = 10, parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for // component I/F with CS_WIDTH=1, // nCS_PER_RANK=# of components parameter DQ_WIDTH = 64, parameter DQS_WIDTH = 8, parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter ROW_WIDTH = 14, parameter CS_WIDTH = 1, parameter RANKS = 1, // # of memory ranks in the interface parameter CKE_WIDTH = 1, // # of cke outputs parameter DRAM_TYPE = "DDR3", parameter REG_CTRL = "ON", parameter ADDR_CMD_MODE= "1T", // calibration Address parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address parameter CALIB_COL_ADD = 12'h000, // Calibration column address parameter CALIB_BA_ADD = 3'h0, // Calibration bank address // DRAM mode settings parameter AL = "0", // Additive Latency option parameter BURST_MODE = "8", // Burst length parameter BURST_TYPE = "SEQ", // Burst type // parameter nAL = 0, // Additive latency (in clk cyc) parameter nCL = 5, // Read CAS latency (in clk cyc) parameter nCWL = 5, // Write CAS latency (in clk cyc) parameter tRFC = 110000, // Refresh-to-command delay (in ps) parameter REFRESH_TIMER = 1553, // Refresh interval in fabrci cycles between 8 posted refreshes parameter REFRESH_TIMER_WIDTH = 8, parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option parameter RTT_NOM = "60", // Nominal ODT termination value parameter RTT_WR = "60", // Write ODT termination value parameter WRLVL = "ON", // Enable write leveling // parameter PHASE_DETECT = "ON", // Enable read phase detector parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter nSLOTS = 1, // Number of DIMM SLOTs in the system parameter SIM_INIT_OPTION = "NONE", // "NONE", "SKIP_PU_DLY", "SKIP_INIT" parameter SIM_CAL_OPTION = "NONE", // "NONE", "FAST_CAL", "SKIP_CAL" parameter CKE_ODT_AUX = "FALSE", parameter PRE_REV3ES = "OFF", // Enable TG error detection during calibration parameter TEST_AL = "0", // Internal use for ICM verification parameter FIXED_VICTIM = "TRUE", parameter BYPASS_COMPLEX_OCAL = "FALSE" ) ( input clk, input rst, input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o, input delay_incdec_done, input ck_addr_cmd_delay_done, input pi_phase_locked_all, input pi_dqs_found_done, input dqsfound_retry, input dqs_found_prech_req, output reg pi_phaselock_start, output pi_phase_locked_err, output pi_calib_done, input phy_if_empty, // Read/write calibration interface input wrlvl_done, input wrlvl_rank_done, input wrlvl_byte_done, input wrlvl_byte_redo, input wrlvl_final, output reg wrlvl_final_if_rst, input oclkdelay_calib_done, input oclk_prech_req, input oclk_calib_resume, input lim_done, input lim_wr_req, output reg oclkdelay_calib_start, //complex oclkdelay calibration input complex_oclkdelay_calib_done, input complex_oclk_prech_req, input complex_oclk_calib_resume, output reg complex_oclkdelay_calib_start, input [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt, // same as oclkdelay_calib_cnt output reg complex_ocal_num_samples_inc, input complex_ocal_num_samples_done_r, input [2:0] complex_ocal_rd_victim_sel, output reg complex_ocal_reset_rd_addr, input complex_ocal_ref_req, output reg complex_ocal_ref_done, input done_dqs_tap_inc, input [5:0] rd_data_offset_0, input [5:0] rd_data_offset_1, input [5:0] rd_data_offset_2, input [6*RANKS-1:0] rd_data_offset_ranks_0, input [6*RANKS-1:0] rd_data_offset_ranks_1, input [6*RANKS-1:0] rd_data_offset_ranks_2, input pi_dqs_found_rank_done, input wrcal_done, input wrcal_prech_req, input wrcal_read_req, input wrcal_act_req, input temp_wrcal_done, input [7:0] slot_0_present, input [7:0] slot_1_present, output reg wl_sm_start, output reg wr_lvl_start, output reg wrcal_start, output reg wrcal_rd_wait, output reg wrcal_sanity_chk, output reg tg_timer_done, output reg no_rst_tg_mc, input rdlvl_stg1_done, input rdlvl_stg1_rank_done, output reg rdlvl_stg1_start, output reg pi_dqs_found_start, output reg detect_pi_found_dqs, // rdlvl stage 1 precharge requested after each DQS input rdlvl_prech_req, input rdlvl_last_byte_done, input wrcal_resume, input wrcal_sanity_chk_done, // MPR read leveling input mpr_rdlvl_done, input mpr_rnk_done, input mpr_last_byte_done, output reg mpr_rdlvl_start, output reg mpr_end_if_reset, // PRBS Read Leveling input prbs_rdlvl_done, input prbs_last_byte_done, input prbs_rdlvl_prech_req, input complex_victim_inc, input [2:0] rd_victim_sel, input [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt, output reg [2:0] victim_sel, output reg [DQS_CNT_WIDTH:0]victim_byte_cnt, output reg prbs_rdlvl_start, output reg prbs_gen_clk_en, output reg prbs_gen_oclk_clk_en, output reg complex_sample_cnt_inc, output reg complex_sample_cnt_inc_ocal, output reg complex_wr_done, // Signals shared btw multiple calibration stages output reg prech_done, // Data select / status output reg init_calib_complete, // Signal to mask memory model error for Invalid latching edge output reg calib_writes, // PHY address/control // 2 commands to PHY Control Block per div 2 clock in 2:1 mode // 4 commands to PHY Control Block per div 4 clock in 4:1 mode output reg [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address, output reg [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank, output reg [nCK_PER_CLK-1:0] phy_ras_n, output reg [nCK_PER_CLK-1:0] phy_cas_n, output reg [nCK_PER_CLK-1:0] phy_we_n, output reg phy_reset_n, output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n, // Hard PHY Interface signals input phy_ctl_ready, input phy_ctl_full, input phy_cmd_full, input phy_data_full, output reg calib_ctl_wren, output reg calib_cmd_wren, output reg [1:0] calib_seq, output reg write_calib, output reg read_calib, // PHY_Ctl_Wd output reg [2:0] calib_cmd, // calib_aux_out used for CKE and ODT output reg [3:0] calib_aux_out, output reg [1:0] calib_odt , output reg [nCK_PER_CLK-1:0] calib_cke , output [1:0] calib_rank_cnt, output reg [1:0] calib_cas_slot, output reg [5:0] calib_data_offset_0, output reg [5:0] calib_data_offset_1, output reg [5:0] calib_data_offset_2, // PHY OUT_FIFO output reg calib_wrdata_en, output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata, // PHY Read output phy_rddata_en, output phy_rddata_valid, output [255:0] dbg_phy_init, input read_pause, input reset_rd_addr, //OCAL centering calibration input oclkdelay_center_calib_start, input oclk_center_write_resume, input oclkdelay_center_calib_done ); //***************************************************************************** // Assertions to be added //***************************************************************************** // The phy_ctl_full signal must never be asserted in synchronous mode of // operation either 4:1 or 2:1 // // The RANKS parameter must never be set to '0' by the user // valid values: 1 to 4 // //***************************************************************************** //*************************************************************************** // Number of Read level stage 1 writes limited to a SDRAM row // The address of Read Level stage 1 reads must also be limited // to a single SDRAM row // (2^COL_WIDTH)/BURST_MODE = (2^10)/8 = 128 localparam NUM_STG1_WR_RD = (BURST_MODE == "8") ? 4 : (BURST_MODE == "4") ? 8 : 4; localparam ADDR_INC = (BURST_MODE == "8") ? 8 : (BURST_MODE == "4") ? 4 : 8; // In a 2 slot dual rank per system RTT_NOM values // for Rank2 and Rank3 default to 40 ohms localparam RTT_NOM2 = "40"; localparam RTT_NOM3 = "40"; localparam RTT_NOM_int = (USE_ODT_PORT == 1) ? RTT_NOM : RTT_WR; // Specifically for use with half-frequency controller (nCK_PER_CLK=2) // = 1 if burst length = 4, = 0 if burst length = 8. Determines how // often row command needs to be issued during read-leveling // For DDR3 the burst length is fixed during calibration localparam BURST4_FLAG = (DRAM_TYPE == "DDR3")? 1'b0 : (BURST_MODE == "8") ? 1'b0 : ((BURST_MODE == "4") ? 1'b1 : 1'b0); //*************************************************************************** // Counter values used to determine bus timing // NOTE on all counter terminal counts - these can/should be one less than // the actual delay to take into account extra clock cycle delay in // generating the corresponding "done" signal //*************************************************************************** localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK; // Calculate initial delay required in number of CLK clock cycles // to delay initially. The counter is clocked by [CLK/1024] - which // is approximately division by 1000 - note that the formulas below will // result in more than the minimum wait time because of this approximation. // NOTE: For DDR3 JEDEC specifies to delay reset // by 200us, and CKE by an additional 500us after power-up // For DDR2 CKE is delayed by 200us after power up. localparam DDR3_RESET_DELAY_NS = 200000; localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS; localparam DDR2_CKE_DELAY_NS = 200000; localparam PWRON_RESET_DELAY_CNT = ((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD); localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == "DDR3") ? (((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) : (((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)); // FOR DDR2 -1 taken out. With -1 not getting 200us. The equation // needs to be reworked. localparam DDR2_INIT_PRE_DELAY_PS = 400000; localparam DDR2_INIT_PRE_CNT = ((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1; // Calculate tXPR time: reset from CKE HIGH to valid command after power-up // tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock // cycles because this counter actually starts up before CKE is asserted // to memory. localparam TXPR_DELAY_CNT = (5*CLK_MEM_PERIOD > tRFC+10000) ? (((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+11 : (((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+11; // tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV localparam TDLLK_TZQINIT_DELAY_CNT = 255; // TWR values in ns. Both DDR2 and DDR3 have the same value. // 15000ns/tCK localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ? (15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD; // time to wait between consecutive commands in PHY_INIT - this is a // generic number, and must be large enough to account for worst case // timing parameter (tRFC - refresh-to-active) across all memory speed // grades and operating frequencies. Expressed in clk // (Divided by 4 or Divided by 2) clock cycles. localparam CNTNEXT_CMD = 7'b1111111; // Counter values to keep track of which MR register to load during init // Set value of INIT_CNT_MR_DONE to equal value of counter for last mode // register configured during initialization. // NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init localparam INIT_CNT_MR2 = 2'b00; localparam INIT_CNT_MR3 = 2'b01; localparam INIT_CNT_MR1 = 2'b10; localparam INIT_CNT_MR0 = 2'b11; localparam INIT_CNT_MR_DONE = 2'b11; // Register chip programmable values for DDR3 // The register chip for the registered DIMM needs to be programmed // before the initialization of the registered DIMM. // Address for the control word is in : DBA2, DA2, DA1, DA0 // Data for the control word is in: DBA1 DBA0, DA4, DA3 // The values will be stored in the local param in the following format // {DBA[2:0], DA[4:0]} // RC0 is global features control word. Address == 000 localparam REG_RC0 = 8'b00000000; // RC1 Clock driver enable control word. Enables or disables the four // output clocks in the register chip. For single rank and dual rank // two clocks will be enabled and for quad rank all the four clocks // will be enabled. Address == 000. Data = 0110 for single and dual rank. // = 0000 for quad rank localparam REG_RC1 = 8'b00000001; // RC2 timing control word. Set in 1T timing mode // Address = 010. Data = 0000 localparam REG_RC2 = 8'b00000010; // RC3 timing control word. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC3 = (RANKS >= 2) ? 8'b00101011 : 8'b00000011; // RC4 timing control work. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC4 = (RANKS >= 2) ? 8'b00101100 : 8'b00000100; // RC5 timing control work. Setting the data based on number of RANKS (inturn the number of loads) // This setting is specific to RDIMMs from Micron Technology localparam REG_RC5 = (RANKS >= 2) ? 8'b00101101 : 8'b00000101; // RC10 timing control work. Setting the data to 0000 localparam [3:0] FREQUENCY_ENCODING = (tCK >= 1072 && tCK < 1250) ? 4'b0100 : (tCK >= 1250 && tCK < 1500) ? 4'b0011 : (tCK >= 1500 && tCK < 1875) ? 4'b0010 : (tCK >= 1875 && tCK < 2500) ? 4'b0001 : 4'b0000; localparam REG_RC10 = {1'b1,FREQUENCY_ENCODING,3'b010}; localparam VREF_ENCODING = (VREF == "INTERNAL") ? 1'b1 : 1'b0; localparam [3:0] DDR3_VOLTAGE_ENCODING = (DDR3_VDD_OP_VOLT == "125") ? {1'b0,VREF_ENCODING,2'b10} : (DDR3_VDD_OP_VOLT == "135") ? {1'b0,VREF_ENCODING,2'b01} : {1'b0,VREF_ENCODING,2'b00} ; localparam REG_RC11 = {1'b1,DDR3_VOLTAGE_ENCODING,3'b011}; // For non-zero AL values localparam nAL = (AL == "CL-1") ? nCL - 1 : 0; // Adding the register dimm latency to write latency localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL; // Count value to generate pi_phase_locked_err signal localparam PHASELOCKED_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 16383 : 1000; // Timeout interval for detecting error with Traffic Generator localparam [13:0] TG_TIMER_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 14'h3FFF : 14'h0001; //bit num per DQS localparam DQ_PER_DQS = DQ_WIDTH/DQS_WIDTH; //COMPLEX_ROW_CNT_BYTE localparam COMPLEX_ROW_CNT_BYTE = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS*2: 2; localparam COMPLEX_RD = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS : 1; // Master state machine encoding localparam INIT_IDLE = 7'b0000000; //0 localparam INIT_WAIT_CKE_EXIT = 7'b0000001; //1 localparam INIT_LOAD_MR = 7'b0000010; //2 localparam INIT_LOAD_MR_WAIT = 7'b0000011; //3 localparam INIT_ZQCL = 7'b0000100; //4 localparam INIT_WAIT_DLLK_ZQINIT = 7'b0000101; //5 localparam INIT_WRLVL_START = 7'b0000110; //6 localparam INIT_WRLVL_WAIT = 7'b0000111; //7 localparam INIT_WRLVL_LOAD_MR = 7'b0001000; //8 localparam INIT_WRLVL_LOAD_MR_WAIT = 7'b0001001; //9 localparam INIT_WRLVL_LOAD_MR2 = 7'b0001010; //A localparam INIT_WRLVL_LOAD_MR2_WAIT = 7'b0001011; //B localparam INIT_RDLVL_ACT = 7'b0001100; //C localparam INIT_RDLVL_ACT_WAIT = 7'b0001101; //D localparam INIT_RDLVL_STG1_WRITE = 7'b0001110; //E localparam INIT_RDLVL_STG1_WRITE_READ = 7'b0001111; //F localparam INIT_RDLVL_STG1_READ = 7'b0010000; //10 localparam INIT_RDLVL_STG2_READ = 7'b0010001; //11 localparam INIT_RDLVL_STG2_READ_WAIT = 7'b0010010; //12 localparam INIT_PRECHARGE_PREWAIT = 7'b0010011; //13 localparam INIT_PRECHARGE = 7'b0010100; //14 localparam INIT_PRECHARGE_WAIT = 7'b0010101; //15 localparam INIT_DONE = 7'b0010110; //16 localparam INIT_DDR2_PRECHARGE = 7'b0010111; //17 localparam INIT_DDR2_PRECHARGE_WAIT = 7'b0011000; //18 localparam INIT_REFRESH = 7'b0011001; //19 localparam INIT_REFRESH_WAIT = 7'b0011010; //1A localparam INIT_REG_WRITE = 7'b0011011; //1B localparam INIT_REG_WRITE_WAIT = 7'b0011100; //1C localparam INIT_DDR2_MULTI_RANK = 7'b0011101; //1D localparam INIT_DDR2_MULTI_RANK_WAIT = 7'b0011110; //1E localparam INIT_WRCAL_ACT = 7'b0011111; //1F localparam INIT_WRCAL_ACT_WAIT = 7'b0100000; //20 localparam INIT_WRCAL_WRITE = 7'b0100001; //21 localparam INIT_WRCAL_WRITE_READ = 7'b0100010; //22 localparam INIT_WRCAL_READ = 7'b0100011; //23 localparam INIT_WRCAL_READ_WAIT = 7'b0100100; //24 localparam INIT_WRCAL_MULT_READS = 7'b0100101; //25 localparam INIT_PI_PHASELOCK_READS = 7'b0100110; //26 localparam INIT_MPR_RDEN = 7'b0100111; //27 localparam INIT_MPR_WAIT = 7'b0101000; //28 localparam INIT_MPR_READ = 7'b0101001; //29 localparam INIT_MPR_DISABLE_PREWAIT = 7'b0101010; //2A localparam INIT_MPR_DISABLE = 7'b0101011; //2B localparam INIT_MPR_DISABLE_WAIT = 7'b0101100; //2C localparam INIT_OCLKDELAY_ACT = 7'b0101101; //2D localparam INIT_OCLKDELAY_ACT_WAIT = 7'b0101110; //2E localparam INIT_OCLKDELAY_WRITE = 7'b0101111; //2F localparam INIT_OCLKDELAY_WRITE_WAIT = 7'b0110000; //30 localparam INIT_OCLKDELAY_READ = 7'b0110001; //31 localparam INIT_OCLKDELAY_READ_WAIT = 7'b0110010; //32 localparam INIT_REFRESH_RNK2_WAIT = 7'b0110011; //33 localparam INIT_RDLVL_COMPLEX_PRECHARGE = 7'b0110100; //34 localparam INIT_RDLVL_COMPLEX_PRECHARGE_WAIT = 7'b0110101; //35 localparam INIT_RDLVL_COMPLEX_ACT = 7'b0110110; //36 localparam INIT_RDLVL_COMPLEX_ACT_WAIT = 7'b0110111; //37 localparam INIT_RDLVL_COMPLEX_READ = 7'b0111000; //38 localparam INIT_RDLVL_COMPLEX_READ_WAIT = 7'b0111001; //39 localparam INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT = 7'b0111010; //3A localparam INIT_OCAL_COMPLEX_ACT = 7'b0111011; //3B localparam INIT_OCAL_COMPLEX_ACT_WAIT = 7'b0111100; //3C localparam INIT_OCAL_COMPLEX_WRITE_WAIT = 7'b0111101; //3D localparam INIT_OCAL_COMPLEX_RESUME_WAIT = 7'b0111110; //3E localparam INIT_OCAL_CENTER_ACT = 7'b0111111; //3F localparam INIT_OCAL_CENTER_WRITE = 7'b1000000; //40 localparam INIT_OCAL_CENTER_WRITE_WAIT = 7'b1000001; //41 localparam INIT_OCAL_CENTER_ACT_WAIT = 7'b1000010; //42 integer i, j, k, l, m, n, p, q; reg pi_dqs_found_all_r; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r1; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r2; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r3; (* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r4; reg pi_calib_rank_done_r; reg [13:0] pi_phaselock_timer; reg stg1_wr_done; reg rnk_ref_cnt; reg pi_dqs_found_done_r1; reg pi_dqs_found_rank_done_r; reg read_calib_int; reg read_calib_r; reg pi_calib_done_r; reg pi_calib_done_r1; reg burst_addr_r; reg [1:0] chip_cnt_r; reg [6:0] cnt_cmd_r; reg cnt_cmd_done_r; reg cnt_cmd_done_m7_r; reg [7:0] cnt_dllk_zqinit_r; reg cnt_dllk_zqinit_done_r; reg cnt_init_af_done_r; reg [1:0] cnt_init_af_r; reg [1:0] cnt_init_data_r; reg [1:0] cnt_init_mr_r; reg cnt_init_mr_done_r; reg cnt_init_pre_wait_done_r; reg [7:0] cnt_init_pre_wait_r; reg [9:0] cnt_pwron_ce_r; reg cnt_pwron_cke_done_r; reg cnt_pwron_cke_done_r1; reg [8:0] cnt_pwron_r; reg cnt_pwron_reset_done_r; reg cnt_txpr_done_r; reg [7:0] cnt_txpr_r; reg ddr2_pre_flag_r; reg ddr2_refresh_flag_r; reg ddr3_lm_done_r; reg [4:0] enable_wrlvl_cnt; reg init_complete_r; reg init_complete_r1; reg init_complete_r2; (* keep = "true" *) reg init_complete_r_timing; (* keep = "true" *) reg init_complete_r1_timing; reg [6:0] init_next_state; reg [6:0] init_state_r; reg [6:0] init_state_r1; wire [15:0] load_mr0; wire [15:0] load_mr1; wire [15:0] load_mr2; wire [15:0] load_mr3; reg mem_init_done_r; reg [1:0] mr2_r [0:3]; reg [2:0] mr1_r [0:3]; reg new_burst_r; reg [15:0] wrcal_start_dly_r; wire wrcal_start_pre; reg wrcal_resume_r; // Only one ODT signal per rank in PHY Control Block reg [nCK_PER_CLK-1:0] phy_tmp_odt_r; reg [nCK_PER_CLK-1:0] phy_tmp_odt_r1; reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r; reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_int_cs_n; wire prech_done_pre; reg [15:0] prech_done_dly_r; reg prech_pending_r; reg prech_req_posedge_r; reg prech_req_r; reg pwron_ce_r; reg first_rdlvl_pat_r; reg first_wrcal_pat_r; reg phy_wrdata_en; reg phy_wrdata_en_r1; reg [1:0] wrdata_pat_cnt; reg [1:0] wrcal_pat_cnt; reg [ROW_WIDTH-1:0] address_w; reg [BANK_WIDTH-1:0] bank_w; reg rdlvl_stg1_done_r1; reg rdlvl_stg1_start_int; reg [15:0] rdlvl_start_dly0_r; reg rdlvl_start_pre; reg rdlvl_last_byte_done_r; wire rdlvl_rd; wire rdlvl_wr; reg rdlvl_wr_r; wire rdlvl_wr_rd; reg [3:0] reg_ctrl_cnt_r; reg [1:0] tmp_mr2_r [0:3]; reg [2:0] tmp_mr1_r [0:3]; reg wrlvl_done_r; reg wrlvl_done_r1; reg wrlvl_rank_done_r1; reg wrlvl_rank_done_r2; reg wrlvl_rank_done_r3; reg wrlvl_rank_done_r4; reg wrlvl_rank_done_r5; reg wrlvl_rank_done_r6; reg wrlvl_rank_done_r7; reg [2:0] wrlvl_rank_cntr; reg wrlvl_odt_ctl; reg wrlvl_odt; reg wrlvl_active; reg wrlvl_active_r1; reg [2:0] num_reads; reg temp_wrcal_done_r; reg temp_lmr_done; reg extend_cal_pat; reg [13:0] tg_timer; reg tg_timer_go; reg cnt_wrcal_rd; reg [3:0] cnt_wait; reg [7:0] wrcal_reads; reg [8:0] stg1_wr_rd_cnt; reg phy_data_full_r; reg wr_level_dqs_asrt; reg wr_level_dqs_asrt_r1; reg [1:0] dqs_asrt_cnt; reg [3:0] num_refresh; wire oclkdelay_calib_start_pre; reg [15:0] oclkdelay_start_dly_r; reg [3:0] oclk_wr_cnt; reg [3:0] wrcal_wr_cnt; reg wrlvl_final_r; reg prbs_rdlvl_done_r1; reg prbs_rdlvl_done_r2; reg prbs_rdlvl_done_r3; reg prbs_last_byte_done_r; reg phy_if_empty_r; reg prbs_pat_resume_int; reg complex_row0_wr_done; reg complex_row1_wr_done; reg complex_row0_rd_done; reg complex_row1_rd_done; reg complex_row0_rd_done_r1; reg [3:0] complex_wait_cnt; reg [3:0] complex_num_reads; reg [3:0] complex_num_reads_dec; reg [ROW_WIDTH-1:0] complex_address; reg wr_victim_inc; reg [2:0] wr_victim_sel; reg [DQS_CNT_WIDTH:0] wr_byte_cnt; reg [7:0] complex_row_cnt; reg complex_sample_cnt_inc_r1; reg complex_sample_cnt_inc_r2; reg complex_odt_ext; reg complex_ocal_odt_ext; reg wrcal_final_chk; wire prech_req; reg read_pause_r1; reg read_pause_r2; wire read_pause_ext; reg reset_rd_addr_r1; reg complex_rdlvl_int_ref_req; reg ext_int_ref_req; //complex OCLK delay calibration reg [7:0] complex_row_cnt_ocal; reg [4:0] complex_num_writes; reg [4:0] complex_num_writes_dec; reg complex_oclkdelay_calib_start_int; reg complex_oclkdelay_calib_start_r1; reg complex_oclkdelay_calib_start_r2; reg complex_oclkdelay_calib_done_r1; // reg [DQS_CNT_WIDTH:0] wr_byte_cnt_ocal; reg [2:0] wr_victim_sel_ocal; reg complex_row1_rd_done_r1; //time for switch to write reg [2:0] complex_row1_rd_cnt; //row1 read number for the byte (8 (16 rows) row1) reg complex_byte_rd_done; //read for the byte is done reg complex_byte_rd_done_r1; // reg complex_row_change; //every 16 rows of read, it is set to "0" for write reg ocal_num_samples_inc; //1 read/write is done reg complex_ocal_wr_start; //indicate complex ocal write is started. used for prbs rd addr gen reg prbs_rdlvl_done_pulse; //rising edge for prbs_rdlvl_done. used for pipelining reg prech_done_r1, prech_done_r2, prech_done_r3; reg mask_lim_done; reg complex_mask_lim_done; reg oclkdelay_calib_start_int; reg [REFRESH_TIMER_WIDTH-1:0] oclkdelay_ref_cnt; reg oclkdelay_int_ref_req; reg [3:0] ocal_act_wait_cnt; reg oclk_calib_resume_level; reg ocal_last_byte_done; wire mmcm_wr; //MMCM centering write. no CS will be set wire exit_ocal_complex_resume_wait = init_state_r == INIT_OCAL_COMPLEX_RESUME_WAIT && complex_oclk_calib_resume; //*************************************************************************** // Debug //*************************************************************************** //synthesis translate_off always @(posedge mem_init_done_r) begin if (!rst) $display ("PHY_INIT: Memory Initialization completed at %t", $time); end always @(posedge wrlvl_done) begin if (!rst && (WRLVL == "ON")) $display ("PHY_INIT: Write Leveling completed at %t", $time); end always @(posedge rdlvl_stg1_done) begin if (!rst) $display ("PHY_INIT: Read Leveling Stage 1 completed at %t", $time); end always @(posedge mpr_rdlvl_done) begin if (!rst) $display ("PHY_INIT: MPR Read Leveling completed at %t", $time); end always @(posedge oclkdelay_calib_done) begin if (!rst) $display ("PHY_INIT: OCLKDELAY calibration completed at %t", $time); end always @(posedge pi_calib_done_r1) begin if (!rst) $display ("PHY_INIT: Phaser_In Phase Locked at %t", $time); end always @(posedge pi_dqs_found_done) begin if (!rst) $display ("PHY_INIT: Phaser_In DQSFOUND completed at %t", $time); end always @(posedge wrcal_done) begin if (!rst && (WRLVL == "ON")) $display ("PHY_INIT: Write Calibration completed at %t", $time); end always@(posedge prbs_rdlvl_done)begin if(!rst) $display("PHY_INIT : PRBS/PER_BIT calibration completed at %t",$time); end always@(posedge complex_oclkdelay_calib_done)begin if(!rst) $display("PHY_INIT : COMPLEX OCLKDELAY calibration completed at %t",$time); end always@(posedge oclkdelay_center_calib_done)begin if(!rst) $display("PHY_INIT : OCLKDELAY CENTER CALIB calibration completed at %t",$time); end //synthesis translate_on assign dbg_phy_init[5:0] = init_state_r; assign dbg_phy_init[6+:8] = complex_row_cnt; assign dbg_phy_init[14+:3] = victim_sel; assign dbg_phy_init[17+:4] = victim_byte_cnt; assign dbg_phy_init[21+:9] = stg1_wr_rd_cnt[8:0]; assign dbg_phy_init[30+:15] = complex_address; assign dbg_phy_init[(30+15)+:15] = phy_address[14:0]; assign dbg_phy_init[60] =prbs_rdlvl_prech_req ; assign dbg_phy_init[61] =prech_req_posedge_r ; //*************************************************************************** // DQS count to be sent to hard PHY during Phaser_IN Phase Locking stage //*************************************************************************** // assign pi_phaselock_calib_cnt = dqs_cnt_r; assign pi_calib_done = pi_calib_done_r1; assign read_pause_ext = read_pause | read_pause_r2; //detect rising edge of prbs_rdlvl_done to reset all control sighals always @ (posedge clk) begin prbs_rdlvl_done_pulse <= #TCQ prbs_rdlvl_done & ~prbs_rdlvl_done_r1; end always @ (posedge clk) begin read_pause_r1 <= #TCQ read_pause; read_pause_r2 <= #TCQ read_pause_r1; end always @(posedge clk) begin if (rst) wrcal_final_chk <= #TCQ 1'b0; else if ((init_next_state == INIT_WRCAL_ACT) && wrcal_done && (DRAM_TYPE == "DDR3")) wrcal_final_chk <= #TCQ 1'b1; end always @(posedge clk) begin rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done; prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done; prbs_rdlvl_done_r2 <= #TCQ prbs_rdlvl_done_r1; prbs_rdlvl_done_r3 <= #TCQ prbs_rdlvl_done_r2; wrcal_resume_r <= #TCQ wrcal_resume; wrcal_sanity_chk <= #TCQ wrcal_final_chk; end always @(posedge clk) begin if (rst) mpr_end_if_reset <= #TCQ 1'b0; else if (mpr_last_byte_done && (num_refresh != 'd0)) mpr_end_if_reset <= #TCQ 1'b1; else mpr_end_if_reset <= #TCQ 1'b0; end // Siganl to mask memory model error for Invalid latching edge always @(posedge clk) if (rst) calib_writes <= #TCQ 1'b0; else if ((init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ)) calib_writes <= #TCQ 1'b1; else calib_writes <= #TCQ 1'b0; always @(posedge clk) if (rst) wrcal_rd_wait <= #TCQ 1'b0; else if (init_state_r == INIT_WRCAL_READ_WAIT) wrcal_rd_wait <= #TCQ 1'b1; else wrcal_rd_wait <= #TCQ 1'b0; //*************************************************************************** // Signal PHY completion when calibration is finished // Signal assertion is delayed by four clock cycles to account for the // multi cycle path constraint to (phy_init_data_sel) signal. //*************************************************************************** always @(posedge clk) if (rst) begin init_complete_r <= #TCQ 1'b0; init_complete_r_timing <= #TCQ 1'b0; init_complete_r1 <= #TCQ 1'b0; init_complete_r1_timing <= #TCQ 1'b0; init_complete_r2 <= #TCQ 1'b0; init_calib_complete <= #TCQ 1'b0; end else begin if (init_state_r == INIT_DONE) begin init_complete_r <= #TCQ 1'b1; init_complete_r_timing <= #TCQ 1'b1; end init_complete_r1 <= #TCQ init_complete_r; init_complete_r1_timing <= #TCQ init_complete_r_timing; init_complete_r2 <= #TCQ init_complete_r1; init_calib_complete <= #TCQ init_complete_r2; end always @ (posedge clk) if (rst) complex_oclkdelay_calib_done_r1 <= #TCQ 1'b0; else complex_oclkdelay_calib_done_r1 <= #TCQ complex_oclkdelay_calib_done; //reset read address for starting complex ocaldealy calib always @ (posedge clk) begin complex_ocal_reset_rd_addr <= #TCQ ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd9)) || (prbs_last_byte_done && ~prbs_last_byte_done_r); end //first write for complex oclkdealy calib always @ (posedge clk) begin if (rst) complex_ocal_wr_start <= #TCQ 'b0; else complex_ocal_wr_start <= #TCQ complex_ocal_reset_rd_addr? 1'b1 : complex_ocal_wr_start; end //ocal stg3 centering start // always @ (posedge clk) // if(rst) oclkdelay_center_calib_start <= #TCQ 1'b0; // else // oclkdelay_center_calib_start <= #TCQ ((init_state_r == INIT_OCAL_CENTER_ACT) && lim_done)? 1'b1: oclkdelay_center_calib_start; //*************************************************************************** // Instantiate FF for the phy_init_data_sel signal. A multi cycle path // constraint will be assigned to this signal. This signal will only be // used within the PHY //*************************************************************************** // FDRSE u_ff_phy_init_data_sel // ( // .Q (phy_init_data_sel), // .C (clk), // .CE (1'b1), // .D (init_complete_r), // .R (1'b0), // .S (1'b0) // ) /* synthesis syn_preserve=1 */ // /* synthesis syn_replicate = 0 */; //*************************************************************************** // Mode register programming //*************************************************************************** //***************************************************************** // DDR3 Load mode reg0 // Mode Register (MR0): // [15:13] - unused - 000 // [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit), // 1 (DLL maintained) // [11:9] - write recovery for Auto Precharge (tWR/tCK = 6) // [8] - DLL reset - 0 or 1 // [7] - Test Mode - 0 (normal) // [6:4],[2] - CAS latency - CAS_LAT // [3] - Burst Type - BURST_TYPE // [1:0] - Burst Length - BURST_LEN // DDR2 Load mode register // Mode Register (MR): // [15:14] - unused - 00 // [13] - reserved - 0 // [12] - Power-down mode - 0 (normal) // [11:9] - write recovery - write recovery for Auto Precharge // (tWR/tCK = 6) // [8] - DLL reset - 0 or 1 // [7] - Test Mode - 0 (normal) // [6:4] - CAS latency - CAS_LAT // [3] - Burst Type - BURST_TYPE // [2:0] - Burst Length - BURST_LEN //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr0_DDR3 assign load_mr0[1:0] = (BURST_MODE == "8") ? 2'b00 : (BURST_MODE == "OTF") ? 2'b01 : (BURST_MODE == "4") ? 2'b10 : 2'b11; assign load_mr0[2] = (nCL >= 12) ? 1'b1 : 1'b0; // LSb of CAS latency assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; assign load_mr0[6:4] = ((nCL == 5) || (nCL == 13)) ? 3'b001 : ((nCL == 6) || (nCL == 14)) ? 3'b010 : (nCL == 7) ? 3'b011 : (nCL == 8) ? 3'b100 : (nCL == 9) ? 3'b101 : (nCL == 10) ? 3'b110 : (nCL == 11) ? 3'b111 : (nCL == 12) ? 3'b000 : 3'b111; assign load_mr0[7] = 1'b0; assign load_mr0[8] = 1'b1; // Reset DLL (init only) assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 : (TWR_CYC == 6) ? 3'b010 : (TWR_CYC == 7) ? 3'b011 : (TWR_CYC == 8) ? 3'b100 : (TWR_CYC == 9) ? 3'b101 : (TWR_CYC == 10) ? 3'b101 : (TWR_CYC == 11) ? 3'b110 : (TWR_CYC == 12) ? 3'b110 : (TWR_CYC == 13) ? 3'b111 : (TWR_CYC == 14) ? 3'b111 : (TWR_CYC == 15) ? 3'b000 : (TWR_CYC == 16) ? 3'b000 : 3'b010; assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit' assign load_mr0[15:13] = 3'b000; end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr0_DDR2 // block: gen assign load_mr0[2:0] = (BURST_MODE == "8") ? 3'b011 : (BURST_MODE == "4") ? 3'b010 : 3'b111; assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1; assign load_mr0[6:4] = (nCL == 3) ? 3'b011 : (nCL == 4) ? 3'b100 : (nCL == 5) ? 3'b101 : (nCL == 6) ? 3'b110 : 3'b111; assign load_mr0[7] = 1'b0; assign load_mr0[8] = 1'b1; // Reset DLL (init only) assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 : (TWR_CYC == 3) ? 3'b010 : (TWR_CYC == 4) ? 3'b011 : (TWR_CYC == 5) ? 3'b100 : (TWR_CYC == 6) ? 3'b101 : 3'b010; assign load_mr0[15:12]= 4'b0000; // Reserved end endgenerate //***************************************************************** // DDR3 Load mode reg1 // Mode Register (MR1): // [15:13] - unused - 00 // [12] - output enable - 0 (enabled for DQ, DQS, DQS#) // [11] - TDQS enable - 0 (TDQS disabled and DM enabled) // [10] - reserved - 0 (must be '0') // [9] - RTT[2] - 0 // [8] - reserved - 0 (must be '0') // [7] - write leveling - 0 (disabled), 1 (enabled) // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) // [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7) // [4:3] - Additive CAS - ADDITIVE_CAS // [2] - RTT[0] // [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7) // [0] - DLL enable - 0 (normal) // DDR2 ext mode register // Extended Mode Register (MR): // [15:14] - unused - 00 // [13] - reserved - 0 // [12] - output enable - 0 (enabled) // [11] - RDQS enable - 0 (disabled) // [10] - DQS# enable - 0 (enabled) // [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init) // [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50) // [5:3] - Additive CAS - ADDITIVE_CAS // [2] - RTT[0] // [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced) // [0] - DLL enable - 0 (normal) //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr1_DDR3 assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b0 : 1'b1; assign load_mr1[2] = ((RTT_NOM_int == "30") || (RTT_NOM_int == "40") || (RTT_NOM_int == "60")) ? 1'b1 : 1'b0; assign load_mr1[4:3] = (AL == "0") ? 2'b00 : (AL == "CL-1") ? 2'b01 : (AL == "CL-2") ? 2'b10 : 2'b11; assign load_mr1[5] = 1'b0; assign load_mr1[6] = ((RTT_NOM_int == "40") || (RTT_NOM_int == "120")) ? 1'b1 : 1'b0; assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence assign load_mr1[8] = 1'b0; assign load_mr1[9] = ((RTT_NOM_int == "20") || (RTT_NOM_int == "30")) ? 1'b1 : 1'b0; assign load_mr1[10] = 1'b0; assign load_mr1[15:11] = 5'b00000; end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr1_DDR2 assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b1 : 1'b0; assign load_mr1[2] = ((RTT_NOM_int == "75") || (RTT_NOM_int == "50")) ? 1'b1 : 1'b0; assign load_mr1[5:3] = (AL == "0") ? 3'b000 : (AL == "1") ? 3'b001 : (AL == "2") ? 3'b010 : (AL == "3") ? 3'b011 : (AL == "4") ? 3'b100 : 3'b111; assign load_mr1[6] = ((RTT_NOM_int == "50") || (RTT_NOM_int == "150")) ? 1'b1 : 1'b0; assign load_mr1[9:7] = 3'b000; assign load_mr1[10] = (DDR2_DQSN_ENABLE == "YES") ? 1'b0 : 1'b1; assign load_mr1[15:11] = 5'b00000; end endgenerate //***************************************************************** // DDR3 Load mode reg2 // Mode Register (MR2): // [15:11] - unused - 00 // [10:9] - RTT_WR - 00 (Dynamic ODT off) // [8] - reserved - 0 (must be '0') // [7] - self-refresh temperature range - // 0 (normal), 1 (extended) // [6] - Auto Self-Refresh - 0 (manual), 1(auto) // [5:3] - CAS Write Latency (CWL) - // 000 (5 for 400 MHz device), // 001 (6 for 400 MHz to 533 MHz devices), // 010 (7 for 533 MHz to 667 MHz devices), // 011 (8 for 667 MHz to 800 MHz) // [2:0] - Partial Array Self-Refresh (Optional) - // 000 (full array) // Not used for DDR2 //***************************************************************** generate if(DRAM_TYPE == "DDR3") begin: gen_load_mr2_DDR3 assign load_mr2[2:0] = 3'b000; assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 : (nCWL == 6) ? 3'b001 : (nCWL == 7) ? 3'b010 : (nCWL == 8) ? 3'b011 : (nCWL == 9) ? 3'b100 : (nCWL == 10) ? 3'b101 : (nCWL == 11) ? 3'b110 : 3'b111; assign load_mr2[6] = 1'b0; assign load_mr2[7] = 1'b0; assign load_mr2[8] = 1'b0; // Dynamic ODT disabled assign load_mr2[10:9] = 2'b00; assign load_mr2[15:11] = 5'b00000; end else begin: gen_load_mr2_DDR2 assign load_mr2[15:0] = 16'd0; end endgenerate //***************************************************************** // DDR3 Load mode reg3 // Mode Register (MR3): // [15:3] - unused - All zeros // [2] - MPR Operation - 0(normal operation), 1(data flow from MPR) // [1:0] - MPR location - 00 (Predefined pattern) //***************************************************************** assign load_mr3[1:0] = 2'b00; assign load_mr3[2] = 1'b0; assign load_mr3[15:3] = 13'b0000000000000; // For multi-rank systems the rank being accessed during writes in // Read Leveling must be sent to phy_write for the bitslip logic assign calib_rank_cnt = chip_cnt_r; //*************************************************************************** // Logic to begin initial calibration, and to handle precharge requests // during read-leveling (to avoid tRAS violations if individual read // levelling calibration stages take more than max{tRAS) to complete). //*************************************************************************** // Assert when readback for each stage of read-leveling begins. However, // note this indicates only when the read command is issued and when // Phaser_IN has phase aligned FREQ_REF clock to read DQS. It does not // indicate when the read data is present on the bus (when this happens // after the read command is issued depends on CAS LATENCY) - there will // need to be some delay before valid data is present on the bus. // assign rdlvl_start_pre = (init_state_r == INIT_PI_PHASELOCK_READS); // Assert when read back for oclkdelay calibration begins assign oclkdelay_calib_start_pre = (init_state_r == INIT_OCAL_CENTER_ACT); //(init_state_r == INIT_OCLKDELAY_READ); // Assert when read back for write calibration begins assign wrcal_start_pre = (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS); // Common precharge signal done signal - pulses only when there has been // a precharge issued as a result of a PRECH_REQ pulse. Note also a common // PRECH_DONE signal is used for all blocks assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || ((rdlvl_last_byte_done_r || prbs_last_byte_done_r) && (init_state_r == INIT_RDLVL_ACT_WAIT) && cnt_cmd_done_r) || (dqs_found_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || (init_state_r == INIT_MPR_RDEN) || ((init_state_r == INIT_WRCAL_ACT_WAIT) && cnt_cmd_done_r) || (init_state_r == INIT_OCAL_CENTER_ACT) || ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && complex_oclkdelay_calib_start_r1) || ((init_state_r == INIT_OCLKDELAY_ACT_WAIT) && cnt_cmd_done_r) || ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) && prbs_last_byte_done_r) || //prbs_rdlvl_done (wrlvl_final && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r && ~oclkdelay_calib_done)) && prech_pending_r && !prech_req_posedge_r); always @(posedge clk) if (rst) pi_phaselock_start <= #TCQ 1'b0; else if (init_state_r == INIT_PI_PHASELOCK_READS) pi_phaselock_start <= #TCQ 1'b1; // Delay start of each calibration by 16 clock cycles to ensure that when // calibration logic begins, read data is already appearing on the bus. // Each circuit should synthesize using an SRL16. Assume that reset is // long enough to clear contents of SRL16. always @(posedge clk) begin rdlvl_last_byte_done_r <= #TCQ rdlvl_last_byte_done; prbs_last_byte_done_r <= #TCQ prbs_last_byte_done; rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0], rdlvl_start_pre}; wrcal_start_dly_r <= #TCQ {wrcal_start_dly_r[14:0], wrcal_start_pre}; oclkdelay_start_dly_r <= #TCQ {oclkdelay_start_dly_r[14:0], oclkdelay_calib_start_pre}; prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0], prech_done_pre}; end always @(posedge clk) if (rst) oclkdelay_calib_start_int <= #TCQ 1'b0; else if (oclkdelay_start_dly_r[5]) oclkdelay_calib_start_int <= #TCQ 1'b1; always @(posedge clk) begin if (rst) ocal_last_byte_done <= #TCQ 1'b0; else if ((complex_oclkdelay_calib_cnt == DQS_WIDTH-1) && oclkdelay_center_calib_done) ocal_last_byte_done <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || (init_state_r == INIT_REFRESH) || prbs_rdlvl_done || ocal_last_byte_done || oclkdelay_center_calib_done) oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; else if (oclkdelay_calib_start_int) begin if (oclkdelay_ref_cnt > 'd0) oclkdelay_ref_cnt <= #TCQ oclkdelay_ref_cnt - 1; else oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER; end end always @(posedge clk) begin if (rst || (init_state_r == INIT_OCAL_CENTER_ACT) || oclkdelay_calib_done || ocal_last_byte_done || oclkdelay_center_calib_done) oclkdelay_int_ref_req <= #TCQ 1'b0; else if (oclkdelay_ref_cnt == 'd1) oclkdelay_int_ref_req <= #TCQ 1'b1; end always @(posedge clk) begin if (rst) ocal_act_wait_cnt <= #TCQ 'd0; else if ((init_state_r == INIT_OCAL_CENTER_ACT_WAIT) && ocal_act_wait_cnt < 'd15) ocal_act_wait_cnt <= #TCQ ocal_act_wait_cnt + 1; else ocal_act_wait_cnt <= #TCQ 'd0; end always @(posedge clk) begin if (rst || (init_state_r == INIT_OCLKDELAY_READ)) oclk_calib_resume_level <= #TCQ 1'b0; else if (oclk_calib_resume) oclk_calib_resume_level <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_ACT_WAIT) || prbs_rdlvl_done) complex_rdlvl_int_ref_req <= #TCQ 1'b0; else if (oclkdelay_ref_cnt == 'd1) // complex_rdlvl_int_ref_req <= #TCQ 1'b1; complex_rdlvl_int_ref_req <= #TCQ 1'b0; //temporary fix for read issue end always @(posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_COMPLEX_READ)) ext_int_ref_req <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_ACT_WAIT) && complex_rdlvl_int_ref_req) ext_int_ref_req <= #TCQ 1'b1; end always @(posedge clk) begin prech_done <= #TCQ prech_done_dly_r[15]; prech_done_r1 <= #TCQ prech_done_dly_r[15]; prech_done_r2 <= #TCQ prech_done_r1; prech_done_r3 <= #TCQ prech_done_r2; end always @(posedge clk) if (rst) mpr_rdlvl_start <= #TCQ 1'b0; else if (pi_dqs_found_done && (init_state_r == INIT_MPR_READ)) mpr_rdlvl_start <= #TCQ 1'b1; always @(posedge clk) phy_if_empty_r <= #TCQ phy_if_empty; always @(posedge clk) if (rst || ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || prbs_rdlvl_done) prbs_gen_clk_en <= #TCQ 1'b0; else if ((~phy_if_empty_r && rdlvl_stg1_done_r1 && ~prbs_rdlvl_done) || ((init_state_r == INIT_RDLVL_ACT_WAIT) && rdlvl_stg1_done_r1 && (cnt_cmd_r == 'd127)) || ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && rdlvl_stg1_done_r1 && (complex_wait_cnt == 'd14)) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || ((init_state_r == INIT_PRECHARGE_PREWAIT) && prbs_rdlvl_start)) prbs_gen_clk_en <= #TCQ 1'b1; //Enable for complex oclkdelay - used in prbs gen always @(posedge clk) if (rst || ((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || complex_oclkdelay_calib_done || (complex_wait_cnt == 'd15 && complex_num_writes == 1 && complex_ocal_wr_start) || ( init_state_r == INIT_RDLVL_STG1_WRITE && complex_num_writes_dec == 'd2) || ~complex_ocal_wr_start || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT ) || (init_state_r != INIT_OCAL_COMPLEX_RESUME_WAIT && init_state_r1 == INIT_OCAL_COMPLEX_RESUME_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_ACT)) prbs_gen_oclk_clk_en <= #TCQ 1'b0; else if ((~phy_if_empty_r && ~complex_oclkdelay_calib_done && prbs_rdlvl_done_r1) || // changed for new algo 3/26 ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd14)) || ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14)) || exit_ocal_complex_resume_wait || ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && ~stg1_wr_done && ~complex_row1_wr_done && ~complex_ocal_num_samples_done_r && (complex_wait_cnt == 'd14)) || (init_state_r == INIT_RDLVL_COMPLEX_READ) ) prbs_gen_oclk_clk_en <= #TCQ 1'b1; generate if (RANKS < 2) begin always @(posedge clk) if (rst) begin rdlvl_stg1_start <= #TCQ 1'b0; rdlvl_stg1_start_int <= #TCQ 1'b0; rdlvl_start_pre <= #TCQ 1'b0; prbs_rdlvl_start <= #TCQ 1'b0; end else begin if (pi_dqs_found_done && cnt_cmd_done_r && (init_state_r == INIT_RDLVL_ACT_WAIT)) rdlvl_stg1_start_int <= #TCQ 1'b1; if (pi_dqs_found_done && (init_state_r == INIT_RDLVL_STG1_READ))begin rdlvl_start_pre <= #TCQ 1'b1; rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; end if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_READ) && (WRLVL == "ON")) begin prbs_rdlvl_start <= #TCQ 1'b1; end end end else begin always @(posedge clk) if (rst || rdlvl_stg1_rank_done) begin rdlvl_stg1_start <= #TCQ 1'b0; rdlvl_stg1_start_int <= #TCQ 1'b0; rdlvl_start_pre <= #TCQ 1'b0; prbs_rdlvl_start <= #TCQ 1'b0; end else begin if (pi_dqs_found_done && cnt_cmd_done_r && (init_state_r == INIT_RDLVL_ACT_WAIT)) rdlvl_stg1_start_int <= #TCQ 1'b1; if (pi_dqs_found_done && (init_state_r == INIT_RDLVL_STG1_READ))begin rdlvl_start_pre <= #TCQ 1'b1; rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14]; end if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_READ) && (WRLVL == "ON")) begin prbs_rdlvl_start <= #TCQ 1'b1; end end end endgenerate always @(posedge clk) begin if (rst || dqsfound_retry || wrlvl_byte_redo) begin pi_dqs_found_start <= #TCQ 1'b0; wrcal_start <= #TCQ 1'b0; end else begin if (!pi_dqs_found_done && init_state_r == INIT_RDLVL_STG2_READ) pi_dqs_found_start <= #TCQ 1'b1; if (wrcal_start_dly_r[5]) wrcal_start <= #TCQ 1'b1; end end // else: !if(rst) always @(posedge clk) if (rst) oclkdelay_calib_start <= #TCQ 1'b0; else if (oclkdelay_start_dly_r[5]) oclkdelay_calib_start <= #TCQ 1'b1; always @(posedge clk) if (rst) pi_dqs_found_done_r1 <= #TCQ 1'b0; else pi_dqs_found_done_r1 <= #TCQ pi_dqs_found_done; always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final; // Reset IN_FIFO after final write leveling to make sure the FIFO // pointers are initialized always @(posedge clk) if (rst || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_REFRESH)) wrlvl_final_if_rst <= #TCQ 1'b0; else if (wrlvl_done_r && //(wrlvl_final_r && wrlvl_done_r && (init_state_r == INIT_WRLVL_LOAD_MR2)) wrlvl_final_if_rst <= #TCQ 1'b1; // Constantly enable DQS while write leveling is enabled in the memory // This is more to get rid of warnings in simulation, can later change // this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted always @(posedge clk) if (rst || ((init_state_r1 != INIT_WRLVL_START) && (init_state_r == INIT_WRLVL_START))) wrlvl_odt_ctl <= #TCQ 1'b0; else if (wrlvl_rank_done && ~wrlvl_rank_done_r1) wrlvl_odt_ctl <= #TCQ 1'b1; generate if (nCK_PER_CLK == 4) begin: en_cnt_div4 always @ (posedge clk) if (rst) enable_wrlvl_cnt <= #TCQ 5'd0; else if ((init_state_r == INIT_WRLVL_START) || (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) enable_wrlvl_cnt <= #TCQ 5'd12; else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; // ODT stays asserted as long as write_calib // signal is asserted always @(posedge clk) if (rst || wrlvl_odt_ctl) wrlvl_odt <= #TCQ 1'b0; else if (enable_wrlvl_cnt == 5'd1) wrlvl_odt <= #TCQ 1'b1; end else begin: en_cnt_div2 always @ (posedge clk) if (rst) enable_wrlvl_cnt <= #TCQ 5'd0; else if ((init_state_r == INIT_WRLVL_START) || (wrlvl_odt && (enable_wrlvl_cnt == 5'd0))) enable_wrlvl_cnt <= #TCQ 5'd21; else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full)) enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1; // ODT stays asserted as long as write_calib // signal is asserted always @(posedge clk) if (rst || wrlvl_odt_ctl) wrlvl_odt <= #TCQ 1'b0; else if (enable_wrlvl_cnt == 5'd1) wrlvl_odt <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst || wrlvl_rank_done || done_dqs_tap_inc) wrlvl_active <= #TCQ 1'b0; else if ((enable_wrlvl_cnt == 5'd1) && wrlvl_odt && !wrlvl_active) wrlvl_active <= #TCQ 1'b1; // signal used to assert DQS for write leveling. // the DQS will be asserted once every 16 clock cycles. always @(posedge clk)begin if(rst || (enable_wrlvl_cnt != 5'd1)) begin wr_level_dqs_asrt <= #TCQ 1'd0; end else if ((enable_wrlvl_cnt == 5'd1) && (wrlvl_active_r1)) begin wr_level_dqs_asrt <= #TCQ 1'd1; end end always @ (posedge clk) begin if (rst || (wrlvl_done_r && ~wrlvl_done_r1)) dqs_asrt_cnt <= #TCQ 2'd0; else if (wr_level_dqs_asrt && dqs_asrt_cnt != 2'd3) dqs_asrt_cnt <= #TCQ (dqs_asrt_cnt + 1); end always @ (posedge clk) begin if (rst || ~wrlvl_active) wr_lvl_start <= #TCQ 1'd0; else if (dqs_asrt_cnt == 2'd3) wr_lvl_start <= #TCQ 1'd1; end always @(posedge clk) begin if (rst) wl_sm_start <= #TCQ 1'b0; else wl_sm_start <= #TCQ wr_level_dqs_asrt_r1; end always @(posedge clk) begin wrlvl_active_r1 <= #TCQ wrlvl_active; wr_level_dqs_asrt_r1 <= #TCQ wr_level_dqs_asrt; wrlvl_done_r <= #TCQ wrlvl_done; wrlvl_done_r1 <= #TCQ wrlvl_done_r; wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done; wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1; wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2; wrlvl_rank_done_r4 <= #TCQ wrlvl_rank_done_r3; wrlvl_rank_done_r5 <= #TCQ wrlvl_rank_done_r4; wrlvl_rank_done_r6 <= #TCQ wrlvl_rank_done_r5; wrlvl_rank_done_r7 <= #TCQ wrlvl_rank_done_r6; end always @ (posedge clk) begin //if (rst) wrlvl_rank_cntr <= #TCQ 3'd0; //else if (wrlvl_rank_done) // wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1; end //***************************************************************** // Precharge request logic - those calibration logic blocks // that require greater than tRAS(max) to finish must break up // their calibration into smaller units of time, with precharges // issued in between. This is done using the XXX_PRECH_REQ and // PRECH_DONE handshaking between PHY_INIT and those blocks //***************************************************************** // Shared request from multiple sources assign prech_req = oclk_prech_req | rdlvl_prech_req | wrcal_prech_req | prbs_rdlvl_prech_req | (dqs_found_prech_req & (init_state_r == INIT_RDLVL_STG2_READ_WAIT)); // Handshaking logic to force precharge during read leveling, and to // notify read leveling logic when precharge has been initiated and // it's okay to proceed with leveling again always @(posedge clk) if (rst) begin prech_req_r <= #TCQ 1'b0; prech_req_posedge_r <= #TCQ 1'b0; prech_pending_r <= #TCQ 1'b0; end else begin prech_req_r <= #TCQ prech_req; prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r; if (prech_req_posedge_r) prech_pending_r <= #TCQ 1'b1; // Clear after we've finished with the precharge and have // returned to issuing read leveling calibration reads else if (prech_done_pre) prech_pending_r <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || prech_done_r3) mask_lim_done <= #TCQ 1'b0; else if (prech_pending_r) mask_lim_done <= #TCQ 1'b1; end always @(posedge clk) begin if (rst || prbs_rdlvl_done_r3) complex_mask_lim_done <= #TCQ 1'b0; else if (~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) complex_mask_lim_done <= #TCQ 1'b1; end //Complex oclkdelay calibrration //*************************************************************************** // Various timing counters //*************************************************************************** //***************************************************************** // Generic delay for various states that require it (e.g. for turnaround // between read and write). Make this a sufficiently large number of clock // cycles to cover all possible frequencies and memory components) // Requirements for this counter: // 1. Greater than tMRD // 2. tRFC (refresh-active) for DDR2 // 3. (list the other requirements, slacker...) //***************************************************************** always @(posedge clk) begin case (init_state_r) INIT_LOAD_MR_WAIT, INIT_WRLVL_LOAD_MR_WAIT, INIT_WRLVL_LOAD_MR2_WAIT, INIT_MPR_WAIT, INIT_MPR_DISABLE_PREWAIT, INIT_MPR_DISABLE_WAIT, INIT_OCLKDELAY_ACT_WAIT, INIT_OCLKDELAY_WRITE_WAIT, INIT_RDLVL_ACT_WAIT, INIT_RDLVL_STG1_WRITE_READ, INIT_RDLVL_STG2_READ_WAIT, INIT_WRCAL_ACT_WAIT, INIT_WRCAL_WRITE_READ, INIT_WRCAL_READ_WAIT, INIT_PRECHARGE_PREWAIT, INIT_PRECHARGE_WAIT, INIT_DDR2_PRECHARGE_WAIT, INIT_REG_WRITE_WAIT, INIT_REFRESH_WAIT, INIT_REFRESH_RNK2_WAIT: begin if (phy_ctl_full || phy_cmd_full) cnt_cmd_r <= #TCQ cnt_cmd_r; else cnt_cmd_r <= #TCQ cnt_cmd_r + 1; end INIT_WRLVL_WAIT: cnt_cmd_r <= #TCQ 'b0; default: cnt_cmd_r <= #TCQ 'b0; endcase end // pulse when count reaches terminal count always @(posedge clk) cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD); // For ODT deassertion - hold throughout post read/write wait stage, but // deassert before next command. The post read/write stage is very long, so // we simply address the longest case here plus some margin. always @(posedge clk) cnt_cmd_done_m7_r <= #TCQ (cnt_cmd_r == (CNTNEXT_CMD - 7)); //************************************************************************ // Added to support PO fine delay inc when TG errors always @(posedge clk) begin case (init_state_r) INIT_WRCAL_READ_WAIT: begin if (phy_ctl_full || phy_cmd_full) cnt_wait <= #TCQ cnt_wait; else cnt_wait <= #TCQ cnt_wait + 1; end default: cnt_wait <= #TCQ 'b0; endcase end always @(posedge clk) cnt_wrcal_rd <= #TCQ (cnt_wait == 'd4); always @(posedge clk) begin if (rst || ~temp_wrcal_done) temp_lmr_done <= #TCQ 1'b0; else if (temp_wrcal_done && (init_state_r == INIT_LOAD_MR)) temp_lmr_done <= #TCQ 1'b1; end always @(posedge clk) temp_wrcal_done_r <= #TCQ temp_wrcal_done; always @(posedge clk) if (rst) begin tg_timer_go <= #TCQ 1'b0; end else if ((PRE_REV3ES == "ON") && temp_wrcal_done && temp_lmr_done && (init_state_r == INIT_WRCAL_READ_WAIT)) begin tg_timer_go <= #TCQ 1'b1; end else begin tg_timer_go <= #TCQ 1'b0; end always @(posedge clk) begin if (rst || (temp_wrcal_done && ~temp_wrcal_done_r) || (init_state_r == INIT_PRECHARGE_PREWAIT)) tg_timer <= #TCQ 'd0; else if ((pi_phaselock_timer == PHASELOCKED_TIMEOUT) && tg_timer_go && (tg_timer != TG_TIMER_TIMEOUT)) tg_timer <= #TCQ tg_timer + 1; end always @(posedge clk) begin if (rst) tg_timer_done <= #TCQ 1'b0; else if (tg_timer == TG_TIMER_TIMEOUT) tg_timer_done <= #TCQ 1'b1; else tg_timer_done <= #TCQ 1'b0; end always @(posedge clk) begin if (rst) no_rst_tg_mc <= #TCQ 1'b0; else if ((init_state_r == INIT_WRCAL_ACT) && wrcal_read_req) no_rst_tg_mc <= #TCQ 1'b1; else no_rst_tg_mc <= #TCQ 1'b0; end //************************************************************************ always @(posedge clk) begin if (rst) detect_pi_found_dqs <= #TCQ 1'b0; else if ((cnt_cmd_r == 7'b0111111) && (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) detect_pi_found_dqs <= #TCQ 1'b1; else detect_pi_found_dqs <= #TCQ 1'b0; end //***************************************************************** // Initial delay after power-on for RESET, CKE // NOTE: Could reduce power consumption by turning off these counters // after initial power-up (at expense of more logic) // NOTE: Likely can combine multiple counters into single counter //***************************************************************** // Create divided by 1024 version of clock always @(posedge clk) if (rst) begin cnt_pwron_ce_r <= #TCQ 10'h000; pwron_ce_r <= #TCQ 1'b0; end else begin cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1; pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF); end // "Main" power-on counter - ticks every CLKDIV/1024 cycles always @(posedge clk) if (rst) cnt_pwron_r <= #TCQ 'b0; else if (pwron_ce_r) cnt_pwron_r <= #TCQ cnt_pwron_r + 1; always @(posedge clk) if (rst || ~phy_ctl_ready) begin cnt_pwron_reset_done_r <= #TCQ 1'b0; cnt_pwron_cke_done_r <= #TCQ 1'b0; end else begin // skip power-up count for simulation purposes only if ((SIM_INIT_OPTION == "SKIP_PU_DLY") || (SIM_INIT_OPTION == "SKIP_INIT")) begin cnt_pwron_reset_done_r <= #TCQ 1'b1; cnt_pwron_cke_done_r <= #TCQ 1'b1; end else begin // otherwise, create latched version of done signal for RESET, CKE if (DRAM_TYPE == "DDR3") begin if (!cnt_pwron_reset_done_r) cnt_pwron_reset_done_r <= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT); if (!cnt_pwron_cke_done_r) cnt_pwron_cke_done_r <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); end else begin // DDR2 cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed if (!cnt_pwron_cke_done_r) cnt_pwron_cke_done_r <= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT); end end end // else: !if(rst || ~phy_ctl_ready) always @(posedge clk) cnt_pwron_cke_done_r1 <= #TCQ cnt_pwron_cke_done_r; // Keep RESET asserted and CKE deasserted until after power-on delay always @(posedge clk or posedge rst) begin if (rst) phy_reset_n <= #TCQ 1'b0; else phy_reset_n <= #TCQ cnt_pwron_reset_done_r; // phy_cke <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}}; end //***************************************************************** // Counter for tXPR (pronouned "Tax-Payer") - wait time after // CKE deassertion before first MRS command can be asserted //***************************************************************** always @(posedge clk) if (!cnt_pwron_cke_done_r) begin cnt_txpr_r <= #TCQ 'b0; cnt_txpr_done_r <= #TCQ 1'b0; end else begin cnt_txpr_r <= #TCQ cnt_txpr_r + 1; if (!cnt_txpr_done_r) cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT); end //***************************************************************** // Counter for the initial 400ns wait for issuing precharge all // command after CKE assertion. Only for DDR2. //***************************************************************** always @(posedge clk) if (!cnt_pwron_cke_done_r) begin cnt_init_pre_wait_r <= #TCQ 'b0; cnt_init_pre_wait_done_r <= #TCQ 1'b0; end else begin cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1; if (!cnt_init_pre_wait_done_r) cnt_init_pre_wait_done_r <= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT); end //***************************************************************** // Wait for both DLL to lock (tDLLK) and ZQ calibration to finish // (tZQINIT). Both take the same amount of time (512*tCK) //***************************************************************** always @(posedge clk) if (init_state_r == INIT_ZQCL) begin cnt_dllk_zqinit_r <= #TCQ 'b0; cnt_dllk_zqinit_done_r <= #TCQ 1'b0; end else if (~(phy_ctl_full || phy_cmd_full)) begin cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1; if (!cnt_dllk_zqinit_done_r) cnt_dllk_zqinit_done_r <= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT); end //***************************************************************** // Keep track of which MRS counter needs to be programmed during // memory initialization // The counter and the done signal are reset an additional time // for DDR2. The same signals are used for the additional DDR2 // initialization sequence. //***************************************************************** always @(posedge clk) if ((init_state_r == INIT_IDLE)|| ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))) begin cnt_init_mr_r <= #TCQ 'b0; cnt_init_mr_done_r <= #TCQ 1'b0; end else if (init_state_r == INIT_LOAD_MR) begin cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1; cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE); end //***************************************************************** // Flag to tell if the first precharge for DDR2 init sequence is // done //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) ddr2_pre_flag_r<= #TCQ 'b0; else if (init_state_r == INIT_LOAD_MR) ddr2_pre_flag_r<= #TCQ 1'b1; // reset the flag for multi rank case else if ((ddr2_refresh_flag_r) && (init_state_r == INIT_LOAD_MR_WAIT)&& (cnt_cmd_done_r) && (cnt_init_mr_done_r)) ddr2_pre_flag_r <= #TCQ 'b0; //***************************************************************** // Flag to tell if the refresh stat for DDR2 init sequence is // reached //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) ddr2_refresh_flag_r<= #TCQ 'b0; else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r)) // reset the flag for multi rank case ddr2_refresh_flag_r<= #TCQ 1'b1; else if ((ddr2_refresh_flag_r) && (init_state_r == INIT_LOAD_MR_WAIT)&& (cnt_cmd_done_r) && (cnt_init_mr_done_r)) ddr2_refresh_flag_r <= #TCQ 'b0; //***************************************************************** // Keep track of the number of auto refreshes for DDR2 // initialization. The spec asks for a minimum of two refreshes. // Four refreshes are performed here. The two extra refreshes is to // account for the 200 clock cycle wait between step h and l. // Without the two extra refreshes we would have to have a // wait state. //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) begin cnt_init_af_r <= #TCQ 'b0; cnt_init_af_done_r <= #TCQ 1'b0; end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))begin cnt_init_af_r <= #TCQ cnt_init_af_r + 1; cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11); end //***************************************************************** // Keep track of the register control word programming for // DDR3 RDIMM //***************************************************************** always @(posedge clk) if (init_state_r == INIT_IDLE) reg_ctrl_cnt_r <= #TCQ 'b0; else if (init_state_r == INIT_REG_WRITE) reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1; generate if (RANKS < 2) begin: one_rank always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || (complex_byte_rd_done) || prbs_rdlvl_done_pulse ) stg1_wr_done <= #TCQ 1'b0; else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) stg1_wr_done <= #TCQ 1'b1; end else begin: two_ranks always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || (complex_byte_rd_done) || prbs_rdlvl_done_pulse || (rdlvl_stg1_rank_done )) stg1_wr_done <= #TCQ 1'b0; else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ) stg1_wr_done <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst) rnk_ref_cnt <= #TCQ 1'b0; else if (stg1_wr_done && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r) rnk_ref_cnt <= #TCQ ~rnk_ref_cnt; always @(posedge clk) if (rst || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r ==INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT)) num_refresh <= #TCQ 'd0; else if ((init_state_r == INIT_REFRESH) && (~pi_dqs_found_done || ((DRAM_TYPE == "DDR3") && ~oclkdelay_calib_done) || (rdlvl_stg1_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done))) num_refresh <= #TCQ num_refresh + 1; //*************************************************************************** // Initialization state machine //*************************************************************************** //***************************************************************** // Next-state logic //***************************************************************** always @(posedge clk) if (rst)begin init_state_r <= #TCQ INIT_IDLE; init_state_r1 <= #TCQ INIT_IDLE; end else begin init_state_r <= #TCQ init_next_state; init_state_r1 <= #TCQ init_state_r; end always @(*) begin init_next_state = init_state_r; (* full_case, parallel_case *) case (init_state_r) //******************************************************* // DRAM initialization //******************************************************* // Initial state - wait for: // 1. Power-on delays to pass // 2. PHY Control Block to assert phy_ctl_ready // 3. PHY Control FIFO must not be FULL // 4. Read path initialization to finish INIT_IDLE: if (cnt_pwron_cke_done_r && phy_ctl_ready && ck_addr_cmd_delay_done && delay_incdec_done && ~(phy_ctl_full || phy_cmd_full) ) begin // If skipping memory initialization (simulation only) if (SIM_INIT_OPTION == "SKIP_INIT") //if (WRLVL == "ON") // Proceed to write leveling // init_next_state = INIT_WRLVL_START; //else //if (SIM_CAL_OPTION != "SKIP_CAL") // Proceed to Phaser_In phase lock init_next_state = INIT_RDLVL_ACT; // else // Skip read leveling //init_next_state = INIT_DONE; else init_next_state = INIT_WAIT_CKE_EXIT; end // Wait minimum of Reset CKE exit time (tXPR = max(tXS, INIT_WAIT_CKE_EXIT: if ((cnt_txpr_done_r) && (DRAM_TYPE == "DDR3") && ~(phy_ctl_full || phy_cmd_full)) begin if((REG_CTRL == "ON") && ((nCS_PER_RANK > 1) || (RANKS > 1))) //register write for reg dimm. Some register chips // have the register chip in a pre-programmed state // in that case the nCS_PER_RANK == 1 && RANKS == 1 init_next_state = INIT_REG_WRITE; else // Load mode register - this state is repeated multiple times init_next_state = INIT_LOAD_MR; end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == "DDR2") && ~(phy_ctl_full || phy_cmd_full)) // DDR2 start with a precharge all command init_next_state = INIT_DDR2_PRECHARGE; INIT_REG_WRITE: init_next_state = INIT_REG_WRITE_WAIT; INIT_REG_WRITE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if(reg_ctrl_cnt_r == 4'd8) init_next_state = INIT_LOAD_MR; else init_next_state = INIT_REG_WRITE; end INIT_LOAD_MR: init_next_state = INIT_LOAD_MR_WAIT; // After loading MR, wait at least tMRD INIT_LOAD_MR_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin // If finished loading all mode registers, proceed to next step if (prbs_rdlvl_done && pi_dqs_found_done && rdlvl_stg1_done) // for ddr3 when the correct burst length is writtern at end init_next_state = INIT_PRECHARGE; else if (~wrcal_done && temp_lmr_done) init_next_state = INIT_PRECHARGE_PREWAIT; else if (cnt_init_mr_done_r)begin if(DRAM_TYPE == "DDR3") init_next_state = INIT_ZQCL; else begin //DDR2 if(ddr2_refresh_flag_r)begin // memory initialization per rank for multi-rank case if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) init_next_state = INIT_DDR2_MULTI_RANK; else init_next_state = INIT_RDLVL_ACT; // ddr2 initialization done.load mode state after refresh end else init_next_state = INIT_DDR2_PRECHARGE; end end else init_next_state = INIT_LOAD_MR; end // DDR2 multi rank transition state INIT_DDR2_MULTI_RANK: init_next_state = INIT_DDR2_MULTI_RANK_WAIT; INIT_DDR2_MULTI_RANK_WAIT: init_next_state = INIT_DDR2_PRECHARGE; // Initial ZQ calibration INIT_ZQCL: init_next_state = INIT_WAIT_DLLK_ZQINIT; // Wait until both DLL have locked, and ZQ calibration done INIT_WAIT_DLLK_ZQINIT: if (cnt_dllk_zqinit_done_r && ~(phy_ctl_full || phy_cmd_full)) // memory initialization per rank for multi-rank case if (!mem_init_done_r && (chip_cnt_r <= RANKS-1)) init_next_state = INIT_LOAD_MR; //else if (WRLVL == "ON") // init_next_state = INIT_WRLVL_START; else // skip write-leveling (e.g. for DDR2 interface) init_next_state = INIT_RDLVL_ACT; // Initial precharge for DDR2 INIT_DDR2_PRECHARGE: init_next_state = INIT_DDR2_PRECHARGE_WAIT; INIT_DDR2_PRECHARGE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if (ddr2_pre_flag_r) init_next_state = INIT_REFRESH; else // from precharge state initially go to load mode init_next_state = INIT_LOAD_MR; end INIT_REFRESH: if ((RANKS == 2) && (chip_cnt_r == RANKS - 1)) init_next_state = INIT_REFRESH_RNK2_WAIT; else init_next_state = INIT_REFRESH_WAIT; INIT_REFRESH_RNK2_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_PRECHARGE; INIT_REFRESH_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin if(cnt_init_af_done_r && (~mem_init_done_r)) // go to lm state as part of DDR2 init sequence init_next_state = INIT_LOAD_MR; // Go to state to issue back-to-back writes during limit check and centering else if (~oclkdelay_calib_done && (mpr_last_byte_done || mpr_rdlvl_done) && (DRAM_TYPE == "DDR3")) begin if (num_refresh == 'd8) init_next_state = INIT_OCAL_CENTER_ACT; else init_next_state = INIT_REFRESH; end else if(rdlvl_stg1_done && oclkdelay_center_calib_done && complex_oclkdelay_calib_done && ~wrlvl_done_r1 && (WRLVL == "ON")) init_next_state = INIT_WRLVL_START; else if (pi_dqs_found_done && ~wrlvl_done_r1 && ~wrlvl_final && ~wrlvl_byte_redo && (WRLVL == "ON")) init_next_state = INIT_WRLVL_START; else if ((((prbs_last_byte_done_r || prbs_rdlvl_done) && ~complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON")) //&& rdlvl_stg1_done // changed for new algo 3/26 && mem_init_done_r) begin if (num_refresh == 'd8) begin if (BYPASS_COMPLEX_OCAL == "FALSE") init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else init_next_state = INIT_WRCAL_ACT; end else init_next_state = INIT_REFRESH; end else if (~pi_dqs_found_done || (rdlvl_stg1_done && ~prbs_rdlvl_done && ~complex_oclkdelay_calib_done) || ((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) || ((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)) begin if (num_refresh == 'd8) init_next_state = INIT_RDLVL_ACT; else init_next_state = INIT_REFRESH; end else if ((~wrcal_done && wrlvl_byte_redo)&& (DRAM_TYPE == "DDR3") && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRLVL_LOAD_MR2; else if (((prbs_rdlvl_done && rdlvl_stg1_done && complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON")) && mem_init_done_r && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRCAL_ACT; else if (pi_dqs_found_done && (DRAM_TYPE == "DDR3") && ~(mpr_last_byte_done || mpr_rdlvl_done)) begin if (num_refresh == 'd8) init_next_state = INIT_MPR_RDEN; else init_next_state = INIT_REFRESH; end else if (((oclkdelay_calib_done && wrlvl_final && ~wrlvl_done_r1) || // changed for new algo 3/25 (~wrcal_done && wrlvl_byte_redo)) && (DRAM_TYPE == "DDR3")) init_next_state = INIT_WRLVL_LOAD_MR2; else if ((~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) && pi_dqs_found_done) init_next_state = INIT_WRCAL_ACT; else if (mem_init_done_r) begin if (RANKS < 2) init_next_state = INIT_RDLVL_ACT; else if (stg1_wr_done && ~rnk_ref_cnt && ~rdlvl_stg1_done) init_next_state = INIT_PRECHARGE; else init_next_state = INIT_RDLVL_ACT; end else // to DDR2 init state as part of DDR2 init sequence init_next_state = INIT_REFRESH; end //****************************************************** // Write Leveling //******************************************************* // Enable write leveling in MR1 and start write leveling // for current rank INIT_WRLVL_START: init_next_state = INIT_WRLVL_WAIT; // Wait for both MR load and write leveling to complete // (write leveling should take much longer than MR load..) INIT_WRLVL_WAIT: if (wrlvl_rank_done_r7 && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRLVL_LOAD_MR; // Disable write leveling in MR1 for current rank INIT_WRLVL_LOAD_MR: init_next_state = INIT_WRLVL_LOAD_MR_WAIT; INIT_WRLVL_LOAD_MR_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRLVL_LOAD_MR2; // Load MR2 to set ODT: Dynamic ODT for single rank case // And ODTs for multi-rank case as well INIT_WRLVL_LOAD_MR2: init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; // Wait tMRD before proceeding INIT_WRLVL_LOAD_MR2_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin //if (wrlvl_byte_done) // init_next_state = INIT_PRECHARGE_PREWAIT; // else if ((RANKS == 2) && wrlvl_rank_done_r2) // init_next_state = INIT_WRLVL_LOAD_MR2_WAIT; if (~wrlvl_done_r1) init_next_state = INIT_WRLVL_START; else if (SIM_CAL_OPTION == "SKIP_CAL") // If skip rdlvl, then we're done init_next_state = INIT_DONE; else // Otherwise, proceed to read leveling //init_next_state = INIT_RDLVL_ACT; init_next_state = INIT_PRECHARGE_PREWAIT; end //******************************************************* // Read Leveling //******************************************************* // single row activate. All subsequent read leveling writes and // read will take place in this row INIT_RDLVL_ACT: init_next_state = INIT_RDLVL_ACT_WAIT; // hang out for awhile before issuing subsequent column commands // it's also possible to reach this state at various points // during read leveling - determine what the current stage is INIT_RDLVL_ACT_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin // Just finished an activate. Now either write, read, or precharge // depending on where we are in the training sequence if (!pi_calib_done_r1) init_next_state = INIT_PI_PHASELOCK_READS; else if (!pi_dqs_found_done) // (!pi_dqs_found_start || pi_dqs_found_rank_done)) init_next_state = INIT_RDLVL_STG2_READ; else if (~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500)) init_next_state = INIT_WRCAL_ACT_WAIT; else if ((!rdlvl_stg1_done && ~stg1_wr_done && ~rdlvl_last_byte_done) || (!prbs_rdlvl_done && ~stg1_wr_done && ~prbs_last_byte_done)) begin // Added to avoid rdlvl_stg1 write data pattern at the start of PRBS rdlvl if (!prbs_rdlvl_done && ~stg1_wr_done && rdlvl_last_byte_done) init_next_state = INIT_RDLVL_ACT_WAIT; else init_next_state = INIT_RDLVL_STG1_WRITE; end else if ((!rdlvl_stg1_done && rdlvl_stg1_start_int) || !prbs_rdlvl_done) begin if (rdlvl_last_byte_done || prbs_last_byte_done) // Added to avoid extra reads at the end of read leveling init_next_state = INIT_RDLVL_ACT_WAIT; else begin // Case 2: If in stage 1, and just precharged after training // previous byte, then continue reading if (rdlvl_stg1_done) init_next_state = INIT_RDLVL_STG1_WRITE_READ; else init_next_state = INIT_RDLVL_STG1_READ; end end else if ((prbs_rdlvl_done && rdlvl_stg1_done && (RANKS == 1)) && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK > 2500)) init_next_state = INIT_WRCAL_ACT_WAIT; else // Otherwise, if we're finished with calibration, then precharge // the row - silly, because we just opened it - possible to take // this out by adding logic to avoid the ACT in first place. Make // sure that cnt_cmd_done will handle tRAS(min) init_next_state = INIT_PRECHARGE_PREWAIT; end //************************************************** // Back-to-back reads for Phaser_IN Phase locking // DQS to FREQ_REF clock //************************************************** INIT_PI_PHASELOCK_READS: if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) init_next_state = INIT_PRECHARGE_PREWAIT; //********************************************* // Stage 1 read-leveling (write and continuous read) //********************************************* // Write training pattern for stage 1 // PRBS pattern of TBD length INIT_RDLVL_STG1_WRITE: // 4:1 DDR3 BL8 will require all 8 words in 1 DIV4 clock cycle // 2:1 DDR2/DDR3 BL8 will require 2 DIV2 clock cycles for 8 words // 2:1 DDR2 BL4 will require 1 DIV2 clock cycle for 4 words // An entire row worth of writes issued before proceeding to reads // The number of write is (2^column width)/burst length to accomodate // PRBS pattern for window detection. //VCCO/VCCAUX write is not done if ((complex_num_writes_dec == 1) && ~complex_row0_wr_done && prbs_rdlvl_done && rdlvl_stg1_done_r1) init_next_state = INIT_OCAL_COMPLEX_WRITE_WAIT; //back to back write from row1 else if (stg1_wr_rd_cnt == 9'd1) begin if (rdlvl_stg1_done_r1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else init_next_state = INIT_RDLVL_STG1_WRITE_READ; end INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT: if(read_pause_ext) begin init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; end else begin if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) //At the end of the byte, it goes to REFRESH init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE; end INIT_RDLVL_COMPLEX_PRECHARGE: init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; INIT_RDLVL_COMPLEX_PRECHARGE_WAIT: if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) begin if (prbs_rdlvl_done || prbs_last_byte_done_r) begin // changed for new algo 3/26 // added condition to ensure that limit starts after rdlvl_stg1_done is asserted in the bypass complex rdlvl mode if ((~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) || ~lim_done) init_next_state = INIT_OCAL_CENTER_ACT; //INIT_OCAL_COMPLEX_ACT; // changed for new algo 3/26 else if (lim_done && complex_oclkdelay_calib_start_r2) init_next_state = INIT_RDLVL_COMPLEX_ACT; else init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT; end else init_next_state = INIT_RDLVL_COMPLEX_ACT; end INIT_RDLVL_COMPLEX_ACT: init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT; INIT_RDLVL_COMPLEX_ACT_WAIT: if (complex_rdlvl_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) begin if (oclkdelay_center_calib_start) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; else if (stg1_wr_done) init_next_state = INIT_RDLVL_COMPLEX_READ; else if (~complex_row1_wr_done) if (complex_oclkdelay_calib_start_int && complex_ocal_num_samples_done_r) //WAIT for resume signal for write init_next_state = INIT_OCAL_COMPLEX_RESUME_WAIT; else init_next_state = INIT_RDLVL_STG1_WRITE; else init_next_state = INIT_RDLVL_STG1_WRITE_READ; end // Write-read turnaround INIT_RDLVL_STG1_WRITE_READ: if (reset_rd_addr_r1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin if (rdlvl_stg1_done_r1) init_next_state = INIT_RDLVL_COMPLEX_READ; else init_next_state = INIT_RDLVL_STG1_READ; end // Continuous read, where interruptible by precharge request from // calibration logic. Also precharges when stage 1 is complete // No precharges when reads provided to Phaser_IN for phase locking // FREQ_REF to read DQS since data integrity is not important. INIT_RDLVL_STG1_READ: if (rdlvl_stg1_rank_done || (rdlvl_stg1_done && ~rdlvl_stg1_done_r1) || prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; INIT_RDLVL_COMPLEX_READ: if (prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; //For non-back-to-back reads from row0 (VCCO and VCCAUX pattern) else if (~prbs_rdlvl_done && (complex_num_reads_dec == 1) && ~complex_row0_rd_done) init_next_state = INIT_RDLVL_COMPLEX_READ_WAIT; //For back-to-back reads from row1 (ISI pattern) else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; INIT_RDLVL_COMPLEX_READ_WAIT: if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) init_next_state = INIT_RDLVL_COMPLEX_READ; //********************************************* // DQSFOUND calibration (set of 4 reads with gaps) //********************************************* // Read of training data. Note that Stage 2 is not a constant read, // instead there is a large gap between each set of back-to-back reads INIT_RDLVL_STG2_READ: // 4 read commands issued back-to-back if (num_reads == 'b1) init_next_state = INIT_RDLVL_STG2_READ_WAIT; // Wait before issuing the next set of reads. If a precharge request // comes in then handle - this can occur after stage 2 calibration is // completed for a DQS group INIT_RDLVL_STG2_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if (pi_dqs_found_rank_done || pi_dqs_found_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; else if (cnt_cmd_done_r) init_next_state = INIT_RDLVL_STG2_READ; end //****************************************************************** // MPR Read Leveling for DDR3 OCLK_DELAYED calibration //****************************************************************** // Issue Load Mode Register 3 command with A[2]=1, A[1:0]=2'b00 // to enable Multi Purpose Register (MPR) Read INIT_MPR_RDEN: init_next_state = INIT_MPR_WAIT; //Wait tMRD, tMOD INIT_MPR_WAIT: if (cnt_cmd_done_r) begin init_next_state = INIT_MPR_READ; end // Issue back-to-back read commands to read from MPR with // Address bus 0x0000 for BL=8. DQ[0] will output the pre-defined // MPR pattern of 01010101 (Rise0 = 1'b0, Fall0 = 1'b1 ...) INIT_MPR_READ: if (mpr_rdlvl_done || mpr_rnk_done || rdlvl_prech_req) init_next_state = INIT_MPR_DISABLE_PREWAIT; INIT_MPR_DISABLE_PREWAIT: if (cnt_cmd_done_r) init_next_state = INIT_MPR_DISABLE; // Issue Load Mode Register 3 command with A[2]=0 to disable // MPR read INIT_MPR_DISABLE: init_next_state = INIT_MPR_DISABLE_WAIT; INIT_MPR_DISABLE_WAIT: init_next_state = INIT_PRECHARGE_PREWAIT; //*********************************************************************** // OCLKDELAY Calibration //*********************************************************************** // This calibration requires single write followed by single read to // determine the Phaser_Out stage 3 delay required to center write DQS // in write DQ valid window. // Single Row Activate command before issuing Write command INIT_OCLKDELAY_ACT: init_next_state = INIT_OCLKDELAY_ACT_WAIT; INIT_OCLKDELAY_ACT_WAIT: if (cnt_cmd_done_r && ~oclk_prech_req) init_next_state = INIT_OCLKDELAY_WRITE; else if (oclkdelay_calib_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; INIT_OCLKDELAY_WRITE: if (oclk_wr_cnt == 4'd1) init_next_state = INIT_OCLKDELAY_WRITE_WAIT; INIT_OCLKDELAY_WRITE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if (oclkdelay_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else init_next_state = INIT_OCLKDELAY_READ; end INIT_OCLKDELAY_READ: init_next_state = INIT_OCLKDELAY_READ_WAIT; INIT_OCLKDELAY_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if ((oclk_calib_resume_level || oclk_calib_resume) && ~oclkdelay_int_ref_req) init_next_state = INIT_OCLKDELAY_WRITE; else if (oclkdelay_calib_done || prech_req_posedge_r || wrlvl_final || oclkdelay_int_ref_req) init_next_state = INIT_PRECHARGE_PREWAIT; else if (oclkdelay_center_calib_start) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; end //********************************************* // Write calibration //********************************************* // single row activate INIT_WRCAL_ACT: init_next_state = INIT_WRCAL_ACT_WAIT; // hang out for awhile before issuing subsequent column command INIT_WRCAL_ACT_WAIT: if (cnt_cmd_done_r && ~wrcal_prech_req) init_next_state = INIT_WRCAL_WRITE; else if (wrcal_done || prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; // Write training pattern for write calibration INIT_WRCAL_WRITE: // Once we've issued enough commands for 8 words - proceed to reads //if (burst_addr_r == 1'b1) if (wrcal_wr_cnt == 4'd1) init_next_state = INIT_WRCAL_WRITE_READ; // Write-read turnaround INIT_WRCAL_WRITE_READ: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_WRCAL_READ; else if (dqsfound_retry) init_next_state = INIT_RDLVL_STG2_READ_WAIT; INIT_WRCAL_READ: if (burst_addr_r == 1'b1) init_next_state = INIT_WRCAL_READ_WAIT; INIT_WRCAL_READ_WAIT: if (~(phy_ctl_full || phy_cmd_full)) begin if (wrcal_resume_r) begin if (wrcal_final_chk) init_next_state = INIT_WRCAL_READ; else init_next_state = INIT_WRCAL_WRITE; end else if (wrcal_done || prech_req_posedge_r || wrcal_act_req || // Added to support PO fine delay inc when TG errors wrlvl_byte_redo || (temp_wrcal_done && ~temp_lmr_done)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (dqsfound_retry) init_next_state = INIT_RDLVL_STG2_READ_WAIT; else if (wrcal_read_req && cnt_wrcal_rd) init_next_state = INIT_WRCAL_MULT_READS; end INIT_WRCAL_MULT_READS: // multiple read commands issued back-to-back if (wrcal_reads == 'b1) init_next_state = INIT_WRCAL_READ_WAIT; //********************************************* // Handling of precharge during and in between read-level stages //********************************************* // Make sure we aren't violating any timing specs by precharging // immediately INIT_PRECHARGE_PREWAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) init_next_state = INIT_PRECHARGE; // Initiate precharge INIT_PRECHARGE: init_next_state = INIT_PRECHARGE_WAIT; INIT_PRECHARGE_WAIT: if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin if ((wrcal_sanity_chk_done && (DRAM_TYPE == "DDR3")) || (rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && (DRAM_TYPE == "DDR2"))) init_next_state = INIT_DONE; else if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done && complex_oclkdelay_calib_done && wrlvl_done_r1 && ((ddr3_lm_done_r) || (DRAM_TYPE == "DDR2"))) init_next_state = INIT_WRCAL_ACT; else if ((wrcal_done || (WRLVL == "OFF") || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) && (rdlvl_stg1_done || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done)) && prbs_rdlvl_done && complex_oclkdelay_calib_done && wrlvl_done_r1 &rdlvl_stg1_done && pi_dqs_found_done) begin // after all calibration program the correct burst length init_next_state = INIT_LOAD_MR; // Added to support PO fine delay inc when TG errors end else if (~wrcal_done && temp_wrcal_done && temp_lmr_done) init_next_state = INIT_WRCAL_READ_WAIT; else if (rdlvl_stg1_done && pi_dqs_found_done && (WRLVL == "ON")) // If read leveling finished, proceed to write calibration init_next_state = INIT_REFRESH; else // Otherwise, open row for read-leveling purposes init_next_state = INIT_REFRESH; end //******************************************************* // COMPLEX OCLK calibration - for fragmented write //******************************************************* INIT_OCAL_COMPLEX_ACT: init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; INIT_OCAL_COMPLEX_ACT_WAIT: if (complex_wait_cnt =='d15) init_next_state = INIT_RDLVL_STG1_WRITE; INIT_OCAL_COMPLEX_WRITE_WAIT: if (prech_req_posedge_r || (complex_oclkdelay_calib_done && ~complex_oclkdelay_calib_done_r1)) init_next_state = INIT_PRECHARGE_PREWAIT; else if (stg1_wr_rd_cnt == 'd1) init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT; else if (complex_wait_cnt == 'd15) init_next_state = INIT_RDLVL_STG1_WRITE; //wait for all srg2/stg3 tap movement is done and go back to write again INIT_OCAL_COMPLEX_RESUME_WAIT: if (complex_oclk_calib_resume) init_next_state = INIT_RDLVL_STG1_WRITE; else if (complex_oclkdelay_calib_done || complex_ocal_ref_req ) init_next_state = INIT_PRECHARGE_PREWAIT; //******************************************************* // OCAL STG3 Centering calibration //******************************************************* INIT_OCAL_CENTER_ACT: init_next_state = INIT_OCAL_CENTER_ACT_WAIT; INIT_OCAL_CENTER_ACT_WAIT: if (ocal_act_wait_cnt == 'd15) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; INIT_OCAL_CENTER_WRITE: if(!oclk_center_write_resume && !lim_wr_req) init_next_state = INIT_OCAL_CENTER_WRITE_WAIT; INIT_OCAL_CENTER_WRITE_WAIT: //if (oclkdelay_center_calib_done || prech_req_posedge_r) if (prech_req_posedge_r) init_next_state = INIT_PRECHARGE_PREWAIT; else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && oclkdelay_calib_done && ~oclkdelay_center_calib_start) init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT; else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && ~oclkdelay_center_calib_start) init_next_state = INIT_OCLKDELAY_READ_WAIT; else if (oclk_center_write_resume || lim_wr_req) init_next_state = INIT_OCAL_CENTER_WRITE; //******************************************************* // Initialization/Calibration done. Take a long rest, relax //******************************************************* INIT_DONE: init_next_state = INIT_DONE; endcase end //***************************************************************** // Initialization done signal - asserted before leveling starts //***************************************************************** always @(posedge clk) if (rst) mem_init_done_r <= #TCQ 1'b0; else if ((!cnt_dllk_zqinit_done_r && (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) && (chip_cnt_r == RANKS-1) && (DRAM_TYPE == "DDR3")) || ( (init_state_r == INIT_LOAD_MR_WAIT) && (ddr2_refresh_flag_r) && (chip_cnt_r == RANKS-1) && (cnt_init_mr_done_r) && (DRAM_TYPE == "DDR2"))) mem_init_done_r <= #TCQ 1'b1; //***************************************************************** // Write Calibration signal to PHY Control Block - asserted before // Write Leveling starts //***************************************************************** //generate //if (RANKS < 2) begin: ranks_one always @(posedge clk) begin if (rst || (done_dqs_tap_inc && (init_state_r == INIT_WRLVL_LOAD_MR2))) write_calib <= #TCQ 1'b0; else if (wrlvl_active_r1) write_calib <= #TCQ 1'b1; end //end else begin: ranks_two // always @(posedge clk) begin // if (rst || // ((init_state_r1 == INIT_WRLVL_LOAD_MR_WAIT) && // ((wrlvl_rank_done_r2 && (chip_cnt_r == RANKS-1)) || // (SIM_CAL_OPTION == "FAST_CAL")))) // write_calib <= #TCQ 1'b0; // else if (wrlvl_active_r1) // write_calib <= #TCQ 1'b1; // end //end //endgenerate //***************************************************************** // Read Calibration signal to PHY Control Block - asserted after // Write Leveling during PHASER_IN phase locking stage. // Must be de-asserted before Read Leveling //***************************************************************** always @(posedge clk) begin if (rst || pi_calib_done_r1) read_calib_int <= #TCQ 1'b0; else if (~pi_calib_done_r1 && (init_state_r == INIT_RDLVL_ACT_WAIT) && (cnt_cmd_r == CNTNEXT_CMD)) read_calib_int <= #TCQ 1'b1; end always @(posedge clk) read_calib_r <= #TCQ read_calib_int; always @(posedge clk) begin if (rst || pi_calib_done_r1) read_calib <= #TCQ 1'b0; else if (~pi_calib_done_r1 && (init_state_r == INIT_PI_PHASELOCK_READS)) read_calib <= #TCQ 1'b1; end always @(posedge clk) if (rst) pi_calib_done_r <= #TCQ 1'b0; else if (pi_calib_rank_done_r)// && (chip_cnt_r == RANKS-1)) pi_calib_done_r <= #TCQ 1'b1; always @(posedge clk) if (rst) pi_calib_rank_done_r <= #TCQ 1'b0; else if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4) pi_calib_rank_done_r <= #TCQ 1'b1; else pi_calib_rank_done_r <= #TCQ 1'b0; always @(posedge clk) begin if (rst || ((PRE_REV3ES == "ON") && temp_wrcal_done && ~temp_wrcal_done_r)) pi_phaselock_timer <= #TCQ 'd0; else if (((init_state_r == INIT_PI_PHASELOCK_READS) && (pi_phaselock_timer != PHASELOCKED_TIMEOUT)) || tg_timer_go) pi_phaselock_timer <= #TCQ pi_phaselock_timer + 1; else pi_phaselock_timer <= #TCQ pi_phaselock_timer; end assign pi_phase_locked_err = (pi_phaselock_timer == PHASELOCKED_TIMEOUT) ? 1'b1 : 1'b0; //***************************************************************** // DDR3 final burst length programming done. For DDR3 during // calibration the burst length is fixed to BL8. After calibration // the correct burst length is programmed. //***************************************************************** always @(posedge clk) if (rst) ddr3_lm_done_r <= #TCQ 1'b0; else if ((init_state_r == INIT_LOAD_MR_WAIT) && (chip_cnt_r == RANKS-1) && wrcal_done) ddr3_lm_done_r <= #TCQ 1'b1; always @(posedge clk) begin pi_dqs_found_rank_done_r <= #TCQ pi_dqs_found_rank_done; pi_phase_locked_all_r1 <= #TCQ pi_phase_locked_all; pi_phase_locked_all_r2 <= #TCQ pi_phase_locked_all_r1; pi_phase_locked_all_r3 <= #TCQ pi_phase_locked_all_r2; pi_phase_locked_all_r4 <= #TCQ pi_phase_locked_all_r3; pi_dqs_found_all_r <= #TCQ pi_dqs_found_done; pi_calib_done_r1 <= #TCQ pi_calib_done_r; end //*************************************************************************** // Logic for deep memory (multi-rank) configurations //*************************************************************************** // For DDR3 asserted when generate if (RANKS < 2) begin: single_rank always @(posedge clk) chip_cnt_r <= #TCQ 2'b00; end else begin: dual_rank always @(posedge clk) if (rst || // Set chip_cnt_r to 2'b00 after both Ranks are read leveled (rdlvl_stg1_done && prbs_rdlvl_done && ~wrcal_done) || // Set chip_cnt_r to 2'b00 after both Ranks are write leveled (wrlvl_done_r && (init_state_r==INIT_WRLVL_LOAD_MR2_WAIT)))begin chip_cnt_r <= #TCQ 2'b00; end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) && (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT)) && (DRAM_TYPE == "DDR3")) || ((init_state_r==INIT_REFRESH_RNK2_WAIT) && (cnt_cmd_r=='d36)) || //mpr_rnk_done || //(rdlvl_stg1_rank_done && ~rdlvl_last_byte_done) || //(stg1_wr_done && (init_state_r == INIT_REFRESH) && //~(rnk_ref_cnt && rdlvl_last_byte_done)) || // Increment chip_cnt_r to issue Refresh to second rank (~pi_dqs_found_all_r && (init_state_r==INIT_PRECHARGE_PREWAIT) && (cnt_cmd_r=='d36)) || // Increment chip_cnt_r when DQSFOUND done for the Rank (pi_dqs_found_rank_done && ~pi_dqs_found_rank_done_r) || ((init_state_r == INIT_LOAD_MR_WAIT)&& cnt_cmd_done_r && wrcal_done) || ((init_state_r == INIT_DDR2_MULTI_RANK) && (DRAM_TYPE == "DDR2"))) begin if ((~mem_init_done_r || ~rdlvl_stg1_done || ~pi_dqs_found_done || // condition to increment chip_cnt during // final burst length programming for DDR3 ~pi_calib_done_r || wrcal_done) //~mpr_rdlvl_done || && (chip_cnt_r != RANKS-1)) chip_cnt_r <= #TCQ chip_cnt_r + 1; else chip_cnt_r <= #TCQ 2'b00; end end endgenerate // verilint STARC-2.2.3.3 off generate if ((REG_CTRL == "ON") && (RANKS == 1)) begin: DDR3_RDIMM_1rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[0] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end end else if (RANKS == 1) begin: DDR3_1rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (n = 0; n < nCS_PER_RANK; n = n + 1) begin phy_int_cs_n[n] <= #TCQ 1'b0; end end else begin //odd CWL for (p = nCS_PER_RANK; p < 2*nCS_PER_RANK; p = p + 1) begin phy_int_cs_n[p] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end end else if ((REG_CTRL == "ON") && (RANKS == 2)) begin: DDR3_2rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; case (chip_cnt_r) 2'b00:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[0] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end 2'b01:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) //even CWL phy_int_cs_n[1] <= #TCQ 1'b0; else // odd CWL phy_int_cs_n[1+1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end endcase end end end else if (RANKS == 2) begin: DDR3_2rank always @(posedge clk) begin if (rst) phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; else if (init_state_r == INIT_REG_WRITE) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if(!(CWL_M%2)) begin phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0; end else begin phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0; phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0; end end else begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; case (chip_cnt_r) 2'b00:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (n = 0; n < nCS_PER_RANK; n = n + 1) begin phy_int_cs_n[n] <= #TCQ 1'b0; end end else begin // odd CWL for (p = CS_WIDTH*nCS_PER_RANK; p < (CS_WIDTH*nCS_PER_RANK + nCS_PER_RANK); p = p + 1) begin phy_int_cs_n[p] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end 2'b01:begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; if (!(CWL_M % 2)) begin //even CWL for (q = nCS_PER_RANK; q < (2 * nCS_PER_RANK); q = q + 1) begin phy_int_cs_n[q] <= #TCQ 1'b0; end end else begin // odd CWL for (m = (nCS_PER_RANK*CS_WIDTH + nCS_PER_RANK); m < (nCS_PER_RANK*CS_WIDTH + 2*nCS_PER_RANK); m = m + 1) begin phy_int_cs_n[m] <= #TCQ 1'b0; end end end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; //for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin // // phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; //end end endcase end end // always @ (posedge clk) end // verilint STARC-2.2.3.3 on // commented out for now. Need it for DDR2 2T timing /* end else begin: DDR2 always @(posedge clk) if (rst) begin phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end else begin if (init_state_r == INIT_REG_WRITE) begin // All ranks selected simultaneously phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}}; end else if ((wrlvl_odt) || (init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH)) begin phy_int_cs_n[0] <= #TCQ 1'b0; end else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}}; end // else: !if(rst) end // block: DDR2 */ endgenerate assign phy_cs_n = phy_int_cs_n; //*************************************************************************** // Write/read burst logic for calibration //*************************************************************************** assign rdlvl_wr = (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE); assign rdlvl_rd = (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_MPR_READ) || (init_state_r == INIT_WRCAL_MULT_READS); assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd; assign mmcm_wr = (init_state_r == INIT_OCAL_CENTER_WRITE); //used to de-assert cs_n during centering // assign mmcm_wr = 'b0; // (init_state_r == INIT_OCAL_CENTER_WRITE); //*************************************************************************** // Address generation and logic to count # of writes/reads issued during // certain stages of calibration //*************************************************************************** // Column address generation logic: // Keep track of the current column address - since all bursts are in // increments of 8 only during calibration, we need to keep track of // addresses [COL_WIDTH-1:3], lower order address bits will always = 0 always @(posedge clk) if (rst || wrcal_done) burst_addr_r <= #TCQ 1'b0; else if ((init_state_r == INIT_WRCAL_ACT_WAIT) || (init_state_r == INIT_OCLKDELAY_ACT_WAIT) || (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS) || (init_state_r == INIT_WRCAL_READ_WAIT)) burst_addr_r <= #TCQ 1'b1; else if (rdlvl_wr_rd && new_burst_r) burst_addr_r <= #TCQ ~burst_addr_r; else burst_addr_r <= #TCQ 1'b0; // Read Level Stage 1 requires writes to the entire row since // a PRBS pattern is being written. This counter keeps track // of the number of writes which depends on the column width // The (stg1_wr_rd_cnt==9'd0) condition was added so the col // address wraps around during stage1 reads always @(posedge clk) if (rst || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && ~rdlvl_stg1_done)) stg1_wr_rd_cnt <= #TCQ NUM_STG1_WR_RD; else if (rdlvl_last_byte_done || (stg1_wr_rd_cnt == 9'd1) || (prbs_rdlvl_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) || (init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) ) begin if (~complex_row0_wr_done || wr_victim_inc || (complex_row1_wr_done && (~complex_row0_rd_done || (complex_row0_rd_done && complex_row1_rd_done)))) stg1_wr_rd_cnt <= #TCQ 'd127; else stg1_wr_rd_cnt <= #TCQ prbs_rdlvl_done?'d30 :'d22; end else if (((init_state_r == INIT_RDLVL_STG1_WRITE) && new_burst_r && ~phy_data_full) ||((init_state_r == INIT_RDLVL_COMPLEX_READ) && rdlvl_stg1_done)) stg1_wr_rd_cnt <= #TCQ stg1_wr_rd_cnt - 1; always @(posedge clk) if (rst) wr_victim_inc <= #TCQ 1'b0; else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2) && ~stg1_wr_done) wr_victim_inc <= #TCQ 1'b1; else wr_victim_inc <= #TCQ 1'b0; always @(posedge clk) reset_rd_addr_r1 <= #TCQ reset_rd_addr; generate if (FIXED_VICTIM == "FALSE") begin: row_cnt_victim_rotate always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt == DQ_WIDTH*2-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) complex_row_cnt <= #TCQ 'd0; else if ((((stg1_wr_rd_cnt == 'd22) && ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (complex_rdlvl_int_ref_req && (init_state_r == INIT_REFRESH_WAIT) && (cnt_cmd_r == 'd127)))) || complex_victim_inc || (complex_sample_cnt_inc_r2 && ~complex_victim_inc) || wr_victim_inc || reset_rd_addr_r1)) begin // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 if ((complex_row_cnt < DQ_WIDTH*2-1) && ~stg1_wr_done) complex_row_cnt <= #TCQ complex_row_cnt + 1; // During reads row count requires different conditions for increments else if (stg1_wr_done) begin if (reset_rd_addr_r1) complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16; // When looping multiple times in the same victim bit in a byte else if (complex_sample_cnt_inc_r2 && ~complex_victim_inc) complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16 + rd_victim_sel*2; // When looping through victim bits within a byte else if (complex_row_cnt < pi_stg2_prbs_rdlvl_cnt*16+15) complex_row_cnt <= #TCQ complex_row_cnt + 1; // When the number of samples is done and tap is incremented within a byte else complex_row_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt*16; end end end else begin: row_cnt_victim_fixed always @(posedge clk) if (rst || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done) complex_row_cnt <= #TCQ 'd0; else if ((stg1_wr_rd_cnt == 'd22) && (((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) && (complex_wait_cnt == 'd15)) || complex_rdlvl_int_ref_req)) complex_row_cnt <= #TCQ 'd1; else complex_row_cnt <= #TCQ 'd0; end endgenerate //row count always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done_pulse || complex_byte_rd_done) complex_row_cnt_ocal <= #TCQ 'd0; else if ( prbs_rdlvl_done && (((stg1_wr_rd_cnt == 'd30) && (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE)) || (complex_sample_cnt_inc_r2) || wr_victim_inc)) begin // During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22 if (complex_row_cnt_ocal < COMPLEX_ROW_CNT_BYTE-1) begin complex_row_cnt_ocal <= #TCQ complex_row_cnt_ocal + 1; end end always @(posedge clk) if (rst) complex_odt_ext <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE)) complex_odt_ext <= #TCQ 1'b0; else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd1) && (init_state_r == INIT_RDLVL_STG1_WRITE)) complex_odt_ext <= #TCQ 1'b1; always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt == DQ_WIDTH*2-1))) begin wr_victim_sel <= #TCQ 'd0; wr_byte_cnt <= #TCQ 'd0; end else if (rdlvl_stg1_done_r1 && wr_victim_inc) begin wr_victim_sel <= #TCQ wr_victim_sel + 1; if (wr_victim_sel == 'd7) wr_byte_cnt <= #TCQ wr_byte_cnt + 1; end always @(posedge clk) if (rst) begin wr_victim_sel_ocal <= #TCQ 'd0; end else if (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) begin wr_victim_sel_ocal <= #TCQ 'd0; end else if (prbs_rdlvl_done && wr_victim_inc) begin wr_victim_sel_ocal <= #TCQ wr_victim_sel_ocal + 1; end always @(posedge clk) if (rst) begin victim_sel <= #TCQ 'd0; victim_byte_cnt <= #TCQ 'd0; end else if ((~stg1_wr_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_wr_done)) begin victim_sel <= #TCQ prbs_rdlvl_done? wr_victim_sel_ocal: wr_victim_sel; victim_byte_cnt <= #TCQ prbs_rdlvl_done? complex_oclkdelay_calib_cnt:wr_byte_cnt; end else begin if( (init_state_r == INIT_RDLVL_COMPLEX_ACT) || reset_rd_addr) victim_sel <= #TCQ prbs_rdlvl_done? complex_ocal_rd_victim_sel:rd_victim_sel; victim_byte_cnt <= #TCQ prbs_rdlvl_done? complex_oclkdelay_calib_cnt:pi_stg2_prbs_rdlvl_cnt; end generate if (FIXED_VICTIM == "FALSE") begin: wr_done_victim_rotate always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt < DQ_WIDTH*2-1) && ~prbs_rdlvl_done) || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done || prbs_rdlvl_done_pulse) begin complex_row0_wr_done <= #TCQ 1'b0; end else if ( rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd2)) begin complex_row0_wr_done <= #TCQ 1'b1; end always @(posedge clk) if (rst || (wr_victim_inc && (complex_row_cnt < DQ_WIDTH*2-1) && ~prbs_rdlvl_done) || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done || prbs_rdlvl_done_pulse) begin complex_row1_wr_done <= #TCQ 1'b0; end else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2)) begin complex_row1_wr_done <= #TCQ 1'b1; end end else begin: wr_done_victim_fixed always @(posedge clk) if (rst || prbs_rdlvl_done_pulse || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done ) begin complex_row0_wr_done <= #TCQ 1'b0; end else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd2)) begin complex_row0_wr_done <= #TCQ 1'b1; end always @(posedge clk) if (rst || prbs_rdlvl_done_pulse || (wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) || complex_byte_rd_done ) begin complex_row1_wr_done <= #TCQ 1'b0; end else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2)) begin complex_row1_wr_done <= #TCQ 1'b1; end end endgenerate always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row0_rd_done <= #TCQ 1'b0; else if (complex_sample_cnt_inc) complex_row0_rd_done <= #TCQ 1'b0; else if ( (prbs_rdlvl_start || complex_oclkdelay_calib_start_int) && (stg1_wr_rd_cnt == 9'd2) && complex_row0_wr_done && complex_row1_wr_done) complex_row0_rd_done <= #TCQ 1'b1; always @(posedge clk) complex_row0_rd_done_r1 <= #TCQ complex_row0_rd_done; always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row1_rd_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE)) complex_row1_rd_done <= #TCQ 1'b0; else if (complex_row0_rd_done && (stg1_wr_rd_cnt == 9'd2)) complex_row1_rd_done <= #TCQ 1'b1; always @(posedge clk) complex_row1_rd_done_r1 <= #TCQ complex_row1_rd_done; //calculate row rd num for complex_oclkdelay_calib //once it reached to 8 always @ (posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_row1_rd_cnt <= #TCQ 'd0; else complex_row1_rd_cnt <= #TCQ (complex_row1_rd_done & ~complex_row1_rd_done_r1) ? ((complex_row1_rd_cnt == (COMPLEX_RD-1))? 0:complex_row1_rd_cnt + 'd1) : complex_row1_rd_cnt; //For write, reset rd_done for the byte always @ (posedge clk) begin if (rst || (init_state_r == INIT_RDLVL_STG1_WRITE) || prbs_rdlvl_done_pulse) complex_byte_rd_done <= #TCQ 'b0; else if (prbs_rdlvl_done && (complex_row1_rd_cnt == (COMPLEX_RD-1)) && (complex_row1_rd_done & ~complex_row1_rd_done_r1)) complex_byte_rd_done <= #TCQ 'b1; end always @ (posedge clk) begin complex_byte_rd_done_r1 <= #TCQ complex_byte_rd_done; complex_ocal_num_samples_inc <= #TCQ (complex_byte_rd_done & ~complex_byte_rd_done_r1); end generate if (RANKS < 2) begin: one_rank_complex always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || ( complex_oclkdelay_calib_done && (init_state_r == INIT_RDLVL_STG1_WRITE )) || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT) || prbs_rdlvl_done_pulse ) complex_wr_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; else if ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; end else begin: dual_rank_complex always @(posedge clk) if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || ( complex_oclkdelay_calib_done && (init_state_r == INIT_RDLVL_STG1_WRITE )) || (rdlvl_stg1_rank_done ) || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT) || prbs_rdlvl_done_pulse ) complex_wr_done <= #TCQ 1'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; else if ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13)) complex_wr_done <= #TCQ 1'b1; end endgenerate always @(posedge clk) if (rst) complex_wait_cnt <= #TCQ 'd0; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) || (init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && complex_wait_cnt < 'd15) complex_wait_cnt <= #TCQ complex_wait_cnt + 1; else complex_wait_cnt <= #TCQ 'd0; always @(posedge clk) if (rst) begin complex_num_reads <= #TCQ 'd1; end else if ((((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd14)) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && ext_int_ref_req && (cnt_cmd_r == 'd127))) && ~complex_row0_rd_done) begin if (stg1_wr_rd_cnt > 'd85) begin if (complex_num_reads < 'd6) complex_num_reads <= #TCQ complex_num_reads + 1; else complex_num_reads <= #TCQ 'd1; // Initila value for VCCAUX pattern is 3, 7, and 12 end else if (stg1_wr_rd_cnt > 'd73) begin if (stg1_wr_rd_cnt == 'd85) complex_num_reads <= #TCQ 'd3; else if (complex_num_reads < 'd5) complex_num_reads <= #TCQ complex_num_reads + 1; end else if (stg1_wr_rd_cnt > 'd39) begin if (stg1_wr_rd_cnt == 'd73) complex_num_reads <= #TCQ 'd7; else if (complex_num_reads < 'd10) complex_num_reads <= #TCQ complex_num_reads + 1; end else begin if (stg1_wr_rd_cnt == 'd39) complex_num_reads <= #TCQ 'd12; else if (complex_num_reads < 'd14) complex_num_reads <= #TCQ complex_num_reads + 1; end // Initialize to 1 at the start of reads or after precharge and activate end else if ((((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && ~ext_int_ref_req) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && (stg1_wr_rd_cnt == 'd22))) complex_num_reads <= #TCQ 'd1; always @(posedge clk) if (rst) complex_num_reads_dec <= #TCQ 'd1; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) complex_num_reads_dec <= #TCQ complex_num_reads; else if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (complex_num_reads_dec > 'd0)) complex_num_reads_dec <= #TCQ complex_num_reads_dec - 1; always @(posedge clk) if (rst) complex_address <= #TCQ 'd0; else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ_WAIT)) || ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (init_state_r1 != INIT_OCAL_COMPLEX_WRITE_WAIT))) complex_address <= #TCQ phy_address[COL_WIDTH-1:0]; always @ (posedge clk) if (rst) complex_oclkdelay_calib_start_int <= #TCQ 'b0; else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && prbs_last_byte_done_r) // changed for new algo 3/26 complex_oclkdelay_calib_start_int <= #TCQ 'b1; always @(posedge clk) begin complex_oclkdelay_calib_start_r1 <= #TCQ complex_oclkdelay_calib_start_int; complex_oclkdelay_calib_start_r2 <= #TCQ complex_oclkdelay_calib_start_r1; end always @ (posedge clk) if (rst) complex_oclkdelay_calib_start <= #TCQ 'b0; else if (complex_oclkdelay_calib_start_int && (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT) && prbs_rdlvl_done) // changed for new algo 3/26 complex_oclkdelay_calib_start <= #TCQ 'b1; //packet fragmentation for complex oclkdealy calib write always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) begin complex_num_writes <= #TCQ 'd1; end else if ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14) && ~complex_row0_wr_done) begin if (stg1_wr_rd_cnt > 'd85) begin if (complex_num_writes < 'd6) complex_num_writes <= #TCQ complex_num_writes + 1; else complex_num_writes <= #TCQ 'd1; // Initila value for VCCAUX pattern is 3, 7, and 12 end else if (stg1_wr_rd_cnt > 'd73) begin if (stg1_wr_rd_cnt == 'd85) complex_num_writes <= #TCQ 'd3; else if (complex_num_writes < 'd5) complex_num_writes <= #TCQ complex_num_writes + 1; end else if (stg1_wr_rd_cnt > 'd39) begin if (stg1_wr_rd_cnt == 'd73) complex_num_writes <= #TCQ 'd7; else if (complex_num_writes < 'd10) complex_num_writes <= #TCQ complex_num_writes + 1; end else begin if (stg1_wr_rd_cnt == 'd39) complex_num_writes <= #TCQ 'd12; else if (complex_num_writes < 'd14) complex_num_writes <= #TCQ complex_num_writes + 1; end // Initialize to 1 at the start of write or after precharge and activate end else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row0_wr_done) complex_num_writes <= #TCQ 'd30; else if (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) complex_num_writes <= #TCQ 'd1; always @(posedge clk) if (rst || prbs_rdlvl_done_pulse) complex_num_writes_dec <= #TCQ 'd1; else if (((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT))) complex_num_writes_dec <= #TCQ complex_num_writes; else if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (complex_num_writes_dec > 'd0)) complex_num_writes_dec <= #TCQ complex_num_writes_dec - 1; always @(posedge clk) if (rst) complex_sample_cnt_inc_ocal <= #TCQ 1'b0; else if ((stg1_wr_rd_cnt == 9'd1) && complex_byte_rd_done && prbs_rdlvl_done) complex_sample_cnt_inc_ocal <= #TCQ 1'b1; else complex_sample_cnt_inc_ocal <= #TCQ 1'b0; always @(posedge clk) if (rst) complex_sample_cnt_inc <= #TCQ 1'b0; else if ((stg1_wr_rd_cnt == 9'd1) && complex_row1_rd_done) complex_sample_cnt_inc <= #TCQ 1'b1; else complex_sample_cnt_inc <= #TCQ 1'b0; always @(posedge clk) begin complex_sample_cnt_inc_r1 <= #TCQ complex_sample_cnt_inc; complex_sample_cnt_inc_r2 <= #TCQ complex_sample_cnt_inc_r1; end //complex refresh req always @ (posedge clk) begin if(rst || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_ACT)) ) complex_ocal_ref_done <= #TCQ 1'b1; else if (init_state_r == INIT_RDLVL_STG1_WRITE) complex_ocal_ref_done <= #TCQ 1'b0; end //complex ocal odt extention always @(posedge clk) if (rst) complex_ocal_odt_ext <= #TCQ 1'b0; else if (((init_state_r == INIT_PRECHARGE_PREWAIT) && cnt_cmd_done_m7_r) || (init_state_r == INIT_OCLKDELAY_READ_WAIT)) complex_ocal_odt_ext <= #TCQ 1'b0; else if ((init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT)) complex_ocal_odt_ext <= #TCQ 1'b1; // OCLKDELAY calibration requires multiple writes because // write can be up to 2 cycles early since OCLKDELAY tap // can go down to 0 always @(posedge clk) if (rst || (init_state_r == INIT_OCLKDELAY_WRITE_WAIT) || (oclk_wr_cnt == 4'd0)) oclk_wr_cnt <= #TCQ NUM_STG1_WR_RD; else if ((init_state_r == INIT_OCLKDELAY_WRITE) && new_burst_r && ~phy_data_full) oclk_wr_cnt <= #TCQ oclk_wr_cnt - 1; // Write calibration requires multiple writes because // write can be up to 2 cycles early due to new write // leveling algorithm to avoid late writes always @(posedge clk) if (rst || (init_state_r == INIT_WRCAL_WRITE_READ) || (wrcal_wr_cnt == 4'd0)) wrcal_wr_cnt <= #TCQ NUM_STG1_WR_RD; else if ((init_state_r == INIT_WRCAL_WRITE) && new_burst_r && ~phy_data_full) wrcal_wr_cnt <= #TCQ wrcal_wr_cnt - 1; generate if(nCK_PER_CLK == 4) begin:back_to_back_reads_4_1 // 4 back-to-back reads with gaps for // read data_offset calibration (rdlvl stage 2) always @(posedge clk) if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) num_reads <= #TCQ 3'b000; else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) num_reads <= #TCQ num_reads - 1; else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || phy_cmd_full && new_burst_r) num_reads <= #TCQ 3'b011; end else if(nCK_PER_CLK == 2) begin: back_to_back_reads_2_1 // 4 back-to-back reads with gaps for // read data_offset calibration (rdlvl stage 2) always @(posedge clk) if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT)) num_reads <= #TCQ 3'b000; else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full)) num_reads <= #TCQ num_reads - 1; else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || phy_cmd_full && new_burst_r) num_reads <= #TCQ 3'b111; end endgenerate // back-to-back reads during write calibration always @(posedge clk) if (rst ||(init_state_r == INIT_WRCAL_READ_WAIT)) wrcal_reads <= #TCQ 2'b00; else if ((wrcal_reads > 2'b00) && ~(phy_ctl_full || phy_cmd_full)) wrcal_reads <= #TCQ wrcal_reads - 1; else if ((init_state_r == INIT_WRCAL_MULT_READS) || phy_ctl_full || phy_cmd_full && new_burst_r) wrcal_reads <= #TCQ 'd255; // determine how often to issue row command during read leveling writes // and reads always @(posedge clk) if (rdlvl_wr_rd) begin // 2:1 mode - every other command issued is a data command // 4:1 mode - every command issued is a data command if (nCK_PER_CLK == 2) begin if (!phy_ctl_full) new_burst_r <= #TCQ ~new_burst_r; end else new_burst_r <= #TCQ 1'b1; end else new_burst_r <= #TCQ 1'b1; // indicate when a write is occurring. PHY_WRDATA_EN must be asserted // simultaneous with the corresponding command/address for CWL = 5,6 always @(posedge clk) begin rdlvl_wr_r <= #TCQ rdlvl_wr; calib_wrdata_en <= #TCQ phy_wrdata_en; end always @(posedge clk) begin if (rst || wrcal_done) extend_cal_pat <= #TCQ 1'b0; else if (temp_lmr_done && (PRE_REV3ES == "ON")) extend_cal_pat <= #TCQ 1'b1; end generate if ((nCK_PER_CLK == 4) || (BURST_MODE == "4")) begin: wrdqen_div4 // Write data enable asserted for one DIV4 clock cycle // Only BL8 supported with DIV4. DDR2 BL4 will use DIV2. always @(*) begin if (~phy_data_full && ((init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_WRCAL_WRITE))) phy_wrdata_en = 1'b1; else phy_wrdata_en = 1'b0; end end else begin: wrdqen_div2 // block: wrdqen_div4 always @(*) if((rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full) | phy_wrdata_en_r1) phy_wrdata_en = 1'b1; else phy_wrdata_en = 1'b0; always @(posedge clk) phy_wrdata_en_r1 <= #TCQ rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full; always @(posedge clk) begin if (!phy_wrdata_en & first_rdlvl_pat_r) wrdata_pat_cnt <= #TCQ 2'b00; else if (wrdata_pat_cnt == 2'b11) wrdata_pat_cnt <= #TCQ 2'b10; else wrdata_pat_cnt <= #TCQ wrdata_pat_cnt + 1; end always @(posedge clk) begin if (!phy_wrdata_en & first_wrcal_pat_r) wrcal_pat_cnt <= #TCQ 2'b00; else if (extend_cal_pat && (wrcal_pat_cnt == 2'b01)) wrcal_pat_cnt <= #TCQ 2'b00; else if (wrcal_pat_cnt == 2'b11) wrcal_pat_cnt <= #TCQ 2'b10; else wrcal_pat_cnt <= #TCQ wrcal_pat_cnt + 1; end end endgenerate // indicate when a write is occurring. PHY_RDDATA_EN must be asserted // simultaneous with the corresponding command/address. PHY_RDDATA_EN // is used during read-leveling to determine read latency assign phy_rddata_en = ~phy_if_empty; // Read data valid generation for MC and User Interface after calibration is // complete assign phy_rddata_valid = init_complete_r1_timing ? phy_rddata_en : 1'b0; //*************************************************************************** // Generate training data written at start of each read-leveling stage // For every stage of read leveling, 8 words are written into memory // The format is as follows (shown as {rise,fall}): // Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0 // Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6 //*************************************************************************** always @(posedge clk) if ((init_state_r == INIT_IDLE) || (init_state_r == INIT_RDLVL_STG1_WRITE)) cnt_init_data_r <= #TCQ 2'b00; else if (phy_wrdata_en) cnt_init_data_r <= #TCQ cnt_init_data_r + 1; else if (init_state_r == INIT_WRCAL_WRITE) cnt_init_data_r <= #TCQ 2'b10; // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling always @(posedge clk) if (rst || rdlvl_stg1_rank_done) first_rdlvl_pat_r <= #TCQ 1'b1; else if (phy_wrdata_en && (init_state_r == INIT_RDLVL_STG1_WRITE)) first_rdlvl_pat_r <= #TCQ 1'b0; always @(posedge clk) if (rst || wrcal_resume || (init_state_r == INIT_WRCAL_ACT_WAIT)) first_wrcal_pat_r <= #TCQ 1'b1; else if (phy_wrdata_en && (init_state_r == INIT_WRCAL_WRITE)) first_wrcal_pat_r <= #TCQ 1'b0; generate if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 2)) begin: wrdq_div2_2to1_rdlvl_first always @(posedge clk) if (~oclkdelay_calib_done) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}}; else if (!rdlvl_stg1_done) begin // The 16 words for stage 1 write data in 2:1 mode is written // over 4 consecutive controller clock cycles. Note that write // data follows phy_wrdata_en by one clock cycle case (wrdata_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}}, {DQ_WIDTH/4{4'h9}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end endcase end else if (!prbs_rdlvl_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ end else if (!wrcal_done) begin case (wrcal_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h5}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, {DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h4}}}; end endcase end end else if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 4)) begin: wrdq_div2_4to1_rdlvl_first always @(posedge clk) if (~oclkdelay_calib_done) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; else if (!rdlvl_stg1_done && ~phy_data_full) // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling if (first_rdlvl_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; else // For all others, change the first two words written in order // to differentiate the "early write" and "on-time write" // readback patterns during read leveling phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; else if (~(prbs_rdlvl_done || prbs_last_byte_done_r) && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ else if (!wrcal_done) if (first_wrcal_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (nCK_PER_CLK == 4) begin: wrdq_div1_4to1_wrcal_first always @(posedge clk) if ((~oclkdelay_calib_done) && (DRAM_TYPE == "DDR3")) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}}; else if ((!wrcal_done)&& (DRAM_TYPE == "DDR3")) begin if (extend_cal_pat) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else if (first_wrcal_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}}; else phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (!rdlvl_stg1_done && ~phy_data_full) begin // write different sequence for very // first write to memory only. Used to help us differentiate // if the writes are "early" or "on-time" during read leveling if (first_rdlvl_pat_r) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}}; else // For all others, change the first two words written in order // to differentiate the "early write" and "on-time write" // readback patterns during read leveling phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}}, {DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}}; end else if (!prbs_rdlvl_done && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}}, {DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}}, {DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ else if (!complex_oclkdelay_calib_done && ~phy_data_full) phy_wrdata <= #TCQ prbs_o; end else begin: wrdq_div1_2to1_wrcal_first always @(posedge clk) if ((~oclkdelay_calib_done)&& (DRAM_TYPE == "DDR3")) phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}, {DQ_WIDTH/4{4'h0}}}; else if ((!wrcal_done) && (DRAM_TYPE == "DDR3"))begin case (wrcal_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h0}}, {DQ_WIDTH/4{4'hF}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hA}}, {DQ_WIDTH/4{4'h5}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}}, {DQ_WIDTH/4{4'hD}}, {DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h4}}}; end endcase end else if (!rdlvl_stg1_done) begin // The 16 words for stage 1 write data in 2:1 mode is written // over 4 consecutive controller clock cycles. Note that write // data follows phy_wrdata_en by one clock cycle case (wrdata_pat_cnt) 2'b00: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h3}}, {DQ_WIDTH/4{4'h9}}}; end 2'b01: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end 2'b10: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}}, {DQ_WIDTH/4{4'h7}}, {DQ_WIDTH/4{4'h1}}, {DQ_WIDTH/4{4'hB}}}; end 2'b11: begin phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}}, {DQ_WIDTH/4{4'h2}}, {DQ_WIDTH/4{4'h9}}, {DQ_WIDTH/4{4'hC}}}; end endcase end else if (!prbs_rdlvl_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; // prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in // prbs_o being concatenated 8 times resulting in DQ_WIDTH /*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}}, {DQ_WIDTH/8{prbs_o[3*8-1:2*8]}}, {DQ_WIDTH/8{prbs_o[2*8-1:8]}}, {DQ_WIDTH/8{prbs_o[8-1:0]}}};*/ end else if (!complex_oclkdelay_calib_done && ~phy_data_full) begin phy_wrdata <= #TCQ prbs_o; end end endgenerate //*************************************************************************** // Memory control/address //*************************************************************************** // Phases [2] and [3] are always deasserted for 4:1 mode generate if (nCK_PER_CLK == 4) begin: gen_div4_ca_tieoff always @(posedge clk) begin phy_ras_n[3:2] <= #TCQ 3'b11; phy_cas_n[3:2] <= #TCQ 3'b11; phy_we_n[3:2] <= #TCQ 3'b11; end end endgenerate // Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging // (4) auto refresh // verilint STARC-2.7.3.3b off generate if (!(CWL_M % 2)) begin: even_cwl always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_REFRESH) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT))begin phy_ras_n[0] <= #TCQ 1'b0; phy_ras_n[1] <= #TCQ 1'b1; end else begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b1; end end // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command // (3) auto refresh always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_REFRESH) || (rdlvl_wr_rd && new_burst_r))begin phy_cas_n[0] <= #TCQ 1'b0; phy_cas_n[1] <= #TCQ 1'b1; end else begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b1; end end // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only // occur during read leveling), (3) Issuing ZQ Long Calib command, // (4) Precharge always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE)|| (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (rdlvl_wr && new_burst_r))begin phy_we_n[0] <= #TCQ 1'b0; phy_we_n[1] <= #TCQ 1'b1; end else begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b1; end end end else begin: odd_cwl always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_REFRESH))begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b0; end else begin phy_ras_n[0] <= #TCQ 1'b1; phy_ras_n[1] <= #TCQ 1'b1; end end // Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command // (3) auto refresh always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_REFRESH) || (rdlvl_wr_rd && new_burst_r))begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b0; end else begin phy_cas_n[0] <= #TCQ 1'b1; phy_cas_n[1] <= #TCQ 1'b1; end end // Assert WE when: (1) Loading MRS, (2) Issuing Write command (only // occur during read leveling), (3) Issuing ZQ Long Calib command, // (4) Precharge always @(posedge clk) begin if ((init_state_r == INIT_LOAD_MR) || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_MPR_DISABLE) || (init_state_r == INIT_REG_WRITE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_WRLVL_START) || (init_state_r == INIT_WRLVL_LOAD_MR) || (init_state_r == INIT_WRLVL_LOAD_MR2) || (init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_DDR2_PRECHARGE)|| (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (rdlvl_wr && new_burst_r))begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b0; end else begin phy_we_n[0] <= #TCQ 1'b1; phy_we_n[1] <= #TCQ 1'b1; end end end endgenerate // verilint STARC-2.7.3.3b on // Assign calib_cmd for the command field in PHY_Ctl_Word always @(posedge clk) begin if (wr_level_dqs_asrt) begin // Request to toggle DQS during write leveling calib_cmd <= #TCQ 3'b001; if (CWL_M % 2) begin // odd write latency calib_data_offset_0 <= #TCQ CWL_M + 3; calib_data_offset_1 <= #TCQ CWL_M + 3; calib_data_offset_2 <= #TCQ CWL_M + 3; calib_cas_slot <= #TCQ 2'b01; end else begin // even write latency calib_data_offset_0 <= #TCQ CWL_M + 2; calib_data_offset_1 <= #TCQ CWL_M + 2; calib_data_offset_2 <= #TCQ CWL_M + 2; calib_cas_slot <= #TCQ 2'b00; end end else if (rdlvl_wr && new_burst_r) begin // Write Command calib_cmd <= #TCQ 3'b001; if (CWL_M % 2) begin // odd write latency calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1; calib_cas_slot <= #TCQ 2'b01; end else begin // even write latency calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ; calib_cas_slot <= #TCQ 2'b00; end end else if (rdlvl_rd && new_burst_r) begin // Read Command calib_cmd <= #TCQ 3'b011; if (CWL_M % 2) calib_cas_slot <= #TCQ 2'b01; else calib_cas_slot <= #TCQ 2'b00; if (~pi_calib_done_r1) begin calib_data_offset_0 <= #TCQ 6'd0; calib_data_offset_1 <= #TCQ 6'd0; calib_data_offset_2 <= #TCQ 6'd0; end else if (~pi_dqs_found_done_r1) begin calib_data_offset_0 <= #TCQ rd_data_offset_0; calib_data_offset_1 <= #TCQ rd_data_offset_1; calib_data_offset_2 <= #TCQ rd_data_offset_2; end else begin calib_data_offset_0 <= #TCQ rd_data_offset_ranks_0[6*chip_cnt_r+:6]; calib_data_offset_1 <= #TCQ rd_data_offset_ranks_1[6*chip_cnt_r+:6]; calib_data_offset_2 <= #TCQ rd_data_offset_ranks_2[6*chip_cnt_r+:6]; end end else begin // Non-Data Commands like NOP, MRS, ZQ Long Cal, Precharge, // Active, Refresh calib_cmd <= #TCQ 3'b100; calib_data_offset_0 <= #TCQ 6'd0; calib_data_offset_1 <= #TCQ 6'd0; calib_data_offset_2 <= #TCQ 6'd0; if (CWL_M % 2) calib_cas_slot <= #TCQ 2'b01; else calib_cas_slot <= #TCQ 2'b00; end end // Write Enable to PHY_Control FIFO always asserted // No danger of this FIFO being Full with 4:1 sync clock ratio // This is also the write enable to the command OUT_FIFO always @(posedge clk) begin if (rst) begin calib_ctl_wren <= #TCQ 1'b0; calib_cmd_wren <= #TCQ 1'b0; calib_seq <= #TCQ 2'b00; end else if (cnt_pwron_cke_done_r && phy_ctl_ready && ~(phy_ctl_full || phy_cmd_full )) begin calib_ctl_wren <= #TCQ 1'b1; calib_cmd_wren <= #TCQ 1'b1; calib_seq <= #TCQ calib_seq + 1; end else begin calib_ctl_wren <= #TCQ 1'b0; calib_cmd_wren <= #TCQ 1'b0; calib_seq <= #TCQ calib_seq; end end generate genvar rnk_i; for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk always @(posedge clk) begin if (rst) begin mr2_r[rnk_i] <= #TCQ 2'b00; mr1_r[rnk_i] <= #TCQ 3'b000; end else begin mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i]; mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i]; end end end endgenerate // ODT assignment based on slot config and slot present // For single slot systems slot_1_present input will be ignored // Assuming component interfaces to be single slot systems generate if (nSLOTS == 1) begin: gen_single_slot_odt always @(posedge clk) begin if (rst) begin tmp_mr2_r[1] <= #TCQ 2'b00; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; tmp_mr1_r[1] <= #TCQ 3'b000; tmp_mr1_r[2] <= #TCQ 3'b000; tmp_mr1_r[3] <= #TCQ 3'b000; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; phy_tmp_odt_r <= #TCQ 4'b0000; phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; end else begin case ({slot_0_present[0],slot_0_present[1], slot_0_present[2],slot_0_present[3]}) // Single slot configuration with quad rank // Assuming same behavior as single slot dual rank for now // DDR2 does not have quad rank parts 4'b1111: begin if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 RTT_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 RTT_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end phy_tmp_odt_r <= #TCQ 4'b0001; // Chip Select assignments phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) ) +: nCS_PER_RANK] <= #TCQ 'b0; end // Single slot configuration with single rank 4'b1000: begin phy_tmp_odt_r <= #TCQ 4'b0001; if ((REG_CTRL == "ON") && (nCS_PER_RANK > 1)) begin phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0; end else begin phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; end if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && ((cnt_init_mr_r == 2'd0) || (USE_ODT_PORT == 1)))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 RTT_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 RTT_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Single slot configuration with dual rank 4'b1100: begin phy_tmp_odt_r <= #TCQ 4'b0001; // Chip Select assignments phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK) ) +: nCS_PER_RANK] <= #TCQ 'b0; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end default: begin phy_tmp_odt_r <= #TCQ 4'b0001; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end endcase end end end else if (nSLOTS == 2) begin: gen_dual_slot_odt always @ (posedge clk) begin if (rst) begin tmp_mr2_r[1] <= #TCQ 2'b00; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; tmp_mr1_r[1] <= #TCQ 3'b000; tmp_mr1_r[2] <= #TCQ 3'b000; tmp_mr1_r[3] <= #TCQ 3'b000; phy_tmp_odt_r <= #TCQ 4'b0000; phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}}; phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r; end else begin case ({slot_0_present[0],slot_0_present[1], slot_1_present[0],slot_1_present[1]}) // Two slot configuration, one slot present, single rank 4'b10_00: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end 4'b00_10: begin //Rank1 ODT enabled if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank1 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank1 Rtt_NOM defaults to 120 ohms tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Two slot configuration, one slot present, dual rank 4'b00_11: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end 4'b11_00: begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // odt turned on only during write phy_tmp_odt_r <= #TCQ 4'b0001; end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank1 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end end // Two slot configuration, one rank per slot 4'b10_10: begin if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r == 2'b00)begin phy_tmp_odt_r <= #TCQ 4'b0010; //bit0 for rank0 end else begin phy_tmp_odt_r <= #TCQ 4'b0001; //bit0 for rank0 end end else begin if((init_state_r == INIT_WRLVL_WAIT) || (init_next_state == INIT_RDLVL_STG1_WRITE) || (init_next_state == INIT_WRCAL_WRITE) || (init_next_state == INIT_OCAL_CENTER_WRITE) || (init_next_state == INIT_OCLKDELAY_WRITE)) phy_tmp_odt_r <= #TCQ 4'b0011; // bit0 for rank0/1 (write) else if ((init_next_state == INIT_PI_PHASELOCK_READS) || (init_next_state == INIT_MPR_READ) || (init_next_state == INIT_RDLVL_STG1_READ) || (init_next_state == INIT_RDLVL_COMPLEX_READ) || (init_next_state == INIT_RDLVL_STG2_READ) || (init_next_state == INIT_OCLKDELAY_READ) || (init_next_state == INIT_WRCAL_READ) || (init_next_state == INIT_WRCAL_MULT_READS)) phy_tmp_odt_r <= #TCQ 4'b0010; // bit0 for rank1 (rank 0 rd) end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_WR == "60") ? 3'b001 : (RTT_WR == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; end end // Two Slots - One slot with dual rank and other with single rank 4'b10_11: begin //Rank3 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[1] <= #TCQ 3'b000; end //Slot1 Rank1 or Rank3 is being written if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r == 2'b00)begin phy_tmp_odt_r <= #TCQ 4'b0010; end else begin phy_tmp_odt_r <= #TCQ 4'b0001; end end else begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0011; //Slot0 Rank0 is being written end else begin phy_tmp_odt_r <= #TCQ 4'b0101; // ODT for ranks 0 and 2 aserted end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))begin if (chip_cnt_r == 2'b00) begin phy_tmp_odt_r <= #TCQ 4'b0100; end else begin phy_tmp_odt_r <= #TCQ 4'b0001; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end // Two Slots - One slot with dual rank and other with single rank 4'b11_10: begin //Rank2 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : (RTT_NOM2 == "120") ? 3'b010 : (RTT_NOM2 == "20") ? 3'b100 : (RTT_NOM2 == "30") ? 3'b101 : (RTT_NOM2 == "40") ? 3'b011: 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011: 3'b000; //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r[1] == 1'b1)begin phy_tmp_odt_r <= #TCQ 4'b0001; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; // rank 2 ODT asserted end end else begin if (// wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin if (chip_cnt_r[1] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0110; end else begin phy_tmp_odt_r <= #TCQ 4'b0101; end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS)) begin if (chip_cnt_r[1] == 1'b1) begin phy_tmp_odt_r[(1*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ 4'b0010; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end // Two Slots - two ranks per slot 4'b11_11: begin //Rank2 Rtt_NOM tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 : (RTT_NOM2 == "120") ? 3'b010 : (RTT_NOM2 == "20") ? 3'b100 : (RTT_NOM2 == "30") ? 3'b101 : (RTT_NOM2 == "40") ? 3'b011 : 3'b000; //Rank3 Rtt_NOM tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 : (RTT_NOM3 == "120") ? 3'b010 : (RTT_NOM3 == "20") ? 3'b100 : (RTT_NOM3 == "30") ? 3'b101 : (RTT_NOM3 == "40") ? 3'b011 : 3'b000; tmp_mr2_r[2] <= #TCQ 2'b00; tmp_mr2_r[3] <= #TCQ 2'b00; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done && (wrlvl_rank_cntr==3'd0))) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; end else begin //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM after write leveling completes tmp_mr1_r[1] <= #TCQ 3'b000; //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM after write leveling completes tmp_mr1_r[0] <= #TCQ 3'b000; end if(DRAM_TYPE == "DDR2")begin if(chip_cnt_r[1] == 1'b1)begin phy_tmp_odt_r <= #TCQ 4'b0001; end else begin phy_tmp_odt_r <= #TCQ 4'b0100; end end else begin if (//wrlvl_odt || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin //Slot1 Rank1 or Rank3 is being written if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0110; //Slot0 Rank0 or Rank2 is being written end else begin phy_tmp_odt_r <= #TCQ 4'b1001; end end else if ((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))begin //Slot1 Rank1 or Rank3 is being read if (chip_cnt_r[0] == 1'b1) begin phy_tmp_odt_r <= #TCQ 4'b0100; //Slot0 Rank0 or Rank2 is being read end else begin phy_tmp_odt_r <= #TCQ 4'b1000; end end end // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; end default: begin phy_tmp_odt_r <= #TCQ 4'b1111; // Chip Select assignments phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}}; if ((RTT_WR == "OFF") || ((WRLVL=="ON") && ~wrlvl_done)) begin //Rank0 Dynamic ODT disabled tmp_mr2_r[0] <= #TCQ 2'b00; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : 3'b000; //Rank1 Dynamic ODT disabled tmp_mr2_r[1] <= #TCQ 2'b00; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 : (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "60") ? 3'b010 : 3'b000; end else begin //Rank0 Dynamic ODT defaults to 120 ohms tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank0 Rtt_NOM tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; //Rank1 Dynamic ODT defaults to 120 ohms tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 : 2'b10; //Rank1 Rtt_NOM tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 : (RTT_NOM_int == "120") ? 3'b010 : (RTT_NOM_int == "20") ? 3'b100 : (RTT_NOM_int == "30") ? 3'b101 : (RTT_NOM_int == "40") ? 3'b011 : 3'b000; end end endcase end end end endgenerate // PHY only supports two ranks. // calib_aux_out[0] is CKE for rank 0 and calib_aux_out[1] is ODT for rank 0 // calib_aux_out[2] is CKE for rank 1 and calib_aux_out[3] is ODT for rank 1 generate if(CKE_ODT_AUX == "FALSE") begin if ((nSLOTS == 1) && (RANKS < 2)) begin always @(posedge clk) if (rst) begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || wrlvl_rank_done || wrlvl_rank_done_r1 || (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt ) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || complex_odt_ext || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_OCAL_CENTER_WRITE) || complex_ocal_odt_ext || (init_state_r == INIT_OCLKDELAY_WRITE)|| (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin // Quad rank in a single slot calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end end end else if ((nSLOTS == 1) && (RANKS <= 2)) begin always @(posedge clk) if (rst) begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt)|| (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) || complex_odt_ext || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_WRITE_READ) || (init_state_r == INIT_OCAL_CENTER_WRITE) || complex_ocal_odt_ext || (init_state_r == INIT_OCLKDELAY_WRITE)|| (init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin // Dual rank in a single slot calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end end end else if ((nSLOTS == 2) && (RANKS == 2)) begin always @(posedge clk) if (rst)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ; calib_odt <= 2'b00 ; end else begin if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin calib_cke <= #TCQ {nCK_PER_CLK{1'b1}}; end else begin calib_cke <= #TCQ {nCK_PER_CLK{1'b0}}; end if (((DRAM_TYPE == "DDR2") && (RTT_NOM == "DISABLED")) || ((DRAM_TYPE == "DDR3") && (RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))) begin calib_odt[0] <= #TCQ 1'b0; calib_odt[1] <= #TCQ 1'b0; end else if (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE)) begin // Quad rank in a single slot if (nCK_PER_CLK == 2) begin calib_odt[0] <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; calib_odt[1] <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end // Turn on for idle rank during read if dynamic ODT is enabled in DDR3 end else if(((DRAM_TYPE == "DDR3") && (RTT_WR != "OFF")) && ((init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_MPR_READ) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ) || (init_state_r == INIT_RDLVL_STG2_READ) || (init_state_r == INIT_OCLKDELAY_READ) || (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS))) begin if (nCK_PER_CLK == 2) begin calib_odt[0] <= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0; calib_odt[1] <= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_odt[0] <= #TCQ phy_tmp_odt_r[0]; calib_odt[1] <= #TCQ phy_tmp_odt_r[1]; end // disable well before next command and before disabling write leveling end else if(cnt_cmd_done_m7_r || (init_state_r == INIT_WRLVL_WAIT && ~wrlvl_odt)) calib_odt <= #TCQ 2'b00; end end end else begin//USE AUX OUTPUT for routing CKE and ODT. if ((nSLOTS == 1) && (RANKS < 2)) begin always @(posedge clk) if (rst) begin calib_aux_out <= #TCQ 4'b0000; end else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done || wrlvl_rank_done_r1 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Quad rank in a single slot calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end else if ((nSLOTS == 1) && (RANKS <= 2)) begin always @(posedge clk) if (rst) begin calib_aux_out <= #TCQ 4'b0000; end else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Dual rank in a single slot calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end else if ((nSLOTS == 2) && (RANKS == 2)) begin always @(posedge clk) if (rst) calib_aux_out <= #TCQ 4'b0000; else begin if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin calib_aux_out[0] <= #TCQ 1'b1; calib_aux_out[2] <= #TCQ 1'b1; end else begin calib_aux_out[0] <= #TCQ 1'b0; calib_aux_out[2] <= #TCQ 1'b0; end if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) || wrlvl_rank_done_r2 || (wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end else if (((DRAM_TYPE == "DDR3") ||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2"))) && (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_WRITE))) begin // Quad rank in a single slot if (nCK_PER_CLK == 2) begin calib_aux_out[1] <= #TCQ (!calib_aux_out[1]) ? phy_tmp_odt_r[0] : 1'b0; calib_aux_out[3] <= #TCQ (!calib_aux_out[3]) ? phy_tmp_odt_r[1] : 1'b0; end else begin calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0]; calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1]; end end else begin calib_aux_out[1] <= #TCQ 1'b0; calib_aux_out[3] <= #TCQ 1'b0; end end end end endgenerate //***************************************************************** // memory address during init //***************************************************************** always @(posedge clk) phy_data_full_r <= #TCQ phy_data_full; // verilint STARC-2.7.3.3b off always @(*)begin // Bus 0 for address/bank never used address_w = 'b0; bank_w = 'b0; if ((init_state_r == INIT_PRECHARGE) || (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_ZQCL) || (init_state_r == INIT_DDR2_PRECHARGE)) begin // Set A10=1 for ZQ long calibration or Precharge All address_w = 'b0; address_w[10] = 1'b1; bank_w = 'b0; end else if (init_state_r == INIT_WRLVL_START) begin // Enable wrlvl in MR1 bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; address_w[7] = 1'b1; end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin // Finished with write leveling, disable wrlvl in MR1 // For single rank disable Rtt_Nom bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin // Set RTT_WR in MR2 after write leveling disabled bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; address_w[10:9] = mr2_r[chip_cnt_r]; end else if (init_state_r == INIT_MPR_READ) begin address_w = 'b0; bank_w = 'b0; end else if (init_state_r == INIT_MPR_RDEN) begin // Enable MPR read with LMR3 and A2=1 bank_w[BANK_WIDTH-1:0] = 'd3; address_w = {ROW_WIDTH{1'b0}}; address_w[2] = 1'b1; end else if (init_state_r == INIT_MPR_DISABLE) begin // Disable MPR read with LMR3 and A2=0 bank_w[BANK_WIDTH-1:0] = 'd3; address_w = {ROW_WIDTH{1'b0}}; end else if ((init_state_r == INIT_REG_WRITE)& (DRAM_TYPE == "DDR3"))begin // bank_w is assigned a 3 bit value. In some // DDR2 cases there will be only two bank bits. //Qualifying the condition with DDR3 bank_w = 'b0; address_w = 'b0; case (reg_ctrl_cnt_r) 4'h1:begin address_w[4:0] = REG_RC1[4:0]; bank_w = REG_RC1[7:5]; end 4'h2: address_w[4:0] = REG_RC2[4:0]; 4'h3: begin address_w[4:0] = REG_RC3[4:0]; bank_w = REG_RC3[7:5]; end 4'h4: begin address_w[4:0] = REG_RC4[4:0]; bank_w = REG_RC4[7:5]; end 4'h5: begin address_w[4:0] = REG_RC5[4:0]; bank_w = REG_RC5[7:5]; end 4'h6: begin address_w[4:0] = REG_RC10[4:0]; bank_w = REG_RC10[7:5]; end 4'h7: begin address_w[4:0] = REG_RC11[4:0]; bank_w = REG_RC11[7:5]; end default: address_w[4:0] = REG_RC0[4:0]; endcase end else if (init_state_r == INIT_LOAD_MR) begin // If loading mode register, look at cnt_init_mr to determine // which MR is currently being programmed address_w = 'b0; bank_w = 'b0; if(DRAM_TYPE == "DDR3")begin if(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done)begin // end of the calibration programming correct // burst length if (TEST_AL == "0") begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //Don't reset DLL end else begin // programming correct AL value bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; if (TEST_AL == "CL-1") address_w[4:3]= 2'b01; // AL="CL-1" else address_w[4:3]= 2'b10; // AL="CL-2" end end else begin case (cnt_init_mr_r) INIT_CNT_MR2: begin bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; address_w[10:9] = mr2_r[chip_cnt_r]; end INIT_CNT_MR3: begin bank_w[1:0] = 2'b11; address_w = load_mr3[ROW_WIDTH-1:0]; end INIT_CNT_MR1: begin bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; address_w[2] = mr1_r[chip_cnt_r][0]; address_w[6] = mr1_r[chip_cnt_r][1]; address_w[9] = mr1_r[chip_cnt_r][2]; end INIT_CNT_MR0: begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; // fixing it to BL8 for calibration address_w[1:0] = 2'b00; end default: begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end endcase end end else begin // DDR2 case (cnt_init_mr_r) INIT_CNT_MR2: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b10; address_w = load_mr2[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //MRS command without resetting DLL end end INIT_CNT_MR3: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b11; address_w = load_mr3[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; address_w[8]= 1'b0; //MRS command without resetting DLL. Repeted again // because there is an extra state. end end INIT_CNT_MR1: begin bank_w[1:0] = 2'b01; if(~ddr2_refresh_flag_r)begin address_w = load_mr1[ROW_WIDTH-1:0]; end else begin // second set of lm commands address_w = load_mr1[ROW_WIDTH-1:0]; address_w[9:7] = 3'b111; //OCD default state end end INIT_CNT_MR0: begin if(~ddr2_refresh_flag_r)begin bank_w[1:0] = 2'b00; address_w = load_mr0[ROW_WIDTH-1:0]; end else begin // second set of lm commands bank_w[1:0] = 2'b01; address_w = load_mr1[ROW_WIDTH-1:0]; if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin // always disable odt for rank 1 and rank 3 as per SPEC address_w[2] = 'b0; address_w[6] = 'b0; end //OCD exit end end default: begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end endcase end end else if ( ~prbs_rdlvl_done && ((init_state_r == INIT_PI_PHASELOCK_READS) || (init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin // Writing and reading PRBS pattern for read leveling stage 1 // Need to support burst length 4 or 8. PRBS pattern will be // written to entire row and read back from the same row repeatedly bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (((stg1_wr_rd_cnt == NUM_STG1_WR_RD) && ~rdlvl_stg1_done) || (stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd22) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; end else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ) )// || // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; else address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end //need to add address for complex oclkdelay calib end else if (prbs_rdlvl_done && ((init_state_r == INIT_RDLVL_STG1_WRITE) || (init_state_r == INIT_RDLVL_COMPLEX_READ))) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if ((stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd30) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; end else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (init_state_r1 != INIT_RDLVL_STG1_WRITE) ) // ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) ) address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC; else address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end end else if ((init_state_r == INIT_OCLKDELAY_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCLKDELAY_READ)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (oclk_wr_cnt == NUM_STG1_WR_RD) address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((oclk_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end else if ((init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_WRCAL_READ)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; if (wrcal_wr_cnt == NUM_STG1_WR_RD) address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}}; else if (phy_data_full_r || (!new_burst_r)) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0]; else if ((wrcal_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r) address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC; end else if ((init_state_r == INIT_WRCAL_MULT_READS) || (init_state_r == INIT_RDLVL_STG2_READ)) begin // when writing or reading back training pattern for read leveling stage2 // need to support burst length of 4 or 8. This may mean issuing // multiple commands to cover the entire range of addresses accessed // during read leveling. // Hard coding A[12] to 1 so that it will always be burst length of 8 // for DDR3. Does not have any effect on DDR2. bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}}; address_w[COL_WIDTH-1:0] = {CALIB_COL_ADD[COL_WIDTH-1:3],burst_addr_r, 3'b000}; address_w[12] = 1'b1; end else if ((init_state_r == INIT_RDLVL_ACT) || (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_WRCAL_ACT) || (init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r == INIT_OCAL_CENTER_ACT) || (init_state_r == INIT_OCLKDELAY_ACT)) begin bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0]; //if (stg1_wr_rd_cnt == 'd22) // address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0] + 1; //else address_w = prbs_rdlvl_done ? CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt_ocal : CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt; end else begin bank_w = {BANK_WIDTH{1'bx}}; address_w = {ROW_WIDTH{1'bx}}; end end // verilint STARC-2.7.3.3b on // registring before sending out generate genvar r,s; if ((DRAM_TYPE != "DDR3") || (CA_MIRROR != "ON")) begin: gen_no_mirror for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: div_clk_loop always @(posedge clk) begin phy_address[(r*ROW_WIDTH) +: ROW_WIDTH] <= #TCQ address_w; phy_bank[(r*BANK_WIDTH) +: BANK_WIDTH] <= #TCQ bank_w; end end end else begin: gen_mirror // Control/addressing mirroring (optional for DDR3 dual rank DIMMs) // Mirror for the 2nd rank only. Logic needs to be enhanced to account // for multiple slots, currently only supports one slot, 2-rank config for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_ba_div_clk_loop for (s = 0; s < BANK_WIDTH; s = s + 1) begin: gen_ba always @(posedge clk) if (chip_cnt_r == 2'b00) begin phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[s]; end else begin phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[(s == 0) ? 1 : ((s == 1) ? 0 : s)]; end end end for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_addr_div_clk_loop for (s = 0; s < ROW_WIDTH; s = s + 1) begin: gen_addr always @(posedge clk) if (chip_cnt_r == 2'b00) begin phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[s]; end else begin phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[ (s == 3) ? 4 : ((s == 4) ? 3 : ((s == 5) ? 6 : ((s == 6) ? 5 : ((s == 7) ? 8 : ((s == 8) ? 7 : s)))))]; end end end end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : bank_mach.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Top level bank machine block. A structural block instantiating the configured // individual bank machines, and a common block that computes various items shared // by all bank machines. `timescale 1ps/1ps module mig_7series_v2_3_bank_mach # ( parameter TCQ = 100, parameter EVEN_CWL_2T_MODE = "OFF", parameter ADDR_CMD_MODE = "1T", parameter BANK_WIDTH = 3, parameter BM_CNT_WIDTH = 2, parameter BURST_MODE = "8", parameter COL_WIDTH = 12, parameter CS_WIDTH = 4, parameter CL = 5, parameter CWL = 5, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter EARLY_WR_DATA_ADDR = "OFF", parameter ECC = "OFF", parameter LOW_IDLE_CNT = 1, parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, parameter nCS_PER_RANK = 1, parameter nOP_WAIT = 0, parameter nRAS = 20, parameter nRCD = 5, parameter nRFC = 44, parameter nRTP = 4, parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal parameter nRP = 10, parameter nSLOTS = 2, parameter nWR = 6, parameter nXSDLL = 512, parameter ORDERING = "NORM", parameter RANK_BM_BV_WIDTH = 16, parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter ROW_WIDTH = 16, parameter RTT_NOM = "40", parameter RTT_WR = "120", parameter STARVE_LIMIT = 2, parameter SLOT_0_CONFIG = 8'b0000_0101, parameter SLOT_1_CONFIG = 8'b0000_1010, parameter tZQCS = 64 ) (/*AUTOARG*/ // Outputs output accept, // From bank_common0 of bank_common.v output accept_ns, // From bank_common0 of bank_common.v output [BM_CNT_WIDTH-1:0] bank_mach_next, // From bank_common0 of bank_common.v output [ROW_WIDTH-1:0] col_a, // From arb_mux0 of arb_mux.v output [BANK_WIDTH-1:0] col_ba, // From arb_mux0 of arb_mux.v output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_mux0 of arb_mux.v output col_periodic_rd, // From arb_mux0 of arb_mux.v output [RANK_WIDTH-1:0] col_ra, // From arb_mux0 of arb_mux.v output col_rmw, // From arb_mux0 of arb_mux.v output col_rd_wr, output [ROW_WIDTH-1:0] col_row, // From arb_mux0 of arb_mux.v output col_size, // From arb_mux0 of arb_mux.v output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_mux0 of arb_mux.v output wire [nCK_PER_CLK-1:0] mc_ras_n, output wire [nCK_PER_CLK-1:0] mc_cas_n, output wire [nCK_PER_CLK-1:0] mc_we_n, output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, output wire [1:0] mc_odt, output wire [nCK_PER_CLK-1:0] mc_cke, output wire [3:0] mc_aux_out0, output wire [3:0] mc_aux_out1, output [2:0] mc_cmd, output [5:0] mc_data_offset, output [5:0] mc_data_offset_1, output [5:0] mc_data_offset_2, output [1:0] mc_cas_slot, output insert_maint_r1, // From arb_mux0 of arb_mux.v output maint_wip_r, // From bank_common0 of bank_common.v output wire [nBANK_MACHS-1:0] sending_row, output wire [nBANK_MACHS-1:0] sending_col, output wire sent_col, output wire sent_col_r, output periodic_rd_ack_r, output wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r, output wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r, output wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r, output wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r, output idle, // Inputs input [BANK_WIDTH-1:0] bank, // To bank0 of bank_cntrl.v input [6*RANKS-1:0] calib_rddata_offset, input [6*RANKS-1:0] calib_rddata_offset_1, input [6*RANKS-1:0] calib_rddata_offset_2, input clk, // To bank0 of bank_cntrl.v, ... input [2:0] cmd, // To bank0 of bank_cntrl.v, ... input [COL_WIDTH-1:0] col, // To bank0 of bank_cntrl.v input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,// To bank0 of bank_cntrl.v input init_calib_complete, // To bank_common0 of bank_common.v input phy_rddata_valid, // To bank0 of bank_cntrl.v input dq_busy_data, // To bank0 of bank_cntrl.v input hi_priority, // To bank0 of bank_cntrl.v, ... input [RANKS-1:0] inhbt_act_faw_r, // To bank0 of bank_cntrl.v input [RANKS-1:0] inhbt_rd, // To bank0 of bank_cntrl.v input [RANKS-1:0] inhbt_wr, // To bank0 of bank_cntrl.v input [RANK_WIDTH-1:0] maint_rank_r, // To bank0 of bank_cntrl.v, ... input maint_req_r, // To bank0 of bank_cntrl.v, ... input maint_zq_r, // To bank0 of bank_cntrl.v, ... input maint_sre_r, // To bank0 of bank_cntrl.v, ... input maint_srx_r, // To bank0 of bank_cntrl.v, ... input periodic_rd_r, // To bank_common0 of bank_common.v input [RANK_WIDTH-1:0] periodic_rd_rank_r, // To bank0 of bank_cntrl.v input phy_mc_ctl_full, input phy_mc_cmd_full, input phy_mc_data_full, input [RANK_WIDTH-1:0] rank, // To bank0 of bank_cntrl.v input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, // To bank0 of bank_cntrl.v input rd_rmw, // To bank0 of bank_cntrl.v input [ROW_WIDTH-1:0] row, // To bank0 of bank_cntrl.v input rst, // To bank0 of bank_cntrl.v, ... input size, // To bank0 of bank_cntrl.v input [7:0] slot_0_present, // To bank_common0 of bank_common.v, ... input [7:0] slot_1_present, // To bank_common0 of bank_common.v, ... input use_addr ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam RANK_VECT_INDX = (nBANK_MACHS *RANK_WIDTH) - 1; localparam BANK_VECT_INDX = (nBANK_MACHS * BANK_WIDTH) - 1; localparam ROW_VECT_INDX = (nBANK_MACHS * ROW_WIDTH) - 1; localparam DATA_BUF_ADDR_VECT_INDX = (nBANK_MACHS * DATA_BUF_ADDR_WIDTH) - 1; localparam nRAS_CLKS = (nCK_PER_CLK == 1) ? nRAS : (nCK_PER_CLK == 2) ? ((nRAS/2) + (nRAS % 2)) : ((nRAS/4) + ((nRAS%4) ? 1 : 0)); localparam nWTP = CWL + ((BURST_MODE == "4") ? 2 : 4) + nWR; // Unless 2T mode, add one to nWTP_CLKS for 2:1 mode. This accounts for loss of // one DRAM CK due to column command to row command fixed offset. In 2T mode, // Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T // mode, in which case we add 1 if the remainder exceeds the fixed offset. localparam nWTP_CLKS = (nCK_PER_CLK == 1) ? nWTP : (nCK_PER_CLK == 2) ? (nWTP/2) + ((ADDR_CMD_MODE == "2T") ? nWTP%2 : 1) : (nWTP/4) + ((ADDR_CMD_MODE == "2T") ? (nWTP%4 > 2 ? 2 : 1) : 2); localparam RAS_TIMER_WIDTH = clogb2(((nRAS_CLKS > nWTP_CLKS) ? nRAS_CLKS : nWTP_CLKS) - 1); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire accept_internal_r; // From bank_common0 of bank_common.v wire accept_req; // From bank_common0 of bank_common.v wire adv_order_q; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v wire insert_maint_r; // From bank_common0 of bank_common.v wire low_idle_cnt_r; // From bank_common0 of bank_common.v wire maint_idle; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v wire periodic_rd_insert; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v wire sent_row; // From arb_mux0 of arb_mux.v wire was_priority; // From bank_common0 of bank_common.v wire was_wr; // From bank_common0 of bank_common.v // End of automatics wire [RANK_WIDTH-1:0] rnk_config; wire rnk_config_strobe; wire rnk_config_kill_rts_col; wire rnk_config_valid_r; wire [nBANK_MACHS-1:0] rts_row; wire [nBANK_MACHS-1:0] rts_col; wire [nBANK_MACHS-1:0] rts_pre; wire [nBANK_MACHS-1:0] col_rdy_wr; wire [nBANK_MACHS-1:0] rtc; wire [nBANK_MACHS-1:0] sending_pre; wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r; wire [nBANK_MACHS-1:0] req_size_r; wire [RANK_VECT_INDX:0] req_rank_r; wire [BANK_VECT_INDX:0] req_bank_r; wire [ROW_VECT_INDX:0] req_row_r; wire [ROW_VECT_INDX:0] col_addr; wire [nBANK_MACHS-1:0] req_periodic_rd_r; wire [nBANK_MACHS-1:0] req_wr_r; wire [nBANK_MACHS-1:0] rd_wr_r; wire [nBANK_MACHS-1:0] req_ras; wire [nBANK_MACHS-1:0] req_cas; wire [ROW_VECT_INDX:0] row_addr; wire [nBANK_MACHS-1:0] row_cmd_wr; wire [nBANK_MACHS-1:0] demand_priority; wire [nBANK_MACHS-1:0] demand_act_priority; wire [nBANK_MACHS-1:0] idle_ns; wire [nBANK_MACHS-1:0] rb_hit_busy_r; wire [nBANK_MACHS-1:0] bm_end; wire [nBANK_MACHS-1:0] passing_open_bank; wire [nBANK_MACHS-1:0] ordered_r; wire [nBANK_MACHS-1:0] ordered_issued; wire [nBANK_MACHS-1:0] rb_hit_busy_ns; wire [nBANK_MACHS-1:0] maint_hit; wire [nBANK_MACHS-1:0] idle_r; wire [nBANK_MACHS-1:0] head_r; wire [nBANK_MACHS-1:0] start_rcd; wire [nBANK_MACHS-1:0] end_rtp; wire [nBANK_MACHS-1:0] op_exit_req; wire [nBANK_MACHS-1:0] op_exit_grant; wire [nBANK_MACHS-1:0] start_pre_wait; wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns; genvar ID; generate for (ID=0; ID<nBANK_MACHS; ID=ID+1) begin:bank_cntrl mig_7series_v2_3_bank_cntrl # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_WIDTH (BANK_WIDTH), .BM_CNT_WIDTH (BM_CNT_WIDTH), .BURST_MODE (BURST_MODE), .COL_WIDTH (COL_WIDTH), .CWL (CWL), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .ECC (ECC), .ID (ID), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nOP_WAIT (nOP_WAIT), .nRAS_CLKS (nRAS_CLKS), .nRCD (nRCD), .nRTP (nRTP), .nRP (nRP), .nWTP_CLKS (nWTP_CLKS), .ORDERING (ORDERING), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .RAS_TIMER_WIDTH (RAS_TIMER_WIDTH), .ROW_WIDTH (ROW_WIDTH), .STARVE_LIMIT (STARVE_LIMIT)) bank0 (.demand_priority (demand_priority[ID]), .demand_priority_in ({2{demand_priority}}), .demand_act_priority (demand_act_priority[ID]), .demand_act_priority_in ({2{demand_act_priority}}), .rts_row (rts_row[ID]), .rts_col (rts_col[ID]), .rts_pre (rts_pre[ID]), .col_rdy_wr (col_rdy_wr[ID]), .rtc (rtc[ID]), .sending_row (sending_row[ID]), .sending_pre (sending_pre[ID]), .sending_col (sending_col[ID]), .req_data_buf_addr_r (req_data_buf_addr_r[(ID*DATA_BUF_ADDR_WIDTH)+:DATA_BUF_ADDR_WIDTH]), .req_size_r (req_size_r[ID]), .req_rank_r (req_rank_r[(ID*RANK_WIDTH)+:RANK_WIDTH]), .req_bank_r (req_bank_r[(ID*BANK_WIDTH)+:BANK_WIDTH]), .req_row_r (req_row_r[(ID*ROW_WIDTH)+:ROW_WIDTH]), .col_addr (col_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]), .req_wr_r (req_wr_r[ID]), .rd_wr_r (rd_wr_r[ID]), .req_periodic_rd_r (req_periodic_rd_r[ID]), .req_ras (req_ras[ID]), .req_cas (req_cas[ID]), .row_addr (row_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]), .row_cmd_wr (row_cmd_wr[ID]), .act_this_rank_r (act_this_rank_r[(ID*RANKS)+:RANKS]), .wr_this_rank_r (wr_this_rank_r[(ID*RANKS)+:RANKS]), .rd_this_rank_r (rd_this_rank_r[(ID*RANKS)+:RANKS]), .idle_ns (idle_ns[ID]), .rb_hit_busy_r (rb_hit_busy_r[ID]), .bm_end (bm_end[ID]), .bm_end_in ({2{bm_end}}), .passing_open_bank (passing_open_bank[ID]), .passing_open_bank_in ({2{passing_open_bank}}), .ordered_r (ordered_r[ID]), .ordered_issued (ordered_issued[ID]), .rb_hit_busy_ns (rb_hit_busy_ns[ID]), .rb_hit_busy_ns_in ({2{rb_hit_busy_ns}}), .maint_hit (maint_hit[ID]), .req_rank_r_in ({2{req_rank_r}}), .idle_r (idle_r[ID]), .head_r (head_r[ID]), .start_rcd (start_rcd[ID]), .start_rcd_in ({2{start_rcd}}), .end_rtp (end_rtp[ID]), .op_exit_req (op_exit_req[ID]), .op_exit_grant (op_exit_grant[ID]), .start_pre_wait (start_pre_wait[ID]), .ras_timer_ns (ras_timer_ns[(ID*RAS_TIMER_WIDTH)+:RAS_TIMER_WIDTH]), .ras_timer_ns_in ({2{ras_timer_ns}}), .rank_busy_r (rank_busy_r[ID*RANKS+:RANKS]), /*AUTOINST*/ // Inputs .accept_internal_r (accept_internal_r), .accept_req (accept_req), .adv_order_q (adv_order_q), .bank (bank[BANK_WIDTH-1:0]), .clk (clk), .cmd (cmd[2:0]), .col (col[COL_WIDTH-1:0]), .data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .phy_rddata_valid (phy_rddata_valid), .dq_busy_data (dq_busy_data), .hi_priority (hi_priority), .idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]), .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), .inhbt_rd (inhbt_rd[RANKS-1:0]), .inhbt_wr (inhbt_wr[RANKS-1:0]), .rnk_config (rnk_config[RANK_WIDTH-1:0]), .rnk_config_strobe (rnk_config_strobe), .rnk_config_kill_rts_col (rnk_config_kill_rts_col), .rnk_config_valid_r (rnk_config_valid_r), .low_idle_cnt_r (low_idle_cnt_r), .maint_idle (maint_idle), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .order_cnt (order_cnt[BM_CNT_WIDTH-1:0]), .periodic_rd_ack_r (periodic_rd_ack_r), .periodic_rd_insert (periodic_rd_insert), .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), .phy_mc_cmd_full (phy_mc_cmd_full), .phy_mc_ctl_full (phy_mc_ctl_full), .phy_mc_data_full (phy_mc_data_full), .rank (rank[RANK_WIDTH-1:0]), .rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]), .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), .rd_rmw (rd_rmw), .row (row[ROW_WIDTH-1:0]), .rst (rst), .sent_col (sent_col), .sent_row (sent_row), .size (size), .use_addr (use_addr), .was_priority (was_priority), .was_wr (was_wr)); end endgenerate mig_7series_v2_3_bank_common # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .BM_CNT_WIDTH (BM_CNT_WIDTH), .LOW_IDLE_CNT (LOW_IDLE_CNT), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nOP_WAIT (nOP_WAIT), .nRFC (nRFC), .nXSDLL (nXSDLL), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .CWL (CWL), .tZQCS (tZQCS)) bank_common0 (.op_exit_grant (op_exit_grant[nBANK_MACHS-1:0]), /*AUTOINST*/ // Outputs .accept_internal_r (accept_internal_r), .accept_ns (accept_ns), .accept (accept), .periodic_rd_insert (periodic_rd_insert), .periodic_rd_ack_r (periodic_rd_ack_r), .accept_req (accept_req), .rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]), .idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]), .idle (idle), .order_cnt (order_cnt[BM_CNT_WIDTH-1:0]), .adv_order_q (adv_order_q), .bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]), .low_idle_cnt_r (low_idle_cnt_r), .was_wr (was_wr), .was_priority (was_priority), .maint_wip_r (maint_wip_r), .maint_idle (maint_idle), .insert_maint_r (insert_maint_r), // Inputs .clk (clk), .rst (rst), .idle_ns (idle_ns[nBANK_MACHS-1:0]), .init_calib_complete (init_calib_complete), .periodic_rd_r (periodic_rd_r), .use_addr (use_addr), .rb_hit_busy_r (rb_hit_busy_r[nBANK_MACHS-1:0]), .idle_r (idle_r[nBANK_MACHS-1:0]), .ordered_r (ordered_r[nBANK_MACHS-1:0]), .ordered_issued (ordered_issued[nBANK_MACHS-1:0]), .head_r (head_r[nBANK_MACHS-1:0]), .end_rtp (end_rtp[nBANK_MACHS-1:0]), .passing_open_bank (passing_open_bank[nBANK_MACHS-1:0]), .op_exit_req (op_exit_req[nBANK_MACHS-1:0]), .start_pre_wait (start_pre_wait[nBANK_MACHS-1:0]), .cmd (cmd[2:0]), .hi_priority (hi_priority), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .maint_hit (maint_hit[nBANK_MACHS-1:0]), .bm_end (bm_end[nBANK_MACHS-1:0]), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0])); mig_7series_v2_3_arb_mux # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_VECT_INDX (BANK_VECT_INDX), .BANK_WIDTH (BANK_WIDTH), .BURST_MODE (BURST_MODE), .CS_WIDTH (CS_WIDTH), .CL (CL), .CWL (CWL), .DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nCS_PER_RANK (nCS_PER_RANK), .nRAS (nRAS), .nRCD (nRCD), .CKE_ODT_AUX (CKE_ODT_AUX), .nSLOTS (nSLOTS), .nWR (nWR), .RANKS (RANKS), .RANK_VECT_INDX (RANK_VECT_INDX), .RANK_WIDTH (RANK_WIDTH), .ROW_VECT_INDX (ROW_VECT_INDX), .ROW_WIDTH (ROW_WIDTH), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG)) arb_mux0 (.rts_col (rts_col[nBANK_MACHS-1:0]), // AUTOs wants to make this an input. /*AUTOINST*/ // Outputs .col_a (col_a[ROW_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_row (col_row[ROW_WIDTH-1:0]), .col_size (col_size), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .mc_bank (mc_bank), .mc_address (mc_address), .mc_ras_n (mc_ras_n), .mc_cas_n (mc_cas_n), .mc_we_n (mc_we_n), .mc_cs_n (mc_cs_n), .mc_odt (mc_odt), .mc_cke (mc_cke), .mc_aux_out0 (mc_aux_out0), .mc_aux_out1 (mc_aux_out1), .mc_cmd (mc_cmd), .mc_data_offset (mc_data_offset), .mc_data_offset_1 (mc_data_offset_1), .mc_data_offset_2 (mc_data_offset_2), .rnk_config (rnk_config[RANK_WIDTH-1:0]), .rnk_config_valid_r (rnk_config_valid_r), .mc_cas_slot (mc_cas_slot), .sending_row (sending_row[nBANK_MACHS-1:0]), .sending_pre (sending_pre[nBANK_MACHS-1:0]), .sent_col (sent_col), .sent_col_r (sent_col_r), .sent_row (sent_row), .sending_col (sending_col[nBANK_MACHS-1:0]), .rnk_config_strobe (rnk_config_strobe), .rnk_config_kill_rts_col (rnk_config_kill_rts_col), .insert_maint_r1 (insert_maint_r1), // Inputs .init_calib_complete (init_calib_complete), .calib_rddata_offset (calib_rddata_offset), .calib_rddata_offset_1 (calib_rddata_offset_1), .calib_rddata_offset_2 (calib_rddata_offset_2), .col_addr (col_addr[ROW_VECT_INDX:0]), .col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]), .insert_maint_r (insert_maint_r), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]), .req_bank_r (req_bank_r[BANK_VECT_INDX:0]), .req_cas (req_cas[nBANK_MACHS-1:0]), .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]), .req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]), .req_rank_r (req_rank_r[RANK_VECT_INDX:0]), .req_ras (req_ras[nBANK_MACHS-1:0]), .req_row_r (req_row_r[ROW_VECT_INDX:0]), .req_size_r (req_size_r[nBANK_MACHS-1:0]), .req_wr_r (req_wr_r[nBANK_MACHS-1:0]), .row_addr (row_addr[ROW_VECT_INDX:0]), .row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]), .rts_row (rts_row[nBANK_MACHS-1:0]), .rtc (rtc[nBANK_MACHS-1:0]), .rts_pre (rts_pre[nBANK_MACHS-1:0]), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0]), .clk (clk), .rst (rst)); endmodule // bank_mach

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : bank_mach.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Top level bank machine block. A structural block instantiating the configured // individual bank machines, and a common block that computes various items shared // by all bank machines. `timescale 1ps/1ps module mig_7series_v2_3_bank_mach # ( parameter TCQ = 100, parameter EVEN_CWL_2T_MODE = "OFF", parameter ADDR_CMD_MODE = "1T", parameter BANK_WIDTH = 3, parameter BM_CNT_WIDTH = 2, parameter BURST_MODE = "8", parameter COL_WIDTH = 12, parameter CS_WIDTH = 4, parameter CL = 5, parameter CWL = 5, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter EARLY_WR_DATA_ADDR = "OFF", parameter ECC = "OFF", parameter LOW_IDLE_CNT = 1, parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, parameter nCS_PER_RANK = 1, parameter nOP_WAIT = 0, parameter nRAS = 20, parameter nRCD = 5, parameter nRFC = 44, parameter nRTP = 4, parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal parameter nRP = 10, parameter nSLOTS = 2, parameter nWR = 6, parameter nXSDLL = 512, parameter ORDERING = "NORM", parameter RANK_BM_BV_WIDTH = 16, parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter ROW_WIDTH = 16, parameter RTT_NOM = "40", parameter RTT_WR = "120", parameter STARVE_LIMIT = 2, parameter SLOT_0_CONFIG = 8'b0000_0101, parameter SLOT_1_CONFIG = 8'b0000_1010, parameter tZQCS = 64 ) (/*AUTOARG*/ // Outputs output accept, // From bank_common0 of bank_common.v output accept_ns, // From bank_common0 of bank_common.v output [BM_CNT_WIDTH-1:0] bank_mach_next, // From bank_common0 of bank_common.v output [ROW_WIDTH-1:0] col_a, // From arb_mux0 of arb_mux.v output [BANK_WIDTH-1:0] col_ba, // From arb_mux0 of arb_mux.v output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_mux0 of arb_mux.v output col_periodic_rd, // From arb_mux0 of arb_mux.v output [RANK_WIDTH-1:0] col_ra, // From arb_mux0 of arb_mux.v output col_rmw, // From arb_mux0 of arb_mux.v output col_rd_wr, output [ROW_WIDTH-1:0] col_row, // From arb_mux0 of arb_mux.v output col_size, // From arb_mux0 of arb_mux.v output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_mux0 of arb_mux.v output wire [nCK_PER_CLK-1:0] mc_ras_n, output wire [nCK_PER_CLK-1:0] mc_cas_n, output wire [nCK_PER_CLK-1:0] mc_we_n, output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, output wire [1:0] mc_odt, output wire [nCK_PER_CLK-1:0] mc_cke, output wire [3:0] mc_aux_out0, output wire [3:0] mc_aux_out1, output [2:0] mc_cmd, output [5:0] mc_data_offset, output [5:0] mc_data_offset_1, output [5:0] mc_data_offset_2, output [1:0] mc_cas_slot, output insert_maint_r1, // From arb_mux0 of arb_mux.v output maint_wip_r, // From bank_common0 of bank_common.v output wire [nBANK_MACHS-1:0] sending_row, output wire [nBANK_MACHS-1:0] sending_col, output wire sent_col, output wire sent_col_r, output periodic_rd_ack_r, output wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r, output wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r, output wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r, output wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r, output idle, // Inputs input [BANK_WIDTH-1:0] bank, // To bank0 of bank_cntrl.v input [6*RANKS-1:0] calib_rddata_offset, input [6*RANKS-1:0] calib_rddata_offset_1, input [6*RANKS-1:0] calib_rddata_offset_2, input clk, // To bank0 of bank_cntrl.v, ... input [2:0] cmd, // To bank0 of bank_cntrl.v, ... input [COL_WIDTH-1:0] col, // To bank0 of bank_cntrl.v input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,// To bank0 of bank_cntrl.v input init_calib_complete, // To bank_common0 of bank_common.v input phy_rddata_valid, // To bank0 of bank_cntrl.v input dq_busy_data, // To bank0 of bank_cntrl.v input hi_priority, // To bank0 of bank_cntrl.v, ... input [RANKS-1:0] inhbt_act_faw_r, // To bank0 of bank_cntrl.v input [RANKS-1:0] inhbt_rd, // To bank0 of bank_cntrl.v input [RANKS-1:0] inhbt_wr, // To bank0 of bank_cntrl.v input [RANK_WIDTH-1:0] maint_rank_r, // To bank0 of bank_cntrl.v, ... input maint_req_r, // To bank0 of bank_cntrl.v, ... input maint_zq_r, // To bank0 of bank_cntrl.v, ... input maint_sre_r, // To bank0 of bank_cntrl.v, ... input maint_srx_r, // To bank0 of bank_cntrl.v, ... input periodic_rd_r, // To bank_common0 of bank_common.v input [RANK_WIDTH-1:0] periodic_rd_rank_r, // To bank0 of bank_cntrl.v input phy_mc_ctl_full, input phy_mc_cmd_full, input phy_mc_data_full, input [RANK_WIDTH-1:0] rank, // To bank0 of bank_cntrl.v input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, // To bank0 of bank_cntrl.v input rd_rmw, // To bank0 of bank_cntrl.v input [ROW_WIDTH-1:0] row, // To bank0 of bank_cntrl.v input rst, // To bank0 of bank_cntrl.v, ... input size, // To bank0 of bank_cntrl.v input [7:0] slot_0_present, // To bank_common0 of bank_common.v, ... input [7:0] slot_1_present, // To bank_common0 of bank_common.v, ... input use_addr ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam RANK_VECT_INDX = (nBANK_MACHS *RANK_WIDTH) - 1; localparam BANK_VECT_INDX = (nBANK_MACHS * BANK_WIDTH) - 1; localparam ROW_VECT_INDX = (nBANK_MACHS * ROW_WIDTH) - 1; localparam DATA_BUF_ADDR_VECT_INDX = (nBANK_MACHS * DATA_BUF_ADDR_WIDTH) - 1; localparam nRAS_CLKS = (nCK_PER_CLK == 1) ? nRAS : (nCK_PER_CLK == 2) ? ((nRAS/2) + (nRAS % 2)) : ((nRAS/4) + ((nRAS%4) ? 1 : 0)); localparam nWTP = CWL + ((BURST_MODE == "4") ? 2 : 4) + nWR; // Unless 2T mode, add one to nWTP_CLKS for 2:1 mode. This accounts for loss of // one DRAM CK due to column command to row command fixed offset. In 2T mode, // Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T // mode, in which case we add 1 if the remainder exceeds the fixed offset. localparam nWTP_CLKS = (nCK_PER_CLK == 1) ? nWTP : (nCK_PER_CLK == 2) ? (nWTP/2) + ((ADDR_CMD_MODE == "2T") ? nWTP%2 : 1) : (nWTP/4) + ((ADDR_CMD_MODE == "2T") ? (nWTP%4 > 2 ? 2 : 1) : 2); localparam RAS_TIMER_WIDTH = clogb2(((nRAS_CLKS > nWTP_CLKS) ? nRAS_CLKS : nWTP_CLKS) - 1); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire accept_internal_r; // From bank_common0 of bank_common.v wire accept_req; // From bank_common0 of bank_common.v wire adv_order_q; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v wire insert_maint_r; // From bank_common0 of bank_common.v wire low_idle_cnt_r; // From bank_common0 of bank_common.v wire maint_idle; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v wire periodic_rd_insert; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v wire sent_row; // From arb_mux0 of arb_mux.v wire was_priority; // From bank_common0 of bank_common.v wire was_wr; // From bank_common0 of bank_common.v // End of automatics wire [RANK_WIDTH-1:0] rnk_config; wire rnk_config_strobe; wire rnk_config_kill_rts_col; wire rnk_config_valid_r; wire [nBANK_MACHS-1:0] rts_row; wire [nBANK_MACHS-1:0] rts_col; wire [nBANK_MACHS-1:0] rts_pre; wire [nBANK_MACHS-1:0] col_rdy_wr; wire [nBANK_MACHS-1:0] rtc; wire [nBANK_MACHS-1:0] sending_pre; wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r; wire [nBANK_MACHS-1:0] req_size_r; wire [RANK_VECT_INDX:0] req_rank_r; wire [BANK_VECT_INDX:0] req_bank_r; wire [ROW_VECT_INDX:0] req_row_r; wire [ROW_VECT_INDX:0] col_addr; wire [nBANK_MACHS-1:0] req_periodic_rd_r; wire [nBANK_MACHS-1:0] req_wr_r; wire [nBANK_MACHS-1:0] rd_wr_r; wire [nBANK_MACHS-1:0] req_ras; wire [nBANK_MACHS-1:0] req_cas; wire [ROW_VECT_INDX:0] row_addr; wire [nBANK_MACHS-1:0] row_cmd_wr; wire [nBANK_MACHS-1:0] demand_priority; wire [nBANK_MACHS-1:0] demand_act_priority; wire [nBANK_MACHS-1:0] idle_ns; wire [nBANK_MACHS-1:0] rb_hit_busy_r; wire [nBANK_MACHS-1:0] bm_end; wire [nBANK_MACHS-1:0] passing_open_bank; wire [nBANK_MACHS-1:0] ordered_r; wire [nBANK_MACHS-1:0] ordered_issued; wire [nBANK_MACHS-1:0] rb_hit_busy_ns; wire [nBANK_MACHS-1:0] maint_hit; wire [nBANK_MACHS-1:0] idle_r; wire [nBANK_MACHS-1:0] head_r; wire [nBANK_MACHS-1:0] start_rcd; wire [nBANK_MACHS-1:0] end_rtp; wire [nBANK_MACHS-1:0] op_exit_req; wire [nBANK_MACHS-1:0] op_exit_grant; wire [nBANK_MACHS-1:0] start_pre_wait; wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns; genvar ID; generate for (ID=0; ID<nBANK_MACHS; ID=ID+1) begin:bank_cntrl mig_7series_v2_3_bank_cntrl # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_WIDTH (BANK_WIDTH), .BM_CNT_WIDTH (BM_CNT_WIDTH), .BURST_MODE (BURST_MODE), .COL_WIDTH (COL_WIDTH), .CWL (CWL), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .ECC (ECC), .ID (ID), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nOP_WAIT (nOP_WAIT), .nRAS_CLKS (nRAS_CLKS), .nRCD (nRCD), .nRTP (nRTP), .nRP (nRP), .nWTP_CLKS (nWTP_CLKS), .ORDERING (ORDERING), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .RAS_TIMER_WIDTH (RAS_TIMER_WIDTH), .ROW_WIDTH (ROW_WIDTH), .STARVE_LIMIT (STARVE_LIMIT)) bank0 (.demand_priority (demand_priority[ID]), .demand_priority_in ({2{demand_priority}}), .demand_act_priority (demand_act_priority[ID]), .demand_act_priority_in ({2{demand_act_priority}}), .rts_row (rts_row[ID]), .rts_col (rts_col[ID]), .rts_pre (rts_pre[ID]), .col_rdy_wr (col_rdy_wr[ID]), .rtc (rtc[ID]), .sending_row (sending_row[ID]), .sending_pre (sending_pre[ID]), .sending_col (sending_col[ID]), .req_data_buf_addr_r (req_data_buf_addr_r[(ID*DATA_BUF_ADDR_WIDTH)+:DATA_BUF_ADDR_WIDTH]), .req_size_r (req_size_r[ID]), .req_rank_r (req_rank_r[(ID*RANK_WIDTH)+:RANK_WIDTH]), .req_bank_r (req_bank_r[(ID*BANK_WIDTH)+:BANK_WIDTH]), .req_row_r (req_row_r[(ID*ROW_WIDTH)+:ROW_WIDTH]), .col_addr (col_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]), .req_wr_r (req_wr_r[ID]), .rd_wr_r (rd_wr_r[ID]), .req_periodic_rd_r (req_periodic_rd_r[ID]), .req_ras (req_ras[ID]), .req_cas (req_cas[ID]), .row_addr (row_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]), .row_cmd_wr (row_cmd_wr[ID]), .act_this_rank_r (act_this_rank_r[(ID*RANKS)+:RANKS]), .wr_this_rank_r (wr_this_rank_r[(ID*RANKS)+:RANKS]), .rd_this_rank_r (rd_this_rank_r[(ID*RANKS)+:RANKS]), .idle_ns (idle_ns[ID]), .rb_hit_busy_r (rb_hit_busy_r[ID]), .bm_end (bm_end[ID]), .bm_end_in ({2{bm_end}}), .passing_open_bank (passing_open_bank[ID]), .passing_open_bank_in ({2{passing_open_bank}}), .ordered_r (ordered_r[ID]), .ordered_issued (ordered_issued[ID]), .rb_hit_busy_ns (rb_hit_busy_ns[ID]), .rb_hit_busy_ns_in ({2{rb_hit_busy_ns}}), .maint_hit (maint_hit[ID]), .req_rank_r_in ({2{req_rank_r}}), .idle_r (idle_r[ID]), .head_r (head_r[ID]), .start_rcd (start_rcd[ID]), .start_rcd_in ({2{start_rcd}}), .end_rtp (end_rtp[ID]), .op_exit_req (op_exit_req[ID]), .op_exit_grant (op_exit_grant[ID]), .start_pre_wait (start_pre_wait[ID]), .ras_timer_ns (ras_timer_ns[(ID*RAS_TIMER_WIDTH)+:RAS_TIMER_WIDTH]), .ras_timer_ns_in ({2{ras_timer_ns}}), .rank_busy_r (rank_busy_r[ID*RANKS+:RANKS]), /*AUTOINST*/ // Inputs .accept_internal_r (accept_internal_r), .accept_req (accept_req), .adv_order_q (adv_order_q), .bank (bank[BANK_WIDTH-1:0]), .clk (clk), .cmd (cmd[2:0]), .col (col[COL_WIDTH-1:0]), .data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .phy_rddata_valid (phy_rddata_valid), .dq_busy_data (dq_busy_data), .hi_priority (hi_priority), .idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]), .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), .inhbt_rd (inhbt_rd[RANKS-1:0]), .inhbt_wr (inhbt_wr[RANKS-1:0]), .rnk_config (rnk_config[RANK_WIDTH-1:0]), .rnk_config_strobe (rnk_config_strobe), .rnk_config_kill_rts_col (rnk_config_kill_rts_col), .rnk_config_valid_r (rnk_config_valid_r), .low_idle_cnt_r (low_idle_cnt_r), .maint_idle (maint_idle), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .order_cnt (order_cnt[BM_CNT_WIDTH-1:0]), .periodic_rd_ack_r (periodic_rd_ack_r), .periodic_rd_insert (periodic_rd_insert), .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), .phy_mc_cmd_full (phy_mc_cmd_full), .phy_mc_ctl_full (phy_mc_ctl_full), .phy_mc_data_full (phy_mc_data_full), .rank (rank[RANK_WIDTH-1:0]), .rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]), .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), .rd_rmw (rd_rmw), .row (row[ROW_WIDTH-1:0]), .rst (rst), .sent_col (sent_col), .sent_row (sent_row), .size (size), .use_addr (use_addr), .was_priority (was_priority), .was_wr (was_wr)); end endgenerate mig_7series_v2_3_bank_common # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .BM_CNT_WIDTH (BM_CNT_WIDTH), .LOW_IDLE_CNT (LOW_IDLE_CNT), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nOP_WAIT (nOP_WAIT), .nRFC (nRFC), .nXSDLL (nXSDLL), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .CWL (CWL), .tZQCS (tZQCS)) bank_common0 (.op_exit_grant (op_exit_grant[nBANK_MACHS-1:0]), /*AUTOINST*/ // Outputs .accept_internal_r (accept_internal_r), .accept_ns (accept_ns), .accept (accept), .periodic_rd_insert (periodic_rd_insert), .periodic_rd_ack_r (periodic_rd_ack_r), .accept_req (accept_req), .rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]), .idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]), .idle (idle), .order_cnt (order_cnt[BM_CNT_WIDTH-1:0]), .adv_order_q (adv_order_q), .bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]), .low_idle_cnt_r (low_idle_cnt_r), .was_wr (was_wr), .was_priority (was_priority), .maint_wip_r (maint_wip_r), .maint_idle (maint_idle), .insert_maint_r (insert_maint_r), // Inputs .clk (clk), .rst (rst), .idle_ns (idle_ns[nBANK_MACHS-1:0]), .init_calib_complete (init_calib_complete), .periodic_rd_r (periodic_rd_r), .use_addr (use_addr), .rb_hit_busy_r (rb_hit_busy_r[nBANK_MACHS-1:0]), .idle_r (idle_r[nBANK_MACHS-1:0]), .ordered_r (ordered_r[nBANK_MACHS-1:0]), .ordered_issued (ordered_issued[nBANK_MACHS-1:0]), .head_r (head_r[nBANK_MACHS-1:0]), .end_rtp (end_rtp[nBANK_MACHS-1:0]), .passing_open_bank (passing_open_bank[nBANK_MACHS-1:0]), .op_exit_req (op_exit_req[nBANK_MACHS-1:0]), .start_pre_wait (start_pre_wait[nBANK_MACHS-1:0]), .cmd (cmd[2:0]), .hi_priority (hi_priority), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .maint_hit (maint_hit[nBANK_MACHS-1:0]), .bm_end (bm_end[nBANK_MACHS-1:0]), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0])); mig_7series_v2_3_arb_mux # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_VECT_INDX (BANK_VECT_INDX), .BANK_WIDTH (BANK_WIDTH), .BURST_MODE (BURST_MODE), .CS_WIDTH (CS_WIDTH), .CL (CL), .CWL (CWL), .DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nCS_PER_RANK (nCS_PER_RANK), .nRAS (nRAS), .nRCD (nRCD), .CKE_ODT_AUX (CKE_ODT_AUX), .nSLOTS (nSLOTS), .nWR (nWR), .RANKS (RANKS), .RANK_VECT_INDX (RANK_VECT_INDX), .RANK_WIDTH (RANK_WIDTH), .ROW_VECT_INDX (ROW_VECT_INDX), .ROW_WIDTH (ROW_WIDTH), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG)) arb_mux0 (.rts_col (rts_col[nBANK_MACHS-1:0]), // AUTOs wants to make this an input. /*AUTOINST*/ // Outputs .col_a (col_a[ROW_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_row (col_row[ROW_WIDTH-1:0]), .col_size (col_size), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .mc_bank (mc_bank), .mc_address (mc_address), .mc_ras_n (mc_ras_n), .mc_cas_n (mc_cas_n), .mc_we_n (mc_we_n), .mc_cs_n (mc_cs_n), .mc_odt (mc_odt), .mc_cke (mc_cke), .mc_aux_out0 (mc_aux_out0), .mc_aux_out1 (mc_aux_out1), .mc_cmd (mc_cmd), .mc_data_offset (mc_data_offset), .mc_data_offset_1 (mc_data_offset_1), .mc_data_offset_2 (mc_data_offset_2), .rnk_config (rnk_config[RANK_WIDTH-1:0]), .rnk_config_valid_r (rnk_config_valid_r), .mc_cas_slot (mc_cas_slot), .sending_row (sending_row[nBANK_MACHS-1:0]), .sending_pre (sending_pre[nBANK_MACHS-1:0]), .sent_col (sent_col), .sent_col_r (sent_col_r), .sent_row (sent_row), .sending_col (sending_col[nBANK_MACHS-1:0]), .rnk_config_strobe (rnk_config_strobe), .rnk_config_kill_rts_col (rnk_config_kill_rts_col), .insert_maint_r1 (insert_maint_r1), // Inputs .init_calib_complete (init_calib_complete), .calib_rddata_offset (calib_rddata_offset), .calib_rddata_offset_1 (calib_rddata_offset_1), .calib_rddata_offset_2 (calib_rddata_offset_2), .col_addr (col_addr[ROW_VECT_INDX:0]), .col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]), .insert_maint_r (insert_maint_r), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]), .req_bank_r (req_bank_r[BANK_VECT_INDX:0]), .req_cas (req_cas[nBANK_MACHS-1:0]), .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]), .req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]), .req_rank_r (req_rank_r[RANK_VECT_INDX:0]), .req_ras (req_ras[nBANK_MACHS-1:0]), .req_row_r (req_row_r[ROW_VECT_INDX:0]), .req_size_r (req_size_r[nBANK_MACHS-1:0]), .req_wr_r (req_wr_r[nBANK_MACHS-1:0]), .row_addr (row_addr[ROW_VECT_INDX:0]), .row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]), .rts_row (rts_row[nBANK_MACHS-1:0]), .rtc (rtc[nBANK_MACHS-1:0]), .rts_pre (rts_pre[nBANK_MACHS-1:0]), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0]), .clk (clk), .rst (rst)); endmodule // bank_mach

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : bank_mach.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Top level bank machine block. A structural block instantiating the configured // individual bank machines, and a common block that computes various items shared // by all bank machines. `timescale 1ps/1ps module mig_7series_v2_3_bank_mach # ( parameter TCQ = 100, parameter EVEN_CWL_2T_MODE = "OFF", parameter ADDR_CMD_MODE = "1T", parameter BANK_WIDTH = 3, parameter BM_CNT_WIDTH = 2, parameter BURST_MODE = "8", parameter COL_WIDTH = 12, parameter CS_WIDTH = 4, parameter CL = 5, parameter CWL = 5, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter EARLY_WR_DATA_ADDR = "OFF", parameter ECC = "OFF", parameter LOW_IDLE_CNT = 1, parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, parameter nCS_PER_RANK = 1, parameter nOP_WAIT = 0, parameter nRAS = 20, parameter nRCD = 5, parameter nRFC = 44, parameter nRTP = 4, parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal parameter nRP = 10, parameter nSLOTS = 2, parameter nWR = 6, parameter nXSDLL = 512, parameter ORDERING = "NORM", parameter RANK_BM_BV_WIDTH = 16, parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter ROW_WIDTH = 16, parameter RTT_NOM = "40", parameter RTT_WR = "120", parameter STARVE_LIMIT = 2, parameter SLOT_0_CONFIG = 8'b0000_0101, parameter SLOT_1_CONFIG = 8'b0000_1010, parameter tZQCS = 64 ) (/*AUTOARG*/ // Outputs output accept, // From bank_common0 of bank_common.v output accept_ns, // From bank_common0 of bank_common.v output [BM_CNT_WIDTH-1:0] bank_mach_next, // From bank_common0 of bank_common.v output [ROW_WIDTH-1:0] col_a, // From arb_mux0 of arb_mux.v output [BANK_WIDTH-1:0] col_ba, // From arb_mux0 of arb_mux.v output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_mux0 of arb_mux.v output col_periodic_rd, // From arb_mux0 of arb_mux.v output [RANK_WIDTH-1:0] col_ra, // From arb_mux0 of arb_mux.v output col_rmw, // From arb_mux0 of arb_mux.v output col_rd_wr, output [ROW_WIDTH-1:0] col_row, // From arb_mux0 of arb_mux.v output col_size, // From arb_mux0 of arb_mux.v output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_mux0 of arb_mux.v output wire [nCK_PER_CLK-1:0] mc_ras_n, output wire [nCK_PER_CLK-1:0] mc_cas_n, output wire [nCK_PER_CLK-1:0] mc_we_n, output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, output wire [1:0] mc_odt, output wire [nCK_PER_CLK-1:0] mc_cke, output wire [3:0] mc_aux_out0, output wire [3:0] mc_aux_out1, output [2:0] mc_cmd, output [5:0] mc_data_offset, output [5:0] mc_data_offset_1, output [5:0] mc_data_offset_2, output [1:0] mc_cas_slot, output insert_maint_r1, // From arb_mux0 of arb_mux.v output maint_wip_r, // From bank_common0 of bank_common.v output wire [nBANK_MACHS-1:0] sending_row, output wire [nBANK_MACHS-1:0] sending_col, output wire sent_col, output wire sent_col_r, output periodic_rd_ack_r, output wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r, output wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r, output wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r, output wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r, output idle, // Inputs input [BANK_WIDTH-1:0] bank, // To bank0 of bank_cntrl.v input [6*RANKS-1:0] calib_rddata_offset, input [6*RANKS-1:0] calib_rddata_offset_1, input [6*RANKS-1:0] calib_rddata_offset_2, input clk, // To bank0 of bank_cntrl.v, ... input [2:0] cmd, // To bank0 of bank_cntrl.v, ... input [COL_WIDTH-1:0] col, // To bank0 of bank_cntrl.v input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,// To bank0 of bank_cntrl.v input init_calib_complete, // To bank_common0 of bank_common.v input phy_rddata_valid, // To bank0 of bank_cntrl.v input dq_busy_data, // To bank0 of bank_cntrl.v input hi_priority, // To bank0 of bank_cntrl.v, ... input [RANKS-1:0] inhbt_act_faw_r, // To bank0 of bank_cntrl.v input [RANKS-1:0] inhbt_rd, // To bank0 of bank_cntrl.v input [RANKS-1:0] inhbt_wr, // To bank0 of bank_cntrl.v input [RANK_WIDTH-1:0] maint_rank_r, // To bank0 of bank_cntrl.v, ... input maint_req_r, // To bank0 of bank_cntrl.v, ... input maint_zq_r, // To bank0 of bank_cntrl.v, ... input maint_sre_r, // To bank0 of bank_cntrl.v, ... input maint_srx_r, // To bank0 of bank_cntrl.v, ... input periodic_rd_r, // To bank_common0 of bank_common.v input [RANK_WIDTH-1:0] periodic_rd_rank_r, // To bank0 of bank_cntrl.v input phy_mc_ctl_full, input phy_mc_cmd_full, input phy_mc_data_full, input [RANK_WIDTH-1:0] rank, // To bank0 of bank_cntrl.v input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, // To bank0 of bank_cntrl.v input rd_rmw, // To bank0 of bank_cntrl.v input [ROW_WIDTH-1:0] row, // To bank0 of bank_cntrl.v input rst, // To bank0 of bank_cntrl.v, ... input size, // To bank0 of bank_cntrl.v input [7:0] slot_0_present, // To bank_common0 of bank_common.v, ... input [7:0] slot_1_present, // To bank_common0 of bank_common.v, ... input use_addr ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam RANK_VECT_INDX = (nBANK_MACHS *RANK_WIDTH) - 1; localparam BANK_VECT_INDX = (nBANK_MACHS * BANK_WIDTH) - 1; localparam ROW_VECT_INDX = (nBANK_MACHS * ROW_WIDTH) - 1; localparam DATA_BUF_ADDR_VECT_INDX = (nBANK_MACHS * DATA_BUF_ADDR_WIDTH) - 1; localparam nRAS_CLKS = (nCK_PER_CLK == 1) ? nRAS : (nCK_PER_CLK == 2) ? ((nRAS/2) + (nRAS % 2)) : ((nRAS/4) + ((nRAS%4) ? 1 : 0)); localparam nWTP = CWL + ((BURST_MODE == "4") ? 2 : 4) + nWR; // Unless 2T mode, add one to nWTP_CLKS for 2:1 mode. This accounts for loss of // one DRAM CK due to column command to row command fixed offset. In 2T mode, // Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T // mode, in which case we add 1 if the remainder exceeds the fixed offset. localparam nWTP_CLKS = (nCK_PER_CLK == 1) ? nWTP : (nCK_PER_CLK == 2) ? (nWTP/2) + ((ADDR_CMD_MODE == "2T") ? nWTP%2 : 1) : (nWTP/4) + ((ADDR_CMD_MODE == "2T") ? (nWTP%4 > 2 ? 2 : 1) : 2); localparam RAS_TIMER_WIDTH = clogb2(((nRAS_CLKS > nWTP_CLKS) ? nRAS_CLKS : nWTP_CLKS) - 1); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire accept_internal_r; // From bank_common0 of bank_common.v wire accept_req; // From bank_common0 of bank_common.v wire adv_order_q; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v wire insert_maint_r; // From bank_common0 of bank_common.v wire low_idle_cnt_r; // From bank_common0 of bank_common.v wire maint_idle; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v wire periodic_rd_insert; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v wire sent_row; // From arb_mux0 of arb_mux.v wire was_priority; // From bank_common0 of bank_common.v wire was_wr; // From bank_common0 of bank_common.v // End of automatics wire [RANK_WIDTH-1:0] rnk_config; wire rnk_config_strobe; wire rnk_config_kill_rts_col; wire rnk_config_valid_r; wire [nBANK_MACHS-1:0] rts_row; wire [nBANK_MACHS-1:0] rts_col; wire [nBANK_MACHS-1:0] rts_pre; wire [nBANK_MACHS-1:0] col_rdy_wr; wire [nBANK_MACHS-1:0] rtc; wire [nBANK_MACHS-1:0] sending_pre; wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r; wire [nBANK_MACHS-1:0] req_size_r; wire [RANK_VECT_INDX:0] req_rank_r; wire [BANK_VECT_INDX:0] req_bank_r; wire [ROW_VECT_INDX:0] req_row_r; wire [ROW_VECT_INDX:0] col_addr; wire [nBANK_MACHS-1:0] req_periodic_rd_r; wire [nBANK_MACHS-1:0] req_wr_r; wire [nBANK_MACHS-1:0] rd_wr_r; wire [nBANK_MACHS-1:0] req_ras; wire [nBANK_MACHS-1:0] req_cas; wire [ROW_VECT_INDX:0] row_addr; wire [nBANK_MACHS-1:0] row_cmd_wr; wire [nBANK_MACHS-1:0] demand_priority; wire [nBANK_MACHS-1:0] demand_act_priority; wire [nBANK_MACHS-1:0] idle_ns; wire [nBANK_MACHS-1:0] rb_hit_busy_r; wire [nBANK_MACHS-1:0] bm_end; wire [nBANK_MACHS-1:0] passing_open_bank; wire [nBANK_MACHS-1:0] ordered_r; wire [nBANK_MACHS-1:0] ordered_issued; wire [nBANK_MACHS-1:0] rb_hit_busy_ns; wire [nBANK_MACHS-1:0] maint_hit; wire [nBANK_MACHS-1:0] idle_r; wire [nBANK_MACHS-1:0] head_r; wire [nBANK_MACHS-1:0] start_rcd; wire [nBANK_MACHS-1:0] end_rtp; wire [nBANK_MACHS-1:0] op_exit_req; wire [nBANK_MACHS-1:0] op_exit_grant; wire [nBANK_MACHS-1:0] start_pre_wait; wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns; genvar ID; generate for (ID=0; ID<nBANK_MACHS; ID=ID+1) begin:bank_cntrl mig_7series_v2_3_bank_cntrl # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_WIDTH (BANK_WIDTH), .BM_CNT_WIDTH (BM_CNT_WIDTH), .BURST_MODE (BURST_MODE), .COL_WIDTH (COL_WIDTH), .CWL (CWL), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .ECC (ECC), .ID (ID), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nOP_WAIT (nOP_WAIT), .nRAS_CLKS (nRAS_CLKS), .nRCD (nRCD), .nRTP (nRTP), .nRP (nRP), .nWTP_CLKS (nWTP_CLKS), .ORDERING (ORDERING), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .RAS_TIMER_WIDTH (RAS_TIMER_WIDTH), .ROW_WIDTH (ROW_WIDTH), .STARVE_LIMIT (STARVE_LIMIT)) bank0 (.demand_priority (demand_priority[ID]), .demand_priority_in ({2{demand_priority}}), .demand_act_priority (demand_act_priority[ID]), .demand_act_priority_in ({2{demand_act_priority}}), .rts_row (rts_row[ID]), .rts_col (rts_col[ID]), .rts_pre (rts_pre[ID]), .col_rdy_wr (col_rdy_wr[ID]), .rtc (rtc[ID]), .sending_row (sending_row[ID]), .sending_pre (sending_pre[ID]), .sending_col (sending_col[ID]), .req_data_buf_addr_r (req_data_buf_addr_r[(ID*DATA_BUF_ADDR_WIDTH)+:DATA_BUF_ADDR_WIDTH]), .req_size_r (req_size_r[ID]), .req_rank_r (req_rank_r[(ID*RANK_WIDTH)+:RANK_WIDTH]), .req_bank_r (req_bank_r[(ID*BANK_WIDTH)+:BANK_WIDTH]), .req_row_r (req_row_r[(ID*ROW_WIDTH)+:ROW_WIDTH]), .col_addr (col_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]), .req_wr_r (req_wr_r[ID]), .rd_wr_r (rd_wr_r[ID]), .req_periodic_rd_r (req_periodic_rd_r[ID]), .req_ras (req_ras[ID]), .req_cas (req_cas[ID]), .row_addr (row_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]), .row_cmd_wr (row_cmd_wr[ID]), .act_this_rank_r (act_this_rank_r[(ID*RANKS)+:RANKS]), .wr_this_rank_r (wr_this_rank_r[(ID*RANKS)+:RANKS]), .rd_this_rank_r (rd_this_rank_r[(ID*RANKS)+:RANKS]), .idle_ns (idle_ns[ID]), .rb_hit_busy_r (rb_hit_busy_r[ID]), .bm_end (bm_end[ID]), .bm_end_in ({2{bm_end}}), .passing_open_bank (passing_open_bank[ID]), .passing_open_bank_in ({2{passing_open_bank}}), .ordered_r (ordered_r[ID]), .ordered_issued (ordered_issued[ID]), .rb_hit_busy_ns (rb_hit_busy_ns[ID]), .rb_hit_busy_ns_in ({2{rb_hit_busy_ns}}), .maint_hit (maint_hit[ID]), .req_rank_r_in ({2{req_rank_r}}), .idle_r (idle_r[ID]), .head_r (head_r[ID]), .start_rcd (start_rcd[ID]), .start_rcd_in ({2{start_rcd}}), .end_rtp (end_rtp[ID]), .op_exit_req (op_exit_req[ID]), .op_exit_grant (op_exit_grant[ID]), .start_pre_wait (start_pre_wait[ID]), .ras_timer_ns (ras_timer_ns[(ID*RAS_TIMER_WIDTH)+:RAS_TIMER_WIDTH]), .ras_timer_ns_in ({2{ras_timer_ns}}), .rank_busy_r (rank_busy_r[ID*RANKS+:RANKS]), /*AUTOINST*/ // Inputs .accept_internal_r (accept_internal_r), .accept_req (accept_req), .adv_order_q (adv_order_q), .bank (bank[BANK_WIDTH-1:0]), .clk (clk), .cmd (cmd[2:0]), .col (col[COL_WIDTH-1:0]), .data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .phy_rddata_valid (phy_rddata_valid), .dq_busy_data (dq_busy_data), .hi_priority (hi_priority), .idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]), .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), .inhbt_rd (inhbt_rd[RANKS-1:0]), .inhbt_wr (inhbt_wr[RANKS-1:0]), .rnk_config (rnk_config[RANK_WIDTH-1:0]), .rnk_config_strobe (rnk_config_strobe), .rnk_config_kill_rts_col (rnk_config_kill_rts_col), .rnk_config_valid_r (rnk_config_valid_r), .low_idle_cnt_r (low_idle_cnt_r), .maint_idle (maint_idle), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .order_cnt (order_cnt[BM_CNT_WIDTH-1:0]), .periodic_rd_ack_r (periodic_rd_ack_r), .periodic_rd_insert (periodic_rd_insert), .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), .phy_mc_cmd_full (phy_mc_cmd_full), .phy_mc_ctl_full (phy_mc_ctl_full), .phy_mc_data_full (phy_mc_data_full), .rank (rank[RANK_WIDTH-1:0]), .rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]), .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), .rd_rmw (rd_rmw), .row (row[ROW_WIDTH-1:0]), .rst (rst), .sent_col (sent_col), .sent_row (sent_row), .size (size), .use_addr (use_addr), .was_priority (was_priority), .was_wr (was_wr)); end endgenerate mig_7series_v2_3_bank_common # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .BM_CNT_WIDTH (BM_CNT_WIDTH), .LOW_IDLE_CNT (LOW_IDLE_CNT), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nOP_WAIT (nOP_WAIT), .nRFC (nRFC), .nXSDLL (nXSDLL), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .CWL (CWL), .tZQCS (tZQCS)) bank_common0 (.op_exit_grant (op_exit_grant[nBANK_MACHS-1:0]), /*AUTOINST*/ // Outputs .accept_internal_r (accept_internal_r), .accept_ns (accept_ns), .accept (accept), .periodic_rd_insert (periodic_rd_insert), .periodic_rd_ack_r (periodic_rd_ack_r), .accept_req (accept_req), .rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]), .idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]), .idle (idle), .order_cnt (order_cnt[BM_CNT_WIDTH-1:0]), .adv_order_q (adv_order_q), .bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]), .low_idle_cnt_r (low_idle_cnt_r), .was_wr (was_wr), .was_priority (was_priority), .maint_wip_r (maint_wip_r), .maint_idle (maint_idle), .insert_maint_r (insert_maint_r), // Inputs .clk (clk), .rst (rst), .idle_ns (idle_ns[nBANK_MACHS-1:0]), .init_calib_complete (init_calib_complete), .periodic_rd_r (periodic_rd_r), .use_addr (use_addr), .rb_hit_busy_r (rb_hit_busy_r[nBANK_MACHS-1:0]), .idle_r (idle_r[nBANK_MACHS-1:0]), .ordered_r (ordered_r[nBANK_MACHS-1:0]), .ordered_issued (ordered_issued[nBANK_MACHS-1:0]), .head_r (head_r[nBANK_MACHS-1:0]), .end_rtp (end_rtp[nBANK_MACHS-1:0]), .passing_open_bank (passing_open_bank[nBANK_MACHS-1:0]), .op_exit_req (op_exit_req[nBANK_MACHS-1:0]), .start_pre_wait (start_pre_wait[nBANK_MACHS-1:0]), .cmd (cmd[2:0]), .hi_priority (hi_priority), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .maint_hit (maint_hit[nBANK_MACHS-1:0]), .bm_end (bm_end[nBANK_MACHS-1:0]), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0])); mig_7series_v2_3_arb_mux # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_VECT_INDX (BANK_VECT_INDX), .BANK_WIDTH (BANK_WIDTH), .BURST_MODE (BURST_MODE), .CS_WIDTH (CS_WIDTH), .CL (CL), .CWL (CWL), .DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nCS_PER_RANK (nCS_PER_RANK), .nRAS (nRAS), .nRCD (nRCD), .CKE_ODT_AUX (CKE_ODT_AUX), .nSLOTS (nSLOTS), .nWR (nWR), .RANKS (RANKS), .RANK_VECT_INDX (RANK_VECT_INDX), .RANK_WIDTH (RANK_WIDTH), .ROW_VECT_INDX (ROW_VECT_INDX), .ROW_WIDTH (ROW_WIDTH), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG)) arb_mux0 (.rts_col (rts_col[nBANK_MACHS-1:0]), // AUTOs wants to make this an input. /*AUTOINST*/ // Outputs .col_a (col_a[ROW_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_row (col_row[ROW_WIDTH-1:0]), .col_size (col_size), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .mc_bank (mc_bank), .mc_address (mc_address), .mc_ras_n (mc_ras_n), .mc_cas_n (mc_cas_n), .mc_we_n (mc_we_n), .mc_cs_n (mc_cs_n), .mc_odt (mc_odt), .mc_cke (mc_cke), .mc_aux_out0 (mc_aux_out0), .mc_aux_out1 (mc_aux_out1), .mc_cmd (mc_cmd), .mc_data_offset (mc_data_offset), .mc_data_offset_1 (mc_data_offset_1), .mc_data_offset_2 (mc_data_offset_2), .rnk_config (rnk_config[RANK_WIDTH-1:0]), .rnk_config_valid_r (rnk_config_valid_r), .mc_cas_slot (mc_cas_slot), .sending_row (sending_row[nBANK_MACHS-1:0]), .sending_pre (sending_pre[nBANK_MACHS-1:0]), .sent_col (sent_col), .sent_col_r (sent_col_r), .sent_row (sent_row), .sending_col (sending_col[nBANK_MACHS-1:0]), .rnk_config_strobe (rnk_config_strobe), .rnk_config_kill_rts_col (rnk_config_kill_rts_col), .insert_maint_r1 (insert_maint_r1), // Inputs .init_calib_complete (init_calib_complete), .calib_rddata_offset (calib_rddata_offset), .calib_rddata_offset_1 (calib_rddata_offset_1), .calib_rddata_offset_2 (calib_rddata_offset_2), .col_addr (col_addr[ROW_VECT_INDX:0]), .col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]), .insert_maint_r (insert_maint_r), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]), .req_bank_r (req_bank_r[BANK_VECT_INDX:0]), .req_cas (req_cas[nBANK_MACHS-1:0]), .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]), .req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]), .req_rank_r (req_rank_r[RANK_VECT_INDX:0]), .req_ras (req_ras[nBANK_MACHS-1:0]), .req_row_r (req_row_r[ROW_VECT_INDX:0]), .req_size_r (req_size_r[nBANK_MACHS-1:0]), .req_wr_r (req_wr_r[nBANK_MACHS-1:0]), .row_addr (row_addr[ROW_VECT_INDX:0]), .row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]), .rts_row (rts_row[nBANK_MACHS-1:0]), .rtc (rtc[nBANK_MACHS-1:0]), .rts_pre (rts_pre[nBANK_MACHS-1:0]), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0]), .clk (clk), .rst (rst)); endmodule // bank_mach

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : bank_mach.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Top level bank machine block. A structural block instantiating the configured // individual bank machines, and a common block that computes various items shared // by all bank machines. `timescale 1ps/1ps module mig_7series_v2_3_bank_mach # ( parameter TCQ = 100, parameter EVEN_CWL_2T_MODE = "OFF", parameter ADDR_CMD_MODE = "1T", parameter BANK_WIDTH = 3, parameter BM_CNT_WIDTH = 2, parameter BURST_MODE = "8", parameter COL_WIDTH = 12, parameter CS_WIDTH = 4, parameter CL = 5, parameter CWL = 5, parameter DATA_BUF_ADDR_WIDTH = 8, parameter DRAM_TYPE = "DDR3", parameter EARLY_WR_DATA_ADDR = "OFF", parameter ECC = "OFF", parameter LOW_IDLE_CNT = 1, parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, parameter nCS_PER_RANK = 1, parameter nOP_WAIT = 0, parameter nRAS = 20, parameter nRCD = 5, parameter nRFC = 44, parameter nRTP = 4, parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal parameter nRP = 10, parameter nSLOTS = 2, parameter nWR = 6, parameter nXSDLL = 512, parameter ORDERING = "NORM", parameter RANK_BM_BV_WIDTH = 16, parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter ROW_WIDTH = 16, parameter RTT_NOM = "40", parameter RTT_WR = "120", parameter STARVE_LIMIT = 2, parameter SLOT_0_CONFIG = 8'b0000_0101, parameter SLOT_1_CONFIG = 8'b0000_1010, parameter tZQCS = 64 ) (/*AUTOARG*/ // Outputs output accept, // From bank_common0 of bank_common.v output accept_ns, // From bank_common0 of bank_common.v output [BM_CNT_WIDTH-1:0] bank_mach_next, // From bank_common0 of bank_common.v output [ROW_WIDTH-1:0] col_a, // From arb_mux0 of arb_mux.v output [BANK_WIDTH-1:0] col_ba, // From arb_mux0 of arb_mux.v output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_mux0 of arb_mux.v output col_periodic_rd, // From arb_mux0 of arb_mux.v output [RANK_WIDTH-1:0] col_ra, // From arb_mux0 of arb_mux.v output col_rmw, // From arb_mux0 of arb_mux.v output col_rd_wr, output [ROW_WIDTH-1:0] col_row, // From arb_mux0 of arb_mux.v output col_size, // From arb_mux0 of arb_mux.v output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_mux0 of arb_mux.v output wire [nCK_PER_CLK-1:0] mc_ras_n, output wire [nCK_PER_CLK-1:0] mc_cas_n, output wire [nCK_PER_CLK-1:0] mc_we_n, output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address, output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank, output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n, output wire [1:0] mc_odt, output wire [nCK_PER_CLK-1:0] mc_cke, output wire [3:0] mc_aux_out0, output wire [3:0] mc_aux_out1, output [2:0] mc_cmd, output [5:0] mc_data_offset, output [5:0] mc_data_offset_1, output [5:0] mc_data_offset_2, output [1:0] mc_cas_slot, output insert_maint_r1, // From arb_mux0 of arb_mux.v output maint_wip_r, // From bank_common0 of bank_common.v output wire [nBANK_MACHS-1:0] sending_row, output wire [nBANK_MACHS-1:0] sending_col, output wire sent_col, output wire sent_col_r, output periodic_rd_ack_r, output wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r, output wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r, output wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r, output wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r, output idle, // Inputs input [BANK_WIDTH-1:0] bank, // To bank0 of bank_cntrl.v input [6*RANKS-1:0] calib_rddata_offset, input [6*RANKS-1:0] calib_rddata_offset_1, input [6*RANKS-1:0] calib_rddata_offset_2, input clk, // To bank0 of bank_cntrl.v, ... input [2:0] cmd, // To bank0 of bank_cntrl.v, ... input [COL_WIDTH-1:0] col, // To bank0 of bank_cntrl.v input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,// To bank0 of bank_cntrl.v input init_calib_complete, // To bank_common0 of bank_common.v input phy_rddata_valid, // To bank0 of bank_cntrl.v input dq_busy_data, // To bank0 of bank_cntrl.v input hi_priority, // To bank0 of bank_cntrl.v, ... input [RANKS-1:0] inhbt_act_faw_r, // To bank0 of bank_cntrl.v input [RANKS-1:0] inhbt_rd, // To bank0 of bank_cntrl.v input [RANKS-1:0] inhbt_wr, // To bank0 of bank_cntrl.v input [RANK_WIDTH-1:0] maint_rank_r, // To bank0 of bank_cntrl.v, ... input maint_req_r, // To bank0 of bank_cntrl.v, ... input maint_zq_r, // To bank0 of bank_cntrl.v, ... input maint_sre_r, // To bank0 of bank_cntrl.v, ... input maint_srx_r, // To bank0 of bank_cntrl.v, ... input periodic_rd_r, // To bank_common0 of bank_common.v input [RANK_WIDTH-1:0] periodic_rd_rank_r, // To bank0 of bank_cntrl.v input phy_mc_ctl_full, input phy_mc_cmd_full, input phy_mc_data_full, input [RANK_WIDTH-1:0] rank, // To bank0 of bank_cntrl.v input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, // To bank0 of bank_cntrl.v input rd_rmw, // To bank0 of bank_cntrl.v input [ROW_WIDTH-1:0] row, // To bank0 of bank_cntrl.v input rst, // To bank0 of bank_cntrl.v, ... input size, // To bank0 of bank_cntrl.v input [7:0] slot_0_present, // To bank_common0 of bank_common.v, ... input [7:0] slot_1_present, // To bank_common0 of bank_common.v, ... input use_addr ); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 localparam RANK_VECT_INDX = (nBANK_MACHS *RANK_WIDTH) - 1; localparam BANK_VECT_INDX = (nBANK_MACHS * BANK_WIDTH) - 1; localparam ROW_VECT_INDX = (nBANK_MACHS * ROW_WIDTH) - 1; localparam DATA_BUF_ADDR_VECT_INDX = (nBANK_MACHS * DATA_BUF_ADDR_WIDTH) - 1; localparam nRAS_CLKS = (nCK_PER_CLK == 1) ? nRAS : (nCK_PER_CLK == 2) ? ((nRAS/2) + (nRAS % 2)) : ((nRAS/4) + ((nRAS%4) ? 1 : 0)); localparam nWTP = CWL + ((BURST_MODE == "4") ? 2 : 4) + nWR; // Unless 2T mode, add one to nWTP_CLKS for 2:1 mode. This accounts for loss of // one DRAM CK due to column command to row command fixed offset. In 2T mode, // Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T // mode, in which case we add 1 if the remainder exceeds the fixed offset. localparam nWTP_CLKS = (nCK_PER_CLK == 1) ? nWTP : (nCK_PER_CLK == 2) ? (nWTP/2) + ((ADDR_CMD_MODE == "2T") ? nWTP%2 : 1) : (nWTP/4) + ((ADDR_CMD_MODE == "2T") ? (nWTP%4 > 2 ? 2 : 1) : 2); localparam RAS_TIMER_WIDTH = clogb2(((nRAS_CLKS > nWTP_CLKS) ? nRAS_CLKS : nWTP_CLKS) - 1); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire accept_internal_r; // From bank_common0 of bank_common.v wire accept_req; // From bank_common0 of bank_common.v wire adv_order_q; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v wire insert_maint_r; // From bank_common0 of bank_common.v wire low_idle_cnt_r; // From bank_common0 of bank_common.v wire maint_idle; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v wire periodic_rd_insert; // From bank_common0 of bank_common.v wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v wire sent_row; // From arb_mux0 of arb_mux.v wire was_priority; // From bank_common0 of bank_common.v wire was_wr; // From bank_common0 of bank_common.v // End of automatics wire [RANK_WIDTH-1:0] rnk_config; wire rnk_config_strobe; wire rnk_config_kill_rts_col; wire rnk_config_valid_r; wire [nBANK_MACHS-1:0] rts_row; wire [nBANK_MACHS-1:0] rts_col; wire [nBANK_MACHS-1:0] rts_pre; wire [nBANK_MACHS-1:0] col_rdy_wr; wire [nBANK_MACHS-1:0] rtc; wire [nBANK_MACHS-1:0] sending_pre; wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r; wire [nBANK_MACHS-1:0] req_size_r; wire [RANK_VECT_INDX:0] req_rank_r; wire [BANK_VECT_INDX:0] req_bank_r; wire [ROW_VECT_INDX:0] req_row_r; wire [ROW_VECT_INDX:0] col_addr; wire [nBANK_MACHS-1:0] req_periodic_rd_r; wire [nBANK_MACHS-1:0] req_wr_r; wire [nBANK_MACHS-1:0] rd_wr_r; wire [nBANK_MACHS-1:0] req_ras; wire [nBANK_MACHS-1:0] req_cas; wire [ROW_VECT_INDX:0] row_addr; wire [nBANK_MACHS-1:0] row_cmd_wr; wire [nBANK_MACHS-1:0] demand_priority; wire [nBANK_MACHS-1:0] demand_act_priority; wire [nBANK_MACHS-1:0] idle_ns; wire [nBANK_MACHS-1:0] rb_hit_busy_r; wire [nBANK_MACHS-1:0] bm_end; wire [nBANK_MACHS-1:0] passing_open_bank; wire [nBANK_MACHS-1:0] ordered_r; wire [nBANK_MACHS-1:0] ordered_issued; wire [nBANK_MACHS-1:0] rb_hit_busy_ns; wire [nBANK_MACHS-1:0] maint_hit; wire [nBANK_MACHS-1:0] idle_r; wire [nBANK_MACHS-1:0] head_r; wire [nBANK_MACHS-1:0] start_rcd; wire [nBANK_MACHS-1:0] end_rtp; wire [nBANK_MACHS-1:0] op_exit_req; wire [nBANK_MACHS-1:0] op_exit_grant; wire [nBANK_MACHS-1:0] start_pre_wait; wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns; genvar ID; generate for (ID=0; ID<nBANK_MACHS; ID=ID+1) begin:bank_cntrl mig_7series_v2_3_bank_cntrl # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_WIDTH (BANK_WIDTH), .BM_CNT_WIDTH (BM_CNT_WIDTH), .BURST_MODE (BURST_MODE), .COL_WIDTH (COL_WIDTH), .CWL (CWL), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .ECC (ECC), .ID (ID), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nOP_WAIT (nOP_WAIT), .nRAS_CLKS (nRAS_CLKS), .nRCD (nRCD), .nRTP (nRTP), .nRP (nRP), .nWTP_CLKS (nWTP_CLKS), .ORDERING (ORDERING), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .RAS_TIMER_WIDTH (RAS_TIMER_WIDTH), .ROW_WIDTH (ROW_WIDTH), .STARVE_LIMIT (STARVE_LIMIT)) bank0 (.demand_priority (demand_priority[ID]), .demand_priority_in ({2{demand_priority}}), .demand_act_priority (demand_act_priority[ID]), .demand_act_priority_in ({2{demand_act_priority}}), .rts_row (rts_row[ID]), .rts_col (rts_col[ID]), .rts_pre (rts_pre[ID]), .col_rdy_wr (col_rdy_wr[ID]), .rtc (rtc[ID]), .sending_row (sending_row[ID]), .sending_pre (sending_pre[ID]), .sending_col (sending_col[ID]), .req_data_buf_addr_r (req_data_buf_addr_r[(ID*DATA_BUF_ADDR_WIDTH)+:DATA_BUF_ADDR_WIDTH]), .req_size_r (req_size_r[ID]), .req_rank_r (req_rank_r[(ID*RANK_WIDTH)+:RANK_WIDTH]), .req_bank_r (req_bank_r[(ID*BANK_WIDTH)+:BANK_WIDTH]), .req_row_r (req_row_r[(ID*ROW_WIDTH)+:ROW_WIDTH]), .col_addr (col_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]), .req_wr_r (req_wr_r[ID]), .rd_wr_r (rd_wr_r[ID]), .req_periodic_rd_r (req_periodic_rd_r[ID]), .req_ras (req_ras[ID]), .req_cas (req_cas[ID]), .row_addr (row_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]), .row_cmd_wr (row_cmd_wr[ID]), .act_this_rank_r (act_this_rank_r[(ID*RANKS)+:RANKS]), .wr_this_rank_r (wr_this_rank_r[(ID*RANKS)+:RANKS]), .rd_this_rank_r (rd_this_rank_r[(ID*RANKS)+:RANKS]), .idle_ns (idle_ns[ID]), .rb_hit_busy_r (rb_hit_busy_r[ID]), .bm_end (bm_end[ID]), .bm_end_in ({2{bm_end}}), .passing_open_bank (passing_open_bank[ID]), .passing_open_bank_in ({2{passing_open_bank}}), .ordered_r (ordered_r[ID]), .ordered_issued (ordered_issued[ID]), .rb_hit_busy_ns (rb_hit_busy_ns[ID]), .rb_hit_busy_ns_in ({2{rb_hit_busy_ns}}), .maint_hit (maint_hit[ID]), .req_rank_r_in ({2{req_rank_r}}), .idle_r (idle_r[ID]), .head_r (head_r[ID]), .start_rcd (start_rcd[ID]), .start_rcd_in ({2{start_rcd}}), .end_rtp (end_rtp[ID]), .op_exit_req (op_exit_req[ID]), .op_exit_grant (op_exit_grant[ID]), .start_pre_wait (start_pre_wait[ID]), .ras_timer_ns (ras_timer_ns[(ID*RAS_TIMER_WIDTH)+:RAS_TIMER_WIDTH]), .ras_timer_ns_in ({2{ras_timer_ns}}), .rank_busy_r (rank_busy_r[ID*RANKS+:RANKS]), /*AUTOINST*/ // Inputs .accept_internal_r (accept_internal_r), .accept_req (accept_req), .adv_order_q (adv_order_q), .bank (bank[BANK_WIDTH-1:0]), .clk (clk), .cmd (cmd[2:0]), .col (col[COL_WIDTH-1:0]), .data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .phy_rddata_valid (phy_rddata_valid), .dq_busy_data (dq_busy_data), .hi_priority (hi_priority), .idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]), .inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]), .inhbt_rd (inhbt_rd[RANKS-1:0]), .inhbt_wr (inhbt_wr[RANKS-1:0]), .rnk_config (rnk_config[RANK_WIDTH-1:0]), .rnk_config_strobe (rnk_config_strobe), .rnk_config_kill_rts_col (rnk_config_kill_rts_col), .rnk_config_valid_r (rnk_config_valid_r), .low_idle_cnt_r (low_idle_cnt_r), .maint_idle (maint_idle), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .order_cnt (order_cnt[BM_CNT_WIDTH-1:0]), .periodic_rd_ack_r (periodic_rd_ack_r), .periodic_rd_insert (periodic_rd_insert), .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), .phy_mc_cmd_full (phy_mc_cmd_full), .phy_mc_ctl_full (phy_mc_ctl_full), .phy_mc_data_full (phy_mc_data_full), .rank (rank[RANK_WIDTH-1:0]), .rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]), .rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]), .rd_rmw (rd_rmw), .row (row[ROW_WIDTH-1:0]), .rst (rst), .sent_col (sent_col), .sent_row (sent_row), .size (size), .use_addr (use_addr), .was_priority (was_priority), .was_wr (was_wr)); end endgenerate mig_7series_v2_3_bank_common # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .BM_CNT_WIDTH (BM_CNT_WIDTH), .LOW_IDLE_CNT (LOW_IDLE_CNT), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nOP_WAIT (nOP_WAIT), .nRFC (nRFC), .nXSDLL (nXSDLL), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .CWL (CWL), .tZQCS (tZQCS)) bank_common0 (.op_exit_grant (op_exit_grant[nBANK_MACHS-1:0]), /*AUTOINST*/ // Outputs .accept_internal_r (accept_internal_r), .accept_ns (accept_ns), .accept (accept), .periodic_rd_insert (periodic_rd_insert), .periodic_rd_ack_r (periodic_rd_ack_r), .accept_req (accept_req), .rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]), .idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]), .idle (idle), .order_cnt (order_cnt[BM_CNT_WIDTH-1:0]), .adv_order_q (adv_order_q), .bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]), .low_idle_cnt_r (low_idle_cnt_r), .was_wr (was_wr), .was_priority (was_priority), .maint_wip_r (maint_wip_r), .maint_idle (maint_idle), .insert_maint_r (insert_maint_r), // Inputs .clk (clk), .rst (rst), .idle_ns (idle_ns[nBANK_MACHS-1:0]), .init_calib_complete (init_calib_complete), .periodic_rd_r (periodic_rd_r), .use_addr (use_addr), .rb_hit_busy_r (rb_hit_busy_r[nBANK_MACHS-1:0]), .idle_r (idle_r[nBANK_MACHS-1:0]), .ordered_r (ordered_r[nBANK_MACHS-1:0]), .ordered_issued (ordered_issued[nBANK_MACHS-1:0]), .head_r (head_r[nBANK_MACHS-1:0]), .end_rtp (end_rtp[nBANK_MACHS-1:0]), .passing_open_bank (passing_open_bank[nBANK_MACHS-1:0]), .op_exit_req (op_exit_req[nBANK_MACHS-1:0]), .start_pre_wait (start_pre_wait[nBANK_MACHS-1:0]), .cmd (cmd[2:0]), .hi_priority (hi_priority), .maint_req_r (maint_req_r), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .maint_hit (maint_hit[nBANK_MACHS-1:0]), .bm_end (bm_end[nBANK_MACHS-1:0]), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0])); mig_7series_v2_3_arb_mux # (/*AUTOINSTPARAM*/ // Parameters .TCQ (TCQ), .EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE), .ADDR_CMD_MODE (ADDR_CMD_MODE), .BANK_VECT_INDX (BANK_VECT_INDX), .BANK_WIDTH (BANK_WIDTH), .BURST_MODE (BURST_MODE), .CS_WIDTH (CS_WIDTH), .CL (CL), .CWL (CWL), .DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX), .DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH), .DRAM_TYPE (DRAM_TYPE), .EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR), .ECC (ECC), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .nCS_PER_RANK (nCS_PER_RANK), .nRAS (nRAS), .nRCD (nRCD), .CKE_ODT_AUX (CKE_ODT_AUX), .nSLOTS (nSLOTS), .nWR (nWR), .RANKS (RANKS), .RANK_VECT_INDX (RANK_VECT_INDX), .RANK_WIDTH (RANK_WIDTH), .ROW_VECT_INDX (ROW_VECT_INDX), .ROW_WIDTH (ROW_WIDTH), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .SLOT_0_CONFIG (SLOT_0_CONFIG), .SLOT_1_CONFIG (SLOT_1_CONFIG)) arb_mux0 (.rts_col (rts_col[nBANK_MACHS-1:0]), // AUTOs wants to make this an input. /*AUTOINST*/ // Outputs .col_a (col_a[ROW_WIDTH-1:0]), .col_ba (col_ba[BANK_WIDTH-1:0]), .col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .col_periodic_rd (col_periodic_rd), .col_ra (col_ra[RANK_WIDTH-1:0]), .col_rmw (col_rmw), .col_rd_wr (col_rd_wr), .col_row (col_row[ROW_WIDTH-1:0]), .col_size (col_size), .col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]), .mc_bank (mc_bank), .mc_address (mc_address), .mc_ras_n (mc_ras_n), .mc_cas_n (mc_cas_n), .mc_we_n (mc_we_n), .mc_cs_n (mc_cs_n), .mc_odt (mc_odt), .mc_cke (mc_cke), .mc_aux_out0 (mc_aux_out0), .mc_aux_out1 (mc_aux_out1), .mc_cmd (mc_cmd), .mc_data_offset (mc_data_offset), .mc_data_offset_1 (mc_data_offset_1), .mc_data_offset_2 (mc_data_offset_2), .rnk_config (rnk_config[RANK_WIDTH-1:0]), .rnk_config_valid_r (rnk_config_valid_r), .mc_cas_slot (mc_cas_slot), .sending_row (sending_row[nBANK_MACHS-1:0]), .sending_pre (sending_pre[nBANK_MACHS-1:0]), .sent_col (sent_col), .sent_col_r (sent_col_r), .sent_row (sent_row), .sending_col (sending_col[nBANK_MACHS-1:0]), .rnk_config_strobe (rnk_config_strobe), .rnk_config_kill_rts_col (rnk_config_kill_rts_col), .insert_maint_r1 (insert_maint_r1), // Inputs .init_calib_complete (init_calib_complete), .calib_rddata_offset (calib_rddata_offset), .calib_rddata_offset_1 (calib_rddata_offset_1), .calib_rddata_offset_2 (calib_rddata_offset_2), .col_addr (col_addr[ROW_VECT_INDX:0]), .col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]), .insert_maint_r (insert_maint_r), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]), .req_bank_r (req_bank_r[BANK_VECT_INDX:0]), .req_cas (req_cas[nBANK_MACHS-1:0]), .req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]), .req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]), .req_rank_r (req_rank_r[RANK_VECT_INDX:0]), .req_ras (req_ras[nBANK_MACHS-1:0]), .req_row_r (req_row_r[ROW_VECT_INDX:0]), .req_size_r (req_size_r[nBANK_MACHS-1:0]), .req_wr_r (req_wr_r[nBANK_MACHS-1:0]), .row_addr (row_addr[ROW_VECT_INDX:0]), .row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]), .rts_row (rts_row[nBANK_MACHS-1:0]), .rtc (rtc[nBANK_MACHS-1:0]), .rts_pre (rts_pre[nBANK_MACHS-1:0]), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0]), .clk (clk), .rst (rst)); endmodule // bank_mach

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : round_robin_arb.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // A simple round robin arbiter implemented in a not so simple // way. Two things make this special. First, it takes width as // a parameter and secondly it's constructed in a way to work with // restrictions synthesis programs. // // Consider each req/grant pair to be a // "channel". The arbiter computes a grant response to a request // on a channel by channel basis. // // The arbiter implementes a "round robin" algorithm. Ie, the granting // process is totally fair and symmetric. Each requester is given // equal priority. If all requests are asserted, the arbiter will // work sequentially around the list of requesters, giving each a grant. // // Grant priority is based on the "last_master". The last_master // vector stores the channel receiving the most recent grant. The // next higher numbered channel (wrapping around to zero) has highest // priority in subsequent cycles. Relative priority wraps around // the request vector with the last_master channel having lowest priority. // // At the highest implementation level, a per channel inhibit signal is computed. // This inhibit is bit-wise AND'ed with the incoming requests to // generate the grant. // // There will be at most a single grant per state. The logic // of the arbiter depends on this. // // Once a grant is given, it is stored as the last_master. The // last_master vector is initialized at reset to the zero'th channel. // Although the particular channel doesn't matter, it does matter // that the last_master contains a valid grant pattern. // // The heavy lifting is in computing the per channel inhibit signals. // This is accomplished in the generate statement. // // The first "for" loop in the generate statement steps through the channels. // // The second "for" loop steps through the last mast_master vector // for each channel. For each last_master bit, an inh_group is generated. // Following the end of the second "for" loop, the inh_group signals are OR'ed // together to generate the overall inhibit bit for the channel. // // For a four bit wide arbiter, this is what's generated for channel zero: // // inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits // inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit // inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits // // For req[0], last_master[3] is ignored because channel zero is highest priority // if last_master[3] is true. // `timescale 1ps/1ps module mig_7series_v2_3_round_robin_arb #( parameter TCQ = 100, parameter WIDTH = 3 ) ( /*AUTOARG*/ // Outputs grant_ns, grant_r, // Inputs clk, rst, req, disable_grant, current_master, upd_last_master ); input clk; input rst; input [WIDTH-1:0] req; wire [WIDTH-1:0] last_master_ns; reg [WIDTH*2-1:0] dbl_last_master_ns; always @(/*AS*/last_master_ns) dbl_last_master_ns = {last_master_ns, last_master_ns}; reg [WIDTH*2-1:0] dbl_req; always @(/*AS*/req) dbl_req = {req, req}; reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}}; genvar i; genvar j; generate for (i = 0; i < WIDTH; i = i + 1) begin : channel wire [WIDTH-1:1] inh_group; for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master assign inh_group[j+1] = dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1]; end always @(/*AS*/inh_group) inhibit[i] = |inh_group; end endgenerate input disable_grant; output wire [WIDTH-1:0] grant_ns; assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}}; output reg [WIDTH-1:0] grant_r; always @(posedge clk) grant_r <= #TCQ grant_ns; input [WIDTH-1:0] current_master; input upd_last_master; reg [WIDTH-1:0] last_master_r; localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024 //A '1' in the LSB of the last_master_r //signal gives a low priority to req[0] //after reset. To avoid this made MSB as //'1' at reset. assign last_master_ns = rst ? ONE[0+:WIDTH] : upd_last_master ? current_master : last_master_r; always @(posedge clk) last_master_r <= #TCQ last_master_ns; `ifdef MC_SVA grant_is_one_hot_zero: assert property (@(posedge clk) (rst || $onehot0(grant_ns))); last_master_r_is_one_hot: assert property (@(posedge clk) (rst || $onehot(last_master_r))); `endif endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : round_robin_arb.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // A simple round robin arbiter implemented in a not so simple // way. Two things make this special. First, it takes width as // a parameter and secondly it's constructed in a way to work with // restrictions synthesis programs. // // Consider each req/grant pair to be a // "channel". The arbiter computes a grant response to a request // on a channel by channel basis. // // The arbiter implementes a "round robin" algorithm. Ie, the granting // process is totally fair and symmetric. Each requester is given // equal priority. If all requests are asserted, the arbiter will // work sequentially around the list of requesters, giving each a grant. // // Grant priority is based on the "last_master". The last_master // vector stores the channel receiving the most recent grant. The // next higher numbered channel (wrapping around to zero) has highest // priority in subsequent cycles. Relative priority wraps around // the request vector with the last_master channel having lowest priority. // // At the highest implementation level, a per channel inhibit signal is computed. // This inhibit is bit-wise AND'ed with the incoming requests to // generate the grant. // // There will be at most a single grant per state. The logic // of the arbiter depends on this. // // Once a grant is given, it is stored as the last_master. The // last_master vector is initialized at reset to the zero'th channel. // Although the particular channel doesn't matter, it does matter // that the last_master contains a valid grant pattern. // // The heavy lifting is in computing the per channel inhibit signals. // This is accomplished in the generate statement. // // The first "for" loop in the generate statement steps through the channels. // // The second "for" loop steps through the last mast_master vector // for each channel. For each last_master bit, an inh_group is generated. // Following the end of the second "for" loop, the inh_group signals are OR'ed // together to generate the overall inhibit bit for the channel. // // For a four bit wide arbiter, this is what's generated for channel zero: // // inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits // inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit // inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits // // For req[0], last_master[3] is ignored because channel zero is highest priority // if last_master[3] is true. // `timescale 1ps/1ps module mig_7series_v2_3_round_robin_arb #( parameter TCQ = 100, parameter WIDTH = 3 ) ( /*AUTOARG*/ // Outputs grant_ns, grant_r, // Inputs clk, rst, req, disable_grant, current_master, upd_last_master ); input clk; input rst; input [WIDTH-1:0] req; wire [WIDTH-1:0] last_master_ns; reg [WIDTH*2-1:0] dbl_last_master_ns; always @(/*AS*/last_master_ns) dbl_last_master_ns = {last_master_ns, last_master_ns}; reg [WIDTH*2-1:0] dbl_req; always @(/*AS*/req) dbl_req = {req, req}; reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}}; genvar i; genvar j; generate for (i = 0; i < WIDTH; i = i + 1) begin : channel wire [WIDTH-1:1] inh_group; for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master assign inh_group[j+1] = dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1]; end always @(/*AS*/inh_group) inhibit[i] = |inh_group; end endgenerate input disable_grant; output wire [WIDTH-1:0] grant_ns; assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}}; output reg [WIDTH-1:0] grant_r; always @(posedge clk) grant_r <= #TCQ grant_ns; input [WIDTH-1:0] current_master; input upd_last_master; reg [WIDTH-1:0] last_master_r; localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024 //A '1' in the LSB of the last_master_r //signal gives a low priority to req[0] //after reset. To avoid this made MSB as //'1' at reset. assign last_master_ns = rst ? ONE[0+:WIDTH] : upd_last_master ? current_master : last_master_r; always @(posedge clk) last_master_r <= #TCQ last_master_ns; `ifdef MC_SVA grant_is_one_hot_zero: assert property (@(posedge clk) (rst || $onehot0(grant_ns))); last_master_r_is_one_hot: assert property (@(posedge clk) (rst || $onehot(last_master_r))); `endif endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : round_robin_arb.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // A simple round robin arbiter implemented in a not so simple // way. Two things make this special. First, it takes width as // a parameter and secondly it's constructed in a way to work with // restrictions synthesis programs. // // Consider each req/grant pair to be a // "channel". The arbiter computes a grant response to a request // on a channel by channel basis. // // The arbiter implementes a "round robin" algorithm. Ie, the granting // process is totally fair and symmetric. Each requester is given // equal priority. If all requests are asserted, the arbiter will // work sequentially around the list of requesters, giving each a grant. // // Grant priority is based on the "last_master". The last_master // vector stores the channel receiving the most recent grant. The // next higher numbered channel (wrapping around to zero) has highest // priority in subsequent cycles. Relative priority wraps around // the request vector with the last_master channel having lowest priority. // // At the highest implementation level, a per channel inhibit signal is computed. // This inhibit is bit-wise AND'ed with the incoming requests to // generate the grant. // // There will be at most a single grant per state. The logic // of the arbiter depends on this. // // Once a grant is given, it is stored as the last_master. The // last_master vector is initialized at reset to the zero'th channel. // Although the particular channel doesn't matter, it does matter // that the last_master contains a valid grant pattern. // // The heavy lifting is in computing the per channel inhibit signals. // This is accomplished in the generate statement. // // The first "for" loop in the generate statement steps through the channels. // // The second "for" loop steps through the last mast_master vector // for each channel. For each last_master bit, an inh_group is generated. // Following the end of the second "for" loop, the inh_group signals are OR'ed // together to generate the overall inhibit bit for the channel. // // For a four bit wide arbiter, this is what's generated for channel zero: // // inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits // inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit // inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits // // For req[0], last_master[3] is ignored because channel zero is highest priority // if last_master[3] is true. // `timescale 1ps/1ps module mig_7series_v2_3_round_robin_arb #( parameter TCQ = 100, parameter WIDTH = 3 ) ( /*AUTOARG*/ // Outputs grant_ns, grant_r, // Inputs clk, rst, req, disable_grant, current_master, upd_last_master ); input clk; input rst; input [WIDTH-1:0] req; wire [WIDTH-1:0] last_master_ns; reg [WIDTH*2-1:0] dbl_last_master_ns; always @(/*AS*/last_master_ns) dbl_last_master_ns = {last_master_ns, last_master_ns}; reg [WIDTH*2-1:0] dbl_req; always @(/*AS*/req) dbl_req = {req, req}; reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}}; genvar i; genvar j; generate for (i = 0; i < WIDTH; i = i + 1) begin : channel wire [WIDTH-1:1] inh_group; for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master assign inh_group[j+1] = dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1]; end always @(/*AS*/inh_group) inhibit[i] = |inh_group; end endgenerate input disable_grant; output wire [WIDTH-1:0] grant_ns; assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}}; output reg [WIDTH-1:0] grant_r; always @(posedge clk) grant_r <= #TCQ grant_ns; input [WIDTH-1:0] current_master; input upd_last_master; reg [WIDTH-1:0] last_master_r; localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024 //A '1' in the LSB of the last_master_r //signal gives a low priority to req[0] //after reset. To avoid this made MSB as //'1' at reset. assign last_master_ns = rst ? ONE[0+:WIDTH] : upd_last_master ? current_master : last_master_r; always @(posedge clk) last_master_r <= #TCQ last_master_ns; `ifdef MC_SVA grant_is_one_hot_zero: assert property (@(posedge clk) (rst || $onehot0(grant_ns))); last_master_r_is_one_hot: assert property (@(posedge clk) (rst || $onehot(last_master_r))); `endif endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : round_robin_arb.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // A simple round robin arbiter implemented in a not so simple // way. Two things make this special. First, it takes width as // a parameter and secondly it's constructed in a way to work with // restrictions synthesis programs. // // Consider each req/grant pair to be a // "channel". The arbiter computes a grant response to a request // on a channel by channel basis. // // The arbiter implementes a "round robin" algorithm. Ie, the granting // process is totally fair and symmetric. Each requester is given // equal priority. If all requests are asserted, the arbiter will // work sequentially around the list of requesters, giving each a grant. // // Grant priority is based on the "last_master". The last_master // vector stores the channel receiving the most recent grant. The // next higher numbered channel (wrapping around to zero) has highest // priority in subsequent cycles. Relative priority wraps around // the request vector with the last_master channel having lowest priority. // // At the highest implementation level, a per channel inhibit signal is computed. // This inhibit is bit-wise AND'ed with the incoming requests to // generate the grant. // // There will be at most a single grant per state. The logic // of the arbiter depends on this. // // Once a grant is given, it is stored as the last_master. The // last_master vector is initialized at reset to the zero'th channel. // Although the particular channel doesn't matter, it does matter // that the last_master contains a valid grant pattern. // // The heavy lifting is in computing the per channel inhibit signals. // This is accomplished in the generate statement. // // The first "for" loop in the generate statement steps through the channels. // // The second "for" loop steps through the last mast_master vector // for each channel. For each last_master bit, an inh_group is generated. // Following the end of the second "for" loop, the inh_group signals are OR'ed // together to generate the overall inhibit bit for the channel. // // For a four bit wide arbiter, this is what's generated for channel zero: // // inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits // inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit // inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits // // For req[0], last_master[3] is ignored because channel zero is highest priority // if last_master[3] is true. // `timescale 1ps/1ps module mig_7series_v2_3_round_robin_arb #( parameter TCQ = 100, parameter WIDTH = 3 ) ( /*AUTOARG*/ // Outputs grant_ns, grant_r, // Inputs clk, rst, req, disable_grant, current_master, upd_last_master ); input clk; input rst; input [WIDTH-1:0] req; wire [WIDTH-1:0] last_master_ns; reg [WIDTH*2-1:0] dbl_last_master_ns; always @(/*AS*/last_master_ns) dbl_last_master_ns = {last_master_ns, last_master_ns}; reg [WIDTH*2-1:0] dbl_req; always @(/*AS*/req) dbl_req = {req, req}; reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}}; genvar i; genvar j; generate for (i = 0; i < WIDTH; i = i + 1) begin : channel wire [WIDTH-1:1] inh_group; for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master assign inh_group[j+1] = dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1]; end always @(/*AS*/inh_group) inhibit[i] = |inh_group; end endgenerate input disable_grant; output wire [WIDTH-1:0] grant_ns; assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}}; output reg [WIDTH-1:0] grant_r; always @(posedge clk) grant_r <= #TCQ grant_ns; input [WIDTH-1:0] current_master; input upd_last_master; reg [WIDTH-1:0] last_master_r; localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024 //A '1' in the LSB of the last_master_r //signal gives a low priority to req[0] //after reset. To avoid this made MSB as //'1' at reset. assign last_master_ns = rst ? ONE[0+:WIDTH] : upd_last_master ? current_master : last_master_r; always @(posedge clk) last_master_r <= #TCQ last_master_ns; `ifdef MC_SVA grant_is_one_hot_zero: assert property (@(posedge clk) (rst || $onehot0(grant_ns))); last_master_r_is_one_hot: assert property (@(posedge clk) (rst || $onehot(last_master_r))); `endif endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : arb_row_col.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // This block receives request to send row and column commands. These requests // come the individual bank machines. The arbitration winner is selected // and driven back to the bank machines. // // The CS enables are generated. For 2:1 mode, row commands are sent // in the "0" phase, and column commands are sent in the "1" phase. // // In 2T mode, a further arbitration is performed between the row // and column commands. The winner of this arbitration inhibits // arbitration by the loser. The winner is allowed to arbitrate, the loser is // blocked until the next state. The winning address command // is repeated on both the "0" and the "1" phases and the CS // is asserted for just the "1" phase. `timescale 1 ps / 1 ps module mig_7series_v2_3_arb_row_col # ( parameter TCQ = 100, parameter ADDR_CMD_MODE = "1T", parameter CWL = 5, parameter EARLY_WR_DATA_ADDR = "OFF", parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, parameter nRAS = 37500, // ACT->PRE cmd period (CKs) parameter nRCD = 12500, // ACT->R/W delay (CKs) parameter nWR = 6 // Write recovery (CKs) ) (/*AUTOARG*/ // Outputs grant_row_r, grant_pre_r, sent_row, sending_row, sending_pre, grant_config_r, rnk_config_strobe, rnk_config_valid_r, grant_col_r, sending_col, sent_col, sent_col_r, grant_col_wr, send_cmd0_row, send_cmd0_col, send_cmd1_row, send_cmd1_col, send_cmd2_row, send_cmd2_col, send_cmd2_pre, send_cmd3_col, col_channel_offset, cs_en0, cs_en1, cs_en2, cs_en3, insert_maint_r1, rnk_config_kill_rts_col, // Inputs clk, rst, rts_row, rts_pre, insert_maint_r, rts_col, rtc, col_rdy_wr ); // Create a delay when switching ranks localparam RNK2RNK_DLY = 12; localparam RNK2RNK_DLY_CLKS = (RNK2RNK_DLY / nCK_PER_CLK) + (RNK2RNK_DLY % nCK_PER_CLK ? 1 : 0); input clk; input rst; input [nBANK_MACHS-1:0] rts_row; input insert_maint_r; input [nBANK_MACHS-1:0] rts_col; reg [RNK2RNK_DLY_CLKS-1:0] rnk_config_strobe_r; wire block_grant_row; wire block_grant_col; wire rnk_config_kill_rts_col_lcl = RNK2RNK_DLY_CLKS > 0 ? |rnk_config_strobe_r : 1'b0; output rnk_config_kill_rts_col; assign rnk_config_kill_rts_col = rnk_config_kill_rts_col_lcl; wire [nBANK_MACHS-1:0] col_request; wire granted_col_ns = |col_request; wire [nBANK_MACHS-1:0] row_request = rts_row & {nBANK_MACHS{~insert_maint_r}}; wire granted_row_ns = |row_request; generate if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK != 4) begin : row_col_2T_arb assign col_request = rts_col & {nBANK_MACHS{~(rnk_config_kill_rts_col_lcl || insert_maint_r)}}; // Give column command priority whenever previous state has no row request. wire [1:0] row_col_grant; wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant; wire upd_last_master = ~granted_row_ns || |row_col_grant; mig_7series_v2_3_round_robin_arb # (.WIDTH (2)) row_col_arb0 (.grant_ns (), .grant_r (row_col_grant), .upd_last_master (upd_last_master), .current_master (current_master), .clk (clk), .rst (rst), .req ({granted_row_ns, granted_col_ns}), .disable_grant (1'b0)); assign {block_grant_col, block_grant_row} = row_col_grant; end else begin : row_col_1T_arb assign col_request = rts_col & {nBANK_MACHS{~rnk_config_kill_rts_col_lcl}}; assign block_grant_row = 1'b0; assign block_grant_col = 1'b0; end endgenerate // Row address/command arbitration. wire[nBANK_MACHS-1:0] grant_row_r_lcl; output wire[nBANK_MACHS-1:0] grant_row_r; assign grant_row_r = grant_row_r_lcl; reg granted_row_r; always @(posedge clk) granted_row_r <= #TCQ granted_row_ns; wire sent_row_lcl = granted_row_r && ~block_grant_row; output wire sent_row; assign sent_row = sent_row_lcl; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) row_arb0 (.grant_ns (), .grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (sent_row_lcl), .current_master (grant_row_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (row_request), .disable_grant (1'b0)); output wire [nBANK_MACHS-1:0] sending_row; assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}}; // Precharge arbitration for 4:1 mode input [nBANK_MACHS-1:0] rts_pre; output wire[nBANK_MACHS-1:0] grant_pre_r; output wire [nBANK_MACHS-1:0] sending_pre; wire sent_pre_lcl; generate if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_4_1_1T_arb reg granted_pre_r; wire[nBANK_MACHS-1:0] grant_pre_r_lcl; wire granted_pre_ns = |rts_pre; assign grant_pre_r = grant_pre_r_lcl; always @(posedge clk) granted_pre_r <= #TCQ granted_pre_ns; assign sent_pre_lcl = granted_pre_r; assign sending_pre = grant_pre_r_lcl; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) pre_arb0 (.grant_ns (), .grant_r (grant_pre_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (sent_pre_lcl), .current_master (grant_pre_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (rts_pre), .disable_grant (1'b0)); end endgenerate `ifdef MC_SVA all_bank_machines_row_arb: cover property (@(posedge clk) (~rst && &rts_row)); `endif // Rank config arbitration. input [nBANK_MACHS-1:0] rtc; wire [nBANK_MACHS-1:0] grant_config_r_lcl; output wire [nBANK_MACHS-1:0] grant_config_r; assign grant_config_r = grant_config_r_lcl; wire upd_rnk_config_last_master; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) config_arb0 (.grant_ns (), .grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (upd_rnk_config_last_master), .current_master (grant_config_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (rtc[nBANK_MACHS-1:0]), .disable_grant (1'b0)); `ifdef MC_SVA all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc)); `endif wire rnk_config_strobe_ns = ~rnk_config_strobe_r[0] && |rtc && ~granted_col_ns; always @(posedge clk) rnk_config_strobe_r[0] <= #TCQ rnk_config_strobe_ns; genvar i; generate for(i = 1; i < RNK2RNK_DLY_CLKS; i = i + 1) always @(posedge clk) rnk_config_strobe_r[i] <= #TCQ rnk_config_strobe_r[i-1]; endgenerate output wire rnk_config_strobe; assign rnk_config_strobe = rnk_config_strobe_r[0]; assign upd_rnk_config_last_master = rnk_config_strobe_r[0]; // Generate rnk_config_valid. reg rnk_config_valid_r_lcl; wire rnk_config_valid_ns; assign rnk_config_valid_ns = ~rst && (rnk_config_valid_r_lcl || rnk_config_strobe_ns); always @(posedge clk) rnk_config_valid_r_lcl <= #TCQ rnk_config_valid_ns; output wire rnk_config_valid_r; assign rnk_config_valid_r = rnk_config_valid_r_lcl; // Column address/command arbitration. wire [nBANK_MACHS-1:0] grant_col_r_lcl; output wire [nBANK_MACHS-1:0] grant_col_r; assign grant_col_r = grant_col_r_lcl; reg granted_col_r; always @(posedge clk) granted_col_r <= #TCQ granted_col_ns; wire sent_col_lcl; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) col_arb0 (.grant_ns (), .grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (sent_col_lcl), .current_master (grant_col_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (col_request), .disable_grant (1'b0)); `ifdef MC_SVA all_bank_machines_col_arb: cover property (@(posedge clk) (~rst && &rts_col)); `endif output wire [nBANK_MACHS-1:0] sending_col; assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}}; assign sent_col_lcl = granted_col_r && ~block_grant_col; reg sent_col_lcl_r = 1'b0; always @(posedge clk) sent_col_lcl_r <= #TCQ sent_col_lcl; output wire sent_col; assign sent_col = sent_col_lcl; output wire sent_col_r; assign sent_col_r = sent_col_lcl_r; // If we need early wr_data_addr because ECC is on, arbitrate // to see which bank machine might sent the next wr_data_addr; input [nBANK_MACHS-1:0] col_rdy_wr; output wire [nBANK_MACHS-1:0] grant_col_wr; generate if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_addr_arb_off assign grant_col_wr = {nBANK_MACHS{1'b0}}; end else begin : early_wr_addr_arb_on wire [nBANK_MACHS-1:0] grant_col_wr_raw; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) col_arb0 (.grant_ns (grant_col_wr_raw), .grant_r (), .upd_last_master (sent_col_lcl), .current_master (grant_col_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (col_rdy_wr), .disable_grant (1'b0)); reg [nBANK_MACHS-1:0] grant_col_wr_r; wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns ? grant_col_wr_raw : grant_col_wr_r; always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns; assign grant_col_wr = grant_col_wr_ns; end // block: early_wr_addr_arb_on endgenerate output reg send_cmd0_row = 1'b0; output reg send_cmd0_col = 1'b0; output reg send_cmd1_row = 1'b0; output reg send_cmd1_col = 1'b0; output reg send_cmd2_row = 1'b0; output reg send_cmd2_col = 1'b0; output reg send_cmd2_pre = 1'b0; output reg send_cmd3_col = 1'b0; output reg cs_en0 = 1'b0; output reg cs_en1 = 1'b0; output reg cs_en2 = 1'b0; output reg cs_en3 = 1'b0; output wire [5:0] col_channel_offset; reg insert_maint_r1_lcl; always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r; output wire insert_maint_r1; assign insert_maint_r1 = insert_maint_r1_lcl; wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl; reg sent_row_or_maint_r = 1'b0; always @(posedge clk) sent_row_or_maint_r <= #TCQ sent_row_or_maint; generate case ({(nCK_PER_CLK == 4), (nCK_PER_CLK == 2), (ADDR_CMD_MODE == "2T")}) 3'b000 : begin : one_one_not2T end 3'b001 : begin : one_one_2T end 3'b010 : begin : two_one_not2T if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL always @(sent_col_lcl) begin cs_en0 = sent_col_lcl; send_cmd0_col = sent_col_lcl; end always @(sent_row_or_maint) begin cs_en1 = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end assign col_channel_offset = 0; end else begin // Place column commands on slot 1 for odd CWL always @(sent_row_or_maint) begin cs_en0 = sent_row_or_maint; send_cmd0_row = sent_row_or_maint; end always @(sent_col_lcl) begin cs_en1 = sent_col_lcl; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 1; end end 3'b011 : begin : two_one_2T if(!(CWL % 2)) begin // Place column commands on slot 1->0 for even CWL always @(sent_row_or_maint_r or sent_col_lcl_r) cs_en0 = sent_row_or_maint_r || sent_col_lcl_r; always @(sent_row_or_maint or sent_row_or_maint_r) begin send_cmd0_row = sent_row_or_maint_r; send_cmd1_row = sent_row_or_maint; end always @(sent_col_lcl or sent_col_lcl_r) begin send_cmd0_col = sent_col_lcl_r; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 0; end else begin // Place column commands on slot 0->1 for odd CWL always @(sent_col_lcl or sent_row_or_maint) cs_en1 = sent_row_or_maint || sent_col_lcl; always @(sent_row_or_maint) begin send_cmd0_row = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end always @(sent_col_lcl) begin send_cmd0_col = sent_col_lcl; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 1; end end 3'b100 : begin : four_one_not2T if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL always @(sent_col_lcl) begin cs_en0 = sent_col_lcl; send_cmd0_col = sent_col_lcl; end always @(sent_row_or_maint) begin cs_en1 = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end assign col_channel_offset = 0; end else begin // Place column commands on slot 1 for odd CWL always @(sent_row_or_maint) begin cs_en0 = sent_row_or_maint; send_cmd0_row = sent_row_or_maint; end always @(sent_col_lcl) begin cs_en1 = sent_col_lcl; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 1; end always @(sent_pre_lcl) begin cs_en2 = sent_pre_lcl; send_cmd2_pre = sent_pre_lcl; end end 3'b101 : begin : four_one_2T if(!(CWL % 2)) begin // Place column commands on slot 3->0 for even CWL always @(sent_col_lcl or sent_col_lcl_r) begin cs_en0 = sent_col_lcl_r; send_cmd0_col = sent_col_lcl_r; send_cmd3_col = sent_col_lcl; end always @(sent_row_or_maint) begin cs_en2 = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; send_cmd2_row = sent_row_or_maint; end assign col_channel_offset = 0; end else begin // Place column commands on slot 2->3 for odd CWL always @(sent_row_or_maint) begin cs_en1 = sent_row_or_maint; send_cmd0_row = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end always @(sent_col_lcl) begin cs_en3 = sent_col_lcl; send_cmd2_col = sent_col_lcl; send_cmd3_col = sent_col_lcl; end assign col_channel_offset = 3; end end endcase endgenerate endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : arb_row_col.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // This block receives request to send row and column commands. These requests // come the individual bank machines. The arbitration winner is selected // and driven back to the bank machines. // // The CS enables are generated. For 2:1 mode, row commands are sent // in the "0" phase, and column commands are sent in the "1" phase. // // In 2T mode, a further arbitration is performed between the row // and column commands. The winner of this arbitration inhibits // arbitration by the loser. The winner is allowed to arbitrate, the loser is // blocked until the next state. The winning address command // is repeated on both the "0" and the "1" phases and the CS // is asserted for just the "1" phase. `timescale 1 ps / 1 ps module mig_7series_v2_3_arb_row_col # ( parameter TCQ = 100, parameter ADDR_CMD_MODE = "1T", parameter CWL = 5, parameter EARLY_WR_DATA_ADDR = "OFF", parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, parameter nRAS = 37500, // ACT->PRE cmd period (CKs) parameter nRCD = 12500, // ACT->R/W delay (CKs) parameter nWR = 6 // Write recovery (CKs) ) (/*AUTOARG*/ // Outputs grant_row_r, grant_pre_r, sent_row, sending_row, sending_pre, grant_config_r, rnk_config_strobe, rnk_config_valid_r, grant_col_r, sending_col, sent_col, sent_col_r, grant_col_wr, send_cmd0_row, send_cmd0_col, send_cmd1_row, send_cmd1_col, send_cmd2_row, send_cmd2_col, send_cmd2_pre, send_cmd3_col, col_channel_offset, cs_en0, cs_en1, cs_en2, cs_en3, insert_maint_r1, rnk_config_kill_rts_col, // Inputs clk, rst, rts_row, rts_pre, insert_maint_r, rts_col, rtc, col_rdy_wr ); // Create a delay when switching ranks localparam RNK2RNK_DLY = 12; localparam RNK2RNK_DLY_CLKS = (RNK2RNK_DLY / nCK_PER_CLK) + (RNK2RNK_DLY % nCK_PER_CLK ? 1 : 0); input clk; input rst; input [nBANK_MACHS-1:0] rts_row; input insert_maint_r; input [nBANK_MACHS-1:0] rts_col; reg [RNK2RNK_DLY_CLKS-1:0] rnk_config_strobe_r; wire block_grant_row; wire block_grant_col; wire rnk_config_kill_rts_col_lcl = RNK2RNK_DLY_CLKS > 0 ? |rnk_config_strobe_r : 1'b0; output rnk_config_kill_rts_col; assign rnk_config_kill_rts_col = rnk_config_kill_rts_col_lcl; wire [nBANK_MACHS-1:0] col_request; wire granted_col_ns = |col_request; wire [nBANK_MACHS-1:0] row_request = rts_row & {nBANK_MACHS{~insert_maint_r}}; wire granted_row_ns = |row_request; generate if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK != 4) begin : row_col_2T_arb assign col_request = rts_col & {nBANK_MACHS{~(rnk_config_kill_rts_col_lcl || insert_maint_r)}}; // Give column command priority whenever previous state has no row request. wire [1:0] row_col_grant; wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant; wire upd_last_master = ~granted_row_ns || |row_col_grant; mig_7series_v2_3_round_robin_arb # (.WIDTH (2)) row_col_arb0 (.grant_ns (), .grant_r (row_col_grant), .upd_last_master (upd_last_master), .current_master (current_master), .clk (clk), .rst (rst), .req ({granted_row_ns, granted_col_ns}), .disable_grant (1'b0)); assign {block_grant_col, block_grant_row} = row_col_grant; end else begin : row_col_1T_arb assign col_request = rts_col & {nBANK_MACHS{~rnk_config_kill_rts_col_lcl}}; assign block_grant_row = 1'b0; assign block_grant_col = 1'b0; end endgenerate // Row address/command arbitration. wire[nBANK_MACHS-1:0] grant_row_r_lcl; output wire[nBANK_MACHS-1:0] grant_row_r; assign grant_row_r = grant_row_r_lcl; reg granted_row_r; always @(posedge clk) granted_row_r <= #TCQ granted_row_ns; wire sent_row_lcl = granted_row_r && ~block_grant_row; output wire sent_row; assign sent_row = sent_row_lcl; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) row_arb0 (.grant_ns (), .grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (sent_row_lcl), .current_master (grant_row_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (row_request), .disable_grant (1'b0)); output wire [nBANK_MACHS-1:0] sending_row; assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}}; // Precharge arbitration for 4:1 mode input [nBANK_MACHS-1:0] rts_pre; output wire[nBANK_MACHS-1:0] grant_pre_r; output wire [nBANK_MACHS-1:0] sending_pre; wire sent_pre_lcl; generate if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_4_1_1T_arb reg granted_pre_r; wire[nBANK_MACHS-1:0] grant_pre_r_lcl; wire granted_pre_ns = |rts_pre; assign grant_pre_r = grant_pre_r_lcl; always @(posedge clk) granted_pre_r <= #TCQ granted_pre_ns; assign sent_pre_lcl = granted_pre_r; assign sending_pre = grant_pre_r_lcl; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) pre_arb0 (.grant_ns (), .grant_r (grant_pre_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (sent_pre_lcl), .current_master (grant_pre_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (rts_pre), .disable_grant (1'b0)); end endgenerate `ifdef MC_SVA all_bank_machines_row_arb: cover property (@(posedge clk) (~rst && &rts_row)); `endif // Rank config arbitration. input [nBANK_MACHS-1:0] rtc; wire [nBANK_MACHS-1:0] grant_config_r_lcl; output wire [nBANK_MACHS-1:0] grant_config_r; assign grant_config_r = grant_config_r_lcl; wire upd_rnk_config_last_master; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) config_arb0 (.grant_ns (), .grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (upd_rnk_config_last_master), .current_master (grant_config_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (rtc[nBANK_MACHS-1:0]), .disable_grant (1'b0)); `ifdef MC_SVA all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc)); `endif wire rnk_config_strobe_ns = ~rnk_config_strobe_r[0] && |rtc && ~granted_col_ns; always @(posedge clk) rnk_config_strobe_r[0] <= #TCQ rnk_config_strobe_ns; genvar i; generate for(i = 1; i < RNK2RNK_DLY_CLKS; i = i + 1) always @(posedge clk) rnk_config_strobe_r[i] <= #TCQ rnk_config_strobe_r[i-1]; endgenerate output wire rnk_config_strobe; assign rnk_config_strobe = rnk_config_strobe_r[0]; assign upd_rnk_config_last_master = rnk_config_strobe_r[0]; // Generate rnk_config_valid. reg rnk_config_valid_r_lcl; wire rnk_config_valid_ns; assign rnk_config_valid_ns = ~rst && (rnk_config_valid_r_lcl || rnk_config_strobe_ns); always @(posedge clk) rnk_config_valid_r_lcl <= #TCQ rnk_config_valid_ns; output wire rnk_config_valid_r; assign rnk_config_valid_r = rnk_config_valid_r_lcl; // Column address/command arbitration. wire [nBANK_MACHS-1:0] grant_col_r_lcl; output wire [nBANK_MACHS-1:0] grant_col_r; assign grant_col_r = grant_col_r_lcl; reg granted_col_r; always @(posedge clk) granted_col_r <= #TCQ granted_col_ns; wire sent_col_lcl; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) col_arb0 (.grant_ns (), .grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (sent_col_lcl), .current_master (grant_col_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (col_request), .disable_grant (1'b0)); `ifdef MC_SVA all_bank_machines_col_arb: cover property (@(posedge clk) (~rst && &rts_col)); `endif output wire [nBANK_MACHS-1:0] sending_col; assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}}; assign sent_col_lcl = granted_col_r && ~block_grant_col; reg sent_col_lcl_r = 1'b0; always @(posedge clk) sent_col_lcl_r <= #TCQ sent_col_lcl; output wire sent_col; assign sent_col = sent_col_lcl; output wire sent_col_r; assign sent_col_r = sent_col_lcl_r; // If we need early wr_data_addr because ECC is on, arbitrate // to see which bank machine might sent the next wr_data_addr; input [nBANK_MACHS-1:0] col_rdy_wr; output wire [nBANK_MACHS-1:0] grant_col_wr; generate if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_addr_arb_off assign grant_col_wr = {nBANK_MACHS{1'b0}}; end else begin : early_wr_addr_arb_on wire [nBANK_MACHS-1:0] grant_col_wr_raw; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) col_arb0 (.grant_ns (grant_col_wr_raw), .grant_r (), .upd_last_master (sent_col_lcl), .current_master (grant_col_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (col_rdy_wr), .disable_grant (1'b0)); reg [nBANK_MACHS-1:0] grant_col_wr_r; wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns ? grant_col_wr_raw : grant_col_wr_r; always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns; assign grant_col_wr = grant_col_wr_ns; end // block: early_wr_addr_arb_on endgenerate output reg send_cmd0_row = 1'b0; output reg send_cmd0_col = 1'b0; output reg send_cmd1_row = 1'b0; output reg send_cmd1_col = 1'b0; output reg send_cmd2_row = 1'b0; output reg send_cmd2_col = 1'b0; output reg send_cmd2_pre = 1'b0; output reg send_cmd3_col = 1'b0; output reg cs_en0 = 1'b0; output reg cs_en1 = 1'b0; output reg cs_en2 = 1'b0; output reg cs_en3 = 1'b0; output wire [5:0] col_channel_offset; reg insert_maint_r1_lcl; always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r; output wire insert_maint_r1; assign insert_maint_r1 = insert_maint_r1_lcl; wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl; reg sent_row_or_maint_r = 1'b0; always @(posedge clk) sent_row_or_maint_r <= #TCQ sent_row_or_maint; generate case ({(nCK_PER_CLK == 4), (nCK_PER_CLK == 2), (ADDR_CMD_MODE == "2T")}) 3'b000 : begin : one_one_not2T end 3'b001 : begin : one_one_2T end 3'b010 : begin : two_one_not2T if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL always @(sent_col_lcl) begin cs_en0 = sent_col_lcl; send_cmd0_col = sent_col_lcl; end always @(sent_row_or_maint) begin cs_en1 = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end assign col_channel_offset = 0; end else begin // Place column commands on slot 1 for odd CWL always @(sent_row_or_maint) begin cs_en0 = sent_row_or_maint; send_cmd0_row = sent_row_or_maint; end always @(sent_col_lcl) begin cs_en1 = sent_col_lcl; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 1; end end 3'b011 : begin : two_one_2T if(!(CWL % 2)) begin // Place column commands on slot 1->0 for even CWL always @(sent_row_or_maint_r or sent_col_lcl_r) cs_en0 = sent_row_or_maint_r || sent_col_lcl_r; always @(sent_row_or_maint or sent_row_or_maint_r) begin send_cmd0_row = sent_row_or_maint_r; send_cmd1_row = sent_row_or_maint; end always @(sent_col_lcl or sent_col_lcl_r) begin send_cmd0_col = sent_col_lcl_r; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 0; end else begin // Place column commands on slot 0->1 for odd CWL always @(sent_col_lcl or sent_row_or_maint) cs_en1 = sent_row_or_maint || sent_col_lcl; always @(sent_row_or_maint) begin send_cmd0_row = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end always @(sent_col_lcl) begin send_cmd0_col = sent_col_lcl; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 1; end end 3'b100 : begin : four_one_not2T if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL always @(sent_col_lcl) begin cs_en0 = sent_col_lcl; send_cmd0_col = sent_col_lcl; end always @(sent_row_or_maint) begin cs_en1 = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end assign col_channel_offset = 0; end else begin // Place column commands on slot 1 for odd CWL always @(sent_row_or_maint) begin cs_en0 = sent_row_or_maint; send_cmd0_row = sent_row_or_maint; end always @(sent_col_lcl) begin cs_en1 = sent_col_lcl; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 1; end always @(sent_pre_lcl) begin cs_en2 = sent_pre_lcl; send_cmd2_pre = sent_pre_lcl; end end 3'b101 : begin : four_one_2T if(!(CWL % 2)) begin // Place column commands on slot 3->0 for even CWL always @(sent_col_lcl or sent_col_lcl_r) begin cs_en0 = sent_col_lcl_r; send_cmd0_col = sent_col_lcl_r; send_cmd3_col = sent_col_lcl; end always @(sent_row_or_maint) begin cs_en2 = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; send_cmd2_row = sent_row_or_maint; end assign col_channel_offset = 0; end else begin // Place column commands on slot 2->3 for odd CWL always @(sent_row_or_maint) begin cs_en1 = sent_row_or_maint; send_cmd0_row = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end always @(sent_col_lcl) begin cs_en3 = sent_col_lcl; send_cmd2_col = sent_col_lcl; send_cmd3_col = sent_col_lcl; end assign col_channel_offset = 3; end end endcase endgenerate endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : arb_row_col.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // This block receives request to send row and column commands. These requests // come the individual bank machines. The arbitration winner is selected // and driven back to the bank machines. // // The CS enables are generated. For 2:1 mode, row commands are sent // in the "0" phase, and column commands are sent in the "1" phase. // // In 2T mode, a further arbitration is performed between the row // and column commands. The winner of this arbitration inhibits // arbitration by the loser. The winner is allowed to arbitrate, the loser is // blocked until the next state. The winning address command // is repeated on both the "0" and the "1" phases and the CS // is asserted for just the "1" phase. `timescale 1 ps / 1 ps module mig_7series_v2_3_arb_row_col # ( parameter TCQ = 100, parameter ADDR_CMD_MODE = "1T", parameter CWL = 5, parameter EARLY_WR_DATA_ADDR = "OFF", parameter nBANK_MACHS = 4, parameter nCK_PER_CLK = 2, parameter nRAS = 37500, // ACT->PRE cmd period (CKs) parameter nRCD = 12500, // ACT->R/W delay (CKs) parameter nWR = 6 // Write recovery (CKs) ) (/*AUTOARG*/ // Outputs grant_row_r, grant_pre_r, sent_row, sending_row, sending_pre, grant_config_r, rnk_config_strobe, rnk_config_valid_r, grant_col_r, sending_col, sent_col, sent_col_r, grant_col_wr, send_cmd0_row, send_cmd0_col, send_cmd1_row, send_cmd1_col, send_cmd2_row, send_cmd2_col, send_cmd2_pre, send_cmd3_col, col_channel_offset, cs_en0, cs_en1, cs_en2, cs_en3, insert_maint_r1, rnk_config_kill_rts_col, // Inputs clk, rst, rts_row, rts_pre, insert_maint_r, rts_col, rtc, col_rdy_wr ); // Create a delay when switching ranks localparam RNK2RNK_DLY = 12; localparam RNK2RNK_DLY_CLKS = (RNK2RNK_DLY / nCK_PER_CLK) + (RNK2RNK_DLY % nCK_PER_CLK ? 1 : 0); input clk; input rst; input [nBANK_MACHS-1:0] rts_row; input insert_maint_r; input [nBANK_MACHS-1:0] rts_col; reg [RNK2RNK_DLY_CLKS-1:0] rnk_config_strobe_r; wire block_grant_row; wire block_grant_col; wire rnk_config_kill_rts_col_lcl = RNK2RNK_DLY_CLKS > 0 ? |rnk_config_strobe_r : 1'b0; output rnk_config_kill_rts_col; assign rnk_config_kill_rts_col = rnk_config_kill_rts_col_lcl; wire [nBANK_MACHS-1:0] col_request; wire granted_col_ns = |col_request; wire [nBANK_MACHS-1:0] row_request = rts_row & {nBANK_MACHS{~insert_maint_r}}; wire granted_row_ns = |row_request; generate if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK != 4) begin : row_col_2T_arb assign col_request = rts_col & {nBANK_MACHS{~(rnk_config_kill_rts_col_lcl || insert_maint_r)}}; // Give column command priority whenever previous state has no row request. wire [1:0] row_col_grant; wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant; wire upd_last_master = ~granted_row_ns || |row_col_grant; mig_7series_v2_3_round_robin_arb # (.WIDTH (2)) row_col_arb0 (.grant_ns (), .grant_r (row_col_grant), .upd_last_master (upd_last_master), .current_master (current_master), .clk (clk), .rst (rst), .req ({granted_row_ns, granted_col_ns}), .disable_grant (1'b0)); assign {block_grant_col, block_grant_row} = row_col_grant; end else begin : row_col_1T_arb assign col_request = rts_col & {nBANK_MACHS{~rnk_config_kill_rts_col_lcl}}; assign block_grant_row = 1'b0; assign block_grant_col = 1'b0; end endgenerate // Row address/command arbitration. wire[nBANK_MACHS-1:0] grant_row_r_lcl; output wire[nBANK_MACHS-1:0] grant_row_r; assign grant_row_r = grant_row_r_lcl; reg granted_row_r; always @(posedge clk) granted_row_r <= #TCQ granted_row_ns; wire sent_row_lcl = granted_row_r && ~block_grant_row; output wire sent_row; assign sent_row = sent_row_lcl; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) row_arb0 (.grant_ns (), .grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (sent_row_lcl), .current_master (grant_row_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (row_request), .disable_grant (1'b0)); output wire [nBANK_MACHS-1:0] sending_row; assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}}; // Precharge arbitration for 4:1 mode input [nBANK_MACHS-1:0] rts_pre; output wire[nBANK_MACHS-1:0] grant_pre_r; output wire [nBANK_MACHS-1:0] sending_pre; wire sent_pre_lcl; generate if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_4_1_1T_arb reg granted_pre_r; wire[nBANK_MACHS-1:0] grant_pre_r_lcl; wire granted_pre_ns = |rts_pre; assign grant_pre_r = grant_pre_r_lcl; always @(posedge clk) granted_pre_r <= #TCQ granted_pre_ns; assign sent_pre_lcl = granted_pre_r; assign sending_pre = grant_pre_r_lcl; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) pre_arb0 (.grant_ns (), .grant_r (grant_pre_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (sent_pre_lcl), .current_master (grant_pre_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (rts_pre), .disable_grant (1'b0)); end endgenerate `ifdef MC_SVA all_bank_machines_row_arb: cover property (@(posedge clk) (~rst && &rts_row)); `endif // Rank config arbitration. input [nBANK_MACHS-1:0] rtc; wire [nBANK_MACHS-1:0] grant_config_r_lcl; output wire [nBANK_MACHS-1:0] grant_config_r; assign grant_config_r = grant_config_r_lcl; wire upd_rnk_config_last_master; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) config_arb0 (.grant_ns (), .grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (upd_rnk_config_last_master), .current_master (grant_config_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (rtc[nBANK_MACHS-1:0]), .disable_grant (1'b0)); `ifdef MC_SVA all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc)); `endif wire rnk_config_strobe_ns = ~rnk_config_strobe_r[0] && |rtc && ~granted_col_ns; always @(posedge clk) rnk_config_strobe_r[0] <= #TCQ rnk_config_strobe_ns; genvar i; generate for(i = 1; i < RNK2RNK_DLY_CLKS; i = i + 1) always @(posedge clk) rnk_config_strobe_r[i] <= #TCQ rnk_config_strobe_r[i-1]; endgenerate output wire rnk_config_strobe; assign rnk_config_strobe = rnk_config_strobe_r[0]; assign upd_rnk_config_last_master = rnk_config_strobe_r[0]; // Generate rnk_config_valid. reg rnk_config_valid_r_lcl; wire rnk_config_valid_ns; assign rnk_config_valid_ns = ~rst && (rnk_config_valid_r_lcl || rnk_config_strobe_ns); always @(posedge clk) rnk_config_valid_r_lcl <= #TCQ rnk_config_valid_ns; output wire rnk_config_valid_r; assign rnk_config_valid_r = rnk_config_valid_r_lcl; // Column address/command arbitration. wire [nBANK_MACHS-1:0] grant_col_r_lcl; output wire [nBANK_MACHS-1:0] grant_col_r; assign grant_col_r = grant_col_r_lcl; reg granted_col_r; always @(posedge clk) granted_col_r <= #TCQ granted_col_ns; wire sent_col_lcl; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) col_arb0 (.grant_ns (), .grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]), .upd_last_master (sent_col_lcl), .current_master (grant_col_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (col_request), .disable_grant (1'b0)); `ifdef MC_SVA all_bank_machines_col_arb: cover property (@(posedge clk) (~rst && &rts_col)); `endif output wire [nBANK_MACHS-1:0] sending_col; assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}}; assign sent_col_lcl = granted_col_r && ~block_grant_col; reg sent_col_lcl_r = 1'b0; always @(posedge clk) sent_col_lcl_r <= #TCQ sent_col_lcl; output wire sent_col; assign sent_col = sent_col_lcl; output wire sent_col_r; assign sent_col_r = sent_col_lcl_r; // If we need early wr_data_addr because ECC is on, arbitrate // to see which bank machine might sent the next wr_data_addr; input [nBANK_MACHS-1:0] col_rdy_wr; output wire [nBANK_MACHS-1:0] grant_col_wr; generate if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_addr_arb_off assign grant_col_wr = {nBANK_MACHS{1'b0}}; end else begin : early_wr_addr_arb_on wire [nBANK_MACHS-1:0] grant_col_wr_raw; mig_7series_v2_3_round_robin_arb # (.WIDTH (nBANK_MACHS)) col_arb0 (.grant_ns (grant_col_wr_raw), .grant_r (), .upd_last_master (sent_col_lcl), .current_master (grant_col_r_lcl[nBANK_MACHS-1:0]), .clk (clk), .rst (rst), .req (col_rdy_wr), .disable_grant (1'b0)); reg [nBANK_MACHS-1:0] grant_col_wr_r; wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns ? grant_col_wr_raw : grant_col_wr_r; always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns; assign grant_col_wr = grant_col_wr_ns; end // block: early_wr_addr_arb_on endgenerate output reg send_cmd0_row = 1'b0; output reg send_cmd0_col = 1'b0; output reg send_cmd1_row = 1'b0; output reg send_cmd1_col = 1'b0; output reg send_cmd2_row = 1'b0; output reg send_cmd2_col = 1'b0; output reg send_cmd2_pre = 1'b0; output reg send_cmd3_col = 1'b0; output reg cs_en0 = 1'b0; output reg cs_en1 = 1'b0; output reg cs_en2 = 1'b0; output reg cs_en3 = 1'b0; output wire [5:0] col_channel_offset; reg insert_maint_r1_lcl; always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r; output wire insert_maint_r1; assign insert_maint_r1 = insert_maint_r1_lcl; wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl; reg sent_row_or_maint_r = 1'b0; always @(posedge clk) sent_row_or_maint_r <= #TCQ sent_row_or_maint; generate case ({(nCK_PER_CLK == 4), (nCK_PER_CLK == 2), (ADDR_CMD_MODE == "2T")}) 3'b000 : begin : one_one_not2T end 3'b001 : begin : one_one_2T end 3'b010 : begin : two_one_not2T if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL always @(sent_col_lcl) begin cs_en0 = sent_col_lcl; send_cmd0_col = sent_col_lcl; end always @(sent_row_or_maint) begin cs_en1 = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end assign col_channel_offset = 0; end else begin // Place column commands on slot 1 for odd CWL always @(sent_row_or_maint) begin cs_en0 = sent_row_or_maint; send_cmd0_row = sent_row_or_maint; end always @(sent_col_lcl) begin cs_en1 = sent_col_lcl; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 1; end end 3'b011 : begin : two_one_2T if(!(CWL % 2)) begin // Place column commands on slot 1->0 for even CWL always @(sent_row_or_maint_r or sent_col_lcl_r) cs_en0 = sent_row_or_maint_r || sent_col_lcl_r; always @(sent_row_or_maint or sent_row_or_maint_r) begin send_cmd0_row = sent_row_or_maint_r; send_cmd1_row = sent_row_or_maint; end always @(sent_col_lcl or sent_col_lcl_r) begin send_cmd0_col = sent_col_lcl_r; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 0; end else begin // Place column commands on slot 0->1 for odd CWL always @(sent_col_lcl or sent_row_or_maint) cs_en1 = sent_row_or_maint || sent_col_lcl; always @(sent_row_or_maint) begin send_cmd0_row = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end always @(sent_col_lcl) begin send_cmd0_col = sent_col_lcl; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 1; end end 3'b100 : begin : four_one_not2T if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL always @(sent_col_lcl) begin cs_en0 = sent_col_lcl; send_cmd0_col = sent_col_lcl; end always @(sent_row_or_maint) begin cs_en1 = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end assign col_channel_offset = 0; end else begin // Place column commands on slot 1 for odd CWL always @(sent_row_or_maint) begin cs_en0 = sent_row_or_maint; send_cmd0_row = sent_row_or_maint; end always @(sent_col_lcl) begin cs_en1 = sent_col_lcl; send_cmd1_col = sent_col_lcl; end assign col_channel_offset = 1; end always @(sent_pre_lcl) begin cs_en2 = sent_pre_lcl; send_cmd2_pre = sent_pre_lcl; end end 3'b101 : begin : four_one_2T if(!(CWL % 2)) begin // Place column commands on slot 3->0 for even CWL always @(sent_col_lcl or sent_col_lcl_r) begin cs_en0 = sent_col_lcl_r; send_cmd0_col = sent_col_lcl_r; send_cmd3_col = sent_col_lcl; end always @(sent_row_or_maint) begin cs_en2 = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; send_cmd2_row = sent_row_or_maint; end assign col_channel_offset = 0; end else begin // Place column commands on slot 2->3 for odd CWL always @(sent_row_or_maint) begin cs_en1 = sent_row_or_maint; send_cmd0_row = sent_row_or_maint; send_cmd1_row = sent_row_or_maint; end always @(sent_col_lcl) begin cs_en3 = sent_col_lcl; send_cmd2_col = sent_col_lcl; send_cmd3_col = sent_col_lcl; end assign col_channel_offset = 3; end end endcase endgenerate endmodule

// (C) 2001-2016 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $File: //acds/rel/16.0/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $ // $Revision: #1 $ // $Date: 2016/02/08 $ // $Author: swbranch $ //------------------------------------------------------------------------------ `timescale 1ns / 1ns module altera_avalon_st_pipeline_base ( clk, reset, in_ready, in_valid, in_data, out_ready, out_valid, out_data ); parameter SYMBOLS_PER_BEAT = 1; parameter BITS_PER_SYMBOL = 8; parameter PIPELINE_READY = 1; localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL; input clk; input reset; output in_ready; input in_valid; input [DATA_WIDTH-1:0] in_data; input out_ready; output out_valid; output [DATA_WIDTH-1:0] out_data; reg full0; reg full1; reg [DATA_WIDTH-1:0] data0; reg [DATA_WIDTH-1:0] data1; assign out_valid = full1; assign out_data = data1; generate if (PIPELINE_READY == 1) begin : REGISTERED_READY_PLINE assign in_ready = !full0; always @(posedge clk, posedge reset) begin if (reset) begin data0 <= {DATA_WIDTH{1'b0}}; data1 <= {DATA_WIDTH{1'b0}}; end else begin // ---------------------------- // always load the second slot if we can // ---------------------------- if (~full0) data0 <= in_data; // ---------------------------- // first slot is loaded either from the second, // or with new data // ---------------------------- if (~full1 || (out_ready && out_valid)) begin if (full0) data1 <= data0; else data1 <= in_data; end end end always @(posedge clk or posedge reset) begin if (reset) begin full0 <= 1'b0; full1 <= 1'b0; end else begin // no data in pipeline if (~full0 & ~full1) begin if (in_valid) begin full1 <= 1'b1; end end // ~f1 & ~f0 // one datum in pipeline if (full1 & ~full0) begin if (in_valid & ~out_ready) begin full0 <= 1'b1; end // back to empty if (~in_valid & out_ready) begin full1 <= 1'b0; end end // f1 & ~f0 // two data in pipeline if (full1 & full0) begin // go back to one datum state if (out_ready) begin full0 <= 1'b0; end end // end go back to one datum stage end end end else begin : UNREGISTERED_READY_PLINE // in_ready will be a pass through of the out_ready signal as it is not registered assign in_ready = (~full1) | out_ready; always @(posedge clk or posedge reset) begin if (reset) begin data1 <= 'b0; full1 <= 1'b0; end else begin if (in_ready) begin data1 <= in_data; full1 <= in_valid; end end end end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : mig_7series_v2_3_ddr_phy_tempmon.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Dec 20 2013 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Monitors chip temperature via the XADC and adjusts the // stage 2 tap values as appropriate. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_ddr_phy_tempmon # ( parameter TCQ = 100, // Register delay (simulation only) // Temperature bands must be in order. To disable bands, set to extreme. parameter TEMP_INCDEC = 1465, // Degrees C * 100 (14.65 * 100) parameter TEMP_HYST = 1, parameter TEMP_MIN_LIMIT = 12'h8ac, parameter TEMP_MAX_LIMIT = 12'hca4 ) ( input clk, // Fabric clock input rst, // System reset input calib_complete, // Calibration complete input tempmon_sample_en, // Signal to enable sampling input [11:0] device_temp, // Current device temperature output tempmon_pi_f_inc, // Increment PHASER_IN taps output tempmon_pi_f_dec, // Decrement PHASER_IN taps output tempmon_sel_pi_incdec // Assume control of PHASER_IN taps ); // translate hysteresis into XADC units localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504; localparam TEMP_INCDEC_OFFSET = ((TEMP_INCDEC * 4096) / 50400) ; // Temperature sampler FSM encoding localparam IDLE = 11'b000_0000_0001; localparam INIT = 11'b000_0000_0010; localparam FOUR_INC = 11'b000_0000_0100; localparam THREE_INC = 11'b000_0000_1000; localparam TWO_INC = 11'b000_0001_0000; localparam ONE_INC = 11'b000_0010_0000; localparam NEUTRAL = 11'b000_0100_0000; localparam ONE_DEC = 11'b000_1000_0000; localparam TWO_DEC = 11'b001_0000_0000; localparam THREE_DEC = 11'b010_0000_0000; localparam FOUR_DEC = 11'b100_0000_0000; //=========================================================================== // Reg declarations //=========================================================================== // Output port flops. Inc and dec are mutex. reg pi_f_dec; // Flop output reg pi_f_inc; // Flop output reg pi_f_dec_nxt; // FSM output reg pi_f_inc_nxt; // FSM output // FSM state reg [10:0] tempmon_state; reg [10:0] tempmon_state_nxt; // FSM output used to capture the initial device termperature reg tempmon_state_init; // Flag to indicate the initial device temperature is captured and normal operation can begin reg tempmon_init_complete; // Temperature band/state boundaries reg [11:0] four_inc_max_limit; reg [11:0] three_inc_max_limit; reg [11:0] two_inc_max_limit; reg [11:0] one_inc_max_limit; reg [11:0] neutral_max_limit; reg [11:0] one_dec_max_limit; reg [11:0] two_dec_max_limit; reg [11:0] three_dec_max_limit; reg [11:0] three_inc_min_limit; reg [11:0] two_inc_min_limit; reg [11:0] one_inc_min_limit; reg [11:0] neutral_min_limit; reg [11:0] one_dec_min_limit; reg [11:0] two_dec_min_limit; reg [11:0] three_dec_min_limit; reg [11:0] four_dec_min_limit; reg [11:0] device_temp_init; // Flops for capturing and storing the current device temperature reg tempmon_sample_en_101; reg tempmon_sample_en_102; reg [11:0] device_temp_101; reg [11:0] device_temp_capture_102; reg update_temp_102; // Flops for comparing temperature to max limits reg temp_cmp_four_inc_max_102; reg temp_cmp_three_inc_max_102; reg temp_cmp_two_inc_max_102; reg temp_cmp_one_inc_max_102; reg temp_cmp_neutral_max_102; reg temp_cmp_one_dec_max_102; reg temp_cmp_two_dec_max_102; reg temp_cmp_three_dec_max_102; // Flops for comparing temperature to min limits reg temp_cmp_three_inc_min_102; reg temp_cmp_two_inc_min_102; reg temp_cmp_one_inc_min_102; reg temp_cmp_neutral_min_102; reg temp_cmp_one_dec_min_102; reg temp_cmp_two_dec_min_102; reg temp_cmp_three_dec_min_102; reg temp_cmp_four_dec_min_102; //=========================================================================== // Overview and temperature band limits //=========================================================================== // The main feature of the tempmon block is an FSM that tracks the temerature provided by the ADC and decides if the phaser needs to be adjusted. The FSM // has nine temperature bands or states, centered around an initial device temperature. The name of each state is the net number of phaser increments or // decrements that have been issued in getting to the state. There are two temperature boundaries or limits between adjacent states. These two boundaries are // offset by a small amount to provide hysteresis. The max limits are the boundaries that are used to determine when to move to the next higher temperature state // and decrement the phaser. The min limits determine when to move to the next lower temperature state and increment the phaser. The limits are calculated when // the initial device temperature is taken, and will always be at fixed offsets from the initial device temperature. States with limits below 0C or above // 125C will never be entered. // Temperature lowest highest // <------------------------------------------------------------------------------------------------------------------------------------------------> // // Temp four three two one neutral one two three four // band/state inc inc inc inc dec dec dec dec // // Max limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| // Min limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| | // | | | | | | | // | | | | | | | // three_inc_min_limit | HYST_OFFSET--->| |<-- | four_dec_min_limit | // | device_temp_init | // four_inc_max_limit three_dec_max_limit // Boundaries for moving from lower temp bands to higher temp bands. // Note that only three_dec_max_limit can roll over, assuming device_temp_init is between 0C and 125C and TEMP_INCDEC_OFFSET is 14.65C, // and none of the min or max limits can roll under. So three_dec_max_limit has a check for being out of the 0x0 to 0xFFF range. wire [11:0] four_inc_max_limit_nxt = device_temp_init - 7*TEMP_INCDEC_OFFSET; // upper boundary of lowest temp band wire [11:0] three_inc_max_limit_nxt = device_temp_init - 5*TEMP_INCDEC_OFFSET; wire [11:0] two_inc_max_limit_nxt = device_temp_init - 3*TEMP_INCDEC_OFFSET; wire [11:0] one_inc_max_limit_nxt = device_temp_init - TEMP_INCDEC_OFFSET; wire [11:0] neutral_max_limit_nxt = device_temp_init + TEMP_INCDEC_OFFSET; // upper boundary of init temp band wire [11:0] one_dec_max_limit_nxt = device_temp_init + 3*TEMP_INCDEC_OFFSET; wire [11:0] two_dec_max_limit_nxt = device_temp_init + 5*TEMP_INCDEC_OFFSET; wire [12:0] three_dec_max_limit_tmp = device_temp_init + 7*TEMP_INCDEC_OFFSET; // upper boundary of 2nd highest temp band wire [11:0] three_dec_max_limit_nxt = three_dec_max_limit_tmp[12] ? 12'hFFF : three_dec_max_limit_tmp[11:0]; // Boundaries for moving from higher temp bands to lower temp bands wire [11:0] three_inc_min_limit_nxt = four_inc_max_limit - HYST_OFFSET; // lower boundary of 2nd lowest temp band wire [11:0] two_inc_min_limit_nxt = three_inc_max_limit - HYST_OFFSET; wire [11:0] one_inc_min_limit_nxt = two_inc_max_limit - HYST_OFFSET; wire [11:0] neutral_min_limit_nxt = one_inc_max_limit - HYST_OFFSET; // lower boundary of init temp band wire [11:0] one_dec_min_limit_nxt = neutral_max_limit - HYST_OFFSET; wire [11:0] two_dec_min_limit_nxt = one_dec_max_limit - HYST_OFFSET; wire [11:0] three_dec_min_limit_nxt = two_dec_max_limit - HYST_OFFSET; wire [11:0] four_dec_min_limit_nxt = three_dec_max_limit - HYST_OFFSET; // lower boundary of highest temp band //=========================================================================== // Capture device temperature //=========================================================================== // There is a three stage pipeline used to capture temperature, calculate the next state // of the FSM, and update the tempmon outputs. // // Stage 100 Inputs device_temp and tempmon_sample_en become valid and are flopped. // Input device_temp is compared to ADC codes for 0C and 125C and limited // at the flop input if needed. // // Stage 101 The flopped version of device_temp is compared to the FSM temperature band boundaries // to determine if a state change is needed. State changes are only enabled on the // rising edge of the flopped tempmon_sample_en signal. If there is a state change a phaser // increment or decrement signal is generated and flopped. // // Stage 102 The flopped versions of the phaser inc/dec signals drive the module outputs. // Limit device_temp to 0C to 125C and assign it to flop input device_temp_100 // temp C = ( ( ADC CODE * 503.975 ) / 4096 ) - 273.15 wire device_temp_high = device_temp > TEMP_MAX_LIMIT; wire device_temp_low = device_temp < TEMP_MIN_LIMIT; wire [11:0] device_temp_100 = ( { 12 { device_temp_high } } & TEMP_MAX_LIMIT ) | ( { 12 { device_temp_low } } & TEMP_MIN_LIMIT ) | ( { 12 { ~device_temp_high & ~device_temp_low } } & device_temp ); // Capture/hold the initial temperature used in setting temperature bands and set init complete flag // to enable normal sample operation. wire [11:0] device_temp_init_nxt = tempmon_state_init ? device_temp_101 : device_temp_init; wire tempmon_init_complete_nxt = tempmon_state_init ? 1'b1 : tempmon_init_complete; // Capture/hold the current temperature on the sample enable signal rising edge after init is complete. // The captured current temp is not used functionaly. It is just useful for debug and waveform review. wire update_temp_101 = tempmon_init_complete & ~tempmon_sample_en_102 & tempmon_sample_en_101; wire [11:0] device_temp_capture_101 = update_temp_101 ? device_temp_101 : device_temp_capture_102; //=========================================================================== // Generate FSM arc signals //=========================================================================== // Temperature comparisons for increasing temperature. wire temp_cmp_four_inc_max_101 = device_temp_101 >= four_inc_max_limit ; wire temp_cmp_three_inc_max_101 = device_temp_101 >= three_inc_max_limit ; wire temp_cmp_two_inc_max_101 = device_temp_101 >= two_inc_max_limit ; wire temp_cmp_one_inc_max_101 = device_temp_101 >= one_inc_max_limit ; wire temp_cmp_neutral_max_101 = device_temp_101 >= neutral_max_limit ; wire temp_cmp_one_dec_max_101 = device_temp_101 >= one_dec_max_limit ; wire temp_cmp_two_dec_max_101 = device_temp_101 >= two_dec_max_limit ; wire temp_cmp_three_dec_max_101 = device_temp_101 >= three_dec_max_limit ; // Temperature comparisons for decreasing temperature. wire temp_cmp_three_inc_min_101 = device_temp_101 < three_inc_min_limit ; wire temp_cmp_two_inc_min_101 = device_temp_101 < two_inc_min_limit ; wire temp_cmp_one_inc_min_101 = device_temp_101 < one_inc_min_limit ; wire temp_cmp_neutral_min_101 = device_temp_101 < neutral_min_limit ; wire temp_cmp_one_dec_min_101 = device_temp_101 < one_dec_min_limit ; wire temp_cmp_two_dec_min_101 = device_temp_101 < two_dec_min_limit ; wire temp_cmp_three_dec_min_101 = device_temp_101 < three_dec_min_limit ; wire temp_cmp_four_dec_min_101 = device_temp_101 < four_dec_min_limit ; // FSM arcs for increasing temperature. wire temp_gte_four_inc_max = update_temp_102 & temp_cmp_four_inc_max_102; wire temp_gte_three_inc_max = update_temp_102 & temp_cmp_three_inc_max_102; wire temp_gte_two_inc_max = update_temp_102 & temp_cmp_two_inc_max_102; wire temp_gte_one_inc_max = update_temp_102 & temp_cmp_one_inc_max_102; wire temp_gte_neutral_max = update_temp_102 & temp_cmp_neutral_max_102; wire temp_gte_one_dec_max = update_temp_102 & temp_cmp_one_dec_max_102; wire temp_gte_two_dec_max = update_temp_102 & temp_cmp_two_dec_max_102; wire temp_gte_three_dec_max = update_temp_102 & temp_cmp_three_dec_max_102; // FSM arcs for decreasing temperature. wire temp_lte_three_inc_min = update_temp_102 & temp_cmp_three_inc_min_102; wire temp_lte_two_inc_min = update_temp_102 & temp_cmp_two_inc_min_102; wire temp_lte_one_inc_min = update_temp_102 & temp_cmp_one_inc_min_102; wire temp_lte_neutral_min = update_temp_102 & temp_cmp_neutral_min_102; wire temp_lte_one_dec_min = update_temp_102 & temp_cmp_one_dec_min_102; wire temp_lte_two_dec_min = update_temp_102 & temp_cmp_two_dec_min_102; wire temp_lte_three_dec_min = update_temp_102 & temp_cmp_three_dec_min_102; wire temp_lte_four_dec_min = update_temp_102 & temp_cmp_four_dec_min_102; //=========================================================================== // Implement FSM //=========================================================================== // In addition to the nine temperature states, there are also IDLE and INIT states. // The INIT state triggers the calculation of the temperature boundaries between the // other states. After INIT, the FSM will always go to the NEUTRAL state. There is // no timing restriction required between calib_complete and tempmon_sample_en. always @(*) begin tempmon_state_nxt = tempmon_state; tempmon_state_init = 1'b0; pi_f_inc_nxt = 1'b0; pi_f_dec_nxt = 1'b0; casez (tempmon_state) IDLE: begin if (calib_complete) tempmon_state_nxt = INIT; end INIT: begin tempmon_state_nxt = NEUTRAL; tempmon_state_init = 1'b1; end FOUR_INC: begin if (temp_gte_four_inc_max) begin tempmon_state_nxt = THREE_INC; pi_f_dec_nxt = 1'b1; end end THREE_INC: begin if (temp_gte_three_inc_max) begin tempmon_state_nxt = TWO_INC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_three_inc_min) begin tempmon_state_nxt = FOUR_INC; pi_f_inc_nxt = 1'b1; end end TWO_INC: begin if (temp_gte_two_inc_max) begin tempmon_state_nxt = ONE_INC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_two_inc_min) begin tempmon_state_nxt = THREE_INC; pi_f_inc_nxt = 1'b1; end end ONE_INC: begin if (temp_gte_one_inc_max) begin tempmon_state_nxt = NEUTRAL; pi_f_dec_nxt = 1'b1; end else if (temp_lte_one_inc_min) begin tempmon_state_nxt = TWO_INC; pi_f_inc_nxt = 1'b1; end end NEUTRAL: begin if (temp_gte_neutral_max) begin tempmon_state_nxt = ONE_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_neutral_min) begin tempmon_state_nxt = ONE_INC; pi_f_inc_nxt = 1'b1; end end ONE_DEC: begin if (temp_gte_one_dec_max) begin tempmon_state_nxt = TWO_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_one_dec_min) begin tempmon_state_nxt = NEUTRAL; pi_f_inc_nxt = 1'b1; end end TWO_DEC: begin if (temp_gte_two_dec_max) begin tempmon_state_nxt = THREE_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_two_dec_min) begin tempmon_state_nxt = ONE_DEC; pi_f_inc_nxt = 1'b1; end end THREE_DEC: begin if (temp_gte_three_dec_max) begin tempmon_state_nxt = FOUR_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_three_dec_min) begin tempmon_state_nxt = TWO_DEC; pi_f_inc_nxt = 1'b1; end end FOUR_DEC: begin if (temp_lte_four_dec_min) begin tempmon_state_nxt = THREE_DEC; pi_f_inc_nxt = 1'b1; end end default: begin tempmon_state_nxt = IDLE; end endcase end //always //synopsys translate_off reg [71:0] tempmon_state_name; always @(*) casez (tempmon_state) IDLE : tempmon_state_name = "IDLE"; INIT : tempmon_state_name = "INIT"; FOUR_INC : tempmon_state_name = "FOUR_INC"; THREE_INC : tempmon_state_name = "THREE_INC"; TWO_INC : tempmon_state_name = "TWO_INC"; ONE_INC : tempmon_state_name = "ONE_INC"; NEUTRAL : tempmon_state_name = "NEUTRAL"; ONE_DEC : tempmon_state_name = "ONE_DEC"; TWO_DEC : tempmon_state_name = "TWO_DEC"; THREE_DEC : tempmon_state_name = "THREE_DEC"; FOUR_DEC : tempmon_state_name = "FOUR_DEC"; default : tempmon_state_name = "BAD_STATE"; endcase //synopsys translate_on //=========================================================================== // Generate final output and implement flops //=========================================================================== // Generate output assign tempmon_pi_f_inc = pi_f_inc; assign tempmon_pi_f_dec = pi_f_dec; assign tempmon_sel_pi_incdec = pi_f_inc | pi_f_dec; // Implement reset flops always @(posedge clk) begin if(rst) begin tempmon_state <= #TCQ 11'b000_0000_0001; pi_f_inc <= #TCQ 1'b0; pi_f_dec <= #TCQ 1'b0; four_inc_max_limit <= #TCQ 12'b0; three_inc_max_limit <= #TCQ 12'b0; two_inc_max_limit <= #TCQ 12'b0; one_inc_max_limit <= #TCQ 12'b0; neutral_max_limit <= #TCQ 12'b0; one_dec_max_limit <= #TCQ 12'b0; two_dec_max_limit <= #TCQ 12'b0; three_dec_max_limit <= #TCQ 12'b0; three_inc_min_limit <= #TCQ 12'b0; two_inc_min_limit <= #TCQ 12'b0; one_inc_min_limit <= #TCQ 12'b0; neutral_min_limit <= #TCQ 12'b0; one_dec_min_limit <= #TCQ 12'b0; two_dec_min_limit <= #TCQ 12'b0; three_dec_min_limit <= #TCQ 12'b0; four_dec_min_limit <= #TCQ 12'b0; device_temp_init <= #TCQ 12'b0; tempmon_init_complete <= #TCQ 1'b0; tempmon_sample_en_101 <= #TCQ 1'b0; tempmon_sample_en_102 <= #TCQ 1'b0; device_temp_101 <= #TCQ 12'b0; device_temp_capture_102 <= #TCQ 12'b0; end else begin tempmon_state <= #TCQ tempmon_state_nxt; pi_f_inc <= #TCQ pi_f_inc_nxt; pi_f_dec <= #TCQ pi_f_dec_nxt; four_inc_max_limit <= #TCQ four_inc_max_limit_nxt; three_inc_max_limit <= #TCQ three_inc_max_limit_nxt; two_inc_max_limit <= #TCQ two_inc_max_limit_nxt; one_inc_max_limit <= #TCQ one_inc_max_limit_nxt; neutral_max_limit <= #TCQ neutral_max_limit_nxt; one_dec_max_limit <= #TCQ one_dec_max_limit_nxt; two_dec_max_limit <= #TCQ two_dec_max_limit_nxt; three_dec_max_limit <= #TCQ three_dec_max_limit_nxt; three_inc_min_limit <= #TCQ three_inc_min_limit_nxt; two_inc_min_limit <= #TCQ two_inc_min_limit_nxt; one_inc_min_limit <= #TCQ one_inc_min_limit_nxt; neutral_min_limit <= #TCQ neutral_min_limit_nxt; one_dec_min_limit <= #TCQ one_dec_min_limit_nxt; two_dec_min_limit <= #TCQ two_dec_min_limit_nxt; three_dec_min_limit <= #TCQ three_dec_min_limit_nxt; four_dec_min_limit <= #TCQ four_dec_min_limit_nxt; device_temp_init <= #TCQ device_temp_init_nxt; tempmon_init_complete <= #TCQ tempmon_init_complete_nxt; tempmon_sample_en_101 <= #TCQ tempmon_sample_en; tempmon_sample_en_102 <= #TCQ tempmon_sample_en_101; device_temp_101 <= #TCQ device_temp_100; device_temp_capture_102 <= #TCQ device_temp_capture_101; end end // Implement non-reset flops always @(posedge clk) begin temp_cmp_four_inc_max_102 <= #TCQ temp_cmp_four_inc_max_101; temp_cmp_three_inc_max_102 <= #TCQ temp_cmp_three_inc_max_101; temp_cmp_two_inc_max_102 <= #TCQ temp_cmp_two_inc_max_101; temp_cmp_one_inc_max_102 <= #TCQ temp_cmp_one_inc_max_101; temp_cmp_neutral_max_102 <= #TCQ temp_cmp_neutral_max_101; temp_cmp_one_dec_max_102 <= #TCQ temp_cmp_one_dec_max_101; temp_cmp_two_dec_max_102 <= #TCQ temp_cmp_two_dec_max_101; temp_cmp_three_dec_max_102 <= #TCQ temp_cmp_three_dec_max_101; temp_cmp_three_inc_min_102 <= #TCQ temp_cmp_three_inc_min_101; temp_cmp_two_inc_min_102 <= #TCQ temp_cmp_two_inc_min_101; temp_cmp_one_inc_min_102 <= #TCQ temp_cmp_one_inc_min_101; temp_cmp_neutral_min_102 <= #TCQ temp_cmp_neutral_min_101; temp_cmp_one_dec_min_102 <= #TCQ temp_cmp_one_dec_min_101; temp_cmp_two_dec_min_102 <= #TCQ temp_cmp_two_dec_min_101; temp_cmp_three_dec_min_102 <= #TCQ temp_cmp_three_dec_min_101; temp_cmp_four_dec_min_102 <= #TCQ temp_cmp_four_dec_min_101; update_temp_102 <= #TCQ update_temp_101; end endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : mig_7series_v2_3_ddr_phy_tempmon.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Dec 20 2013 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Monitors chip temperature via the XADC and adjusts the // stage 2 tap values as appropriate. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_ddr_phy_tempmon # ( parameter TCQ = 100, // Register delay (simulation only) // Temperature bands must be in order. To disable bands, set to extreme. parameter TEMP_INCDEC = 1465, // Degrees C * 100 (14.65 * 100) parameter TEMP_HYST = 1, parameter TEMP_MIN_LIMIT = 12'h8ac, parameter TEMP_MAX_LIMIT = 12'hca4 ) ( input clk, // Fabric clock input rst, // System reset input calib_complete, // Calibration complete input tempmon_sample_en, // Signal to enable sampling input [11:0] device_temp, // Current device temperature output tempmon_pi_f_inc, // Increment PHASER_IN taps output tempmon_pi_f_dec, // Decrement PHASER_IN taps output tempmon_sel_pi_incdec // Assume control of PHASER_IN taps ); // translate hysteresis into XADC units localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504; localparam TEMP_INCDEC_OFFSET = ((TEMP_INCDEC * 4096) / 50400) ; // Temperature sampler FSM encoding localparam IDLE = 11'b000_0000_0001; localparam INIT = 11'b000_0000_0010; localparam FOUR_INC = 11'b000_0000_0100; localparam THREE_INC = 11'b000_0000_1000; localparam TWO_INC = 11'b000_0001_0000; localparam ONE_INC = 11'b000_0010_0000; localparam NEUTRAL = 11'b000_0100_0000; localparam ONE_DEC = 11'b000_1000_0000; localparam TWO_DEC = 11'b001_0000_0000; localparam THREE_DEC = 11'b010_0000_0000; localparam FOUR_DEC = 11'b100_0000_0000; //=========================================================================== // Reg declarations //=========================================================================== // Output port flops. Inc and dec are mutex. reg pi_f_dec; // Flop output reg pi_f_inc; // Flop output reg pi_f_dec_nxt; // FSM output reg pi_f_inc_nxt; // FSM output // FSM state reg [10:0] tempmon_state; reg [10:0] tempmon_state_nxt; // FSM output used to capture the initial device termperature reg tempmon_state_init; // Flag to indicate the initial device temperature is captured and normal operation can begin reg tempmon_init_complete; // Temperature band/state boundaries reg [11:0] four_inc_max_limit; reg [11:0] three_inc_max_limit; reg [11:0] two_inc_max_limit; reg [11:0] one_inc_max_limit; reg [11:0] neutral_max_limit; reg [11:0] one_dec_max_limit; reg [11:0] two_dec_max_limit; reg [11:0] three_dec_max_limit; reg [11:0] three_inc_min_limit; reg [11:0] two_inc_min_limit; reg [11:0] one_inc_min_limit; reg [11:0] neutral_min_limit; reg [11:0] one_dec_min_limit; reg [11:0] two_dec_min_limit; reg [11:0] three_dec_min_limit; reg [11:0] four_dec_min_limit; reg [11:0] device_temp_init; // Flops for capturing and storing the current device temperature reg tempmon_sample_en_101; reg tempmon_sample_en_102; reg [11:0] device_temp_101; reg [11:0] device_temp_capture_102; reg update_temp_102; // Flops for comparing temperature to max limits reg temp_cmp_four_inc_max_102; reg temp_cmp_three_inc_max_102; reg temp_cmp_two_inc_max_102; reg temp_cmp_one_inc_max_102; reg temp_cmp_neutral_max_102; reg temp_cmp_one_dec_max_102; reg temp_cmp_two_dec_max_102; reg temp_cmp_three_dec_max_102; // Flops for comparing temperature to min limits reg temp_cmp_three_inc_min_102; reg temp_cmp_two_inc_min_102; reg temp_cmp_one_inc_min_102; reg temp_cmp_neutral_min_102; reg temp_cmp_one_dec_min_102; reg temp_cmp_two_dec_min_102; reg temp_cmp_three_dec_min_102; reg temp_cmp_four_dec_min_102; //=========================================================================== // Overview and temperature band limits //=========================================================================== // The main feature of the tempmon block is an FSM that tracks the temerature provided by the ADC and decides if the phaser needs to be adjusted. The FSM // has nine temperature bands or states, centered around an initial device temperature. The name of each state is the net number of phaser increments or // decrements that have been issued in getting to the state. There are two temperature boundaries or limits between adjacent states. These two boundaries are // offset by a small amount to provide hysteresis. The max limits are the boundaries that are used to determine when to move to the next higher temperature state // and decrement the phaser. The min limits determine when to move to the next lower temperature state and increment the phaser. The limits are calculated when // the initial device temperature is taken, and will always be at fixed offsets from the initial device temperature. States with limits below 0C or above // 125C will never be entered. // Temperature lowest highest // <------------------------------------------------------------------------------------------------------------------------------------------------> // // Temp four three two one neutral one two three four // band/state inc inc inc inc dec dec dec dec // // Max limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| // Min limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| | // | | | | | | | // | | | | | | | // three_inc_min_limit | HYST_OFFSET--->| |<-- | four_dec_min_limit | // | device_temp_init | // four_inc_max_limit three_dec_max_limit // Boundaries for moving from lower temp bands to higher temp bands. // Note that only three_dec_max_limit can roll over, assuming device_temp_init is between 0C and 125C and TEMP_INCDEC_OFFSET is 14.65C, // and none of the min or max limits can roll under. So three_dec_max_limit has a check for being out of the 0x0 to 0xFFF range. wire [11:0] four_inc_max_limit_nxt = device_temp_init - 7*TEMP_INCDEC_OFFSET; // upper boundary of lowest temp band wire [11:0] three_inc_max_limit_nxt = device_temp_init - 5*TEMP_INCDEC_OFFSET; wire [11:0] two_inc_max_limit_nxt = device_temp_init - 3*TEMP_INCDEC_OFFSET; wire [11:0] one_inc_max_limit_nxt = device_temp_init - TEMP_INCDEC_OFFSET; wire [11:0] neutral_max_limit_nxt = device_temp_init + TEMP_INCDEC_OFFSET; // upper boundary of init temp band wire [11:0] one_dec_max_limit_nxt = device_temp_init + 3*TEMP_INCDEC_OFFSET; wire [11:0] two_dec_max_limit_nxt = device_temp_init + 5*TEMP_INCDEC_OFFSET; wire [12:0] three_dec_max_limit_tmp = device_temp_init + 7*TEMP_INCDEC_OFFSET; // upper boundary of 2nd highest temp band wire [11:0] three_dec_max_limit_nxt = three_dec_max_limit_tmp[12] ? 12'hFFF : three_dec_max_limit_tmp[11:0]; // Boundaries for moving from higher temp bands to lower temp bands wire [11:0] three_inc_min_limit_nxt = four_inc_max_limit - HYST_OFFSET; // lower boundary of 2nd lowest temp band wire [11:0] two_inc_min_limit_nxt = three_inc_max_limit - HYST_OFFSET; wire [11:0] one_inc_min_limit_nxt = two_inc_max_limit - HYST_OFFSET; wire [11:0] neutral_min_limit_nxt = one_inc_max_limit - HYST_OFFSET; // lower boundary of init temp band wire [11:0] one_dec_min_limit_nxt = neutral_max_limit - HYST_OFFSET; wire [11:0] two_dec_min_limit_nxt = one_dec_max_limit - HYST_OFFSET; wire [11:0] three_dec_min_limit_nxt = two_dec_max_limit - HYST_OFFSET; wire [11:0] four_dec_min_limit_nxt = three_dec_max_limit - HYST_OFFSET; // lower boundary of highest temp band //=========================================================================== // Capture device temperature //=========================================================================== // There is a three stage pipeline used to capture temperature, calculate the next state // of the FSM, and update the tempmon outputs. // // Stage 100 Inputs device_temp and tempmon_sample_en become valid and are flopped. // Input device_temp is compared to ADC codes for 0C and 125C and limited // at the flop input if needed. // // Stage 101 The flopped version of device_temp is compared to the FSM temperature band boundaries // to determine if a state change is needed. State changes are only enabled on the // rising edge of the flopped tempmon_sample_en signal. If there is a state change a phaser // increment or decrement signal is generated and flopped. // // Stage 102 The flopped versions of the phaser inc/dec signals drive the module outputs. // Limit device_temp to 0C to 125C and assign it to flop input device_temp_100 // temp C = ( ( ADC CODE * 503.975 ) / 4096 ) - 273.15 wire device_temp_high = device_temp > TEMP_MAX_LIMIT; wire device_temp_low = device_temp < TEMP_MIN_LIMIT; wire [11:0] device_temp_100 = ( { 12 { device_temp_high } } & TEMP_MAX_LIMIT ) | ( { 12 { device_temp_low } } & TEMP_MIN_LIMIT ) | ( { 12 { ~device_temp_high & ~device_temp_low } } & device_temp ); // Capture/hold the initial temperature used in setting temperature bands and set init complete flag // to enable normal sample operation. wire [11:0] device_temp_init_nxt = tempmon_state_init ? device_temp_101 : device_temp_init; wire tempmon_init_complete_nxt = tempmon_state_init ? 1'b1 : tempmon_init_complete; // Capture/hold the current temperature on the sample enable signal rising edge after init is complete. // The captured current temp is not used functionaly. It is just useful for debug and waveform review. wire update_temp_101 = tempmon_init_complete & ~tempmon_sample_en_102 & tempmon_sample_en_101; wire [11:0] device_temp_capture_101 = update_temp_101 ? device_temp_101 : device_temp_capture_102; //=========================================================================== // Generate FSM arc signals //=========================================================================== // Temperature comparisons for increasing temperature. wire temp_cmp_four_inc_max_101 = device_temp_101 >= four_inc_max_limit ; wire temp_cmp_three_inc_max_101 = device_temp_101 >= three_inc_max_limit ; wire temp_cmp_two_inc_max_101 = device_temp_101 >= two_inc_max_limit ; wire temp_cmp_one_inc_max_101 = device_temp_101 >= one_inc_max_limit ; wire temp_cmp_neutral_max_101 = device_temp_101 >= neutral_max_limit ; wire temp_cmp_one_dec_max_101 = device_temp_101 >= one_dec_max_limit ; wire temp_cmp_two_dec_max_101 = device_temp_101 >= two_dec_max_limit ; wire temp_cmp_three_dec_max_101 = device_temp_101 >= three_dec_max_limit ; // Temperature comparisons for decreasing temperature. wire temp_cmp_three_inc_min_101 = device_temp_101 < three_inc_min_limit ; wire temp_cmp_two_inc_min_101 = device_temp_101 < two_inc_min_limit ; wire temp_cmp_one_inc_min_101 = device_temp_101 < one_inc_min_limit ; wire temp_cmp_neutral_min_101 = device_temp_101 < neutral_min_limit ; wire temp_cmp_one_dec_min_101 = device_temp_101 < one_dec_min_limit ; wire temp_cmp_two_dec_min_101 = device_temp_101 < two_dec_min_limit ; wire temp_cmp_three_dec_min_101 = device_temp_101 < three_dec_min_limit ; wire temp_cmp_four_dec_min_101 = device_temp_101 < four_dec_min_limit ; // FSM arcs for increasing temperature. wire temp_gte_four_inc_max = update_temp_102 & temp_cmp_four_inc_max_102; wire temp_gte_three_inc_max = update_temp_102 & temp_cmp_three_inc_max_102; wire temp_gte_two_inc_max = update_temp_102 & temp_cmp_two_inc_max_102; wire temp_gte_one_inc_max = update_temp_102 & temp_cmp_one_inc_max_102; wire temp_gte_neutral_max = update_temp_102 & temp_cmp_neutral_max_102; wire temp_gte_one_dec_max = update_temp_102 & temp_cmp_one_dec_max_102; wire temp_gte_two_dec_max = update_temp_102 & temp_cmp_two_dec_max_102; wire temp_gte_three_dec_max = update_temp_102 & temp_cmp_three_dec_max_102; // FSM arcs for decreasing temperature. wire temp_lte_three_inc_min = update_temp_102 & temp_cmp_three_inc_min_102; wire temp_lte_two_inc_min = update_temp_102 & temp_cmp_two_inc_min_102; wire temp_lte_one_inc_min = update_temp_102 & temp_cmp_one_inc_min_102; wire temp_lte_neutral_min = update_temp_102 & temp_cmp_neutral_min_102; wire temp_lte_one_dec_min = update_temp_102 & temp_cmp_one_dec_min_102; wire temp_lte_two_dec_min = update_temp_102 & temp_cmp_two_dec_min_102; wire temp_lte_three_dec_min = update_temp_102 & temp_cmp_three_dec_min_102; wire temp_lte_four_dec_min = update_temp_102 & temp_cmp_four_dec_min_102; //=========================================================================== // Implement FSM //=========================================================================== // In addition to the nine temperature states, there are also IDLE and INIT states. // The INIT state triggers the calculation of the temperature boundaries between the // other states. After INIT, the FSM will always go to the NEUTRAL state. There is // no timing restriction required between calib_complete and tempmon_sample_en. always @(*) begin tempmon_state_nxt = tempmon_state; tempmon_state_init = 1'b0; pi_f_inc_nxt = 1'b0; pi_f_dec_nxt = 1'b0; casez (tempmon_state) IDLE: begin if (calib_complete) tempmon_state_nxt = INIT; end INIT: begin tempmon_state_nxt = NEUTRAL; tempmon_state_init = 1'b1; end FOUR_INC: begin if (temp_gte_four_inc_max) begin tempmon_state_nxt = THREE_INC; pi_f_dec_nxt = 1'b1; end end THREE_INC: begin if (temp_gte_three_inc_max) begin tempmon_state_nxt = TWO_INC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_three_inc_min) begin tempmon_state_nxt = FOUR_INC; pi_f_inc_nxt = 1'b1; end end TWO_INC: begin if (temp_gte_two_inc_max) begin tempmon_state_nxt = ONE_INC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_two_inc_min) begin tempmon_state_nxt = THREE_INC; pi_f_inc_nxt = 1'b1; end end ONE_INC: begin if (temp_gte_one_inc_max) begin tempmon_state_nxt = NEUTRAL; pi_f_dec_nxt = 1'b1; end else if (temp_lte_one_inc_min) begin tempmon_state_nxt = TWO_INC; pi_f_inc_nxt = 1'b1; end end NEUTRAL: begin if (temp_gte_neutral_max) begin tempmon_state_nxt = ONE_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_neutral_min) begin tempmon_state_nxt = ONE_INC; pi_f_inc_nxt = 1'b1; end end ONE_DEC: begin if (temp_gte_one_dec_max) begin tempmon_state_nxt = TWO_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_one_dec_min) begin tempmon_state_nxt = NEUTRAL; pi_f_inc_nxt = 1'b1; end end TWO_DEC: begin if (temp_gte_two_dec_max) begin tempmon_state_nxt = THREE_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_two_dec_min) begin tempmon_state_nxt = ONE_DEC; pi_f_inc_nxt = 1'b1; end end THREE_DEC: begin if (temp_gte_three_dec_max) begin tempmon_state_nxt = FOUR_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_three_dec_min) begin tempmon_state_nxt = TWO_DEC; pi_f_inc_nxt = 1'b1; end end FOUR_DEC: begin if (temp_lte_four_dec_min) begin tempmon_state_nxt = THREE_DEC; pi_f_inc_nxt = 1'b1; end end default: begin tempmon_state_nxt = IDLE; end endcase end //always //synopsys translate_off reg [71:0] tempmon_state_name; always @(*) casez (tempmon_state) IDLE : tempmon_state_name = "IDLE"; INIT : tempmon_state_name = "INIT"; FOUR_INC : tempmon_state_name = "FOUR_INC"; THREE_INC : tempmon_state_name = "THREE_INC"; TWO_INC : tempmon_state_name = "TWO_INC"; ONE_INC : tempmon_state_name = "ONE_INC"; NEUTRAL : tempmon_state_name = "NEUTRAL"; ONE_DEC : tempmon_state_name = "ONE_DEC"; TWO_DEC : tempmon_state_name = "TWO_DEC"; THREE_DEC : tempmon_state_name = "THREE_DEC"; FOUR_DEC : tempmon_state_name = "FOUR_DEC"; default : tempmon_state_name = "BAD_STATE"; endcase //synopsys translate_on //=========================================================================== // Generate final output and implement flops //=========================================================================== // Generate output assign tempmon_pi_f_inc = pi_f_inc; assign tempmon_pi_f_dec = pi_f_dec; assign tempmon_sel_pi_incdec = pi_f_inc | pi_f_dec; // Implement reset flops always @(posedge clk) begin if(rst) begin tempmon_state <= #TCQ 11'b000_0000_0001; pi_f_inc <= #TCQ 1'b0; pi_f_dec <= #TCQ 1'b0; four_inc_max_limit <= #TCQ 12'b0; three_inc_max_limit <= #TCQ 12'b0; two_inc_max_limit <= #TCQ 12'b0; one_inc_max_limit <= #TCQ 12'b0; neutral_max_limit <= #TCQ 12'b0; one_dec_max_limit <= #TCQ 12'b0; two_dec_max_limit <= #TCQ 12'b0; three_dec_max_limit <= #TCQ 12'b0; three_inc_min_limit <= #TCQ 12'b0; two_inc_min_limit <= #TCQ 12'b0; one_inc_min_limit <= #TCQ 12'b0; neutral_min_limit <= #TCQ 12'b0; one_dec_min_limit <= #TCQ 12'b0; two_dec_min_limit <= #TCQ 12'b0; three_dec_min_limit <= #TCQ 12'b0; four_dec_min_limit <= #TCQ 12'b0; device_temp_init <= #TCQ 12'b0; tempmon_init_complete <= #TCQ 1'b0; tempmon_sample_en_101 <= #TCQ 1'b0; tempmon_sample_en_102 <= #TCQ 1'b0; device_temp_101 <= #TCQ 12'b0; device_temp_capture_102 <= #TCQ 12'b0; end else begin tempmon_state <= #TCQ tempmon_state_nxt; pi_f_inc <= #TCQ pi_f_inc_nxt; pi_f_dec <= #TCQ pi_f_dec_nxt; four_inc_max_limit <= #TCQ four_inc_max_limit_nxt; three_inc_max_limit <= #TCQ three_inc_max_limit_nxt; two_inc_max_limit <= #TCQ two_inc_max_limit_nxt; one_inc_max_limit <= #TCQ one_inc_max_limit_nxt; neutral_max_limit <= #TCQ neutral_max_limit_nxt; one_dec_max_limit <= #TCQ one_dec_max_limit_nxt; two_dec_max_limit <= #TCQ two_dec_max_limit_nxt; three_dec_max_limit <= #TCQ three_dec_max_limit_nxt; three_inc_min_limit <= #TCQ three_inc_min_limit_nxt; two_inc_min_limit <= #TCQ two_inc_min_limit_nxt; one_inc_min_limit <= #TCQ one_inc_min_limit_nxt; neutral_min_limit <= #TCQ neutral_min_limit_nxt; one_dec_min_limit <= #TCQ one_dec_min_limit_nxt; two_dec_min_limit <= #TCQ two_dec_min_limit_nxt; three_dec_min_limit <= #TCQ three_dec_min_limit_nxt; four_dec_min_limit <= #TCQ four_dec_min_limit_nxt; device_temp_init <= #TCQ device_temp_init_nxt; tempmon_init_complete <= #TCQ tempmon_init_complete_nxt; tempmon_sample_en_101 <= #TCQ tempmon_sample_en; tempmon_sample_en_102 <= #TCQ tempmon_sample_en_101; device_temp_101 <= #TCQ device_temp_100; device_temp_capture_102 <= #TCQ device_temp_capture_101; end end // Implement non-reset flops always @(posedge clk) begin temp_cmp_four_inc_max_102 <= #TCQ temp_cmp_four_inc_max_101; temp_cmp_three_inc_max_102 <= #TCQ temp_cmp_three_inc_max_101; temp_cmp_two_inc_max_102 <= #TCQ temp_cmp_two_inc_max_101; temp_cmp_one_inc_max_102 <= #TCQ temp_cmp_one_inc_max_101; temp_cmp_neutral_max_102 <= #TCQ temp_cmp_neutral_max_101; temp_cmp_one_dec_max_102 <= #TCQ temp_cmp_one_dec_max_101; temp_cmp_two_dec_max_102 <= #TCQ temp_cmp_two_dec_max_101; temp_cmp_three_dec_max_102 <= #TCQ temp_cmp_three_dec_max_101; temp_cmp_three_inc_min_102 <= #TCQ temp_cmp_three_inc_min_101; temp_cmp_two_inc_min_102 <= #TCQ temp_cmp_two_inc_min_101; temp_cmp_one_inc_min_102 <= #TCQ temp_cmp_one_inc_min_101; temp_cmp_neutral_min_102 <= #TCQ temp_cmp_neutral_min_101; temp_cmp_one_dec_min_102 <= #TCQ temp_cmp_one_dec_min_101; temp_cmp_two_dec_min_102 <= #TCQ temp_cmp_two_dec_min_101; temp_cmp_three_dec_min_102 <= #TCQ temp_cmp_three_dec_min_101; temp_cmp_four_dec_min_102 <= #TCQ temp_cmp_four_dec_min_101; update_temp_102 <= #TCQ update_temp_101; end endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : mig_7series_v2_3_ddr_phy_tempmon.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Dec 20 2013 // \___\/\___\ // //Device : 7 Series //Design Name : DDR3 SDRAM //Purpose : Monitors chip temperature via the XADC and adjusts the // stage 2 tap values as appropriate. //Reference : //Revision History : //***************************************************************************** `timescale 1 ps / 1 ps module mig_7series_v2_3_ddr_phy_tempmon # ( parameter TCQ = 100, // Register delay (simulation only) // Temperature bands must be in order. To disable bands, set to extreme. parameter TEMP_INCDEC = 1465, // Degrees C * 100 (14.65 * 100) parameter TEMP_HYST = 1, parameter TEMP_MIN_LIMIT = 12'h8ac, parameter TEMP_MAX_LIMIT = 12'hca4 ) ( input clk, // Fabric clock input rst, // System reset input calib_complete, // Calibration complete input tempmon_sample_en, // Signal to enable sampling input [11:0] device_temp, // Current device temperature output tempmon_pi_f_inc, // Increment PHASER_IN taps output tempmon_pi_f_dec, // Decrement PHASER_IN taps output tempmon_sel_pi_incdec // Assume control of PHASER_IN taps ); // translate hysteresis into XADC units localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504; localparam TEMP_INCDEC_OFFSET = ((TEMP_INCDEC * 4096) / 50400) ; // Temperature sampler FSM encoding localparam IDLE = 11'b000_0000_0001; localparam INIT = 11'b000_0000_0010; localparam FOUR_INC = 11'b000_0000_0100; localparam THREE_INC = 11'b000_0000_1000; localparam TWO_INC = 11'b000_0001_0000; localparam ONE_INC = 11'b000_0010_0000; localparam NEUTRAL = 11'b000_0100_0000; localparam ONE_DEC = 11'b000_1000_0000; localparam TWO_DEC = 11'b001_0000_0000; localparam THREE_DEC = 11'b010_0000_0000; localparam FOUR_DEC = 11'b100_0000_0000; //=========================================================================== // Reg declarations //=========================================================================== // Output port flops. Inc and dec are mutex. reg pi_f_dec; // Flop output reg pi_f_inc; // Flop output reg pi_f_dec_nxt; // FSM output reg pi_f_inc_nxt; // FSM output // FSM state reg [10:0] tempmon_state; reg [10:0] tempmon_state_nxt; // FSM output used to capture the initial device termperature reg tempmon_state_init; // Flag to indicate the initial device temperature is captured and normal operation can begin reg tempmon_init_complete; // Temperature band/state boundaries reg [11:0] four_inc_max_limit; reg [11:0] three_inc_max_limit; reg [11:0] two_inc_max_limit; reg [11:0] one_inc_max_limit; reg [11:0] neutral_max_limit; reg [11:0] one_dec_max_limit; reg [11:0] two_dec_max_limit; reg [11:0] three_dec_max_limit; reg [11:0] three_inc_min_limit; reg [11:0] two_inc_min_limit; reg [11:0] one_inc_min_limit; reg [11:0] neutral_min_limit; reg [11:0] one_dec_min_limit; reg [11:0] two_dec_min_limit; reg [11:0] three_dec_min_limit; reg [11:0] four_dec_min_limit; reg [11:0] device_temp_init; // Flops for capturing and storing the current device temperature reg tempmon_sample_en_101; reg tempmon_sample_en_102; reg [11:0] device_temp_101; reg [11:0] device_temp_capture_102; reg update_temp_102; // Flops for comparing temperature to max limits reg temp_cmp_four_inc_max_102; reg temp_cmp_three_inc_max_102; reg temp_cmp_two_inc_max_102; reg temp_cmp_one_inc_max_102; reg temp_cmp_neutral_max_102; reg temp_cmp_one_dec_max_102; reg temp_cmp_two_dec_max_102; reg temp_cmp_three_dec_max_102; // Flops for comparing temperature to min limits reg temp_cmp_three_inc_min_102; reg temp_cmp_two_inc_min_102; reg temp_cmp_one_inc_min_102; reg temp_cmp_neutral_min_102; reg temp_cmp_one_dec_min_102; reg temp_cmp_two_dec_min_102; reg temp_cmp_three_dec_min_102; reg temp_cmp_four_dec_min_102; //=========================================================================== // Overview and temperature band limits //=========================================================================== // The main feature of the tempmon block is an FSM that tracks the temerature provided by the ADC and decides if the phaser needs to be adjusted. The FSM // has nine temperature bands or states, centered around an initial device temperature. The name of each state is the net number of phaser increments or // decrements that have been issued in getting to the state. There are two temperature boundaries or limits between adjacent states. These two boundaries are // offset by a small amount to provide hysteresis. The max limits are the boundaries that are used to determine when to move to the next higher temperature state // and decrement the phaser. The min limits determine when to move to the next lower temperature state and increment the phaser. The limits are calculated when // the initial device temperature is taken, and will always be at fixed offsets from the initial device temperature. States with limits below 0C or above // 125C will never be entered. // Temperature lowest highest // <------------------------------------------------------------------------------------------------------------------------------------------------> // // Temp four three two one neutral one two three four // band/state inc inc inc inc dec dec dec dec // // Max limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| // Min limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| | // | | | | | | | // | | | | | | | // three_inc_min_limit | HYST_OFFSET--->| |<-- | four_dec_min_limit | // | device_temp_init | // four_inc_max_limit three_dec_max_limit // Boundaries for moving from lower temp bands to higher temp bands. // Note that only three_dec_max_limit can roll over, assuming device_temp_init is between 0C and 125C and TEMP_INCDEC_OFFSET is 14.65C, // and none of the min or max limits can roll under. So three_dec_max_limit has a check for being out of the 0x0 to 0xFFF range. wire [11:0] four_inc_max_limit_nxt = device_temp_init - 7*TEMP_INCDEC_OFFSET; // upper boundary of lowest temp band wire [11:0] three_inc_max_limit_nxt = device_temp_init - 5*TEMP_INCDEC_OFFSET; wire [11:0] two_inc_max_limit_nxt = device_temp_init - 3*TEMP_INCDEC_OFFSET; wire [11:0] one_inc_max_limit_nxt = device_temp_init - TEMP_INCDEC_OFFSET; wire [11:0] neutral_max_limit_nxt = device_temp_init + TEMP_INCDEC_OFFSET; // upper boundary of init temp band wire [11:0] one_dec_max_limit_nxt = device_temp_init + 3*TEMP_INCDEC_OFFSET; wire [11:0] two_dec_max_limit_nxt = device_temp_init + 5*TEMP_INCDEC_OFFSET; wire [12:0] three_dec_max_limit_tmp = device_temp_init + 7*TEMP_INCDEC_OFFSET; // upper boundary of 2nd highest temp band wire [11:0] three_dec_max_limit_nxt = three_dec_max_limit_tmp[12] ? 12'hFFF : three_dec_max_limit_tmp[11:0]; // Boundaries for moving from higher temp bands to lower temp bands wire [11:0] three_inc_min_limit_nxt = four_inc_max_limit - HYST_OFFSET; // lower boundary of 2nd lowest temp band wire [11:0] two_inc_min_limit_nxt = three_inc_max_limit - HYST_OFFSET; wire [11:0] one_inc_min_limit_nxt = two_inc_max_limit - HYST_OFFSET; wire [11:0] neutral_min_limit_nxt = one_inc_max_limit - HYST_OFFSET; // lower boundary of init temp band wire [11:0] one_dec_min_limit_nxt = neutral_max_limit - HYST_OFFSET; wire [11:0] two_dec_min_limit_nxt = one_dec_max_limit - HYST_OFFSET; wire [11:0] three_dec_min_limit_nxt = two_dec_max_limit - HYST_OFFSET; wire [11:0] four_dec_min_limit_nxt = three_dec_max_limit - HYST_OFFSET; // lower boundary of highest temp band //=========================================================================== // Capture device temperature //=========================================================================== // There is a three stage pipeline used to capture temperature, calculate the next state // of the FSM, and update the tempmon outputs. // // Stage 100 Inputs device_temp and tempmon_sample_en become valid and are flopped. // Input device_temp is compared to ADC codes for 0C and 125C and limited // at the flop input if needed. // // Stage 101 The flopped version of device_temp is compared to the FSM temperature band boundaries // to determine if a state change is needed. State changes are only enabled on the // rising edge of the flopped tempmon_sample_en signal. If there is a state change a phaser // increment or decrement signal is generated and flopped. // // Stage 102 The flopped versions of the phaser inc/dec signals drive the module outputs. // Limit device_temp to 0C to 125C and assign it to flop input device_temp_100 // temp C = ( ( ADC CODE * 503.975 ) / 4096 ) - 273.15 wire device_temp_high = device_temp > TEMP_MAX_LIMIT; wire device_temp_low = device_temp < TEMP_MIN_LIMIT; wire [11:0] device_temp_100 = ( { 12 { device_temp_high } } & TEMP_MAX_LIMIT ) | ( { 12 { device_temp_low } } & TEMP_MIN_LIMIT ) | ( { 12 { ~device_temp_high & ~device_temp_low } } & device_temp ); // Capture/hold the initial temperature used in setting temperature bands and set init complete flag // to enable normal sample operation. wire [11:0] device_temp_init_nxt = tempmon_state_init ? device_temp_101 : device_temp_init; wire tempmon_init_complete_nxt = tempmon_state_init ? 1'b1 : tempmon_init_complete; // Capture/hold the current temperature on the sample enable signal rising edge after init is complete. // The captured current temp is not used functionaly. It is just useful for debug and waveform review. wire update_temp_101 = tempmon_init_complete & ~tempmon_sample_en_102 & tempmon_sample_en_101; wire [11:0] device_temp_capture_101 = update_temp_101 ? device_temp_101 : device_temp_capture_102; //=========================================================================== // Generate FSM arc signals //=========================================================================== // Temperature comparisons for increasing temperature. wire temp_cmp_four_inc_max_101 = device_temp_101 >= four_inc_max_limit ; wire temp_cmp_three_inc_max_101 = device_temp_101 >= three_inc_max_limit ; wire temp_cmp_two_inc_max_101 = device_temp_101 >= two_inc_max_limit ; wire temp_cmp_one_inc_max_101 = device_temp_101 >= one_inc_max_limit ; wire temp_cmp_neutral_max_101 = device_temp_101 >= neutral_max_limit ; wire temp_cmp_one_dec_max_101 = device_temp_101 >= one_dec_max_limit ; wire temp_cmp_two_dec_max_101 = device_temp_101 >= two_dec_max_limit ; wire temp_cmp_three_dec_max_101 = device_temp_101 >= three_dec_max_limit ; // Temperature comparisons for decreasing temperature. wire temp_cmp_three_inc_min_101 = device_temp_101 < three_inc_min_limit ; wire temp_cmp_two_inc_min_101 = device_temp_101 < two_inc_min_limit ; wire temp_cmp_one_inc_min_101 = device_temp_101 < one_inc_min_limit ; wire temp_cmp_neutral_min_101 = device_temp_101 < neutral_min_limit ; wire temp_cmp_one_dec_min_101 = device_temp_101 < one_dec_min_limit ; wire temp_cmp_two_dec_min_101 = device_temp_101 < two_dec_min_limit ; wire temp_cmp_three_dec_min_101 = device_temp_101 < three_dec_min_limit ; wire temp_cmp_four_dec_min_101 = device_temp_101 < four_dec_min_limit ; // FSM arcs for increasing temperature. wire temp_gte_four_inc_max = update_temp_102 & temp_cmp_four_inc_max_102; wire temp_gte_three_inc_max = update_temp_102 & temp_cmp_three_inc_max_102; wire temp_gte_two_inc_max = update_temp_102 & temp_cmp_two_inc_max_102; wire temp_gte_one_inc_max = update_temp_102 & temp_cmp_one_inc_max_102; wire temp_gte_neutral_max = update_temp_102 & temp_cmp_neutral_max_102; wire temp_gte_one_dec_max = update_temp_102 & temp_cmp_one_dec_max_102; wire temp_gte_two_dec_max = update_temp_102 & temp_cmp_two_dec_max_102; wire temp_gte_three_dec_max = update_temp_102 & temp_cmp_three_dec_max_102; // FSM arcs for decreasing temperature. wire temp_lte_three_inc_min = update_temp_102 & temp_cmp_three_inc_min_102; wire temp_lte_two_inc_min = update_temp_102 & temp_cmp_two_inc_min_102; wire temp_lte_one_inc_min = update_temp_102 & temp_cmp_one_inc_min_102; wire temp_lte_neutral_min = update_temp_102 & temp_cmp_neutral_min_102; wire temp_lte_one_dec_min = update_temp_102 & temp_cmp_one_dec_min_102; wire temp_lte_two_dec_min = update_temp_102 & temp_cmp_two_dec_min_102; wire temp_lte_three_dec_min = update_temp_102 & temp_cmp_three_dec_min_102; wire temp_lte_four_dec_min = update_temp_102 & temp_cmp_four_dec_min_102; //=========================================================================== // Implement FSM //=========================================================================== // In addition to the nine temperature states, there are also IDLE and INIT states. // The INIT state triggers the calculation of the temperature boundaries between the // other states. After INIT, the FSM will always go to the NEUTRAL state. There is // no timing restriction required between calib_complete and tempmon_sample_en. always @(*) begin tempmon_state_nxt = tempmon_state; tempmon_state_init = 1'b0; pi_f_inc_nxt = 1'b0; pi_f_dec_nxt = 1'b0; casez (tempmon_state) IDLE: begin if (calib_complete) tempmon_state_nxt = INIT; end INIT: begin tempmon_state_nxt = NEUTRAL; tempmon_state_init = 1'b1; end FOUR_INC: begin if (temp_gte_four_inc_max) begin tempmon_state_nxt = THREE_INC; pi_f_dec_nxt = 1'b1; end end THREE_INC: begin if (temp_gte_three_inc_max) begin tempmon_state_nxt = TWO_INC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_three_inc_min) begin tempmon_state_nxt = FOUR_INC; pi_f_inc_nxt = 1'b1; end end TWO_INC: begin if (temp_gte_two_inc_max) begin tempmon_state_nxt = ONE_INC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_two_inc_min) begin tempmon_state_nxt = THREE_INC; pi_f_inc_nxt = 1'b1; end end ONE_INC: begin if (temp_gte_one_inc_max) begin tempmon_state_nxt = NEUTRAL; pi_f_dec_nxt = 1'b1; end else if (temp_lte_one_inc_min) begin tempmon_state_nxt = TWO_INC; pi_f_inc_nxt = 1'b1; end end NEUTRAL: begin if (temp_gte_neutral_max) begin tempmon_state_nxt = ONE_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_neutral_min) begin tempmon_state_nxt = ONE_INC; pi_f_inc_nxt = 1'b1; end end ONE_DEC: begin if (temp_gte_one_dec_max) begin tempmon_state_nxt = TWO_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_one_dec_min) begin tempmon_state_nxt = NEUTRAL; pi_f_inc_nxt = 1'b1; end end TWO_DEC: begin if (temp_gte_two_dec_max) begin tempmon_state_nxt = THREE_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_two_dec_min) begin tempmon_state_nxt = ONE_DEC; pi_f_inc_nxt = 1'b1; end end THREE_DEC: begin if (temp_gte_three_dec_max) begin tempmon_state_nxt = FOUR_DEC; pi_f_dec_nxt = 1'b1; end else if (temp_lte_three_dec_min) begin tempmon_state_nxt = TWO_DEC; pi_f_inc_nxt = 1'b1; end end FOUR_DEC: begin if (temp_lte_four_dec_min) begin tempmon_state_nxt = THREE_DEC; pi_f_inc_nxt = 1'b1; end end default: begin tempmon_state_nxt = IDLE; end endcase end //always //synopsys translate_off reg [71:0] tempmon_state_name; always @(*) casez (tempmon_state) IDLE : tempmon_state_name = "IDLE"; INIT : tempmon_state_name = "INIT"; FOUR_INC : tempmon_state_name = "FOUR_INC"; THREE_INC : tempmon_state_name = "THREE_INC"; TWO_INC : tempmon_state_name = "TWO_INC"; ONE_INC : tempmon_state_name = "ONE_INC"; NEUTRAL : tempmon_state_name = "NEUTRAL"; ONE_DEC : tempmon_state_name = "ONE_DEC"; TWO_DEC : tempmon_state_name = "TWO_DEC"; THREE_DEC : tempmon_state_name = "THREE_DEC"; FOUR_DEC : tempmon_state_name = "FOUR_DEC"; default : tempmon_state_name = "BAD_STATE"; endcase //synopsys translate_on //=========================================================================== // Generate final output and implement flops //=========================================================================== // Generate output assign tempmon_pi_f_inc = pi_f_inc; assign tempmon_pi_f_dec = pi_f_dec; assign tempmon_sel_pi_incdec = pi_f_inc | pi_f_dec; // Implement reset flops always @(posedge clk) begin if(rst) begin tempmon_state <= #TCQ 11'b000_0000_0001; pi_f_inc <= #TCQ 1'b0; pi_f_dec <= #TCQ 1'b0; four_inc_max_limit <= #TCQ 12'b0; three_inc_max_limit <= #TCQ 12'b0; two_inc_max_limit <= #TCQ 12'b0; one_inc_max_limit <= #TCQ 12'b0; neutral_max_limit <= #TCQ 12'b0; one_dec_max_limit <= #TCQ 12'b0; two_dec_max_limit <= #TCQ 12'b0; three_dec_max_limit <= #TCQ 12'b0; three_inc_min_limit <= #TCQ 12'b0; two_inc_min_limit <= #TCQ 12'b0; one_inc_min_limit <= #TCQ 12'b0; neutral_min_limit <= #TCQ 12'b0; one_dec_min_limit <= #TCQ 12'b0; two_dec_min_limit <= #TCQ 12'b0; three_dec_min_limit <= #TCQ 12'b0; four_dec_min_limit <= #TCQ 12'b0; device_temp_init <= #TCQ 12'b0; tempmon_init_complete <= #TCQ 1'b0; tempmon_sample_en_101 <= #TCQ 1'b0; tempmon_sample_en_102 <= #TCQ 1'b0; device_temp_101 <= #TCQ 12'b0; device_temp_capture_102 <= #TCQ 12'b0; end else begin tempmon_state <= #TCQ tempmon_state_nxt; pi_f_inc <= #TCQ pi_f_inc_nxt; pi_f_dec <= #TCQ pi_f_dec_nxt; four_inc_max_limit <= #TCQ four_inc_max_limit_nxt; three_inc_max_limit <= #TCQ three_inc_max_limit_nxt; two_inc_max_limit <= #TCQ two_inc_max_limit_nxt; one_inc_max_limit <= #TCQ one_inc_max_limit_nxt; neutral_max_limit <= #TCQ neutral_max_limit_nxt; one_dec_max_limit <= #TCQ one_dec_max_limit_nxt; two_dec_max_limit <= #TCQ two_dec_max_limit_nxt; three_dec_max_limit <= #TCQ three_dec_max_limit_nxt; three_inc_min_limit <= #TCQ three_inc_min_limit_nxt; two_inc_min_limit <= #TCQ two_inc_min_limit_nxt; one_inc_min_limit <= #TCQ one_inc_min_limit_nxt; neutral_min_limit <= #TCQ neutral_min_limit_nxt; one_dec_min_limit <= #TCQ one_dec_min_limit_nxt; two_dec_min_limit <= #TCQ two_dec_min_limit_nxt; three_dec_min_limit <= #TCQ three_dec_min_limit_nxt; four_dec_min_limit <= #TCQ four_dec_min_limit_nxt; device_temp_init <= #TCQ device_temp_init_nxt; tempmon_init_complete <= #TCQ tempmon_init_complete_nxt; tempmon_sample_en_101 <= #TCQ tempmon_sample_en; tempmon_sample_en_102 <= #TCQ tempmon_sample_en_101; device_temp_101 <= #TCQ device_temp_100; device_temp_capture_102 <= #TCQ device_temp_capture_101; end end // Implement non-reset flops always @(posedge clk) begin temp_cmp_four_inc_max_102 <= #TCQ temp_cmp_four_inc_max_101; temp_cmp_three_inc_max_102 <= #TCQ temp_cmp_three_inc_max_101; temp_cmp_two_inc_max_102 <= #TCQ temp_cmp_two_inc_max_101; temp_cmp_one_inc_max_102 <= #TCQ temp_cmp_one_inc_max_101; temp_cmp_neutral_max_102 <= #TCQ temp_cmp_neutral_max_101; temp_cmp_one_dec_max_102 <= #TCQ temp_cmp_one_dec_max_101; temp_cmp_two_dec_max_102 <= #TCQ temp_cmp_two_dec_max_101; temp_cmp_three_dec_max_102 <= #TCQ temp_cmp_three_dec_max_101; temp_cmp_three_inc_min_102 <= #TCQ temp_cmp_three_inc_min_101; temp_cmp_two_inc_min_102 <= #TCQ temp_cmp_two_inc_min_101; temp_cmp_one_inc_min_102 <= #TCQ temp_cmp_one_inc_min_101; temp_cmp_neutral_min_102 <= #TCQ temp_cmp_neutral_min_101; temp_cmp_one_dec_min_102 <= #TCQ temp_cmp_one_dec_min_101; temp_cmp_two_dec_min_102 <= #TCQ temp_cmp_two_dec_min_101; temp_cmp_three_dec_min_102 <= #TCQ temp_cmp_three_dec_min_101; temp_cmp_four_dec_min_102 <= #TCQ temp_cmp_four_dec_min_101; update_temp_102 <= #TCQ update_temp_101; end endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: infrastructure.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ // \ \ / \ Date Created:Tue Jun 30 2009 // \___\/\___\ // //Device: Virtex-6 //Design Name: DDR3 SDRAM //Purpose: // Clock generation/distribution and reset synchronization //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: infrastructure.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ **$Date: 2011/06/02 08:34:56 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/infrastructure.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_infrastructure # ( parameter SIMULATION = "FALSE", // Should be TRUE during design simulations and // FALSE during implementations parameter TCQ = 100, // clk->out delay (sim only) parameter CLKIN_PERIOD = 3000, // Memory clock period parameter nCK_PER_CLK = 2, // Fabric clk period:Memory clk period parameter SYSCLK_TYPE = "DIFFERENTIAL", // input clock type // "DIFFERENTIAL","SINGLE_ENDED" parameter UI_EXTRA_CLOCKS = "FALSE", // Generates extra clocks as // 1/2, 1/4 and 1/8 of fabrick clock. // Valid for DDR2/DDR3 AXI interfaces // based on GUI selection parameter CLKFBOUT_MULT = 4, // write PLL VCO multiplier parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor parameter CLKOUT0_PHASE = 45.0, // VCO output divisor for clkout0 parameter CLKOUT0_DIVIDE = 16, // VCO output divisor for PLL clkout0 parameter CLKOUT1_DIVIDE = 4, // VCO output divisor for PLL clkout1 parameter CLKOUT2_DIVIDE = 64, // VCO output divisor for PLL clkout2 parameter CLKOUT3_DIVIDE = 16, // VCO output divisor for PLL clkout3 parameter MMCM_VCO = 1200, // Max Freq (MHz) of MMCM VCO parameter MMCM_MULT_F = 4, // write MMCM VCO multiplier parameter MMCM_DIVCLK_DIVIDE = 1, // write MMCM VCO divisor parameter MMCM_CLKOUT0_EN = "FALSE", // Enabled (or) Disable MMCM clkout0 parameter MMCM_CLKOUT1_EN = "FALSE", // Enabled (or) Disable MMCM clkout1 parameter MMCM_CLKOUT2_EN = "FALSE", // Enabled (or) Disable MMCM clkout2 parameter MMCM_CLKOUT3_EN = "FALSE", // Enabled (or) Disable MMCM clkout3 parameter MMCM_CLKOUT4_EN = "FALSE", // Enabled (or) Disable MMCM clkout4 parameter MMCM_CLKOUT0_DIVIDE = 1, // VCO output divisor for MMCM clkout0 parameter MMCM_CLKOUT1_DIVIDE = 1, // VCO output divisor for MMCM clkout1 parameter MMCM_CLKOUT2_DIVIDE = 1, // VCO output divisor for MMCM clkout2 parameter MMCM_CLKOUT3_DIVIDE = 1, // VCO output divisor for MMCM clkout3 parameter MMCM_CLKOUT4_DIVIDE = 1, // VCO output divisor for MMCM clkout4 parameter RST_ACT_LOW = 1, parameter tCK = 1250, // memory tCK paramter. // # = Clock Period in pS. parameter MEM_TYPE = "DDR3" ) ( // Clock inputs input mmcm_clk, // System clock diff input // System reset input input sys_rst, // core reset from user application // PLLE2/IDELAYCTRL Lock status input [1:0] iodelay_ctrl_rdy, // IDELAYCTRL lock status // Clock outputs output clk, // fabric clock freq ; either half rate or quarter rate and is // determined by PLL parameters settings. output mem_refclk, // equal to memory clock output freq_refclk, // freq above 400 MHz: set freq_refclk = mem_refclk // freq below 400 MHz: set freq_refclk = 2* mem_refclk or 4* mem_refclk; // to hard PHY for phaser output sync_pulse, // exactly 1/16 of mem_refclk and the sync pulse is exactly 1 memref_clk wide output auxout_clk, // IO clk used to clock out Aux_Out ports output mmcm_ps_clk, // Phase shift clock output poc_sample_pd, // Tell POC when to sample phase detector output. output ui_addn_clk_0, // MMCM out0 clk output ui_addn_clk_1, // MMCM out1 clk output ui_addn_clk_2, // MMCM out2 clk output ui_addn_clk_3, // MMCM out3 clk output ui_addn_clk_4, // MMCM out4 clk output pll_locked, // locked output from PLLE2_ADV output mmcm_locked, // locked output from MMCME2_ADV // Reset outputs output rstdiv0, // Reset CLK and CLKDIV logic (incl I/O), output iddr_rst ,output rst_phaser_ref ,input ref_dll_lock ,input psen ,input psincdec ,output psdone ); // # of clock cycles to delay deassertion of reset. Needs to be a fairly // high number not so much for metastability protection, but to give time // for reset (i.e. stable clock cycles) to propagate through all state // machines and to all control signals (i.e. not all control signals have // resets, instead they rely on base state logic being reset, and the effect // of that reset propagating through the logic). Need this because we may not // be getting stable clock cycles while reset asserted (i.e. since reset // depends on DCM lock status) localparam RST_SYNC_NUM = 25; // Round up for clk reset delay to ensure that CLKDIV reset deassertion // occurs at same time or after CLK reset deassertion (still need to // consider route delay - add one or two extra cycles to be sure!) localparam RST_DIV_SYNC_NUM = (RST_SYNC_NUM+1)/2; // Input clock is assumed to be equal to the memory clock frequency // User should change the parameter as necessary if a different input // clock frequency is used localparam real CLKIN1_PERIOD_NS = CLKIN_PERIOD / 1000.0; localparam CLKOUT4_DIVIDE = 2 * CLKOUT1_DIVIDE; localparam integer VCO_PERIOD = (CLKIN1_PERIOD_NS * DIVCLK_DIVIDE * 1000) / CLKFBOUT_MULT; localparam CLKOUT0_PERIOD = VCO_PERIOD * CLKOUT0_DIVIDE; localparam CLKOUT1_PERIOD = VCO_PERIOD * CLKOUT1_DIVIDE; localparam CLKOUT2_PERIOD = VCO_PERIOD * CLKOUT2_DIVIDE; localparam CLKOUT3_PERIOD = VCO_PERIOD * CLKOUT3_DIVIDE; localparam CLKOUT4_PERIOD = VCO_PERIOD * CLKOUT4_DIVIDE; localparam CLKOUT4_PHASE = (SIMULATION == "TRUE") ? 22.5 : 168.75; localparam real CLKOUT3_PERIOD_NS = CLKOUT3_PERIOD / 1000.0; localparam real CLKOUT4_PERIOD_NS = CLKOUT4_PERIOD / 1000.0; //synthesis translate_off initial begin $display("############# Write Clocks PLLE2_ADV Parameters #############\n"); $display("nCK_PER_CLK = %7d", nCK_PER_CLK ); $display("CLK_PERIOD = %7d", CLKIN_PERIOD ); $display("CLKIN1_PERIOD = %7.3f", CLKIN1_PERIOD_NS); $display("DIVCLK_DIVIDE = %7d", DIVCLK_DIVIDE ); $display("CLKFBOUT_MULT = %7d", CLKFBOUT_MULT ); $display("VCO_PERIOD = %7.1f", VCO_PERIOD ); $display("CLKOUT0_DIVIDE_F = %7d", CLKOUT0_DIVIDE ); $display("CLKOUT1_DIVIDE = %7d", CLKOUT1_DIVIDE ); $display("CLKOUT2_DIVIDE = %7d", CLKOUT2_DIVIDE ); $display("CLKOUT3_DIVIDE = %7d", CLKOUT3_DIVIDE ); $display("CLKOUT0_PERIOD = %7d", CLKOUT0_PERIOD ); $display("CLKOUT1_PERIOD = %7d", CLKOUT1_PERIOD ); $display("CLKOUT2_PERIOD = %7d", CLKOUT2_PERIOD ); $display("CLKOUT3_PERIOD = %7d", CLKOUT3_PERIOD ); $display("CLKOUT4_PERIOD = %7d", CLKOUT4_PERIOD ); $display("############################################################\n"); end //synthesis translate_on wire clk_bufg; wire clk_pll; wire clkfbout_pll; wire mmcm_clkfbout; wire pll_locked_i /* synthesis syn_maxfan = 10 */; (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-2:0] rstdiv0_sync_r; wire rst_tmp; (* max_fanout = 50 *) reg rstdiv0_sync_r1 /* synthesis syn_maxfan = 50 */; reg [RST_DIV_SYNC_NUM-2:0] rst_sync_r; (* max_fanout = 10 *) reg rst_sync_r1 /* synthesis syn_maxfan = 10 */; wire sys_rst_act_hi; wire rst_tmp_phaser_ref; (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-1:0] rst_phaser_ref_sync_r /* synthesis syn_maxfan = 10 */; // Instantiation of the MMCM primitive wire clkfbout; wire MMCM_Locked_i; wire mmcm_clkout0; wire mmcm_clkout1; wire mmcm_clkout2; wire mmcm_clkout3; wire mmcm_clkout4; wire mmcm_ps_clk_bufg_in; wire pll_clk3_out; wire pll_clk3; assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst; //*************************************************************************** // Assign global clocks: // 2. clk : Half rate / Quarter rate(used for majority of internal logic) //*************************************************************************** assign clk = clk_bufg; assign pll_locked = pll_locked_i & MMCM_Locked_i; assign mmcm_locked = MMCM_Locked_i; //*************************************************************************** // Global base clock generation and distribution //*************************************************************************** //***************************************************************** // NOTES ON CALCULTING PROPER VCO FREQUENCY // 1. VCO frequency = // 1/((DIVCLK_DIVIDE * CLKIN_PERIOD)/(CLKFBOUT_MULT * nCK_PER_CLK)) // 2. VCO frequency must be in the range [TBD, TBD] //***************************************************************** PLLE2_ADV # ( .BANDWIDTH ("OPTIMIZED"), .COMPENSATION ("INTERNAL"), .STARTUP_WAIT ("FALSE"), .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), // 4 freq_ref .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), // 4 mem_ref .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), // 16 sync .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), // 16 sysclk .CLKOUT4_DIVIDE (CLKOUT4_DIVIDE), .CLKOUT5_DIVIDE (), .DIVCLK_DIVIDE (DIVCLK_DIVIDE), .CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_PHASE (0.000), .CLKIN1_PERIOD (CLKIN1_PERIOD_NS), .CLKIN2_PERIOD (), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_PHASE (CLKOUT0_PHASE), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_PHASE (0.000), .CLKOUT2_DUTY_CYCLE (1.0/16.0), .CLKOUT2_PHASE (9.84375), // PHASE shift is required for sync pulse generation. .CLKOUT3_DUTY_CYCLE (0.500), .CLKOUT3_PHASE (0.000), .CLKOUT4_DUTY_CYCLE (0.500), .CLKOUT4_PHASE (CLKOUT4_PHASE), .CLKOUT5_DUTY_CYCLE (0.500), .CLKOUT5_PHASE (0.000), .REF_JITTER1 (0.010), .REF_JITTER2 (0.010) ) plle2_i ( .CLKFBOUT (pll_clkfbout), .CLKOUT0 (freq_refclk), .CLKOUT1 (mem_refclk), .CLKOUT2 (sync_pulse), // always 1/16 of mem_ref_clk .CLKOUT3 (pll_clk3_out), .CLKOUT4 (auxout_clk_i), .CLKOUT5 (), .DO (), .DRDY (), .LOCKED (pll_locked_i), .CLKFBIN (pll_clkfbout), .CLKIN1 (mmcm_clk), .CLKIN2 (), .CLKINSEL (1'b1), .DADDR (7'b0), .DCLK (1'b0), .DEN (1'b0), .DI (16'b0), .DWE (1'b0), .PWRDWN (1'b0), .RST ( sys_rst_act_hi) ); BUFH u_bufh_auxout_clk ( .O (auxout_clk), .I (auxout_clk_i) ); BUFG u_bufg_clkdiv0 ( .O (clk_bufg), .I (clk_pll_i) ); BUFH u_bufh_pll_clk3 ( .O (pll_clk3), .I (pll_clk3_out) ); localparam real MMCM_VCO_PERIOD = 1000000.0/MMCM_VCO; //synthesis translate_off initial begin $display("############# MMCME2_ADV Parameters #############\n"); $display("MMCM_MULT_F = %d", MMCM_MULT_F); $display("MMCM_VCO_FREQ (MHz) = %7.3f", MMCM_VCO*1000.0); $display("MMCM_VCO_PERIOD = %7.3f", MMCM_VCO_PERIOD); $display("#################################################\n"); end //synthesis translate_on generate if (UI_EXTRA_CLOCKS == "TRUE") begin: gen_ui_extra_clocks localparam MMCM_CLKOUT0_DIVIDE_CAL = (MMCM_CLKOUT0_EN == "TRUE") ? MMCM_CLKOUT0_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT1_DIVIDE_CAL = (MMCM_CLKOUT1_EN == "TRUE") ? MMCM_CLKOUT1_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT2_DIVIDE_CAL = (MMCM_CLKOUT2_EN == "TRUE") ? MMCM_CLKOUT2_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT3_DIVIDE_CAL = (MMCM_CLKOUT3_EN == "TRUE") ? MMCM_CLKOUT3_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT4_DIVIDE_CAL = (MMCM_CLKOUT4_EN == "TRUE") ? MMCM_CLKOUT4_DIVIDE : MMCM_MULT_F; MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("BUF_IN"), .STARTUP_WAIT ("FALSE"), // .DIVCLK_DIVIDE (1), .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), .CLKFBOUT_MULT_F (MMCM_MULT_F), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (MMCM_CLKOUT0_DIVIDE_CAL), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), .CLKOUT1_DIVIDE (MMCM_CLKOUT1_DIVIDE_CAL), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKOUT2_DIVIDE (MMCM_CLKOUT2_DIVIDE_CAL), .CLKOUT2_PHASE (0.000), .CLKOUT2_DUTY_CYCLE (0.500), .CLKOUT2_USE_FINE_PS ("FALSE"), .CLKOUT3_DIVIDE (MMCM_CLKOUT3_DIVIDE_CAL), .CLKOUT3_PHASE (0.000), .CLKOUT3_DUTY_CYCLE (0.500), .CLKOUT3_USE_FINE_PS ("FALSE"), .CLKOUT4_DIVIDE (MMCM_CLKOUT4_DIVIDE_CAL), .CLKOUT4_PHASE (0.000), .CLKOUT4_DUTY_CYCLE (0.500), .CLKOUT4_USE_FINE_PS ("FALSE"), .CLKOUT5_DIVIDE (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), .CLKOUT5_PHASE (0.000), .CLKOUT5_DUTY_CYCLE (0.500), .CLKOUT5_USE_FINE_PS ("TRUE"), .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (clk_pll_i), .CLKFBOUTB (), .CLKOUT0 (mmcm_clkout0), .CLKOUT0B (), .CLKOUT1 (mmcm_clkout1), .CLKOUT1B (), .CLKOUT2 (mmcm_clkout2), .CLKOUT2B (), .CLKOUT3 (mmcm_clkout3), .CLKOUT3B (), .CLKOUT4 (mmcm_clkout4), .CLKOUT5 (mmcm_ps_clk_bufg_in), .CLKOUT6 (), // Input clock control .CLKFBIN (clk_bufg), // From BUFH network .CLKIN1 (pll_clk3), // From PLL .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (clk), .PSEN (psen), .PSINCDEC (psincdec), .PSDONE (psdone), // Other control and status signals .LOCKED (MMCM_Locked_i), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (~pll_locked_i)); BUFG u_bufg_ui_addn_clk_0 ( .O (ui_addn_clk_0), .I (mmcm_clkout0) ); BUFG u_bufg_ui_addn_clk_1 ( .O (ui_addn_clk_1), .I (mmcm_clkout1) ); BUFG u_bufg_ui_addn_clk_2 ( .O (ui_addn_clk_2), .I (mmcm_clkout2) ); BUFG u_bufg_ui_addn_clk_3 ( .O (ui_addn_clk_3), .I (mmcm_clkout3) ); BUFG u_bufg_ui_addn_clk_4 ( .O (ui_addn_clk_4), .I (mmcm_clkout4) ); BUFG u_bufg_mmcm_ps_clk ( .O (mmcm_ps_clk), .I (mmcm_ps_clk_bufg_in) ); end else begin: gen_mmcm MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("BUF_IN"), .STARTUP_WAIT ("FALSE"), // .DIVCLK_DIVIDE (1), .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), .CLKFBOUT_MULT_F (MMCM_MULT_F), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("TRUE"), .CLKOUT1_DIVIDE (), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (clk_pll_i), .CLKFBOUTB (), .CLKOUT0 (mmcm_ps_clk_bufg_in), .CLKOUT0B (), .CLKOUT1 (), .CLKOUT1B (), .CLKOUT2 (), .CLKOUT2B (), .CLKOUT3 (), .CLKOUT3B (), .CLKOUT4 (), .CLKOUT5 (), .CLKOUT6 (), // Input clock control .CLKFBIN (clk_bufg), // From BUFH network .CLKIN1 (pll_clk3), // From PLL .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (clk), .PSEN (psen), .PSINCDEC (psincdec), .PSDONE (psdone), // Other control and status signals .LOCKED (MMCM_Locked_i), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (~pll_locked_i)); BUFG u_bufg_mmcm_ps_clk ( .O (mmcm_ps_clk), .I (mmcm_ps_clk_bufg_in) ); end // block: gen_mmcm endgenerate //*************************************************************************** // Generate poc_sample_pd. // // As the phase shift clocks precesses around kclk, it also precesses // around the fabric clock. Noise may be generated as output of the // IDDR is registered into the fabric clock domain. // // The mmcm_ps_clk signal runs at half the rate of the fabric clock. // This means that there are two rising edges of fabric clock per mmcm_ps_clk. // If we can guarantee that the POC uses the data sampled on the second // fabric clock, then we are certain that the setup time to the second // fabric clock is greater than 1 fabric clock cycle. // // To predict when the phase detctor output is from this second edge, we // need to know two things. The initial phase of fabric clock and mmcm_ps_clk // and the number of phase offsets set into the mmcm. The later is a // trivial count of the PSEN signal. // // The former is a bit tricky because latching a clock with a clock is // not well defined. This problem is solved by generating a signal // the goes high on the first rising edge of mmcm_ps_clk. Logic in // the fabric domain can look at this signal and then develop an analog // the mmcm_ps_clk with zero offset. // // This all depends on the timing tools making the timing work when // when the mmcm phase offset is zero. // // poc_sample_pd tells the POC when to sample the phase detector output. // Setup from the IDDR to the fabric clock is always one plus some // fraction of the fabric clock. //*************************************************************************** localparam ONE = 1; localparam integer TAPSPERFCLK = 56 * MMCM_MULT_F; localparam TAPSPERFCLK_MINUS_ONE = TAPSPERFCLK - 1; localparam QCNTR_WIDTH = clogb2(TAPSPERFCLK); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 reg [QCNTR_WIDTH-1:0] qcntr_ns, qcntr_r; always @(posedge clk) qcntr_r <= #TCQ qcntr_ns; reg inv_poc_sample_ns, inv_poc_sample_r; always @(posedge clk) inv_poc_sample_r <= #TCQ inv_poc_sample_ns; always @(*) begin qcntr_ns = qcntr_r; inv_poc_sample_ns = inv_poc_sample_r; if (rstdiv0) begin qcntr_ns = TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0]; inv_poc_sample_ns = 1'b1; end else if (psen) begin if (qcntr_r < TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0]) qcntr_ns = (qcntr_r + ONE[QCNTR_WIDTH-1:0]); else begin qcntr_ns = {QCNTR_WIDTH{1'b0}}; inv_poc_sample_ns = ~inv_poc_sample_r; end end end // Be vewy vewy careful to make sure this path is aligned with the // phase detector out pipeline. reg first_rising_ps_clk_ns, first_rising_ps_clk_r; always @(posedge mmcm_ps_clk) first_rising_ps_clk_r <= #TCQ first_rising_ps_clk_ns; always @(*) first_rising_ps_clk_ns = ~rstdiv0; reg mmcm_hi0_ns, mmcm_hi0_r; always @(posedge clk) mmcm_hi0_r <= #TCQ mmcm_hi0_ns; always @(*) mmcm_hi0_ns = ~first_rising_ps_clk_r || ~mmcm_hi0_r; reg poc_sample_pd_ns, poc_sample_pd_r; always @(*) poc_sample_pd_ns = inv_poc_sample_ns ^ mmcm_hi0_r; always @(posedge clk) poc_sample_pd_r <= #TCQ poc_sample_pd_ns; assign poc_sample_pd = poc_sample_pd_r; //*************************************************************************** // Make sure logic acheives 90 degree setup time from rising mmcm_ps_clk // to the appropriate edge of fabric clock //*************************************************************************** //synthesis translate_off generate if ( tCK <= 2500 ) begin : check_ocal_timing localparam CLK_PERIOD_PS = MMCM_VCO_PERIOD * MMCM_MULT_F; localparam integer CLK_PERIOD_PS_DIV4 = CLK_PERIOD_PS/4; time rising_mmcm_ps_clk; always @(posedge mmcm_ps_clk) rising_mmcm_ps_clk = $time(); time pdiff; // Not used, except in waveform plots. always @(posedge clk) pdiff = $time() - rising_mmcm_ps_clk; end endgenerate //synthesis translate_on //*************************************************************************** // RESET SYNCHRONIZATION DESCRIPTION: // Various resets are generated to ensure that: // 1. All resets are synchronously deasserted with respect to the clock // domain they are interfacing to. There are several different clock // domains - each one will receive a synchronized reset. // 2. The reset deassertion order starts with deassertion of SYS_RST, // followed by deassertion of resets for various parts of the design // (see "RESET ORDER" below) based on the lock status of PLLE2s. // RESET ORDER: // 1. User deasserts SYS_RST // 2. Reset PLLE2 and IDELAYCTRL // 3. Wait for PLLE2 and IDELAYCTRL to lock // 4. Release reset for all I/O primitives and internal logic // OTHER NOTES: // 1. Asynchronously assert reset. This way we can assert reset even if // there is no clock (needed for things like 3-stating output buffers // to prevent initial bus contention). Reset deassertion is synchronous. //*************************************************************************** //***************************************************************** // CLKDIV logic reset //***************************************************************** // Wait for PLLE2 and IDELAYCTRL to lock before releasing reset // current O,25.0 unisim phaser_ref never locks. Need to find out why . generate if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_300_400 assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[1] | ~ref_dll_lock | ~MMCM_Locked_i; end else begin: rst_tmp_200 assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[0] | ~ref_dll_lock | ~MMCM_Locked_i; end endgenerate always @(posedge clk_bufg or posedge rst_tmp) begin if (rst_tmp) begin rstdiv0_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; rstdiv0_sync_r1 <= #TCQ 1'b1 ; end else begin rstdiv0_sync_r <= #TCQ rstdiv0_sync_r << 1; rstdiv0_sync_r1 <= #TCQ rstdiv0_sync_r[RST_DIV_SYNC_NUM-2]; end end assign rstdiv0 = rstdiv0_sync_r1 ; //IDDR rest always @(posedge mmcm_ps_clk or posedge rst_tmp) begin if (rst_tmp) begin rst_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; rst_sync_r1 <= #TCQ 1'b1 ; end else begin rst_sync_r <= #TCQ rst_sync_r << 1; rst_sync_r1 <= #TCQ rst_sync_r[RST_DIV_SYNC_NUM-2]; end end assign iddr_rst = rst_sync_r1 ; generate if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_phaser_ref_300_400 assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[1]; end else begin: rst_tmp_phaser_ref_200 assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[0]; end endgenerate always @(posedge clk_bufg or posedge rst_tmp_phaser_ref) if (rst_tmp_phaser_ref) rst_phaser_ref_sync_r <= #TCQ {RST_DIV_SYNC_NUM{1'b1}}; else rst_phaser_ref_sync_r <= #TCQ rst_phaser_ref_sync_r << 1; assign rst_phaser_ref = rst_phaser_ref_sync_r[RST_DIV_SYNC_NUM-1]; endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: infrastructure.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ // \ \ / \ Date Created:Tue Jun 30 2009 // \___\/\___\ // //Device: Virtex-6 //Design Name: DDR3 SDRAM //Purpose: // Clock generation/distribution and reset synchronization //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: infrastructure.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ **$Date: 2011/06/02 08:34:56 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/infrastructure.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_infrastructure # ( parameter SIMULATION = "FALSE", // Should be TRUE during design simulations and // FALSE during implementations parameter TCQ = 100, // clk->out delay (sim only) parameter CLKIN_PERIOD = 3000, // Memory clock period parameter nCK_PER_CLK = 2, // Fabric clk period:Memory clk period parameter SYSCLK_TYPE = "DIFFERENTIAL", // input clock type // "DIFFERENTIAL","SINGLE_ENDED" parameter UI_EXTRA_CLOCKS = "FALSE", // Generates extra clocks as // 1/2, 1/4 and 1/8 of fabrick clock. // Valid for DDR2/DDR3 AXI interfaces // based on GUI selection parameter CLKFBOUT_MULT = 4, // write PLL VCO multiplier parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor parameter CLKOUT0_PHASE = 45.0, // VCO output divisor for clkout0 parameter CLKOUT0_DIVIDE = 16, // VCO output divisor for PLL clkout0 parameter CLKOUT1_DIVIDE = 4, // VCO output divisor for PLL clkout1 parameter CLKOUT2_DIVIDE = 64, // VCO output divisor for PLL clkout2 parameter CLKOUT3_DIVIDE = 16, // VCO output divisor for PLL clkout3 parameter MMCM_VCO = 1200, // Max Freq (MHz) of MMCM VCO parameter MMCM_MULT_F = 4, // write MMCM VCO multiplier parameter MMCM_DIVCLK_DIVIDE = 1, // write MMCM VCO divisor parameter MMCM_CLKOUT0_EN = "FALSE", // Enabled (or) Disable MMCM clkout0 parameter MMCM_CLKOUT1_EN = "FALSE", // Enabled (or) Disable MMCM clkout1 parameter MMCM_CLKOUT2_EN = "FALSE", // Enabled (or) Disable MMCM clkout2 parameter MMCM_CLKOUT3_EN = "FALSE", // Enabled (or) Disable MMCM clkout3 parameter MMCM_CLKOUT4_EN = "FALSE", // Enabled (or) Disable MMCM clkout4 parameter MMCM_CLKOUT0_DIVIDE = 1, // VCO output divisor for MMCM clkout0 parameter MMCM_CLKOUT1_DIVIDE = 1, // VCO output divisor for MMCM clkout1 parameter MMCM_CLKOUT2_DIVIDE = 1, // VCO output divisor for MMCM clkout2 parameter MMCM_CLKOUT3_DIVIDE = 1, // VCO output divisor for MMCM clkout3 parameter MMCM_CLKOUT4_DIVIDE = 1, // VCO output divisor for MMCM clkout4 parameter RST_ACT_LOW = 1, parameter tCK = 1250, // memory tCK paramter. // # = Clock Period in pS. parameter MEM_TYPE = "DDR3" ) ( // Clock inputs input mmcm_clk, // System clock diff input // System reset input input sys_rst, // core reset from user application // PLLE2/IDELAYCTRL Lock status input [1:0] iodelay_ctrl_rdy, // IDELAYCTRL lock status // Clock outputs output clk, // fabric clock freq ; either half rate or quarter rate and is // determined by PLL parameters settings. output mem_refclk, // equal to memory clock output freq_refclk, // freq above 400 MHz: set freq_refclk = mem_refclk // freq below 400 MHz: set freq_refclk = 2* mem_refclk or 4* mem_refclk; // to hard PHY for phaser output sync_pulse, // exactly 1/16 of mem_refclk and the sync pulse is exactly 1 memref_clk wide output auxout_clk, // IO clk used to clock out Aux_Out ports output mmcm_ps_clk, // Phase shift clock output poc_sample_pd, // Tell POC when to sample phase detector output. output ui_addn_clk_0, // MMCM out0 clk output ui_addn_clk_1, // MMCM out1 clk output ui_addn_clk_2, // MMCM out2 clk output ui_addn_clk_3, // MMCM out3 clk output ui_addn_clk_4, // MMCM out4 clk output pll_locked, // locked output from PLLE2_ADV output mmcm_locked, // locked output from MMCME2_ADV // Reset outputs output rstdiv0, // Reset CLK and CLKDIV logic (incl I/O), output iddr_rst ,output rst_phaser_ref ,input ref_dll_lock ,input psen ,input psincdec ,output psdone ); // # of clock cycles to delay deassertion of reset. Needs to be a fairly // high number not so much for metastability protection, but to give time // for reset (i.e. stable clock cycles) to propagate through all state // machines and to all control signals (i.e. not all control signals have // resets, instead they rely on base state logic being reset, and the effect // of that reset propagating through the logic). Need this because we may not // be getting stable clock cycles while reset asserted (i.e. since reset // depends on DCM lock status) localparam RST_SYNC_NUM = 25; // Round up for clk reset delay to ensure that CLKDIV reset deassertion // occurs at same time or after CLK reset deassertion (still need to // consider route delay - add one or two extra cycles to be sure!) localparam RST_DIV_SYNC_NUM = (RST_SYNC_NUM+1)/2; // Input clock is assumed to be equal to the memory clock frequency // User should change the parameter as necessary if a different input // clock frequency is used localparam real CLKIN1_PERIOD_NS = CLKIN_PERIOD / 1000.0; localparam CLKOUT4_DIVIDE = 2 * CLKOUT1_DIVIDE; localparam integer VCO_PERIOD = (CLKIN1_PERIOD_NS * DIVCLK_DIVIDE * 1000) / CLKFBOUT_MULT; localparam CLKOUT0_PERIOD = VCO_PERIOD * CLKOUT0_DIVIDE; localparam CLKOUT1_PERIOD = VCO_PERIOD * CLKOUT1_DIVIDE; localparam CLKOUT2_PERIOD = VCO_PERIOD * CLKOUT2_DIVIDE; localparam CLKOUT3_PERIOD = VCO_PERIOD * CLKOUT3_DIVIDE; localparam CLKOUT4_PERIOD = VCO_PERIOD * CLKOUT4_DIVIDE; localparam CLKOUT4_PHASE = (SIMULATION == "TRUE") ? 22.5 : 168.75; localparam real CLKOUT3_PERIOD_NS = CLKOUT3_PERIOD / 1000.0; localparam real CLKOUT4_PERIOD_NS = CLKOUT4_PERIOD / 1000.0; //synthesis translate_off initial begin $display("############# Write Clocks PLLE2_ADV Parameters #############\n"); $display("nCK_PER_CLK = %7d", nCK_PER_CLK ); $display("CLK_PERIOD = %7d", CLKIN_PERIOD ); $display("CLKIN1_PERIOD = %7.3f", CLKIN1_PERIOD_NS); $display("DIVCLK_DIVIDE = %7d", DIVCLK_DIVIDE ); $display("CLKFBOUT_MULT = %7d", CLKFBOUT_MULT ); $display("VCO_PERIOD = %7.1f", VCO_PERIOD ); $display("CLKOUT0_DIVIDE_F = %7d", CLKOUT0_DIVIDE ); $display("CLKOUT1_DIVIDE = %7d", CLKOUT1_DIVIDE ); $display("CLKOUT2_DIVIDE = %7d", CLKOUT2_DIVIDE ); $display("CLKOUT3_DIVIDE = %7d", CLKOUT3_DIVIDE ); $display("CLKOUT0_PERIOD = %7d", CLKOUT0_PERIOD ); $display("CLKOUT1_PERIOD = %7d", CLKOUT1_PERIOD ); $display("CLKOUT2_PERIOD = %7d", CLKOUT2_PERIOD ); $display("CLKOUT3_PERIOD = %7d", CLKOUT3_PERIOD ); $display("CLKOUT4_PERIOD = %7d", CLKOUT4_PERIOD ); $display("############################################################\n"); end //synthesis translate_on wire clk_bufg; wire clk_pll; wire clkfbout_pll; wire mmcm_clkfbout; wire pll_locked_i /* synthesis syn_maxfan = 10 */; (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-2:0] rstdiv0_sync_r; wire rst_tmp; (* max_fanout = 50 *) reg rstdiv0_sync_r1 /* synthesis syn_maxfan = 50 */; reg [RST_DIV_SYNC_NUM-2:0] rst_sync_r; (* max_fanout = 10 *) reg rst_sync_r1 /* synthesis syn_maxfan = 10 */; wire sys_rst_act_hi; wire rst_tmp_phaser_ref; (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-1:0] rst_phaser_ref_sync_r /* synthesis syn_maxfan = 10 */; // Instantiation of the MMCM primitive wire clkfbout; wire MMCM_Locked_i; wire mmcm_clkout0; wire mmcm_clkout1; wire mmcm_clkout2; wire mmcm_clkout3; wire mmcm_clkout4; wire mmcm_ps_clk_bufg_in; wire pll_clk3_out; wire pll_clk3; assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst; //*************************************************************************** // Assign global clocks: // 2. clk : Half rate / Quarter rate(used for majority of internal logic) //*************************************************************************** assign clk = clk_bufg; assign pll_locked = pll_locked_i & MMCM_Locked_i; assign mmcm_locked = MMCM_Locked_i; //*************************************************************************** // Global base clock generation and distribution //*************************************************************************** //***************************************************************** // NOTES ON CALCULTING PROPER VCO FREQUENCY // 1. VCO frequency = // 1/((DIVCLK_DIVIDE * CLKIN_PERIOD)/(CLKFBOUT_MULT * nCK_PER_CLK)) // 2. VCO frequency must be in the range [TBD, TBD] //***************************************************************** PLLE2_ADV # ( .BANDWIDTH ("OPTIMIZED"), .COMPENSATION ("INTERNAL"), .STARTUP_WAIT ("FALSE"), .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), // 4 freq_ref .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), // 4 mem_ref .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), // 16 sync .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), // 16 sysclk .CLKOUT4_DIVIDE (CLKOUT4_DIVIDE), .CLKOUT5_DIVIDE (), .DIVCLK_DIVIDE (DIVCLK_DIVIDE), .CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_PHASE (0.000), .CLKIN1_PERIOD (CLKIN1_PERIOD_NS), .CLKIN2_PERIOD (), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_PHASE (CLKOUT0_PHASE), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_PHASE (0.000), .CLKOUT2_DUTY_CYCLE (1.0/16.0), .CLKOUT2_PHASE (9.84375), // PHASE shift is required for sync pulse generation. .CLKOUT3_DUTY_CYCLE (0.500), .CLKOUT3_PHASE (0.000), .CLKOUT4_DUTY_CYCLE (0.500), .CLKOUT4_PHASE (CLKOUT4_PHASE), .CLKOUT5_DUTY_CYCLE (0.500), .CLKOUT5_PHASE (0.000), .REF_JITTER1 (0.010), .REF_JITTER2 (0.010) ) plle2_i ( .CLKFBOUT (pll_clkfbout), .CLKOUT0 (freq_refclk), .CLKOUT1 (mem_refclk), .CLKOUT2 (sync_pulse), // always 1/16 of mem_ref_clk .CLKOUT3 (pll_clk3_out), .CLKOUT4 (auxout_clk_i), .CLKOUT5 (), .DO (), .DRDY (), .LOCKED (pll_locked_i), .CLKFBIN (pll_clkfbout), .CLKIN1 (mmcm_clk), .CLKIN2 (), .CLKINSEL (1'b1), .DADDR (7'b0), .DCLK (1'b0), .DEN (1'b0), .DI (16'b0), .DWE (1'b0), .PWRDWN (1'b0), .RST ( sys_rst_act_hi) ); BUFH u_bufh_auxout_clk ( .O (auxout_clk), .I (auxout_clk_i) ); BUFG u_bufg_clkdiv0 ( .O (clk_bufg), .I (clk_pll_i) ); BUFH u_bufh_pll_clk3 ( .O (pll_clk3), .I (pll_clk3_out) ); localparam real MMCM_VCO_PERIOD = 1000000.0/MMCM_VCO; //synthesis translate_off initial begin $display("############# MMCME2_ADV Parameters #############\n"); $display("MMCM_MULT_F = %d", MMCM_MULT_F); $display("MMCM_VCO_FREQ (MHz) = %7.3f", MMCM_VCO*1000.0); $display("MMCM_VCO_PERIOD = %7.3f", MMCM_VCO_PERIOD); $display("#################################################\n"); end //synthesis translate_on generate if (UI_EXTRA_CLOCKS == "TRUE") begin: gen_ui_extra_clocks localparam MMCM_CLKOUT0_DIVIDE_CAL = (MMCM_CLKOUT0_EN == "TRUE") ? MMCM_CLKOUT0_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT1_DIVIDE_CAL = (MMCM_CLKOUT1_EN == "TRUE") ? MMCM_CLKOUT1_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT2_DIVIDE_CAL = (MMCM_CLKOUT2_EN == "TRUE") ? MMCM_CLKOUT2_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT3_DIVIDE_CAL = (MMCM_CLKOUT3_EN == "TRUE") ? MMCM_CLKOUT3_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT4_DIVIDE_CAL = (MMCM_CLKOUT4_EN == "TRUE") ? MMCM_CLKOUT4_DIVIDE : MMCM_MULT_F; MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("BUF_IN"), .STARTUP_WAIT ("FALSE"), // .DIVCLK_DIVIDE (1), .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), .CLKFBOUT_MULT_F (MMCM_MULT_F), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (MMCM_CLKOUT0_DIVIDE_CAL), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), .CLKOUT1_DIVIDE (MMCM_CLKOUT1_DIVIDE_CAL), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKOUT2_DIVIDE (MMCM_CLKOUT2_DIVIDE_CAL), .CLKOUT2_PHASE (0.000), .CLKOUT2_DUTY_CYCLE (0.500), .CLKOUT2_USE_FINE_PS ("FALSE"), .CLKOUT3_DIVIDE (MMCM_CLKOUT3_DIVIDE_CAL), .CLKOUT3_PHASE (0.000), .CLKOUT3_DUTY_CYCLE (0.500), .CLKOUT3_USE_FINE_PS ("FALSE"), .CLKOUT4_DIVIDE (MMCM_CLKOUT4_DIVIDE_CAL), .CLKOUT4_PHASE (0.000), .CLKOUT4_DUTY_CYCLE (0.500), .CLKOUT4_USE_FINE_PS ("FALSE"), .CLKOUT5_DIVIDE (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), .CLKOUT5_PHASE (0.000), .CLKOUT5_DUTY_CYCLE (0.500), .CLKOUT5_USE_FINE_PS ("TRUE"), .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (clk_pll_i), .CLKFBOUTB (), .CLKOUT0 (mmcm_clkout0), .CLKOUT0B (), .CLKOUT1 (mmcm_clkout1), .CLKOUT1B (), .CLKOUT2 (mmcm_clkout2), .CLKOUT2B (), .CLKOUT3 (mmcm_clkout3), .CLKOUT3B (), .CLKOUT4 (mmcm_clkout4), .CLKOUT5 (mmcm_ps_clk_bufg_in), .CLKOUT6 (), // Input clock control .CLKFBIN (clk_bufg), // From BUFH network .CLKIN1 (pll_clk3), // From PLL .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (clk), .PSEN (psen), .PSINCDEC (psincdec), .PSDONE (psdone), // Other control and status signals .LOCKED (MMCM_Locked_i), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (~pll_locked_i)); BUFG u_bufg_ui_addn_clk_0 ( .O (ui_addn_clk_0), .I (mmcm_clkout0) ); BUFG u_bufg_ui_addn_clk_1 ( .O (ui_addn_clk_1), .I (mmcm_clkout1) ); BUFG u_bufg_ui_addn_clk_2 ( .O (ui_addn_clk_2), .I (mmcm_clkout2) ); BUFG u_bufg_ui_addn_clk_3 ( .O (ui_addn_clk_3), .I (mmcm_clkout3) ); BUFG u_bufg_ui_addn_clk_4 ( .O (ui_addn_clk_4), .I (mmcm_clkout4) ); BUFG u_bufg_mmcm_ps_clk ( .O (mmcm_ps_clk), .I (mmcm_ps_clk_bufg_in) ); end else begin: gen_mmcm MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("BUF_IN"), .STARTUP_WAIT ("FALSE"), // .DIVCLK_DIVIDE (1), .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), .CLKFBOUT_MULT_F (MMCM_MULT_F), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("TRUE"), .CLKOUT1_DIVIDE (), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (clk_pll_i), .CLKFBOUTB (), .CLKOUT0 (mmcm_ps_clk_bufg_in), .CLKOUT0B (), .CLKOUT1 (), .CLKOUT1B (), .CLKOUT2 (), .CLKOUT2B (), .CLKOUT3 (), .CLKOUT3B (), .CLKOUT4 (), .CLKOUT5 (), .CLKOUT6 (), // Input clock control .CLKFBIN (clk_bufg), // From BUFH network .CLKIN1 (pll_clk3), // From PLL .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (clk), .PSEN (psen), .PSINCDEC (psincdec), .PSDONE (psdone), // Other control and status signals .LOCKED (MMCM_Locked_i), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (~pll_locked_i)); BUFG u_bufg_mmcm_ps_clk ( .O (mmcm_ps_clk), .I (mmcm_ps_clk_bufg_in) ); end // block: gen_mmcm endgenerate //*************************************************************************** // Generate poc_sample_pd. // // As the phase shift clocks precesses around kclk, it also precesses // around the fabric clock. Noise may be generated as output of the // IDDR is registered into the fabric clock domain. // // The mmcm_ps_clk signal runs at half the rate of the fabric clock. // This means that there are two rising edges of fabric clock per mmcm_ps_clk. // If we can guarantee that the POC uses the data sampled on the second // fabric clock, then we are certain that the setup time to the second // fabric clock is greater than 1 fabric clock cycle. // // To predict when the phase detctor output is from this second edge, we // need to know two things. The initial phase of fabric clock and mmcm_ps_clk // and the number of phase offsets set into the mmcm. The later is a // trivial count of the PSEN signal. // // The former is a bit tricky because latching a clock with a clock is // not well defined. This problem is solved by generating a signal // the goes high on the first rising edge of mmcm_ps_clk. Logic in // the fabric domain can look at this signal and then develop an analog // the mmcm_ps_clk with zero offset. // // This all depends on the timing tools making the timing work when // when the mmcm phase offset is zero. // // poc_sample_pd tells the POC when to sample the phase detector output. // Setup from the IDDR to the fabric clock is always one plus some // fraction of the fabric clock. //*************************************************************************** localparam ONE = 1; localparam integer TAPSPERFCLK = 56 * MMCM_MULT_F; localparam TAPSPERFCLK_MINUS_ONE = TAPSPERFCLK - 1; localparam QCNTR_WIDTH = clogb2(TAPSPERFCLK); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 reg [QCNTR_WIDTH-1:0] qcntr_ns, qcntr_r; always @(posedge clk) qcntr_r <= #TCQ qcntr_ns; reg inv_poc_sample_ns, inv_poc_sample_r; always @(posedge clk) inv_poc_sample_r <= #TCQ inv_poc_sample_ns; always @(*) begin qcntr_ns = qcntr_r; inv_poc_sample_ns = inv_poc_sample_r; if (rstdiv0) begin qcntr_ns = TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0]; inv_poc_sample_ns = 1'b1; end else if (psen) begin if (qcntr_r < TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0]) qcntr_ns = (qcntr_r + ONE[QCNTR_WIDTH-1:0]); else begin qcntr_ns = {QCNTR_WIDTH{1'b0}}; inv_poc_sample_ns = ~inv_poc_sample_r; end end end // Be vewy vewy careful to make sure this path is aligned with the // phase detector out pipeline. reg first_rising_ps_clk_ns, first_rising_ps_clk_r; always @(posedge mmcm_ps_clk) first_rising_ps_clk_r <= #TCQ first_rising_ps_clk_ns; always @(*) first_rising_ps_clk_ns = ~rstdiv0; reg mmcm_hi0_ns, mmcm_hi0_r; always @(posedge clk) mmcm_hi0_r <= #TCQ mmcm_hi0_ns; always @(*) mmcm_hi0_ns = ~first_rising_ps_clk_r || ~mmcm_hi0_r; reg poc_sample_pd_ns, poc_sample_pd_r; always @(*) poc_sample_pd_ns = inv_poc_sample_ns ^ mmcm_hi0_r; always @(posedge clk) poc_sample_pd_r <= #TCQ poc_sample_pd_ns; assign poc_sample_pd = poc_sample_pd_r; //*************************************************************************** // Make sure logic acheives 90 degree setup time from rising mmcm_ps_clk // to the appropriate edge of fabric clock //*************************************************************************** //synthesis translate_off generate if ( tCK <= 2500 ) begin : check_ocal_timing localparam CLK_PERIOD_PS = MMCM_VCO_PERIOD * MMCM_MULT_F; localparam integer CLK_PERIOD_PS_DIV4 = CLK_PERIOD_PS/4; time rising_mmcm_ps_clk; always @(posedge mmcm_ps_clk) rising_mmcm_ps_clk = $time(); time pdiff; // Not used, except in waveform plots. always @(posedge clk) pdiff = $time() - rising_mmcm_ps_clk; end endgenerate //synthesis translate_on //*************************************************************************** // RESET SYNCHRONIZATION DESCRIPTION: // Various resets are generated to ensure that: // 1. All resets are synchronously deasserted with respect to the clock // domain they are interfacing to. There are several different clock // domains - each one will receive a synchronized reset. // 2. The reset deassertion order starts with deassertion of SYS_RST, // followed by deassertion of resets for various parts of the design // (see "RESET ORDER" below) based on the lock status of PLLE2s. // RESET ORDER: // 1. User deasserts SYS_RST // 2. Reset PLLE2 and IDELAYCTRL // 3. Wait for PLLE2 and IDELAYCTRL to lock // 4. Release reset for all I/O primitives and internal logic // OTHER NOTES: // 1. Asynchronously assert reset. This way we can assert reset even if // there is no clock (needed for things like 3-stating output buffers // to prevent initial bus contention). Reset deassertion is synchronous. //*************************************************************************** //***************************************************************** // CLKDIV logic reset //***************************************************************** // Wait for PLLE2 and IDELAYCTRL to lock before releasing reset // current O,25.0 unisim phaser_ref never locks. Need to find out why . generate if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_300_400 assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[1] | ~ref_dll_lock | ~MMCM_Locked_i; end else begin: rst_tmp_200 assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[0] | ~ref_dll_lock | ~MMCM_Locked_i; end endgenerate always @(posedge clk_bufg or posedge rst_tmp) begin if (rst_tmp) begin rstdiv0_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; rstdiv0_sync_r1 <= #TCQ 1'b1 ; end else begin rstdiv0_sync_r <= #TCQ rstdiv0_sync_r << 1; rstdiv0_sync_r1 <= #TCQ rstdiv0_sync_r[RST_DIV_SYNC_NUM-2]; end end assign rstdiv0 = rstdiv0_sync_r1 ; //IDDR rest always @(posedge mmcm_ps_clk or posedge rst_tmp) begin if (rst_tmp) begin rst_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; rst_sync_r1 <= #TCQ 1'b1 ; end else begin rst_sync_r <= #TCQ rst_sync_r << 1; rst_sync_r1 <= #TCQ rst_sync_r[RST_DIV_SYNC_NUM-2]; end end assign iddr_rst = rst_sync_r1 ; generate if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_phaser_ref_300_400 assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[1]; end else begin: rst_tmp_phaser_ref_200 assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[0]; end endgenerate always @(posedge clk_bufg or posedge rst_tmp_phaser_ref) if (rst_tmp_phaser_ref) rst_phaser_ref_sync_r <= #TCQ {RST_DIV_SYNC_NUM{1'b1}}; else rst_phaser_ref_sync_r <= #TCQ rst_phaser_ref_sync_r << 1; assign rst_phaser_ref = rst_phaser_ref_sync_r[RST_DIV_SYNC_NUM-1]; endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: infrastructure.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ // \ \ / \ Date Created:Tue Jun 30 2009 // \___\/\___\ // //Device: Virtex-6 //Design Name: DDR3 SDRAM //Purpose: // Clock generation/distribution and reset synchronization //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: infrastructure.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ **$Date: 2011/06/02 08:34:56 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/infrastructure.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_infrastructure # ( parameter SIMULATION = "FALSE", // Should be TRUE during design simulations and // FALSE during implementations parameter TCQ = 100, // clk->out delay (sim only) parameter CLKIN_PERIOD = 3000, // Memory clock period parameter nCK_PER_CLK = 2, // Fabric clk period:Memory clk period parameter SYSCLK_TYPE = "DIFFERENTIAL", // input clock type // "DIFFERENTIAL","SINGLE_ENDED" parameter UI_EXTRA_CLOCKS = "FALSE", // Generates extra clocks as // 1/2, 1/4 and 1/8 of fabrick clock. // Valid for DDR2/DDR3 AXI interfaces // based on GUI selection parameter CLKFBOUT_MULT = 4, // write PLL VCO multiplier parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor parameter CLKOUT0_PHASE = 45.0, // VCO output divisor for clkout0 parameter CLKOUT0_DIVIDE = 16, // VCO output divisor for PLL clkout0 parameter CLKOUT1_DIVIDE = 4, // VCO output divisor for PLL clkout1 parameter CLKOUT2_DIVIDE = 64, // VCO output divisor for PLL clkout2 parameter CLKOUT3_DIVIDE = 16, // VCO output divisor for PLL clkout3 parameter MMCM_VCO = 1200, // Max Freq (MHz) of MMCM VCO parameter MMCM_MULT_F = 4, // write MMCM VCO multiplier parameter MMCM_DIVCLK_DIVIDE = 1, // write MMCM VCO divisor parameter MMCM_CLKOUT0_EN = "FALSE", // Enabled (or) Disable MMCM clkout0 parameter MMCM_CLKOUT1_EN = "FALSE", // Enabled (or) Disable MMCM clkout1 parameter MMCM_CLKOUT2_EN = "FALSE", // Enabled (or) Disable MMCM clkout2 parameter MMCM_CLKOUT3_EN = "FALSE", // Enabled (or) Disable MMCM clkout3 parameter MMCM_CLKOUT4_EN = "FALSE", // Enabled (or) Disable MMCM clkout4 parameter MMCM_CLKOUT0_DIVIDE = 1, // VCO output divisor for MMCM clkout0 parameter MMCM_CLKOUT1_DIVIDE = 1, // VCO output divisor for MMCM clkout1 parameter MMCM_CLKOUT2_DIVIDE = 1, // VCO output divisor for MMCM clkout2 parameter MMCM_CLKOUT3_DIVIDE = 1, // VCO output divisor for MMCM clkout3 parameter MMCM_CLKOUT4_DIVIDE = 1, // VCO output divisor for MMCM clkout4 parameter RST_ACT_LOW = 1, parameter tCK = 1250, // memory tCK paramter. // # = Clock Period in pS. parameter MEM_TYPE = "DDR3" ) ( // Clock inputs input mmcm_clk, // System clock diff input // System reset input input sys_rst, // core reset from user application // PLLE2/IDELAYCTRL Lock status input [1:0] iodelay_ctrl_rdy, // IDELAYCTRL lock status // Clock outputs output clk, // fabric clock freq ; either half rate or quarter rate and is // determined by PLL parameters settings. output mem_refclk, // equal to memory clock output freq_refclk, // freq above 400 MHz: set freq_refclk = mem_refclk // freq below 400 MHz: set freq_refclk = 2* mem_refclk or 4* mem_refclk; // to hard PHY for phaser output sync_pulse, // exactly 1/16 of mem_refclk and the sync pulse is exactly 1 memref_clk wide output auxout_clk, // IO clk used to clock out Aux_Out ports output mmcm_ps_clk, // Phase shift clock output poc_sample_pd, // Tell POC when to sample phase detector output. output ui_addn_clk_0, // MMCM out0 clk output ui_addn_clk_1, // MMCM out1 clk output ui_addn_clk_2, // MMCM out2 clk output ui_addn_clk_3, // MMCM out3 clk output ui_addn_clk_4, // MMCM out4 clk output pll_locked, // locked output from PLLE2_ADV output mmcm_locked, // locked output from MMCME2_ADV // Reset outputs output rstdiv0, // Reset CLK and CLKDIV logic (incl I/O), output iddr_rst ,output rst_phaser_ref ,input ref_dll_lock ,input psen ,input psincdec ,output psdone ); // # of clock cycles to delay deassertion of reset. Needs to be a fairly // high number not so much for metastability protection, but to give time // for reset (i.e. stable clock cycles) to propagate through all state // machines and to all control signals (i.e. not all control signals have // resets, instead they rely on base state logic being reset, and the effect // of that reset propagating through the logic). Need this because we may not // be getting stable clock cycles while reset asserted (i.e. since reset // depends on DCM lock status) localparam RST_SYNC_NUM = 25; // Round up for clk reset delay to ensure that CLKDIV reset deassertion // occurs at same time or after CLK reset deassertion (still need to // consider route delay - add one or two extra cycles to be sure!) localparam RST_DIV_SYNC_NUM = (RST_SYNC_NUM+1)/2; // Input clock is assumed to be equal to the memory clock frequency // User should change the parameter as necessary if a different input // clock frequency is used localparam real CLKIN1_PERIOD_NS = CLKIN_PERIOD / 1000.0; localparam CLKOUT4_DIVIDE = 2 * CLKOUT1_DIVIDE; localparam integer VCO_PERIOD = (CLKIN1_PERIOD_NS * DIVCLK_DIVIDE * 1000) / CLKFBOUT_MULT; localparam CLKOUT0_PERIOD = VCO_PERIOD * CLKOUT0_DIVIDE; localparam CLKOUT1_PERIOD = VCO_PERIOD * CLKOUT1_DIVIDE; localparam CLKOUT2_PERIOD = VCO_PERIOD * CLKOUT2_DIVIDE; localparam CLKOUT3_PERIOD = VCO_PERIOD * CLKOUT3_DIVIDE; localparam CLKOUT4_PERIOD = VCO_PERIOD * CLKOUT4_DIVIDE; localparam CLKOUT4_PHASE = (SIMULATION == "TRUE") ? 22.5 : 168.75; localparam real CLKOUT3_PERIOD_NS = CLKOUT3_PERIOD / 1000.0; localparam real CLKOUT4_PERIOD_NS = CLKOUT4_PERIOD / 1000.0; //synthesis translate_off initial begin $display("############# Write Clocks PLLE2_ADV Parameters #############\n"); $display("nCK_PER_CLK = %7d", nCK_PER_CLK ); $display("CLK_PERIOD = %7d", CLKIN_PERIOD ); $display("CLKIN1_PERIOD = %7.3f", CLKIN1_PERIOD_NS); $display("DIVCLK_DIVIDE = %7d", DIVCLK_DIVIDE ); $display("CLKFBOUT_MULT = %7d", CLKFBOUT_MULT ); $display("VCO_PERIOD = %7.1f", VCO_PERIOD ); $display("CLKOUT0_DIVIDE_F = %7d", CLKOUT0_DIVIDE ); $display("CLKOUT1_DIVIDE = %7d", CLKOUT1_DIVIDE ); $display("CLKOUT2_DIVIDE = %7d", CLKOUT2_DIVIDE ); $display("CLKOUT3_DIVIDE = %7d", CLKOUT3_DIVIDE ); $display("CLKOUT0_PERIOD = %7d", CLKOUT0_PERIOD ); $display("CLKOUT1_PERIOD = %7d", CLKOUT1_PERIOD ); $display("CLKOUT2_PERIOD = %7d", CLKOUT2_PERIOD ); $display("CLKOUT3_PERIOD = %7d", CLKOUT3_PERIOD ); $display("CLKOUT4_PERIOD = %7d", CLKOUT4_PERIOD ); $display("############################################################\n"); end //synthesis translate_on wire clk_bufg; wire clk_pll; wire clkfbout_pll; wire mmcm_clkfbout; wire pll_locked_i /* synthesis syn_maxfan = 10 */; (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-2:0] rstdiv0_sync_r; wire rst_tmp; (* max_fanout = 50 *) reg rstdiv0_sync_r1 /* synthesis syn_maxfan = 50 */; reg [RST_DIV_SYNC_NUM-2:0] rst_sync_r; (* max_fanout = 10 *) reg rst_sync_r1 /* synthesis syn_maxfan = 10 */; wire sys_rst_act_hi; wire rst_tmp_phaser_ref; (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-1:0] rst_phaser_ref_sync_r /* synthesis syn_maxfan = 10 */; // Instantiation of the MMCM primitive wire clkfbout; wire MMCM_Locked_i; wire mmcm_clkout0; wire mmcm_clkout1; wire mmcm_clkout2; wire mmcm_clkout3; wire mmcm_clkout4; wire mmcm_ps_clk_bufg_in; wire pll_clk3_out; wire pll_clk3; assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst; //*************************************************************************** // Assign global clocks: // 2. clk : Half rate / Quarter rate(used for majority of internal logic) //*************************************************************************** assign clk = clk_bufg; assign pll_locked = pll_locked_i & MMCM_Locked_i; assign mmcm_locked = MMCM_Locked_i; //*************************************************************************** // Global base clock generation and distribution //*************************************************************************** //***************************************************************** // NOTES ON CALCULTING PROPER VCO FREQUENCY // 1. VCO frequency = // 1/((DIVCLK_DIVIDE * CLKIN_PERIOD)/(CLKFBOUT_MULT * nCK_PER_CLK)) // 2. VCO frequency must be in the range [TBD, TBD] //***************************************************************** PLLE2_ADV # ( .BANDWIDTH ("OPTIMIZED"), .COMPENSATION ("INTERNAL"), .STARTUP_WAIT ("FALSE"), .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), // 4 freq_ref .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), // 4 mem_ref .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), // 16 sync .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), // 16 sysclk .CLKOUT4_DIVIDE (CLKOUT4_DIVIDE), .CLKOUT5_DIVIDE (), .DIVCLK_DIVIDE (DIVCLK_DIVIDE), .CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_PHASE (0.000), .CLKIN1_PERIOD (CLKIN1_PERIOD_NS), .CLKIN2_PERIOD (), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_PHASE (CLKOUT0_PHASE), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_PHASE (0.000), .CLKOUT2_DUTY_CYCLE (1.0/16.0), .CLKOUT2_PHASE (9.84375), // PHASE shift is required for sync pulse generation. .CLKOUT3_DUTY_CYCLE (0.500), .CLKOUT3_PHASE (0.000), .CLKOUT4_DUTY_CYCLE (0.500), .CLKOUT4_PHASE (CLKOUT4_PHASE), .CLKOUT5_DUTY_CYCLE (0.500), .CLKOUT5_PHASE (0.000), .REF_JITTER1 (0.010), .REF_JITTER2 (0.010) ) plle2_i ( .CLKFBOUT (pll_clkfbout), .CLKOUT0 (freq_refclk), .CLKOUT1 (mem_refclk), .CLKOUT2 (sync_pulse), // always 1/16 of mem_ref_clk .CLKOUT3 (pll_clk3_out), .CLKOUT4 (auxout_clk_i), .CLKOUT5 (), .DO (), .DRDY (), .LOCKED (pll_locked_i), .CLKFBIN (pll_clkfbout), .CLKIN1 (mmcm_clk), .CLKIN2 (), .CLKINSEL (1'b1), .DADDR (7'b0), .DCLK (1'b0), .DEN (1'b0), .DI (16'b0), .DWE (1'b0), .PWRDWN (1'b0), .RST ( sys_rst_act_hi) ); BUFH u_bufh_auxout_clk ( .O (auxout_clk), .I (auxout_clk_i) ); BUFG u_bufg_clkdiv0 ( .O (clk_bufg), .I (clk_pll_i) ); BUFH u_bufh_pll_clk3 ( .O (pll_clk3), .I (pll_clk3_out) ); localparam real MMCM_VCO_PERIOD = 1000000.0/MMCM_VCO; //synthesis translate_off initial begin $display("############# MMCME2_ADV Parameters #############\n"); $display("MMCM_MULT_F = %d", MMCM_MULT_F); $display("MMCM_VCO_FREQ (MHz) = %7.3f", MMCM_VCO*1000.0); $display("MMCM_VCO_PERIOD = %7.3f", MMCM_VCO_PERIOD); $display("#################################################\n"); end //synthesis translate_on generate if (UI_EXTRA_CLOCKS == "TRUE") begin: gen_ui_extra_clocks localparam MMCM_CLKOUT0_DIVIDE_CAL = (MMCM_CLKOUT0_EN == "TRUE") ? MMCM_CLKOUT0_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT1_DIVIDE_CAL = (MMCM_CLKOUT1_EN == "TRUE") ? MMCM_CLKOUT1_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT2_DIVIDE_CAL = (MMCM_CLKOUT2_EN == "TRUE") ? MMCM_CLKOUT2_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT3_DIVIDE_CAL = (MMCM_CLKOUT3_EN == "TRUE") ? MMCM_CLKOUT3_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT4_DIVIDE_CAL = (MMCM_CLKOUT4_EN == "TRUE") ? MMCM_CLKOUT4_DIVIDE : MMCM_MULT_F; MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("BUF_IN"), .STARTUP_WAIT ("FALSE"), // .DIVCLK_DIVIDE (1), .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), .CLKFBOUT_MULT_F (MMCM_MULT_F), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (MMCM_CLKOUT0_DIVIDE_CAL), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), .CLKOUT1_DIVIDE (MMCM_CLKOUT1_DIVIDE_CAL), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKOUT2_DIVIDE (MMCM_CLKOUT2_DIVIDE_CAL), .CLKOUT2_PHASE (0.000), .CLKOUT2_DUTY_CYCLE (0.500), .CLKOUT2_USE_FINE_PS ("FALSE"), .CLKOUT3_DIVIDE (MMCM_CLKOUT3_DIVIDE_CAL), .CLKOUT3_PHASE (0.000), .CLKOUT3_DUTY_CYCLE (0.500), .CLKOUT3_USE_FINE_PS ("FALSE"), .CLKOUT4_DIVIDE (MMCM_CLKOUT4_DIVIDE_CAL), .CLKOUT4_PHASE (0.000), .CLKOUT4_DUTY_CYCLE (0.500), .CLKOUT4_USE_FINE_PS ("FALSE"), .CLKOUT5_DIVIDE (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), .CLKOUT5_PHASE (0.000), .CLKOUT5_DUTY_CYCLE (0.500), .CLKOUT5_USE_FINE_PS ("TRUE"), .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (clk_pll_i), .CLKFBOUTB (), .CLKOUT0 (mmcm_clkout0), .CLKOUT0B (), .CLKOUT1 (mmcm_clkout1), .CLKOUT1B (), .CLKOUT2 (mmcm_clkout2), .CLKOUT2B (), .CLKOUT3 (mmcm_clkout3), .CLKOUT3B (), .CLKOUT4 (mmcm_clkout4), .CLKOUT5 (mmcm_ps_clk_bufg_in), .CLKOUT6 (), // Input clock control .CLKFBIN (clk_bufg), // From BUFH network .CLKIN1 (pll_clk3), // From PLL .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (clk), .PSEN (psen), .PSINCDEC (psincdec), .PSDONE (psdone), // Other control and status signals .LOCKED (MMCM_Locked_i), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (~pll_locked_i)); BUFG u_bufg_ui_addn_clk_0 ( .O (ui_addn_clk_0), .I (mmcm_clkout0) ); BUFG u_bufg_ui_addn_clk_1 ( .O (ui_addn_clk_1), .I (mmcm_clkout1) ); BUFG u_bufg_ui_addn_clk_2 ( .O (ui_addn_clk_2), .I (mmcm_clkout2) ); BUFG u_bufg_ui_addn_clk_3 ( .O (ui_addn_clk_3), .I (mmcm_clkout3) ); BUFG u_bufg_ui_addn_clk_4 ( .O (ui_addn_clk_4), .I (mmcm_clkout4) ); BUFG u_bufg_mmcm_ps_clk ( .O (mmcm_ps_clk), .I (mmcm_ps_clk_bufg_in) ); end else begin: gen_mmcm MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("BUF_IN"), .STARTUP_WAIT ("FALSE"), // .DIVCLK_DIVIDE (1), .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), .CLKFBOUT_MULT_F (MMCM_MULT_F), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("TRUE"), .CLKOUT1_DIVIDE (), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (clk_pll_i), .CLKFBOUTB (), .CLKOUT0 (mmcm_ps_clk_bufg_in), .CLKOUT0B (), .CLKOUT1 (), .CLKOUT1B (), .CLKOUT2 (), .CLKOUT2B (), .CLKOUT3 (), .CLKOUT3B (), .CLKOUT4 (), .CLKOUT5 (), .CLKOUT6 (), // Input clock control .CLKFBIN (clk_bufg), // From BUFH network .CLKIN1 (pll_clk3), // From PLL .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (clk), .PSEN (psen), .PSINCDEC (psincdec), .PSDONE (psdone), // Other control and status signals .LOCKED (MMCM_Locked_i), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (~pll_locked_i)); BUFG u_bufg_mmcm_ps_clk ( .O (mmcm_ps_clk), .I (mmcm_ps_clk_bufg_in) ); end // block: gen_mmcm endgenerate //*************************************************************************** // Generate poc_sample_pd. // // As the phase shift clocks precesses around kclk, it also precesses // around the fabric clock. Noise may be generated as output of the // IDDR is registered into the fabric clock domain. // // The mmcm_ps_clk signal runs at half the rate of the fabric clock. // This means that there are two rising edges of fabric clock per mmcm_ps_clk. // If we can guarantee that the POC uses the data sampled on the second // fabric clock, then we are certain that the setup time to the second // fabric clock is greater than 1 fabric clock cycle. // // To predict when the phase detctor output is from this second edge, we // need to know two things. The initial phase of fabric clock and mmcm_ps_clk // and the number of phase offsets set into the mmcm. The later is a // trivial count of the PSEN signal. // // The former is a bit tricky because latching a clock with a clock is // not well defined. This problem is solved by generating a signal // the goes high on the first rising edge of mmcm_ps_clk. Logic in // the fabric domain can look at this signal and then develop an analog // the mmcm_ps_clk with zero offset. // // This all depends on the timing tools making the timing work when // when the mmcm phase offset is zero. // // poc_sample_pd tells the POC when to sample the phase detector output. // Setup from the IDDR to the fabric clock is always one plus some // fraction of the fabric clock. //*************************************************************************** localparam ONE = 1; localparam integer TAPSPERFCLK = 56 * MMCM_MULT_F; localparam TAPSPERFCLK_MINUS_ONE = TAPSPERFCLK - 1; localparam QCNTR_WIDTH = clogb2(TAPSPERFCLK); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 reg [QCNTR_WIDTH-1:0] qcntr_ns, qcntr_r; always @(posedge clk) qcntr_r <= #TCQ qcntr_ns; reg inv_poc_sample_ns, inv_poc_sample_r; always @(posedge clk) inv_poc_sample_r <= #TCQ inv_poc_sample_ns; always @(*) begin qcntr_ns = qcntr_r; inv_poc_sample_ns = inv_poc_sample_r; if (rstdiv0) begin qcntr_ns = TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0]; inv_poc_sample_ns = 1'b1; end else if (psen) begin if (qcntr_r < TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0]) qcntr_ns = (qcntr_r + ONE[QCNTR_WIDTH-1:0]); else begin qcntr_ns = {QCNTR_WIDTH{1'b0}}; inv_poc_sample_ns = ~inv_poc_sample_r; end end end // Be vewy vewy careful to make sure this path is aligned with the // phase detector out pipeline. reg first_rising_ps_clk_ns, first_rising_ps_clk_r; always @(posedge mmcm_ps_clk) first_rising_ps_clk_r <= #TCQ first_rising_ps_clk_ns; always @(*) first_rising_ps_clk_ns = ~rstdiv0; reg mmcm_hi0_ns, mmcm_hi0_r; always @(posedge clk) mmcm_hi0_r <= #TCQ mmcm_hi0_ns; always @(*) mmcm_hi0_ns = ~first_rising_ps_clk_r || ~mmcm_hi0_r; reg poc_sample_pd_ns, poc_sample_pd_r; always @(*) poc_sample_pd_ns = inv_poc_sample_ns ^ mmcm_hi0_r; always @(posedge clk) poc_sample_pd_r <= #TCQ poc_sample_pd_ns; assign poc_sample_pd = poc_sample_pd_r; //*************************************************************************** // Make sure logic acheives 90 degree setup time from rising mmcm_ps_clk // to the appropriate edge of fabric clock //*************************************************************************** //synthesis translate_off generate if ( tCK <= 2500 ) begin : check_ocal_timing localparam CLK_PERIOD_PS = MMCM_VCO_PERIOD * MMCM_MULT_F; localparam integer CLK_PERIOD_PS_DIV4 = CLK_PERIOD_PS/4; time rising_mmcm_ps_clk; always @(posedge mmcm_ps_clk) rising_mmcm_ps_clk = $time(); time pdiff; // Not used, except in waveform plots. always @(posedge clk) pdiff = $time() - rising_mmcm_ps_clk; end endgenerate //synthesis translate_on //*************************************************************************** // RESET SYNCHRONIZATION DESCRIPTION: // Various resets are generated to ensure that: // 1. All resets are synchronously deasserted with respect to the clock // domain they are interfacing to. There are several different clock // domains - each one will receive a synchronized reset. // 2. The reset deassertion order starts with deassertion of SYS_RST, // followed by deassertion of resets for various parts of the design // (see "RESET ORDER" below) based on the lock status of PLLE2s. // RESET ORDER: // 1. User deasserts SYS_RST // 2. Reset PLLE2 and IDELAYCTRL // 3. Wait for PLLE2 and IDELAYCTRL to lock // 4. Release reset for all I/O primitives and internal logic // OTHER NOTES: // 1. Asynchronously assert reset. This way we can assert reset even if // there is no clock (needed for things like 3-stating output buffers // to prevent initial bus contention). Reset deassertion is synchronous. //*************************************************************************** //***************************************************************** // CLKDIV logic reset //***************************************************************** // Wait for PLLE2 and IDELAYCTRL to lock before releasing reset // current O,25.0 unisim phaser_ref never locks. Need to find out why . generate if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_300_400 assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[1] | ~ref_dll_lock | ~MMCM_Locked_i; end else begin: rst_tmp_200 assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[0] | ~ref_dll_lock | ~MMCM_Locked_i; end endgenerate always @(posedge clk_bufg or posedge rst_tmp) begin if (rst_tmp) begin rstdiv0_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; rstdiv0_sync_r1 <= #TCQ 1'b1 ; end else begin rstdiv0_sync_r <= #TCQ rstdiv0_sync_r << 1; rstdiv0_sync_r1 <= #TCQ rstdiv0_sync_r[RST_DIV_SYNC_NUM-2]; end end assign rstdiv0 = rstdiv0_sync_r1 ; //IDDR rest always @(posedge mmcm_ps_clk or posedge rst_tmp) begin if (rst_tmp) begin rst_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; rst_sync_r1 <= #TCQ 1'b1 ; end else begin rst_sync_r <= #TCQ rst_sync_r << 1; rst_sync_r1 <= #TCQ rst_sync_r[RST_DIV_SYNC_NUM-2]; end end assign iddr_rst = rst_sync_r1 ; generate if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_phaser_ref_300_400 assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[1]; end else begin: rst_tmp_phaser_ref_200 assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[0]; end endgenerate always @(posedge clk_bufg or posedge rst_tmp_phaser_ref) if (rst_tmp_phaser_ref) rst_phaser_ref_sync_r <= #TCQ {RST_DIV_SYNC_NUM{1'b1}}; else rst_phaser_ref_sync_r <= #TCQ rst_phaser_ref_sync_r << 1; assign rst_phaser_ref = rst_phaser_ref_sync_r[RST_DIV_SYNC_NUM-1]; endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: infrastructure.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ // \ \ / \ Date Created:Tue Jun 30 2009 // \___\/\___\ // //Device: Virtex-6 //Design Name: DDR3 SDRAM //Purpose: // Clock generation/distribution and reset synchronization //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: infrastructure.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ **$Date: 2011/06/02 08:34:56 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/infrastructure.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_infrastructure # ( parameter SIMULATION = "FALSE", // Should be TRUE during design simulations and // FALSE during implementations parameter TCQ = 100, // clk->out delay (sim only) parameter CLKIN_PERIOD = 3000, // Memory clock period parameter nCK_PER_CLK = 2, // Fabric clk period:Memory clk period parameter SYSCLK_TYPE = "DIFFERENTIAL", // input clock type // "DIFFERENTIAL","SINGLE_ENDED" parameter UI_EXTRA_CLOCKS = "FALSE", // Generates extra clocks as // 1/2, 1/4 and 1/8 of fabrick clock. // Valid for DDR2/DDR3 AXI interfaces // based on GUI selection parameter CLKFBOUT_MULT = 4, // write PLL VCO multiplier parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor parameter CLKOUT0_PHASE = 45.0, // VCO output divisor for clkout0 parameter CLKOUT0_DIVIDE = 16, // VCO output divisor for PLL clkout0 parameter CLKOUT1_DIVIDE = 4, // VCO output divisor for PLL clkout1 parameter CLKOUT2_DIVIDE = 64, // VCO output divisor for PLL clkout2 parameter CLKOUT3_DIVIDE = 16, // VCO output divisor for PLL clkout3 parameter MMCM_VCO = 1200, // Max Freq (MHz) of MMCM VCO parameter MMCM_MULT_F = 4, // write MMCM VCO multiplier parameter MMCM_DIVCLK_DIVIDE = 1, // write MMCM VCO divisor parameter MMCM_CLKOUT0_EN = "FALSE", // Enabled (or) Disable MMCM clkout0 parameter MMCM_CLKOUT1_EN = "FALSE", // Enabled (or) Disable MMCM clkout1 parameter MMCM_CLKOUT2_EN = "FALSE", // Enabled (or) Disable MMCM clkout2 parameter MMCM_CLKOUT3_EN = "FALSE", // Enabled (or) Disable MMCM clkout3 parameter MMCM_CLKOUT4_EN = "FALSE", // Enabled (or) Disable MMCM clkout4 parameter MMCM_CLKOUT0_DIVIDE = 1, // VCO output divisor for MMCM clkout0 parameter MMCM_CLKOUT1_DIVIDE = 1, // VCO output divisor for MMCM clkout1 parameter MMCM_CLKOUT2_DIVIDE = 1, // VCO output divisor for MMCM clkout2 parameter MMCM_CLKOUT3_DIVIDE = 1, // VCO output divisor for MMCM clkout3 parameter MMCM_CLKOUT4_DIVIDE = 1, // VCO output divisor for MMCM clkout4 parameter RST_ACT_LOW = 1, parameter tCK = 1250, // memory tCK paramter. // # = Clock Period in pS. parameter MEM_TYPE = "DDR3" ) ( // Clock inputs input mmcm_clk, // System clock diff input // System reset input input sys_rst, // core reset from user application // PLLE2/IDELAYCTRL Lock status input [1:0] iodelay_ctrl_rdy, // IDELAYCTRL lock status // Clock outputs output clk, // fabric clock freq ; either half rate or quarter rate and is // determined by PLL parameters settings. output mem_refclk, // equal to memory clock output freq_refclk, // freq above 400 MHz: set freq_refclk = mem_refclk // freq below 400 MHz: set freq_refclk = 2* mem_refclk or 4* mem_refclk; // to hard PHY for phaser output sync_pulse, // exactly 1/16 of mem_refclk and the sync pulse is exactly 1 memref_clk wide output auxout_clk, // IO clk used to clock out Aux_Out ports output mmcm_ps_clk, // Phase shift clock output poc_sample_pd, // Tell POC when to sample phase detector output. output ui_addn_clk_0, // MMCM out0 clk output ui_addn_clk_1, // MMCM out1 clk output ui_addn_clk_2, // MMCM out2 clk output ui_addn_clk_3, // MMCM out3 clk output ui_addn_clk_4, // MMCM out4 clk output pll_locked, // locked output from PLLE2_ADV output mmcm_locked, // locked output from MMCME2_ADV // Reset outputs output rstdiv0, // Reset CLK and CLKDIV logic (incl I/O), output iddr_rst ,output rst_phaser_ref ,input ref_dll_lock ,input psen ,input psincdec ,output psdone ); // # of clock cycles to delay deassertion of reset. Needs to be a fairly // high number not so much for metastability protection, but to give time // for reset (i.e. stable clock cycles) to propagate through all state // machines and to all control signals (i.e. not all control signals have // resets, instead they rely on base state logic being reset, and the effect // of that reset propagating through the logic). Need this because we may not // be getting stable clock cycles while reset asserted (i.e. since reset // depends on DCM lock status) localparam RST_SYNC_NUM = 25; // Round up for clk reset delay to ensure that CLKDIV reset deassertion // occurs at same time or after CLK reset deassertion (still need to // consider route delay - add one or two extra cycles to be sure!) localparam RST_DIV_SYNC_NUM = (RST_SYNC_NUM+1)/2; // Input clock is assumed to be equal to the memory clock frequency // User should change the parameter as necessary if a different input // clock frequency is used localparam real CLKIN1_PERIOD_NS = CLKIN_PERIOD / 1000.0; localparam CLKOUT4_DIVIDE = 2 * CLKOUT1_DIVIDE; localparam integer VCO_PERIOD = (CLKIN1_PERIOD_NS * DIVCLK_DIVIDE * 1000) / CLKFBOUT_MULT; localparam CLKOUT0_PERIOD = VCO_PERIOD * CLKOUT0_DIVIDE; localparam CLKOUT1_PERIOD = VCO_PERIOD * CLKOUT1_DIVIDE; localparam CLKOUT2_PERIOD = VCO_PERIOD * CLKOUT2_DIVIDE; localparam CLKOUT3_PERIOD = VCO_PERIOD * CLKOUT3_DIVIDE; localparam CLKOUT4_PERIOD = VCO_PERIOD * CLKOUT4_DIVIDE; localparam CLKOUT4_PHASE = (SIMULATION == "TRUE") ? 22.5 : 168.75; localparam real CLKOUT3_PERIOD_NS = CLKOUT3_PERIOD / 1000.0; localparam real CLKOUT4_PERIOD_NS = CLKOUT4_PERIOD / 1000.0; //synthesis translate_off initial begin $display("############# Write Clocks PLLE2_ADV Parameters #############\n"); $display("nCK_PER_CLK = %7d", nCK_PER_CLK ); $display("CLK_PERIOD = %7d", CLKIN_PERIOD ); $display("CLKIN1_PERIOD = %7.3f", CLKIN1_PERIOD_NS); $display("DIVCLK_DIVIDE = %7d", DIVCLK_DIVIDE ); $display("CLKFBOUT_MULT = %7d", CLKFBOUT_MULT ); $display("VCO_PERIOD = %7.1f", VCO_PERIOD ); $display("CLKOUT0_DIVIDE_F = %7d", CLKOUT0_DIVIDE ); $display("CLKOUT1_DIVIDE = %7d", CLKOUT1_DIVIDE ); $display("CLKOUT2_DIVIDE = %7d", CLKOUT2_DIVIDE ); $display("CLKOUT3_DIVIDE = %7d", CLKOUT3_DIVIDE ); $display("CLKOUT0_PERIOD = %7d", CLKOUT0_PERIOD ); $display("CLKOUT1_PERIOD = %7d", CLKOUT1_PERIOD ); $display("CLKOUT2_PERIOD = %7d", CLKOUT2_PERIOD ); $display("CLKOUT3_PERIOD = %7d", CLKOUT3_PERIOD ); $display("CLKOUT4_PERIOD = %7d", CLKOUT4_PERIOD ); $display("############################################################\n"); end //synthesis translate_on wire clk_bufg; wire clk_pll; wire clkfbout_pll; wire mmcm_clkfbout; wire pll_locked_i /* synthesis syn_maxfan = 10 */; (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-2:0] rstdiv0_sync_r; wire rst_tmp; (* max_fanout = 50 *) reg rstdiv0_sync_r1 /* synthesis syn_maxfan = 50 */; reg [RST_DIV_SYNC_NUM-2:0] rst_sync_r; (* max_fanout = 10 *) reg rst_sync_r1 /* synthesis syn_maxfan = 10 */; wire sys_rst_act_hi; wire rst_tmp_phaser_ref; (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-1:0] rst_phaser_ref_sync_r /* synthesis syn_maxfan = 10 */; // Instantiation of the MMCM primitive wire clkfbout; wire MMCM_Locked_i; wire mmcm_clkout0; wire mmcm_clkout1; wire mmcm_clkout2; wire mmcm_clkout3; wire mmcm_clkout4; wire mmcm_ps_clk_bufg_in; wire pll_clk3_out; wire pll_clk3; assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst; //*************************************************************************** // Assign global clocks: // 2. clk : Half rate / Quarter rate(used for majority of internal logic) //*************************************************************************** assign clk = clk_bufg; assign pll_locked = pll_locked_i & MMCM_Locked_i; assign mmcm_locked = MMCM_Locked_i; //*************************************************************************** // Global base clock generation and distribution //*************************************************************************** //***************************************************************** // NOTES ON CALCULTING PROPER VCO FREQUENCY // 1. VCO frequency = // 1/((DIVCLK_DIVIDE * CLKIN_PERIOD)/(CLKFBOUT_MULT * nCK_PER_CLK)) // 2. VCO frequency must be in the range [TBD, TBD] //***************************************************************** PLLE2_ADV # ( .BANDWIDTH ("OPTIMIZED"), .COMPENSATION ("INTERNAL"), .STARTUP_WAIT ("FALSE"), .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), // 4 freq_ref .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), // 4 mem_ref .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), // 16 sync .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), // 16 sysclk .CLKOUT4_DIVIDE (CLKOUT4_DIVIDE), .CLKOUT5_DIVIDE (), .DIVCLK_DIVIDE (DIVCLK_DIVIDE), .CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_PHASE (0.000), .CLKIN1_PERIOD (CLKIN1_PERIOD_NS), .CLKIN2_PERIOD (), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_PHASE (CLKOUT0_PHASE), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_PHASE (0.000), .CLKOUT2_DUTY_CYCLE (1.0/16.0), .CLKOUT2_PHASE (9.84375), // PHASE shift is required for sync pulse generation. .CLKOUT3_DUTY_CYCLE (0.500), .CLKOUT3_PHASE (0.000), .CLKOUT4_DUTY_CYCLE (0.500), .CLKOUT4_PHASE (CLKOUT4_PHASE), .CLKOUT5_DUTY_CYCLE (0.500), .CLKOUT5_PHASE (0.000), .REF_JITTER1 (0.010), .REF_JITTER2 (0.010) ) plle2_i ( .CLKFBOUT (pll_clkfbout), .CLKOUT0 (freq_refclk), .CLKOUT1 (mem_refclk), .CLKOUT2 (sync_pulse), // always 1/16 of mem_ref_clk .CLKOUT3 (pll_clk3_out), .CLKOUT4 (auxout_clk_i), .CLKOUT5 (), .DO (), .DRDY (), .LOCKED (pll_locked_i), .CLKFBIN (pll_clkfbout), .CLKIN1 (mmcm_clk), .CLKIN2 (), .CLKINSEL (1'b1), .DADDR (7'b0), .DCLK (1'b0), .DEN (1'b0), .DI (16'b0), .DWE (1'b0), .PWRDWN (1'b0), .RST ( sys_rst_act_hi) ); BUFH u_bufh_auxout_clk ( .O (auxout_clk), .I (auxout_clk_i) ); BUFG u_bufg_clkdiv0 ( .O (clk_bufg), .I (clk_pll_i) ); BUFH u_bufh_pll_clk3 ( .O (pll_clk3), .I (pll_clk3_out) ); localparam real MMCM_VCO_PERIOD = 1000000.0/MMCM_VCO; //synthesis translate_off initial begin $display("############# MMCME2_ADV Parameters #############\n"); $display("MMCM_MULT_F = %d", MMCM_MULT_F); $display("MMCM_VCO_FREQ (MHz) = %7.3f", MMCM_VCO*1000.0); $display("MMCM_VCO_PERIOD = %7.3f", MMCM_VCO_PERIOD); $display("#################################################\n"); end //synthesis translate_on generate if (UI_EXTRA_CLOCKS == "TRUE") begin: gen_ui_extra_clocks localparam MMCM_CLKOUT0_DIVIDE_CAL = (MMCM_CLKOUT0_EN == "TRUE") ? MMCM_CLKOUT0_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT1_DIVIDE_CAL = (MMCM_CLKOUT1_EN == "TRUE") ? MMCM_CLKOUT1_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT2_DIVIDE_CAL = (MMCM_CLKOUT2_EN == "TRUE") ? MMCM_CLKOUT2_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT3_DIVIDE_CAL = (MMCM_CLKOUT3_EN == "TRUE") ? MMCM_CLKOUT3_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT4_DIVIDE_CAL = (MMCM_CLKOUT4_EN == "TRUE") ? MMCM_CLKOUT4_DIVIDE : MMCM_MULT_F; MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("BUF_IN"), .STARTUP_WAIT ("FALSE"), // .DIVCLK_DIVIDE (1), .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), .CLKFBOUT_MULT_F (MMCM_MULT_F), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (MMCM_CLKOUT0_DIVIDE_CAL), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), .CLKOUT1_DIVIDE (MMCM_CLKOUT1_DIVIDE_CAL), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKOUT2_DIVIDE (MMCM_CLKOUT2_DIVIDE_CAL), .CLKOUT2_PHASE (0.000), .CLKOUT2_DUTY_CYCLE (0.500), .CLKOUT2_USE_FINE_PS ("FALSE"), .CLKOUT3_DIVIDE (MMCM_CLKOUT3_DIVIDE_CAL), .CLKOUT3_PHASE (0.000), .CLKOUT3_DUTY_CYCLE (0.500), .CLKOUT3_USE_FINE_PS ("FALSE"), .CLKOUT4_DIVIDE (MMCM_CLKOUT4_DIVIDE_CAL), .CLKOUT4_PHASE (0.000), .CLKOUT4_DUTY_CYCLE (0.500), .CLKOUT4_USE_FINE_PS ("FALSE"), .CLKOUT5_DIVIDE (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), .CLKOUT5_PHASE (0.000), .CLKOUT5_DUTY_CYCLE (0.500), .CLKOUT5_USE_FINE_PS ("TRUE"), .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (clk_pll_i), .CLKFBOUTB (), .CLKOUT0 (mmcm_clkout0), .CLKOUT0B (), .CLKOUT1 (mmcm_clkout1), .CLKOUT1B (), .CLKOUT2 (mmcm_clkout2), .CLKOUT2B (), .CLKOUT3 (mmcm_clkout3), .CLKOUT3B (), .CLKOUT4 (mmcm_clkout4), .CLKOUT5 (mmcm_ps_clk_bufg_in), .CLKOUT6 (), // Input clock control .CLKFBIN (clk_bufg), // From BUFH network .CLKIN1 (pll_clk3), // From PLL .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (clk), .PSEN (psen), .PSINCDEC (psincdec), .PSDONE (psdone), // Other control and status signals .LOCKED (MMCM_Locked_i), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (~pll_locked_i)); BUFG u_bufg_ui_addn_clk_0 ( .O (ui_addn_clk_0), .I (mmcm_clkout0) ); BUFG u_bufg_ui_addn_clk_1 ( .O (ui_addn_clk_1), .I (mmcm_clkout1) ); BUFG u_bufg_ui_addn_clk_2 ( .O (ui_addn_clk_2), .I (mmcm_clkout2) ); BUFG u_bufg_ui_addn_clk_3 ( .O (ui_addn_clk_3), .I (mmcm_clkout3) ); BUFG u_bufg_ui_addn_clk_4 ( .O (ui_addn_clk_4), .I (mmcm_clkout4) ); BUFG u_bufg_mmcm_ps_clk ( .O (mmcm_ps_clk), .I (mmcm_ps_clk_bufg_in) ); end else begin: gen_mmcm MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("BUF_IN"), .STARTUP_WAIT ("FALSE"), // .DIVCLK_DIVIDE (1), .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), .CLKFBOUT_MULT_F (MMCM_MULT_F), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("TRUE"), .CLKOUT1_DIVIDE (), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (clk_pll_i), .CLKFBOUTB (), .CLKOUT0 (mmcm_ps_clk_bufg_in), .CLKOUT0B (), .CLKOUT1 (), .CLKOUT1B (), .CLKOUT2 (), .CLKOUT2B (), .CLKOUT3 (), .CLKOUT3B (), .CLKOUT4 (), .CLKOUT5 (), .CLKOUT6 (), // Input clock control .CLKFBIN (clk_bufg), // From BUFH network .CLKIN1 (pll_clk3), // From PLL .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (clk), .PSEN (psen), .PSINCDEC (psincdec), .PSDONE (psdone), // Other control and status signals .LOCKED (MMCM_Locked_i), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (~pll_locked_i)); BUFG u_bufg_mmcm_ps_clk ( .O (mmcm_ps_clk), .I (mmcm_ps_clk_bufg_in) ); end // block: gen_mmcm endgenerate //*************************************************************************** // Generate poc_sample_pd. // // As the phase shift clocks precesses around kclk, it also precesses // around the fabric clock. Noise may be generated as output of the // IDDR is registered into the fabric clock domain. // // The mmcm_ps_clk signal runs at half the rate of the fabric clock. // This means that there are two rising edges of fabric clock per mmcm_ps_clk. // If we can guarantee that the POC uses the data sampled on the second // fabric clock, then we are certain that the setup time to the second // fabric clock is greater than 1 fabric clock cycle. // // To predict when the phase detctor output is from this second edge, we // need to know two things. The initial phase of fabric clock and mmcm_ps_clk // and the number of phase offsets set into the mmcm. The later is a // trivial count of the PSEN signal. // // The former is a bit tricky because latching a clock with a clock is // not well defined. This problem is solved by generating a signal // the goes high on the first rising edge of mmcm_ps_clk. Logic in // the fabric domain can look at this signal and then develop an analog // the mmcm_ps_clk with zero offset. // // This all depends on the timing tools making the timing work when // when the mmcm phase offset is zero. // // poc_sample_pd tells the POC when to sample the phase detector output. // Setup from the IDDR to the fabric clock is always one plus some // fraction of the fabric clock. //*************************************************************************** localparam ONE = 1; localparam integer TAPSPERFCLK = 56 * MMCM_MULT_F; localparam TAPSPERFCLK_MINUS_ONE = TAPSPERFCLK - 1; localparam QCNTR_WIDTH = clogb2(TAPSPERFCLK); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 reg [QCNTR_WIDTH-1:0] qcntr_ns, qcntr_r; always @(posedge clk) qcntr_r <= #TCQ qcntr_ns; reg inv_poc_sample_ns, inv_poc_sample_r; always @(posedge clk) inv_poc_sample_r <= #TCQ inv_poc_sample_ns; always @(*) begin qcntr_ns = qcntr_r; inv_poc_sample_ns = inv_poc_sample_r; if (rstdiv0) begin qcntr_ns = TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0]; inv_poc_sample_ns = 1'b1; end else if (psen) begin if (qcntr_r < TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0]) qcntr_ns = (qcntr_r + ONE[QCNTR_WIDTH-1:0]); else begin qcntr_ns = {QCNTR_WIDTH{1'b0}}; inv_poc_sample_ns = ~inv_poc_sample_r; end end end // Be vewy vewy careful to make sure this path is aligned with the // phase detector out pipeline. reg first_rising_ps_clk_ns, first_rising_ps_clk_r; always @(posedge mmcm_ps_clk) first_rising_ps_clk_r <= #TCQ first_rising_ps_clk_ns; always @(*) first_rising_ps_clk_ns = ~rstdiv0; reg mmcm_hi0_ns, mmcm_hi0_r; always @(posedge clk) mmcm_hi0_r <= #TCQ mmcm_hi0_ns; always @(*) mmcm_hi0_ns = ~first_rising_ps_clk_r || ~mmcm_hi0_r; reg poc_sample_pd_ns, poc_sample_pd_r; always @(*) poc_sample_pd_ns = inv_poc_sample_ns ^ mmcm_hi0_r; always @(posedge clk) poc_sample_pd_r <= #TCQ poc_sample_pd_ns; assign poc_sample_pd = poc_sample_pd_r; //*************************************************************************** // Make sure logic acheives 90 degree setup time from rising mmcm_ps_clk // to the appropriate edge of fabric clock //*************************************************************************** //synthesis translate_off generate if ( tCK <= 2500 ) begin : check_ocal_timing localparam CLK_PERIOD_PS = MMCM_VCO_PERIOD * MMCM_MULT_F; localparam integer CLK_PERIOD_PS_DIV4 = CLK_PERIOD_PS/4; time rising_mmcm_ps_clk; always @(posedge mmcm_ps_clk) rising_mmcm_ps_clk = $time(); time pdiff; // Not used, except in waveform plots. always @(posedge clk) pdiff = $time() - rising_mmcm_ps_clk; end endgenerate //synthesis translate_on //*************************************************************************** // RESET SYNCHRONIZATION DESCRIPTION: // Various resets are generated to ensure that: // 1. All resets are synchronously deasserted with respect to the clock // domain they are interfacing to. There are several different clock // domains - each one will receive a synchronized reset. // 2. The reset deassertion order starts with deassertion of SYS_RST, // followed by deassertion of resets for various parts of the design // (see "RESET ORDER" below) based on the lock status of PLLE2s. // RESET ORDER: // 1. User deasserts SYS_RST // 2. Reset PLLE2 and IDELAYCTRL // 3. Wait for PLLE2 and IDELAYCTRL to lock // 4. Release reset for all I/O primitives and internal logic // OTHER NOTES: // 1. Asynchronously assert reset. This way we can assert reset even if // there is no clock (needed for things like 3-stating output buffers // to prevent initial bus contention). Reset deassertion is synchronous. //*************************************************************************** //***************************************************************** // CLKDIV logic reset //***************************************************************** // Wait for PLLE2 and IDELAYCTRL to lock before releasing reset // current O,25.0 unisim phaser_ref never locks. Need to find out why . generate if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_300_400 assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[1] | ~ref_dll_lock | ~MMCM_Locked_i; end else begin: rst_tmp_200 assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[0] | ~ref_dll_lock | ~MMCM_Locked_i; end endgenerate always @(posedge clk_bufg or posedge rst_tmp) begin if (rst_tmp) begin rstdiv0_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; rstdiv0_sync_r1 <= #TCQ 1'b1 ; end else begin rstdiv0_sync_r <= #TCQ rstdiv0_sync_r << 1; rstdiv0_sync_r1 <= #TCQ rstdiv0_sync_r[RST_DIV_SYNC_NUM-2]; end end assign rstdiv0 = rstdiv0_sync_r1 ; //IDDR rest always @(posedge mmcm_ps_clk or posedge rst_tmp) begin if (rst_tmp) begin rst_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; rst_sync_r1 <= #TCQ 1'b1 ; end else begin rst_sync_r <= #TCQ rst_sync_r << 1; rst_sync_r1 <= #TCQ rst_sync_r[RST_DIV_SYNC_NUM-2]; end end assign iddr_rst = rst_sync_r1 ; generate if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_phaser_ref_300_400 assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[1]; end else begin: rst_tmp_phaser_ref_200 assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[0]; end endgenerate always @(posedge clk_bufg or posedge rst_tmp_phaser_ref) if (rst_tmp_phaser_ref) rst_phaser_ref_sync_r <= #TCQ {RST_DIV_SYNC_NUM{1'b1}}; else rst_phaser_ref_sync_r <= #TCQ rst_phaser_ref_sync_r << 1; assign rst_phaser_ref = rst_phaser_ref_sync_r[RST_DIV_SYNC_NUM-1]; endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: infrastructure.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ // \ \ / \ Date Created:Tue Jun 30 2009 // \___\/\___\ // //Device: Virtex-6 //Design Name: DDR3 SDRAM //Purpose: // Clock generation/distribution and reset synchronization //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: infrastructure.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ **$Date: 2011/06/02 08:34:56 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/infrastructure.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_infrastructure # ( parameter SIMULATION = "FALSE", // Should be TRUE during design simulations and // FALSE during implementations parameter TCQ = 100, // clk->out delay (sim only) parameter CLKIN_PERIOD = 3000, // Memory clock period parameter nCK_PER_CLK = 2, // Fabric clk period:Memory clk period parameter SYSCLK_TYPE = "DIFFERENTIAL", // input clock type // "DIFFERENTIAL","SINGLE_ENDED" parameter UI_EXTRA_CLOCKS = "FALSE", // Generates extra clocks as // 1/2, 1/4 and 1/8 of fabrick clock. // Valid for DDR2/DDR3 AXI interfaces // based on GUI selection parameter CLKFBOUT_MULT = 4, // write PLL VCO multiplier parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor parameter CLKOUT0_PHASE = 45.0, // VCO output divisor for clkout0 parameter CLKOUT0_DIVIDE = 16, // VCO output divisor for PLL clkout0 parameter CLKOUT1_DIVIDE = 4, // VCO output divisor for PLL clkout1 parameter CLKOUT2_DIVIDE = 64, // VCO output divisor for PLL clkout2 parameter CLKOUT3_DIVIDE = 16, // VCO output divisor for PLL clkout3 parameter MMCM_VCO = 1200, // Max Freq (MHz) of MMCM VCO parameter MMCM_MULT_F = 4, // write MMCM VCO multiplier parameter MMCM_DIVCLK_DIVIDE = 1, // write MMCM VCO divisor parameter MMCM_CLKOUT0_EN = "FALSE", // Enabled (or) Disable MMCM clkout0 parameter MMCM_CLKOUT1_EN = "FALSE", // Enabled (or) Disable MMCM clkout1 parameter MMCM_CLKOUT2_EN = "FALSE", // Enabled (or) Disable MMCM clkout2 parameter MMCM_CLKOUT3_EN = "FALSE", // Enabled (or) Disable MMCM clkout3 parameter MMCM_CLKOUT4_EN = "FALSE", // Enabled (or) Disable MMCM clkout4 parameter MMCM_CLKOUT0_DIVIDE = 1, // VCO output divisor for MMCM clkout0 parameter MMCM_CLKOUT1_DIVIDE = 1, // VCO output divisor for MMCM clkout1 parameter MMCM_CLKOUT2_DIVIDE = 1, // VCO output divisor for MMCM clkout2 parameter MMCM_CLKOUT3_DIVIDE = 1, // VCO output divisor for MMCM clkout3 parameter MMCM_CLKOUT4_DIVIDE = 1, // VCO output divisor for MMCM clkout4 parameter RST_ACT_LOW = 1, parameter tCK = 1250, // memory tCK paramter. // # = Clock Period in pS. parameter MEM_TYPE = "DDR3" ) ( // Clock inputs input mmcm_clk, // System clock diff input // System reset input input sys_rst, // core reset from user application // PLLE2/IDELAYCTRL Lock status input [1:0] iodelay_ctrl_rdy, // IDELAYCTRL lock status // Clock outputs output clk, // fabric clock freq ; either half rate or quarter rate and is // determined by PLL parameters settings. output mem_refclk, // equal to memory clock output freq_refclk, // freq above 400 MHz: set freq_refclk = mem_refclk // freq below 400 MHz: set freq_refclk = 2* mem_refclk or 4* mem_refclk; // to hard PHY for phaser output sync_pulse, // exactly 1/16 of mem_refclk and the sync pulse is exactly 1 memref_clk wide output auxout_clk, // IO clk used to clock out Aux_Out ports output mmcm_ps_clk, // Phase shift clock output poc_sample_pd, // Tell POC when to sample phase detector output. output ui_addn_clk_0, // MMCM out0 clk output ui_addn_clk_1, // MMCM out1 clk output ui_addn_clk_2, // MMCM out2 clk output ui_addn_clk_3, // MMCM out3 clk output ui_addn_clk_4, // MMCM out4 clk output pll_locked, // locked output from PLLE2_ADV output mmcm_locked, // locked output from MMCME2_ADV // Reset outputs output rstdiv0, // Reset CLK and CLKDIV logic (incl I/O), output iddr_rst ,output rst_phaser_ref ,input ref_dll_lock ,input psen ,input psincdec ,output psdone ); // # of clock cycles to delay deassertion of reset. Needs to be a fairly // high number not so much for metastability protection, but to give time // for reset (i.e. stable clock cycles) to propagate through all state // machines and to all control signals (i.e. not all control signals have // resets, instead they rely on base state logic being reset, and the effect // of that reset propagating through the logic). Need this because we may not // be getting stable clock cycles while reset asserted (i.e. since reset // depends on DCM lock status) localparam RST_SYNC_NUM = 25; // Round up for clk reset delay to ensure that CLKDIV reset deassertion // occurs at same time or after CLK reset deassertion (still need to // consider route delay - add one or two extra cycles to be sure!) localparam RST_DIV_SYNC_NUM = (RST_SYNC_NUM+1)/2; // Input clock is assumed to be equal to the memory clock frequency // User should change the parameter as necessary if a different input // clock frequency is used localparam real CLKIN1_PERIOD_NS = CLKIN_PERIOD / 1000.0; localparam CLKOUT4_DIVIDE = 2 * CLKOUT1_DIVIDE; localparam integer VCO_PERIOD = (CLKIN1_PERIOD_NS * DIVCLK_DIVIDE * 1000) / CLKFBOUT_MULT; localparam CLKOUT0_PERIOD = VCO_PERIOD * CLKOUT0_DIVIDE; localparam CLKOUT1_PERIOD = VCO_PERIOD * CLKOUT1_DIVIDE; localparam CLKOUT2_PERIOD = VCO_PERIOD * CLKOUT2_DIVIDE; localparam CLKOUT3_PERIOD = VCO_PERIOD * CLKOUT3_DIVIDE; localparam CLKOUT4_PERIOD = VCO_PERIOD * CLKOUT4_DIVIDE; localparam CLKOUT4_PHASE = (SIMULATION == "TRUE") ? 22.5 : 168.75; localparam real CLKOUT3_PERIOD_NS = CLKOUT3_PERIOD / 1000.0; localparam real CLKOUT4_PERIOD_NS = CLKOUT4_PERIOD / 1000.0; //synthesis translate_off initial begin $display("############# Write Clocks PLLE2_ADV Parameters #############\n"); $display("nCK_PER_CLK = %7d", nCK_PER_CLK ); $display("CLK_PERIOD = %7d", CLKIN_PERIOD ); $display("CLKIN1_PERIOD = %7.3f", CLKIN1_PERIOD_NS); $display("DIVCLK_DIVIDE = %7d", DIVCLK_DIVIDE ); $display("CLKFBOUT_MULT = %7d", CLKFBOUT_MULT ); $display("VCO_PERIOD = %7.1f", VCO_PERIOD ); $display("CLKOUT0_DIVIDE_F = %7d", CLKOUT0_DIVIDE ); $display("CLKOUT1_DIVIDE = %7d", CLKOUT1_DIVIDE ); $display("CLKOUT2_DIVIDE = %7d", CLKOUT2_DIVIDE ); $display("CLKOUT3_DIVIDE = %7d", CLKOUT3_DIVIDE ); $display("CLKOUT0_PERIOD = %7d", CLKOUT0_PERIOD ); $display("CLKOUT1_PERIOD = %7d", CLKOUT1_PERIOD ); $display("CLKOUT2_PERIOD = %7d", CLKOUT2_PERIOD ); $display("CLKOUT3_PERIOD = %7d", CLKOUT3_PERIOD ); $display("CLKOUT4_PERIOD = %7d", CLKOUT4_PERIOD ); $display("############################################################\n"); end //synthesis translate_on wire clk_bufg; wire clk_pll; wire clkfbout_pll; wire mmcm_clkfbout; wire pll_locked_i /* synthesis syn_maxfan = 10 */; (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-2:0] rstdiv0_sync_r; wire rst_tmp; (* max_fanout = 50 *) reg rstdiv0_sync_r1 /* synthesis syn_maxfan = 50 */; reg [RST_DIV_SYNC_NUM-2:0] rst_sync_r; (* max_fanout = 10 *) reg rst_sync_r1 /* synthesis syn_maxfan = 10 */; wire sys_rst_act_hi; wire rst_tmp_phaser_ref; (* max_fanout = 50 *) reg [RST_DIV_SYNC_NUM-1:0] rst_phaser_ref_sync_r /* synthesis syn_maxfan = 10 */; // Instantiation of the MMCM primitive wire clkfbout; wire MMCM_Locked_i; wire mmcm_clkout0; wire mmcm_clkout1; wire mmcm_clkout2; wire mmcm_clkout3; wire mmcm_clkout4; wire mmcm_ps_clk_bufg_in; wire pll_clk3_out; wire pll_clk3; assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst; //*************************************************************************** // Assign global clocks: // 2. clk : Half rate / Quarter rate(used for majority of internal logic) //*************************************************************************** assign clk = clk_bufg; assign pll_locked = pll_locked_i & MMCM_Locked_i; assign mmcm_locked = MMCM_Locked_i; //*************************************************************************** // Global base clock generation and distribution //*************************************************************************** //***************************************************************** // NOTES ON CALCULTING PROPER VCO FREQUENCY // 1. VCO frequency = // 1/((DIVCLK_DIVIDE * CLKIN_PERIOD)/(CLKFBOUT_MULT * nCK_PER_CLK)) // 2. VCO frequency must be in the range [TBD, TBD] //***************************************************************** PLLE2_ADV # ( .BANDWIDTH ("OPTIMIZED"), .COMPENSATION ("INTERNAL"), .STARTUP_WAIT ("FALSE"), .CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), // 4 freq_ref .CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), // 4 mem_ref .CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), // 16 sync .CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), // 16 sysclk .CLKOUT4_DIVIDE (CLKOUT4_DIVIDE), .CLKOUT5_DIVIDE (), .DIVCLK_DIVIDE (DIVCLK_DIVIDE), .CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_PHASE (0.000), .CLKIN1_PERIOD (CLKIN1_PERIOD_NS), .CLKIN2_PERIOD (), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_PHASE (CLKOUT0_PHASE), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_PHASE (0.000), .CLKOUT2_DUTY_CYCLE (1.0/16.0), .CLKOUT2_PHASE (9.84375), // PHASE shift is required for sync pulse generation. .CLKOUT3_DUTY_CYCLE (0.500), .CLKOUT3_PHASE (0.000), .CLKOUT4_DUTY_CYCLE (0.500), .CLKOUT4_PHASE (CLKOUT4_PHASE), .CLKOUT5_DUTY_CYCLE (0.500), .CLKOUT5_PHASE (0.000), .REF_JITTER1 (0.010), .REF_JITTER2 (0.010) ) plle2_i ( .CLKFBOUT (pll_clkfbout), .CLKOUT0 (freq_refclk), .CLKOUT1 (mem_refclk), .CLKOUT2 (sync_pulse), // always 1/16 of mem_ref_clk .CLKOUT3 (pll_clk3_out), .CLKOUT4 (auxout_clk_i), .CLKOUT5 (), .DO (), .DRDY (), .LOCKED (pll_locked_i), .CLKFBIN (pll_clkfbout), .CLKIN1 (mmcm_clk), .CLKIN2 (), .CLKINSEL (1'b1), .DADDR (7'b0), .DCLK (1'b0), .DEN (1'b0), .DI (16'b0), .DWE (1'b0), .PWRDWN (1'b0), .RST ( sys_rst_act_hi) ); BUFH u_bufh_auxout_clk ( .O (auxout_clk), .I (auxout_clk_i) ); BUFG u_bufg_clkdiv0 ( .O (clk_bufg), .I (clk_pll_i) ); BUFH u_bufh_pll_clk3 ( .O (pll_clk3), .I (pll_clk3_out) ); localparam real MMCM_VCO_PERIOD = 1000000.0/MMCM_VCO; //synthesis translate_off initial begin $display("############# MMCME2_ADV Parameters #############\n"); $display("MMCM_MULT_F = %d", MMCM_MULT_F); $display("MMCM_VCO_FREQ (MHz) = %7.3f", MMCM_VCO*1000.0); $display("MMCM_VCO_PERIOD = %7.3f", MMCM_VCO_PERIOD); $display("#################################################\n"); end //synthesis translate_on generate if (UI_EXTRA_CLOCKS == "TRUE") begin: gen_ui_extra_clocks localparam MMCM_CLKOUT0_DIVIDE_CAL = (MMCM_CLKOUT0_EN == "TRUE") ? MMCM_CLKOUT0_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT1_DIVIDE_CAL = (MMCM_CLKOUT1_EN == "TRUE") ? MMCM_CLKOUT1_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT2_DIVIDE_CAL = (MMCM_CLKOUT2_EN == "TRUE") ? MMCM_CLKOUT2_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT3_DIVIDE_CAL = (MMCM_CLKOUT3_EN == "TRUE") ? MMCM_CLKOUT3_DIVIDE : MMCM_MULT_F; localparam MMCM_CLKOUT4_DIVIDE_CAL = (MMCM_CLKOUT4_EN == "TRUE") ? MMCM_CLKOUT4_DIVIDE : MMCM_MULT_F; MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("BUF_IN"), .STARTUP_WAIT ("FALSE"), // .DIVCLK_DIVIDE (1), .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), .CLKFBOUT_MULT_F (MMCM_MULT_F), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (MMCM_CLKOUT0_DIVIDE_CAL), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), .CLKOUT1_DIVIDE (MMCM_CLKOUT1_DIVIDE_CAL), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKOUT2_DIVIDE (MMCM_CLKOUT2_DIVIDE_CAL), .CLKOUT2_PHASE (0.000), .CLKOUT2_DUTY_CYCLE (0.500), .CLKOUT2_USE_FINE_PS ("FALSE"), .CLKOUT3_DIVIDE (MMCM_CLKOUT3_DIVIDE_CAL), .CLKOUT3_PHASE (0.000), .CLKOUT3_DUTY_CYCLE (0.500), .CLKOUT3_USE_FINE_PS ("FALSE"), .CLKOUT4_DIVIDE (MMCM_CLKOUT4_DIVIDE_CAL), .CLKOUT4_PHASE (0.000), .CLKOUT4_DUTY_CYCLE (0.500), .CLKOUT4_USE_FINE_PS ("FALSE"), .CLKOUT5_DIVIDE (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), .CLKOUT5_PHASE (0.000), .CLKOUT5_DUTY_CYCLE (0.500), .CLKOUT5_USE_FINE_PS ("TRUE"), .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (clk_pll_i), .CLKFBOUTB (), .CLKOUT0 (mmcm_clkout0), .CLKOUT0B (), .CLKOUT1 (mmcm_clkout1), .CLKOUT1B (), .CLKOUT2 (mmcm_clkout2), .CLKOUT2B (), .CLKOUT3 (mmcm_clkout3), .CLKOUT3B (), .CLKOUT4 (mmcm_clkout4), .CLKOUT5 (mmcm_ps_clk_bufg_in), .CLKOUT6 (), // Input clock control .CLKFBIN (clk_bufg), // From BUFH network .CLKIN1 (pll_clk3), // From PLL .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (clk), .PSEN (psen), .PSINCDEC (psincdec), .PSDONE (psdone), // Other control and status signals .LOCKED (MMCM_Locked_i), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (~pll_locked_i)); BUFG u_bufg_ui_addn_clk_0 ( .O (ui_addn_clk_0), .I (mmcm_clkout0) ); BUFG u_bufg_ui_addn_clk_1 ( .O (ui_addn_clk_1), .I (mmcm_clkout1) ); BUFG u_bufg_ui_addn_clk_2 ( .O (ui_addn_clk_2), .I (mmcm_clkout2) ); BUFG u_bufg_ui_addn_clk_3 ( .O (ui_addn_clk_3), .I (mmcm_clkout3) ); BUFG u_bufg_ui_addn_clk_4 ( .O (ui_addn_clk_4), .I (mmcm_clkout4) ); BUFG u_bufg_mmcm_ps_clk ( .O (mmcm_ps_clk), .I (mmcm_ps_clk_bufg_in) ); end else begin: gen_mmcm MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("BUF_IN"), .STARTUP_WAIT ("FALSE"), // .DIVCLK_DIVIDE (1), .DIVCLK_DIVIDE (MMCM_DIVCLK_DIVIDE), .CLKFBOUT_MULT_F (MMCM_MULT_F), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (((MMCM_MULT_F*2)/MMCM_DIVCLK_DIVIDE)), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("TRUE"), .CLKOUT1_DIVIDE (), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (CLKOUT3_PERIOD_NS), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (clk_pll_i), .CLKFBOUTB (), .CLKOUT0 (mmcm_ps_clk_bufg_in), .CLKOUT0B (), .CLKOUT1 (), .CLKOUT1B (), .CLKOUT2 (), .CLKOUT2B (), .CLKOUT3 (), .CLKOUT3B (), .CLKOUT4 (), .CLKOUT5 (), .CLKOUT6 (), // Input clock control .CLKFBIN (clk_bufg), // From BUFH network .CLKIN1 (pll_clk3), // From PLL .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (clk), .PSEN (psen), .PSINCDEC (psincdec), .PSDONE (psdone), // Other control and status signals .LOCKED (MMCM_Locked_i), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (~pll_locked_i)); BUFG u_bufg_mmcm_ps_clk ( .O (mmcm_ps_clk), .I (mmcm_ps_clk_bufg_in) ); end // block: gen_mmcm endgenerate //*************************************************************************** // Generate poc_sample_pd. // // As the phase shift clocks precesses around kclk, it also precesses // around the fabric clock. Noise may be generated as output of the // IDDR is registered into the fabric clock domain. // // The mmcm_ps_clk signal runs at half the rate of the fabric clock. // This means that there are two rising edges of fabric clock per mmcm_ps_clk. // If we can guarantee that the POC uses the data sampled on the second // fabric clock, then we are certain that the setup time to the second // fabric clock is greater than 1 fabric clock cycle. // // To predict when the phase detctor output is from this second edge, we // need to know two things. The initial phase of fabric clock and mmcm_ps_clk // and the number of phase offsets set into the mmcm. The later is a // trivial count of the PSEN signal. // // The former is a bit tricky because latching a clock with a clock is // not well defined. This problem is solved by generating a signal // the goes high on the first rising edge of mmcm_ps_clk. Logic in // the fabric domain can look at this signal and then develop an analog // the mmcm_ps_clk with zero offset. // // This all depends on the timing tools making the timing work when // when the mmcm phase offset is zero. // // poc_sample_pd tells the POC when to sample the phase detector output. // Setup from the IDDR to the fabric clock is always one plus some // fraction of the fabric clock. //*************************************************************************** localparam ONE = 1; localparam integer TAPSPERFCLK = 56 * MMCM_MULT_F; localparam TAPSPERFCLK_MINUS_ONE = TAPSPERFCLK - 1; localparam QCNTR_WIDTH = clogb2(TAPSPERFCLK); function integer clogb2 (input integer size); // ceiling logb2 begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // clogb2 reg [QCNTR_WIDTH-1:0] qcntr_ns, qcntr_r; always @(posedge clk) qcntr_r <= #TCQ qcntr_ns; reg inv_poc_sample_ns, inv_poc_sample_r; always @(posedge clk) inv_poc_sample_r <= #TCQ inv_poc_sample_ns; always @(*) begin qcntr_ns = qcntr_r; inv_poc_sample_ns = inv_poc_sample_r; if (rstdiv0) begin qcntr_ns = TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0]; inv_poc_sample_ns = 1'b1; end else if (psen) begin if (qcntr_r < TAPSPERFCLK_MINUS_ONE[QCNTR_WIDTH-1:0]) qcntr_ns = (qcntr_r + ONE[QCNTR_WIDTH-1:0]); else begin qcntr_ns = {QCNTR_WIDTH{1'b0}}; inv_poc_sample_ns = ~inv_poc_sample_r; end end end // Be vewy vewy careful to make sure this path is aligned with the // phase detector out pipeline. reg first_rising_ps_clk_ns, first_rising_ps_clk_r; always @(posedge mmcm_ps_clk) first_rising_ps_clk_r <= #TCQ first_rising_ps_clk_ns; always @(*) first_rising_ps_clk_ns = ~rstdiv0; reg mmcm_hi0_ns, mmcm_hi0_r; always @(posedge clk) mmcm_hi0_r <= #TCQ mmcm_hi0_ns; always @(*) mmcm_hi0_ns = ~first_rising_ps_clk_r || ~mmcm_hi0_r; reg poc_sample_pd_ns, poc_sample_pd_r; always @(*) poc_sample_pd_ns = inv_poc_sample_ns ^ mmcm_hi0_r; always @(posedge clk) poc_sample_pd_r <= #TCQ poc_sample_pd_ns; assign poc_sample_pd = poc_sample_pd_r; //*************************************************************************** // Make sure logic acheives 90 degree setup time from rising mmcm_ps_clk // to the appropriate edge of fabric clock //*************************************************************************** //synthesis translate_off generate if ( tCK <= 2500 ) begin : check_ocal_timing localparam CLK_PERIOD_PS = MMCM_VCO_PERIOD * MMCM_MULT_F; localparam integer CLK_PERIOD_PS_DIV4 = CLK_PERIOD_PS/4; time rising_mmcm_ps_clk; always @(posedge mmcm_ps_clk) rising_mmcm_ps_clk = $time(); time pdiff; // Not used, except in waveform plots. always @(posedge clk) pdiff = $time() - rising_mmcm_ps_clk; end endgenerate //synthesis translate_on //*************************************************************************** // RESET SYNCHRONIZATION DESCRIPTION: // Various resets are generated to ensure that: // 1. All resets are synchronously deasserted with respect to the clock // domain they are interfacing to. There are several different clock // domains - each one will receive a synchronized reset. // 2. The reset deassertion order starts with deassertion of SYS_RST, // followed by deassertion of resets for various parts of the design // (see "RESET ORDER" below) based on the lock status of PLLE2s. // RESET ORDER: // 1. User deasserts SYS_RST // 2. Reset PLLE2 and IDELAYCTRL // 3. Wait for PLLE2 and IDELAYCTRL to lock // 4. Release reset for all I/O primitives and internal logic // OTHER NOTES: // 1. Asynchronously assert reset. This way we can assert reset even if // there is no clock (needed for things like 3-stating output buffers // to prevent initial bus contention). Reset deassertion is synchronous. //*************************************************************************** //***************************************************************** // CLKDIV logic reset //***************************************************************** // Wait for PLLE2 and IDELAYCTRL to lock before releasing reset // current O,25.0 unisim phaser_ref never locks. Need to find out why . generate if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_300_400 assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[1] | ~ref_dll_lock | ~MMCM_Locked_i; end else begin: rst_tmp_200 assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy[0] | ~ref_dll_lock | ~MMCM_Locked_i; end endgenerate always @(posedge clk_bufg or posedge rst_tmp) begin if (rst_tmp) begin rstdiv0_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; rstdiv0_sync_r1 <= #TCQ 1'b1 ; end else begin rstdiv0_sync_r <= #TCQ rstdiv0_sync_r << 1; rstdiv0_sync_r1 <= #TCQ rstdiv0_sync_r[RST_DIV_SYNC_NUM-2]; end end assign rstdiv0 = rstdiv0_sync_r1 ; //IDDR rest always @(posedge mmcm_ps_clk or posedge rst_tmp) begin if (rst_tmp) begin rst_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}}; rst_sync_r1 <= #TCQ 1'b1 ; end else begin rst_sync_r <= #TCQ rst_sync_r << 1; rst_sync_r1 <= #TCQ rst_sync_r[RST_DIV_SYNC_NUM-2]; end end assign iddr_rst = rst_sync_r1 ; generate if (MEM_TYPE == "DDR3" && tCK <= 1500) begin: rst_tmp_phaser_ref_300_400 assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[1]; end else begin: rst_tmp_phaser_ref_200 assign rst_tmp_phaser_ref = sys_rst_act_hi | ~MMCM_Locked_i | ~iodelay_ctrl_rdy[0]; end endgenerate always @(posedge clk_bufg or posedge rst_tmp_phaser_ref) if (rst_tmp_phaser_ref) rst_phaser_ref_sync_r <= #TCQ {RST_DIV_SYNC_NUM{1'b1}}; else rst_phaser_ref_sync_r <= #TCQ rst_phaser_ref_sync_r << 1; assign rst_phaser_ref = rst_phaser_ref_sync_r[RST_DIV_SYNC_NUM-1]; endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : rank_mach.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // Top level rank machine structural block. This block // instantiates a configurable number of rank controller blocks. `timescale 1ps/1ps module mig_7series_v2_3_rank_mach # ( parameter BURST_MODE = "8", parameter CS_WIDTH = 4, parameter DRAM_TYPE = "DDR3", parameter MAINT_PRESCALER_DIV = 40, parameter nBANK_MACHS = 4, parameter nCKESR = 4, parameter nCK_PER_CLK = 2, parameter CL = 5, parameter CWL = 5, parameter DQRD2DQWR_DLY = 2, parameter nFAW = 30, parameter nREFRESH_BANK = 8, parameter nRRD = 4, parameter nWTR = 4, parameter PERIODIC_RD_TIMER_DIV = 20, parameter RANK_BM_BV_WIDTH = 16, parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter REFRESH_TIMER_DIV = 39, parameter ZQ_TIMER_DIV = 640000 ) (/*AUTOARG*/ // Outputs periodic_rd_rank_r, periodic_rd_r, maint_req_r, inhbt_act_faw_r, inhbt_rd, inhbt_wr, maint_rank_r, maint_zq_r, maint_sre_r, maint_srx_r, app_sr_active, app_ref_ack, app_zq_ack, col_rd_wr, maint_ref_zq_wip, // Inputs wr_this_rank_r, slot_1_present, slot_0_present, sending_row, sending_col, rst, rd_this_rank_r, rank_busy_r, periodic_rd_ack_r, maint_wip_r, insert_maint_r1, init_calib_complete, clk, app_zq_req, app_sr_req, app_ref_req, app_periodic_rd_req, act_this_rank_r ); /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; // To rank_cntrl0 of rank_cntrl.v input app_periodic_rd_req; // To rank_cntrl0 of rank_cntrl.v input app_ref_req; // To rank_cntrl0 of rank_cntrl.v input app_zq_req; // To rank_common0 of rank_common.v input app_sr_req; // To rank_common0 of rank_common.v input clk; // To rank_cntrl0 of rank_cntrl.v, ... input col_rd_wr; // To rank_cntrl0 of rank_cntrl.v, ... input init_calib_complete; // To rank_cntrl0 of rank_cntrl.v, ... input insert_maint_r1; // To rank_cntrl0 of rank_cntrl.v, ... input maint_wip_r; // To rank_common0 of rank_common.v input periodic_rd_ack_r; // To rank_common0 of rank_common.v input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; // To rank_cntrl0 of rank_cntrl.v input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; // To rank_cntrl0 of rank_cntrl.v input rst; // To rank_cntrl0 of rank_cntrl.v, ... input [nBANK_MACHS-1:0] sending_col; // To rank_cntrl0 of rank_cntrl.v input [nBANK_MACHS-1:0] sending_row; // To rank_cntrl0 of rank_cntrl.v input [7:0] slot_0_present; // To rank_common0 of rank_common.v input [7:0] slot_1_present; // To rank_common0 of rank_common.v input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // To rank_cntrl0 of rank_cntrl.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) output maint_req_r; // From rank_common0 of rank_common.v output periodic_rd_r; // From rank_common0 of rank_common.v output [RANK_WIDTH-1:0] periodic_rd_rank_r; // From rank_common0 of rank_common.v // End of automatics /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire maint_prescaler_tick_r; // From rank_common0 of rank_common.v wire refresh_tick; // From rank_common0 of rank_common.v // End of automatics output [RANKS-1:0] inhbt_act_faw_r; output [RANKS-1:0] inhbt_rd; output [RANKS-1:0] inhbt_wr; output [RANK_WIDTH-1:0] maint_rank_r; output maint_zq_r; output maint_sre_r; output maint_srx_r; output app_sr_active; output app_ref_ack; output app_zq_ack; output maint_ref_zq_wip; wire [RANKS-1:0] refresh_request; wire [RANKS-1:0] periodic_rd_request; wire [RANKS-1:0] clear_periodic_rd_request; genvar ID; generate for (ID=0; ID<RANKS; ID=ID+1) begin:rank_cntrl mig_7series_v2_3_rank_cntrl # (/*AUTOINSTPARAM*/ // Parameters .BURST_MODE (BURST_MODE), .ID (ID), .nBANK_MACHS (nBANK_MACHS), .nCK_PER_CLK (nCK_PER_CLK), .CL (CL), .CWL (CWL), .DQRD2DQWR_DLY (DQRD2DQWR_DLY), .nFAW (nFAW), .nREFRESH_BANK (nREFRESH_BANK), .nRRD (nRRD), .nWTR (nWTR), .PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV), .RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .REFRESH_TIMER_DIV (REFRESH_TIMER_DIV)) rank_cntrl0 (.clear_periodic_rd_request (clear_periodic_rd_request[ID]), .inhbt_act_faw_r (inhbt_act_faw_r[ID]), .inhbt_rd (inhbt_rd[ID]), .inhbt_wr (inhbt_wr[ID]), .periodic_rd_request (periodic_rd_request[ID]), .refresh_request (refresh_request[ID]), /*AUTOINST*/ // Inputs .clk (clk), .rst (rst), .col_rd_wr (col_rd_wr), .sending_row (sending_row[nBANK_MACHS-1:0]), .act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .sending_col (sending_col[nBANK_MACHS-1:0]), .wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]), .app_ref_req (app_ref_req), .init_calib_complete (init_calib_complete), .rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]), .refresh_tick (refresh_tick), .insert_maint_r1 (insert_maint_r1), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .app_periodic_rd_req (app_periodic_rd_req), .maint_prescaler_tick_r (maint_prescaler_tick_r), .rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0])); end endgenerate mig_7series_v2_3_rank_common # (/*AUTOINSTPARAM*/ // Parameters .DRAM_TYPE (DRAM_TYPE), .MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV), .nBANK_MACHS (nBANK_MACHS), .nCKESR (nCKESR), .nCK_PER_CLK (nCK_PER_CLK), .PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV), .RANK_WIDTH (RANK_WIDTH), .RANKS (RANKS), .REFRESH_TIMER_DIV (REFRESH_TIMER_DIV), .ZQ_TIMER_DIV (ZQ_TIMER_DIV)) rank_common0 (.clear_periodic_rd_request (clear_periodic_rd_request[RANKS-1:0]), /*AUTOINST*/ // Outputs .maint_prescaler_tick_r (maint_prescaler_tick_r), .refresh_tick (refresh_tick), .maint_zq_r (maint_zq_r), .maint_sre_r (maint_sre_r), .maint_srx_r (maint_srx_r), .maint_req_r (maint_req_r), .maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]), .maint_ref_zq_wip (maint_ref_zq_wip), .periodic_rd_r (periodic_rd_r), .periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]), // Inputs .clk (clk), .rst (rst), .init_calib_complete (init_calib_complete), .app_ref_req (app_ref_req), .app_ref_ack (app_ref_ack), .app_zq_req (app_zq_req), .app_zq_ack (app_zq_ack), .app_sr_req (app_sr_req), .app_sr_active (app_sr_active), .insert_maint_r1 (insert_maint_r1), .refresh_request (refresh_request[RANKS-1:0]), .maint_wip_r (maint_wip_r), .slot_0_present (slot_0_present[7:0]), .slot_1_present (slot_1_present[7:0]), .periodic_rd_request (periodic_rd_request[RANKS-1:0]), .periodic_rd_ack_r (periodic_rd_ack_r)); endmodule

//***************************************************************************** // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : %version // \ \ Application : MIG // / / Filename : bank_compare.v // /___/ /\ Date Last Modified : $date$ // \ \ / \ Date Created : Tue Jun 30 2009 // \___\/\___\ // //Device : 7-Series //Design Name : DDR3 SDRAM //Purpose : //Reference : //Revision History : //***************************************************************************** // This block stores the request for this bank machine. // // All possible new requests are compared against the request stored // here. The compare results are shared with the bank machines and // is used to determine where to enqueue a new request. `timescale 1ps/1ps module mig_7series_v2_3_bank_compare # (parameter BANK_WIDTH = 3, parameter TCQ = 100, parameter BURST_MODE = "8", parameter COL_WIDTH = 12, parameter DATA_BUF_ADDR_WIDTH = 8, parameter ECC = "OFF", parameter RANK_WIDTH = 2, parameter RANKS = 4, parameter ROW_WIDTH = 16) (/*AUTOARG*/ // Outputs req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r, req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r, rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr, req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r, // Inputs clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd, sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority, maint_rank_r, maint_zq_r, maint_sre_r, auto_pre_r, rd_half_rmw, act_wait_r ); input clk; input idle_ns; input idle_r; input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr; output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r; wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns = idle_r ? data_buf_addr : req_data_buf_addr_r; always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns; input periodic_rd_insert; reg req_periodic_rd_r_lcl; wire req_periodic_rd_ns = idle_ns ? periodic_rd_insert : req_periodic_rd_r_lcl; always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns; output wire req_periodic_rd_r; assign req_periodic_rd_r = req_periodic_rd_r_lcl; input size; wire req_size_r_lcl; generate if (BURST_MODE == "4") begin : burst_mode_4 assign req_size_r_lcl = 1'b0; end else if (BURST_MODE == "8") begin : burst_mode_8 assign req_size_r_lcl = 1'b1; end else if (BURST_MODE == "OTF") begin : burst_mode_otf reg req_size; wire req_size_ns = idle_ns ? (periodic_rd_insert || size) : req_size; always @(posedge clk) req_size <= #TCQ req_size_ns; assign req_size_r_lcl = req_size; end endgenerate output wire req_size_r; assign req_size_r = req_size_r_lcl; input [2:0] cmd; reg [2:0] req_cmd_r; wire [2:0] req_cmd_ns = idle_ns ? (periodic_rd_insert ? 3'b001 : cmd) : req_cmd_r; always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns; `ifdef MC_SVA rd_wr_only_wo_ecc: assert property (@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1])); `endif input sending_col; reg rd_wr_r_lcl; wire rd_wr_ns = idle_ns ? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0]) : ~sending_col && rd_wr_r_lcl; always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns; output wire rd_wr_r; assign rd_wr_r = rd_wr_r_lcl; input [RANK_WIDTH-1:0] rank; input [RANK_WIDTH-1:0] periodic_rd_rank_r; reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}}; reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}}; generate if (RANKS != 1) begin always @(/*AS*/idle_ns or periodic_rd_insert or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns ? periodic_rd_insert ? periodic_rd_rank_r : rank : req_rank_r_lcl; always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns; end endgenerate output wire [RANK_WIDTH-1:0] req_rank_r; assign req_rank_r = req_rank_r_lcl; input [BANK_WIDTH-1:0] bank; reg [BANK_WIDTH-1:0] req_bank_r_lcl; wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl; always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns; output wire[BANK_WIDTH-1:0] req_bank_r; assign req_bank_r = req_bank_r_lcl; input [ROW_WIDTH-1:0] row; reg [ROW_WIDTH-1:0] req_row_r_lcl; wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl; always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns; output wire [ROW_WIDTH-1:0] req_row_r; assign req_row_r = req_row_r_lcl; // Make req_col_r as wide as the max row address. This // makes it easier to deal with indexing different column widths. input [COL_WIDTH-1:0] col; reg [15:0] req_col_r = 16'b0; wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0]; always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns; reg req_wr_r_lcl; wire req_wr_ns = idle_ns ? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0]) : req_wr_r_lcl; always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns; output wire req_wr_r; assign req_wr_r = req_wr_r_lcl; input hi_priority; output reg req_priority_r; wire req_priority_ns = idle_ns ? hi_priority : req_priority_r; always @(posedge clk) req_priority_r <= #TCQ req_priority_ns; wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert ? periodic_rd_rank_r : rank)); wire bank_hit = (req_bank_r_lcl == bank); wire rank_bank_hit = rank_hit && bank_hit; output reg rb_hit_busy_r; // rank-bank hit on non idle row machine wire rb_hit_busy_ns_lcl; assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns; output wire rb_hit_busy_ns; assign rb_hit_busy_ns = rb_hit_busy_ns_lcl; wire row_hit_ns = (req_row_r_lcl == row); output reg row_hit_r; always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl; always @(posedge clk) row_hit_r <= #TCQ row_hit_ns; input [RANK_WIDTH-1:0] maint_rank_r; input maint_zq_r; input maint_sre_r; output wire maint_hit; assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r || maint_sre_r; // Assemble column address. Structure to be the same // width as the row address. This makes it easier // for the downstream muxing. Depending on the sizes // of the row and column addresses, fill in as appropriate. input auto_pre_r; input rd_half_rmw; reg [15:0] col_addr_template = 16'b0; always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r or req_size_r_lcl) begin col_addr_template = req_col_r; col_addr_template[10] = auto_pre_r && ~rd_half_rmw; col_addr_template[11] = req_col_r[10]; col_addr_template[12] = req_size_r_lcl; col_addr_template[13] = req_col_r[11]; end output wire [ROW_WIDTH-1:0] col_addr; assign col_addr = col_addr_template[ROW_WIDTH-1:0]; output wire req_ras; output wire req_cas; output wire row_cmd_wr; input act_wait_r; assign req_ras = 1'b0; assign req_cas = 1'b1; assign row_cmd_wr = act_wait_r; output reg [ROW_WIDTH-1:0] row_addr; always @(/*AS*/act_wait_r or req_row_r_lcl) begin row_addr = req_row_r_lcl; // This causes all precharges to be precharge single bank command. if (~act_wait_r) row_addr[10] = 1'b0; end // Indicate which, if any, rank this bank machine is busy with. // Not registering the result would probably be more accurate, but // would create timing issues. This is used for refresh banking, perfect // accuracy is not required. localparam ONE = 1; output reg [RANKS-1:0] rank_busy_r; wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns); always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns; endmodule // bank_compare

// (C) 2001-2016 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ // $Revision: #1 $ // $Date: 2016/02/08 $ // $Author: swbranch $ // ----------------------------------------------- // Reset Synchronizer // ----------------------------------------------- `timescale 1 ns / 1 ns module altera_reset_synchronizer #( parameter ASYNC_RESET = 1, parameter DEPTH = 2 ) ( input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, input clk, output reset_out ); // ----------------------------------------------- // Synchronizer register chain. We cannot reuse the // standard synchronizer in this implementation // because our timing constraints are different. // // Instead of cutting the timing path to the d-input // on the first flop we need to cut the aclr input. // // We omit the "preserve" attribute on the final // output register, so that the synthesis tool can // duplicate it where needed. // ----------------------------------------------- (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; reg altera_reset_synchronizer_int_chain_out; generate if (ASYNC_RESET) begin // ----------------------------------------------- // Assert asynchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk or posedge reset_in) begin if (reset_in) begin altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; altera_reset_synchronizer_int_chain_out <= 1'b1; end else begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end end assign reset_out = altera_reset_synchronizer_int_chain_out; end else begin // ----------------------------------------------- // Assert synchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk) begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end assign reset_out = altera_reset_synchronizer_int_chain_out; end endgenerate endmodule

// (C) 2001-2016 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ // $Revision: #1 $ // $Date: 2016/02/08 $ // $Author: swbranch $ // ----------------------------------------------- // Reset Synchronizer // ----------------------------------------------- `timescale 1 ns / 1 ns module altera_reset_synchronizer #( parameter ASYNC_RESET = 1, parameter DEPTH = 2 ) ( input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, input clk, output reset_out ); // ----------------------------------------------- // Synchronizer register chain. We cannot reuse the // standard synchronizer in this implementation // because our timing constraints are different. // // Instead of cutting the timing path to the d-input // on the first flop we need to cut the aclr input. // // We omit the "preserve" attribute on the final // output register, so that the synthesis tool can // duplicate it where needed. // ----------------------------------------------- (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; reg altera_reset_synchronizer_int_chain_out; generate if (ASYNC_RESET) begin // ----------------------------------------------- // Assert asynchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk or posedge reset_in) begin if (reset_in) begin altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; altera_reset_synchronizer_int_chain_out <= 1'b1; end else begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end end assign reset_out = altera_reset_synchronizer_int_chain_out; end else begin // ----------------------------------------------- // Assert synchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk) begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end assign reset_out = altera_reset_synchronizer_int_chain_out; end endgenerate endmodule

// (C) 2001-2016 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ // $Revision: #1 $ // $Date: 2016/02/08 $ // $Author: swbranch $ // ----------------------------------------------- // Reset Synchronizer // ----------------------------------------------- `timescale 1 ns / 1 ns module altera_reset_synchronizer #( parameter ASYNC_RESET = 1, parameter DEPTH = 2 ) ( input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, input clk, output reset_out ); // ----------------------------------------------- // Synchronizer register chain. We cannot reuse the // standard synchronizer in this implementation // because our timing constraints are different. // // Instead of cutting the timing path to the d-input // on the first flop we need to cut the aclr input. // // We omit the "preserve" attribute on the final // output register, so that the synthesis tool can // duplicate it where needed. // ----------------------------------------------- (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; reg altera_reset_synchronizer_int_chain_out; generate if (ASYNC_RESET) begin // ----------------------------------------------- // Assert asynchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk or posedge reset_in) begin if (reset_in) begin altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; altera_reset_synchronizer_int_chain_out <= 1'b1; end else begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end end assign reset_out = altera_reset_synchronizer_int_chain_out; end else begin // ----------------------------------------------- // Assert synchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk) begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end assign reset_out = altera_reset_synchronizer_int_chain_out; end endgenerate endmodule

// (C) 2001-2016 Altera Corporation. All rights reserved. // Your use of Altera Corporation's design tools, logic functions and other // software and tools, and its AMPP partner logic functions, and any output // files any of the foregoing (including device programming or simulation // files), and any associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License Subscription // Agreement, Altera MegaCore Function License Agreement, or other applicable // license agreement, including, without limitation, that your use is for the // sole purpose of programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the applicable // agreement for further details. // $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ // $Revision: #1 $ // $Date: 2016/02/08 $ // $Author: swbranch $ // ----------------------------------------------- // Reset Synchronizer // ----------------------------------------------- `timescale 1 ns / 1 ns module altera_reset_synchronizer #( parameter ASYNC_RESET = 1, parameter DEPTH = 2 ) ( input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, input clk, output reset_out ); // ----------------------------------------------- // Synchronizer register chain. We cannot reuse the // standard synchronizer in this implementation // because our timing constraints are different. // // Instead of cutting the timing path to the d-input // on the first flop we need to cut the aclr input. // // We omit the "preserve" attribute on the final // output register, so that the synthesis tool can // duplicate it where needed. // ----------------------------------------------- (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; reg altera_reset_synchronizer_int_chain_out; generate if (ASYNC_RESET) begin // ----------------------------------------------- // Assert asynchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk or posedge reset_in) begin if (reset_in) begin altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; altera_reset_synchronizer_int_chain_out <= 1'b1; end else begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end end assign reset_out = altera_reset_synchronizer_int_chain_out; end else begin // ----------------------------------------------- // Assert synchronously, deassert synchronously. // ----------------------------------------------- always @(posedge clk) begin altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; end assign reset_out = altera_reset_synchronizer_int_chain_out; end endgenerate endmodule

//***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_calib_top.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:06 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: //Purpose: // Top-level for memory physical layer (PHY) interface // NOTES: // 1. Need to support multiple copies of CS outputs // 2. DFI_DRAM_CKE_DISABLE not supported // //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_calib_top.v,v 1.1 2011/06/02 08:35:06 mishra Exp $ **$Date: 2011/06/02 08:35:06 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_calib_top.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_calib_top # ( parameter TCQ = 100, parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter tCK = 2500, // DDR3 SDRAM clock period parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3 parameter CLK_PERIOD = 3333, // Internal clock period (in ps) parameter N_CTL_LANES = 3, // # of control byte lanes in the PHY parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" parameter PRBS_WIDTH = 8, // The PRBS sequence is 2^PRBS_WIDTH parameter HIGHEST_LANE = 4, parameter HIGHEST_BANK = 3, parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" // five fields, one per possible I/O bank, 4 bits in each field, // 1 per lane data=1/ctl=0 parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf, // defines the byte lanes in I/O banks being used in the interface // 1- Used, 0- Unused parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter CTL_BYTE_LANE = 8'hE4, // Control byte lane map parameter CTL_BANK = 3'b000, // Bank used for control byte lanes // Slot Conifg parameters parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000, // DRAM bus widths parameter BANK_WIDTH = 2, // # of bank bits parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank parameter COL_WIDTH = 10, // column address width parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter ROW_WIDTH = 14, // DRAM address bus width parameter RANKS = 1, // # of memory ranks in the interface parameter CS_WIDTH = 1, // # of CS# signals in the interface parameter CKE_WIDTH = 1, // # of cke outputs parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter PER_BIT_DESKEW = "ON", // calibration Address. The address given below will be used for calibration // read and write operations. parameter NUM_DQSFOUND_CAL = 1020, // # of iteration of DQSFOUND calib parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address parameter CALIB_COL_ADD = 12'h000, // Calibration column address parameter CALIB_BA_ADD = 3'h0, // Calibration bank address // DRAM mode settings parameter AL = "0", // Additive Latency option parameter TEST_AL = "0", // Additive Latency for internal use parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T" parameter BURST_MODE = "8", // Burst length parameter BURST_TYPE = "SEQ", // Burst type parameter nCL = 5, // Read CAS latency (in clk cyc) parameter nCWL = 5, // Write CAS latency (in clk cyc) parameter tRFC = 110000, // Refresh-to-command delay parameter tREFI = 7800000, // pS Refresh-to-Refresh delay parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter RTT_NOM = "60", // ODT Nominal termination value parameter RTT_WR = "60", // ODT Write termination value parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA // 1 - ODT output from FPGA parameter WRLVL = "OFF", // Enable write leveling parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly parameter POC_USE_METASTABLE_SAMP = "FALSE", // Simulation /debug options parameter SIM_INIT_OPTION = "NONE", // Performs all initialization steps parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps parameter CKE_ODT_AUX = "FALSE", parameter IDELAY_ADJ = "ON", parameter FINE_PER_BIT = "ON", parameter CENTER_COMP_MODE = "ON", parameter PI_VAL_ADJ = "ON", parameter TAPSPERKCLK = 56, parameter DEBUG_PORT = "OFF" // Enable debug port ) ( input clk, // Internal (logic) clock input rst, // Reset sync'ed to CLK // Slot present inputs input [7:0] slot_0_present, input [7:0] slot_1_present, // Hard PHY signals // From PHY Ctrl Block input phy_ctl_ready, input phy_ctl_full, input phy_cmd_full, input phy_data_full, // To PHY Ctrl Block output write_calib, output read_calib, output calib_ctl_wren, output calib_cmd_wren, output [1:0] calib_seq, output [3:0] calib_aux_out, output [nCK_PER_CLK -1:0] calib_cke, output [1:0] calib_odt, output [2:0] calib_cmd, output calib_wrdata_en, output [1:0] calib_rank_cnt, output [1:0] calib_cas_slot, output [5:0] calib_data_offset_0, output [5:0] calib_data_offset_1, output [5:0] calib_data_offset_2, output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address, output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank, output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n, output [nCK_PER_CLK-1:0] phy_ras_n, output [nCK_PER_CLK-1:0] phy_cas_n, output [nCK_PER_CLK-1:0] phy_we_n, output phy_reset_n, // To hard PHY wrapper output reg [5:0] calib_sel/* synthesis syn_maxfan = 10 */, output reg calib_in_common/* synthesis syn_maxfan = 10 */, output reg [HIGHEST_BANK-1:0] calib_zero_inputs/* synthesis syn_maxfan = 10 */, output reg [HIGHEST_BANK-1:0] calib_zero_ctrl, output phy_if_empty_def, output reg phy_if_reset, // output reg ck_addr_ctl_delay_done, // From DQS Phaser_In input pi_phaselocked, input pi_phase_locked_all, input pi_found_dqs, input pi_dqs_found_all, input [HIGHEST_LANE-1:0] pi_dqs_found_lanes, input [5:0] pi_counter_read_val, // To DQS Phaser_In output [HIGHEST_BANK-1:0] pi_rst_stg1_cal, output pi_en_stg2_f, output pi_stg2_f_incdec, output pi_stg2_load, output [5:0] pi_stg2_reg_l, // To DQ IDELAY output idelay_ce, output idelay_inc, output idelay_ld, // To DQS Phaser_Out output [2:0] po_sel_stg2stg3 /* synthesis syn_maxfan = 3 */, output [2:0] po_stg2_c_incdec /* synthesis syn_maxfan = 3 */, output [2:0] po_en_stg2_c /* synthesis syn_maxfan = 3 */, output [2:0] po_stg2_f_incdec /* synthesis syn_maxfan = 3 */, output [2:0] po_en_stg2_f /* synthesis syn_maxfan = 3 */, output po_counter_load_en, input [8:0] po_counter_read_val, // To command Phaser_Out input phy_if_empty, input [4:0] idelaye2_init_val, input [5:0] oclkdelay_init_val, input tg_err, output rst_tg_mc, // Write data to OUT_FIFO output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata, // To CNTVALUEIN input of DQ IDELAYs for perbit de-skew output [5*RANKS*DQ_WIDTH-1:0] dlyval_dq, // IN_FIFO read enable during write leveling, write calibration, // and read leveling // Read data from hard PHY fans out to mc and calib logic input[2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata, // To MC output [6*RANKS-1:0] calib_rd_data_offset_0, output [6*RANKS-1:0] calib_rd_data_offset_1, output [6*RANKS-1:0] calib_rd_data_offset_2, output phy_rddata_valid, output calib_writes, (* max_fanout = 50 *) output reg init_calib_complete/* synthesis syn_maxfan = 10 */, output init_wrcal_complete, output pi_phase_locked_err, output pi_dqsfound_err, output wrcal_err, input pd_out, // input mmcm_ps_clk, //phase shift clock // input oclkdelay_fb_clk, //Write DQS feedback clk //phase shift clock control output psen, output psincdec, input psdone, input poc_sample_pd, // Debug Port output dbg_pi_phaselock_start, output dbg_pi_dqsfound_start, output dbg_pi_dqsfound_done, output dbg_wrcal_start, output dbg_wrcal_done, output dbg_wrlvl_start, output dbg_wrlvl_done, output dbg_wrlvl_err, output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, output [255:0] dbg_phy_wrlvl, output [5:0] dbg_tap_cnt_during_wrlvl, output dbg_wl_edge_detect_valid, output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect, // Write Calibration Logic output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, output [99:0] dbg_phy_wrcal, // Read leveling logic output [1:0] dbg_rdlvl_start, output [1:0] dbg_rdlvl_done, output [1:0] dbg_rdlvl_err, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, // Delay control input [11:0] device_temp, input tempmon_sample_en, input dbg_sel_pi_incdec, input dbg_sel_po_incdec, input [DQS_CNT_WIDTH:0] dbg_byte_sel, input dbg_pi_f_inc, input dbg_pi_f_dec, input dbg_po_f_inc, input dbg_po_f_stg23_sel, input dbg_po_f_dec, input dbg_idel_up_all, input dbg_idel_down_all, input dbg_idel_up_cpt, input dbg_idel_down_cpt, input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, input dbg_sel_all_idel_cpt, output [255:0] dbg_phy_rdlvl, // Read leveling calibration output [255:0] dbg_calib_top, // General PHY debug output dbg_oclkdelay_calib_start, output dbg_oclkdelay_calib_done, output [255:0] dbg_phy_oclkdelay_cal, output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data, output [255:0] dbg_phy_init, output [255:0] dbg_prbs_rdlvl, output [255:0] dbg_dqs_found_cal, output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps, output reg [DQS_CNT_WIDTH:0] byte_sel_cnt, output [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit output fine_delay_sel ); function integer clogb2 (input integer size); begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center // align DQ and DQS on writes. Round (up or down) value to nearest integer // localparam integer SHIFT_TBY4_TAP // = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) / // (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4); // Calculate number of slots in the system localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0); localparam OCAL_EN = ((SIM_CAL_OPTION == "FAST_CAL") || (tCK > 2500)) ? "OFF" : "ON"; // Different CTL_LANES value for DDR2. In DDR2 during DQS found all // the add,ctl & data phaser out fine delays will be adjusted. // In DDR3 only the add/ctrl lane delays will be adjusted localparam DQS_FOUND_N_CTL_LANES = (DRAM_TYPE == "DDR3") ? N_CTL_LANES : 1; localparam DQSFOUND_CAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && tCK > 2500)) ? "LEFT" : "RIGHT"; // IO Bank used for Memory I/F: "LEFT", "RIGHT" localparam FIXED_VICTIM = (SIM_CAL_OPTION == "NONE") ? "FALSE" : "TRUE"; localparam VCCO_PAT_EN = 1; // Enable VCCO pattern during calibration localparam VCCAUX_PAT_EN = 1; // Enable VCCAUX pattern during calibration localparam ISI_PAT_EN = 1; // Enable VCCO pattern during calibration //Per-bit deskew for higher freqency (>800Mhz) //localparam FINE_DELAY = (tCK < 1250) ? "ON" : "OFF"; //BYPASS localparam BYPASS_COMPLEX_RDLVL = (tCK > 2500) ? "TRUE": "FALSE"; //"TRUE"; localparam BYPASS_COMPLEX_OCAL = "TRUE"; //localparam BYPASS_COMPLEX_OCAL = ((DRAM_TYPE == "DDR2") || (nCK_PER_CLK == 2) || (OCAL_EN == "OFF")) ? "TRUE" : "FALSE"; // 8*tREFI in ps is divided by the fabric clock period in ps // 270 fabric clock cycles is subtracted to account for PRECHARGE, WR, RD times localparam REFRESH_TIMER = (SIM_CAL_OPTION == "NONE") ? (8*tREFI/(tCK*nCK_PER_CLK)) - 270 : 10795; localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER); wire [2*8*nCK_PER_CLK-1:0] prbs_seed; //wire [2*8*nCK_PER_CLK-1:0] prbs_out; wire [8*DQ_WIDTH-1:0] prbs_out; wire [7:0] prbs_rise0; wire [7:0] prbs_fall0; wire [7:0] prbs_rise1; wire [7:0] prbs_fall1; wire [7:0] prbs_rise2; wire [7:0] prbs_fall2; wire [7:0] prbs_rise3; wire [7:0] prbs_fall3; //wire [2*8*nCK_PER_CLK-1:0] prbs_o; wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; wire dqsfound_retry; wire dqsfound_retry_done; wire phy_rddata_en; wire prech_done; wire rdlvl_stg1_done; reg rdlvl_stg1_done_r1; wire pi_dqs_found_done; wire rdlvl_stg1_err; wire pi_dqs_found_err; wire wrcal_pat_resume; wire wrcal_resume_w; wire rdlvl_prech_req; wire rdlvl_last_byte_done; wire rdlvl_stg1_start; wire rdlvl_stg1_rank_done; wire rdlvl_assrt_common; wire pi_dqs_found_start; wire pi_dqs_found_rank_done; wire wl_sm_start; wire wrcal_start; wire wrcal_rd_wait; wire wrcal_prech_req; wire wrcal_pat_err; wire wrcal_done; wire wrlvl_done; wire wrlvl_err; wire wrlvl_start; wire ck_addr_cmd_delay_done; wire po_ck_addr_cmd_delay_done; wire pi_calib_done; wire detect_pi_found_dqs; wire [5:0] rd_data_offset_0; wire [5:0] rd_data_offset_1; wire [5:0] rd_data_offset_2; wire [6*RANKS-1:0] rd_data_offset_ranks_0; wire [6*RANKS-1:0] rd_data_offset_ranks_1; wire [6*RANKS-1:0] rd_data_offset_ranks_2; wire [6*RANKS-1:0] rd_data_offset_ranks_mc_0; wire [6*RANKS-1:0] rd_data_offset_ranks_mc_1; wire [6*RANKS-1:0] rd_data_offset_ranks_mc_2; wire cmd_po_stg2_f_incdec; wire cmd_po_stg2_incdec_ddr2_c; wire cmd_po_en_stg2_f; wire cmd_po_en_stg2_ddr2_c; wire cmd_po_stg2_c_incdec; wire cmd_po_en_stg2_c; wire po_stg2_ddr2_incdec; wire po_en_stg2_ddr2; wire dqs_po_stg2_f_incdec; wire dqs_po_en_stg2_f; wire dqs_wl_po_stg2_c_incdec; wire wrcal_po_stg2_c_incdec; wire dqs_wl_po_en_stg2_c; wire wrcal_po_en_stg2_c; wire [N_CTL_LANES-1:0] ctl_lane_cnt; reg [N_CTL_LANES-1:0] ctl_lane_sel; wire [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt; wire [DQS_CNT_WIDTH:0] po_stg2_wl_cnt; wire [DQS_CNT_WIDTH:0] po_stg2_ddr2_cnt; wire [8:0] dqs_wl_po_stg2_reg_l; wire dqs_wl_po_stg2_load; wire [8:0] dqs_po_stg2_reg_l; wire dqs_po_stg2_load; wire dqs_po_dec_done; wire pi_fine_dly_dec_done; wire rdlvl_pi_stg2_f_incdec; wire rdlvl_pi_stg2_f_en; wire [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt; //reg [DQS_CNT_WIDTH:0] byte_sel_cnt; wire [3*DQS_WIDTH-1:0] wl_po_coarse_cnt; wire [6*DQS_WIDTH-1:0] wl_po_fine_cnt; wire phase_locked_err; wire phy_ctl_rdy_dly; wire idelay_ce_int; wire idelay_inc_int; reg idelay_ce_r1; reg idelay_ce_r2; reg idelay_inc_r1; reg idelay_inc_r2 /* synthesis syn_maxfan = 30 */; reg po_dly_req_r; wire wrcal_read_req; wire wrcal_act_req; wire temp_wrcal_done; wire tg_timer_done; wire no_rst_tg_mc; wire calib_complete; reg reset_if_r1; reg reset_if_r2; reg reset_if_r3; reg reset_if_r4; reg reset_if_r5; reg reset_if_r6; reg reset_if_r7; reg reset_if_r8; reg reset_if_r9; reg reset_if; wire phy_if_reset_w; wire pi_phaselock_start; reg dbg_pi_f_inc_r; reg dbg_pi_f_en_r; reg dbg_sel_pi_incdec_r; reg dbg_po_f_inc_r; reg dbg_po_f_stg23_sel_r; reg dbg_po_f_en_r; reg dbg_sel_po_incdec_r; reg tempmon_pi_f_inc_r; reg tempmon_pi_f_en_r; reg tempmon_sel_pi_incdec_r; reg ck_addr_cmd_delay_done_r1; reg ck_addr_cmd_delay_done_r2; reg ck_addr_cmd_delay_done_r3; reg ck_addr_cmd_delay_done_r4; reg ck_addr_cmd_delay_done_r5; reg ck_addr_cmd_delay_done_r6; // wire oclk_init_delay_start; wire oclk_prech_req; wire oclk_calib_resume; // wire oclk_init_delay_done; wire [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; wire [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt; wire oclkdelay_calib_start; wire oclkdelay_calib_done; wire complex_oclk_prech_req; wire complex_oclk_calib_resume; wire complex_oclkdelay_calib_start; wire complex_oclkdelay_calib_done; wire complex_ocal_num_samples_inc; wire complex_ocal_num_samples_done_r; wire [2:0] complex_ocal_rd_victim_sel; wire complex_ocal_ref_req; wire complex_ocal_ref_done; wire [6*DQS_WIDTH-1:0] oclkdelay_left_edge_val; wire [6*DQS_WIDTH-1:0] oclkdelay_right_edge_val; wire wrlvl_final; wire complex_wrlvl_final; reg wrlvl_final_mux; wire wrlvl_final_if_rst; wire wrlvl_byte_redo; wire wrlvl_byte_done; wire early1_data; wire early2_data; //wire po_stg3_incdec; //wire po_en_stg3; wire po_stg23_sel; wire po_stg23_incdec; wire po_en_stg23; wire complex_po_stg23_sel; wire complex_po_stg23_incdec; wire complex_po_en_stg23; wire mpr_rdlvl_done; wire mpr_rdlvl_start; wire mpr_last_byte_done; wire mpr_rnk_done; wire mpr_end_if_reset; wire mpr_rdlvl_err; wire rdlvl_err; wire prbs_rdlvl_start; wire prbs_rdlvl_done; reg prbs_rdlvl_done_r1; wire prbs_last_byte_done; wire prbs_rdlvl_prech_req; wire prbs_pi_stg2_f_incdec; wire prbs_pi_stg2_f_en; wire complex_sample_cnt_inc; wire complex_sample_cnt_inc_ocal; wire [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt; wire prbs_gen_clk_en; wire prbs_gen_oclk_clk_en; wire rd_data_offset_cal_done; wire fine_adjust_done; wire [N_CTL_LANES-1:0] fine_adjust_lane_cnt; wire ck_po_stg2_f_indec; wire ck_po_stg2_f_en; wire dqs_found_prech_req; wire tempmon_pi_f_inc; wire tempmon_pi_f_dec; wire tempmon_sel_pi_incdec; wire wrcal_sanity_chk; wire wrcal_sanity_chk_done; wire wrlvl_done_w; wire wrlvl_rank_done; wire done_dqs_tap_inc; wire [2:0] rd_victim_sel; wire [2:0] victim_sel; wire [DQS_CNT_WIDTH:0] victim_byte_cnt; wire complex_wr_done; wire complex_victim_inc; wire reset_rd_addr; wire read_pause; wire complex_ocal_reset_rd_addr; wire oclkdelay_center_calib_start; wire poc_error; wire prbs_ignore_first_byte; wire prbs_ignore_last_bytes; //stg3 tap values // wire [6*DQS_WIDTH-1:0] oclkdelay_center_val; //byte selection // wire [DQS_CNT_WIDTH:0] oclkdelay_center_cnt; //INC/DEC for stg3 taps // wire ocal_ctr_po_stg23_sel; // wire ocal_ctr_po_stg23_incdec; // wire ocal_ctr_po_en_stg23; //Write resume for DQS toggling wire oclk_center_write_resume; wire oclkdelay_center_calib_done; //Write request to toggle DQS for limit module wire lim2init_write_request; wire lim_done; // Bypass complex ocal wire complex_oclkdelay_calib_start_w; wire complex_oclkdelay_calib_done_w; wire [2:0] complex_ocal_rd_victim_sel_w; wire complex_wrlvl_final_w; wire [255:0] dbg_ocd_lim; //with MMCM phase detect logic //wire mmcm_edge_detect_rdy; // ready for MMCM detect //wire ktap_at_rightedge; // stg3 tap at right edge //wire ktap_at_leftedge; // stg3 tap at left edge //wire mmcm_tap_at_center; // indicate stg3 tap at center //wire mmcm_ps_clkphase_ok; // ps clkphase is OK //wire mmcm_edge_detect_done; // mmcm edge detect is done //wire mmcm_lbclk_edges_aligned; // mmcm edge detect is done //wire reset_mmcm; //mmcm detect logic reset per byte // wire [255:0] dbg_phy_oclkdelay_center_cal; //***************************************************************************** // Assertions to check correctness of parameter values //***************************************************************************** // synthesis translate_off initial begin if (RANKS == 0) begin $display ("Error: Invalid RANKS parameter. Must be 1 or greater"); $finish; end if (phy_ctl_full == 1'b1) begin $display ("Error: Incorrect phy_ctl_full input value in 2:1 or 4:1 mode"); $finish; end end // synthesis translate_on //*************************************************************************** // Debug //*************************************************************************** assign dbg_pi_phaselock_start = pi_phaselock_start; assign dbg_pi_dqsfound_start = pi_dqs_found_start; assign dbg_pi_dqsfound_done = pi_dqs_found_done; assign dbg_wrcal_start = wrcal_start; assign dbg_wrcal_done = wrcal_done; // Unused for now - use these as needed to bring up lower level signals assign dbg_calib_top = dbg_ocd_lim; // Write Level and write calibration debug observation ports assign dbg_wrlvl_start = wrlvl_start; assign dbg_wrlvl_done = wrlvl_done; assign dbg_wrlvl_err = wrlvl_err; // Read Level debug observation ports assign dbg_rdlvl_start = {mpr_rdlvl_start, rdlvl_stg1_start}; assign dbg_rdlvl_done = {mpr_rdlvl_done, rdlvl_stg1_done}; assign dbg_rdlvl_err = {mpr_rdlvl_err, rdlvl_err}; assign dbg_oclkdelay_calib_done = oclkdelay_calib_done; assign dbg_oclkdelay_calib_start = oclkdelay_calib_start; //*************************************************************************** // Write leveling dependent signals //*************************************************************************** assign wrcal_resume_w = (WRLVL == "ON") ? wrcal_pat_resume : 1'b0; assign wrlvl_done_w = (WRLVL == "ON") ? wrlvl_done : 1'b1; assign ck_addr_cmd_delay_done = (WRLVL == "ON") ? po_ck_addr_cmd_delay_done : (po_ck_addr_cmd_delay_done && pi_fine_dly_dec_done) ; generate if((WRLVL == "ON") && (BYPASS_COMPLEX_OCAL=="FALSE")) begin: complex_oclk_calib assign complex_oclkdelay_calib_start_w = complex_oclkdelay_calib_start; assign complex_oclkdelay_calib_done_w = complex_oclkdelay_calib_done; assign complex_ocal_rd_victim_sel_w = complex_ocal_rd_victim_sel; assign complex_wrlvl_final_w = complex_wrlvl_final; end else begin: bypass_complex_ocal assign complex_oclkdelay_calib_start_w = 1'b0; assign complex_oclkdelay_calib_done_w = prbs_rdlvl_done; assign complex_ocal_rd_victim_sel_w = 'd0; assign complex_wrlvl_final_w = 1'b0; end endgenerate generate genvar i; for (i = 0; i <= 2; i = i+1) begin : bankwise_signal assign po_sel_stg2stg3[i] = ((ck_addr_cmd_delay_done && ~oclkdelay_calib_done && mpr_rdlvl_done) ? po_stg23_sel : (complex_oclkdelay_calib_start_w&&~complex_oclkdelay_calib_done_w? po_stg23_sel : 1'b0 ) // (~oclkdelay_center_calib_done? ocal_ctr_po_stg23_sel:1'b0)) ) | dbg_po_f_stg23_sel_r; assign po_stg2_c_incdec[i] = cmd_po_stg2_c_incdec || cmd_po_stg2_incdec_ddr2_c || dqs_wl_po_stg2_c_incdec; assign po_en_stg2_c[i] = cmd_po_en_stg2_c || cmd_po_en_stg2_ddr2_c || dqs_wl_po_en_stg2_c; assign po_stg2_f_incdec[i] = dqs_po_stg2_f_incdec || cmd_po_stg2_f_incdec || //po_stg3_incdec || ck_po_stg2_f_indec || po_stg23_incdec || // complex_po_stg23_incdec || // ocal_ctr_po_stg23_incdec || dbg_po_f_inc_r; assign po_en_stg2_f[i] = dqs_po_en_stg2_f || cmd_po_en_stg2_f || //po_en_stg3 || ck_po_stg2_f_en || po_en_stg23 || // complex_po_en_stg23 || // ocal_ctr_po_en_stg23 || dbg_po_f_en_r; end endgenerate assign pi_stg2_f_incdec = (dbg_pi_f_inc_r | rdlvl_pi_stg2_f_incdec | prbs_pi_stg2_f_incdec | tempmon_pi_f_inc_r); assign pi_en_stg2_f = (dbg_pi_f_en_r | rdlvl_pi_stg2_f_en | prbs_pi_stg2_f_en | tempmon_pi_f_en_r); assign idelay_ce = idelay_ce_r2; assign idelay_inc = idelay_inc_r2; assign po_counter_load_en = 1'b0; assign complex_oclkdelay_calib_cnt = oclkdelay_calib_cnt; assign complex_oclk_calib_resume = oclk_calib_resume; assign complex_ocal_ref_req = oclk_prech_req; // Added single stage flop to meet timing always @(posedge clk) init_calib_complete <= calib_complete; assign calib_rd_data_offset_0 = rd_data_offset_ranks_mc_0; assign calib_rd_data_offset_1 = rd_data_offset_ranks_mc_1; assign calib_rd_data_offset_2 = rd_data_offset_ranks_mc_2; //*************************************************************************** // Hard PHY signals //*************************************************************************** assign pi_phase_locked_err = phase_locked_err; assign pi_dqsfound_err = pi_dqs_found_err; assign wrcal_err = wrcal_pat_err; assign rst_tg_mc = 1'b0; //Restart WRLVL after oclkdealy cal always @ (posedge clk) wrlvl_final_mux <= #TCQ complex_oclkdelay_calib_start_w? complex_wrlvl_final_w: wrlvl_final; always @(posedge clk) phy_if_reset <= #TCQ (phy_if_reset_w | mpr_end_if_reset | reset_if | wrlvl_final_if_rst); //*************************************************************************** // Phaser_IN inc dec control for debug //*************************************************************************** always @(posedge clk) begin if (rst) begin dbg_pi_f_inc_r <= #TCQ 1'b0; dbg_pi_f_en_r <= #TCQ 1'b0; dbg_sel_pi_incdec_r <= #TCQ 1'b0; end else begin dbg_pi_f_inc_r <= #TCQ dbg_pi_f_inc; dbg_pi_f_en_r <= #TCQ (dbg_pi_f_inc | dbg_pi_f_dec); dbg_sel_pi_incdec_r <= #TCQ dbg_sel_pi_incdec; end end //*************************************************************************** // Phaser_OUT inc dec control for debug //*************************************************************************** always @(posedge clk) begin if (rst) begin dbg_po_f_inc_r <= #TCQ 1'b0; dbg_po_f_stg23_sel_r<= #TCQ 1'b0; dbg_po_f_en_r <= #TCQ 1'b0; dbg_sel_po_incdec_r <= #TCQ 1'b0; end else begin dbg_po_f_inc_r <= #TCQ dbg_po_f_inc; dbg_po_f_stg23_sel_r<= #TCQ dbg_po_f_stg23_sel; dbg_po_f_en_r <= #TCQ (dbg_po_f_inc | dbg_po_f_dec); dbg_sel_po_incdec_r <= #TCQ dbg_sel_po_incdec; end end //*************************************************************************** // Phaser_IN inc dec control for temperature tracking //*************************************************************************** always @(posedge clk) begin if (rst) begin tempmon_pi_f_inc_r <= #TCQ 1'b0; tempmon_pi_f_en_r <= #TCQ 1'b0; tempmon_sel_pi_incdec_r <= #TCQ 1'b0; end else begin tempmon_pi_f_inc_r <= #TCQ tempmon_pi_f_inc; tempmon_pi_f_en_r <= #TCQ (tempmon_pi_f_inc | tempmon_pi_f_dec); tempmon_sel_pi_incdec_r <= #TCQ tempmon_sel_pi_incdec; end end //*************************************************************************** // OCLKDELAY calibration signals //*************************************************************************** // Minimum of 5 'clk' cycles required between assertion of po_sel_stg2stg3 // and increment/decrement of Phaser_Out stage 3 delay always @(posedge clk) begin ck_addr_cmd_delay_done_r1 <= #TCQ ck_addr_cmd_delay_done; ck_addr_cmd_delay_done_r2 <= #TCQ ck_addr_cmd_delay_done_r1; ck_addr_cmd_delay_done_r3 <= #TCQ ck_addr_cmd_delay_done_r2; ck_addr_cmd_delay_done_r4 <= #TCQ ck_addr_cmd_delay_done_r3; ck_addr_cmd_delay_done_r5 <= #TCQ ck_addr_cmd_delay_done_r4; ck_addr_cmd_delay_done_r6 <= #TCQ ck_addr_cmd_delay_done_r5; end //*************************************************************************** // MUX select logic to select current byte undergoing calibration // Use DQS_CAL_MAP to determine the correlation between the physical // byte numbering, and the byte numbering within the hard PHY //*************************************************************************** generate if (tCK > 2500) begin: gen_byte_sel_div2 always @(posedge clk) begin if (rst) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b0; end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~ck_addr_cmd_delay_done) begin ctl_lane_sel <= #TCQ ctl_lane_cnt; calib_in_common <= #TCQ 1'b0; end else if (~fine_adjust_done && rd_data_offset_cal_done) begin if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ fine_adjust_lane_cnt; calib_in_common <= #TCQ 1'b0; end end else if (~pi_calib_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~pi_dqs_found_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~wrlvl_done_w) begin if (SIM_CAL_OPTION != "FAST_CAL") begin byte_sel_cnt <= #TCQ po_stg2_wl_cnt; calib_in_common <= #TCQ 1'b0; end else begin // Special case for FAST_CAL simulation only to ensure that // calib_in_common isn't asserted too soon if (!phy_ctl_rdy_dly) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b0; end else begin byte_sel_cnt <= #TCQ po_stg2_wl_cnt; calib_in_common <= #TCQ 1'b1; end end end else if (~mpr_rdlvl_done) begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end else if (~oclkdelay_calib_done) begin byte_sel_cnt <= #TCQ oclkdelay_calib_cnt; calib_in_common <= #TCQ 1'b0; end else if (~rdlvl_stg1_done && pi_calib_done) begin if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b1; end else begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt; calib_in_common <= #TCQ 1'b0; end else if (~wrcal_done) begin byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt; calib_in_common <= #TCQ 1'b0; end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin byte_sel_cnt <= #TCQ dbg_byte_sel; calib_in_common <= #TCQ 1'b0; end else if (tempmon_sel_pi_incdec) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end end end else begin: gen_byte_sel_div1 always @(posedge clk) begin if (rst) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b0; end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~ck_addr_cmd_delay_done) begin ctl_lane_sel <= #TCQ ctl_lane_cnt; calib_in_common <= #TCQ 1'b0; end else if (~fine_adjust_done && rd_data_offset_cal_done) begin if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ fine_adjust_lane_cnt; calib_in_common <= #TCQ 1'b0; end end else if (~pi_calib_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~pi_dqs_found_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~wrlvl_done_w) begin if (SIM_CAL_OPTION != "FAST_CAL") begin byte_sel_cnt <= #TCQ po_stg2_wl_cnt; calib_in_common <= #TCQ 1'b0; end else begin // Special case for FAST_CAL simulation only to ensure that // calib_in_common isn't asserted too soon if (!phy_ctl_rdy_dly) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b0; end else begin byte_sel_cnt <= #TCQ po_stg2_wl_cnt; calib_in_common <= #TCQ 1'b1; end end end else if (~mpr_rdlvl_done) begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end else if (~oclkdelay_calib_done) begin byte_sel_cnt <= #TCQ oclkdelay_calib_cnt; calib_in_common <= #TCQ 1'b0; end else if ((~wrcal_done)&& (DRAM_TYPE == "DDR3")) begin byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt; calib_in_common <= #TCQ 1'b0; end else if (~rdlvl_stg1_done && pi_calib_done) begin if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b1; end else begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt; calib_in_common <= #TCQ 1'b0; end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin byte_sel_cnt <= #TCQ dbg_byte_sel; calib_in_common <= #TCQ 1'b0; end else if (tempmon_sel_pi_incdec) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end end end endgenerate // verilint STARC-2.2.3.3 off always @(posedge clk) begin if (rst || (calib_complete && ~ (dbg_sel_pi_incdec_r|dbg_sel_po_incdec_r|tempmon_sel_pi_incdec) )) begin calib_sel <= #TCQ 6'b000100; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; if (~dqs_po_dec_done && (WRLVL != "ON")) //if (~dqs_po_dec_done && ((SIM_CAL_OPTION == "FAST_CAL") ||(WRLVL != "ON"))) calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}}; else calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else if (~ck_addr_cmd_delay_done || (~fine_adjust_done && rd_data_offset_cal_done)) begin if(WRLVL =="ON") begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ CTL_BYTE_LANE[(ctl_lane_sel*2)+:2]; calib_sel[5:3] <= #TCQ CTL_BANK; if (|pi_rst_stg1_cal) begin calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; end else begin calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; calib_zero_inputs[1*CTL_BANK] <= #TCQ 1'b0; end calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else begin // if (WRLVL =="ON") calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; if(~ck_addr_cmd_delay_done) calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; else calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}}; end // else: !if(WRLVL =="ON") end else if ((~wrlvl_done_w) && (SIM_CAL_OPTION == "FAST_CAL")) begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else if (~rdlvl_stg1_done && (SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else if (tempmon_sel_pi_incdec) begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; if (~calib_in_common) begin calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; calib_zero_inputs[(1*DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3])] <= #TCQ 1'b0; end else calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; end end // verilint STARC-2.2.3.3 on // Logic to reset IN_FIFO flags to account for the possibility that // one or more PHASER_IN's have not correctly found the DQS preamble // If this happens, we can still complete read leveling, but the # of // words written into the IN_FIFO's may be an odd #, so that if the // IN_FIFO is used in 2:1 mode ("8:4 mode"), there may be a "half" word // of data left that can only be flushed out by reseting the IN_FIFO always @(posedge clk) begin rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done; prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done; reset_if_r1 <= #TCQ reset_if; reset_if_r2 <= #TCQ reset_if_r1; reset_if_r3 <= #TCQ reset_if_r2; reset_if_r4 <= #TCQ reset_if_r3; reset_if_r5 <= #TCQ reset_if_r4; reset_if_r6 <= #TCQ reset_if_r5; reset_if_r7 <= #TCQ reset_if_r6; reset_if_r8 <= #TCQ reset_if_r7; reset_if_r9 <= #TCQ reset_if_r8; end always @(posedge clk) begin if (rst || reset_if_r9) reset_if <= #TCQ 1'b0; else if ((rdlvl_stg1_done && ~rdlvl_stg1_done_r1) || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) reset_if <= #TCQ 1'b1; end assign phy_if_empty_def = 1'b0; // DQ IDELAY tap inc and ce signals registered to control calib_in_common // signal during read leveling in FAST_CAL mode. The calib_in_common signal // is only asserted for IDELAY tap increments not Phaser_IN tap increments // in FAST_CAL mode. For Phaser_IN tap increments the Phaser_IN counter load // inputs are used. always @(posedge clk) begin if (rst) begin idelay_ce_r1 <= #TCQ 1'b0; idelay_ce_r2 <= #TCQ 1'b0; idelay_inc_r1 <= #TCQ 1'b0; idelay_inc_r2 <= #TCQ 1'b0; end else begin idelay_ce_r1 <= #TCQ idelay_ce_int; idelay_ce_r2 <= #TCQ idelay_ce_r1; idelay_inc_r1 <= #TCQ idelay_inc_int; idelay_inc_r2 <= #TCQ idelay_inc_r1; end end //*************************************************************************** // Delay all Outputs using Phaser_Out fine taps //*************************************************************************** assign init_wrcal_complete = 1'b0; //*************************************************************************** // PRBS Generator for Read Leveling Stage 1 - read window detection and // DQS Centering //*************************************************************************** // Assign initial seed (used for 1st data word in 8-burst sequence); use alternating 1/0 pat assign prbs_seed = 64'h9966aa559966aa55; // A single PRBS generator // writes 64-bits every 4to1 fabric clock cycle and // write 32-bits every 2to1 fabric clock cycle // used for complex read leveling and complex oclkdealy calib mig_7series_v2_3_ddr_prbs_gen # ( .TCQ (TCQ), .PRBS_WIDTH (2*8*nCK_PER_CLK), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQ_WIDTH (DQ_WIDTH), .VCCO_PAT_EN (VCCO_PAT_EN), .VCCAUX_PAT_EN (VCCAUX_PAT_EN), .ISI_PAT_EN (ISI_PAT_EN), .FIXED_VICTIM (FIXED_VICTIM) ) u_ddr_prbs_gen (.prbs_ignore_first_byte (prbs_ignore_first_byte), .prbs_ignore_last_bytes (prbs_ignore_last_bytes), .clk_i (clk), .clk_en_i (prbs_gen_clk_en | prbs_gen_oclk_clk_en), .rst_i (rst), .prbs_o (prbs_out), .prbs_seed_i (prbs_seed), .phy_if_empty (phy_if_empty), .prbs_rdlvl_start (prbs_rdlvl_start), .prbs_rdlvl_done (prbs_rdlvl_done), .complex_wr_done (complex_wr_done), .victim_sel (victim_sel), .byte_cnt (victim_byte_cnt), .dbg_prbs_gen (), .reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr) ); // PRBS data slice that decides the Rise0, Fall0, Rise1, Fall1, // Rise2, Fall2, Rise3, Fall3 data generate if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4 assign prbs_o = prbs_out; /*assign prbs_rise0 = prbs_out[7:0]; assign prbs_fall0 = prbs_out[15:8]; assign prbs_rise1 = prbs_out[23:16]; assign prbs_fall1 = prbs_out[31:24]; assign prbs_rise2 = prbs_out[39:32]; assign prbs_fall2 = prbs_out[47:40]; assign prbs_rise3 = prbs_out[55:48]; assign prbs_fall3 = prbs_out[63:56]; assign prbs_o = {prbs_fall3, prbs_rise3, prbs_fall2, prbs_rise2, prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/ end else begin :gen_ck_per_clk2 assign prbs_o = prbs_out[4*DQ_WIDTH-1:0]; /*assign prbs_rise0 = prbs_out[7:0]; assign prbs_fall0 = prbs_out[15:8]; assign prbs_rise1 = prbs_out[23:16]; assign prbs_fall1 = prbs_out[31:24]; assign prbs_o = {prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/ end endgenerate //*************************************************************************** // Initialization / Master PHY state logic (overall control during memory // init, timing leveling) //*************************************************************************** mig_7series_v2_3_ddr_phy_init # ( .tCK (tCK), .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .CLK_PERIOD (CLK_PERIOD), .DRAM_TYPE (DRAM_TYPE), .PRBS_WIDTH (PRBS_WIDTH), .BANK_WIDTH (BANK_WIDTH), .CA_MIRROR (CA_MIRROR), .COL_WIDTH (COL_WIDTH), .nCS_PER_RANK (nCS_PER_RANK), .DQ_WIDTH (DQ_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .ROW_WIDTH (ROW_WIDTH), .CS_WIDTH (CS_WIDTH), .RANKS (RANKS), .CKE_WIDTH (CKE_WIDTH), .CALIB_ROW_ADD (CALIB_ROW_ADD), .CALIB_COL_ADD (CALIB_COL_ADD), .CALIB_BA_ADD (CALIB_BA_ADD), .AL (AL), .BURST_MODE (BURST_MODE), .BURST_TYPE (BURST_TYPE), .nCL (nCL), .nCWL (nCWL), .tRFC (tRFC), .REFRESH_TIMER (REFRESH_TIMER), .REFRESH_TIMER_WIDTH (REFRESH_TIMER_WIDTH), .OUTPUT_DRV (OUTPUT_DRV), .REG_CTRL (REG_CTRL), .ADDR_CMD_MODE (ADDR_CMD_MODE), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .WRLVL (WRLVL), .USE_ODT_PORT (USE_ODT_PORT), .DDR2_DQSN_ENABLE(DDR2_DQSN_ENABLE), .nSLOTS (nSLOTS), .SIM_INIT_OPTION (SIM_INIT_OPTION), .SIM_CAL_OPTION (SIM_CAL_OPTION), .CKE_ODT_AUX (CKE_ODT_AUX), .PRE_REV3ES (PRE_REV3ES), .TEST_AL (TEST_AL), .FIXED_VICTIM (FIXED_VICTIM), .BYPASS_COMPLEX_OCAL(BYPASS_COMPLEX_OCAL) ) u_ddr_phy_init ( .clk (clk), .rst (rst), .prbs_o (prbs_o), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .delay_incdec_done (ck_addr_cmd_delay_done), .pi_phase_locked_all (pi_phase_locked_all), .pi_phaselock_start (pi_phaselock_start), .pi_phase_locked_err (phase_locked_err), .pi_calib_done (pi_calib_done), .phy_if_empty (phy_if_empty), .phy_ctl_ready (phy_ctl_ready), .phy_ctl_full (phy_ctl_full), .phy_cmd_full (phy_cmd_full), .phy_data_full (phy_data_full), .calib_ctl_wren (calib_ctl_wren), .calib_cmd_wren (calib_cmd_wren), .calib_wrdata_en (calib_wrdata_en), .calib_seq (calib_seq), .calib_aux_out (calib_aux_out), .calib_rank_cnt (calib_rank_cnt), .calib_cas_slot (calib_cas_slot), .calib_data_offset_0 (calib_data_offset_0), .calib_data_offset_1 (calib_data_offset_1), .calib_data_offset_2 (calib_data_offset_2), .calib_cmd (calib_cmd), .calib_cke (calib_cke), .calib_odt (calib_odt), .write_calib (write_calib), .read_calib (read_calib), .wrlvl_done (wrlvl_done), .wrlvl_rank_done (wrlvl_rank_done), .wrlvl_byte_done (wrlvl_byte_done), .wrlvl_byte_redo (wrlvl_byte_redo), .wrlvl_final (wrlvl_final_mux), .wrlvl_final_if_rst (wrlvl_final_if_rst), .oclkdelay_calib_start (oclkdelay_calib_start), .oclkdelay_calib_done (oclkdelay_calib_done), .oclk_prech_req (oclk_prech_req), .oclk_calib_resume (oclk_calib_resume), .lim_wr_req (lim2init_write_request), .lim_done (lim_done), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done_w), .complex_oclk_calib_resume (complex_oclk_calib_resume), .complex_oclkdelay_calib_cnt (complex_oclkdelay_calib_cnt), .complex_sample_cnt_inc_ocal (complex_sample_cnt_inc_ocal), .complex_ocal_num_samples_inc (complex_ocal_num_samples_inc), .complex_ocal_num_samples_done_r (complex_ocal_num_samples_done_r), .complex_ocal_reset_rd_addr (complex_ocal_reset_rd_addr), .complex_ocal_ref_req (complex_ocal_ref_req), .complex_ocal_ref_done (complex_ocal_ref_done), .done_dqs_tap_inc (done_dqs_tap_inc), .wl_sm_start (wl_sm_start), .wr_lvl_start (wrlvl_start), .slot_0_present (slot_0_present), .slot_1_present (slot_1_present), .mpr_rdlvl_done (mpr_rdlvl_done), .mpr_rdlvl_start (mpr_rdlvl_start), .mpr_last_byte_done (mpr_last_byte_done), .mpr_rnk_done (mpr_rnk_done), .mpr_end_if_reset (mpr_end_if_reset), .rdlvl_stg1_done (rdlvl_stg1_done), .rdlvl_stg1_rank_done (rdlvl_stg1_rank_done), .rdlvl_stg1_start (rdlvl_stg1_start), .rdlvl_prech_req (rdlvl_prech_req), .rdlvl_last_byte_done (rdlvl_last_byte_done), .prbs_rdlvl_start (prbs_rdlvl_start), .complex_wr_done (complex_wr_done), .prbs_rdlvl_done (prbs_rdlvl_done), .prbs_last_byte_done (prbs_last_byte_done), .prbs_rdlvl_prech_req (prbs_rdlvl_prech_req), .complex_victim_inc (complex_victim_inc), .rd_victim_sel (rd_victim_sel), .complex_ocal_rd_victim_sel (complex_ocal_rd_victim_sel), .pi_stg2_prbs_rdlvl_cnt(pi_stg2_prbs_rdlvl_cnt), .victim_sel (victim_sel), .victim_byte_cnt (victim_byte_cnt), .prbs_gen_clk_en (prbs_gen_clk_en), .prbs_gen_oclk_clk_en (prbs_gen_oclk_clk_en), .complex_sample_cnt_inc(complex_sample_cnt_inc), .pi_dqs_found_start (pi_dqs_found_start), .dqsfound_retry (dqsfound_retry), .dqs_found_prech_req (dqs_found_prech_req), .pi_dqs_found_rank_done(pi_dqs_found_rank_done), .pi_dqs_found_done (pi_dqs_found_done), .detect_pi_found_dqs (detect_pi_found_dqs), .rd_data_offset_0 (rd_data_offset_0), .rd_data_offset_1 (rd_data_offset_1), .rd_data_offset_2 (rd_data_offset_2), .rd_data_offset_ranks_0(rd_data_offset_ranks_0), .rd_data_offset_ranks_1(rd_data_offset_ranks_1), .rd_data_offset_ranks_2(rd_data_offset_ranks_2), .wrcal_start (wrcal_start), .wrcal_rd_wait (wrcal_rd_wait), .wrcal_prech_req (wrcal_prech_req), .wrcal_resume (wrcal_resume_w), .wrcal_read_req (wrcal_read_req), .wrcal_act_req (wrcal_act_req), .wrcal_sanity_chk (wrcal_sanity_chk), .temp_wrcal_done (temp_wrcal_done), .wrcal_sanity_chk_done (wrcal_sanity_chk_done), .tg_timer_done (tg_timer_done), .no_rst_tg_mc (no_rst_tg_mc), .wrcal_done (wrcal_done), .prech_done (prech_done), .calib_writes (calib_writes), .init_calib_complete (calib_complete), .phy_address (phy_address), .phy_bank (phy_bank), .phy_cas_n (phy_cas_n), .phy_cs_n (phy_cs_n), .phy_ras_n (phy_ras_n), .phy_reset_n (phy_reset_n), .phy_we_n (phy_we_n), .phy_wrdata (phy_wrdata), .phy_rddata_en (phy_rddata_en), .phy_rddata_valid (phy_rddata_valid), .dbg_phy_init (dbg_phy_init), .read_pause (read_pause), .reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr), .oclkdelay_center_calib_start (oclkdelay_center_calib_start), .oclk_center_write_resume (oclk_center_write_resume), .oclkdelay_center_calib_done (oclkdelay_center_calib_done) ); //***************************************************************** // Write Calibration //***************************************************************** mig_7series_v2_3_ddr_phy_wrcal # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .CLK_PERIOD (CLK_PERIOD), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .SIM_CAL_OPTION (SIM_CAL_OPTION) ) u_ddr_phy_wrcal ( .clk (clk), .rst (rst), .wrcal_start (wrcal_start), .wrcal_rd_wait (wrcal_rd_wait), .wrcal_sanity_chk (wrcal_sanity_chk), .dqsfound_retry_done (pi_dqs_found_done), .dqsfound_retry (dqsfound_retry), .wrcal_read_req (wrcal_read_req), .wrcal_act_req (wrcal_act_req), .phy_rddata_en (phy_rddata_en), .wrcal_done (wrcal_done), .wrcal_pat_err (wrcal_pat_err), .wrcal_prech_req (wrcal_prech_req), .temp_wrcal_done (temp_wrcal_done), .wrcal_sanity_chk_done (wrcal_sanity_chk_done), .prech_done (prech_done), .rd_data (phy_rddata), .wrcal_pat_resume (wrcal_pat_resume), .po_stg2_wrcal_cnt (po_stg2_wrcal_cnt), .phy_if_reset (phy_if_reset_w), .wl_po_coarse_cnt (wl_po_coarse_cnt), .wl_po_fine_cnt (wl_po_fine_cnt), .wrlvl_byte_redo (wrlvl_byte_redo), .wrlvl_byte_done (wrlvl_byte_done), .early1_data (early1_data), .early2_data (early2_data), .idelay_ld (idelay_ld), .dbg_phy_wrcal (dbg_phy_wrcal), .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt) ); //*************************************************************************** // Write-leveling calibration logic //*************************************************************************** generate if (WRLVL == "ON") begin: mb_wrlvl_inst mig_7series_v2_3_ddr_phy_wrlvl # ( .TCQ (TCQ), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQ_WIDTH (DQ_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .RANKS (1), .CLK_PERIOD (CLK_PERIOD), .nCK_PER_CLK (nCK_PER_CLK), .SIM_CAL_OPTION (SIM_CAL_OPTION) ) u_ddr_phy_wrlvl ( .clk (clk), .rst (rst), .phy_ctl_ready (phy_ctl_ready), .wr_level_start (wrlvl_start), .wl_sm_start (wl_sm_start), .wrlvl_byte_redo (wrlvl_byte_redo), .wrcal_cnt (po_stg2_wrcal_cnt), .early1_data (early1_data), .early2_data (early2_data), .wrlvl_final (wrlvl_final_mux), .oclkdelay_calib_cnt (oclkdelay_calib_cnt), .wrlvl_byte_done (wrlvl_byte_done), .oclkdelay_calib_done (oclkdelay_calib_done), .rd_data_rise0 (phy_rddata[DQ_WIDTH-1:0]), .dqs_po_dec_done (dqs_po_dec_done), .phy_ctl_rdy_dly (phy_ctl_rdy_dly), .wr_level_done (wrlvl_done), .wrlvl_rank_done (wrlvl_rank_done), .done_dqs_tap_inc (done_dqs_tap_inc), .dqs_po_stg2_f_incdec (dqs_po_stg2_f_incdec), .dqs_po_en_stg2_f (dqs_po_en_stg2_f), .dqs_wl_po_stg2_c_incdec (dqs_wl_po_stg2_c_incdec), .dqs_wl_po_en_stg2_c (dqs_wl_po_en_stg2_c), .po_counter_read_val (po_counter_read_val), .po_stg2_wl_cnt (po_stg2_wl_cnt), .wrlvl_err (wrlvl_err), .wl_po_coarse_cnt (wl_po_coarse_cnt), .wl_po_fine_cnt (wl_po_fine_cnt), .dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl), .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), .dbg_dqs_count (), .dbg_wl_state (), .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), .dbg_phy_wrlvl (dbg_phy_wrlvl) ); mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay # ( .TCQ (TCQ), .tCK (tCK), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .N_CTL_LANES (N_CTL_LANES), .SIM_CAL_OPTION(SIM_CAL_OPTION) ) u_ddr_phy_ck_addr_cmd_delay ( .clk (clk), .rst (rst), .cmd_delay_start (dqs_po_dec_done & pi_fine_dly_dec_done), .ctl_lane_cnt (ctl_lane_cnt), .po_stg2_f_incdec (cmd_po_stg2_f_incdec), .po_en_stg2_f (cmd_po_en_stg2_f), .po_stg2_c_incdec (cmd_po_stg2_c_incdec), .po_en_stg2_c (cmd_po_en_stg2_c), .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done) ); assign cmd_po_stg2_incdec_ddr2_c = 1'b0; assign cmd_po_en_stg2_ddr2_c = 1'b0; end else begin: mb_wrlvl_off mig_7series_v2_3_ddr_phy_wrlvl_off_delay # ( .TCQ (TCQ), .tCK (tCK), .nCK_PER_CLK (nCK_PER_CLK), .CLK_PERIOD (CLK_PERIOD), .PO_INITIAL_DLY(60), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .N_CTL_LANES (N_CTL_LANES) ) u_phy_wrlvl_off_delay ( .clk (clk), .rst (rst), .pi_fine_dly_dec_done (pi_fine_dly_dec_done), .cmd_delay_start (phy_ctl_ready), .ctl_lane_cnt (ctl_lane_cnt), .po_s2_incdec_f (cmd_po_stg2_f_incdec), .po_en_s2_f (cmd_po_en_stg2_f), .po_s2_incdec_c (cmd_po_stg2_incdec_ddr2_c), .po_en_s2_c (cmd_po_en_stg2_ddr2_c), .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done), .po_dec_done (dqs_po_dec_done), .phy_ctl_rdy_dly (phy_ctl_rdy_dly) ); assign wrlvl_byte_done = 1'b1; assign wrlvl_rank_done = 1'b1; assign po_stg2_wl_cnt = 'h0; assign wl_po_coarse_cnt = 'h0; assign wl_po_fine_cnt = 'h0; assign dbg_tap_cnt_during_wrlvl = 'h0; assign dbg_wl_edge_detect_valid = 'h0; assign dbg_rd_data_edge_detect = 'h0; assign dbg_wrlvl_fine_tap_cnt = 'h0; assign dbg_wrlvl_coarse_tap_cnt = 'h0; assign dbg_phy_wrlvl = 'h0; assign wrlvl_done = 1'b1; assign wrlvl_err = 1'b0; assign dqs_po_stg2_f_incdec = 1'b0; assign dqs_po_en_stg2_f = 1'b0; assign dqs_wl_po_en_stg2_c = 1'b0; assign cmd_po_stg2_c_incdec = 1'b0; assign dqs_wl_po_stg2_c_incdec = 1'b0; assign cmd_po_en_stg2_c = 1'b0; end endgenerate generate if((WRLVL == "ON") && (OCAL_EN == "ON")) begin: oclk_calib localparam SAMPCNTRWIDTH = 17; localparam SAMPLES = (SIM_CAL_OPTION=="NONE") ? 2048 : 4; localparam TAPCNTRWIDTH = clogb2(TAPSPERKCLK); localparam MMCM_SAMP_WAIT = (SIM_CAL_OPTION=="NONE") ? 256 : 10; localparam OCAL_SIMPLE_SCAN_SAMPS = (SIM_CAL_OPTION=="NONE") ? 2048 : 1; localparam POC_PCT_SAMPS_SOLID = 80; localparam SCAN_PCT_SAMPS_SOLID = 95; mig_7series_v2_3_ddr_phy_oclkdelay_cal # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DQ_WIDTH (DQ_WIDTH), //.DRAM_TYPE (DRAM_TYPE), .DRAM_WIDTH (DRAM_WIDTH), //.OCAL_EN (OCAL_EN), .OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS), .PCT_SAMPS_SOLID (POC_PCT_SAMPS_SOLID), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), .SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .SAMPLES (SAMPLES), .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), .SIM_CAL_OPTION (SIM_CAL_OPTION), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL) //.tCK (tCK) ) u_ddr_phy_oclkdelay_cal (/*AUTOINST*/ // Outputs .prbs_ignore_first_byte (prbs_ignore_first_byte), .prbs_ignore_last_bytes (prbs_ignore_last_bytes), .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done), .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data[16*DRAM_WIDTH-1:0]), .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal[255:0]), .lim2init_write_request (lim2init_write_request), .lim_done (lim_done), .oclk_calib_resume (oclk_calib_resume), //.oclk_init_delay_done (oclk_init_delay_done), .oclk_prech_req (oclk_prech_req), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .oclkdelay_calib_done (oclkdelay_calib_done), .po_en_stg23 (po_en_stg23), //.po_en_stg3 (po_en_stg3), .po_stg23_incdec (po_stg23_incdec), .po_stg23_sel (po_stg23_sel), //.po_stg3_incdec (po_stg3_incdec), .psen (psen), .psincdec (psincdec), .wrlvl_final (wrlvl_final), .rd_victim_sel (complex_ocal_rd_victim_sel), .ocal_num_samples_done_r (complex_ocal_num_samples_done_r), .complex_wrlvl_final (complex_wrlvl_final), .poc_error (poc_error), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start_w), .metaQ (pd_out), //.oclk_init_delay_start (oclk_init_delay_start), .po_counter_read_val (po_counter_read_val), .oclkdelay_calib_start (oclkdelay_calib_start), .oclkdelay_init_val (oclkdelay_init_val[5:0]), .poc_sample_pd (poc_sample_pd), .phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]), .phy_rddata_en (phy_rddata_en), .prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]), .prech_done (prech_done), .psdone (psdone), .rst (rst), .wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0]), .ocal_num_samples_inc (complex_ocal_num_samples_inc), .oclkdelay_center_calib_start (oclkdelay_center_calib_start), .oclk_center_write_resume (oclk_center_write_resume), .oclkdelay_center_calib_done (oclkdelay_center_calib_done), .dbg_ocd_lim (dbg_ocd_lim)); end else begin : oclk_calib_disabled assign wrlvl_final = 'b0; assign psen = 'b0; assign psincdec = 'b0; assign po_stg23_sel = 'b0; assign po_stg23_incdec = 'b0; assign po_en_stg23 = 'b0; //assign oclk_init_delay_done = 1'b1; assign oclkdelay_calib_cnt = 'b0; assign oclk_prech_req = 'b0; assign oclk_calib_resume = 'b0; assign oclkdelay_calib_done = 1'b1; assign dbg_phy_oclkdelay_cal = 'h0; assign dbg_oclkdelay_rd_data = 'h0; end endgenerate //*************************************************************************** // Read data-offset calibration required for Phaser_In //*************************************************************************** generate if(DQSFOUND_CAL == "RIGHT") begin: dqsfind_calib_right mig_7series_v2_3_ddr_phy_dqs_found_cal # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .nCL (nCL), .AL (AL), .nCWL (nCWL), //.RANKS (RANKS), .RANKS (1), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .REG_CTRL (REG_CTRL), .SIM_CAL_OPTION (SIM_CAL_OPTION), .DRAM_TYPE (DRAM_TYPE), .NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL), .N_CTL_LANES (DQS_FOUND_N_CTL_LANES), .HIGHEST_LANE (HIGHEST_LANE), .HIGHEST_BANK (HIGHEST_BANK), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4) ) u_ddr_phy_dqs_found_cal ( .clk (clk), .rst (rst), .pi_dqs_found_start (pi_dqs_found_start), .dqsfound_retry (dqsfound_retry), .detect_pi_found_dqs (detect_pi_found_dqs), .prech_done (prech_done), .pi_dqs_found_lanes (pi_dqs_found_lanes), .pi_rst_stg1_cal (pi_rst_stg1_cal), .rd_data_offset_0 (rd_data_offset_0), .rd_data_offset_1 (rd_data_offset_1), .rd_data_offset_2 (rd_data_offset_2), .pi_dqs_found_rank_done (pi_dqs_found_rank_done), .pi_dqs_found_done (pi_dqs_found_done), .dqsfound_retry_done (dqsfound_retry_done), .dqs_found_prech_req (dqs_found_prech_req), .pi_dqs_found_err (pi_dqs_found_err), .rd_data_offset_ranks_0 (rd_data_offset_ranks_0), .rd_data_offset_ranks_1 (rd_data_offset_ranks_1), .rd_data_offset_ranks_2 (rd_data_offset_ranks_2), .rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0), .rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1), .rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2), .po_counter_read_val (po_counter_read_val), .rd_data_offset_cal_done (rd_data_offset_cal_done), .fine_adjust_done (fine_adjust_done), .fine_adjust_lane_cnt (fine_adjust_lane_cnt), .ck_po_stg2_f_indec (ck_po_stg2_f_indec), .ck_po_stg2_f_en (ck_po_stg2_f_en), .dbg_dqs_found_cal (dbg_dqs_found_cal) ); end else begin: dqsfind_calib_left mig_7series_v2_3_ddr_phy_dqs_found_cal_hr # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .nCL (nCL), .AL (AL), .nCWL (nCWL), //.RANKS (RANKS), .RANKS (1), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .REG_CTRL (REG_CTRL), .SIM_CAL_OPTION (SIM_CAL_OPTION), .DRAM_TYPE (DRAM_TYPE), .NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL), .N_CTL_LANES (DQS_FOUND_N_CTL_LANES), .HIGHEST_LANE (HIGHEST_LANE), .HIGHEST_BANK (HIGHEST_BANK), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4) ) u_ddr_phy_dqs_found_cal_hr ( .clk (clk), .rst (rst), .pi_dqs_found_start (pi_dqs_found_start), .dqsfound_retry (dqsfound_retry), .detect_pi_found_dqs (detect_pi_found_dqs), .prech_done (prech_done), .pi_dqs_found_lanes (pi_dqs_found_lanes), .pi_rst_stg1_cal (pi_rst_stg1_cal), .rd_data_offset_0 (rd_data_offset_0), .rd_data_offset_1 (rd_data_offset_1), .rd_data_offset_2 (rd_data_offset_2), .pi_dqs_found_rank_done (pi_dqs_found_rank_done), .pi_dqs_found_done (pi_dqs_found_done), .dqsfound_retry_done (dqsfound_retry_done), .dqs_found_prech_req (dqs_found_prech_req), .pi_dqs_found_err (pi_dqs_found_err), .rd_data_offset_ranks_0 (rd_data_offset_ranks_0), .rd_data_offset_ranks_1 (rd_data_offset_ranks_1), .rd_data_offset_ranks_2 (rd_data_offset_ranks_2), .rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0), .rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1), .rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2), .po_counter_read_val (po_counter_read_val), .rd_data_offset_cal_done (rd_data_offset_cal_done), .fine_adjust_done (fine_adjust_done), .fine_adjust_lane_cnt (fine_adjust_lane_cnt), .ck_po_stg2_f_indec (ck_po_stg2_f_indec), .ck_po_stg2_f_en (ck_po_stg2_f_en), .dbg_dqs_found_cal (dbg_dqs_found_cal) ); end endgenerate //*************************************************************************** // Read-leveling calibration logic //*************************************************************************** mig_7series_v2_3_ddr_phy_rdlvl # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .CLK_PERIOD (CLK_PERIOD), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .RANKS (1), .PER_BIT_DESKEW (PER_BIT_DESKEW), .SIM_CAL_OPTION (SIM_CAL_OPTION), .DEBUG_PORT (DEBUG_PORT), .DRAM_TYPE (DRAM_TYPE), .OCAL_EN (OCAL_EN), .IDELAY_ADJ (IDELAY_ADJ) ) u_ddr_phy_rdlvl ( .clk (clk), .rst (rst), .mpr_rdlvl_done (mpr_rdlvl_done), .mpr_rdlvl_start (mpr_rdlvl_start), .mpr_last_byte_done (mpr_last_byte_done), .mpr_rnk_done (mpr_rnk_done), .rdlvl_stg1_start (rdlvl_stg1_start), .rdlvl_stg1_done (rdlvl_stg1_done), .rdlvl_stg1_rnk_done (rdlvl_stg1_rank_done), .rdlvl_stg1_err (rdlvl_stg1_err), .mpr_rdlvl_err (mpr_rdlvl_err), .rdlvl_err (rdlvl_err), .rdlvl_prech_req (rdlvl_prech_req), .rdlvl_last_byte_done (rdlvl_last_byte_done), .rdlvl_assrt_common (rdlvl_assrt_common), .prech_done (prech_done), .phy_if_empty (phy_if_empty), .idelaye2_init_val (idelaye2_init_val), .rd_data (phy_rddata), .pi_en_stg2_f (rdlvl_pi_stg2_f_en), .pi_stg2_f_incdec (rdlvl_pi_stg2_f_incdec), .pi_stg2_load (pi_stg2_load), .pi_stg2_reg_l (pi_stg2_reg_l), .dqs_po_dec_done (dqs_po_dec_done), .pi_counter_read_val (pi_counter_read_val), .pi_fine_dly_dec_done (pi_fine_dly_dec_done), .idelay_ce (idelay_ce_int), .idelay_inc (idelay_inc_int), .idelay_ld (idelay_ld), .wrcal_cnt (po_stg2_wrcal_cnt), .pi_stg2_rdlvl_cnt (pi_stg2_rdlvl_cnt), .dlyval_dq (dlyval_dq), .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), .dbg_idel_up_all (dbg_idel_up_all), .dbg_idel_down_all (dbg_idel_down_all), .dbg_idel_up_cpt (dbg_idel_up_cpt), .dbg_idel_down_cpt (dbg_idel_down_cpt), .dbg_sel_idel_cpt (dbg_sel_idel_cpt), .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), .dbg_phy_rdlvl (dbg_phy_rdlvl) ); generate if((DRAM_TYPE == "DDR3") && (nCK_PER_CLK == 4) && (BYPASS_COMPLEX_RDLVL=="FALSE")) begin:ddr_phy_prbs_rdlvl_gen mig_7series_v2_3_ddr_phy_prbs_rdlvl # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .RANKS (1), .SIM_CAL_OPTION (SIM_CAL_OPTION), .PRBS_WIDTH (PRBS_WIDTH), .FIXED_VICTIM (FIXED_VICTIM), .FINE_PER_BIT (FINE_PER_BIT), .CENTER_COMP_MODE (CENTER_COMP_MODE), .PI_VAL_ADJ (PI_VAL_ADJ) ) u_ddr_phy_prbs_rdlvl ( .clk (clk), .rst (rst), .prbs_rdlvl_start (prbs_rdlvl_start), .prbs_rdlvl_done (prbs_rdlvl_done), .prbs_last_byte_done (prbs_last_byte_done), .prbs_rdlvl_prech_req (prbs_rdlvl_prech_req), .complex_sample_cnt_inc (complex_sample_cnt_inc), .prech_done (prech_done), .phy_if_empty (phy_if_empty), .rd_data (phy_rddata), .compare_data (prbs_o), .pi_counter_read_val (pi_counter_read_val), .pi_en_stg2_f (prbs_pi_stg2_f_en), .pi_stg2_f_incdec (prbs_pi_stg2_f_incdec), .dbg_prbs_rdlvl (dbg_prbs_rdlvl), .pi_stg2_prbs_rdlvl_cnt (pi_stg2_prbs_rdlvl_cnt), .prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r), .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps), .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps), .rd_victim_sel (rd_victim_sel), .complex_victim_inc (complex_victim_inc), .reset_rd_addr (reset_rd_addr), .read_pause (read_pause), .fine_delay_incdec_pb (fine_delay_incdec_pb), .fine_delay_sel (fine_delay_sel) ); end else begin:ddr_phy_prbs_rdlvl_off assign prbs_rdlvl_done = rdlvl_stg1_done ; //assign prbs_last_byte_done = rdlvl_stg1_rank_done ; assign prbs_last_byte_done = rdlvl_stg1_done; assign read_pause = 1'b0; assign reset_rd_addr = 1'b0; assign prbs_rdlvl_prech_req = 1'b0 ; assign prbs_pi_stg2_f_en = 1'b0 ; assign prbs_pi_stg2_f_incdec = 1'b0 ; assign pi_stg2_prbs_rdlvl_cnt = 'b0 ; assign dbg_prbs_rdlvl = 'h0 ; assign prbs_final_dqs_tap_cnt_r = {(6*DQS_WIDTH*RANKS){1'b0}}; assign dbg_prbs_first_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}}; assign dbg_prbs_second_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}}; end endgenerate //*************************************************************************** // Temperature induced PI tap adjustment logic //*************************************************************************** mig_7series_v2_3_ddr_phy_tempmon # ( .TCQ (TCQ) ) ddr_phy_tempmon_0 ( .rst (rst), .clk (clk), .calib_complete (calib_complete), .tempmon_pi_f_inc (tempmon_pi_f_inc), .tempmon_pi_f_dec (tempmon_pi_f_dec), .tempmon_sel_pi_incdec (tempmon_sel_pi_incdec), .device_temp (device_temp), .tempmon_sample_en (tempmon_sample_en) ); endmodule

//***************************************************************************** // (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: ddr_calib_top.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:06 $ // \ \ / \ Date Created: Aug 03 2009 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: //Purpose: // Top-level for memory physical layer (PHY) interface // NOTES: // 1. Need to support multiple copies of CS outputs // 2. DFI_DRAM_CKE_DISABLE not supported // //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: ddr_calib_top.v,v 1.1 2011/06/02 08:35:06 mishra Exp $ **$Date: 2011/06/02 08:35:06 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_calib_top.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_ddr_calib_top # ( parameter TCQ = 100, parameter nCK_PER_CLK = 2, // # of memory clocks per CLK parameter tCK = 2500, // DDR3 SDRAM clock period parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3 parameter CLK_PERIOD = 3333, // Internal clock period (in ps) parameter N_CTL_LANES = 3, // # of control byte lanes in the PHY parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2" parameter PRBS_WIDTH = 8, // The PRBS sequence is 2^PRBS_WIDTH parameter HIGHEST_LANE = 4, parameter HIGHEST_BANK = 3, parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO" // five fields, one per possible I/O bank, 4 bits in each field, // 1 per lane data=1/ctl=0 parameter DATA_CTL_B0 = 4'hc, parameter DATA_CTL_B1 = 4'hf, parameter DATA_CTL_B2 = 4'hf, parameter DATA_CTL_B3 = 4'hf, parameter DATA_CTL_B4 = 4'hf, // defines the byte lanes in I/O banks being used in the interface // 1- Used, 0- Unused parameter BYTE_LANES_B0 = 4'b1111, parameter BYTE_LANES_B1 = 4'b0000, parameter BYTE_LANES_B2 = 4'b0000, parameter BYTE_LANES_B3 = 4'b0000, parameter BYTE_LANES_B4 = 4'b0000, parameter DQS_BYTE_MAP = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00, parameter CTL_BYTE_LANE = 8'hE4, // Control byte lane map parameter CTL_BANK = 3'b000, // Bank used for control byte lanes // Slot Conifg parameters parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000, // DRAM bus widths parameter BANK_WIDTH = 2, // # of bank bits parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank parameter COL_WIDTH = 10, // column address width parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank parameter DQ_WIDTH = 64, // # of DQ (data) parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH)) parameter DQS_WIDTH = 8, // # of DQS (strobe) parameter DRAM_WIDTH = 8, // # of DQ per DQS parameter ROW_WIDTH = 14, // DRAM address bus width parameter RANKS = 1, // # of memory ranks in the interface parameter CS_WIDTH = 1, // # of CS# signals in the interface parameter CKE_WIDTH = 1, // # of cke outputs parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2 parameter PER_BIT_DESKEW = "ON", // calibration Address. The address given below will be used for calibration // read and write operations. parameter NUM_DQSFOUND_CAL = 1020, // # of iteration of DQSFOUND calib parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address parameter CALIB_COL_ADD = 12'h000, // Calibration column address parameter CALIB_BA_ADD = 3'h0, // Calibration bank address // DRAM mode settings parameter AL = "0", // Additive Latency option parameter TEST_AL = "0", // Additive Latency for internal use parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T" parameter BURST_MODE = "8", // Burst length parameter BURST_TYPE = "SEQ", // Burst type parameter nCL = 5, // Read CAS latency (in clk cyc) parameter nCWL = 5, // Write CAS latency (in clk cyc) parameter tRFC = 110000, // Refresh-to-command delay parameter tREFI = 7800000, // pS Refresh-to-Refresh delay parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option parameter REG_CTRL = "ON", // "ON" for registered DIMM parameter RTT_NOM = "60", // ODT Nominal termination value parameter RTT_WR = "60", // ODT Write termination value parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA // 1 - ODT output from FPGA parameter WRLVL = "OFF", // Enable write leveling parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly parameter POC_USE_METASTABLE_SAMP = "FALSE", // Simulation /debug options parameter SIM_INIT_OPTION = "NONE", // Performs all initialization steps parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps parameter CKE_ODT_AUX = "FALSE", parameter IDELAY_ADJ = "ON", parameter FINE_PER_BIT = "ON", parameter CENTER_COMP_MODE = "ON", parameter PI_VAL_ADJ = "ON", parameter TAPSPERKCLK = 56, parameter DEBUG_PORT = "OFF" // Enable debug port ) ( input clk, // Internal (logic) clock input rst, // Reset sync'ed to CLK // Slot present inputs input [7:0] slot_0_present, input [7:0] slot_1_present, // Hard PHY signals // From PHY Ctrl Block input phy_ctl_ready, input phy_ctl_full, input phy_cmd_full, input phy_data_full, // To PHY Ctrl Block output write_calib, output read_calib, output calib_ctl_wren, output calib_cmd_wren, output [1:0] calib_seq, output [3:0] calib_aux_out, output [nCK_PER_CLK -1:0] calib_cke, output [1:0] calib_odt, output [2:0] calib_cmd, output calib_wrdata_en, output [1:0] calib_rank_cnt, output [1:0] calib_cas_slot, output [5:0] calib_data_offset_0, output [5:0] calib_data_offset_1, output [5:0] calib_data_offset_2, output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address, output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank, output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n, output [nCK_PER_CLK-1:0] phy_ras_n, output [nCK_PER_CLK-1:0] phy_cas_n, output [nCK_PER_CLK-1:0] phy_we_n, output phy_reset_n, // To hard PHY wrapper output reg [5:0] calib_sel/* synthesis syn_maxfan = 10 */, output reg calib_in_common/* synthesis syn_maxfan = 10 */, output reg [HIGHEST_BANK-1:0] calib_zero_inputs/* synthesis syn_maxfan = 10 */, output reg [HIGHEST_BANK-1:0] calib_zero_ctrl, output phy_if_empty_def, output reg phy_if_reset, // output reg ck_addr_ctl_delay_done, // From DQS Phaser_In input pi_phaselocked, input pi_phase_locked_all, input pi_found_dqs, input pi_dqs_found_all, input [HIGHEST_LANE-1:0] pi_dqs_found_lanes, input [5:0] pi_counter_read_val, // To DQS Phaser_In output [HIGHEST_BANK-1:0] pi_rst_stg1_cal, output pi_en_stg2_f, output pi_stg2_f_incdec, output pi_stg2_load, output [5:0] pi_stg2_reg_l, // To DQ IDELAY output idelay_ce, output idelay_inc, output idelay_ld, // To DQS Phaser_Out output [2:0] po_sel_stg2stg3 /* synthesis syn_maxfan = 3 */, output [2:0] po_stg2_c_incdec /* synthesis syn_maxfan = 3 */, output [2:0] po_en_stg2_c /* synthesis syn_maxfan = 3 */, output [2:0] po_stg2_f_incdec /* synthesis syn_maxfan = 3 */, output [2:0] po_en_stg2_f /* synthesis syn_maxfan = 3 */, output po_counter_load_en, input [8:0] po_counter_read_val, // To command Phaser_Out input phy_if_empty, input [4:0] idelaye2_init_val, input [5:0] oclkdelay_init_val, input tg_err, output rst_tg_mc, // Write data to OUT_FIFO output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata, // To CNTVALUEIN input of DQ IDELAYs for perbit de-skew output [5*RANKS*DQ_WIDTH-1:0] dlyval_dq, // IN_FIFO read enable during write leveling, write calibration, // and read leveling // Read data from hard PHY fans out to mc and calib logic input[2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata, // To MC output [6*RANKS-1:0] calib_rd_data_offset_0, output [6*RANKS-1:0] calib_rd_data_offset_1, output [6*RANKS-1:0] calib_rd_data_offset_2, output phy_rddata_valid, output calib_writes, (* max_fanout = 50 *) output reg init_calib_complete/* synthesis syn_maxfan = 10 */, output init_wrcal_complete, output pi_phase_locked_err, output pi_dqsfound_err, output wrcal_err, input pd_out, // input mmcm_ps_clk, //phase shift clock // input oclkdelay_fb_clk, //Write DQS feedback clk //phase shift clock control output psen, output psincdec, input psdone, input poc_sample_pd, // Debug Port output dbg_pi_phaselock_start, output dbg_pi_dqsfound_start, output dbg_pi_dqsfound_done, output dbg_wrcal_start, output dbg_wrcal_done, output dbg_wrlvl_start, output dbg_wrlvl_done, output dbg_wrlvl_err, output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt, output [255:0] dbg_phy_wrlvl, output [5:0] dbg_tap_cnt_during_wrlvl, output dbg_wl_edge_detect_valid, output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect, // Write Calibration Logic output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt, output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt, output [99:0] dbg_phy_wrcal, // Read leveling logic output [1:0] dbg_rdlvl_start, output [1:0] dbg_rdlvl_done, output [1:0] dbg_rdlvl_err, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt, output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt, output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt, // Delay control input [11:0] device_temp, input tempmon_sample_en, input dbg_sel_pi_incdec, input dbg_sel_po_incdec, input [DQS_CNT_WIDTH:0] dbg_byte_sel, input dbg_pi_f_inc, input dbg_pi_f_dec, input dbg_po_f_inc, input dbg_po_f_stg23_sel, input dbg_po_f_dec, input dbg_idel_up_all, input dbg_idel_down_all, input dbg_idel_up_cpt, input dbg_idel_down_cpt, input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt, input dbg_sel_all_idel_cpt, output [255:0] dbg_phy_rdlvl, // Read leveling calibration output [255:0] dbg_calib_top, // General PHY debug output dbg_oclkdelay_calib_start, output dbg_oclkdelay_calib_done, output [255:0] dbg_phy_oclkdelay_cal, output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data, output [255:0] dbg_phy_init, output [255:0] dbg_prbs_rdlvl, output [255:0] dbg_dqs_found_cal, output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps, output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps, output reg [DQS_CNT_WIDTH:0] byte_sel_cnt, output [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit output fine_delay_sel ); function integer clogb2 (input integer size); begin size = size - 1; for (clogb2=1; size>1; clogb2=clogb2+1) size = size >> 1; end endfunction // Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center // align DQ and DQS on writes. Round (up or down) value to nearest integer // localparam integer SHIFT_TBY4_TAP // = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) / // (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4); // Calculate number of slots in the system localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0); localparam OCAL_EN = ((SIM_CAL_OPTION == "FAST_CAL") || (tCK > 2500)) ? "OFF" : "ON"; // Different CTL_LANES value for DDR2. In DDR2 during DQS found all // the add,ctl & data phaser out fine delays will be adjusted. // In DDR3 only the add/ctrl lane delays will be adjusted localparam DQS_FOUND_N_CTL_LANES = (DRAM_TYPE == "DDR3") ? N_CTL_LANES : 1; localparam DQSFOUND_CAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && tCK > 2500)) ? "LEFT" : "RIGHT"; // IO Bank used for Memory I/F: "LEFT", "RIGHT" localparam FIXED_VICTIM = (SIM_CAL_OPTION == "NONE") ? "FALSE" : "TRUE"; localparam VCCO_PAT_EN = 1; // Enable VCCO pattern during calibration localparam VCCAUX_PAT_EN = 1; // Enable VCCAUX pattern during calibration localparam ISI_PAT_EN = 1; // Enable VCCO pattern during calibration //Per-bit deskew for higher freqency (>800Mhz) //localparam FINE_DELAY = (tCK < 1250) ? "ON" : "OFF"; //BYPASS localparam BYPASS_COMPLEX_RDLVL = (tCK > 2500) ? "TRUE": "FALSE"; //"TRUE"; localparam BYPASS_COMPLEX_OCAL = "TRUE"; //localparam BYPASS_COMPLEX_OCAL = ((DRAM_TYPE == "DDR2") || (nCK_PER_CLK == 2) || (OCAL_EN == "OFF")) ? "TRUE" : "FALSE"; // 8*tREFI in ps is divided by the fabric clock period in ps // 270 fabric clock cycles is subtracted to account for PRECHARGE, WR, RD times localparam REFRESH_TIMER = (SIM_CAL_OPTION == "NONE") ? (8*tREFI/(tCK*nCK_PER_CLK)) - 270 : 10795; localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER); wire [2*8*nCK_PER_CLK-1:0] prbs_seed; //wire [2*8*nCK_PER_CLK-1:0] prbs_out; wire [8*DQ_WIDTH-1:0] prbs_out; wire [7:0] prbs_rise0; wire [7:0] prbs_fall0; wire [7:0] prbs_rise1; wire [7:0] prbs_fall1; wire [7:0] prbs_rise2; wire [7:0] prbs_fall2; wire [7:0] prbs_rise3; wire [7:0] prbs_fall3; //wire [2*8*nCK_PER_CLK-1:0] prbs_o; wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; wire dqsfound_retry; wire dqsfound_retry_done; wire phy_rddata_en; wire prech_done; wire rdlvl_stg1_done; reg rdlvl_stg1_done_r1; wire pi_dqs_found_done; wire rdlvl_stg1_err; wire pi_dqs_found_err; wire wrcal_pat_resume; wire wrcal_resume_w; wire rdlvl_prech_req; wire rdlvl_last_byte_done; wire rdlvl_stg1_start; wire rdlvl_stg1_rank_done; wire rdlvl_assrt_common; wire pi_dqs_found_start; wire pi_dqs_found_rank_done; wire wl_sm_start; wire wrcal_start; wire wrcal_rd_wait; wire wrcal_prech_req; wire wrcal_pat_err; wire wrcal_done; wire wrlvl_done; wire wrlvl_err; wire wrlvl_start; wire ck_addr_cmd_delay_done; wire po_ck_addr_cmd_delay_done; wire pi_calib_done; wire detect_pi_found_dqs; wire [5:0] rd_data_offset_0; wire [5:0] rd_data_offset_1; wire [5:0] rd_data_offset_2; wire [6*RANKS-1:0] rd_data_offset_ranks_0; wire [6*RANKS-1:0] rd_data_offset_ranks_1; wire [6*RANKS-1:0] rd_data_offset_ranks_2; wire [6*RANKS-1:0] rd_data_offset_ranks_mc_0; wire [6*RANKS-1:0] rd_data_offset_ranks_mc_1; wire [6*RANKS-1:0] rd_data_offset_ranks_mc_2; wire cmd_po_stg2_f_incdec; wire cmd_po_stg2_incdec_ddr2_c; wire cmd_po_en_stg2_f; wire cmd_po_en_stg2_ddr2_c; wire cmd_po_stg2_c_incdec; wire cmd_po_en_stg2_c; wire po_stg2_ddr2_incdec; wire po_en_stg2_ddr2; wire dqs_po_stg2_f_incdec; wire dqs_po_en_stg2_f; wire dqs_wl_po_stg2_c_incdec; wire wrcal_po_stg2_c_incdec; wire dqs_wl_po_en_stg2_c; wire wrcal_po_en_stg2_c; wire [N_CTL_LANES-1:0] ctl_lane_cnt; reg [N_CTL_LANES-1:0] ctl_lane_sel; wire [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt; wire [DQS_CNT_WIDTH:0] po_stg2_wl_cnt; wire [DQS_CNT_WIDTH:0] po_stg2_ddr2_cnt; wire [8:0] dqs_wl_po_stg2_reg_l; wire dqs_wl_po_stg2_load; wire [8:0] dqs_po_stg2_reg_l; wire dqs_po_stg2_load; wire dqs_po_dec_done; wire pi_fine_dly_dec_done; wire rdlvl_pi_stg2_f_incdec; wire rdlvl_pi_stg2_f_en; wire [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt; //reg [DQS_CNT_WIDTH:0] byte_sel_cnt; wire [3*DQS_WIDTH-1:0] wl_po_coarse_cnt; wire [6*DQS_WIDTH-1:0] wl_po_fine_cnt; wire phase_locked_err; wire phy_ctl_rdy_dly; wire idelay_ce_int; wire idelay_inc_int; reg idelay_ce_r1; reg idelay_ce_r2; reg idelay_inc_r1; reg idelay_inc_r2 /* synthesis syn_maxfan = 30 */; reg po_dly_req_r; wire wrcal_read_req; wire wrcal_act_req; wire temp_wrcal_done; wire tg_timer_done; wire no_rst_tg_mc; wire calib_complete; reg reset_if_r1; reg reset_if_r2; reg reset_if_r3; reg reset_if_r4; reg reset_if_r5; reg reset_if_r6; reg reset_if_r7; reg reset_if_r8; reg reset_if_r9; reg reset_if; wire phy_if_reset_w; wire pi_phaselock_start; reg dbg_pi_f_inc_r; reg dbg_pi_f_en_r; reg dbg_sel_pi_incdec_r; reg dbg_po_f_inc_r; reg dbg_po_f_stg23_sel_r; reg dbg_po_f_en_r; reg dbg_sel_po_incdec_r; reg tempmon_pi_f_inc_r; reg tempmon_pi_f_en_r; reg tempmon_sel_pi_incdec_r; reg ck_addr_cmd_delay_done_r1; reg ck_addr_cmd_delay_done_r2; reg ck_addr_cmd_delay_done_r3; reg ck_addr_cmd_delay_done_r4; reg ck_addr_cmd_delay_done_r5; reg ck_addr_cmd_delay_done_r6; // wire oclk_init_delay_start; wire oclk_prech_req; wire oclk_calib_resume; // wire oclk_init_delay_done; wire [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt; wire [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt; wire oclkdelay_calib_start; wire oclkdelay_calib_done; wire complex_oclk_prech_req; wire complex_oclk_calib_resume; wire complex_oclkdelay_calib_start; wire complex_oclkdelay_calib_done; wire complex_ocal_num_samples_inc; wire complex_ocal_num_samples_done_r; wire [2:0] complex_ocal_rd_victim_sel; wire complex_ocal_ref_req; wire complex_ocal_ref_done; wire [6*DQS_WIDTH-1:0] oclkdelay_left_edge_val; wire [6*DQS_WIDTH-1:0] oclkdelay_right_edge_val; wire wrlvl_final; wire complex_wrlvl_final; reg wrlvl_final_mux; wire wrlvl_final_if_rst; wire wrlvl_byte_redo; wire wrlvl_byte_done; wire early1_data; wire early2_data; //wire po_stg3_incdec; //wire po_en_stg3; wire po_stg23_sel; wire po_stg23_incdec; wire po_en_stg23; wire complex_po_stg23_sel; wire complex_po_stg23_incdec; wire complex_po_en_stg23; wire mpr_rdlvl_done; wire mpr_rdlvl_start; wire mpr_last_byte_done; wire mpr_rnk_done; wire mpr_end_if_reset; wire mpr_rdlvl_err; wire rdlvl_err; wire prbs_rdlvl_start; wire prbs_rdlvl_done; reg prbs_rdlvl_done_r1; wire prbs_last_byte_done; wire prbs_rdlvl_prech_req; wire prbs_pi_stg2_f_incdec; wire prbs_pi_stg2_f_en; wire complex_sample_cnt_inc; wire complex_sample_cnt_inc_ocal; wire [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt; wire prbs_gen_clk_en; wire prbs_gen_oclk_clk_en; wire rd_data_offset_cal_done; wire fine_adjust_done; wire [N_CTL_LANES-1:0] fine_adjust_lane_cnt; wire ck_po_stg2_f_indec; wire ck_po_stg2_f_en; wire dqs_found_prech_req; wire tempmon_pi_f_inc; wire tempmon_pi_f_dec; wire tempmon_sel_pi_incdec; wire wrcal_sanity_chk; wire wrcal_sanity_chk_done; wire wrlvl_done_w; wire wrlvl_rank_done; wire done_dqs_tap_inc; wire [2:0] rd_victim_sel; wire [2:0] victim_sel; wire [DQS_CNT_WIDTH:0] victim_byte_cnt; wire complex_wr_done; wire complex_victim_inc; wire reset_rd_addr; wire read_pause; wire complex_ocal_reset_rd_addr; wire oclkdelay_center_calib_start; wire poc_error; wire prbs_ignore_first_byte; wire prbs_ignore_last_bytes; //stg3 tap values // wire [6*DQS_WIDTH-1:0] oclkdelay_center_val; //byte selection // wire [DQS_CNT_WIDTH:0] oclkdelay_center_cnt; //INC/DEC for stg3 taps // wire ocal_ctr_po_stg23_sel; // wire ocal_ctr_po_stg23_incdec; // wire ocal_ctr_po_en_stg23; //Write resume for DQS toggling wire oclk_center_write_resume; wire oclkdelay_center_calib_done; //Write request to toggle DQS for limit module wire lim2init_write_request; wire lim_done; // Bypass complex ocal wire complex_oclkdelay_calib_start_w; wire complex_oclkdelay_calib_done_w; wire [2:0] complex_ocal_rd_victim_sel_w; wire complex_wrlvl_final_w; wire [255:0] dbg_ocd_lim; //with MMCM phase detect logic //wire mmcm_edge_detect_rdy; // ready for MMCM detect //wire ktap_at_rightedge; // stg3 tap at right edge //wire ktap_at_leftedge; // stg3 tap at left edge //wire mmcm_tap_at_center; // indicate stg3 tap at center //wire mmcm_ps_clkphase_ok; // ps clkphase is OK //wire mmcm_edge_detect_done; // mmcm edge detect is done //wire mmcm_lbclk_edges_aligned; // mmcm edge detect is done //wire reset_mmcm; //mmcm detect logic reset per byte // wire [255:0] dbg_phy_oclkdelay_center_cal; //***************************************************************************** // Assertions to check correctness of parameter values //***************************************************************************** // synthesis translate_off initial begin if (RANKS == 0) begin $display ("Error: Invalid RANKS parameter. Must be 1 or greater"); $finish; end if (phy_ctl_full == 1'b1) begin $display ("Error: Incorrect phy_ctl_full input value in 2:1 or 4:1 mode"); $finish; end end // synthesis translate_on //*************************************************************************** // Debug //*************************************************************************** assign dbg_pi_phaselock_start = pi_phaselock_start; assign dbg_pi_dqsfound_start = pi_dqs_found_start; assign dbg_pi_dqsfound_done = pi_dqs_found_done; assign dbg_wrcal_start = wrcal_start; assign dbg_wrcal_done = wrcal_done; // Unused for now - use these as needed to bring up lower level signals assign dbg_calib_top = dbg_ocd_lim; // Write Level and write calibration debug observation ports assign dbg_wrlvl_start = wrlvl_start; assign dbg_wrlvl_done = wrlvl_done; assign dbg_wrlvl_err = wrlvl_err; // Read Level debug observation ports assign dbg_rdlvl_start = {mpr_rdlvl_start, rdlvl_stg1_start}; assign dbg_rdlvl_done = {mpr_rdlvl_done, rdlvl_stg1_done}; assign dbg_rdlvl_err = {mpr_rdlvl_err, rdlvl_err}; assign dbg_oclkdelay_calib_done = oclkdelay_calib_done; assign dbg_oclkdelay_calib_start = oclkdelay_calib_start; //*************************************************************************** // Write leveling dependent signals //*************************************************************************** assign wrcal_resume_w = (WRLVL == "ON") ? wrcal_pat_resume : 1'b0; assign wrlvl_done_w = (WRLVL == "ON") ? wrlvl_done : 1'b1; assign ck_addr_cmd_delay_done = (WRLVL == "ON") ? po_ck_addr_cmd_delay_done : (po_ck_addr_cmd_delay_done && pi_fine_dly_dec_done) ; generate if((WRLVL == "ON") && (BYPASS_COMPLEX_OCAL=="FALSE")) begin: complex_oclk_calib assign complex_oclkdelay_calib_start_w = complex_oclkdelay_calib_start; assign complex_oclkdelay_calib_done_w = complex_oclkdelay_calib_done; assign complex_ocal_rd_victim_sel_w = complex_ocal_rd_victim_sel; assign complex_wrlvl_final_w = complex_wrlvl_final; end else begin: bypass_complex_ocal assign complex_oclkdelay_calib_start_w = 1'b0; assign complex_oclkdelay_calib_done_w = prbs_rdlvl_done; assign complex_ocal_rd_victim_sel_w = 'd0; assign complex_wrlvl_final_w = 1'b0; end endgenerate generate genvar i; for (i = 0; i <= 2; i = i+1) begin : bankwise_signal assign po_sel_stg2stg3[i] = ((ck_addr_cmd_delay_done && ~oclkdelay_calib_done && mpr_rdlvl_done) ? po_stg23_sel : (complex_oclkdelay_calib_start_w&&~complex_oclkdelay_calib_done_w? po_stg23_sel : 1'b0 ) // (~oclkdelay_center_calib_done? ocal_ctr_po_stg23_sel:1'b0)) ) | dbg_po_f_stg23_sel_r; assign po_stg2_c_incdec[i] = cmd_po_stg2_c_incdec || cmd_po_stg2_incdec_ddr2_c || dqs_wl_po_stg2_c_incdec; assign po_en_stg2_c[i] = cmd_po_en_stg2_c || cmd_po_en_stg2_ddr2_c || dqs_wl_po_en_stg2_c; assign po_stg2_f_incdec[i] = dqs_po_stg2_f_incdec || cmd_po_stg2_f_incdec || //po_stg3_incdec || ck_po_stg2_f_indec || po_stg23_incdec || // complex_po_stg23_incdec || // ocal_ctr_po_stg23_incdec || dbg_po_f_inc_r; assign po_en_stg2_f[i] = dqs_po_en_stg2_f || cmd_po_en_stg2_f || //po_en_stg3 || ck_po_stg2_f_en || po_en_stg23 || // complex_po_en_stg23 || // ocal_ctr_po_en_stg23 || dbg_po_f_en_r; end endgenerate assign pi_stg2_f_incdec = (dbg_pi_f_inc_r | rdlvl_pi_stg2_f_incdec | prbs_pi_stg2_f_incdec | tempmon_pi_f_inc_r); assign pi_en_stg2_f = (dbg_pi_f_en_r | rdlvl_pi_stg2_f_en | prbs_pi_stg2_f_en | tempmon_pi_f_en_r); assign idelay_ce = idelay_ce_r2; assign idelay_inc = idelay_inc_r2; assign po_counter_load_en = 1'b0; assign complex_oclkdelay_calib_cnt = oclkdelay_calib_cnt; assign complex_oclk_calib_resume = oclk_calib_resume; assign complex_ocal_ref_req = oclk_prech_req; // Added single stage flop to meet timing always @(posedge clk) init_calib_complete <= calib_complete; assign calib_rd_data_offset_0 = rd_data_offset_ranks_mc_0; assign calib_rd_data_offset_1 = rd_data_offset_ranks_mc_1; assign calib_rd_data_offset_2 = rd_data_offset_ranks_mc_2; //*************************************************************************** // Hard PHY signals //*************************************************************************** assign pi_phase_locked_err = phase_locked_err; assign pi_dqsfound_err = pi_dqs_found_err; assign wrcal_err = wrcal_pat_err; assign rst_tg_mc = 1'b0; //Restart WRLVL after oclkdealy cal always @ (posedge clk) wrlvl_final_mux <= #TCQ complex_oclkdelay_calib_start_w? complex_wrlvl_final_w: wrlvl_final; always @(posedge clk) phy_if_reset <= #TCQ (phy_if_reset_w | mpr_end_if_reset | reset_if | wrlvl_final_if_rst); //*************************************************************************** // Phaser_IN inc dec control for debug //*************************************************************************** always @(posedge clk) begin if (rst) begin dbg_pi_f_inc_r <= #TCQ 1'b0; dbg_pi_f_en_r <= #TCQ 1'b0; dbg_sel_pi_incdec_r <= #TCQ 1'b0; end else begin dbg_pi_f_inc_r <= #TCQ dbg_pi_f_inc; dbg_pi_f_en_r <= #TCQ (dbg_pi_f_inc | dbg_pi_f_dec); dbg_sel_pi_incdec_r <= #TCQ dbg_sel_pi_incdec; end end //*************************************************************************** // Phaser_OUT inc dec control for debug //*************************************************************************** always @(posedge clk) begin if (rst) begin dbg_po_f_inc_r <= #TCQ 1'b0; dbg_po_f_stg23_sel_r<= #TCQ 1'b0; dbg_po_f_en_r <= #TCQ 1'b0; dbg_sel_po_incdec_r <= #TCQ 1'b0; end else begin dbg_po_f_inc_r <= #TCQ dbg_po_f_inc; dbg_po_f_stg23_sel_r<= #TCQ dbg_po_f_stg23_sel; dbg_po_f_en_r <= #TCQ (dbg_po_f_inc | dbg_po_f_dec); dbg_sel_po_incdec_r <= #TCQ dbg_sel_po_incdec; end end //*************************************************************************** // Phaser_IN inc dec control for temperature tracking //*************************************************************************** always @(posedge clk) begin if (rst) begin tempmon_pi_f_inc_r <= #TCQ 1'b0; tempmon_pi_f_en_r <= #TCQ 1'b0; tempmon_sel_pi_incdec_r <= #TCQ 1'b0; end else begin tempmon_pi_f_inc_r <= #TCQ tempmon_pi_f_inc; tempmon_pi_f_en_r <= #TCQ (tempmon_pi_f_inc | tempmon_pi_f_dec); tempmon_sel_pi_incdec_r <= #TCQ tempmon_sel_pi_incdec; end end //*************************************************************************** // OCLKDELAY calibration signals //*************************************************************************** // Minimum of 5 'clk' cycles required between assertion of po_sel_stg2stg3 // and increment/decrement of Phaser_Out stage 3 delay always @(posedge clk) begin ck_addr_cmd_delay_done_r1 <= #TCQ ck_addr_cmd_delay_done; ck_addr_cmd_delay_done_r2 <= #TCQ ck_addr_cmd_delay_done_r1; ck_addr_cmd_delay_done_r3 <= #TCQ ck_addr_cmd_delay_done_r2; ck_addr_cmd_delay_done_r4 <= #TCQ ck_addr_cmd_delay_done_r3; ck_addr_cmd_delay_done_r5 <= #TCQ ck_addr_cmd_delay_done_r4; ck_addr_cmd_delay_done_r6 <= #TCQ ck_addr_cmd_delay_done_r5; end //*************************************************************************** // MUX select logic to select current byte undergoing calibration // Use DQS_CAL_MAP to determine the correlation between the physical // byte numbering, and the byte numbering within the hard PHY //*************************************************************************** generate if (tCK > 2500) begin: gen_byte_sel_div2 always @(posedge clk) begin if (rst) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b0; end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~ck_addr_cmd_delay_done) begin ctl_lane_sel <= #TCQ ctl_lane_cnt; calib_in_common <= #TCQ 1'b0; end else if (~fine_adjust_done && rd_data_offset_cal_done) begin if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ fine_adjust_lane_cnt; calib_in_common <= #TCQ 1'b0; end end else if (~pi_calib_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~pi_dqs_found_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~wrlvl_done_w) begin if (SIM_CAL_OPTION != "FAST_CAL") begin byte_sel_cnt <= #TCQ po_stg2_wl_cnt; calib_in_common <= #TCQ 1'b0; end else begin // Special case for FAST_CAL simulation only to ensure that // calib_in_common isn't asserted too soon if (!phy_ctl_rdy_dly) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b0; end else begin byte_sel_cnt <= #TCQ po_stg2_wl_cnt; calib_in_common <= #TCQ 1'b1; end end end else if (~mpr_rdlvl_done) begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end else if (~oclkdelay_calib_done) begin byte_sel_cnt <= #TCQ oclkdelay_calib_cnt; calib_in_common <= #TCQ 1'b0; end else if (~rdlvl_stg1_done && pi_calib_done) begin if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b1; end else begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt; calib_in_common <= #TCQ 1'b0; end else if (~wrcal_done) begin byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt; calib_in_common <= #TCQ 1'b0; end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin byte_sel_cnt <= #TCQ dbg_byte_sel; calib_in_common <= #TCQ 1'b0; end else if (tempmon_sel_pi_incdec) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end end end else begin: gen_byte_sel_div1 always @(posedge clk) begin if (rst) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b0; end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~ck_addr_cmd_delay_done) begin ctl_lane_sel <= #TCQ ctl_lane_cnt; calib_in_common <= #TCQ 1'b0; end else if (~fine_adjust_done && rd_data_offset_cal_done) begin if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else begin byte_sel_cnt <= #TCQ 'd0; ctl_lane_sel <= #TCQ fine_adjust_lane_cnt; calib_in_common <= #TCQ 1'b0; end end else if (~pi_calib_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~pi_dqs_found_done) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end else if (~wrlvl_done_w) begin if (SIM_CAL_OPTION != "FAST_CAL") begin byte_sel_cnt <= #TCQ po_stg2_wl_cnt; calib_in_common <= #TCQ 1'b0; end else begin // Special case for FAST_CAL simulation only to ensure that // calib_in_common isn't asserted too soon if (!phy_ctl_rdy_dly) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b0; end else begin byte_sel_cnt <= #TCQ po_stg2_wl_cnt; calib_in_common <= #TCQ 1'b1; end end end else if (~mpr_rdlvl_done) begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end else if (~oclkdelay_calib_done) begin byte_sel_cnt <= #TCQ oclkdelay_calib_cnt; calib_in_common <= #TCQ 1'b0; end else if ((~wrcal_done)&& (DRAM_TYPE == "DDR3")) begin byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt; calib_in_common <= #TCQ 1'b0; end else if (~rdlvl_stg1_done && pi_calib_done) begin if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b1; end else begin byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt; calib_in_common <= #TCQ 1'b0; end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt; calib_in_common <= #TCQ 1'b0; end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin byte_sel_cnt <= #TCQ dbg_byte_sel; calib_in_common <= #TCQ 1'b0; end else if (tempmon_sel_pi_incdec) begin byte_sel_cnt <= #TCQ 'd0; calib_in_common <= #TCQ 1'b1; end end end endgenerate // verilint STARC-2.2.3.3 off always @(posedge clk) begin if (rst || (calib_complete && ~ (dbg_sel_pi_incdec_r|dbg_sel_po_incdec_r|tempmon_sel_pi_incdec) )) begin calib_sel <= #TCQ 6'b000100; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; if (~dqs_po_dec_done && (WRLVL != "ON")) //if (~dqs_po_dec_done && ((SIM_CAL_OPTION == "FAST_CAL") ||(WRLVL != "ON"))) calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}}; else calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else if (~ck_addr_cmd_delay_done || (~fine_adjust_done && rd_data_offset_cal_done)) begin if(WRLVL =="ON") begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ CTL_BYTE_LANE[(ctl_lane_sel*2)+:2]; calib_sel[5:3] <= #TCQ CTL_BANK; if (|pi_rst_stg1_cal) begin calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; end else begin calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; calib_zero_inputs[1*CTL_BANK] <= #TCQ 1'b0; end calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else begin // if (WRLVL =="ON") calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; if(~ck_addr_cmd_delay_done) calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; else calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}}; end // else: !if(WRLVL =="ON") end else if ((~wrlvl_done_w) && (SIM_CAL_OPTION == "FAST_CAL")) begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else if (~rdlvl_stg1_done && (SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else if (tempmon_sel_pi_incdec) begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; end else begin calib_sel[2] <= #TCQ 1'b0; calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2]; calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3]; calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}}; if (~calib_in_common) begin calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}}; calib_zero_inputs[(1*DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3])] <= #TCQ 1'b0; end else calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}}; end end // verilint STARC-2.2.3.3 on // Logic to reset IN_FIFO flags to account for the possibility that // one or more PHASER_IN's have not correctly found the DQS preamble // If this happens, we can still complete read leveling, but the # of // words written into the IN_FIFO's may be an odd #, so that if the // IN_FIFO is used in 2:1 mode ("8:4 mode"), there may be a "half" word // of data left that can only be flushed out by reseting the IN_FIFO always @(posedge clk) begin rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done; prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done; reset_if_r1 <= #TCQ reset_if; reset_if_r2 <= #TCQ reset_if_r1; reset_if_r3 <= #TCQ reset_if_r2; reset_if_r4 <= #TCQ reset_if_r3; reset_if_r5 <= #TCQ reset_if_r4; reset_if_r6 <= #TCQ reset_if_r5; reset_if_r7 <= #TCQ reset_if_r6; reset_if_r8 <= #TCQ reset_if_r7; reset_if_r9 <= #TCQ reset_if_r8; end always @(posedge clk) begin if (rst || reset_if_r9) reset_if <= #TCQ 1'b0; else if ((rdlvl_stg1_done && ~rdlvl_stg1_done_r1) || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1)) reset_if <= #TCQ 1'b1; end assign phy_if_empty_def = 1'b0; // DQ IDELAY tap inc and ce signals registered to control calib_in_common // signal during read leveling in FAST_CAL mode. The calib_in_common signal // is only asserted for IDELAY tap increments not Phaser_IN tap increments // in FAST_CAL mode. For Phaser_IN tap increments the Phaser_IN counter load // inputs are used. always @(posedge clk) begin if (rst) begin idelay_ce_r1 <= #TCQ 1'b0; idelay_ce_r2 <= #TCQ 1'b0; idelay_inc_r1 <= #TCQ 1'b0; idelay_inc_r2 <= #TCQ 1'b0; end else begin idelay_ce_r1 <= #TCQ idelay_ce_int; idelay_ce_r2 <= #TCQ idelay_ce_r1; idelay_inc_r1 <= #TCQ idelay_inc_int; idelay_inc_r2 <= #TCQ idelay_inc_r1; end end //*************************************************************************** // Delay all Outputs using Phaser_Out fine taps //*************************************************************************** assign init_wrcal_complete = 1'b0; //*************************************************************************** // PRBS Generator for Read Leveling Stage 1 - read window detection and // DQS Centering //*************************************************************************** // Assign initial seed (used for 1st data word in 8-burst sequence); use alternating 1/0 pat assign prbs_seed = 64'h9966aa559966aa55; // A single PRBS generator // writes 64-bits every 4to1 fabric clock cycle and // write 32-bits every 2to1 fabric clock cycle // used for complex read leveling and complex oclkdealy calib mig_7series_v2_3_ddr_prbs_gen # ( .TCQ (TCQ), .PRBS_WIDTH (2*8*nCK_PER_CLK), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQ_WIDTH (DQ_WIDTH), .VCCO_PAT_EN (VCCO_PAT_EN), .VCCAUX_PAT_EN (VCCAUX_PAT_EN), .ISI_PAT_EN (ISI_PAT_EN), .FIXED_VICTIM (FIXED_VICTIM) ) u_ddr_prbs_gen (.prbs_ignore_first_byte (prbs_ignore_first_byte), .prbs_ignore_last_bytes (prbs_ignore_last_bytes), .clk_i (clk), .clk_en_i (prbs_gen_clk_en | prbs_gen_oclk_clk_en), .rst_i (rst), .prbs_o (prbs_out), .prbs_seed_i (prbs_seed), .phy_if_empty (phy_if_empty), .prbs_rdlvl_start (prbs_rdlvl_start), .prbs_rdlvl_done (prbs_rdlvl_done), .complex_wr_done (complex_wr_done), .victim_sel (victim_sel), .byte_cnt (victim_byte_cnt), .dbg_prbs_gen (), .reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr) ); // PRBS data slice that decides the Rise0, Fall0, Rise1, Fall1, // Rise2, Fall2, Rise3, Fall3 data generate if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4 assign prbs_o = prbs_out; /*assign prbs_rise0 = prbs_out[7:0]; assign prbs_fall0 = prbs_out[15:8]; assign prbs_rise1 = prbs_out[23:16]; assign prbs_fall1 = prbs_out[31:24]; assign prbs_rise2 = prbs_out[39:32]; assign prbs_fall2 = prbs_out[47:40]; assign prbs_rise3 = prbs_out[55:48]; assign prbs_fall3 = prbs_out[63:56]; assign prbs_o = {prbs_fall3, prbs_rise3, prbs_fall2, prbs_rise2, prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/ end else begin :gen_ck_per_clk2 assign prbs_o = prbs_out[4*DQ_WIDTH-1:0]; /*assign prbs_rise0 = prbs_out[7:0]; assign prbs_fall0 = prbs_out[15:8]; assign prbs_rise1 = prbs_out[23:16]; assign prbs_fall1 = prbs_out[31:24]; assign prbs_o = {prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/ end endgenerate //*************************************************************************** // Initialization / Master PHY state logic (overall control during memory // init, timing leveling) //*************************************************************************** mig_7series_v2_3_ddr_phy_init # ( .tCK (tCK), .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .CLK_PERIOD (CLK_PERIOD), .DRAM_TYPE (DRAM_TYPE), .PRBS_WIDTH (PRBS_WIDTH), .BANK_WIDTH (BANK_WIDTH), .CA_MIRROR (CA_MIRROR), .COL_WIDTH (COL_WIDTH), .nCS_PER_RANK (nCS_PER_RANK), .DQ_WIDTH (DQ_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .ROW_WIDTH (ROW_WIDTH), .CS_WIDTH (CS_WIDTH), .RANKS (RANKS), .CKE_WIDTH (CKE_WIDTH), .CALIB_ROW_ADD (CALIB_ROW_ADD), .CALIB_COL_ADD (CALIB_COL_ADD), .CALIB_BA_ADD (CALIB_BA_ADD), .AL (AL), .BURST_MODE (BURST_MODE), .BURST_TYPE (BURST_TYPE), .nCL (nCL), .nCWL (nCWL), .tRFC (tRFC), .REFRESH_TIMER (REFRESH_TIMER), .REFRESH_TIMER_WIDTH (REFRESH_TIMER_WIDTH), .OUTPUT_DRV (OUTPUT_DRV), .REG_CTRL (REG_CTRL), .ADDR_CMD_MODE (ADDR_CMD_MODE), .RTT_NOM (RTT_NOM), .RTT_WR (RTT_WR), .WRLVL (WRLVL), .USE_ODT_PORT (USE_ODT_PORT), .DDR2_DQSN_ENABLE(DDR2_DQSN_ENABLE), .nSLOTS (nSLOTS), .SIM_INIT_OPTION (SIM_INIT_OPTION), .SIM_CAL_OPTION (SIM_CAL_OPTION), .CKE_ODT_AUX (CKE_ODT_AUX), .PRE_REV3ES (PRE_REV3ES), .TEST_AL (TEST_AL), .FIXED_VICTIM (FIXED_VICTIM), .BYPASS_COMPLEX_OCAL(BYPASS_COMPLEX_OCAL) ) u_ddr_phy_init ( .clk (clk), .rst (rst), .prbs_o (prbs_o), .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done), .delay_incdec_done (ck_addr_cmd_delay_done), .pi_phase_locked_all (pi_phase_locked_all), .pi_phaselock_start (pi_phaselock_start), .pi_phase_locked_err (phase_locked_err), .pi_calib_done (pi_calib_done), .phy_if_empty (phy_if_empty), .phy_ctl_ready (phy_ctl_ready), .phy_ctl_full (phy_ctl_full), .phy_cmd_full (phy_cmd_full), .phy_data_full (phy_data_full), .calib_ctl_wren (calib_ctl_wren), .calib_cmd_wren (calib_cmd_wren), .calib_wrdata_en (calib_wrdata_en), .calib_seq (calib_seq), .calib_aux_out (calib_aux_out), .calib_rank_cnt (calib_rank_cnt), .calib_cas_slot (calib_cas_slot), .calib_data_offset_0 (calib_data_offset_0), .calib_data_offset_1 (calib_data_offset_1), .calib_data_offset_2 (calib_data_offset_2), .calib_cmd (calib_cmd), .calib_cke (calib_cke), .calib_odt (calib_odt), .write_calib (write_calib), .read_calib (read_calib), .wrlvl_done (wrlvl_done), .wrlvl_rank_done (wrlvl_rank_done), .wrlvl_byte_done (wrlvl_byte_done), .wrlvl_byte_redo (wrlvl_byte_redo), .wrlvl_final (wrlvl_final_mux), .wrlvl_final_if_rst (wrlvl_final_if_rst), .oclkdelay_calib_start (oclkdelay_calib_start), .oclkdelay_calib_done (oclkdelay_calib_done), .oclk_prech_req (oclk_prech_req), .oclk_calib_resume (oclk_calib_resume), .lim_wr_req (lim2init_write_request), .lim_done (lim_done), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start), .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done_w), .complex_oclk_calib_resume (complex_oclk_calib_resume), .complex_oclkdelay_calib_cnt (complex_oclkdelay_calib_cnt), .complex_sample_cnt_inc_ocal (complex_sample_cnt_inc_ocal), .complex_ocal_num_samples_inc (complex_ocal_num_samples_inc), .complex_ocal_num_samples_done_r (complex_ocal_num_samples_done_r), .complex_ocal_reset_rd_addr (complex_ocal_reset_rd_addr), .complex_ocal_ref_req (complex_ocal_ref_req), .complex_ocal_ref_done (complex_ocal_ref_done), .done_dqs_tap_inc (done_dqs_tap_inc), .wl_sm_start (wl_sm_start), .wr_lvl_start (wrlvl_start), .slot_0_present (slot_0_present), .slot_1_present (slot_1_present), .mpr_rdlvl_done (mpr_rdlvl_done), .mpr_rdlvl_start (mpr_rdlvl_start), .mpr_last_byte_done (mpr_last_byte_done), .mpr_rnk_done (mpr_rnk_done), .mpr_end_if_reset (mpr_end_if_reset), .rdlvl_stg1_done (rdlvl_stg1_done), .rdlvl_stg1_rank_done (rdlvl_stg1_rank_done), .rdlvl_stg1_start (rdlvl_stg1_start), .rdlvl_prech_req (rdlvl_prech_req), .rdlvl_last_byte_done (rdlvl_last_byte_done), .prbs_rdlvl_start (prbs_rdlvl_start), .complex_wr_done (complex_wr_done), .prbs_rdlvl_done (prbs_rdlvl_done), .prbs_last_byte_done (prbs_last_byte_done), .prbs_rdlvl_prech_req (prbs_rdlvl_prech_req), .complex_victim_inc (complex_victim_inc), .rd_victim_sel (rd_victim_sel), .complex_ocal_rd_victim_sel (complex_ocal_rd_victim_sel), .pi_stg2_prbs_rdlvl_cnt(pi_stg2_prbs_rdlvl_cnt), .victim_sel (victim_sel), .victim_byte_cnt (victim_byte_cnt), .prbs_gen_clk_en (prbs_gen_clk_en), .prbs_gen_oclk_clk_en (prbs_gen_oclk_clk_en), .complex_sample_cnt_inc(complex_sample_cnt_inc), .pi_dqs_found_start (pi_dqs_found_start), .dqsfound_retry (dqsfound_retry), .dqs_found_prech_req (dqs_found_prech_req), .pi_dqs_found_rank_done(pi_dqs_found_rank_done), .pi_dqs_found_done (pi_dqs_found_done), .detect_pi_found_dqs (detect_pi_found_dqs), .rd_data_offset_0 (rd_data_offset_0), .rd_data_offset_1 (rd_data_offset_1), .rd_data_offset_2 (rd_data_offset_2), .rd_data_offset_ranks_0(rd_data_offset_ranks_0), .rd_data_offset_ranks_1(rd_data_offset_ranks_1), .rd_data_offset_ranks_2(rd_data_offset_ranks_2), .wrcal_start (wrcal_start), .wrcal_rd_wait (wrcal_rd_wait), .wrcal_prech_req (wrcal_prech_req), .wrcal_resume (wrcal_resume_w), .wrcal_read_req (wrcal_read_req), .wrcal_act_req (wrcal_act_req), .wrcal_sanity_chk (wrcal_sanity_chk), .temp_wrcal_done (temp_wrcal_done), .wrcal_sanity_chk_done (wrcal_sanity_chk_done), .tg_timer_done (tg_timer_done), .no_rst_tg_mc (no_rst_tg_mc), .wrcal_done (wrcal_done), .prech_done (prech_done), .calib_writes (calib_writes), .init_calib_complete (calib_complete), .phy_address (phy_address), .phy_bank (phy_bank), .phy_cas_n (phy_cas_n), .phy_cs_n (phy_cs_n), .phy_ras_n (phy_ras_n), .phy_reset_n (phy_reset_n), .phy_we_n (phy_we_n), .phy_wrdata (phy_wrdata), .phy_rddata_en (phy_rddata_en), .phy_rddata_valid (phy_rddata_valid), .dbg_phy_init (dbg_phy_init), .read_pause (read_pause), .reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr), .oclkdelay_center_calib_start (oclkdelay_center_calib_start), .oclk_center_write_resume (oclk_center_write_resume), .oclkdelay_center_calib_done (oclkdelay_center_calib_done) ); //***************************************************************** // Write Calibration //***************************************************************** mig_7series_v2_3_ddr_phy_wrcal # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .CLK_PERIOD (CLK_PERIOD), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .SIM_CAL_OPTION (SIM_CAL_OPTION) ) u_ddr_phy_wrcal ( .clk (clk), .rst (rst), .wrcal_start (wrcal_start), .wrcal_rd_wait (wrcal_rd_wait), .wrcal_sanity_chk (wrcal_sanity_chk), .dqsfound_retry_done (pi_dqs_found_done), .dqsfound_retry (dqsfound_retry), .wrcal_read_req (wrcal_read_req), .wrcal_act_req (wrcal_act_req), .phy_rddata_en (phy_rddata_en), .wrcal_done (wrcal_done), .wrcal_pat_err (wrcal_pat_err), .wrcal_prech_req (wrcal_prech_req), .temp_wrcal_done (temp_wrcal_done), .wrcal_sanity_chk_done (wrcal_sanity_chk_done), .prech_done (prech_done), .rd_data (phy_rddata), .wrcal_pat_resume (wrcal_pat_resume), .po_stg2_wrcal_cnt (po_stg2_wrcal_cnt), .phy_if_reset (phy_if_reset_w), .wl_po_coarse_cnt (wl_po_coarse_cnt), .wl_po_fine_cnt (wl_po_fine_cnt), .wrlvl_byte_redo (wrlvl_byte_redo), .wrlvl_byte_done (wrlvl_byte_done), .early1_data (early1_data), .early2_data (early2_data), .idelay_ld (idelay_ld), .dbg_phy_wrcal (dbg_phy_wrcal), .dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt), .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt) ); //*************************************************************************** // Write-leveling calibration logic //*************************************************************************** generate if (WRLVL == "ON") begin: mb_wrlvl_inst mig_7series_v2_3_ddr_phy_wrlvl # ( .TCQ (TCQ), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQ_WIDTH (DQ_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .RANKS (1), .CLK_PERIOD (CLK_PERIOD), .nCK_PER_CLK (nCK_PER_CLK), .SIM_CAL_OPTION (SIM_CAL_OPTION) ) u_ddr_phy_wrlvl ( .clk (clk), .rst (rst), .phy_ctl_ready (phy_ctl_ready), .wr_level_start (wrlvl_start), .wl_sm_start (wl_sm_start), .wrlvl_byte_redo (wrlvl_byte_redo), .wrcal_cnt (po_stg2_wrcal_cnt), .early1_data (early1_data), .early2_data (early2_data), .wrlvl_final (wrlvl_final_mux), .oclkdelay_calib_cnt (oclkdelay_calib_cnt), .wrlvl_byte_done (wrlvl_byte_done), .oclkdelay_calib_done (oclkdelay_calib_done), .rd_data_rise0 (phy_rddata[DQ_WIDTH-1:0]), .dqs_po_dec_done (dqs_po_dec_done), .phy_ctl_rdy_dly (phy_ctl_rdy_dly), .wr_level_done (wrlvl_done), .wrlvl_rank_done (wrlvl_rank_done), .done_dqs_tap_inc (done_dqs_tap_inc), .dqs_po_stg2_f_incdec (dqs_po_stg2_f_incdec), .dqs_po_en_stg2_f (dqs_po_en_stg2_f), .dqs_wl_po_stg2_c_incdec (dqs_wl_po_stg2_c_incdec), .dqs_wl_po_en_stg2_c (dqs_wl_po_en_stg2_c), .po_counter_read_val (po_counter_read_val), .po_stg2_wl_cnt (po_stg2_wl_cnt), .wrlvl_err (wrlvl_err), .wl_po_coarse_cnt (wl_po_coarse_cnt), .wl_po_fine_cnt (wl_po_fine_cnt), .dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl), .dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid), .dbg_rd_data_edge_detect (dbg_rd_data_edge_detect), .dbg_dqs_count (), .dbg_wl_state (), .dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt), .dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt), .dbg_phy_wrlvl (dbg_phy_wrlvl) ); mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay # ( .TCQ (TCQ), .tCK (tCK), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .N_CTL_LANES (N_CTL_LANES), .SIM_CAL_OPTION(SIM_CAL_OPTION) ) u_ddr_phy_ck_addr_cmd_delay ( .clk (clk), .rst (rst), .cmd_delay_start (dqs_po_dec_done & pi_fine_dly_dec_done), .ctl_lane_cnt (ctl_lane_cnt), .po_stg2_f_incdec (cmd_po_stg2_f_incdec), .po_en_stg2_f (cmd_po_en_stg2_f), .po_stg2_c_incdec (cmd_po_stg2_c_incdec), .po_en_stg2_c (cmd_po_en_stg2_c), .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done) ); assign cmd_po_stg2_incdec_ddr2_c = 1'b0; assign cmd_po_en_stg2_ddr2_c = 1'b0; end else begin: mb_wrlvl_off mig_7series_v2_3_ddr_phy_wrlvl_off_delay # ( .TCQ (TCQ), .tCK (tCK), .nCK_PER_CLK (nCK_PER_CLK), .CLK_PERIOD (CLK_PERIOD), .PO_INITIAL_DLY(60), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .N_CTL_LANES (N_CTL_LANES) ) u_phy_wrlvl_off_delay ( .clk (clk), .rst (rst), .pi_fine_dly_dec_done (pi_fine_dly_dec_done), .cmd_delay_start (phy_ctl_ready), .ctl_lane_cnt (ctl_lane_cnt), .po_s2_incdec_f (cmd_po_stg2_f_incdec), .po_en_s2_f (cmd_po_en_stg2_f), .po_s2_incdec_c (cmd_po_stg2_incdec_ddr2_c), .po_en_s2_c (cmd_po_en_stg2_ddr2_c), .po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done), .po_dec_done (dqs_po_dec_done), .phy_ctl_rdy_dly (phy_ctl_rdy_dly) ); assign wrlvl_byte_done = 1'b1; assign wrlvl_rank_done = 1'b1; assign po_stg2_wl_cnt = 'h0; assign wl_po_coarse_cnt = 'h0; assign wl_po_fine_cnt = 'h0; assign dbg_tap_cnt_during_wrlvl = 'h0; assign dbg_wl_edge_detect_valid = 'h0; assign dbg_rd_data_edge_detect = 'h0; assign dbg_wrlvl_fine_tap_cnt = 'h0; assign dbg_wrlvl_coarse_tap_cnt = 'h0; assign dbg_phy_wrlvl = 'h0; assign wrlvl_done = 1'b1; assign wrlvl_err = 1'b0; assign dqs_po_stg2_f_incdec = 1'b0; assign dqs_po_en_stg2_f = 1'b0; assign dqs_wl_po_en_stg2_c = 1'b0; assign cmd_po_stg2_c_incdec = 1'b0; assign dqs_wl_po_stg2_c_incdec = 1'b0; assign cmd_po_en_stg2_c = 1'b0; end endgenerate generate if((WRLVL == "ON") && (OCAL_EN == "ON")) begin: oclk_calib localparam SAMPCNTRWIDTH = 17; localparam SAMPLES = (SIM_CAL_OPTION=="NONE") ? 2048 : 4; localparam TAPCNTRWIDTH = clogb2(TAPSPERKCLK); localparam MMCM_SAMP_WAIT = (SIM_CAL_OPTION=="NONE") ? 256 : 10; localparam OCAL_SIMPLE_SCAN_SAMPS = (SIM_CAL_OPTION=="NONE") ? 2048 : 1; localparam POC_PCT_SAMPS_SOLID = 80; localparam SCAN_PCT_SAMPS_SOLID = 95; mig_7series_v2_3_ddr_phy_oclkdelay_cal # (/*AUTOINSTPARAM*/ // Parameters .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DQ_WIDTH (DQ_WIDTH), //.DRAM_TYPE (DRAM_TYPE), .DRAM_WIDTH (DRAM_WIDTH), //.OCAL_EN (OCAL_EN), .OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS), .PCT_SAMPS_SOLID (POC_PCT_SAMPS_SOLID), .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP), .SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID), .SAMPCNTRWIDTH (SAMPCNTRWIDTH), .SAMPLES (SAMPLES), .MMCM_SAMP_WAIT (MMCM_SAMP_WAIT), .SIM_CAL_OPTION (SIM_CAL_OPTION), .TAPCNTRWIDTH (TAPCNTRWIDTH), .TAPSPERKCLK (TAPSPERKCLK), .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL) //.tCK (tCK) ) u_ddr_phy_oclkdelay_cal (/*AUTOINST*/ // Outputs .prbs_ignore_first_byte (prbs_ignore_first_byte), .prbs_ignore_last_bytes (prbs_ignore_last_bytes), .complex_oclkdelay_calib_done (complex_oclkdelay_calib_done), .dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data[16*DRAM_WIDTH-1:0]), .dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal[255:0]), .lim2init_write_request (lim2init_write_request), .lim_done (lim_done), .oclk_calib_resume (oclk_calib_resume), //.oclk_init_delay_done (oclk_init_delay_done), .oclk_prech_req (oclk_prech_req), .oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]), .oclkdelay_calib_done (oclkdelay_calib_done), .po_en_stg23 (po_en_stg23), //.po_en_stg3 (po_en_stg3), .po_stg23_incdec (po_stg23_incdec), .po_stg23_sel (po_stg23_sel), //.po_stg3_incdec (po_stg3_incdec), .psen (psen), .psincdec (psincdec), .wrlvl_final (wrlvl_final), .rd_victim_sel (complex_ocal_rd_victim_sel), .ocal_num_samples_done_r (complex_ocal_num_samples_done_r), .complex_wrlvl_final (complex_wrlvl_final), .poc_error (poc_error), // Inputs .clk (clk), .complex_oclkdelay_calib_start (complex_oclkdelay_calib_start_w), .metaQ (pd_out), //.oclk_init_delay_start (oclk_init_delay_start), .po_counter_read_val (po_counter_read_val), .oclkdelay_calib_start (oclkdelay_calib_start), .oclkdelay_init_val (oclkdelay_init_val[5:0]), .poc_sample_pd (poc_sample_pd), .phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]), .phy_rddata_en (phy_rddata_en), .prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]), .prech_done (prech_done), .psdone (psdone), .rst (rst), .wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0]), .ocal_num_samples_inc (complex_ocal_num_samples_inc), .oclkdelay_center_calib_start (oclkdelay_center_calib_start), .oclk_center_write_resume (oclk_center_write_resume), .oclkdelay_center_calib_done (oclkdelay_center_calib_done), .dbg_ocd_lim (dbg_ocd_lim)); end else begin : oclk_calib_disabled assign wrlvl_final = 'b0; assign psen = 'b0; assign psincdec = 'b0; assign po_stg23_sel = 'b0; assign po_stg23_incdec = 'b0; assign po_en_stg23 = 'b0; //assign oclk_init_delay_done = 1'b1; assign oclkdelay_calib_cnt = 'b0; assign oclk_prech_req = 'b0; assign oclk_calib_resume = 'b0; assign oclkdelay_calib_done = 1'b1; assign dbg_phy_oclkdelay_cal = 'h0; assign dbg_oclkdelay_rd_data = 'h0; end endgenerate //*************************************************************************** // Read data-offset calibration required for Phaser_In //*************************************************************************** generate if(DQSFOUND_CAL == "RIGHT") begin: dqsfind_calib_right mig_7series_v2_3_ddr_phy_dqs_found_cal # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .nCL (nCL), .AL (AL), .nCWL (nCWL), //.RANKS (RANKS), .RANKS (1), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .REG_CTRL (REG_CTRL), .SIM_CAL_OPTION (SIM_CAL_OPTION), .DRAM_TYPE (DRAM_TYPE), .NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL), .N_CTL_LANES (DQS_FOUND_N_CTL_LANES), .HIGHEST_LANE (HIGHEST_LANE), .HIGHEST_BANK (HIGHEST_BANK), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4) ) u_ddr_phy_dqs_found_cal ( .clk (clk), .rst (rst), .pi_dqs_found_start (pi_dqs_found_start), .dqsfound_retry (dqsfound_retry), .detect_pi_found_dqs (detect_pi_found_dqs), .prech_done (prech_done), .pi_dqs_found_lanes (pi_dqs_found_lanes), .pi_rst_stg1_cal (pi_rst_stg1_cal), .rd_data_offset_0 (rd_data_offset_0), .rd_data_offset_1 (rd_data_offset_1), .rd_data_offset_2 (rd_data_offset_2), .pi_dqs_found_rank_done (pi_dqs_found_rank_done), .pi_dqs_found_done (pi_dqs_found_done), .dqsfound_retry_done (dqsfound_retry_done), .dqs_found_prech_req (dqs_found_prech_req), .pi_dqs_found_err (pi_dqs_found_err), .rd_data_offset_ranks_0 (rd_data_offset_ranks_0), .rd_data_offset_ranks_1 (rd_data_offset_ranks_1), .rd_data_offset_ranks_2 (rd_data_offset_ranks_2), .rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0), .rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1), .rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2), .po_counter_read_val (po_counter_read_val), .rd_data_offset_cal_done (rd_data_offset_cal_done), .fine_adjust_done (fine_adjust_done), .fine_adjust_lane_cnt (fine_adjust_lane_cnt), .ck_po_stg2_f_indec (ck_po_stg2_f_indec), .ck_po_stg2_f_en (ck_po_stg2_f_en), .dbg_dqs_found_cal (dbg_dqs_found_cal) ); end else begin: dqsfind_calib_left mig_7series_v2_3_ddr_phy_dqs_found_cal_hr # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .nCL (nCL), .AL (AL), .nCWL (nCWL), //.RANKS (RANKS), .RANKS (1), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .REG_CTRL (REG_CTRL), .SIM_CAL_OPTION (SIM_CAL_OPTION), .DRAM_TYPE (DRAM_TYPE), .NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL), .N_CTL_LANES (DQS_FOUND_N_CTL_LANES), .HIGHEST_LANE (HIGHEST_LANE), .HIGHEST_BANK (HIGHEST_BANK), .BYTE_LANES_B0 (BYTE_LANES_B0), .BYTE_LANES_B1 (BYTE_LANES_B1), .BYTE_LANES_B2 (BYTE_LANES_B2), .BYTE_LANES_B3 (BYTE_LANES_B3), .BYTE_LANES_B4 (BYTE_LANES_B4), .DATA_CTL_B0 (DATA_CTL_B0), .DATA_CTL_B1 (DATA_CTL_B1), .DATA_CTL_B2 (DATA_CTL_B2), .DATA_CTL_B3 (DATA_CTL_B3), .DATA_CTL_B4 (DATA_CTL_B4) ) u_ddr_phy_dqs_found_cal_hr ( .clk (clk), .rst (rst), .pi_dqs_found_start (pi_dqs_found_start), .dqsfound_retry (dqsfound_retry), .detect_pi_found_dqs (detect_pi_found_dqs), .prech_done (prech_done), .pi_dqs_found_lanes (pi_dqs_found_lanes), .pi_rst_stg1_cal (pi_rst_stg1_cal), .rd_data_offset_0 (rd_data_offset_0), .rd_data_offset_1 (rd_data_offset_1), .rd_data_offset_2 (rd_data_offset_2), .pi_dqs_found_rank_done (pi_dqs_found_rank_done), .pi_dqs_found_done (pi_dqs_found_done), .dqsfound_retry_done (dqsfound_retry_done), .dqs_found_prech_req (dqs_found_prech_req), .pi_dqs_found_err (pi_dqs_found_err), .rd_data_offset_ranks_0 (rd_data_offset_ranks_0), .rd_data_offset_ranks_1 (rd_data_offset_ranks_1), .rd_data_offset_ranks_2 (rd_data_offset_ranks_2), .rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0), .rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1), .rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2), .po_counter_read_val (po_counter_read_val), .rd_data_offset_cal_done (rd_data_offset_cal_done), .fine_adjust_done (fine_adjust_done), .fine_adjust_lane_cnt (fine_adjust_lane_cnt), .ck_po_stg2_f_indec (ck_po_stg2_f_indec), .ck_po_stg2_f_en (ck_po_stg2_f_en), .dbg_dqs_found_cal (dbg_dqs_found_cal) ); end endgenerate //*************************************************************************** // Read-leveling calibration logic //*************************************************************************** mig_7series_v2_3_ddr_phy_rdlvl # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .CLK_PERIOD (CLK_PERIOD), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .RANKS (1), .PER_BIT_DESKEW (PER_BIT_DESKEW), .SIM_CAL_OPTION (SIM_CAL_OPTION), .DEBUG_PORT (DEBUG_PORT), .DRAM_TYPE (DRAM_TYPE), .OCAL_EN (OCAL_EN), .IDELAY_ADJ (IDELAY_ADJ) ) u_ddr_phy_rdlvl ( .clk (clk), .rst (rst), .mpr_rdlvl_done (mpr_rdlvl_done), .mpr_rdlvl_start (mpr_rdlvl_start), .mpr_last_byte_done (mpr_last_byte_done), .mpr_rnk_done (mpr_rnk_done), .rdlvl_stg1_start (rdlvl_stg1_start), .rdlvl_stg1_done (rdlvl_stg1_done), .rdlvl_stg1_rnk_done (rdlvl_stg1_rank_done), .rdlvl_stg1_err (rdlvl_stg1_err), .mpr_rdlvl_err (mpr_rdlvl_err), .rdlvl_err (rdlvl_err), .rdlvl_prech_req (rdlvl_prech_req), .rdlvl_last_byte_done (rdlvl_last_byte_done), .rdlvl_assrt_common (rdlvl_assrt_common), .prech_done (prech_done), .phy_if_empty (phy_if_empty), .idelaye2_init_val (idelaye2_init_val), .rd_data (phy_rddata), .pi_en_stg2_f (rdlvl_pi_stg2_f_en), .pi_stg2_f_incdec (rdlvl_pi_stg2_f_incdec), .pi_stg2_load (pi_stg2_load), .pi_stg2_reg_l (pi_stg2_reg_l), .dqs_po_dec_done (dqs_po_dec_done), .pi_counter_read_val (pi_counter_read_val), .pi_fine_dly_dec_done (pi_fine_dly_dec_done), .idelay_ce (idelay_ce_int), .idelay_inc (idelay_inc_int), .idelay_ld (idelay_ld), .wrcal_cnt (po_stg2_wrcal_cnt), .pi_stg2_rdlvl_cnt (pi_stg2_rdlvl_cnt), .dlyval_dq (dlyval_dq), .dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt), .dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt), .dbg_cpt_tap_cnt (dbg_cpt_tap_cnt), .dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt), .dbg_idel_up_all (dbg_idel_up_all), .dbg_idel_down_all (dbg_idel_down_all), .dbg_idel_up_cpt (dbg_idel_up_cpt), .dbg_idel_down_cpt (dbg_idel_down_cpt), .dbg_sel_idel_cpt (dbg_sel_idel_cpt), .dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt), .dbg_phy_rdlvl (dbg_phy_rdlvl) ); generate if((DRAM_TYPE == "DDR3") && (nCK_PER_CLK == 4) && (BYPASS_COMPLEX_RDLVL=="FALSE")) begin:ddr_phy_prbs_rdlvl_gen mig_7series_v2_3_ddr_phy_prbs_rdlvl # ( .TCQ (TCQ), .nCK_PER_CLK (nCK_PER_CLK), .DQ_WIDTH (DQ_WIDTH), .DQS_CNT_WIDTH (DQS_CNT_WIDTH), .DQS_WIDTH (DQS_WIDTH), .DRAM_WIDTH (DRAM_WIDTH), .RANKS (1), .SIM_CAL_OPTION (SIM_CAL_OPTION), .PRBS_WIDTH (PRBS_WIDTH), .FIXED_VICTIM (FIXED_VICTIM), .FINE_PER_BIT (FINE_PER_BIT), .CENTER_COMP_MODE (CENTER_COMP_MODE), .PI_VAL_ADJ (PI_VAL_ADJ) ) u_ddr_phy_prbs_rdlvl ( .clk (clk), .rst (rst), .prbs_rdlvl_start (prbs_rdlvl_start), .prbs_rdlvl_done (prbs_rdlvl_done), .prbs_last_byte_done (prbs_last_byte_done), .prbs_rdlvl_prech_req (prbs_rdlvl_prech_req), .complex_sample_cnt_inc (complex_sample_cnt_inc), .prech_done (prech_done), .phy_if_empty (phy_if_empty), .rd_data (phy_rddata), .compare_data (prbs_o), .pi_counter_read_val (pi_counter_read_val), .pi_en_stg2_f (prbs_pi_stg2_f_en), .pi_stg2_f_incdec (prbs_pi_stg2_f_incdec), .dbg_prbs_rdlvl (dbg_prbs_rdlvl), .pi_stg2_prbs_rdlvl_cnt (pi_stg2_prbs_rdlvl_cnt), .prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r), .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps), .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps), .rd_victim_sel (rd_victim_sel), .complex_victim_inc (complex_victim_inc), .reset_rd_addr (reset_rd_addr), .read_pause (read_pause), .fine_delay_incdec_pb (fine_delay_incdec_pb), .fine_delay_sel (fine_delay_sel) ); end else begin:ddr_phy_prbs_rdlvl_off assign prbs_rdlvl_done = rdlvl_stg1_done ; //assign prbs_last_byte_done = rdlvl_stg1_rank_done ; assign prbs_last_byte_done = rdlvl_stg1_done; assign read_pause = 1'b0; assign reset_rd_addr = 1'b0; assign prbs_rdlvl_prech_req = 1'b0 ; assign prbs_pi_stg2_f_en = 1'b0 ; assign prbs_pi_stg2_f_incdec = 1'b0 ; assign pi_stg2_prbs_rdlvl_cnt = 'b0 ; assign dbg_prbs_rdlvl = 'h0 ; assign prbs_final_dqs_tap_cnt_r = {(6*DQS_WIDTH*RANKS){1'b0}}; assign dbg_prbs_first_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}}; assign dbg_prbs_second_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}}; end endgenerate //*************************************************************************** // Temperature induced PI tap adjustment logic //*************************************************************************** mig_7series_v2_3_ddr_phy_tempmon # ( .TCQ (TCQ) ) ddr_phy_tempmon_0 ( .rst (rst), .clk (clk), .calib_complete (calib_complete), .tempmon_pi_f_inc (tempmon_pi_f_inc), .tempmon_pi_f_dec (tempmon_pi_f_dec), .tempmon_sel_pi_incdec (tempmon_sel_pi_incdec), .device_temp (device_temp), .tempmon_sample_en (tempmon_sample_en) ); endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: iodelay_ctrl.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ // \ \ / \ Date Created: Wed Aug 16 2006 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // This module instantiates the IDELAYCTRL primitive, which continously // calibrates the IODELAY elements in the region to account for varying // environmental conditions. A 200MHz or 300MHz reference clock (depending // on the desired IODELAY tap resolution) must be supplied //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ **$Date: 2011/06/02 08:34:56 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_iodelay_ctrl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter IODELAY_GRP0 = "IODELAY_MIG0", // May be assigned unique name when // multiple IP cores used in design parameter IODELAY_GRP1 = "IODELAY_MIG1", // May be assigned unique name when // multiple IP cores used in design parameter REFCLK_TYPE = "DIFFERENTIAL", // Reference clock type // "DIFFERENTIAL","SINGLE_ENDED" // NO_BUFFER, USE_SYSTEM_CLOCK parameter SYSCLK_TYPE = "DIFFERENTIAL", // input clock type // DIFFERENTIAL, SINGLE_ENDED, // NO_BUFFER parameter SYS_RST_PORT = "FALSE", // "TRUE" - if pin is selected for sys_rst // and IBUF will be instantiated. // "FALSE" - if pin is not selected for sys_rst parameter RST_ACT_LOW = 1, // Reset input polarity // (0 = active high, 1 = active low) parameter DIFF_TERM_REFCLK = "TRUE", // Differential Termination parameter FPGA_SPEED_GRADE = 1, // FPGA speed grade parameter REF_CLK_MMCM_IODELAY_CTRL = "FALSE" ) ( input clk_ref_p, input clk_ref_n, input clk_ref_i, input sys_rst, output [1:0] clk_ref, output sys_rst_o, output [1:0] iodelay_ctrl_rdy ); // # of clock cycles to delay deassertion of reset. Needs to be a fairly // high number not so much for metastability protection, but to give time // for reset (i.e. stable clock cycles) to propagate through all state // machines and to all control signals (i.e. not all control signals have // resets, instead they rely on base state logic being reset, and the effect // of that reset propagating through the logic). Need this because we may not // be getting stable clock cycles while reset asserted (i.e. since reset // depends on DCM lock status) // COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger # localparam RST_SYNC_NUM = 15; // localparam RST_SYNC_NUM = 25; wire clk_ref_ibufg; wire clk_ref_mmcm_300; wire clk_ref_mmcm_400; wire mmcm_clkfbout; wire mmcm_Locked; wire [1:0] rst_ref; reg [RST_SYNC_NUM-1:0] rst_ref_sync_r [1:0] /* synthesis syn_maxfan = 10 */; wire rst_tmp_idelay; wire sys_rst_act_hi; //*************************************************************************** // If the pin is selected for sys_rst in GUI, IBUF will be instantiated. // If the pin is not selected in GUI, sys_rst signal is expected to be // driven internally. generate if (SYS_RST_PORT == "TRUE") IBUF u_sys_rst_ibuf ( .I (sys_rst), .O (sys_rst_o) ); else assign sys_rst_o = sys_rst; endgenerate // Possible inversion of system reset as appropriate assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_o: sys_rst_o; //*************************************************************************** // 1) Input buffer for IDELAYCTRL reference clock - handle either a // differential or single-ended input. Global clock buffer is used to // drive the rest of FPGA logic. // 2) For NO_BUFFER option, Reference clock will be driven from internal // clock i.e., clock is driven from fabric. Input buffers and Global // clock buffers will not be instaitaed. // 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used // as the input reference clock. Global clock buffer is used to drive // the rest of FPGA logic. //*************************************************************************** generate if (REFCLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref IBUFGDS # ( .DIFF_TERM (DIFF_TERM_REFCLK), .IBUF_LOW_PWR ("FALSE") ) u_ibufg_clk_ref ( .I (clk_ref_p), .IB (clk_ref_n), .O (clk_ref_ibufg) ); end else if (REFCLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref IBUFG # ( .IBUF_LOW_PWR ("FALSE") ) u_ibufg_clk_ref ( .I (clk_ref_i), .O (clk_ref_ibufg) ); end else if ((REFCLK_TYPE == "NO_BUFFER") || (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE == "NO_BUFFER")) begin : clk_ref_noibuf_nobuf assign clk_ref_ibufg = clk_ref_i; end else if (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER") begin : clk_ref_noibuf assign clk_ref_ibufg = clk_ref_i; end endgenerate // reference clock 300MHz and 400MHz generation with MMCM generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: clk_ref_mmcm_gen MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("INTERNAL"), .STARTUP_WAIT ("FALSE"), .DIVCLK_DIVIDE (1), .CLKFBOUT_MULT_F (6), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (4), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), .CLKOUT1_DIVIDE (3), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (5), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (mmcm_clkfbout), .CLKFBOUTB (), .CLKOUT0 (clk_ref_mmcm_300), .CLKOUT0B (), .CLKOUT1 (clk_ref_mmcm_400), .CLKOUT1B (), .CLKOUT2 (), .CLKOUT2B (), .CLKOUT3 (), .CLKOUT3B (), .CLKOUT4 (), .CLKOUT5 (), .CLKOUT6 (), // Input clock control .CLKFBIN (mmcm_clkfbout), .CLKIN1 (clk_ref_ibufg), .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (1'b0), .PSEN (1'b0), .PSINCDEC (1'b0), .PSDONE (), // Other control and status signals .LOCKED (mmcm_Locked), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (sys_rst_act_hi)); end endgenerate generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin : clk_ref_300_400_en if(FPGA_SPEED_GRADE == 1) begin: clk_ref_300 BUFG u_bufg_clk_ref_300 ( .O (clk_ref[1]), .I (clk_ref_mmcm_300) ); end else if (FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) begin: clk_ref_400 BUFG u_bufg_clk_ref_400 ( .O (clk_ref[1]), .I (clk_ref_mmcm_400) ); end end endgenerate generate if ((REFCLK_TYPE == "DIFFERENTIAL") || (REFCLK_TYPE == "SINGLE_ENDED") || (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER")) begin: clk_ref_200 BUFG u_bufg_clk_ref ( .O (clk_ref[0]), .I (clk_ref_ibufg) ); end else begin: clk_ref_200_no_buffer assign clk_ref[0] = clk_ref_i; end endgenerate //***************************************************************** // IDELAYCTRL reset // This assumes an external clock signal driving the IDELAYCTRL // blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL // lock signal will need to be incorporated in this. //***************************************************************** // Add PLL lock if PLL drives IDELAYCTRL in user design assign rst_tmp_idelay = sys_rst_act_hi; generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: rst_ref_gen_1 always @(posedge clk_ref[1] or posedge rst_tmp_idelay) if (rst_tmp_idelay) rst_ref_sync_r[1] <= #TCQ {RST_SYNC_NUM{1'b1}}; else rst_ref_sync_r[1] <= #TCQ rst_ref_sync_r[1] << 1; assign rst_ref[1] = rst_ref_sync_r[1][RST_SYNC_NUM-1]; end endgenerate always @(posedge clk_ref[0] or posedge rst_tmp_idelay) if (rst_tmp_idelay) rst_ref_sync_r[0] <= #TCQ {RST_SYNC_NUM{1'b1}}; else rst_ref_sync_r[0] <= #TCQ rst_ref_sync_r[0] << 1; assign rst_ref[0] = rst_ref_sync_r[0][RST_SYNC_NUM-1]; //***************************************************************** generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: idelayctrl_gen_1 (* IODELAY_GROUP = IODELAY_GRP1 *) IDELAYCTRL u_idelayctrl_300_400 ( .RDY (iodelay_ctrl_rdy[1]), .REFCLK (clk_ref[1]), .RST (rst_ref[1]) ); end endgenerate (* IODELAY_GROUP = IODELAY_GRP0 *) IDELAYCTRL u_idelayctrl_200 ( .RDY (iodelay_ctrl_rdy[0]), .REFCLK (clk_ref[0]), .RST (rst_ref[0]) ); endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: iodelay_ctrl.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ // \ \ / \ Date Created: Wed Aug 16 2006 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // This module instantiates the IDELAYCTRL primitive, which continously // calibrates the IODELAY elements in the region to account for varying // environmental conditions. A 200MHz or 300MHz reference clock (depending // on the desired IODELAY tap resolution) must be supplied //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ **$Date: 2011/06/02 08:34:56 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_iodelay_ctrl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter IODELAY_GRP0 = "IODELAY_MIG0", // May be assigned unique name when // multiple IP cores used in design parameter IODELAY_GRP1 = "IODELAY_MIG1", // May be assigned unique name when // multiple IP cores used in design parameter REFCLK_TYPE = "DIFFERENTIAL", // Reference clock type // "DIFFERENTIAL","SINGLE_ENDED" // NO_BUFFER, USE_SYSTEM_CLOCK parameter SYSCLK_TYPE = "DIFFERENTIAL", // input clock type // DIFFERENTIAL, SINGLE_ENDED, // NO_BUFFER parameter SYS_RST_PORT = "FALSE", // "TRUE" - if pin is selected for sys_rst // and IBUF will be instantiated. // "FALSE" - if pin is not selected for sys_rst parameter RST_ACT_LOW = 1, // Reset input polarity // (0 = active high, 1 = active low) parameter DIFF_TERM_REFCLK = "TRUE", // Differential Termination parameter FPGA_SPEED_GRADE = 1, // FPGA speed grade parameter REF_CLK_MMCM_IODELAY_CTRL = "FALSE" ) ( input clk_ref_p, input clk_ref_n, input clk_ref_i, input sys_rst, output [1:0] clk_ref, output sys_rst_o, output [1:0] iodelay_ctrl_rdy ); // # of clock cycles to delay deassertion of reset. Needs to be a fairly // high number not so much for metastability protection, but to give time // for reset (i.e. stable clock cycles) to propagate through all state // machines and to all control signals (i.e. not all control signals have // resets, instead they rely on base state logic being reset, and the effect // of that reset propagating through the logic). Need this because we may not // be getting stable clock cycles while reset asserted (i.e. since reset // depends on DCM lock status) // COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger # localparam RST_SYNC_NUM = 15; // localparam RST_SYNC_NUM = 25; wire clk_ref_ibufg; wire clk_ref_mmcm_300; wire clk_ref_mmcm_400; wire mmcm_clkfbout; wire mmcm_Locked; wire [1:0] rst_ref; reg [RST_SYNC_NUM-1:0] rst_ref_sync_r [1:0] /* synthesis syn_maxfan = 10 */; wire rst_tmp_idelay; wire sys_rst_act_hi; //*************************************************************************** // If the pin is selected for sys_rst in GUI, IBUF will be instantiated. // If the pin is not selected in GUI, sys_rst signal is expected to be // driven internally. generate if (SYS_RST_PORT == "TRUE") IBUF u_sys_rst_ibuf ( .I (sys_rst), .O (sys_rst_o) ); else assign sys_rst_o = sys_rst; endgenerate // Possible inversion of system reset as appropriate assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_o: sys_rst_o; //*************************************************************************** // 1) Input buffer for IDELAYCTRL reference clock - handle either a // differential or single-ended input. Global clock buffer is used to // drive the rest of FPGA logic. // 2) For NO_BUFFER option, Reference clock will be driven from internal // clock i.e., clock is driven from fabric. Input buffers and Global // clock buffers will not be instaitaed. // 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used // as the input reference clock. Global clock buffer is used to drive // the rest of FPGA logic. //*************************************************************************** generate if (REFCLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref IBUFGDS # ( .DIFF_TERM (DIFF_TERM_REFCLK), .IBUF_LOW_PWR ("FALSE") ) u_ibufg_clk_ref ( .I (clk_ref_p), .IB (clk_ref_n), .O (clk_ref_ibufg) ); end else if (REFCLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref IBUFG # ( .IBUF_LOW_PWR ("FALSE") ) u_ibufg_clk_ref ( .I (clk_ref_i), .O (clk_ref_ibufg) ); end else if ((REFCLK_TYPE == "NO_BUFFER") || (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE == "NO_BUFFER")) begin : clk_ref_noibuf_nobuf assign clk_ref_ibufg = clk_ref_i; end else if (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER") begin : clk_ref_noibuf assign clk_ref_ibufg = clk_ref_i; end endgenerate // reference clock 300MHz and 400MHz generation with MMCM generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: clk_ref_mmcm_gen MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("INTERNAL"), .STARTUP_WAIT ("FALSE"), .DIVCLK_DIVIDE (1), .CLKFBOUT_MULT_F (6), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (4), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), .CLKOUT1_DIVIDE (3), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (5), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (mmcm_clkfbout), .CLKFBOUTB (), .CLKOUT0 (clk_ref_mmcm_300), .CLKOUT0B (), .CLKOUT1 (clk_ref_mmcm_400), .CLKOUT1B (), .CLKOUT2 (), .CLKOUT2B (), .CLKOUT3 (), .CLKOUT3B (), .CLKOUT4 (), .CLKOUT5 (), .CLKOUT6 (), // Input clock control .CLKFBIN (mmcm_clkfbout), .CLKIN1 (clk_ref_ibufg), .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (1'b0), .PSEN (1'b0), .PSINCDEC (1'b0), .PSDONE (), // Other control and status signals .LOCKED (mmcm_Locked), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (sys_rst_act_hi)); end endgenerate generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin : clk_ref_300_400_en if(FPGA_SPEED_GRADE == 1) begin: clk_ref_300 BUFG u_bufg_clk_ref_300 ( .O (clk_ref[1]), .I (clk_ref_mmcm_300) ); end else if (FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) begin: clk_ref_400 BUFG u_bufg_clk_ref_400 ( .O (clk_ref[1]), .I (clk_ref_mmcm_400) ); end end endgenerate generate if ((REFCLK_TYPE == "DIFFERENTIAL") || (REFCLK_TYPE == "SINGLE_ENDED") || (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER")) begin: clk_ref_200 BUFG u_bufg_clk_ref ( .O (clk_ref[0]), .I (clk_ref_ibufg) ); end else begin: clk_ref_200_no_buffer assign clk_ref[0] = clk_ref_i; end endgenerate //***************************************************************** // IDELAYCTRL reset // This assumes an external clock signal driving the IDELAYCTRL // blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL // lock signal will need to be incorporated in this. //***************************************************************** // Add PLL lock if PLL drives IDELAYCTRL in user design assign rst_tmp_idelay = sys_rst_act_hi; generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: rst_ref_gen_1 always @(posedge clk_ref[1] or posedge rst_tmp_idelay) if (rst_tmp_idelay) rst_ref_sync_r[1] <= #TCQ {RST_SYNC_NUM{1'b1}}; else rst_ref_sync_r[1] <= #TCQ rst_ref_sync_r[1] << 1; assign rst_ref[1] = rst_ref_sync_r[1][RST_SYNC_NUM-1]; end endgenerate always @(posedge clk_ref[0] or posedge rst_tmp_idelay) if (rst_tmp_idelay) rst_ref_sync_r[0] <= #TCQ {RST_SYNC_NUM{1'b1}}; else rst_ref_sync_r[0] <= #TCQ rst_ref_sync_r[0] << 1; assign rst_ref[0] = rst_ref_sync_r[0][RST_SYNC_NUM-1]; //***************************************************************** generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: idelayctrl_gen_1 (* IODELAY_GROUP = IODELAY_GRP1 *) IDELAYCTRL u_idelayctrl_300_400 ( .RDY (iodelay_ctrl_rdy[1]), .REFCLK (clk_ref[1]), .RST (rst_ref[1]) ); end endgenerate (* IODELAY_GROUP = IODELAY_GRP0 *) IDELAYCTRL u_idelayctrl_200 ( .RDY (iodelay_ctrl_rdy[0]), .REFCLK (clk_ref[0]), .RST (rst_ref[0]) ); endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: iodelay_ctrl.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ // \ \ / \ Date Created: Wed Aug 16 2006 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // This module instantiates the IDELAYCTRL primitive, which continously // calibrates the IODELAY elements in the region to account for varying // environmental conditions. A 200MHz or 300MHz reference clock (depending // on the desired IODELAY tap resolution) must be supplied //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ **$Date: 2011/06/02 08:34:56 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_iodelay_ctrl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter IODELAY_GRP0 = "IODELAY_MIG0", // May be assigned unique name when // multiple IP cores used in design parameter IODELAY_GRP1 = "IODELAY_MIG1", // May be assigned unique name when // multiple IP cores used in design parameter REFCLK_TYPE = "DIFFERENTIAL", // Reference clock type // "DIFFERENTIAL","SINGLE_ENDED" // NO_BUFFER, USE_SYSTEM_CLOCK parameter SYSCLK_TYPE = "DIFFERENTIAL", // input clock type // DIFFERENTIAL, SINGLE_ENDED, // NO_BUFFER parameter SYS_RST_PORT = "FALSE", // "TRUE" - if pin is selected for sys_rst // and IBUF will be instantiated. // "FALSE" - if pin is not selected for sys_rst parameter RST_ACT_LOW = 1, // Reset input polarity // (0 = active high, 1 = active low) parameter DIFF_TERM_REFCLK = "TRUE", // Differential Termination parameter FPGA_SPEED_GRADE = 1, // FPGA speed grade parameter REF_CLK_MMCM_IODELAY_CTRL = "FALSE" ) ( input clk_ref_p, input clk_ref_n, input clk_ref_i, input sys_rst, output [1:0] clk_ref, output sys_rst_o, output [1:0] iodelay_ctrl_rdy ); // # of clock cycles to delay deassertion of reset. Needs to be a fairly // high number not so much for metastability protection, but to give time // for reset (i.e. stable clock cycles) to propagate through all state // machines and to all control signals (i.e. not all control signals have // resets, instead they rely on base state logic being reset, and the effect // of that reset propagating through the logic). Need this because we may not // be getting stable clock cycles while reset asserted (i.e. since reset // depends on DCM lock status) // COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger # localparam RST_SYNC_NUM = 15; // localparam RST_SYNC_NUM = 25; wire clk_ref_ibufg; wire clk_ref_mmcm_300; wire clk_ref_mmcm_400; wire mmcm_clkfbout; wire mmcm_Locked; wire [1:0] rst_ref; reg [RST_SYNC_NUM-1:0] rst_ref_sync_r [1:0] /* synthesis syn_maxfan = 10 */; wire rst_tmp_idelay; wire sys_rst_act_hi; //*************************************************************************** // If the pin is selected for sys_rst in GUI, IBUF will be instantiated. // If the pin is not selected in GUI, sys_rst signal is expected to be // driven internally. generate if (SYS_RST_PORT == "TRUE") IBUF u_sys_rst_ibuf ( .I (sys_rst), .O (sys_rst_o) ); else assign sys_rst_o = sys_rst; endgenerate // Possible inversion of system reset as appropriate assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_o: sys_rst_o; //*************************************************************************** // 1) Input buffer for IDELAYCTRL reference clock - handle either a // differential or single-ended input. Global clock buffer is used to // drive the rest of FPGA logic. // 2) For NO_BUFFER option, Reference clock will be driven from internal // clock i.e., clock is driven from fabric. Input buffers and Global // clock buffers will not be instaitaed. // 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used // as the input reference clock. Global clock buffer is used to drive // the rest of FPGA logic. //*************************************************************************** generate if (REFCLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref IBUFGDS # ( .DIFF_TERM (DIFF_TERM_REFCLK), .IBUF_LOW_PWR ("FALSE") ) u_ibufg_clk_ref ( .I (clk_ref_p), .IB (clk_ref_n), .O (clk_ref_ibufg) ); end else if (REFCLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref IBUFG # ( .IBUF_LOW_PWR ("FALSE") ) u_ibufg_clk_ref ( .I (clk_ref_i), .O (clk_ref_ibufg) ); end else if ((REFCLK_TYPE == "NO_BUFFER") || (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE == "NO_BUFFER")) begin : clk_ref_noibuf_nobuf assign clk_ref_ibufg = clk_ref_i; end else if (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER") begin : clk_ref_noibuf assign clk_ref_ibufg = clk_ref_i; end endgenerate // reference clock 300MHz and 400MHz generation with MMCM generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: clk_ref_mmcm_gen MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("INTERNAL"), .STARTUP_WAIT ("FALSE"), .DIVCLK_DIVIDE (1), .CLKFBOUT_MULT_F (6), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (4), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), .CLKOUT1_DIVIDE (3), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (5), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (mmcm_clkfbout), .CLKFBOUTB (), .CLKOUT0 (clk_ref_mmcm_300), .CLKOUT0B (), .CLKOUT1 (clk_ref_mmcm_400), .CLKOUT1B (), .CLKOUT2 (), .CLKOUT2B (), .CLKOUT3 (), .CLKOUT3B (), .CLKOUT4 (), .CLKOUT5 (), .CLKOUT6 (), // Input clock control .CLKFBIN (mmcm_clkfbout), .CLKIN1 (clk_ref_ibufg), .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (1'b0), .PSEN (1'b0), .PSINCDEC (1'b0), .PSDONE (), // Other control and status signals .LOCKED (mmcm_Locked), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (sys_rst_act_hi)); end endgenerate generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin : clk_ref_300_400_en if(FPGA_SPEED_GRADE == 1) begin: clk_ref_300 BUFG u_bufg_clk_ref_300 ( .O (clk_ref[1]), .I (clk_ref_mmcm_300) ); end else if (FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) begin: clk_ref_400 BUFG u_bufg_clk_ref_400 ( .O (clk_ref[1]), .I (clk_ref_mmcm_400) ); end end endgenerate generate if ((REFCLK_TYPE == "DIFFERENTIAL") || (REFCLK_TYPE == "SINGLE_ENDED") || (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER")) begin: clk_ref_200 BUFG u_bufg_clk_ref ( .O (clk_ref[0]), .I (clk_ref_ibufg) ); end else begin: clk_ref_200_no_buffer assign clk_ref[0] = clk_ref_i; end endgenerate //***************************************************************** // IDELAYCTRL reset // This assumes an external clock signal driving the IDELAYCTRL // blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL // lock signal will need to be incorporated in this. //***************************************************************** // Add PLL lock if PLL drives IDELAYCTRL in user design assign rst_tmp_idelay = sys_rst_act_hi; generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: rst_ref_gen_1 always @(posedge clk_ref[1] or posedge rst_tmp_idelay) if (rst_tmp_idelay) rst_ref_sync_r[1] <= #TCQ {RST_SYNC_NUM{1'b1}}; else rst_ref_sync_r[1] <= #TCQ rst_ref_sync_r[1] << 1; assign rst_ref[1] = rst_ref_sync_r[1][RST_SYNC_NUM-1]; end endgenerate always @(posedge clk_ref[0] or posedge rst_tmp_idelay) if (rst_tmp_idelay) rst_ref_sync_r[0] <= #TCQ {RST_SYNC_NUM{1'b1}}; else rst_ref_sync_r[0] <= #TCQ rst_ref_sync_r[0] << 1; assign rst_ref[0] = rst_ref_sync_r[0][RST_SYNC_NUM-1]; //***************************************************************** generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: idelayctrl_gen_1 (* IODELAY_GROUP = IODELAY_GRP1 *) IDELAYCTRL u_idelayctrl_300_400 ( .RDY (iodelay_ctrl_rdy[1]), .REFCLK (clk_ref[1]), .RST (rst_ref[1]) ); end endgenerate (* IODELAY_GROUP = IODELAY_GRP0 *) IDELAYCTRL u_idelayctrl_200 ( .RDY (iodelay_ctrl_rdy[0]), .REFCLK (clk_ref[0]), .RST (rst_ref[0]) ); endmodule

//***************************************************************************** // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // //***************************************************************************** // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version: %version // \ \ Application: MIG // / / Filename: iodelay_ctrl.v // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ // \ \ / \ Date Created: Wed Aug 16 2006 // \___\/\___\ // //Device: 7 Series //Design Name: DDR3 SDRAM //Purpose: // This module instantiates the IDELAYCTRL primitive, which continously // calibrates the IODELAY elements in the region to account for varying // environmental conditions. A 200MHz or 300MHz reference clock (depending // on the desired IODELAY tap resolution) must be supplied //Reference: //Revision History: //***************************************************************************** /****************************************************************************** **$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $ **$Date: 2011/06/02 08:34:56 $ **$Author: mishra $ **$Revision: 1.1 $ **$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $ ******************************************************************************/ `timescale 1ps/1ps module mig_7series_v2_3_iodelay_ctrl # ( parameter TCQ = 100, // clk->out delay (sim only) parameter IODELAY_GRP0 = "IODELAY_MIG0", // May be assigned unique name when // multiple IP cores used in design parameter IODELAY_GRP1 = "IODELAY_MIG1", // May be assigned unique name when // multiple IP cores used in design parameter REFCLK_TYPE = "DIFFERENTIAL", // Reference clock type // "DIFFERENTIAL","SINGLE_ENDED" // NO_BUFFER, USE_SYSTEM_CLOCK parameter SYSCLK_TYPE = "DIFFERENTIAL", // input clock type // DIFFERENTIAL, SINGLE_ENDED, // NO_BUFFER parameter SYS_RST_PORT = "FALSE", // "TRUE" - if pin is selected for sys_rst // and IBUF will be instantiated. // "FALSE" - if pin is not selected for sys_rst parameter RST_ACT_LOW = 1, // Reset input polarity // (0 = active high, 1 = active low) parameter DIFF_TERM_REFCLK = "TRUE", // Differential Termination parameter FPGA_SPEED_GRADE = 1, // FPGA speed grade parameter REF_CLK_MMCM_IODELAY_CTRL = "FALSE" ) ( input clk_ref_p, input clk_ref_n, input clk_ref_i, input sys_rst, output [1:0] clk_ref, output sys_rst_o, output [1:0] iodelay_ctrl_rdy ); // # of clock cycles to delay deassertion of reset. Needs to be a fairly // high number not so much for metastability protection, but to give time // for reset (i.e. stable clock cycles) to propagate through all state // machines and to all control signals (i.e. not all control signals have // resets, instead they rely on base state logic being reset, and the effect // of that reset propagating through the logic). Need this because we may not // be getting stable clock cycles while reset asserted (i.e. since reset // depends on DCM lock status) // COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger # localparam RST_SYNC_NUM = 15; // localparam RST_SYNC_NUM = 25; wire clk_ref_ibufg; wire clk_ref_mmcm_300; wire clk_ref_mmcm_400; wire mmcm_clkfbout; wire mmcm_Locked; wire [1:0] rst_ref; reg [RST_SYNC_NUM-1:0] rst_ref_sync_r [1:0] /* synthesis syn_maxfan = 10 */; wire rst_tmp_idelay; wire sys_rst_act_hi; //*************************************************************************** // If the pin is selected for sys_rst in GUI, IBUF will be instantiated. // If the pin is not selected in GUI, sys_rst signal is expected to be // driven internally. generate if (SYS_RST_PORT == "TRUE") IBUF u_sys_rst_ibuf ( .I (sys_rst), .O (sys_rst_o) ); else assign sys_rst_o = sys_rst; endgenerate // Possible inversion of system reset as appropriate assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_o: sys_rst_o; //*************************************************************************** // 1) Input buffer for IDELAYCTRL reference clock - handle either a // differential or single-ended input. Global clock buffer is used to // drive the rest of FPGA logic. // 2) For NO_BUFFER option, Reference clock will be driven from internal // clock i.e., clock is driven from fabric. Input buffers and Global // clock buffers will not be instaitaed. // 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used // as the input reference clock. Global clock buffer is used to drive // the rest of FPGA logic. //*************************************************************************** generate if (REFCLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref IBUFGDS # ( .DIFF_TERM (DIFF_TERM_REFCLK), .IBUF_LOW_PWR ("FALSE") ) u_ibufg_clk_ref ( .I (clk_ref_p), .IB (clk_ref_n), .O (clk_ref_ibufg) ); end else if (REFCLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref IBUFG # ( .IBUF_LOW_PWR ("FALSE") ) u_ibufg_clk_ref ( .I (clk_ref_i), .O (clk_ref_ibufg) ); end else if ((REFCLK_TYPE == "NO_BUFFER") || (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE == "NO_BUFFER")) begin : clk_ref_noibuf_nobuf assign clk_ref_ibufg = clk_ref_i; end else if (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER") begin : clk_ref_noibuf assign clk_ref_ibufg = clk_ref_i; end endgenerate // reference clock 300MHz and 400MHz generation with MMCM generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: clk_ref_mmcm_gen MMCME2_ADV #(.BANDWIDTH ("HIGH"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("INTERNAL"), .STARTUP_WAIT ("FALSE"), .DIVCLK_DIVIDE (1), .CLKFBOUT_MULT_F (6), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (4), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), .CLKOUT1_DIVIDE (3), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (5), .REF_JITTER1 (0.000)) mmcm_i // Output clocks (.CLKFBOUT (mmcm_clkfbout), .CLKFBOUTB (), .CLKOUT0 (clk_ref_mmcm_300), .CLKOUT0B (), .CLKOUT1 (clk_ref_mmcm_400), .CLKOUT1B (), .CLKOUT2 (), .CLKOUT2B (), .CLKOUT3 (), .CLKOUT3B (), .CLKOUT4 (), .CLKOUT5 (), .CLKOUT6 (), // Input clock control .CLKFBIN (mmcm_clkfbout), .CLKIN1 (clk_ref_ibufg), .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (), .DRDY (), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (1'b0), .PSEN (1'b0), .PSINCDEC (1'b0), .PSDONE (), // Other control and status signals .LOCKED (mmcm_Locked), .CLKINSTOPPED (), .CLKFBSTOPPED (), .PWRDWN (1'b0), .RST (sys_rst_act_hi)); end endgenerate generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin : clk_ref_300_400_en if(FPGA_SPEED_GRADE == 1) begin: clk_ref_300 BUFG u_bufg_clk_ref_300 ( .O (clk_ref[1]), .I (clk_ref_mmcm_300) ); end else if (FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) begin: clk_ref_400 BUFG u_bufg_clk_ref_400 ( .O (clk_ref[1]), .I (clk_ref_mmcm_400) ); end end endgenerate generate if ((REFCLK_TYPE == "DIFFERENTIAL") || (REFCLK_TYPE == "SINGLE_ENDED") || (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER")) begin: clk_ref_200 BUFG u_bufg_clk_ref ( .O (clk_ref[0]), .I (clk_ref_ibufg) ); end else begin: clk_ref_200_no_buffer assign clk_ref[0] = clk_ref_i; end endgenerate //***************************************************************** // IDELAYCTRL reset // This assumes an external clock signal driving the IDELAYCTRL // blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL // lock signal will need to be incorporated in this. //***************************************************************** // Add PLL lock if PLL drives IDELAYCTRL in user design assign rst_tmp_idelay = sys_rst_act_hi; generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: rst_ref_gen_1 always @(posedge clk_ref[1] or posedge rst_tmp_idelay) if (rst_tmp_idelay) rst_ref_sync_r[1] <= #TCQ {RST_SYNC_NUM{1'b1}}; else rst_ref_sync_r[1] <= #TCQ rst_ref_sync_r[1] << 1; assign rst_ref[1] = rst_ref_sync_r[1][RST_SYNC_NUM-1]; end endgenerate always @(posedge clk_ref[0] or posedge rst_tmp_idelay) if (rst_tmp_idelay) rst_ref_sync_r[0] <= #TCQ {RST_SYNC_NUM{1'b1}}; else rst_ref_sync_r[0] <= #TCQ rst_ref_sync_r[0] << 1; assign rst_ref[0] = rst_ref_sync_r[0][RST_SYNC_NUM-1]; //***************************************************************** generate if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: idelayctrl_gen_1 (* IODELAY_GROUP = IODELAY_GRP1 *) IDELAYCTRL u_idelayctrl_300_400 ( .RDY (iodelay_ctrl_rdy[1]), .REFCLK (clk_ref[1]), .RST (rst_ref[1]) ); end endgenerate (* IODELAY_GROUP = IODELAY_GRP0 *) IDELAYCTRL u_idelayctrl_200 ( .RDY (iodelay_ctrl_rdy[0]), .REFCLK (clk_ref[0]), .RST (rst_ref[0]) ); endmodule