Datasets:

mamamiya405

/

verilog

like 0

module conmutacion ( input [3:0] centenas, input [3:0] decenas, input [3:0] unidades, input C, input De, input U, input CLKOUTseg, output reg [1:0] mostrar, output reg [3:0] digito ); reg logic0; reg [1:0] titileo; initial begin titileo = 0; end always@(posedge CLKOUTseg) begin if(C && De && U) begin /*if(titileo == 3) begin titileo <= 1; end*/ titileo <= titileo + 1; end else begin if(De && U) begin /*if(titileo == 1) begin titileo <= 1; end*/ titileo <= titileo + 1; end else begin if(U) begin titileo <= 1; end else begin titileo <= 0; end end end end always@(posedge CLKOUTseg) begin case(titileo) 2'b00: begin mostrar = 2'b01; digito = 0; end 2'b01: begin mostrar = 2'b01; digito = unidades; end 2'b10: begin mostrar = 2'b10; digito = decenas; end 2'b11: begin mostrar = 2'b11; digito = centenas; end endcase end endmodule

/* Copyright 2018 Nuclei System Technology, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ //===================================================================== // // Designer : Bob Hu // // Description: // The top level module of qspi_4cs // // ==================================================================== module sirv_qspi_4cs_top( input clk, input rst_n, input i_icb_cmd_valid, output i_icb_cmd_ready, input [32-1:0] i_icb_cmd_addr, input i_icb_cmd_read, input [32-1:0] i_icb_cmd_wdata, output i_icb_rsp_valid, input i_icb_rsp_ready, output [32-1:0] i_icb_rsp_rdata, output io_port_sck, input io_port_dq_0_i, output io_port_dq_0_o, output io_port_dq_0_oe, input io_port_dq_1_i, output io_port_dq_1_o, output io_port_dq_1_oe, input io_port_dq_2_i, output io_port_dq_2_o, output io_port_dq_2_oe, input io_port_dq_3_i, output io_port_dq_3_o, output io_port_dq_3_oe, output io_port_cs_0, output io_port_cs_1, output io_port_cs_2, output io_port_cs_3, output io_tl_i_0_0 ); wire io_tl_r_0_a_ready; assign i_icb_cmd_ready = io_tl_r_0_a_ready; wire io_tl_r_0_a_valid = i_icb_cmd_valid; wire [2:0] io_tl_r_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0; wire [2:0] io_tl_r_0_a_bits_param = 3'b0; wire [2:0] io_tl_r_0_a_bits_size = 3'd2; wire [4:0] io_tl_r_0_a_bits_source = 5'b0; wire [28:0] io_tl_r_0_a_bits_address = i_icb_cmd_addr[28:0]; wire [3:0] io_tl_r_0_a_bits_mask = 4'b1111; wire [31:0] io_tl_r_0_a_bits_data = i_icb_cmd_wdata; wire io_tl_r_0_d_ready = i_icb_rsp_ready; wire [2:0] io_tl_r_0_d_bits_opcode; wire [1:0] io_tl_r_0_d_bits_param; wire [2:0] io_tl_r_0_d_bits_size; wire [4:0] io_tl_r_0_d_bits_source; wire io_tl_r_0_d_bits_sink; wire [1:0] io_tl_r_0_d_bits_addr_lo; wire [31:0] io_tl_r_0_d_bits_data; wire io_tl_r_0_d_bits_error; wire io_tl_r_0_d_valid; assign i_icb_rsp_valid = io_tl_r_0_d_valid; assign i_icb_rsp_rdata = io_tl_r_0_d_bits_data; // Not used wire io_tl_r_0_b_ready = 1'b0; wire io_tl_r_0_b_valid; wire [2:0] io_tl_r_0_b_bits_opcode; wire [1:0] io_tl_r_0_b_bits_param; wire [2:0] io_tl_r_0_b_bits_size; wire [4:0] io_tl_r_0_b_bits_source; wire [28:0] io_tl_r_0_b_bits_address; wire [3:0] io_tl_r_0_b_bits_mask; wire [31:0] io_tl_r_0_b_bits_data; // Not used wire io_tl_r_0_c_ready; wire io_tl_r_0_c_valid = 1'b0; wire [2:0] io_tl_r_0_c_bits_opcode = 3'b0; wire [2:0] io_tl_r_0_c_bits_param = 3'b0; wire [2:0] io_tl_r_0_c_bits_size = 3'd2; wire [4:0] io_tl_r_0_c_bits_source = 5'b0; wire [28:0] io_tl_r_0_c_bits_address = 29'b0; wire [31:0] io_tl_r_0_c_bits_data = 32'b0; wire io_tl_r_0_c_bits_error = 1'b0; // Not used wire io_tl_r_0_e_ready; wire io_tl_r_0_e_valid = 1'b0; wire io_tl_r_0_e_bits_sink = 1'b0; sirv_qspi_4cs u_sirv_qspi_4cs( .clock (clk ), .reset (~rst_n ), .io_tl_r_0_a_ready (io_tl_r_0_a_ready ), .io_tl_r_0_a_valid (io_tl_r_0_a_valid ), .io_tl_r_0_a_bits_opcode (io_tl_r_0_a_bits_opcode ), .io_tl_r_0_a_bits_param (io_tl_r_0_a_bits_param ), .io_tl_r_0_a_bits_size (io_tl_r_0_a_bits_size ), .io_tl_r_0_a_bits_source (io_tl_r_0_a_bits_source ), .io_tl_r_0_a_bits_address (io_tl_r_0_a_bits_address ), .io_tl_r_0_a_bits_mask (io_tl_r_0_a_bits_mask ), .io_tl_r_0_a_bits_data (io_tl_r_0_a_bits_data ), .io_tl_r_0_b_ready (io_tl_r_0_b_ready ), .io_tl_r_0_b_valid (io_tl_r_0_b_valid ), .io_tl_r_0_b_bits_opcode (io_tl_r_0_b_bits_opcode ), .io_tl_r_0_b_bits_param (io_tl_r_0_b_bits_param ), .io_tl_r_0_b_bits_size (io_tl_r_0_b_bits_size ), .io_tl_r_0_b_bits_source (io_tl_r_0_b_bits_source ), .io_tl_r_0_b_bits_address (io_tl_r_0_b_bits_address ), .io_tl_r_0_b_bits_mask (io_tl_r_0_b_bits_mask ), .io_tl_r_0_b_bits_data (io_tl_r_0_b_bits_data ), .io_tl_r_0_c_ready (io_tl_r_0_c_ready ), .io_tl_r_0_c_valid (io_tl_r_0_c_valid ), .io_tl_r_0_c_bits_opcode (io_tl_r_0_c_bits_opcode ), .io_tl_r_0_c_bits_param (io_tl_r_0_c_bits_param ), .io_tl_r_0_c_bits_size (io_tl_r_0_c_bits_size ), .io_tl_r_0_c_bits_source (io_tl_r_0_c_bits_source ), .io_tl_r_0_c_bits_address (io_tl_r_0_c_bits_address ), .io_tl_r_0_c_bits_data (io_tl_r_0_c_bits_data ), .io_tl_r_0_c_bits_error (io_tl_r_0_c_bits_error ), .io_tl_r_0_d_ready (io_tl_r_0_d_ready ), .io_tl_r_0_d_valid (io_tl_r_0_d_valid ), .io_tl_r_0_d_bits_opcode (io_tl_r_0_d_bits_opcode ), .io_tl_r_0_d_bits_param (io_tl_r_0_d_bits_param ), .io_tl_r_0_d_bits_size (io_tl_r_0_d_bits_size ), .io_tl_r_0_d_bits_source (io_tl_r_0_d_bits_source ), .io_tl_r_0_d_bits_sink (io_tl_r_0_d_bits_sink ), .io_tl_r_0_d_bits_addr_lo (io_tl_r_0_d_bits_addr_lo ), .io_tl_r_0_d_bits_data (io_tl_r_0_d_bits_data ), .io_tl_r_0_d_bits_error (io_tl_r_0_d_bits_error ), .io_tl_r_0_e_ready (io_tl_r_0_e_ready ), .io_tl_r_0_e_valid (io_tl_r_0_e_valid ), .io_tl_r_0_e_bits_sink (io_tl_r_0_e_bits_sink ), .io_port_sck (io_port_sck ), .io_port_dq_0_i (io_port_dq_0_i ), .io_port_dq_0_o (io_port_dq_0_o ), .io_port_dq_0_oe (io_port_dq_0_oe), .io_port_dq_1_i (io_port_dq_1_i ), .io_port_dq_1_o (io_port_dq_1_o ), .io_port_dq_1_oe (io_port_dq_1_oe), .io_port_dq_2_i (io_port_dq_2_i ), .io_port_dq_2_o (io_port_dq_2_o ), .io_port_dq_2_oe (io_port_dq_2_oe), .io_port_dq_3_i (io_port_dq_3_i ), .io_port_dq_3_o (io_port_dq_3_o ), .io_port_dq_3_oe (io_port_dq_3_oe), .io_port_cs_0 (io_port_cs_0 ), .io_port_cs_1 (io_port_cs_1 ), .io_port_cs_2 (io_port_cs_2 ), .io_port_cs_3 (io_port_cs_3 ), .io_tl_i_0_0 (io_tl_i_0_0 ) ); endmodule

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Xilinx // Engineer: dtysky // // Create Date: 2015/01/19 09:26:57 // Design Name: INST_MEM // Module Name: INST_MEM // Project Name: MIPS_CPU // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module INST_MEM( input[31:0] a, output[31:0] inst_out ); wire[31:0] rom[0:31]; assign rom[5'h0] = 32'h3c010000; assign rom[5'h1] = 32'h34240050; assign rom[5'h2] = 32'h20050004; assign rom[5'h3] = 32'h0c000018; assign rom[5'h4] = 32'hac820000; assign rom[5'h5] = 32'h8c890000; assign rom[5'h6] = 32'h01244022; assign rom[5'h7] = 32'h20050003; assign rom[5'h8] = 32'h20a5ffff; assign rom[5'h9] = 32'h34a8ffff; assign rom[5'ha] = 32'h39085555; assign rom[5'hb] = 32'h2009ffff; assign rom[5'hc] = 32'h3124ffff; assign rom[5'hd] = 32'h01493025; assign rom[5'he] = 32'h01494026; assign rom[5'hf] = 32'h01463824; assign rom[5'h10] = 32'h10a00001; assign rom[5'h11] = 32'h08000008; assign rom[5'h12] = 32'h2005ffff; assign rom[5'h13] = 32'h000543c0; assign rom[5'h14] = 32'h00084400; assign rom[5'h15] = 32'h00084403; assign rom[5'h16] = 32'h000843c2; assign rom[5'h17] = 32'h08000017; assign rom[5'h18] = 32'h00004020; assign rom[5'h19] = 32'h8c890000; assign rom[5'h1a] = 32'h20840004; assign rom[5'h1b] = 32'h01094020; assign rom[5'h1c] = 32'h20a5ffff; assign rom[5'h1d] = 32'h14a0fffb; assign rom[5'h1e] = 32'h00081000; assign rom[5'h1f] = 32'h03e00008; assign inst_out = rom[a[6:2]]; endmodule

// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Wilson Snyder. module t (/*AUTOARG*/ // Inputs clk ); input clk; integer cyc=0; reg [63:0] crc; reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] Operand1 = crc[31:0]; wire [15:0] Operand2 = crc[47:32]; wire Unsigned = crc[48]; reg rst; parameter wl = 16; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire [wl-1:0] Quotient; // From test of Test.v wire [wl-1:0] Remainder; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ // Outputs .Quotient (Quotient[wl-1:0]), .Remainder (Remainder[wl-1:0]), // Inputs .Operand1 (Operand1[wl*2-1:0]), .Operand2 (Operand2[wl-1:0]), .clk (clk), .rst (rst), .Unsigned (Unsigned)); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, Quotient, Remainder}; // What checksum will we end up with `define EXPECTED_SUM 64'h98d41f89a8be5693 // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x it=%x\n",$time, cyc, crc, result, test.Iteration); `endif cyc <= cyc + 1; if (cyc < 20 || test.Iteration==4'd15) begin crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; end sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; if (cyc==0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; rst <= 1'b1; end else if (cyc<20) begin sum <= 64'h0; rst <= 1'b0; end else if (cyc<90) begin end else if (cyc==99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'h8dd70a44972ad809) $stop; if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; end end endmodule module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder); parameter wl = 16; input [wl*2-1:0] Operand1; input [wl-1:0] Operand2; input clk, rst, Unsigned; output [wl-1:0] Quotient, Remainder; reg Cy, Overflow, Sign1, Sign2, Zero, Negative; reg [wl-1:0] ah,al,Quotient, Remainder; reg [3:0] Iteration; reg [wl-1:0] sub_quot,op; reg ah_ext; reg [1:0] a,b,c,d,e; always @(posedge clk) begin if (!rst) begin {a,b,c,d,e} = Operand1[9:0]; {a,b,c,d,e} = {e,d,c,b,a}; if (a != Operand1[1:0]) $stop; if (b != Operand1[3:2]) $stop; if (c != Operand1[5:4]) $stop; if (d != Operand1[7:6]) $stop; if (e != Operand1[9:8]) $stop; end end always @(posedge clk) begin if (rst) begin Iteration <= 0; Quotient <= 0; Remainder <= 0; end else begin if (Iteration == 0) begin {ah,al} = Operand1; op = Operand2; Cy = 0; Overflow = 0; Sign1 = (~Unsigned)&ah[wl-1]; Sign2 = (~Unsigned)&(ah[wl-1]^op[wl-1]); if (Sign1) {ah,al} = -{ah,al}; end `define BUG1 `ifdef BUG1 {ah_ext,ah,al} = {ah,al,Cy}; `else ah_ext = ah[15]; ah[15:1] = ah[14:0]; ah[0] = al[15]; al[15:1] = al[14:0]; al[0] = Cy; `endif `ifdef TEST_VERBOSE $display("%x %x %x %x %x %x %x %x %x", Iteration, ah, al, Quotient, Remainder, Overflow, ah_ext, sub_quot, Cy); `endif {Cy,sub_quot} = (~Unsigned)&op[wl-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1'b1,op}; if (Cy) begin {ah_ext,ah} = {1'b0,sub_quot}; end if (Iteration != 15 ) begin if (ah_ext) Overflow = 1; end else begin if (al[14] && ~Unsigned) Overflow = 1; Quotient <= Sign2 ? -{al[14:0],Cy} : {al[14:0],Cy}; Remainder <= Sign1 ? -ah : ah; if (Overflow) begin Quotient <= Sign2 ? 16'h8001 : {Unsigned,{15{1'b1}}}; Remainder <= Unsigned ? 16'hffff : 16'h8000; Zero = 1; Negative = 1; end end Iteration <= Iteration + 1; // Count number of times this instruction is repeated end end endmodule

/* ---------------------------------------------------------------------------------- Copyright (c) 2013-2014 Embedded and Network Computing Lab. Open SSD Project Hanyang University All rights reserved. ---------------------------------------------------------------------------------- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. All advertising materials mentioning features or use of this source code must display the following acknowledgement: This product includes source code developed by the Embedded and Network Computing Lab. and the Open SSD Project. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------------- http://enclab.hanyang.ac.kr/ http://www.openssd-project.org/ http://www.hanyang.ac.kr/ ---------------------------------------------------------------------------------- */ `timescale 1ns / 1ps module user_top # ( parameter C_S0_AXI_ADDR_WIDTH = 32, parameter C_S0_AXI_DATA_WIDTH = 32, parameter C_S0_AXI_BASEADDR = 32'h80000000, parameter C_S0_AXI_HIGHADDR = 32'h80010000, parameter C_M0_AXI_ADDR_WIDTH = 32, parameter C_M0_AXI_DATA_WIDTH = 64, parameter C_M0_AXI_ID_WIDTH = 1, parameter C_M0_AXI_AWUSER_WIDTH = 1, parameter C_M0_AXI_WUSER_WIDTH = 1, parameter C_M0_AXI_BUSER_WIDTH = 1, parameter C_M0_AXI_ARUSER_WIDTH = 1, parameter C_M0_AXI_RUSER_WIDTH = 1, parameter C_PCIE_DATA_WIDTH = 128 ) ( //////////////////////////////////////////////////////////////// //AXI4-lite slave interface signals input s0_axi_aclk, input s0_axi_aresetn, //Write address channel input [C_S0_AXI_ADDR_WIDTH-1 : 0] s0_axi_awaddr, output s0_axi_awready, input s0_axi_awvalid, input [2 : 0] s0_axi_awprot, //Write data channel input s0_axi_wvalid, output s0_axi_wready, input [C_S0_AXI_DATA_WIDTH-1 : 0] s0_axi_wdata, input [(C_S0_AXI_DATA_WIDTH/8)-1 : 0] s0_axi_wstrb, //Write response channel output s0_axi_bvalid, input s0_axi_bready, output [1 : 0] s0_axi_bresp, //Read address channel input s0_axi_arvalid, output s0_axi_arready, input [C_S0_AXI_ADDR_WIDTH-1 : 0] s0_axi_araddr, input [2 : 0] s0_axi_arprot, //Read data channel output s0_axi_rvalid, input s0_axi_rready, output [C_S0_AXI_DATA_WIDTH-1 : 0] s0_axi_rdata, output [1 : 0] s0_axi_rresp, //////////////////////////////////////////////////////////////// //AXI4 master interface signals input m0_axi_aclk, input m0_axi_aresetn, // Write address channel output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_awid, output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_awaddr, output [7:0] m0_axi_awlen, output [2:0] m0_axi_awsize, output [1:0] m0_axi_awburst, output [1:0] m0_axi_awlock, output [3:0] m0_axi_awcache, output [2:0] m0_axi_awprot, output [3:0] m0_axi_awregion, output [3:0] m0_axi_awqos, output [C_M0_AXI_AWUSER_WIDTH-1:0] m0_axi_awuser, output m0_axi_awvalid, input m0_axi_awready, // Write data channel output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_wid, output [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_wdata, output [(C_M0_AXI_DATA_WIDTH/8)-1:0] m0_axi_wstrb, output m0_axi_wlast, output [C_M0_AXI_WUSER_WIDTH-1:0] m0_axi_wuser, output m0_axi_wvalid, input m0_axi_wready, // Write response channel input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_bid, input [1:0] m0_axi_bresp, input m0_axi_bvalid, input [C_M0_AXI_BUSER_WIDTH-1:0] m0_axi_buser, output m0_axi_bready, // Read address channel output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_arid, output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_araddr, output [7:0] m0_axi_arlen, output [2:0] m0_axi_arsize, output [1:0] m0_axi_arburst, output [1:0] m0_axi_arlock, output [3:0] m0_axi_arcache, output [2:0] m0_axi_arprot, output [3:0] m0_axi_arregion, output [3:0] m0_axi_arqos, output [C_M0_AXI_ARUSER_WIDTH-1:0] m0_axi_aruser, output m0_axi_arvalid, input m0_axi_arready, // Read data channel input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_rid, input [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_rdata, input [1:0] m0_axi_rresp, input m0_axi_rlast, input [C_M0_AXI_RUSER_WIDTH-1:0] m0_axi_ruser, input m0_axi_rvalid, output m0_axi_rready, input pcie_ref_clk_p, input pcie_ref_clk_n, input pcie_perst_n, output dev_irq_assert, //PCIe Integrated Block Interface input user_clk_out, input user_reset_out, input user_lnk_up, input [5:0] tx_buf_av, input tx_err_drop, input tx_cfg_req, input s_axis_tx_tready, output [C_PCIE_DATA_WIDTH-1:0] s_axis_tx_tdata, output [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_tx_tkeep, output [3:0] s_axis_tx_tuser, output s_axis_tx_tlast, output s_axis_tx_tvalid, output tx_cfg_gnt, input [C_PCIE_DATA_WIDTH-1:0] m_axis_rx_tdata, input [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_rx_tkeep, input m_axis_rx_tlast, input m_axis_rx_tvalid, output m_axis_rx_tready, input [21:0] m_axis_rx_tuser, output rx_np_ok, output rx_np_req, input [11:0] fc_cpld, input [7:0] fc_cplh, input [11:0] fc_npd, input [7:0] fc_nph, input [11:0] fc_pd, input [7:0] fc_ph, output [2:0] fc_sel, input [7:0] cfg_bus_number, input [4:0] cfg_device_number, input [2:0] cfg_function_number, output cfg_interrupt, input cfg_interrupt_rdy, output cfg_interrupt_assert, output [7:0] cfg_interrupt_di, input [7:0] cfg_interrupt_do, input [2:0] cfg_interrupt_mmenable, input cfg_interrupt_msienable, input cfg_interrupt_msixenable, input cfg_interrupt_msixfm, output cfg_interrupt_stat, output [4:0] cfg_pciecap_interrupt_msgnum, input cfg_to_turnoff, output cfg_turnoff_ok, input [15:0] cfg_command, input [15:0] cfg_dcommand, input [15:0] cfg_lcommand, input [5:0] pl_ltssm_state, input pl_received_hot_rst, output sys_clk, output sys_rst_n ); parameter C_PCIE_ADDR_WIDTH = 36; wire pcie_user_rst_n; wire w_pcie_user_logic_rst; wire w_pcie_link_up_sync; wire [5:0] w_pl_ltssm_state_sync; wire [15:0] w_cfg_command_sync; wire [2:0] w_cfg_interrupt_mmenable_sync; wire w_cfg_interrupt_msienable_sync; wire w_cfg_interrupt_msixenable_sync; wire w_pcie_mreq_err_sync; wire w_pcie_cpld_err_sync; wire w_pcie_cpld_len_err_sync; wire w_nvme_cc_en_sync; wire [1:0] w_nvme_cc_shn_sync; wire [1:0] w_nvme_csts_shst; wire w_nvme_csts_rdy; wire [8:0] w_sq_valid; wire [7:0] w_io_sq1_size; wire [7:0] w_io_sq2_size; wire [7:0] w_io_sq3_size; wire [7:0] w_io_sq4_size; wire [7:0] w_io_sq5_size; wire [7:0] w_io_sq6_size; wire [7:0] w_io_sq7_size; wire [7:0] w_io_sq8_size; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq1_bs_addr; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq2_bs_addr; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq3_bs_addr; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq4_bs_addr; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq5_bs_addr; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq6_bs_addr; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq7_bs_addr; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq8_bs_addr; wire [3:0] w_io_sq1_cq_vec; wire [3:0] w_io_sq2_cq_vec; wire [3:0] w_io_sq3_cq_vec; wire [3:0] w_io_sq4_cq_vec; wire [3:0] w_io_sq5_cq_vec; wire [3:0] w_io_sq6_cq_vec; wire [3:0] w_io_sq7_cq_vec; wire [3:0] w_io_sq8_cq_vec; wire [8:0] w_cq_valid; wire [7:0] w_io_cq1_size; wire [7:0] w_io_cq2_size; wire [7:0] w_io_cq3_size; wire [7:0] w_io_cq4_size; wire [7:0] w_io_cq5_size; wire [7:0] w_io_cq6_size; wire [7:0] w_io_cq7_size; wire [7:0] w_io_cq8_size; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq1_bs_addr; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq2_bs_addr; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq3_bs_addr; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq4_bs_addr; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq5_bs_addr; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq6_bs_addr; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq7_bs_addr; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq8_bs_addr; wire [8:0] w_io_cq_irq_en; wire [2:0] w_io_cq1_iv; wire [2:0] w_io_cq2_iv; wire [2:0] w_io_cq3_iv; wire [2:0] w_io_cq4_iv; wire [2:0] w_io_cq5_iv; wire [2:0] w_io_cq6_iv; wire [2:0] w_io_cq7_iv; wire [2:0] w_io_cq8_iv; wire w_nvme_cc_en; wire [1:0] w_nvme_cc_shn; wire w_pcie_mreq_err; wire w_pcie_cpld_err; wire w_pcie_cpld_len_err; wire [1:0] w_nvme_csts_shst_sync; wire w_nvme_csts_rdy_sync; wire [8:0] w_sq_rst_n_sync; wire [8:0] w_sq_valid_sync; wire [7:0] w_io_sq1_size_sync; wire [7:0] w_io_sq2_size_sync; wire [7:0] w_io_sq3_size_sync; wire [7:0] w_io_sq4_size_sync; wire [7:0] w_io_sq5_size_sync; wire [7:0] w_io_sq6_size_sync; wire [7:0] w_io_sq7_size_sync; wire [7:0] w_io_sq8_size_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq1_bs_addr_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq2_bs_addr_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq3_bs_addr_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq4_bs_addr_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq5_bs_addr_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq6_bs_addr_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq7_bs_addr_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq8_bs_addr_sync; wire [3:0] w_io_sq1_cq_vec_sync; wire [3:0] w_io_sq2_cq_vec_sync; wire [3:0] w_io_sq3_cq_vec_sync; wire [3:0] w_io_sq4_cq_vec_sync; wire [3:0] w_io_sq5_cq_vec_sync; wire [3:0] w_io_sq6_cq_vec_sync; wire [3:0] w_io_sq7_cq_vec_sync; wire [3:0] w_io_sq8_cq_vec_sync; wire [8:0] w_cq_rst_n_sync; wire [8:0] w_cq_valid_sync; wire [7:0] w_io_cq1_size_sync; wire [7:0] w_io_cq2_size_sync; wire [7:0] w_io_cq3_size_sync; wire [7:0] w_io_cq4_size_sync; wire [7:0] w_io_cq5_size_sync; wire [7:0] w_io_cq6_size_sync; wire [7:0] w_io_cq7_size_sync; wire [7:0] w_io_cq8_size_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq1_bs_addr_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq2_bs_addr_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq3_bs_addr_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq4_bs_addr_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq5_bs_addr_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq6_bs_addr_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq7_bs_addr_sync; wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq8_bs_addr_sync; wire [8:0] w_io_cq_irq_en_sync; wire [2:0] w_io_cq1_iv_sync; wire [2:0] w_io_cq2_iv_sync; wire [2:0] w_io_cq3_iv_sync; wire [2:0] w_io_cq4_iv_sync; wire [2:0] w_io_cq5_iv_sync; wire [2:0] w_io_cq6_iv_sync; wire [2:0] w_io_cq7_iv_sync; wire [2:0] w_io_cq8_iv_sync; wire [10:0] w_hcmd_table_rd_addr; wire [31:0] w_hcmd_table_rd_data; wire w_hcmd_sq_rd_en; wire [18:0] w_hcmd_sq_rd_data; wire w_hcmd_sq_empty_n; wire w_hcmd_cq_wr1_en; wire [34:0] w_hcmd_cq_wr1_data0; wire [34:0] w_hcmd_cq_wr1_data1; wire w_hcmd_cq_wr1_rdy_n; wire w_dma_cmd_wr_en; wire [49:0] w_dma_cmd_wr_data0; wire [49:0] w_dma_cmd_wr_data1; wire w_dma_cmd_wr_rdy_n; wire [7:0] w_dma_rx_direct_done_cnt; wire [7:0] w_dma_tx_direct_done_cnt; wire [7:0] w_dma_rx_done_cnt; wire [7:0] w_dma_tx_done_cnt; wire w_pcie_rx_fifo_rd_en; wire [C_M0_AXI_DATA_WIDTH-1:0] w_pcie_rx_fifo_rd_data; wire w_pcie_rx_fifo_free_en; wire [9:4] w_pcie_rx_fifo_free_len; wire w_pcie_rx_fifo_empty_n; wire w_pcie_tx_fifo_alloc_en; wire [9:4] w_pcie_tx_fifo_alloc_len; wire w_pcie_tx_fifo_wr_en; wire [C_M0_AXI_DATA_WIDTH-1:0] w_pcie_tx_fifo_wr_data; wire w_pcie_tx_fifo_full_n; wire w_dma_rx_done_wr_en; wire [20:0] w_dma_rx_done_wr_data; wire w_dma_rx_done_wr_rdy_n; wire w_dev_rx_cmd_wr_en; wire [29:0] w_dev_rx_cmd_wr_data; wire w_dev_rx_cmd_full_n; wire w_dev_tx_cmd_wr_en; wire [29:0] w_dev_tx_cmd_wr_data; wire w_dev_tx_cmd_full_n; sys_rst sys_rst_inst0( .cpu_bus_clk (s0_axi_aclk), .cpu_bus_rst_n (s0_axi_aresetn), .pcie_perst_n (pcie_perst_n), .user_reset_out (user_reset_out), .pcie_pl_hot_rst (pl_received_hot_rst), .pcie_user_logic_rst (w_pcie_user_logic_rst), .pcie_sys_rst_n (sys_rst_n), .pcie_user_rst_n (pcie_user_rst_n) ); s_axi_top # ( .C_S0_AXI_ADDR_WIDTH (C_S0_AXI_ADDR_WIDTH), .C_S0_AXI_DATA_WIDTH (C_S0_AXI_DATA_WIDTH), .C_S0_AXI_BASEADDR (C_S0_AXI_BASEADDR), .C_S0_AXI_HIGHADDR (C_S0_AXI_HIGHADDR), .C_M0_AXI_ADDR_WIDTH (C_M0_AXI_ADDR_WIDTH), .C_M0_AXI_DATA_WIDTH (C_M0_AXI_DATA_WIDTH), .C_M0_AXI_ID_WIDTH (C_M0_AXI_ID_WIDTH), .C_M0_AXI_AWUSER_WIDTH (C_M0_AXI_AWUSER_WIDTH), .C_M0_AXI_WUSER_WIDTH (C_M0_AXI_WUSER_WIDTH), .C_M0_AXI_BUSER_WIDTH (C_M0_AXI_BUSER_WIDTH), .C_M0_AXI_ARUSER_WIDTH (C_M0_AXI_ARUSER_WIDTH), .C_M0_AXI_RUSER_WIDTH (C_M0_AXI_RUSER_WIDTH) ) s_axi_top_inst0 ( //////////////////////////////////////////////////////////////// //AXI4-lite slave interface signals .s0_axi_aclk (s0_axi_aclk), .s0_axi_aresetn (s0_axi_aresetn), //Write address channel .s0_axi_awaddr (s0_axi_awaddr), .s0_axi_awready (s0_axi_awready), .s0_axi_awvalid (s0_axi_awvalid), .s0_axi_awprot (s0_axi_awprot), //Write data channel .s0_axi_wvalid (s0_axi_wvalid), .s0_axi_wready (s0_axi_wready), .s0_axi_wdata (s0_axi_wdata), .s0_axi_wstrb (s0_axi_wstrb), //Write response channel .s0_axi_bvalid (s0_axi_bvalid), .s0_axi_bready (s0_axi_bready), .s0_axi_bresp (s0_axi_bresp), //Read address channel .s0_axi_arvalid (s0_axi_arvalid), .s0_axi_arready (s0_axi_arready), .s0_axi_araddr (s0_axi_araddr), .s0_axi_arprot (s0_axi_arprot), //Read data channel .s0_axi_rvalid (s0_axi_rvalid), .s0_axi_rready (s0_axi_rready), .s0_axi_rdata (s0_axi_rdata), .s0_axi_rresp (s0_axi_rresp), .pcie_mreq_err (w_pcie_mreq_err_sync), .pcie_cpld_err (w_pcie_cpld_err_sync), .pcie_cpld_len_err (w_pcie_cpld_len_err_sync), .dev_irq_assert (dev_irq_assert), .pcie_user_logic_rst (w_pcie_user_logic_rst), .nvme_cc_en (w_nvme_cc_en_sync), .nvme_cc_shn (w_nvme_cc_shn_sync), .nvme_csts_shst (w_nvme_csts_shst), .nvme_csts_rdy (w_nvme_csts_rdy), .sq_valid (w_sq_valid), .io_sq1_size (w_io_sq1_size), .io_sq2_size (w_io_sq2_size), .io_sq3_size (w_io_sq3_size), .io_sq4_size (w_io_sq4_size), .io_sq5_size (w_io_sq5_size), .io_sq6_size (w_io_sq6_size), .io_sq7_size (w_io_sq7_size), .io_sq8_size (w_io_sq8_size), .io_sq1_bs_addr (w_io_sq1_bs_addr), .io_sq2_bs_addr (w_io_sq2_bs_addr), .io_sq3_bs_addr (w_io_sq3_bs_addr), .io_sq4_bs_addr (w_io_sq4_bs_addr), .io_sq5_bs_addr (w_io_sq5_bs_addr), .io_sq6_bs_addr (w_io_sq6_bs_addr), .io_sq7_bs_addr (w_io_sq7_bs_addr), .io_sq8_bs_addr (w_io_sq8_bs_addr), .io_sq1_cq_vec (w_io_sq1_cq_vec), .io_sq2_cq_vec (w_io_sq2_cq_vec), .io_sq3_cq_vec (w_io_sq3_cq_vec), .io_sq4_cq_vec (w_io_sq4_cq_vec), .io_sq5_cq_vec (w_io_sq5_cq_vec), .io_sq6_cq_vec (w_io_sq6_cq_vec), .io_sq7_cq_vec (w_io_sq7_cq_vec), .io_sq8_cq_vec (w_io_sq8_cq_vec), .cq_valid (w_cq_valid), .io_cq1_size (w_io_cq1_size), .io_cq2_size (w_io_cq2_size), .io_cq3_size (w_io_cq3_size), .io_cq4_size (w_io_cq4_size), .io_cq5_size (w_io_cq5_size), .io_cq6_size (w_io_cq6_size), .io_cq7_size (w_io_cq7_size), .io_cq8_size (w_io_cq8_size), .io_cq1_bs_addr (w_io_cq1_bs_addr), .io_cq2_bs_addr (w_io_cq2_bs_addr), .io_cq3_bs_addr (w_io_cq3_bs_addr), .io_cq4_bs_addr (w_io_cq4_bs_addr), .io_cq5_bs_addr (w_io_cq5_bs_addr), .io_cq6_bs_addr (w_io_cq6_bs_addr), .io_cq7_bs_addr (w_io_cq7_bs_addr), .io_cq8_bs_addr (w_io_cq8_bs_addr), .io_cq_irq_en (w_io_cq_irq_en), .io_cq1_iv (w_io_cq1_iv), .io_cq2_iv (w_io_cq2_iv), .io_cq3_iv (w_io_cq3_iv), .io_cq4_iv (w_io_cq4_iv), .io_cq5_iv (w_io_cq5_iv), .io_cq6_iv (w_io_cq6_iv), .io_cq7_iv (w_io_cq7_iv), .io_cq8_iv (w_io_cq8_iv), .hcmd_sq_rd_en (w_hcmd_sq_rd_en), .hcmd_sq_rd_data (w_hcmd_sq_rd_data), .hcmd_sq_empty_n (w_hcmd_sq_empty_n), .hcmd_table_rd_addr (w_hcmd_table_rd_addr), .hcmd_table_rd_data (w_hcmd_table_rd_data), .hcmd_cq_wr1_en (w_hcmd_cq_wr1_en), .hcmd_cq_wr1_data0 (w_hcmd_cq_wr1_data0), .hcmd_cq_wr1_data1 (w_hcmd_cq_wr1_data1), .hcmd_cq_wr1_rdy_n (w_hcmd_cq_wr1_rdy_n), .dma_cmd_wr_en (w_dma_cmd_wr_en), .dma_cmd_wr_data0 (w_dma_cmd_wr_data0), .dma_cmd_wr_data1 (w_dma_cmd_wr_data1), .dma_cmd_wr_rdy_n (w_dma_cmd_wr_rdy_n), //////////////////////////////////////////////////////////////// //AXI4 master interface signals .m0_axi_aclk (m0_axi_aclk), .m0_axi_aresetn (m0_axi_aresetn), // Write address channel .m0_axi_awid (m0_axi_awid), .m0_axi_awaddr (m0_axi_awaddr), .m0_axi_awlen (m0_axi_awlen), .m0_axi_awsize (m0_axi_awsize), .m0_axi_awburst (m0_axi_awburst), .m0_axi_awlock (m0_axi_awlock), .m0_axi_awcache (m0_axi_awcache), .m0_axi_awprot (m0_axi_awprot), .m0_axi_awregion (m0_axi_awregion), .m0_axi_awqos (m0_axi_awqos), .m0_axi_awuser (m0_axi_awuser), .m0_axi_awvalid (m0_axi_awvalid), .m0_axi_awready (m0_axi_awready), // Write data channel .m0_axi_wid (m0_axi_wid), .m0_axi_wdata (m0_axi_wdata), .m0_axi_wstrb (m0_axi_wstrb), .m0_axi_wlast (m0_axi_wlast), .m0_axi_wuser (m0_axi_wuser), .m0_axi_wvalid (m0_axi_wvalid), .m0_axi_wready (m0_axi_wready), // Write response channel .m0_axi_bid (m0_axi_bid), .m0_axi_bresp (m0_axi_bresp), .m0_axi_bvalid (m0_axi_bvalid), .m0_axi_buser (m0_axi_buser), .m0_axi_bready (m0_axi_bready), // Read address channel .m0_axi_arid (m0_axi_arid), .m0_axi_araddr (m0_axi_araddr), .m0_axi_arlen (m0_axi_arlen), .m0_axi_arsize (m0_axi_arsize), .m0_axi_arburst (m0_axi_arburst), .m0_axi_arlock (m0_axi_arlock), .m0_axi_arcache (m0_axi_arcache), .m0_axi_arprot (m0_axi_arprot), .m0_axi_arregion (m0_axi_arregion), .m0_axi_arqos (m0_axi_arqos), .m0_axi_aruser (m0_axi_aruser), .m0_axi_arvalid (m0_axi_arvalid), .m0_axi_arready (m0_axi_arready), // Read data channel .m0_axi_rid (m0_axi_rid), .m0_axi_rdata (m0_axi_rdata), .m0_axi_rresp (m0_axi_rresp), .m0_axi_rlast (m0_axi_rlast), .m0_axi_ruser (m0_axi_ruser), .m0_axi_rvalid (m0_axi_rvalid), .m0_axi_rready (m0_axi_rready), .pcie_rx_fifo_rd_en (w_pcie_rx_fifo_rd_en), .pcie_rx_fifo_rd_data (w_pcie_rx_fifo_rd_data), .pcie_rx_fifo_free_en (w_pcie_rx_fifo_free_en), .pcie_rx_fifo_free_len (w_pcie_rx_fifo_free_len), .pcie_rx_fifo_empty_n (w_pcie_rx_fifo_empty_n), .pcie_tx_fifo_alloc_en (w_pcie_tx_fifo_alloc_en), .pcie_tx_fifo_alloc_len (w_pcie_tx_fifo_alloc_len), .pcie_tx_fifo_wr_en (w_pcie_tx_fifo_wr_en), .pcie_tx_fifo_wr_data (w_pcie_tx_fifo_wr_data), .pcie_tx_fifo_full_n (w_pcie_tx_fifo_full_n), .dma_rx_done_wr_en (w_dma_rx_done_wr_en), .dma_rx_done_wr_data (w_dma_rx_done_wr_data), .dma_rx_done_wr_rdy_n (w_dma_rx_done_wr_rdy_n), .pcie_user_clk (user_clk_out), .pcie_user_rst_n (pcie_user_rst_n), .dev_rx_cmd_wr_en (w_dev_rx_cmd_wr_en), .dev_rx_cmd_wr_data (w_dev_rx_cmd_wr_data), .dev_rx_cmd_full_n (w_dev_rx_cmd_full_n), .dev_tx_cmd_wr_en (w_dev_tx_cmd_wr_en), .dev_tx_cmd_wr_data (w_dev_tx_cmd_wr_data), .dev_tx_cmd_full_n (w_dev_tx_cmd_full_n), .dma_rx_direct_done_cnt (w_dma_rx_direct_done_cnt), .dma_tx_direct_done_cnt (w_dma_tx_direct_done_cnt), .dma_rx_done_cnt (w_dma_rx_done_cnt), .dma_tx_done_cnt (w_dma_tx_done_cnt), .pcie_link_up (w_pcie_link_up_sync), .pl_ltssm_state (w_pl_ltssm_state_sync), .cfg_command (w_cfg_command_sync), .cfg_interrupt_mmenable (w_cfg_interrupt_mmenable_sync), .cfg_interrupt_msienable (w_cfg_interrupt_msienable_sync), .cfg_interrupt_msixenable (w_cfg_interrupt_msixenable_sync) ); reg_cpu_pcie_sync reg_cpu_pcie_sync_isnt0 ( .cpu_bus_clk (s0_axi_aclk), .nvme_csts_shst (w_nvme_csts_shst), .nvme_csts_rdy (w_nvme_csts_rdy), .sq_valid (w_sq_valid), .io_sq1_size (w_io_sq1_size), .io_sq2_size (w_io_sq2_size), .io_sq3_size (w_io_sq3_size), .io_sq4_size (w_io_sq4_size), .io_sq5_size (w_io_sq5_size), .io_sq6_size (w_io_sq6_size), .io_sq7_size (w_io_sq7_size), .io_sq8_size (w_io_sq8_size), .io_sq1_bs_addr (w_io_sq1_bs_addr), .io_sq2_bs_addr (w_io_sq2_bs_addr), .io_sq3_bs_addr (w_io_sq3_bs_addr), .io_sq4_bs_addr (w_io_sq4_bs_addr), .io_sq5_bs_addr (w_io_sq5_bs_addr), .io_sq6_bs_addr (w_io_sq6_bs_addr), .io_sq7_bs_addr (w_io_sq7_bs_addr), .io_sq8_bs_addr (w_io_sq8_bs_addr), .io_sq1_cq_vec (w_io_sq1_cq_vec), .io_sq2_cq_vec (w_io_sq2_cq_vec), .io_sq3_cq_vec (w_io_sq3_cq_vec), .io_sq4_cq_vec (w_io_sq4_cq_vec), .io_sq5_cq_vec (w_io_sq5_cq_vec), .io_sq6_cq_vec (w_io_sq6_cq_vec), .io_sq7_cq_vec (w_io_sq7_cq_vec), .io_sq8_cq_vec (w_io_sq8_cq_vec), .cq_valid (w_cq_valid), .io_cq1_size (w_io_cq1_size), .io_cq2_size (w_io_cq2_size), .io_cq3_size (w_io_cq3_size), .io_cq4_size (w_io_cq4_size), .io_cq5_size (w_io_cq5_size), .io_cq6_size (w_io_cq6_size), .io_cq7_size (w_io_cq7_size), .io_cq8_size (w_io_cq8_size), .io_cq1_bs_addr (w_io_cq1_bs_addr), .io_cq2_bs_addr (w_io_cq2_bs_addr), .io_cq3_bs_addr (w_io_cq3_bs_addr), .io_cq4_bs_addr (w_io_cq4_bs_addr), .io_cq5_bs_addr (w_io_cq5_bs_addr), .io_cq6_bs_addr (w_io_cq6_bs_addr), .io_cq7_bs_addr (w_io_cq7_bs_addr), .io_cq8_bs_addr (w_io_cq8_bs_addr), .io_cq_irq_en (w_io_cq_irq_en), .io_cq1_iv (w_io_cq1_iv), .io_cq2_iv (w_io_cq2_iv), .io_cq3_iv (w_io_cq3_iv), .io_cq4_iv (w_io_cq4_iv), .io_cq5_iv (w_io_cq5_iv), .io_cq6_iv (w_io_cq6_iv), .io_cq7_iv (w_io_cq7_iv), .io_cq8_iv (w_io_cq8_iv), .pcie_link_up_sync (w_pcie_link_up_sync), .pl_ltssm_state_sync (w_pl_ltssm_state_sync), .cfg_command_sync (w_cfg_command_sync), .cfg_interrupt_mmenable_sync (w_cfg_interrupt_mmenable_sync), .cfg_interrupt_msienable_sync (w_cfg_interrupt_msienable_sync), .cfg_interrupt_msixenable_sync (w_cfg_interrupt_msixenable_sync), .pcie_mreq_err_sync (w_pcie_mreq_err_sync), .pcie_cpld_err_sync (w_pcie_cpld_err_sync), .pcie_cpld_len_err_sync (w_pcie_cpld_len_err_sync), .nvme_cc_en_sync (w_nvme_cc_en_sync), .nvme_cc_shn_sync (w_nvme_cc_shn_sync), .pcie_user_clk (user_clk_out), .pcie_link_up (user_lnk_up), .pl_ltssm_state (pl_ltssm_state), .cfg_command (cfg_command), .cfg_interrupt_mmenable (cfg_interrupt_mmenable), .cfg_interrupt_msienable (cfg_interrupt_msienable), .cfg_interrupt_msixenable (cfg_interrupt_msixenable), .pcie_mreq_err (w_pcie_mreq_err), .pcie_cpld_err (w_pcie_cpld_err), .pcie_cpld_len_err (w_pcie_cpld_len_err), .nvme_cc_en (w_nvme_cc_en), .nvme_cc_shn (w_nvme_cc_shn), .nvme_csts_shst_sync (w_nvme_csts_shst_sync), .nvme_csts_rdy_sync (w_nvme_csts_rdy_sync), .sq_rst_n_sync (w_sq_rst_n_sync), .sq_valid_sync (w_sq_valid_sync), .io_sq1_size_sync (w_io_sq1_size_sync), .io_sq2_size_sync (w_io_sq2_size_sync), .io_sq3_size_sync (w_io_sq3_size_sync), .io_sq4_size_sync (w_io_sq4_size_sync), .io_sq5_size_sync (w_io_sq5_size_sync), .io_sq6_size_sync (w_io_sq6_size_sync), .io_sq7_size_sync (w_io_sq7_size_sync), .io_sq8_size_sync (w_io_sq8_size_sync), .io_sq1_bs_addr_sync (w_io_sq1_bs_addr_sync), .io_sq2_bs_addr_sync (w_io_sq2_bs_addr_sync), .io_sq3_bs_addr_sync (w_io_sq3_bs_addr_sync), .io_sq4_bs_addr_sync (w_io_sq4_bs_addr_sync), .io_sq5_bs_addr_sync (w_io_sq5_bs_addr_sync), .io_sq6_bs_addr_sync (w_io_sq6_bs_addr_sync), .io_sq7_bs_addr_sync (w_io_sq7_bs_addr_sync), .io_sq8_bs_addr_sync (w_io_sq8_bs_addr_sync), .io_sq1_cq_vec_sync (w_io_sq1_cq_vec_sync), .io_sq2_cq_vec_sync (w_io_sq2_cq_vec_sync), .io_sq3_cq_vec_sync (w_io_sq3_cq_vec_sync), .io_sq4_cq_vec_sync (w_io_sq4_cq_vec_sync), .io_sq5_cq_vec_sync (w_io_sq5_cq_vec_sync), .io_sq6_cq_vec_sync (w_io_sq6_cq_vec_sync), .io_sq7_cq_vec_sync (w_io_sq7_cq_vec_sync), .io_sq8_cq_vec_sync (w_io_sq8_cq_vec_sync), .cq_rst_n_sync (w_cq_rst_n_sync), .cq_valid_sync (w_cq_valid_sync), .io_cq1_size_sync (w_io_cq1_size_sync), .io_cq2_size_sync (w_io_cq2_size_sync), .io_cq3_size_sync (w_io_cq3_size_sync), .io_cq4_size_sync (w_io_cq4_size_sync), .io_cq5_size_sync (w_io_cq5_size_sync), .io_cq6_size_sync (w_io_cq6_size_sync), .io_cq7_size_sync (w_io_cq7_size_sync), .io_cq8_size_sync (w_io_cq8_size_sync), .io_cq1_bs_addr_sync (w_io_cq1_bs_addr_sync), .io_cq2_bs_addr_sync (w_io_cq2_bs_addr_sync), .io_cq3_bs_addr_sync (w_io_cq3_bs_addr_sync), .io_cq4_bs_addr_sync (w_io_cq4_bs_addr_sync), .io_cq5_bs_addr_sync (w_io_cq5_bs_addr_sync), .io_cq6_bs_addr_sync (w_io_cq6_bs_addr_sync), .io_cq7_bs_addr_sync (w_io_cq7_bs_addr_sync), .io_cq8_bs_addr_sync (w_io_cq8_bs_addr_sync), .io_cq_irq_en_sync (w_io_cq_irq_en_sync), .io_cq1_iv_sync (w_io_cq1_iv_sync), .io_cq2_iv_sync (w_io_cq2_iv_sync), .io_cq3_iv_sync (w_io_cq3_iv_sync), .io_cq4_iv_sync (w_io_cq4_iv_sync), .io_cq5_iv_sync (w_io_cq5_iv_sync), .io_cq6_iv_sync (w_io_cq6_iv_sync), .io_cq7_iv_sync (w_io_cq7_iv_sync), .io_cq8_iv_sync (w_io_cq8_iv_sync) ); nvme_pcie # ( .C_PCIE_DATA_WIDTH (128) ) nvme_pcie_inst0( .pcie_ref_clk_p (pcie_ref_clk_p), .pcie_ref_clk_n (pcie_ref_clk_n), //PCIe user clock .pcie_user_clk (user_clk_out), .pcie_user_rst_n (pcie_user_rst_n), .dev_rx_cmd_wr_en (w_dev_rx_cmd_wr_en), .dev_rx_cmd_wr_data (w_dev_rx_cmd_wr_data), .dev_rx_cmd_full_n (w_dev_rx_cmd_full_n), .dev_tx_cmd_wr_en (w_dev_tx_cmd_wr_en), .dev_tx_cmd_wr_data (w_dev_tx_cmd_wr_data), .dev_tx_cmd_full_n (w_dev_tx_cmd_full_n), .cpu_bus_clk (s0_axi_aclk), .cpu_bus_rst_n (s0_axi_aresetn), .nvme_cc_en (w_nvme_cc_en), .nvme_cc_shn (w_nvme_cc_shn), .nvme_csts_shst (w_nvme_csts_shst_sync), .nvme_csts_rdy (w_nvme_csts_rdy_sync), .sq_rst_n (w_sq_rst_n_sync), .sq_valid (w_sq_valid_sync), .io_sq1_size (w_io_sq1_size_sync), .io_sq2_size (w_io_sq2_size_sync), .io_sq3_size (w_io_sq3_size_sync), .io_sq4_size (w_io_sq4_size_sync), .io_sq5_size (w_io_sq5_size_sync), .io_sq6_size (w_io_sq6_size_sync), .io_sq7_size (w_io_sq7_size_sync), .io_sq8_size (w_io_sq8_size_sync), .io_sq1_bs_addr (w_io_sq1_bs_addr_sync), .io_sq2_bs_addr (w_io_sq2_bs_addr_sync), .io_sq3_bs_addr (w_io_sq3_bs_addr_sync), .io_sq4_bs_addr (w_io_sq4_bs_addr_sync), .io_sq5_bs_addr (w_io_sq5_bs_addr_sync), .io_sq6_bs_addr (w_io_sq6_bs_addr_sync), .io_sq7_bs_addr (w_io_sq7_bs_addr_sync), .io_sq8_bs_addr (w_io_sq8_bs_addr_sync), .io_sq1_cq_vec (w_io_sq1_cq_vec_sync), .io_sq2_cq_vec (w_io_sq2_cq_vec_sync), .io_sq3_cq_vec (w_io_sq3_cq_vec_sync), .io_sq4_cq_vec (w_io_sq4_cq_vec_sync), .io_sq5_cq_vec (w_io_sq5_cq_vec_sync), .io_sq6_cq_vec (w_io_sq6_cq_vec_sync), .io_sq7_cq_vec (w_io_sq7_cq_vec_sync), .io_sq8_cq_vec (w_io_sq8_cq_vec_sync), .cq_rst_n (w_cq_rst_n_sync), .cq_valid (w_cq_valid_sync), .io_cq1_size (w_io_cq1_size_sync), .io_cq2_size (w_io_cq2_size_sync), .io_cq3_size (w_io_cq3_size_sync), .io_cq4_size (w_io_cq4_size_sync), .io_cq5_size (w_io_cq5_size_sync), .io_cq6_size (w_io_cq6_size_sync), .io_cq7_size (w_io_cq7_size_sync), .io_cq8_size (w_io_cq8_size_sync), .io_cq1_bs_addr (w_io_cq1_bs_addr_sync), .io_cq2_bs_addr (w_io_cq2_bs_addr_sync), .io_cq3_bs_addr (w_io_cq3_bs_addr_sync), .io_cq4_bs_addr (w_io_cq4_bs_addr_sync), .io_cq5_bs_addr (w_io_cq5_bs_addr_sync), .io_cq6_bs_addr (w_io_cq6_bs_addr_sync), .io_cq7_bs_addr (w_io_cq7_bs_addr_sync), .io_cq8_bs_addr (w_io_cq8_bs_addr_sync), .io_cq_irq_en (w_io_cq_irq_en_sync), .io_cq1_iv (w_io_cq1_iv_sync), .io_cq2_iv (w_io_cq2_iv_sync), .io_cq3_iv (w_io_cq3_iv_sync), .io_cq4_iv (w_io_cq4_iv_sync), .io_cq5_iv (w_io_cq5_iv_sync), .io_cq6_iv (w_io_cq6_iv_sync), .io_cq7_iv (w_io_cq7_iv_sync), .io_cq8_iv (w_io_cq8_iv_sync), .hcmd_sq_rd_en (w_hcmd_sq_rd_en), .hcmd_sq_rd_data (w_hcmd_sq_rd_data), .hcmd_sq_empty_n (w_hcmd_sq_empty_n), .hcmd_table_rd_addr (w_hcmd_table_rd_addr), .hcmd_table_rd_data (w_hcmd_table_rd_data), .hcmd_cq_wr1_en (w_hcmd_cq_wr1_en), .hcmd_cq_wr1_data0 (w_hcmd_cq_wr1_data0), .hcmd_cq_wr1_data1 (w_hcmd_cq_wr1_data1), .hcmd_cq_wr1_rdy_n (w_hcmd_cq_wr1_rdy_n), .dma_cmd_wr_en (w_dma_cmd_wr_en), .dma_cmd_wr_data0 (w_dma_cmd_wr_data0), .dma_cmd_wr_data1 (w_dma_cmd_wr_data1), .dma_cmd_wr_rdy_n (w_dma_cmd_wr_rdy_n), .dma_rx_direct_done_cnt (w_dma_rx_direct_done_cnt), .dma_tx_direct_done_cnt (w_dma_tx_direct_done_cnt), .dma_rx_done_cnt (w_dma_rx_done_cnt), .dma_tx_done_cnt (w_dma_tx_done_cnt), .dma_bus_clk (m0_axi_aclk), .dma_bus_rst_n (m0_axi_aresetn), .pcie_rx_fifo_rd_en (w_pcie_rx_fifo_rd_en), .pcie_rx_fifo_rd_data (w_pcie_rx_fifo_rd_data), .pcie_rx_fifo_free_en (w_pcie_rx_fifo_free_en), .pcie_rx_fifo_free_len (w_pcie_rx_fifo_free_len), .pcie_rx_fifo_empty_n (w_pcie_rx_fifo_empty_n), .pcie_tx_fifo_alloc_en (w_pcie_tx_fifo_alloc_en), .pcie_tx_fifo_alloc_len (w_pcie_tx_fifo_alloc_len), .pcie_tx_fifo_wr_en (w_pcie_tx_fifo_wr_en), .pcie_tx_fifo_wr_data (w_pcie_tx_fifo_wr_data), .pcie_tx_fifo_full_n (w_pcie_tx_fifo_full_n), .dma_rx_done_wr_en (w_dma_rx_done_wr_en), .dma_rx_done_wr_data (w_dma_rx_done_wr_data), .dma_rx_done_wr_rdy_n (w_dma_rx_done_wr_rdy_n), .pcie_mreq_err (w_pcie_mreq_err), .pcie_cpld_err (w_pcie_cpld_err), .pcie_cpld_len_err (w_pcie_cpld_len_err), .tx_buf_av (tx_buf_av), .tx_err_drop (tx_err_drop), .tx_cfg_req (tx_cfg_req), .s_axis_tx_tready (s_axis_tx_tready), .s_axis_tx_tdata (s_axis_tx_tdata), .s_axis_tx_tkeep (s_axis_tx_tkeep), .s_axis_tx_tuser (s_axis_tx_tuser), .s_axis_tx_tlast (s_axis_tx_tlast), .s_axis_tx_tvalid (s_axis_tx_tvalid), .tx_cfg_gnt (tx_cfg_gnt), .m_axis_rx_tdata (m_axis_rx_tdata), .m_axis_rx_tkeep (m_axis_rx_tkeep), .m_axis_rx_tlast (m_axis_rx_tlast), .m_axis_rx_tvalid (m_axis_rx_tvalid), .m_axis_rx_tready (m_axis_rx_tready), .m_axis_rx_tuser (m_axis_rx_tuser), .rx_np_ok (rx_np_ok), .rx_np_req (rx_np_req), .fc_cpld (fc_cpld), .fc_cplh (fc_cplh), .fc_npd (fc_npd), .fc_nph (fc_nph), .fc_pd (fc_pd), .fc_ph (fc_ph), .fc_sel (fc_sel), .cfg_interrupt (cfg_interrupt), .cfg_interrupt_rdy (cfg_interrupt_rdy), .cfg_interrupt_assert (cfg_interrupt_assert), .cfg_interrupt_di (cfg_interrupt_di), .cfg_interrupt_do (cfg_interrupt_do), .cfg_interrupt_mmenable (cfg_interrupt_mmenable), .cfg_interrupt_msienable (cfg_interrupt_msienable), .cfg_interrupt_msixenable (cfg_interrupt_msixenable), .cfg_interrupt_msixfm (cfg_interrupt_msixfm), .cfg_interrupt_stat (cfg_interrupt_stat), .cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum), .cfg_bus_number (cfg_bus_number), .cfg_device_number (cfg_device_number), .cfg_function_number (cfg_function_number), .cfg_to_turnoff (cfg_to_turnoff), .cfg_turnoff_ok (cfg_turnoff_ok), .cfg_command (cfg_command), .cfg_dcommand (cfg_dcommand), .cfg_lcommand (cfg_lcommand), .sys_clk (sys_clk) ); endmodule

//Copyright (C) 1991-2003 Altera Corporation //Any megafunction design, and related netlist (encrypted or decrypted), //support information, device programming or simulation file, and any other //associated documentation or information provided by Altera or a partner //under Altera's Megafunction Partnership Program may be used only //to program PLD devices (but not masked PLD devices) from Altera. Any //other use of such megafunction design, netlist, support information, //device programming or simulation file, or any other related documentation //or information is prohibited for any other purpose, including, but not //limited to modification, reverse engineering, de-compiling, or use with //any other silicon devices, unless such use is explicitly licensed under //a separate agreement with Altera or a megafunction partner. Title to the //intellectual property, including patents, copyrights, trademarks, trade //secrets, or maskworks, embodied in any such megafunction design, netlist, //support information, device programming or simulation file, or any other //related documentation or information provided by Altera or a megafunction //partner, remains with Altera, the megafunction partner, or their respective //licensors. No other licenses, including any licenses needed under any third //party's intellectual property, are provided herein. module accum32 ( data, clock, clken, aclr, result)/* synthesis synthesis_clearbox = 1 */; input [31:0] data; input clock; input clken; input aclr; output [31:0] result; endmodule

// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2003 by Wilson Snyder. module t (/*AUTOARG*/ // Inputs fastclk ); input fastclk; t_netlist tnetlist (.also_fastclk (fastclk), /*AUTOINST*/ // Inputs .fastclk (fastclk)); endmodule module t_netlist (/*AUTOARG*/ // Inputs fastclk, also_fastclk ); // surefire lint_off ASWEMB input fastclk; input also_fastclk; integer _mode; initial _mode = 0; // This entire module should optimize to nearly nothing... // verilator lint_off UNOPTFLAT reg [4:0] a,a2,b,c,d,e; // verilator lint_on UNOPTFLAT initial a=5'd1; always @ (posedge fastclk) begin b <= a+5'd1; c <= b+5'd1; // Better for ordering if this moves before previous statement end // verilator lint_off UNOPT always @ (d or /*AS*/a or c) begin e = d+5'd1; a2 = a+5'd1; // This can be pulled out of the middle of the always d = c+5'd1; // Better for ordering if this moves before previous statement end // verilator lint_on UNOPT always @ (posedge also_fastclk) begin if (_mode==5) begin if (a2 != 5'd2) $stop; if (e != 5'd5) $stop; $write("*-* All Finished *-*\n"); $finish; end _mode <= _mode + 1; end endmodule

/* * Copyright 2020 The SkyWater PDK Authors * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * SPDX-License-Identifier: Apache-2.0 */ `ifndef SKY130_FD_SC_LP__FAHCON_FUNCTIONAL_V `define SKY130_FD_SC_LP__FAHCON_FUNCTIONAL_V /** * fahcon: Full adder, inverted carry in, inverted carry out. * * Verilog simulation functional model. */ `timescale 1ns / 1ps `default_nettype none `celldefine module sky130_fd_sc_lp__fahcon ( COUT_N, SUM , A , B , CI ); // Module ports output COUT_N; output SUM ; input A ; input B ; input CI ; // Local signals wire xor0_out_SUM ; wire a_b ; wire a_ci ; wire b_ci ; wire or0_out_coutn; // Name Output Other arguments xor xor0 (xor0_out_SUM , A, B, CI ); buf buf0 (SUM , xor0_out_SUM ); nor nor0 (a_b , A, B ); nor nor1 (a_ci , A, CI ); nor nor2 (b_ci , B, CI ); or or0 (or0_out_coutn, a_b, a_ci, b_ci); buf buf1 (COUT_N , or0_out_coutn ); endmodule `endcelldefine `default_nettype wire `endif // SKY130_FD_SC_LP__FAHCON_FUNCTIONAL_V

// ----------------------------------------------------------------------------- // -- -- // -- (C) 2016-2022 Revanth Kamaraj (krevanth) -- // -- -- // -- -------------------------------------------------------------------------- // -- -- // -- This program is free software; you can redistribute it and/or -- // -- modify it under the terms of the GNU General Public License -- // -- as published by the Free Software Foundation; either version 2 -- // -- of the License, or (at your option) any later version. -- // -- -- // -- This program is distributed in the hope that it will be useful, -- // -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- // -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- // -- GNU General Public License for more details. -- // -- -- // -- You should have received a copy of the GNU General Public License -- // -- along with this program; if not, write to the Free Software -- // -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -- // -- 02110-1301, USA. -- // -- -- // ----------------------------------------------------------------------------- // -- -- // -- Examines TLB entries to authorize access. Purely combo logic. -- // -- -- // ----------------------------------------------------------------------------- `default_nettype none module zap_tlb_check ( // ZAP TLB Processing Logic. i_mmu_en, // MMU enable. // Dynamics i_va, // Virtual address. i_rd, // WB rd. i_wr, // WB wr. // Static almost. i_cpsr, i_sr, i_dac_reg, // Data from TLB dist RAMs. i_sptlb_rdata, i_sptlb_rdav, i_lptlb_rdata, i_lptlb_rdav, i_setlb_rdata, i_setlb_rdav, i_fptlb_rdata, i_fptlb_rdav, // Outputs to other units. o_walk, // Need to page walk. o_fsr, // FSR. o_far, // FAR. 0 means no fault. This is a 4-bit number. o_cacheable, // Cacheable based on PTE. o_phy_addr // Physical address. ); // Pass this from top. parameter LPAGE_TLB_ENTRIES = 8; parameter SPAGE_TLB_ENTRIES = 8; parameter SECTION_TLB_ENTRIES = 8; parameter FPAGE_TLB_ENTRIES = 8; `include "zap_localparams.vh" `include "zap_defines.vh" `include "zap_functions.vh" input wire i_mmu_en; // MMU enable. input wire [31:0] i_va; // Virtual address. input wire i_rd; // Read request. input wire i_wr; // Write request. input wire [31:0] i_cpsr; // CPSR. input wire [1:0] i_sr; // Status Register. input wire [31:0] i_dac_reg; // Domain Access Control Register. input wire [`SPAGE_TLB_WDT -1:0] i_sptlb_rdata; // Small page TLB. input wire i_sptlb_rdav; // TLB entry valid. input wire [`LPAGE_TLB_WDT -1:0] i_lptlb_rdata; // Large page TLB read data. input wire i_lptlb_rdav; // Large page TLB valid. input wire [`SECTION_TLB_WDT-1:0] i_setlb_rdata; // Small page TLB read data. input wire i_setlb_rdav; // Small page TLB valid. input wire [`FPAGE_TLB_WDT-1:0] i_fptlb_rdata; // Fine page TLB read data. input wire i_fptlb_rdav; // Fine page TLB valid. output reg o_walk; // Signal page walk. output reg [7:0] o_fsr; // FSR. 0 means all OK. output reg [31:0] o_far; // Fault Address Register. output reg o_cacheable; // Cacheble stats of the PTE. output reg [31:0] o_phy_addr; // Physical address. // ---------------------------------------------------------------------------- always @* begin // Default values. Taken for MMU disabled esp. o_fsr = 0; // No fault. o_far = i_va; // Fault address. o_phy_addr = i_va; // VA = PA o_walk = 0; // Walk disabled. o_cacheable = 0; // Uncacheable. if ( i_mmu_en && (i_rd|i_wr) ) // MMU enabled. begin if ( (i_sptlb_rdata[`SPAGE_TLB__TAG] == i_va[`VA__SPAGE_TAG]) && i_sptlb_rdav ) begin // Entry found in small page TLB. o_fsr = get_fsr ( 1'd0, 1'd1, 1'd0, 1'd0, // Small page. i_va[`VA__SPAGE_AP_SEL], i_cpsr[4:0] == USR, i_rd, i_wr, i_sr, i_dac_reg, i_sptlb_rdata ) ; o_phy_addr = {i_sptlb_rdata[`SPAGE_TLB__BASE], i_va[11:0]}; o_cacheable = i_sptlb_rdata[`SECTION_TLB__CB] >> 1; end else if ( (i_lptlb_rdata[`LPAGE_TLB__TAG] == i_va[`VA__LPAGE_TAG]) && i_lptlb_rdav ) begin // Entry found in large page TLB. o_fsr = get_fsr ( 1'd0, 1'd0, 1'd1, 1'd0, // Large page. i_va[`VA__LPAGE_AP_SEL], i_cpsr[4:0] == USR, i_rd, i_wr, i_sr, i_dac_reg, i_lptlb_rdata ) ; o_phy_addr = {i_lptlb_rdata[`LPAGE_TLB__BASE], i_va[15:0]}; o_cacheable = i_lptlb_rdata[`LPAGE_TLB__CB] >> 1; end else if ( (i_setlb_rdata[`SECTION_TLB__TAG] == i_va[`VA__SECTION_TAG]) && i_setlb_rdav ) begin // Entry found in section TLB. o_fsr = get_fsr ( 1'd1, 1'd0, 1'd0, 1'd0, // Section. 2'd0, // DONT CARE. Sections do not further divisions in AP SEL. i_cpsr[4:0] == USR, i_rd, i_wr, i_sr, i_dac_reg, i_setlb_rdata ) ; o_phy_addr = {i_setlb_rdata[`SECTION_TLB__BASE], i_va[19:0]}; o_cacheable = i_setlb_rdata[`SECTION_TLB__CB] >> 1; end else if( (i_fptlb_rdata[`FPAGE_TLB__TAG] == i_va[`VA__FPAGE_TAG]) && i_fptlb_rdav ) begin // Entry found in fine page TLB. o_fsr = get_fsr ( 1'd0, 1'd0, 1'd0, 1'd1, 2'd0, i_cpsr[4:0] == USR, i_rd, i_wr, i_sr, i_dac_reg, i_fptlb_rdata ); end else begin // Trigger TLB walk. o_walk = 1'd1; end end // Else MMU disabled. end // ---------------------------------------------------------------------------- function [7:0] get_fsr ( // Return 0 means OK to access else is a valid FSR. input section, spage, lpage, fpage, // Select one. input [1:0] ap_sel, // AP sel bits. dont care for sections or fine pages. input user, rd, wr, // Access properties. input [1:0] sr, // S and R bits. input [31:0] dac_reg, // DAC register. input [63:0] tlb // TLB entry. ); reg [3:0] apsr; // Concat of AP and SR. reg [1:0] dac; // DAC bits. begin // Get AP and DAC. if ( section ) // section. begin apsr = (tlb [ `SECTION_TLB__AP ]); dac = (dac_reg >> (tlb [ `SECTION_TLB__DAC_SEL ] << 1)); end else if ( spage ) // small page. begin apsr = (tlb [ `SPAGE_TLB__AP ]) >> (ap_sel << 1); dac = (dac_reg >> (tlb [ `SPAGE_TLB__DAC_SEL ] << 1)); end else if ( fpage ) // fine page begin apsr = (tlb [ `FPAGE_TLB__AP ]); dac = (dac_reg >> (tlb [ `FPAGE_TLB__DAC_SEL ] << 1)); end else // large page. begin apsr = (tlb [ `LPAGE_TLB__AP ]) >> (ap_sel << 1); dac = (dac_reg >> (tlb [ `LPAGE_TLB__DAC_SEL ] << 1)); end // Concat AP and SR bits. apsr[3:2] = apsr[1:0]; apsr[1:0] = sr[1:0]; case(dac) DAC_MANAGER: get_fsr = 0; // No fault. DAC_CLIENT : get_fsr = is_apsr_ok ( user, rd, wr, apsr ) ? 0 : ( section ? {tlb[`SECTION_TLB__DAC_SEL], FSR_SECTION_PERMISSION_FAULT}: spage ? {tlb[`SPAGE_TLB__DAC_SEL] , FSR_PAGE_PERMISSION_FAULT }: fpage ? {tlb[`FPAGE_TLB__DAC_SEL] , FSR_PAGE_PERMISSION_FAULT }: {tlb[`LPAGE_TLB__DAC_SEL] , FSR_PAGE_PERMISSION_FAULT } ); default : get_fsr = section ? {tlb[`SECTION_TLB__DAC_SEL], FSR_SECTION_DOMAIN_FAULT} : spage ? {tlb[`SPAGE_TLB__DAC_SEL], FSR_PAGE_DOMAIN_FAULT } : fpage ? {tlb[`FPAGE_TLB__DAC_SEL], FSR_PAGE_DOMAIN_FAULT } : {tlb[`LPAGE_TLB__DAC_SEL], FSR_PAGE_DOMAIN_FAULT } ; endcase end endfunction // ---------------------------------------------------------------------------- // // Function to check APSR bits. // // Returns 0 for failure, 1 for okay. // Checks AP and SR bits. // localparam APSR_BAD = 1'd0; localparam APSR_OK = 1'd1; function is_apsr_ok ( input user, input rd, input wr, input [3:0] apsr); reg x; begin x = APSR_BAD; // Assume fail. casez (apsr) APSR_NA_NA: x = APSR_BAD; // No access. APSR_RO_RO: x = !wr; // Reads allowed for all. APSR_RO_NA: x = !user && rd; // Only kernel reads. APSR_RW_NA: x = !user; // Only kernel access. APSR_RW_RO: x = !user | (user && rd); // User RO, Kernel RW. APSR_RW_RW: x = APSR_OK; // Grant all the time. default : x = APSR_BAD; // Deny all the time. endcase // Assign to function. Return. is_apsr_ok = x; end endfunction endmodule // zap_tlb_check.v `default_nettype wire // ---------------------------------------------------------------------------- // EOF // ----------------------------------------------------------------------------

/* ---------------------------------------------------------------------------------- Copyright (c) 2013-2014 Embedded and Network Computing Lab. Open SSD Project Hanyang University All rights reserved. ---------------------------------------------------------------------------------- Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. All advertising materials mentioning features or use of this source code must display the following acknowledgement: This product includes source code developed by the Embedded and Network Computing Lab. and the Open SSD Project. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------------- http://enclab.hanyang.ac.kr/ http://www.openssd-project.org/ http://www.hanyang.ac.kr/ ---------------------------------------------------------------------------------- */ `timescale 1ns / 1ps module pcie_hcmd # ( parameter C_PCIE_DATA_WIDTH = 128, parameter C_PCIE_ADDR_WIDTH = 36 ) ( input pcie_user_clk, input pcie_user_rst_n, input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr, input [7:0] admin_sq_size, input [7:0] admin_cq_size, input [7:0] admin_sq_tail_ptr, input [7:0] io_sq1_tail_ptr, input [7:0] io_sq2_tail_ptr, input [7:0] io_sq3_tail_ptr, input [7:0] io_sq4_tail_ptr, input [7:0] io_sq5_tail_ptr, input [7:0] io_sq6_tail_ptr, input [7:0] io_sq7_tail_ptr, input [7:0] io_sq8_tail_ptr, input [7:0] cpld_sq_fifo_tag, input [C_PCIE_DATA_WIDTH-1:0] cpld_sq_fifo_wr_data, input cpld_sq_fifo_wr_en, input cpld_sq_fifo_tag_last, output tx_mrd_req, output [7:0] tx_mrd_tag, output [11:2] tx_mrd_len, output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr, input tx_mrd_req_ack, output [7:0] admin_cq_tail_ptr, output [7:0] io_cq1_tail_ptr, output [7:0] io_cq2_tail_ptr, output [7:0] io_cq3_tail_ptr, output [7:0] io_cq4_tail_ptr, output [7:0] io_cq5_tail_ptr, output [7:0] io_cq6_tail_ptr, output [7:0] io_cq7_tail_ptr, output [7:0] io_cq8_tail_ptr, output tx_cq_mwr_req, output [7:0] tx_cq_mwr_tag, output [11:2] tx_cq_mwr_len, output [C_PCIE_ADDR_WIDTH-1:2] tx_cq_mwr_addr, input tx_cq_mwr_req_ack, input tx_cq_mwr_rd_en, output [C_PCIE_DATA_WIDTH-1:0] tx_cq_mwr_rd_data, input tx_cq_mwr_data_last, input [7:0] hcmd_prp_rd_addr, output [44:0] hcmd_prp_rd_data, input hcmd_nlb_wr1_en, input [6:0] hcmd_nlb_wr1_addr, input [18:0] hcmd_nlb_wr1_data, output hcmd_nlb_wr1_rdy_n, input [6:0] hcmd_nlb_rd_addr, output [18:0] hcmd_nlb_rd_data, input hcmd_cq_wr0_en, input [34:0] hcmd_cq_wr0_data0, input [34:0] hcmd_cq_wr0_data1, output hcmd_cq_wr0_rdy_n, input cpu_bus_clk, input cpu_bus_rst_n, input [8:0] sq_rst_n, input [8:0] sq_valid, input [7:0] io_sq1_size, input [7:0] io_sq2_size, input [7:0] io_sq3_size, input [7:0] io_sq4_size, input [7:0] io_sq5_size, input [7:0] io_sq6_size, input [7:0] io_sq7_size, input [7:0] io_sq8_size, input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr, input [3:0] io_sq1_cq_vec, input [3:0] io_sq2_cq_vec, input [3:0] io_sq3_cq_vec, input [3:0] io_sq4_cq_vec, input [3:0] io_sq5_cq_vec, input [3:0] io_sq6_cq_vec, input [3:0] io_sq7_cq_vec, input [3:0] io_sq8_cq_vec, input [8:0] cq_rst_n, input [8:0] cq_valid, input [7:0] io_cq1_size, input [7:0] io_cq2_size, input [7:0] io_cq3_size, input [7:0] io_cq4_size, input [7:0] io_cq5_size, input [7:0] io_cq6_size, input [7:0] io_cq7_size, input [7:0] io_cq8_size, input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr, input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr, input hcmd_sq_rd_en, output [18:0] hcmd_sq_rd_data, output hcmd_sq_empty_n, input [10:0] hcmd_table_rd_addr, output [31:0] hcmd_table_rd_data, input hcmd_cq_wr1_en, input [34:0] hcmd_cq_wr1_data0, input [34:0] hcmd_cq_wr1_data1, output hcmd_cq_wr1_rdy_n ); wire w_hcmd_table_wr_en; wire [8:0] w_hcmd_table_wr_addr; wire [127:0] w_hcmd_table_wr_data; wire w_hcmd_cid_wr_en; wire [6:0] w_hcmd_cid_wr_addr; wire [19:0] w_hcmd_cid_wr_data; wire [6:0] w_hcmd_cid_rd_addr; wire [19:0] w_hcmd_cid_rd_data; wire w_hcmd_prp_wr_en; wire [7:0] w_hcmd_prp_wr_addr; wire [44:0] w_hcmd_prp_wr_data; wire w_hcmd_nlb_wr0_en; wire [6:0] w_hcmd_nlb_wr0_addr; wire [18:0] w_hcmd_nlb_wr0_data; wire w_hcmd_nlb_wr0_rdy_n; wire w_hcmd_slot_rdy; wire [6:0] w_hcmd_slot_tag; wire w_hcmd_slot_alloc_en; wire w_hcmd_slot_free_en; wire [6:0] w_hcmd_slot_invalid_tag; wire [7:0] w_admin_sq_head_ptr; wire [7:0] w_io_sq1_head_ptr; wire [7:0] w_io_sq2_head_ptr; wire [7:0] w_io_sq3_head_ptr; wire [7:0] w_io_sq4_head_ptr; wire [7:0] w_io_sq5_head_ptr; wire [7:0] w_io_sq6_head_ptr; wire [7:0] w_io_sq7_head_ptr; wire [7:0] w_io_sq8_head_ptr; pcie_hcmd_table pcie_hcmd_table_inst0( .wr_clk (pcie_user_clk), .wr_en (w_hcmd_table_wr_en), .wr_addr (w_hcmd_table_wr_addr), .wr_data (w_hcmd_table_wr_data), .rd_clk (cpu_bus_clk), .rd_addr (hcmd_table_rd_addr), .rd_data (hcmd_table_rd_data) ); pcie_hcmd_table_cid pcie_hcmd_table_cid_isnt0( .clk (pcie_user_clk), .wr_en (w_hcmd_cid_wr_en), .wr_addr (w_hcmd_cid_wr_addr), .wr_data (w_hcmd_cid_wr_data), .rd_addr (w_hcmd_cid_rd_addr), .rd_data (w_hcmd_cid_rd_data) ); pcie_hcmd_table_prp pcie_hcmd_table_prp_isnt0( .clk (pcie_user_clk), .wr_en (w_hcmd_prp_wr_en), .wr_addr (w_hcmd_prp_wr_addr), .wr_data (w_hcmd_prp_wr_data), .rd_addr (hcmd_prp_rd_addr), .rd_data (hcmd_prp_rd_data) ); pcie_hcmd_nlb pcie_hcmd_nlb_inst0 ( .clk (pcie_user_clk), .rst_n (pcie_user_rst_n), .wr0_en (w_hcmd_nlb_wr0_en), .wr0_addr (w_hcmd_nlb_wr0_addr), .wr0_data (w_hcmd_nlb_wr0_data), .wr0_rdy_n (w_hcmd_nlb_wr0_rdy_n), .wr1_en (hcmd_nlb_wr1_en), .wr1_addr (hcmd_nlb_wr1_addr), .wr1_data (hcmd_nlb_wr1_data), .wr1_rdy_n (hcmd_nlb_wr1_rdy_n), .rd_addr (hcmd_nlb_rd_addr), .rd_data (hcmd_nlb_rd_data) ); pcie_hcmd_slot_mgt pcie_hcmd_slot_mgt_inst0 ( .pcie_user_clk (pcie_user_clk), .pcie_user_rst_n (pcie_user_rst_n), .hcmd_slot_rdy (w_hcmd_slot_rdy), .hcmd_slot_tag (w_hcmd_slot_tag), .hcmd_slot_alloc_en (w_hcmd_slot_alloc_en), .hcmd_slot_free_en (w_hcmd_slot_free_en), .hcmd_slot_invalid_tag (w_hcmd_slot_invalid_tag) ); pcie_hcmd_sq # ( .C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH) ) pcie_hcmd_sq_inst0( .pcie_user_clk (pcie_user_clk), .pcie_user_rst_n (pcie_user_rst_n), .admin_sq_bs_addr (admin_sq_bs_addr), .admin_sq_size (admin_sq_size), .admin_sq_tail_ptr (admin_sq_tail_ptr), .io_sq1_tail_ptr (io_sq1_tail_ptr), .io_sq2_tail_ptr (io_sq2_tail_ptr), .io_sq3_tail_ptr (io_sq3_tail_ptr), .io_sq4_tail_ptr (io_sq4_tail_ptr), .io_sq5_tail_ptr (io_sq5_tail_ptr), .io_sq6_tail_ptr (io_sq6_tail_ptr), .io_sq7_tail_ptr (io_sq7_tail_ptr), .io_sq8_tail_ptr (io_sq8_tail_ptr), .admin_sq_head_ptr (w_admin_sq_head_ptr), .io_sq1_head_ptr (w_io_sq1_head_ptr), .io_sq2_head_ptr (w_io_sq2_head_ptr), .io_sq3_head_ptr (w_io_sq3_head_ptr), .io_sq4_head_ptr (w_io_sq4_head_ptr), .io_sq5_head_ptr (w_io_sq5_head_ptr), .io_sq6_head_ptr (w_io_sq6_head_ptr), .io_sq7_head_ptr (w_io_sq7_head_ptr), .io_sq8_head_ptr (w_io_sq8_head_ptr), .hcmd_slot_rdy (w_hcmd_slot_rdy), .hcmd_slot_tag (w_hcmd_slot_tag), .hcmd_slot_alloc_en (w_hcmd_slot_alloc_en), .cpld_sq_fifo_tag (cpld_sq_fifo_tag), .cpld_sq_fifo_wr_data (cpld_sq_fifo_wr_data), .cpld_sq_fifo_wr_en (cpld_sq_fifo_wr_en), .cpld_sq_fifo_tag_last (cpld_sq_fifo_tag_last), .tx_mrd_req (tx_mrd_req), .tx_mrd_tag (tx_mrd_tag), .tx_mrd_len (tx_mrd_len), .tx_mrd_addr (tx_mrd_addr), .tx_mrd_req_ack (tx_mrd_req_ack), .hcmd_table_wr_en (w_hcmd_table_wr_en), .hcmd_table_wr_addr (w_hcmd_table_wr_addr), .hcmd_table_wr_data (w_hcmd_table_wr_data), .hcmd_cid_wr_en (w_hcmd_cid_wr_en), .hcmd_cid_wr_addr (w_hcmd_cid_wr_addr), .hcmd_cid_wr_data (w_hcmd_cid_wr_data), .hcmd_prp_wr_en (w_hcmd_prp_wr_en), .hcmd_prp_wr_addr (w_hcmd_prp_wr_addr), .hcmd_prp_wr_data (w_hcmd_prp_wr_data), .hcmd_nlb_wr0_en (w_hcmd_nlb_wr0_en), .hcmd_nlb_wr0_addr (w_hcmd_nlb_wr0_addr), .hcmd_nlb_wr0_data (w_hcmd_nlb_wr0_data), .hcmd_nlb_wr0_rdy_n (w_hcmd_nlb_wr0_rdy_n), .cpu_bus_clk (cpu_bus_clk), .cpu_bus_rst_n (cpu_bus_rst_n), .sq_rst_n (sq_rst_n), .sq_valid (sq_valid), .io_sq1_size (io_sq1_size), .io_sq2_size (io_sq2_size), .io_sq3_size (io_sq3_size), .io_sq4_size (io_sq4_size), .io_sq5_size (io_sq5_size), .io_sq6_size (io_sq6_size), .io_sq7_size (io_sq7_size), .io_sq8_size (io_sq8_size), .io_sq1_bs_addr (io_sq1_bs_addr), .io_sq2_bs_addr (io_sq2_bs_addr), .io_sq3_bs_addr (io_sq3_bs_addr), .io_sq4_bs_addr (io_sq4_bs_addr), .io_sq5_bs_addr (io_sq5_bs_addr), .io_sq6_bs_addr (io_sq6_bs_addr), .io_sq7_bs_addr (io_sq7_bs_addr), .io_sq8_bs_addr (io_sq8_bs_addr), .hcmd_sq_rd_en (hcmd_sq_rd_en), .hcmd_sq_rd_data (hcmd_sq_rd_data), .hcmd_sq_empty_n (hcmd_sq_empty_n) ); pcie_hcmd_cq # ( .C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH) ) pcie_hcmd_cq_inst0( .pcie_user_clk (pcie_user_clk), .pcie_user_rst_n (pcie_user_rst_n), .hcmd_cid_rd_addr (w_hcmd_cid_rd_addr), .hcmd_cid_rd_data (w_hcmd_cid_rd_data), .admin_cq_bs_addr (admin_cq_bs_addr), .admin_cq_size (admin_cq_size), .admin_cq_tail_ptr (admin_cq_tail_ptr), .io_cq1_tail_ptr (io_cq1_tail_ptr), .io_cq2_tail_ptr (io_cq2_tail_ptr), .io_cq3_tail_ptr (io_cq3_tail_ptr), .io_cq4_tail_ptr (io_cq4_tail_ptr), .io_cq5_tail_ptr (io_cq5_tail_ptr), .io_cq6_tail_ptr (io_cq6_tail_ptr), .io_cq7_tail_ptr (io_cq7_tail_ptr), .io_cq8_tail_ptr (io_cq8_tail_ptr), .admin_sq_head_ptr (w_admin_sq_head_ptr), .io_sq1_head_ptr (w_io_sq1_head_ptr), .io_sq2_head_ptr (w_io_sq2_head_ptr), .io_sq3_head_ptr (w_io_sq3_head_ptr), .io_sq4_head_ptr (w_io_sq4_head_ptr), .io_sq5_head_ptr (w_io_sq5_head_ptr), .io_sq6_head_ptr (w_io_sq6_head_ptr), .io_sq7_head_ptr (w_io_sq7_head_ptr), .io_sq8_head_ptr (w_io_sq8_head_ptr), .hcmd_slot_free_en (w_hcmd_slot_free_en), .hcmd_slot_invalid_tag (w_hcmd_slot_invalid_tag), .tx_cq_mwr_req (tx_cq_mwr_req), .tx_cq_mwr_tag (tx_cq_mwr_tag), .tx_cq_mwr_len (tx_cq_mwr_len), .tx_cq_mwr_addr (tx_cq_mwr_addr), .tx_cq_mwr_req_ack (tx_cq_mwr_req_ack), .tx_cq_mwr_rd_en (tx_cq_mwr_rd_en), .tx_cq_mwr_rd_data (tx_cq_mwr_rd_data), .tx_cq_mwr_data_last (tx_cq_mwr_data_last), .hcmd_cq_wr0_en (hcmd_cq_wr0_en), .hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0), .hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1), .hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n), .cpu_bus_clk (cpu_bus_clk), .cpu_bus_rst_n (cpu_bus_rst_n), .io_sq1_cq_vec (io_sq1_cq_vec), .io_sq2_cq_vec (io_sq2_cq_vec), .io_sq3_cq_vec (io_sq3_cq_vec), .io_sq4_cq_vec (io_sq4_cq_vec), .io_sq5_cq_vec (io_sq5_cq_vec), .io_sq6_cq_vec (io_sq6_cq_vec), .io_sq7_cq_vec (io_sq7_cq_vec), .io_sq8_cq_vec (io_sq8_cq_vec), .sq_valid (sq_valid), .cq_rst_n (cq_rst_n), .cq_valid (cq_valid), .io_cq1_size (io_cq1_size), .io_cq2_size (io_cq2_size), .io_cq3_size (io_cq3_size), .io_cq4_size (io_cq4_size), .io_cq5_size (io_cq5_size), .io_cq6_size (io_cq6_size), .io_cq7_size (io_cq7_size), .io_cq8_size (io_cq8_size), .io_cq1_bs_addr (io_cq1_bs_addr), .io_cq2_bs_addr (io_cq2_bs_addr), .io_cq3_bs_addr (io_cq3_bs_addr), .io_cq4_bs_addr (io_cq4_bs_addr), .io_cq5_bs_addr (io_cq5_bs_addr), .io_cq6_bs_addr (io_cq6_bs_addr), .io_cq7_bs_addr (io_cq7_bs_addr), .io_cq8_bs_addr (io_cq8_bs_addr), .hcmd_cq_wr1_en (hcmd_cq_wr1_en), .hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0), .hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1), .hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n) ); endmodule

/////////////////////////////////////////////////////////////////////////////// // // File name: axi_protocol_converter_v2_1_9_b2s_wrap_cmd.v // /////////////////////////////////////////////////////////////////////////////// `timescale 1ps/1ps `default_nettype none (* DowngradeIPIdentifiedWarnings="yes" *) module axi_protocol_converter_v2_1_9_b2s_wrap_cmd # ( /////////////////////////////////////////////////////////////////////////////// // Parameter Definitions /////////////////////////////////////////////////////////////////////////////// // Width of AxADDR // Range: 32. parameter integer C_AXI_ADDR_WIDTH = 32 ) ( /////////////////////////////////////////////////////////////////////////////// // Port Declarations /////////////////////////////////////////////////////////////////////////////// input wire clk , input wire reset , input wire [C_AXI_ADDR_WIDTH-1:0] axaddr , input wire [7:0] axlen , input wire [2:0] axsize , // axhandshake = axvalid & axready input wire axhandshake , output wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr , // Connections to/from fsm module // signal to increment to the next mc transaction input wire next , // signal to the fsm there is another transaction required output reg next_pending ); //////////////////////////////////////////////////////////////////////////////// // Wire and register declarations //////////////////////////////////////////////////////////////////////////////// reg sel_first; wire [11:0] axaddr_i; wire [3:0] axlen_i; reg [11:0] wrap_boundary_axaddr; reg [3:0] axaddr_offset; reg [3:0] wrap_second_len; reg [11:0] wrap_boundary_axaddr_r; reg [3:0] axaddr_offset_r; reg [3:0] wrap_second_len_r; reg [4:0] axlen_cnt; reg [4:0] wrap_cnt_r; wire [4:0] wrap_cnt; reg [11:0] axaddr_wrap; reg next_pending_r; localparam L_AXI_ADDR_LOW_BIT = (C_AXI_ADDR_WIDTH >= 12) ? 12 : 11; //////////////////////////////////////////////////////////////////////////////// // BEGIN RTL //////////////////////////////////////////////////////////////////////////////// generate if (C_AXI_ADDR_WIDTH > 12) begin : ADDR_GT_4K assign cmd_byte_addr = (sel_first) ? axaddr : {axaddr[C_AXI_ADDR_WIDTH-1:L_AXI_ADDR_LOW_BIT],axaddr_wrap[11:0]}; end else begin : ADDR_4K assign cmd_byte_addr = (sel_first) ? axaddr : axaddr_wrap[11:0]; end endgenerate assign axaddr_i = axaddr[11:0]; assign axlen_i = axlen[3:0]; // Mask bits based on transaction length to get wrap boundary low address // Offset used to calculate the length of each transaction always @( * ) begin if(axhandshake) begin wrap_boundary_axaddr = axaddr_i & ~(axlen_i << axsize[1:0]); axaddr_offset = axaddr_i[axsize[1:0] +: 4] & axlen_i; end else begin wrap_boundary_axaddr = wrap_boundary_axaddr_r; axaddr_offset = axaddr_offset_r; end end // case (axsize[1:0]) // 2'b00 : axaddr_offset = axaddr_i[4:0] & axlen_i; // 2'b01 : axaddr_offset = axaddr_i[5:1] & axlen_i; // 2'b10 : axaddr_offset = axaddr_i[6:2] & axlen_i; // 2'b11 : axaddr_offset = axaddr_i[7:3] & axlen_i; // default : axaddr_offset = axaddr_i[7:3] & axlen_i; // endcase // The first and the second command from the wrap transaction could // be of odd length or even length with address offset. This will be // an issue with BL8, extra transactions have to be issued. // Rounding up the length to account for extra transactions. always @( * ) begin if(axhandshake) begin wrap_second_len = (axaddr_offset >0) ? axaddr_offset - 1 : 0; end else begin wrap_second_len = wrap_second_len_r; end end // registering to be used in the combo logic. always @(posedge clk) begin wrap_boundary_axaddr_r <= wrap_boundary_axaddr; axaddr_offset_r <= axaddr_offset; wrap_second_len_r <= wrap_second_len; end // determining if extra data is required for even offsets // wrap_cnt used to switch the address for first and second transaction. assign wrap_cnt = {1'b0, wrap_second_len + {3'b000, (|axaddr_offset)}}; always @(posedge clk) wrap_cnt_r <= wrap_cnt; always @(posedge clk) begin if (axhandshake) begin axaddr_wrap <= axaddr[11:0]; end if(next)begin if(axlen_cnt == wrap_cnt_r) begin axaddr_wrap <= wrap_boundary_axaddr_r; end else begin axaddr_wrap <= axaddr_wrap + (1 << axsize[1:0]); end end end // Even numbber of transactions with offset, inc len by 2 for BL8 always @(posedge clk) begin if (axhandshake)begin axlen_cnt <= axlen_i; next_pending_r <= axlen_i >= 1; end else if (next) begin if (axlen_cnt > 1) begin axlen_cnt <= axlen_cnt - 1; next_pending_r <= (axlen_cnt - 1) >= 1; end else begin axlen_cnt <= 5'd0; next_pending_r <= 1'b0; end end end always @( * ) begin if (axhandshake)begin next_pending = axlen_i >= 1; end else if (next) begin if (axlen_cnt > 1) begin next_pending = (axlen_cnt - 1) >= 1; end else begin next_pending = 1'b0; end end else begin next_pending = next_pending_r; end end // last and ignore signals to data channel. These signals are used for // BL8 to ignore and insert data for even len transactions with offset // and odd len transactions // For odd len transactions with no offset the last read is ignored and // last write is masked // For odd len transactions with offset the first read is ignored and // first write is masked // For even len transactions with offset the last & first read is ignored and // last& first write is masked // For even len transactions no ingnores or masks. // Indicates if we are on the first transaction of a mc translation with more // than 1 transaction. always @(posedge clk) begin if (reset | axhandshake) begin sel_first <= 1'b1; end else if (next) begin sel_first <= 1'b0; end end endmodule `default_nettype wire

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 01/27/2015 03:47:45 PM // Design Name: // Module Name: wildcard_processer // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module wildcard_processor #(parameter NUM_OUTPUT_QUEUES = 8, parameter DATA_WIDTH = 64, parameter CTRL_WIDTH = DATA_WIDTH/8, parameter RESULT_WIDTH = `OPENFLOW_ACTION_WIDTH, parameter CURRENT_TABLE_ID = 0, parameter TABLE_NUM=2 ) ( input [RESULT_WIDTH-1:0] result_fifo_dout, output reg result_fifo_rd_en, input result_fifo_empty, input [CTRL_WIDTH-1:0] in_fifo_ctrl, input [DATA_WIDTH-1:0] in_fifo_data, output reg in_fifo_rd_en, input in_fifo_empty, output reg [DATA_WIDTH-1:0] out_data, output reg [CTRL_WIDTH-1:0] out_ctrl, output reg out_wr, input out_rdy, input wildcard_hit_dout, output reg actions_en, output reg actions_hit, output reg [`OPENFLOW_ACTION_WIDTH-1:0] actions, input clk, input reset, output reg [3:0] src_port, input skip_lookup ); reg [DATA_WIDTH-1:0] out_data_d1; reg [CTRL_WIDTH-1:0] out_ctrl_d1; reg [DATA_WIDTH-1:0] out_data_d2; reg [CTRL_WIDTH-1:0] out_ctrl_d2; reg out_wr_d1; reg out_wr_d2; reg out_wr_d3; // assign out_data_d1=in_fifo_data; // assign out_ctrl_d1=in_fifo_ctrl; always@(posedge clk) actions_hit<=wildcard_hit_dout; always@(posedge clk) begin out_data_d1<=in_fifo_data; out_ctrl_d1<=in_fifo_ctrl; out_data_d2<=out_data_d1; out_ctrl_d2<=out_ctrl_d1; out_data<=out_data_d2; out_ctrl<=out_ctrl_d2; out_wr_d1<=in_fifo_rd_en; out_wr_d2<=out_wr_d1; out_wr_d3<=out_wr_d2; out_wr<=out_wr_d3; end reg [`OPENFLOW_NEXT_TABLE_ID_WIDTH-1:0] pkt_dst_table_id; reg [5:0]cur_st,nxt_st; always@(posedge clk) if(reset) cur_st<=0; else cur_st<=nxt_st; localparam IDLE=0, WAIT_FOR_ACTION=1, READ_ACTION=2, READ_HEAD=3, READ_DATA=4, WAIT_EOP=5; always@(*) begin nxt_st=cur_st; case(cur_st) IDLE: nxt_st=WAIT_FOR_ACTION; WAIT_FOR_ACTION: if(!result_fifo_empty) nxt_st=READ_ACTION; READ_ACTION: nxt_st=READ_HEAD; READ_HEAD: if(out_rdy) nxt_st=READ_DATA; READ_DATA: if(in_fifo_ctrl==0 && out_rdy) nxt_st=WAIT_EOP; WAIT_EOP: if(in_fifo_ctrl!=0 && out_rdy) nxt_st=IDLE; default:nxt_st=IDLE; endcase end always@(*) begin result_fifo_rd_en=0; in_fifo_rd_en=0; if(cur_st==READ_ACTION) result_fifo_rd_en=out_rdy; else if(cur_st==READ_HEAD) in_fifo_rd_en=out_rdy; else if(cur_st==READ_DATA) in_fifo_rd_en=out_rdy; else if(cur_st==WAIT_EOP) begin if(in_fifo_ctrl!=0) in_fifo_rd_en=0; else in_fifo_rd_en=out_rdy; end end always@(posedge clk) if(reset) src_port<=0; else// if(cur_st==READ_HEAD) if(in_fifo_ctrl==`IO_QUEUE_STAGE_NUM) src_port<=in_fifo_data[`IOQ_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1 : `IOQ_SRC_PORT_POS] ; always@(posedge clk) if(reset) actions<=0; else if(cur_st==READ_DATA) actions<= result_fifo_dout; always@(posedge clk) if(reset) actions_en<=0; else if(in_fifo_ctrl==`IO_QUEUE_STAGE_NUM) begin if(in_fifo_data[`IOQ_DST_TABLE_ID_POS+8-1:`IOQ_DST_TABLE_ID_POS]==CURRENT_TABLE_ID) actions_en<=1; else actions_en<=0; end else if(cur_st==IDLE) actions_en<=0; endmodule