VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation Paper • 2504.15659 • Published Apr 22
Improving Assembly Code Performance with Large Language Models via Reinforcement Learning Paper • 2505.11480 • Published 24 days ago • 8
SATBench: Benchmarking LLMs' Logical Reasoning via Automated Puzzle Generation from SAT Formulas Paper • 2505.14615 • Published 20 days ago • 1