Dataset Viewer
source
string | id
string | file
string | content
string | metadata
dict |
|---|---|---|---|---|
shailja_vgen
|
vgen_0
|
prompts-and-testbenches/test_ex.v
|
// This is a RAM module
module ram #(
parameter ADDR_WIDTH=6,
parameter DATA_WIDTH=8
) (
input [DATA_WIDTH-1:0] data,
input [ADDR_WIDTH-1:0] addr,
input we, clk,
output reg [DATA_WIDTH-1:0] q
);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we)
ram[addr] <= data; // write data to RAM at address addr when we is high
q <= ram[addr]; // assign the RAM value at address addr to q
end
endmodule
|
{
"file_size": 496,
"has_module": true,
"has_testbench": false,
"lines": 20
}
|
shailja_vgen
|
vgen_1
|
prompts-and-testbenches/basic1/prompt3_wire_assign.v
|
// This is a module that assigns the output to the input
module wire_assign( input in, output out );
// assign the output out to the input in
|
{
"file_size": 141,
"has_module": true,
"has_testbench": false,
"lines": 3
}
|
shailja_vgen
|
vgen_2
|
prompts-and-testbenches/basic1/answer_wire_assign.v
|
// Create a module with one input and one output that behaves like a wire
module wire_assign( input in, output out );
// assign out to in
assign out = in;
endmodule
|
{
"file_size": 173,
"has_module": true,
"has_testbench": false,
"lines": 6
}
|
shailja_vgen
|
vgen_3
|
prompts-and-testbenches/basic1/prompt1_wire_assign.v
|
// This is a module that assigns the output to the input
module wire_assign( input in, output out );
|
{
"file_size": 100,
"has_module": true,
"has_testbench": false,
"lines": 2
}
|
shailja_vgen
|
vgen_4
|
prompts-and-testbenches/basic1/prompt2_wire_assign.v
|
// This is a module that assigns the output to the input
module wire_assign( input in, output out );
// assign the output to the input
|
{
"file_size": 134,
"has_module": true,
"has_testbench": false,
"lines": 3
}
|
shailja_vgen
|
vgen_5
|
prompts-and-testbenches/basic1/tb_wire_assign.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_wire_assign;
reg in;
wire out;
// duration for each bit = 2 * timescale = 2 * 1 ns = 2ns
localparam period = 2;
wire_assign UUT (.in(in), .out(out) );
initial // initial block executes only once
begin
// values for inputs
in = 0;
#period; // wait for period
if (out!==0) begin
$display("test 1 failed");
$finish;
end
else $display("in = %b , out = %b", in, out);
in = 1;
#period; // wait for period
if (out!==1) begin
$display("test 2 failed");
$finish;
end
else $display("in = %b , out = %b", in, out);
in = 0;
#period; // wait for period
if (out!==0) begin
$display("test 3 failed");
$finish;
end
else $display("in = %b , out = %b", in, out);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 1142,
"has_module": true,
"has_testbench": false,
"lines": 46
}
|
shailja_vgen
|
vgen_6
|
prompts-and-testbenches/intermediate2/answer_counter.v
|
// Design a counter that counts from 1 to 12
module counter(
input clk,
input reset,
output [3:0] q
);
reg q;
always @ (posedge clk) begin
if (reset) q <= 4'd1;
else if (q == 4'd12) q<= 4'd1;
else q <= q+4'd1;
end
endmodule
|
{
"file_size": 277,
"has_module": true,
"has_testbench": false,
"lines": 17
}
|
shailja_vgen
|
vgen_7
|
prompts-and-testbenches/intermediate2/prompt1_counter.v
|
// This is a counter that counts from 1 to 12
module counter(
input clk,
input reset,
output reg [3:0] q
);
|
{
"file_size": 109,
"has_module": true,
"has_testbench": false,
"lines": 6
}
|
shailja_vgen
|
vgen_8
|
prompts-and-testbenches/intermediate2/prompt2_counter.v
|
// This is a counter that counts from 1 to 12
module counter(
input clk,
input reset,
output reg [3:0] q
);
// update q on the positive edge of the clock
// q increments by 1 from 1 to 12
|
{
"file_size": 190,
"has_module": true,
"has_testbench": false,
"lines": 8
}
|
shailja_vgen
|
vgen_9
|
prompts-and-testbenches/intermediate2/prompt3_counter.v
|
// This is a counter that counts from 1 to 12
module counter(
input clk,
input reset,
output reg [3:0] q
);
// update q on the positive edge of the clock according to the following cases:
// on reset, assign q to 1
// else if q is 12, assign q to 1
// else, increment q by 1
|
{
"file_size": 277,
"has_module": true,
"has_testbench": false,
"lines": 10
}
|
shailja_vgen
|
vgen_10
|
prompts-and-testbenches/intermediate2/tb_counter.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_counter;
reg clk, reset;
wire [3:0] q;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
counter UUT (.clk(clk), .reset(reset), .q(q) );
initial // Clock generation
begin
clk = 0;
forever begin
#(period/2);
clk = ~clk;
end
end
initial begin
#2;
// check reset
reset = 1;
#period;
if(q!==1) begin
$display("test 1 failed");
$finish;
end
else $display("clk=%b, reset=%b, q=%b",clk,reset, q);
// check value does not change during reset
#period;
if(q!==1) begin
$display("test 1a failed");
$finish;
end
else $display("clk=%b, reset=%b, q=%b",clk,reset, q);
// start counter
reset = 0;
#period;
if(q!==2) begin
$display("test 2 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==3) begin
$display("test 3 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==4) begin
$display("test 4 failed");
//$finish;
end
else $display("q=%b",q);
#period;
if(q!==5) begin
$display("test 5 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==6) begin
$display("test 6 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==7) begin
$display("test 7 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==8) begin
$display("test 8 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==9) begin
$display("test 9 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==10) begin
$display("test 10 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==11) begin
$display("test 11 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==12) begin
$display("test 12 failed");
$finish;
end
else $display("q=%b",q);
// counter should go back to 1
#period;
if(q!==1) begin
$display("test 13 failed");
$finish;
end
else $display("q=%b",q);
// check reset after a few cycles
#period;
if(q!==2) begin
$display("test 14 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==3) begin
$display("test 15 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==4) begin
$display("test 16 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5) begin
$display("test 17 failed");
$finish;
end
else $display("q=%b",q);
reset = 1;
#period;
if(q!==1) begin
$display("test 18 failed");
$finish;
end
else $display("q=%b",q);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 3647,
"has_module": true,
"has_testbench": false,
"lines": 174
}
|
shailja_vgen
|
vgen_11
|
prompts-and-testbenches/intermediate5/prompt1_shift-left-rotate.v
|
// This is a shift left and rotate operation
module left_rotate(input clk,input reset,input [2:0] amount,input [7:0] data,input load,output reg [7:0] out);
|
{
"file_size": 155,
"has_module": true,
"has_testbench": false,
"lines": 2
}
|
shailja_vgen
|
vgen_12
|
prompts-and-testbenches/intermediate5/prompt2_shift-left-rotate.v
|
// This is a shift left and rotate operation
module left_rotate(input clk,input reset,input [2:0] amount,input [7:0] data,input load,output reg [7:0] out);
// when load is high, load data to out
// shift left and rotate the register out by amount bits
|
{
"file_size": 251,
"has_module": true,
"has_testbench": false,
"lines": 4
}
|
shailja_vgen
|
vgen_13
|
prompts-and-testbenches/intermediate5/prompt3_shift-left-rotate.v
|
// This is a shift left and rotate operation
module left_rotate(input clk,input reset,input [2:0] amount,input [7:0] data,input load,output reg [7:0] out);
// when load is high, load data to out
// when load is low, shift left and rotate the register out by amount bits
|
{
"file_size": 269,
"has_module": true,
"has_testbench": false,
"lines": 4
}
|
shailja_vgen
|
vgen_14
|
prompts-and-testbenches/intermediate5/tb_shift-left-rotate.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_left_rotate;
reg clk, load;
reg [2:0] amount;
reg [7:0] data;
wire [7:0] out;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
left_rotate UUT (.clk(clk), .load(load), .amount(amount), .data(data), .out(out) );
initial // Clock generation
begin
clk = 0;
forever begin
#(period/2);
clk = ~clk;
end
end
initial begin
// load data (load not enabled, should not load)
data = 8'hff;
load = 0;
amount = 0;
#period;
if(out===8'hff) begin
$display("test 1 failed");
$finish;
end
else $display("load =%b, amount = %b, out=%b",load,amount, out);
// enable load
data = 8'haa;
load = 1;
amount = 0;
#period;
if(out!==8'haa) begin
$display("test 2 failed");
$finish;
end
else $display("load =%b, amount = %b, out=%b",load,amount, out);
// enable load, amount should not make a difference
data = 8'h01;
load = 1;
amount = 2;
#period;
if(out!==8'h01) begin
$display("test 3 failed");
$finish;
end
else $display("load =%b, amount = %b, out=%b",load,amount, out);
// shift
load = 0;
amount = 1;
#period;
if(out!==8'h02) begin
$display("test 4 failed");
$finish;
end
else $display("load =%b, amount = %b, out=%b",load,amount, out);
amount = 2;
#period;
if(out!==8'h08) begin
$display("test 5 failed");
$finish;
end
else $display("load =%b, amount = %b, out=%b",load,amount, out);
amount = 3;
#period;
if(out!==8'h40) begin
$display("test 6 failed");
$finish;
end
else $display("load =%b, amount = %b, out=%b",load,amount, out);
amount = 4;
#period;
if(out!==8'h04) begin
$display("test 7 failed");
$finish;
end
else $display("load =%b, amount = %b, out=%b",load,amount, out);
amount = 5;
#period;
if(out!==8'h80) begin
$display("test 8 failed");
$finish;
end
else $display("load =%b, amount = %b, out=%b",load,amount, out);
amount = 6;
#period;
if(out!==8'h20) begin
$display("test 9 failed");
$finish;
end
else $display("load =%b, amount = %b, out=%b",load,amount, out);
amount = 7;
#period;
if(out!==8'h10) begin
$display("test 10 failed");
$finish;
end
else $display("load =%b, amount = %b, out=%b",load,amount, out);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 3015,
"has_module": true,
"has_testbench": false,
"lines": 116
}
|
shailja_vgen
|
vgen_15
|
prompts-and-testbenches/intermediate5/answer_shift-left-rotate.v
|
// This is a shift left and rotate operation
module left_rotate(input clk,input reset,input [2:0] amount,input [7:0] data,input load,output reg [7:0] out);
// when load is high, load data to out
// shift left and rotate the register out by amount bits
always@(posedge clk) begin
if (load)
out <= data;
else begin
case (amount)
0:out<=out;
1:out<={out[6:0],out[7]};
2:out<={out[5:0],out[7:6]};
3:out<={out[4:0],out[7:5]};
4:out<={out[3:0],out[7:4]};
5:out<={out[2:0],out[7:3]};
6:out<={out[1:0],out[7:2]};
7:out<={out[0],out[7:1]};
endcase
end
end
endmodule
|
{
"file_size": 659,
"has_module": true,
"has_testbench": false,
"lines": 24
}
|
shailja_vgen
|
vgen_16
|
prompts-and-testbenches/intermediate4/answer_simple-fsm.v
|
// This is a Moore state machine with two states 0 and 1, one input in, and one output out.
// Reset state is 0. Output is high in state 0. If in is low, state changes.
module simple_fsm(input clk, input reset, input in, output out);
reg present_state, next_state;
// In state 0, if in=1, stay in state 0. In state 0, if in=0, go to state 1
// In state 1, if in=1, stay in state 1. In state 1, if in=0, go to state 0
// out=1 in state 0 and out=0 in state 1
always @(posedge clk) begin
if (reset) begin
present_state <= 0;
end
else begin
// State flip-flops
present_state <= next_state;
end
end
always @(present_state,in) begin
case (present_state)
// next state logic
0: begin
if(in) next_state <= 0;
else next_state <= 1;
end
1: begin
if(in) next_state <= 1;
else next_state <= 0;
end
endcase
end
// output logic
assign out = present_state?0:1;
endmodule
|
{
"file_size": 1065,
"has_module": true,
"has_testbench": false,
"lines": 38
}
|
shailja_vgen
|
vgen_17
|
prompts-and-testbenches/intermediate4/prompt1_simple-fsm.v
|
// This is a Moore state machine with two states 0 and 1, one input in, and one output out.
// Reset state is 0. Output is high in state 0. If in is low, state changes.
module simple_fsm(input clk, input reset, input in, output out);
reg present_state, next_state;
|
{
"file_size": 266,
"has_module": true,
"has_testbench": false,
"lines": 5
}
|
shailja_vgen
|
vgen_18
|
prompts-and-testbenches/intermediate4/tb_simple-fsm.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_simple_fsm;
reg clk, reset, in;
wire out;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
simple_fsm UUT (.clk(clk), .reset(reset), .in(in), .out(out) );
initial // Clock generation
begin
clk = 0;
forever begin
#(period/2);
clk = ~clk;
end
end
initial begin
#2;
// check reset
reset = 1; in = 0;
#period;
// goes to state 0
if(out!==1) begin
$display("test 1 failed");
$finish;
end
else $display("clk=%b, reset=%b, in=%b, out=%b",clk,reset, in,out);
// start fsm
reset = 0;
in = 0;
#period;
// goes to state 1
if(out!==0) begin
$display("test 2 failed");
$finish;
end
else $display("clk=%b, reset=%b, in=%b, out=%b",clk,reset, in,out);
in = 0;
#period;
// goes to state 0
if(out!==1) begin
$display("test 3 failed");
$finish;
end
else $display("clk=%b, reset=%b, in=%b, out=%b",clk,reset, in,out);
in = 1;
#period;
// stays in state 0
if(out!==1) begin
$display("test 4 failed");
$finish;
end
else $display("clk=%b, reset=%b, in=%b, out=%b",clk,reset, in,out);
in = 0;
#period;
// goes to state 1
if(out!==0) begin
$display("test 5 failed");
$finish;
end
else $display("clk=%b, reset=%b, in=%b, out=%b",clk,reset, in,out);
in = 1;
#period;
// stays in state 1
if(out!==0) begin
$display("test 6 failed");
$finish;
end
else $display("clk=%b, reset=%b, in=%b, out=%b",clk,reset, in,out);
// check reset again
reset = 1; in = 1;
#period;
// goes to state 0
if(out!==1) begin
$display("test 7 failed");
$finish;
end
else $display("clk=%b, reset=%b, in=%b, out=%b",clk,reset, in,out);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 2314,
"has_module": true,
"has_testbench": false,
"lines": 98
}
|
shailja_vgen
|
vgen_19
|
prompts-and-testbenches/intermediate4/prompt3_simple-fsm.v
|
// This is a Moore state machine with two states 0 and 1, one input in, and one output out.
// Reset state is 0. Output is high in state 0. If in is low, state changes.
module simple_fsm(input clk, input reset, input in, output out);
reg present_state, next_state;
// In state 0, if in=1, stay in state 0. In state 0, if in=0, go to state 1
// In state 1, if in=1, stay in state 1. In state 1, if in=0, go to state 0
// out=1 in state 0 and out=0 in state 1
|
{
"file_size": 458,
"has_module": true,
"has_testbench": false,
"lines": 7
}
|
shailja_vgen
|
vgen_20
|
prompts-and-testbenches/intermediate4/prompt2_simple-fsm.v
|
// This is a Moore state machine with two states 0 and 1, one input in, and one output out.
// Reset state is 0. Output is high in state 0. If in is low, state changes.
module simple_fsm(input clk, input reset, input in, output out);
reg present_state, next_state;
// Output out is high only in state 0, it is low otherwise
// state toggles when input in is low. state does not change when input in is high
|
{
"file_size": 407,
"has_module": true,
"has_testbench": false,
"lines": 6
}
|
shailja_vgen
|
vgen_21
|
prompts-and-testbenches/intermediate3/tb_lfsr.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_lfsr;
reg clk, reset;
wire [4:0] q;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
lfsr UUT (.clk(clk), .reset(reset), .q(q) );
initial // Clock generation
begin
clk = 0;
forever begin
#(period/2);
clk = ~clk;
end
end
initial begin
#2;
// check reset
reset = 1;
#period;
if(q!==1) begin
$display("test 1 failed");
$finish;
end
else $display("clk=%b, reset=%b, q=%b",clk,reset, q);
// check value does not change during reset
#period;
if(q!==1) begin
$display("test 1a failed");
$finish;
end
else $display("clk=%b, reset=%b, q=%b",clk,reset, q);
// start counter
reset = 0;
#period;
if(q!==5'b10000) begin
$display("test 2 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5'b11000) begin
$display("test 3 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5'b11100) begin
$display("test 4 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5'b01110) begin
$display("test 5 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5'b10111) begin
$display("test 6 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5'b11011) begin
$display("test 7 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5'b01101) begin
$display("test 8 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5'b00110) begin
$display("test 9 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5'b10011) begin
$display("test 10 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5'b01001) begin
$display("test 11 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5'b10100) begin
$display("test 12 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5'b01010) begin
$display("test 13 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5'b00101) begin
$display("test 14 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5'b00010) begin
$display("test 15 failed");
$finish;
end
else $display("q=%b",q);
#period;
if(q!==5'b00001) begin
$display("test 16 failed");
$finish;
end
else $display("q=%b",q);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 3335,
"has_module": true,
"has_testbench": false,
"lines": 155
}
|
shailja_vgen
|
vgen_22
|
prompts-and-testbenches/intermediate3/prompt2_lfsr.v
|
// This is a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3
module lfsr(
input clk,
input reset,
output [4:0] q
);
reg [4:0] r_reg;
wire [4:0] r_next;
wire feedback_value;
// r_reg is reset to 1 and is updated to r_next otherwise
// feedback_value is concatenated with r_next for the update
|
{
"file_size": 313,
"has_module": true,
"has_testbench": false,
"lines": 11
}
|
shailja_vgen
|
vgen_23
|
prompts-and-testbenches/intermediate3/answer_lfsr.v
|
// Design a 5-bit maximal-length Galois LFSR with taps at bit positions 5 , 3 and 1
// https://verilogguide.readthedocs.io/en/latest/verilog/designs.html
module lfsr(
input clk,
input reset,
output [4:0] q
);
reg [4:0] r_reg;
wire [4:0] r_next;
wire feedback_value;
always @(posedge clk, posedge reset)
begin
if (reset)
begin
// set initial value to 1
r_reg <= 1;
end
else if (clk == 1'b1)
r_reg <= r_next;
end
assign feedback_value =r_reg[4] ^ r_reg[2] ^ r_reg[0];
assign r_next = {feedback_value, r_reg[4:1]};
assign q = r_reg;
endmodule
|
{
"file_size": 613,
"has_module": true,
"has_testbench": false,
"lines": 29
}
|
shailja_vgen
|
vgen_24
|
prompts-and-testbenches/intermediate3/prompt1_lfsr.v
|
// This is a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3
module lfsr(
input clk,
input reset,
output [4:0] q
);
reg [4:0] r_reg;
wire [4:0] r_next;
wire feedback_value;
|
{
"file_size": 194,
"has_module": true,
"has_testbench": false,
"lines": 9
}
|
shailja_vgen
|
vgen_25
|
prompts-and-testbenches/intermediate3/prompt3_lfsr.v
|
// This is a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3
module lfsr(
input clk,
input reset,
output [4:0] q
);
reg [4:0] r_reg;
wire [4:0] r_next;
wire feedback_value;
// on reset set the value of r_reg to 1
// otherwise assign r_next to r_reg
// assign the xor of bit positions 2 and 4 of r_reg to feedback_value
// concatenate feedback value with 4 MSBs of r_reg and assign it to r_next
// assign r_reg to the output q
|
{
"file_size": 447,
"has_module": true,
"has_testbench": false,
"lines": 14
}
|
shailja_vgen
|
vgen_26
|
prompts-and-testbenches/advanced5/prompt1_abro.v
|
// This is an ABRO FSM.
// It outputs 1 when 1 is received for signals a and b irrespetive of their order, either simultaneously or non-simultaneously.
module abro(
input clk,
input reset,
input a,
input b,
output z );
parameter IDLE = 0,
SA = 1,
SB = 2,
SAB = 3;
reg [1:0] cur_state,next_state;
|
{
"file_size": 299,
"has_module": true,
"has_testbench": false,
"lines": 13
}
|
shailja_vgen
|
vgen_27
|
prompts-and-testbenches/advanced5/prompt3_abro.v
|
// This is an FSM
// It outputs 1 when 1 is received for signals a and b irrespetive of their order, either simultaneously or non-simultaneously.
module abro( input clk, input reset,input a, input b, output z );
parameter IDLE = 0,
SA = 1,
SB = 2,
SAB = 3;
reg [1:0] cur_state,next_state;
// Update state or reset on every clock edge
// Output z depends only on the state SAB
// The output z is high when cur_state is SAB
// cur_state is reset to IDLE when reset is high. Otherwise, it takes value of next_state.
// Next state generation logic:
// If cur_state is IDLE and a and b are both high, state changes to SAB
// If cur_state is IDLE, and a is high, state changes to SA
// If cur_state is IDLE, and b is high, state changes to SB
// If cur_state is SA, and b is high, state changes to SAB
// If cur_state is SB, and a is high, state changes to SAB
// If cur_state is SAB, state changes to IDLE
// Implements an FSM in Verilog
|
{
"file_size": 933,
"has_module": true,
"has_testbench": false,
"lines": 20
}
|
shailja_vgen
|
vgen_28
|
prompts-and-testbenches/advanced5/test-example.v
|
// This is an FSM
// It outputs 1 when 1 is received for signals a and b irrespetive of their order, either simultaneously or non-simultaneously.
module abro( input clk, input reset,input a, input b, output z );
parameter IDLE = 0,
SA = 1,
SB = 2,
SAB = 3;
reg [1:0] cur_state,next_state;
// Output z depends only on the state SAB
// The output z is high when cur_state is SAB
// cur_state is reset to IDLE when reset is high. Otherwise, it takes value of next_state.
// Next state generation logic:
// If cur_state is IDLE and a and b are both high, state changes to SAB
// If cur_state is IDLE, and a is high, state changes to SA
// If cur_state is IDLE, and b is high, state changes to SB
// If cur_state is SA, and b is high, state changes to SAB
// If cur_state is SB, and a is high, state changes to SAB
// If cur_state is SAB, state changes to IDLE
// Implements an FSM in Verilog
always @(posedge clk or posedge reset)
begin
if(reset)
cur_state <= IDLE;
else
cur_state <= next_state;
end
always @(cur_state or a or b)
begin
case(cur_state)
IDLE:
begin
if(a && b)
next_state = SAB;
else if(a)
next_state = SA;
else if(b)
next_state = SB;
end
SA:
begin
if(b)
next_state = SAB;
else
next_state = SA;
end
SB:
begin
if(a)
next_state = SAB;
else
next_state = SB;
end
SAB:
begin
next_state = IDLE;
end
default:
next_state = IDLE;
endcase
end
// Output logic:
// Output z is high when cur_state is SAB
assign z = (cur_state == SAB);
endmodule
|
{
"file_size": 1444,
"has_module": true,
"has_testbench": false,
"lines": 65
}
|
shailja_vgen
|
vgen_29
|
prompts-and-testbenches/advanced5/prompt2_abro.v
|
// This is an ABRO FSM.
// It outputs 1 when 1 is received for signals a and b irrespetive of their order, either simultaneously or non-simultaneously.
module abro(
input clk,
input reset,
input a,
input b,
output z );
parameter IDLE = 0,
SA = 1,
SB = 2,
SAB = 3;
reg [1:0] cur_state,next_state;
// The output z is high when 1 is received for signals a and b in any order.
|
{
"file_size": 376,
"has_module": true,
"has_testbench": false,
"lines": 14
}
|
shailja_vgen
|
vgen_30
|
prompts-and-testbenches/advanced5/answer_abro.v
|
// chrome-extension://efaidnbmnnnibpcajpcglclefindmkaj/https://ptolemy.berkeley.edu/books/Systems/chapters/FiniteStateMachines.pdf
module abro(
input clk,
input reset,
input a,
input b,
output z );
parameter IDLE = 0,
SA = 1,
SB = 2,
SAB = 3;
reg [1:0] cur_state,next_state;
assign z = cur_state == SAB ? 1 : 0;
always @ (posedge clk) begin
if (reset)
cur_state <= IDLE;
else
cur_state <= next_state;
end
always @ (cur_state or a or b) begin
case (cur_state)
IDLE : begin
if (a && !b) next_state = SA;
else if (!a && b) next_state = SB;
else if (a && b) next_state = SAB;
else next_state = IDLE;
end
SA: begin
if (b) next_state = SAB;
else next_state = SA;
end
SB : begin
if (a) next_state = SAB;
else next_state = SB;
end
SAB: begin
next_state = IDLE;
end
endcase
end
endmodule
|
{
"file_size": 1032,
"has_module": true,
"has_testbench": false,
"lines": 48
}
|
shailja_vgen
|
vgen_31
|
prompts-and-testbenches/advanced5/tb_abro.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_adv_fsm;
reg clk, reset, a,b;
wire z;
parameter IDLE = 0,
SA = 1,
SB = 2,
SAB = 3;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
abro UUT (.clk(clk), .reset(reset), .a(a), .b(b), .z(z) );
initial // Clock generation
begin
clk = 0;
forever begin
#(period/2);
clk = ~clk;
end
end
initial begin
#2;
// check reset
reset = 1; a = 0; b=0;
#period;
// goes to state IDLE
if(z!==0) begin
$display("test 1 failed");
$finish;
end
else $display("a=%b, b=%b z=%b",a,b,z);
// // check reset with a,b=1
// reset = 1; a = 1; b=1;
// #period;
// // goes to state IDLE
// if(z!==0) begin
// $display("test 2 failed");
// $finish;
// end
// else $display("a=%b, b=%b z=%b",a,b,z);
// start fsm
reset = 0; a = 0; b=0;
#period;
// goes to state IDLE
if(z!==0) begin
$display("test 3 failed");
$finish;
end
else $display("a=%b, b=%b z=%b",a,b,z);
// case: a then b
a = 1; b=0;
#period;
a = 0; b=1;
#period;
// goes to state IDLE
if(z!==1) begin
$display("test 4 failed");
$finish;
end
else $display("a=%b, b=%b z=%b",a,b,z);
// check if it goes back to 0
#period;
// goes to state IDLE
if(z!==0) begin
$display("test 5 failed");
$finish;
end
else $display("a=%b, b=%b z=%b",a,b,z);
// case: a , gap, then b
#period;
a = 1; b=0;
#period;
#period;
#period;
#period;
a = 0; b=1;
#period;
// goes to state IDLE
if(z!==1) begin
$display("test 6 failed");
$finish;
end
else $display("a=%b, b=%b z=%b",a,b,z);
// case: b then a
#period;
a = 0; b=1;
#period;
a = 1; b=0;
#period;
// goes to state IDLE
if(z!==1) begin
$display("test 7 failed");
$finish;
end
else $display("a=%b, b=%b z=%b",a,b,z);
// case: b , gap, then a
#period;
a = 0; b=1;
#period;
#period;
#period;
#period;
a = 1; b=0;
#period;
// goes to state IDLE
if(z!==1) begin
$display("test 8 failed");
$finish;
end
else $display("a=%b, b=%b z=%b",a,b,z);
// case:a and b together
#period;
a = 1; b=1;
#period;
// goes to state IDLE
if(z!==1) begin
$display("test 8 failed");
$finish;
end
else $display("a=%b, b=%b z=%b",a,b,z);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 3139,
"has_module": true,
"has_testbench": false,
"lines": 144
}
|
shailja_vgen
|
vgen_32
|
prompts-and-testbenches/advanced2/tb_countslow.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_count_slow;
reg clk, slowena, reset;
wire [3:0] q;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
count_slow UUT (.clk(clk), .reset(reset), .slowena(slowena), .q(q) );
initial // Clock generation
begin
clk = 0;
forever begin
#(period/2);
clk = ~clk;
end
end
initial begin
#2;
// check reset
reset = 1;
#period;
if(q!==0) begin
$display("test 1 failed");
$finish;
end
else $display("clk=%b, reset=%b, ena=%b, q=%b",clk,reset,slowena, q);
// should stay in reset
slowena=1;
#period;
#period;
if(q!==0) begin
$display("test 2 failed");
$finish;
end
else $display("clk=%b, reset=%b, ena=%b, q=%b",clk,reset,slowena, q);
// start counter
reset=0;
slowena=1;
#period;
if(q!==1) begin
$display("test 3 failed");
$finish;
end
else $display("clk=%b, reset=%b, ena=%b, q=%b",clk,reset,slowena, q);
#period;
if(q!==2) begin
$display("test 4 failed");
$finish;
end
else $display("clk=%b, reset=%b, ena=%b, q=%b",clk,reset,slowena, q);
#period;
if(q!==3) begin
$display("test 5 failed");
$finish;
end
else $display("clk=%b, reset=%b, ena=%b, q=%b",clk,reset,slowena, q);
#period;
if(q!==4) begin
$display("test 6 failed");
$finish;
end
else $display("clk=%b, reset=%b, ena=%b, q=%b",clk,reset,slowena, q);
#period;
if(q!==5) begin
$display("test 7 failed");
$finish;
end
else $display("clk=%b, reset=%b, ena=%b, q=%b",clk,reset,slowena, q);
// pause counter
slowena=0;
#period;
if(q!==5) begin
$display("test 8 failed");
$finish;
end
else $display("clk=%b, reset=%b, ena=%b, q=%b",clk,reset,slowena, q);
#period;
if(q!==5) begin
$display("test 9 failed");
$finish;
end
else $display("clk=%b, reset=%b, ena=%b, q=%b",clk,reset,slowena, q);
// resume counter
slowena=1;
#period;
if(q!==6) begin
$display("test 10 failed");
$finish;
end
else $display("clk=%b, reset=%b, ena=%b, q=%b",clk,reset,slowena, q);
#period;
if(q!==7) begin
$display("test 11 failed");
$finish;
end
else $display("clk=%b, reset=%b, ena=%b, q=%b",clk,reset,slowena, q);
#period;
if(q!==8) begin
$display("test 12 failed");
$finish;
end
else $display("clk=%b, reset=%b, ena=%b, q=%b",clk,reset,slowena, q);
#period;
if(q!==9) begin
$display("test 13 failed");
$finish;
end
else $display("clk=%b, reset=%b, ena=%b, q=%b",clk,reset,slowena, q);
#period;
if(q!==0) begin
$display("test 14 failed");
$finish;
end
else $display("clk=%b, reset=%b, ena=%b, q=%b",clk,reset,slowena, q);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 3531,
"has_module": true,
"has_testbench": false,
"lines": 144
}
|
shailja_vgen
|
vgen_33
|
prompts-and-testbenches/advanced2/prompt3_countslow.v
|
// This is a decade counter that counts from 0 through 9, inclusive. It counts only when slowena is high.
module count_slow(input clk, input slowena, input reset, output reg [3:0] q);
// On the positive edge of the clock:
// if reset is high, reset the output q to 0.
// Otherwise, only increment the output q if the slowena input is high and q is not 9.
|
{
"file_size": 355,
"has_module": true,
"has_testbench": false,
"lines": 5
}
|
shailja_vgen
|
vgen_34
|
prompts-and-testbenches/advanced2/prompt1_countslow.v
|
// This is a decade counter that counts from 0 through 9, inclusive. It counts only when slowena is high.
module count_slow(input clk, input slowena, input reset, output reg [3:0] q);
|
{
"file_size": 183,
"has_module": true,
"has_testbench": false,
"lines": 2
}
|
shailja_vgen
|
vgen_35
|
prompts-and-testbenches/advanced2/prompt2_countslow.v
|
// This is a decade counter that counts from 0 through 9, inclusive. It counts only when slowena is high.
module count_slow(input clk, input slowena, input reset, output reg [3:0] q);
// Increment q if slowena is high and q is not 9.
|
{
"file_size": 233,
"has_module": true,
"has_testbench": false,
"lines": 3
}
|
shailja_vgen
|
vgen_36
|
prompts-and-testbenches/advanced2/answer_countslow.v
|
// Build a decade counter that counts from 0 through 9, inclusive, with a period of 10.
// The reset input is synchronous, and should reset the counter to 0.
// The slowena input indicates when the counter should increment. The counter should stay paused otherwise
module count_slow(
input clk,
input slowena,
input reset,
output reg [3:0] q
);
always @ (posedge clk) begin
if (reset) q <= 4'd0;
else if (slowena) begin
if (q == 4'd9) q<= 4'd0;
else q <= q+4'd1;
end
end
endmodule
|
{
"file_size": 555,
"has_module": true,
"has_testbench": false,
"lines": 20
}
|
shailja_vgen
|
vgen_37
|
prompts-and-testbenches/advanced3/tb_advfsm.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_adv_fsm;
reg clk, reset, x;
wire z;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
adv_fsm UUT (.clk(clk), .reset(reset), .x(x), .z(z) );
initial // Clock generation
begin
clk = 0;
forever begin
#(period/2);
clk = ~clk;
end
end
initial begin
#2;
// check reset
reset = 1; x = 0;
#period;
// goes to state IDLE
if(z!==0) begin
$display("test 1 failed");
$finish;
end
else $display("x=%b, z=%b",x,z);
// start fsm
reset = 0;
x = 0;
#period;
// stays in state IDLE
if(z!==0) begin
$display("test 2 failed");
$finish;
end
else $display("x=%b, z=%b",x,z);
// start pattern
x = 1;
#period;
// goes to S1
if(z!==0) begin
$display("test 3 failed");
$finish;
end
else $display("x=%b, z=%b",x,z);
x = 0;
#period;
// goes to S2
if(z!==0) begin
$display("test 4 failed");
$finish;
end
else $display("x=%b, z=%b",x,z);
x = 1;
#period;
// goes to S3
if(z!==1) begin
$display("test 5 failed");
$finish;
end
else $display("x=%b, z=%b",x,z);
#period;
// goes to S1
if(z!==0) begin
$display("test 6 failed");
$finish;
end
else $display("x=%b, z=%b",x,z);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 1789,
"has_module": true,
"has_testbench": false,
"lines": 86
}
|
shailja_vgen
|
vgen_38
|
prompts-and-testbenches/advanced3/prompt1_advfsm.v
|
// This is a finite state machine that recognizes the sequence 101 on the input signal x.
module adv_fsm(
input clk,
input reset,
input x,
output z );
reg [1:0] present_state, next_state;
parameter IDLE=0, S1=1, S10=2, S101=3;
// output signal z is asserted to 1 when present_state is S101
// present_state is reset to IDLE when rset is high
// otherwise it is assigned next state
// if present_state is IDLE, next_state is assigned S1 if x is 1, otherwise next_state stays at IDLE
// if present_state is S1, next_state is assigned S10 if x is 0, otherwise next_state stays at IDLE
// if present_state is S10, next_state is assigned S101 if x is 1, otherwise next_state stays at IDLE
// if present_state is S101, next_state is assigned IDLE
|
{
"file_size": 746,
"has_module": true,
"has_testbench": false,
"lines": 16
}
|
shailja_vgen
|
vgen_39
|
prompts-and-testbenches/advanced3/prompt3_advfsm.v
|
// https://www.chipverify.com/verilog/verilog-sequence-detector
// This is a finite state machine that recognizes the sequence 101 on the input signal x.
module adv_fsm(
input clk,
input reset,
input x,
output z );
reg [1:0] present_state, next_state;
parameter IDLE=0, S1=1, S10=2, S101=3;
// output signal z is asserted to 1 when present_state is S101
// present_state is reset to IDLE when rset is high
// otherwise it is assigned next state
// if present_state is IDLE, next_state is assigned S1 if x is 1, otherwise next_state stays at IDLE
// if present_state is S1, next_state is assigned S10 if x is 0, otherwise next_state stays at IDLE
// if present_state is S10, next_state is assigned S101 if x is 1, otherwise next_state stays at IDLE
// if present_state is S101, next_state is assigned IDLE
assign z = present_state == S101 ? 1 : 0;
always @ (posedge clk) begin
if (reset)
present_state <= IDLE;
else
present_state <= next_state;
end
always @ (present_state or x) begin
case (present_state)
IDLE : begin
if (x) next_state = S1;
else next_state = IDLE;
end
S1: begin
if (x) next_state = IDLE;
else next_state = S10;
end
S10 : begin
if (x) next_state = S101;
else next_state = IDLE;
end
S101: begin
next_state = IDLE;
end
endcase
end
endmodule
|
{
"file_size": 1454,
"has_module": true,
"has_testbench": false,
"lines": 49
}
|
shailja_vgen
|
vgen_40
|
prompts-and-testbenches/advanced3/prompt2_advfsm.v
|
// This is a finite state machine that recognizes the sequence 101 on the input signal x.
module adv_fsm(
input clk,
input reset,
input x,
output z );
reg [1:0] present_state, next_state;
parameter IDLE=0, S1=1, S10=2, S101=3;
// output signal z is asserted to 1 when present_state is S101
// present_state is reset to IDLE when rset is high
// otherwise it is assigned next state
// if present_state is IDLE, next_state is assigned S1 if x is 1, otherwise next_state stays at IDLE
// if present_state is S1, next_state is assigned S10 if x is 0, otherwise next_state stays at IDLE
// if present_state is S10, next_state is assigned S101 if x is 1, otherwise next_state stays at IDLE
// if present_state is S101, next_state is assigned IDLE
|
{
"file_size": 746,
"has_module": true,
"has_testbench": false,
"lines": 16
}
|
shailja_vgen
|
vgen_41
|
prompts-and-testbenches/advanced3/advfsm.v
|
// This is a finite state machine that recognizes the sequence 101 on the input signal x.
module adv_fsm(
input clk,
input reset,
input x,
output z );
reg [1:0] present_state, next_state;
parameter IDLE=0, S1=1, S10=2, S101=3;
// output signal z is asserted to 1 when present_state is S101
// present_state is reset to IDLE when rset is high
// otherwise it is assigned next state
// if present_state is IDLE, next_state is assigned S1 if x is 1, otherwise next_state stays at IDLE
// if present_state is S1, next_state is assigned S10 if x is 0, otherwise next_state stays at IDLE
// if present_state is S10, next_state is assigned S101 if x is 1, otherwise next_state stays at IDLE
// if present_state is S101, next_state is assigned IDLE
|
{
"file_size": 746,
"has_module": true,
"has_testbench": false,
"lines": 16
}
|
shailja_vgen
|
vgen_42
|
prompts-and-testbenches/advanced4/tb_advshifter.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_adv_shifter;
reg clk, load, ena;
reg [1:0] amount;
reg [63:0] data;
wire [63:0] q;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
advshift UUT (.clk(clk), .load(load), .amount(amount), .data(data), .ena(ena), .q(q) );
initial // Clock generation
begin
clk = 0;
forever begin
#(period/2);
clk = ~clk;
end
end
initial begin
// load data (load not enabled, should not load)
data = 64'hffff_ffff_ffff_ffff;
load = 0;
amount = 0;
ena = 0;
#period;
if(q===64'hffff_ffff_ffff_ffff) begin
$display("test 1 failed");
$finish;
end
else $display("load =%b, amount = %b, ena=%b, q=%b",load,amount,ena, q);
// enable load
load = 1;
amount = 0;
ena = 0;
#period;
if(q!==64'hffff_ffff_ffff_ffff) begin
$display("test 2 failed");
$finish;
end
else $display("load =%b, amount = %b, ena=%b, q=%b",load,amount,ena, q);
// chead load override
load = 1;
amount = 2;
ena = 0;
#period;
if(q!==64'hffff_ffff_ffff_ffff) begin
$display("test 3 failed");
$finish;
end
else $display("load =%b, amount = %b, ena=%b, q=%b",load,amount,ena, q);
// amount = 0 but not enabled (checking enable functionality)
load = 0;
amount = 0;
ena = 0;
#period;
if(q===64'hffff_ffff_ffff_fffe) begin
$display("test 4 failed");
$finish;
end
else $display("load =%b, amount = %b, ena=%b, q=%b",load,amount,ena, q);
// enable, amount=0
load = 0;
amount = 0;
ena = 1;
#period;
if(q!==64'hffff_ffff_ffff_fffe) begin
$display("test 5 failed");
$finish;
end
else $display("load =%b, amount = %b, ena=%b, q=%b",load,amount,ena, q);
// enable, amount=1
load = 0;
amount = 1;
ena = 1;
#period;
if(q!==64'hffff_ffff_ffff_fe00) begin
$display("test 6 failed");
$finish;
end
else $display("load =%b, amount = %b, ena=%b, q=%b",load,amount,ena, q);
// enable, amount=2
load = 0;
amount = 2;
ena = 1;
#period;
if(q!==64'h7fff_ffff_ffff_ff00) begin
$display("test 7 failed");
$finish;
end
else $display("load =%b, amount = %b, ena=%b, q=%b",load,amount,ena, q);
// enable, amount=3
load = 0;
amount = 3;
ena = 1;
#period;
if(q!==64'h007f_ffff_ffff_ffff) begin
$display("test 8 failed");
$finish;
end
else $display("load =%b, amount = %b, ena=%b, q=%b",load,amount,ena, q);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 3114,
"has_module": true,
"has_testbench": false,
"lines": 121
}
|
shailja_vgen
|
vgen_43
|
prompts-and-testbenches/advanced4/prompt1_advshifter.v
|
// Design a 64-bit arithmetic shift register, with synchronous load.
// When ena is high, the shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.
module advshift(input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
// shift according to the following values of amount:
// 2'b00: shift left by 1 bit.
// 2'b01: shift left by 8 bits.
// 2'b10: shift right by 1 bit.
// 2'b11: shift right by 8 bits.
|
{
"file_size": 476,
"has_module": true,
"has_testbench": false,
"lines": 13
}
|
shailja_vgen
|
vgen_44
|
prompts-and-testbenches/advanced4/answer_advshifter.v
|
// Build a 64-bit arithmetic shift register, with synchronous load.
// The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.
// load: Loads shift register with data[63:0] instead of shifting.
// ena: Chooses whether to shift.
// amount: Chooses which direction and how much to shift.
// 2'b00: shift left by 1 bit.
// 2'b01: shift left by 8 bits.
// 2'b10: shift right by 1 bit.
// 2'b11: shift right by 8 bits.
// q: The contents of the shifter.
module advshift(input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always @(posedge clk) begin
if (load) begin
q<=data;
end
else if (ena) begin
case (amount)
0: q <= {q[62:0],1'b0};
1: q <= {q[55:0],8'b0};
2: q <= {1'b0,q[63:1]};
3: q <= {8'b0,q[63:8]};
endcase
end
end
endmodule
|
{
"file_size": 980,
"has_module": true,
"has_testbench": false,
"lines": 35
}
|
shailja_vgen
|
vgen_45
|
prompts-and-testbenches/advanced4/prompt2_advshifter.v
|
// Design a 64-bit arithmetic shift register, with synchronous load.
// When ena is high, the shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.
module advshift(input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
// when load is high, data is loaded.
// if ena is high, shift q according to the following values of amount:
// 2'b00: shift left by 1 bit.
// 2'b01: shift left by 8 bits.
// 2'b10: shift right by 1 bit.
// 2'b11: shift right by 8 bits.
|
{
"file_size": 533,
"has_module": true,
"has_testbench": false,
"lines": 15
}
|
shailja_vgen
|
vgen_46
|
prompts-and-testbenches/advanced4/prompt3_advshifter.v
|
// Design a 64-bit arithmetic shift register, with synchronous load.
// When ena is high, the shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.
module advshift(input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
// when load is high, assign data[63:0] to shift register q.
// if ena is high, shift q.
// amount: Chooses which direction and how much to shift.
// 2'b00: shift left by 1 bit.
// 2'b01: shift left by 8 bits.
// 2'b10: shift right by 1 bit.
// 2'b11: shift right by 8 bits.
|
{
"file_size": 570,
"has_module": true,
"has_testbench": false,
"lines": 16
}
|
shailja_vgen
|
vgen_47
|
prompts-and-testbenches/basic2/prompt2_and_gate.v
|
// This is a module that implements an AND gate
module and_gate(
input a,
input b,
output out );
// ouput the AND of a and b
|
{
"file_size": 127,
"has_module": true,
"has_testbench": false,
"lines": 6
}
|
shailja_vgen
|
vgen_48
|
prompts-and-testbenches/basic2/prompt3_and_gate.v
|
// This is a module that implements an AND gate
module and_gate(
input a,
input b,
output out );
// assign the AND of a and b to out
|
{
"file_size": 135,
"has_module": true,
"has_testbench": false,
"lines": 6
}
|
shailja_vgen
|
vgen_49
|
prompts-and-testbenches/basic2/tb_and_gate.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_and_gate;
reg a,b;
wire out;
// duration for each bit = 2 * timescale = 2 * 1 ns = 2ns
localparam period = 2;
and_gate UUT (.a(a), .b(b), .out(out) );
initial // initial block executes only once
begin
// values for inputs
a = 0; b= 0;
#period; // wait for period
if (out!==0) begin
$display("test 1 failed");
$finish;
end
else $display("a = %b , b = %b, out = %b", a,b, out);
a = 0; b= 1;
#period; // wait for period
if (out!==0) begin
$display("test 2 failed");
$finish;
end
else $display("a = %b , b = %b, out = %b", a,b, out);
a = 1; b= 0;
#period; // wait for period
if (out!==0) begin
$display("test 3 failed");
$finish;
end
else $display("a = %b , b = %b, out = %b", a,b, out);
a = 1; b= 1;
#period; // wait for period
if (out!==1) begin
$display("test 4 failed");
$finish;
end
else $display("a = %b , b = %b, out = %b", a,b, out);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 1428,
"has_module": true,
"has_testbench": false,
"lines": 53
}
|
shailja_vgen
|
vgen_50
|
prompts-and-testbenches/basic2/answer_and_gate.v
|
// Create a module that implements an AND gate
module and_gate(
input a,
input b,
output out );
assign out = a && b;
endmodule
|
{
"file_size": 152,
"has_module": true,
"has_testbench": false,
"lines": 10
}
|
shailja_vgen
|
vgen_51
|
prompts-and-testbenches/basic2/prompt1_and_gate.v
|
// This is a module that implements an AND gate
module and_gate(
input a,
input b,
output out );
|
{
"file_size": 99,
"has_module": true,
"has_testbench": false,
"lines": 5
}
|
shailja_vgen
|
vgen_52
|
prompts-and-testbenches/basic4/answer_mux.v
|
// Create a module that implements an AND gate
module mux(
input [4:0] a, b,
input sel,
output [4:0] out );
assign out = sel?b:a;
endmodule
|
{
"file_size": 159,
"has_module": true,
"has_testbench": false,
"lines": 10
}
|
shailja_vgen
|
vgen_53
|
prompts-and-testbenches/basic4/tb_mux.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
// When sel=0, assign a to out.
// When sel=1, assign b to out.
module tb_mux;
reg [4:0] a,b;
reg sel;
wire [4:0] out;
integer increment_a = 0;
// duration for each bit = 2 * timescale = 2 * 1 ns = 2ns
localparam period = 2;
mux UUT (.a(a), .b(b), .sel(sel), .out(out) );
initial // initial block executes only once
begin
// values for inputs
a = 0; b= 0;
while (b<4'b1111) begin
sel=0;
#period; // wait for period
if (out!==a) begin
$display("test failed");
$finish;
end
else $display("a = %b , b = %b, sel=%b, out = %b", a,b,sel,out);
sel=1;
#period; // wait for period
if (out!==b) begin
$display("test failed");
$finish;
end
else $display("a = %b , b = %b, sel=%b, out = %b", a,b,sel,out);
if (increment_a) a = a+1;
else b = b+1;
if(increment_a) increment_a = 0;
else increment_a=1;
end
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 1368,
"has_module": true,
"has_testbench": false,
"lines": 55
}
|
shailja_vgen
|
vgen_54
|
prompts-and-testbenches/basic4/prompt3_mux.v
|
// This is a 2-to-1 multiplexer.
module mux(
input [4:0] a, b,
input sel,
output [4:0] out );
// When sel=0, assign a to out.
// When sel=1, assign b to out.
|
{
"file_size": 159,
"has_module": true,
"has_testbench": false,
"lines": 7
}
|
shailja_vgen
|
vgen_55
|
prompts-and-testbenches/basic4/prompt1_mux.v
|
// This is a 2-to-1 multiplexer.
module mux(
input [4:0] a, b,
input sel,
output [4:0] out );
|
{
"file_size": 94,
"has_module": true,
"has_testbench": false,
"lines": 5
}
|
shailja_vgen
|
vgen_56
|
prompts-and-testbenches/basic4/prompt2_mux.v
|
// This is a 2-to-1 multiplexer.
module mux(
input [4:0] a, b,
input sel,
output [4:0] out );
// select a when sel is low, otherwise select b
|
{
"file_size": 142,
"has_module": true,
"has_testbench": false,
"lines": 6
}
|
shailja_vgen
|
vgen_57
|
prompts-and-testbenches/basic3/prompt2_priority_encoder.v
|
// This is a 3-bit priority encoder. It outputs the position of the first high bit.
module priority_encoder(
input [2:0] in,
output reg [1:0] pos );
// If none of the input bits are high (i.e., input is zero), output zero.
// assign the position of the highest bit of in to pos
|
{
"file_size": 279,
"has_module": true,
"has_testbench": false,
"lines": 6
}
|
shailja_vgen
|
vgen_58
|
prompts-and-testbenches/basic3/answer_priority_encoder.v
|
// Design a 3-bit priority encoder. If none of the input bits are high (i.e., input is zero), output zero.
module priority_encoder(
input [2:0] in,
output reg [1:0] pos );
always @(*) begin
if (in[0]==1'b1)
pos = 0;
else if (in[1]==1'b1)
pos = 1;
else if (in[2]==1'b1)
pos = 2;
else
pos = 0;
end
endmodule
|
{
"file_size": 410,
"has_module": true,
"has_testbench": false,
"lines": 18
}
|
shailja_vgen
|
vgen_59
|
prompts-and-testbenches/basic3/prompt1_priority_encoder.v
|
// This is a 3-bit priority encoder. It outputs the position of the first high bit.
module priority_encoder(
input [2:0] in,
output reg [1:0] pos );
|
{
"file_size": 150,
"has_module": true,
"has_testbench": false,
"lines": 4
}
|
shailja_vgen
|
vgen_60
|
prompts-and-testbenches/basic3/tb_priority_encoder.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_priority_encoder;
reg[2:0] in;
wire[1:0] pos;
// duration for each bit = 2 * timescale = 2 * 1 ns = 2ns
localparam period = 2;
priority_encoder UUT (.in(in), .pos(pos) );
initial // initial block executes only once
begin
// values for inputs
in = 0;
#period; // wait for period
if (pos!==1'd0) begin
$display("test 1 failed");
$finish;
end
else $display("in = %d , pos = %d ", in, pos);
in = 1;
#period; // wait for period
if (pos!==0) begin
$display("test 2 failed");
$finish;
end
else $display("in = %b , pos = %b ", in, pos);
in = 2;
#period; // wait for period
if (pos!==1) begin
$display("test 3 failed");
$finish;
end
else $display("in = %b , pos = %b ", in, pos);
in = 3;
#period; // wait for period
if (pos!==0) begin
$display("test 4 failed");
$finish;
end
else $display("in = %b , pos = %b ", in, pos);
in = 4;
#period; // wait for period
if (pos!==2) begin
$display("test 5 failed");
$finish;
end
else $display("in = %b , pos = %b ", in, pos);
in = 5;
#period; // wait for period
if (pos!==0) begin
$display("test 6 failed");
$finish;
end
else $display("in = %b , pos = %b ", in, pos);
in = 6;
#period; // wait for period
if (pos!==1) begin
$display("test 7 failed");
$finish;
end
else $display("in = %b , pos = %b ", in, pos);
in = 7;
#period; // wait for period
if (pos!==0) begin
$display("test 8 failed");
$finish;
end
else $display("in = %b , pos = %b ", in, pos);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 2348,
"has_module": true,
"has_testbench": false,
"lines": 86
}
|
shailja_vgen
|
vgen_61
|
prompts-and-testbenches/basic3/prompt3_priority_encoder.v
|
// This is a 3-bit priority encoder. It outputs the position of the first high bit.
module priority_encoder(
input [2:0] in,
output reg [1:0] pos );
// If in==0, assign zero to pos
// If in[0] is high, assign 0 to pos
// If in[1] is high, assign 1 to pos
// If in[2] is high, assign 2 to pos
|
{
"file_size": 293,
"has_module": true,
"has_testbench": false,
"lines": 8
}
|
shailja_vgen
|
vgen_62
|
prompts-and-testbenches/intermediate6/tb_ram.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_ram;
parameter ADDR_WIDTH=6;
parameter DATA_WIDTH=8;
reg [DATA_WIDTH-1:0] data;
reg [ADDR_WIDTH-1:0] addr;
reg we, clk;
wire [DATA_WIDTH-1:0] q;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
ram UUT (.clk(clk), .we(we), .addr(addr), .data(data), .q(q) );
initial // Clock generation
begin
clk = 0;
forever begin
#(period/2);
clk = ~clk;
end
end
initial begin
// write to ram[0]
data = 8'hab;
addr=0;
we = 1;
#period;
if(q!==8'hab) begin
$display("test 1 failed");
$finish;
end
else $display("q=%b",q);
// write to ram[20]
data = 8'h77;
addr=20;
we = 1;
#period;
if(q!==8'h77) begin
$display("test 2 failed");
$finish;
end
else $display("q=%b",q);
// read ram[0]
data = 8'h77;
addr=0;
we = 0;
#period;
if(q!==8'hab) begin
$display("test 3 failed");
$finish;
end
else $display("q=%b",q);
// read ram[20]
data = 8'h12;
addr=20;
we = 0;
#period;
if(q!==8'h77) begin
$display("test 3 failed");
$finish;
end
else $display("q=%b",q);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 1575,
"has_module": true,
"has_testbench": false,
"lines": 78
}
|
shailja_vgen
|
vgen_63
|
prompts-and-testbenches/intermediate6/answer_ram.v
|
// This is a RAM module
module ram #( parameter ADDR_WIDTH=6, parameter DATA_WIDTH=8)
(input [DATA_WIDTH-1:0] data, input [ADDR_WIDTH-1:0] addr, input we, clk, output [DATA_WIDTH-1:0] q);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// when we is high, write data to ram at address addr
// assign the ram value at address addr to q
always @ (posedge clk)
begin
if (we)
ram[addr] <= data;
end
assign q = ram[addr];
endmodule
|
{
"file_size": 444,
"has_module": true,
"has_testbench": false,
"lines": 16
}
|
shailja_vgen
|
vgen_64
|
prompts-and-testbenches/intermediate6/prompt1_ram.v
|
// This is a RAM module
module ram #( parameter ADDR_WIDTH=6, parameter DATA_WIDTH=8)
(input [DATA_WIDTH-1:0] data, input [ADDR_WIDTH-1:0] addr, input we, clk, output [DATA_WIDTH-1:0] q);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
|
{
"file_size": 233,
"has_module": true,
"has_testbench": false,
"lines": 4
}
|
shailja_vgen
|
vgen_65
|
prompts-and-testbenches/intermediate6/prompt3_ram.v
|
// This is a RAM module
module ram #( parameter ADDR_WIDTH=6, parameter DATA_WIDTH=8)
(input [DATA_WIDTH-1:0] data, input [ADDR_WIDTH-1:0] addr, input we, clk, output [DATA_WIDTH-1:0] q);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// when we is high, write data to ram at address addr
// assign the ram value at address addr to q
|
{
"file_size": 332,
"has_module": true,
"has_testbench": false,
"lines": 6
}
|
shailja_vgen
|
vgen_66
|
prompts-and-testbenches/intermediate6/prompt2_ram.v
|
// This is a RAM module
module ram #( parameter ADDR_WIDTH=6, parameter DATA_WIDTH=8)
(input [DATA_WIDTH-1:0] data, input [ADDR_WIDTH-1:0] addr, input we, clk, output [DATA_WIDTH-1:0] q);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// when we is high, write data to ram
// read teh value of ram at address addr
|
{
"file_size": 312,
"has_module": true,
"has_testbench": false,
"lines": 6
}
|
shailja_vgen
|
vgen_67
|
prompts-and-testbenches/intermediate1/answer_half_adder.v
|
// Design a half adder. A half adder adds two bits and produces a sum and carry-out
module half_adder(
input a, b,
output cout, sum );
assign sum = a^b;
assign cout = a&b;
endmodule
|
{
"file_size": 202,
"has_module": true,
"has_testbench": false,
"lines": 9
}
|
shailja_vgen
|
vgen_68
|
prompts-and-testbenches/intermediate1/tb_half_adder.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_half_adder;
reg a,b;
wire cout,sum;
// duration for each bit = 2 * timescale = 2 * 1 ns = 2ns
localparam period = 2;
half_adder UUT ( .a(a), .b(b), .cout(cout), .sum(sum) );
initial // initial block executes only once
begin
// values for inputs
a = 0; b=0;
#period; // wait for period
if (cout!==0 && sum!==0) begin
$display("test 1 failed");
$finish;
end
else $display("a=%b, b=%b, cout=%b, sum=%b ", a,b,cout,sum);
a = 0; b=1;
#period; // wait for period
if (cout!==0 && sum!==1) begin
$display("test 2 failed");
$finish;
end
else $display("a=%b, b=%b, cout=%b, sum=%b ", a,b,cout,sum);
a = 1; b=0;
#period; // wait for period
if (cout!==0 && sum!==1) begin
$display("test 3 failed");
$finish;
end
else $display("a=%b, b=%b, cout=%b, sum=%b ", a,b,cout,sum);
a = 1; b=1;
#period; // wait for period
if (cout!==1 && sum!==0) begin
$display("test 4 failed");
$finish;
end
else $display("a=%b, b=%b, cout=%b, sum=%b ", a,b,cout,sum);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 1524,
"has_module": true,
"has_testbench": false,
"lines": 54
}
|
shailja_vgen
|
vgen_69
|
prompts-and-testbenches/intermediate1/prompt1_half_adder.v
|
// This is a half adder.
module half_adder(
input a, b,
output cout, sum );
|
{
"file_size": 76,
"has_module": true,
"has_testbench": false,
"lines": 4
}
|
shailja_vgen
|
vgen_70
|
prompts-and-testbenches/intermediate1/prompt3_half_adder.v
|
// This is a half adder.
module half_adder(
input a, b,
output cout, sum );
// A half adder adds two bits and produces a sum and carry-out.
// assign the xor of a and b to sum
// assign the and of a and b to cout
|
{
"file_size": 213,
"has_module": true,
"has_testbench": false,
"lines": 7
}
|
shailja_vgen
|
vgen_71
|
prompts-and-testbenches/intermediate1/prompt2_half_adder.v
|
// This is a half adder.
module half_adder(
input a, b,
output cout, sum );
// A half adder adds two bits and produces a sum and carry-out.
|
{
"file_size": 140,
"has_module": true,
"has_testbench": false,
"lines": 5
}
|
shailja_vgen
|
vgen_72
|
prompts-and-testbenches/intermediate8/answer_truthtable.v
|
// https://hdlbits.01xz.net/wiki/Truthtable1
// This is a circuit synthesized from a truth table
// The truth table is for a three-input, one-output function. It has 8 rows for each of the 8 possible input combinations, and one output column.
// There are four inputs combinations where the output is 1, and four where the output is 0.
// Inputs | Outputs
// x3 x2 x1 | f
// 0 0 0 | 1
// 0 0 1 | 1
// 0 1 0 | 0
// 0 1 1 | 1
// 1 0 0 | 0
// 1 0 1 | 0
// 1 1 0 | 1
// 1 1 1 | 0
module truthtable(input x3, input x2, input x1, output f );
assign f = (~x3 && ~x2 && ~x1) || (~x3 && ~x2 && x1) || (~x3 && x2 && x1) || (x3 && x2 && ~x1);
endmodule
|
{
"file_size": 730,
"has_module": true,
"has_testbench": false,
"lines": 20
}
|
shailja_vgen
|
vgen_73
|
prompts-and-testbenches/intermediate8/prompt1_truthtable.v
|
// This is a circuit synthesized from a truth table
// Inputs | Outputs
// x3 x2 x1 | f
// 0 0 0 | 1
// 0 0 1 | 1
// 0 1 0 | 0
// 0 1 1 | 1
// 1 0 0 | 0
// 1 0 1 | 0
// 1 1 0 | 1
// 1 1 1 | 0
module truthtable(input x3, input x2, input x1, output f );
|
{
"file_size": 336,
"has_module": true,
"has_testbench": false,
"lines": 12
}
|
shailja_vgen
|
vgen_74
|
prompts-and-testbenches/intermediate8/tb_truthtable.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_truthtable;
reg x3,x2,x1;
wire f;
// duration for each bit = 2 * timescale = 2 * 1 ns = 2ns
localparam period = 2;
integer i;
truthtable UUT ( .x3(x3), .x2(x2), .x1(x1), .f(f) );
initial // initial block executes only once
begin
x3=0; x2=0; x1=0;
#period; // wait for period
if (f!==1) begin
$display("test 1 failed");
$finish;
end
else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3,x2,x1,f);
x3=0; x2=0; x1=1;
#period; // wait for period
if (f!==1) begin
$display("test 2 failed");
$finish;
end
else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3,x2,x1,f);
x3=0; x2=1; x1=0;
#period; // wait for period
if (f!==0) begin
$display("test 3 failed");
$finish;
end
else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3,x2,x1,f);
x3=0; x2=1; x1=1;
#period; // wait for period
if (f!==1) begin
$display("test 4 failed");
$finish;
end
else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3,x2,x1,f);
x3=1; x2=0; x1=0;
#period; // wait for period
if (f!==0) begin
$display("test 5 failed");
$finish;
end
else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3,x2,x1,f);
x3=1; x2=0; x1=1;
#period; // wait for period
if (f!==0) begin
$display("test 6 failed");
$finish;
end
else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3,x2,x1,f);
x3=1; x2=1; x1=0;
#period; // wait for period
if (f!==1) begin
$display("test 7 failed");
$finish;
end
else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3,x2,x1,f);
x3=1; x2=1; x1=1;
#period; // wait for period
if (f!==0) begin
$display("test 8 failed");
$finish;
end
else $display("x3=%b, x2=%b, x1=%b, f=%b ", x3,x2,x1,f);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 2228,
"has_module": true,
"has_testbench": false,
"lines": 86
}
|
shailja_vgen
|
vgen_75
|
prompts-and-testbenches/intermediate8/prompt3_truthtable.v
|
// This is a circuit synthesized from a truth table
// The truth table is for a three-input, one-output function. It has 8 rows for each of the 8 possible input combinations, and one output column.
// There are four inputs combinations where the output is 1, and four where the output is 0.
// Inputs | Outputs
// x3 x2 x1 | f
// 0 0 0 | 1
// 0 0 1 | 1
// 0 1 0 | 0
// 0 1 1 | 1
// 1 0 0 | 0
// 1 0 1 | 0
// 1 1 0 | 1
// 1 1 1 | 0
module truthtable(input x3, input x2, input x1, output f );
// If x3 is low and x2 is low and x3 is low, assign 1 to f
// If x3 is low and x2 is low and x3 is high, assign 1 to f
// If x3 is low and x2 is high and x3 is low, assign 0 to f
// If x3 is low and x2 is high and x3 is high, assign 1 to f
// If x3 is high and x2 is low and x3 is low, assign 0 to f
// If x3 is high and x2 is low and x3 is high, assign 0 to f
// If x3 is high and x2 is high and x3 is low, assign 1 to f
// If x3 is high and x2 is high and x3 is high, assign 0 to f
|
{
"file_size": 1061,
"has_module": true,
"has_testbench": false,
"lines": 23
}
|
shailja_vgen
|
vgen_76
|
prompts-and-testbenches/intermediate8/prompt2_truthtable.v
|
// This is a circuit synthesized from a truth table
// The truth table is for a three-input, one-output function. It has 8 rows for each of the 8 possible input combinations, and one output column.
// There are four inputs combinations where the output is 1, and four where the output is 0.
// Inputs | Outputs
// x3 x2 x1 | f
// 0 0 0 | 1
// 0 0 1 | 1
// 0 1 0 | 0
// 0 1 1 | 1
// 1 0 0 | 0
// 1 0 1 | 0
// 1 1 0 | 1
// 1 1 1 | 0
module truthtable(input x3, input x2, input x1, output f );
|
{
"file_size": 576,
"has_module": true,
"has_testbench": false,
"lines": 14
}
|
shailja_vgen
|
vgen_77
|
prompts-and-testbenches/intermediate7/tb_permutation.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_permutation;
reg [31:0] In32;
wire [31:0] Out32;
// duration for each bit = 2 * timescale = 2 * 1 ns = 2ns
localparam period = 2;
integer i;
P_box UUT ( .In32(In32), .Out32(Out32) );
initial // initial block executes only once
begin
// values for inputs
In32 = 0;
#period; // wait for period
if(Out32!==32'b0000_0000_0000_0000_0000_0000_0000_0000) begin
$display("test 1 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
In32=1;
#period; // wait for period
if(Out32!==32'b00001000000000000000000000000000 ) begin
$display("test 2 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
In32=1009;
#period; // wait for period
if(Out32!==32'b00001000000000000000111011000010) begin
$display("test 3 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
In32=1997;
#period; // wait for period
if(Out32!==32'b00111000000000000000011010001010) begin
$display("test 4 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
In32=876;
#period; // wait for period
if(Out32!==32'b00110000000000000000010011000010) begin
$display("test 5 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
In32=925;
#period; // wait for period
if(Out32!==32'b00111000000000000000111010000000) begin
$display("test 6 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
In32=2020;
#period; // wait for period
if(Out32!==32'b00010000000000000000011011001010) begin
$display("test 7 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
In32=11111;
#period; // wait for period
if(Out32!==32'b00011000000000000010010111010010) begin
$display("test 8 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
In32=909090;
#period; // wait for period
if(Out32!==32'b00000000000101010101010111011001) begin
$display("test 9 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
In32=81818;
#period; // wait for period
if(Out32!==32'b00100000000000010011111110011000) begin
$display("test 10 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
In32=666;
#period; // wait for period
if(Out32!==32'b00100000000000000000101110000000) begin
$display("test 11 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
In32=3123;
#period; // wait for period
if(Out32!==32'b00001000000000000000100101011000) begin
$display("test 12 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
In32=67898;
#period; // wait for period
if(Out32!==32'b00100000000000010000110101010000) begin
$display("test 13 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
In32=917;
#period; // wait for period
if(Out32!==32'b00011000000000000000111010000000) begin
$display("test 14 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
In32=90210;
#period; // wait for period
if(Out32!==32'b00000000000000010110000101000010) begin
$display("test 15 failed");
$finish;
end
else $display("In=%b, Out=%b ", In32, Out32);
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 4607,
"has_module": true,
"has_testbench": false,
"lines": 143
}
|
shailja_vgen
|
vgen_78
|
prompts-and-testbenches/intermediate7/prompt2_permutation.v
|
// This is a permutation block module.
module P_box ( input wire [31:0] In32, output reg [31:0] Out32 );
localparam len_table = 32;
reg [5:0] In32table [len_table-1:0];
initial begin
In32table[0] = 15;
In32table[1] = 6;
In32table[2] = 20;
In32table[3] = 10;
In32table[4] = 11;
In32table[5] = 22;
In32table[6] = 5;
In32table[7] = 9;
In32table[8] = 1;
In32table[9] = 7;
In32table[10] = 8;
In32table[11] = 4;
In32table[12] = 12;
In32table[13] = 13;
In32table[14] = 14;
In32table[15] = 17;
In32table[16] = 16;
In32table[17] = 25;
In32table[18] = 19;
In32table[19] = 23;
In32table[20] = 18;
In32table[21] = 26;
In32table[22] = 28;
In32table[23] = 27;
In32table[24] = 29;
In32table[25] = 31;
In32table[26] = 30;
In32table[27] = 0;
In32table[28] = 2;
In32table[29] = 3;
In32table[30] = 21;
In32table[31] = 24;
end
integer i;
// The input signal bits are permuted according to the table In32table.
|
{
"file_size": 897,
"has_module": true,
"has_testbench": false,
"lines": 41
}
|
shailja_vgen
|
vgen_79
|
prompts-and-testbenches/intermediate7/prompt1_permutation.v
|
// This is a permutation block module.
module P_box ( input wire [31:0] In32, output reg [31:0] Out32 );
localparam len_table = 32;
reg [5:0] In32table [len_table-1:0];
initial begin
In32table[0] = 15;
In32table[1] = 6;
In32table[2] = 20;
In32table[3] = 10;
In32table[4] = 11;
In32table[5] = 22;
In32table[6] = 5;
In32table[7] = 9;
In32table[8] = 1;
In32table[9] = 7;
In32table[10] = 8;
In32table[11] = 4;
In32table[12] = 12;
In32table[13] = 13;
In32table[14] = 14;
In32table[15] = 17;
In32table[16] = 16;
In32table[17] = 25;
In32table[18] = 19;
In32table[19] = 23;
In32table[20] = 18;
In32table[21] = 26;
In32table[22] = 28;
In32table[23] = 27;
In32table[24] = 29;
In32table[25] = 31;
In32table[26] = 30;
In32table[27] = 0;
In32table[28] = 2;
In32table[29] = 3;
In32table[30] = 21;
In32table[31] = 24;
end
integer i;
|
{
"file_size": 825,
"has_module": true,
"has_testbench": false,
"lines": 40
}
|
shailja_vgen
|
vgen_80
|
prompts-and-testbenches/intermediate7/answer_permutation.v
|
// Advanced Hardware Design, lecture 1
module P_box ( input wire [31:0] In32, output reg [31:0] Out32 );
localparam len_table = 32;
reg [5:0] In32table [len_table-1:0];
initial begin
In32table[0] = 15;
In32table[1] = 6;
In32table[2] = 20;
In32table[3] = 10;
In32table[4] = 11;
In32table[5] = 22;
In32table[6] = 5;
In32table[7] = 9;
In32table[8] = 1;
In32table[9] = 7;
In32table[10] = 8;
In32table[11] = 4;
In32table[12] = 12;
In32table[13] = 13;
In32table[14] = 14;
In32table[15] = 17;
In32table[16] = 16;
In32table[17] = 25;
In32table[18] = 19;
In32table[19] = 23;
In32table[20] = 18;
In32table[21] = 26;
In32table[22] = 28;
In32table[23] = 27;
In32table[24] = 29;
In32table[25] = 31;
In32table[26] = 30;
In32table[27] = 0;
In32table[28] = 2;
In32table[29] = 3;
In32table[30] = 21;
In32table[31] = 24;
end
integer i;
always @(In32) begin
for (i = 0; i < len_table; i = i + 1) begin
Out32[i] <= In32[In32table[i]];
end
end
endmodule
|
{
"file_size": 1244,
"has_module": true,
"has_testbench": false,
"lines": 50
}
|
shailja_vgen
|
vgen_81
|
prompts-and-testbenches/intermediate7/prompt3_permutation.v
|
// This is a permutation block module.
module P_box ( input wire [31:0] In32, output reg [31:0] Out32 );
localparam len_table = 32;
reg [5:0] In32table [len_table-1:0];
initial begin
In32table[0] = 15;
In32table[1] = 6;
In32table[2] = 20;
In32table[3] = 10;
In32table[4] = 11;
In32table[5] = 22;
In32table[6] = 5;
In32table[7] = 9;
In32table[8] = 1;
In32table[9] = 7;
In32table[10] = 8;
In32table[11] = 4;
In32table[12] = 12;
In32table[13] = 13;
In32table[14] = 14;
In32table[15] = 17;
In32table[16] = 16;
In32table[17] = 25;
In32table[18] = 19;
In32table[19] = 23;
In32table[20] = 18;
In32table[21] = 26;
In32table[22] = 28;
In32table[23] = 27;
In32table[24] = 29;
In32table[25] = 31;
In32table[26] = 30;
In32table[27] = 0;
In32table[28] = 2;
In32table[29] = 3;
In32table[30] = 21;
In32table[31] = 24;
end
integer i;
// The input signal bits are permuted according to the table In32table.
// For i=0 till i<32, assign the bit of in32 indexed by In32table[i] to Out32[i]
|
{
"file_size": 979,
"has_module": true,
"has_testbench": false,
"lines": 42
}
|
shailja_vgen
|
vgen_82
|
prompts-and-testbenches/advanced1/prompt2_signed-addition-overflow.v
|
// This is a signed adder that adds two 8-bit 2's complement numbers. It also captures a signed overflow.
module signed_adder(input [7:0] a, input [7:0] b, output [7:0] s, output overflow );
// The numbers a and b are added to the output s.
// The signed overflow of a and b is assigned to the output overflow.
|
{
"file_size": 312,
"has_module": true,
"has_testbench": false,
"lines": 4
}
|
shailja_vgen
|
vgen_83
|
prompts-and-testbenches/advanced1/prompt3_signed-addition-overflow.v
|
// This is a signed adder that adds two 8-bit 2's complement numbers. It also captures a signed overflow.
module signed_adder(input [7:0] a, input [7:0] b, output [7:0] s, output overflow );
// The numbers a and b are added to the output s.
// assign the occurence of the signed overflow of a and b to the output overflow.
// a signed overflow occurs if the most significant bits of a and b are low and the most significant bit of s is high
// a signed overflow may also occur if the most significant bits of a and b are high and the most significant bit of s is low
|
{
"file_size": 570,
"has_module": true,
"has_testbench": false,
"lines": 8
}
|
shailja_vgen
|
vgen_84
|
prompts-and-testbenches/advanced1/prompt1_signed-addition-overflow.v
|
// This is a signed adder that adds two 8-bit 2's complement numbers. It also captures a signed overflow.
module signed_adder(input [7:0] a, input [7:0] b, output [7:0] s, output overflow );
|
{
"file_size": 192,
"has_module": true,
"has_testbench": false,
"lines": 2
}
|
shailja_vgen
|
vgen_85
|
prompts-and-testbenches/advanced1/answer_signed-addition-overflow.v
|
// Design a signed adder that adds two 8-bit 2's complement numbers, a[7:0] and b[7:0].
// These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred.
module signed_adder(input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
);
assign s = a+b;
assign overflow = a[7]&&b[7]&&(~s[7]) || (~a[7])&&(~b[7])&&(s[7]);
endmodule
|
{
"file_size": 392,
"has_module": true,
"has_testbench": false,
"lines": 13
}
|
shailja_vgen
|
vgen_86
|
prompts-and-testbenches/advanced1/tb_signed-addition-overflow.v
|
`timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps
module tb_signed_adder;
reg [7:0] a,b;
wire [7:0] s;
wire overflow;
integer increment_a = 0;
// duration for each bit = 2 * timescale = 2 * 1 ns = 2ns
localparam period = 2;
signed_adder UUT (.a(a), .b(b), .s(s), .overflow(overflow) );
initial // initial block executes only once
begin
// values for inputs
a = 0; b= 0;
while (b<8'b1111_1111) begin
#period; // wait for period
if (s!==a+b || overflow!==(a[7]&&b[7]&&(~s[7]) || (~a[7])&&(~b[7])&&(s[7])) ) begin
$display("test failed");
$display(" a = %b , b = %b, sum=%b, overflow = %b", a,b,s,overflow);
$finish;
end
$display(" a = %b , b = %b, sum=%b, overflow = %b", a,b,s,overflow);
if (increment_a) a = a+1;
else b = b+1;
if (increment_a) increment_a = 0;
else increment_a=1;
end
$display("all tests passed");
$finish;
end
endmodule
|
{
"file_size": 1194,
"has_module": true,
"has_testbench": false,
"lines": 44
}
|
hardware-shailja-vgen
Shailja VGen Collection - 87 Verilog files
Dataset Overview
This dataset is part of a comprehensive collection of hardware design datasets for training and evaluating LLMs on Verilog/SystemVerilog code generation and hardware design tasks.
Files
- vgen_files.json: 87 Verilog files from VGen framework
Usage
from datasets import load_dataset
# Load the dataset
dataset = load_dataset('AbiralArch/hardware-shailja-vgen')
# Access the data
data = dataset['train']
Citation
If you use this dataset in your research, please cite:
@dataset{hardware_design_dataset,
title={hardware-shailja-vgen},
author={Architect-Chips},
year={2025},
url={https://huggingface.co/datasets/AbiralArch/hardware-shailja-vgen}
}
License
This dataset is provided for research and educational purposes. Please check individual source licenses.
Acknowledgments
This dataset combines data from multiple sources in the hardware design community. We thank all contributors and original dataset creators.
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