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Datasets:
AbiralArch
/
hardware-shailja-vgen
Like
0
Tasks:
Text Generation
Modalities:
Text
Formats:
json
Languages:
code
Size:
< 1K
Tags:
hardware
rtl
verilog
systemverilog
fpga
asic
+ 2
Libraries:
Datasets
pandas
Croissant
+ 1
Dataset card
Data Studio
Files
Files and versions
xet
Community
main
hardware-shailja-vgen
103 kB
Ctrl+K
Ctrl+K
1 contributor
History:
3 commits
AbiralArch
Upload README.md with huggingface_hub
e000cd1
verified
about 1 year ago
.gitattributes
Safe
2.46 kB
initial commit
about 1 year ago
README.md
Safe
1.29 kB
Upload README.md with huggingface_hub
about 1 year ago
vgen_files.json
Safe
98.9 kB
Upload vgen_files.json with huggingface_hub
about 1 year ago
