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Datasets:
AbiralArch
/
hardware-shailja-vgen

Tasks:
Text Generation
Modalities:
Text
Formats:
json
Languages:
code
Size:
< 1K
Tags:
hardware
rtl
verilog
systemverilog
fpga
asic
Libraries:
Datasets
pandas
Dataset card Data Studio Files
xet
Community
AbiralArch commited on
Commit
1f15891
·
verified ·
1 Parent(s): 6e7a3c0

Upload vgen_files.json with huggingface_hub

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