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--- |
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license: mit |
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language: |
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- en |
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tags: |
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- FPGA |
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- HLS |
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pretty_name: GNΩSIS |
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size_categories: |
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- 100K<n<1M |
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--- |
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# Dataset Card for GNΩSIS |
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## Dataset Details |
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### Dataset Description |
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GNΩSIS is an open-source HLS dataset, containing more than 220K design points generated from prominent benchmark suites and public repositories. |
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The dataset covers two Xilinx/AMD FPGAs with varying resource characteristics and three clock frequencies. |
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- **Curated by:** Aggelos Ferikoglou |
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- **Shared by:** Aggelos Ferikoglou |
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- **License:** MIT |
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### Dataset Sources |
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- **Repository:** https://github.com/aferikoglou/GNWSIS |
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## Dataset Structure |
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The GNΩSIS dataset is organized as a CSV file, where each row corresponds to a distinct hardware design configuration for a specific application, targeting a particular FPGA and clock frequency. It includes both configuration parameters and associated performance and resource utilization metrics. |
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#### Configuration Parameters |
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These columns define the application context and the design parameters: |
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* **Application\_Name**: The name of the application being analyzed. |
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* **Version**: Identifier for a specific version or configuration of the application. |
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* **Device**: The target FPGA device (e.g., `xczu7ev-ffvc1156-2-e`, `xcu200-fsgd2104-2-e`). |
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* **Clock\_Period\_nsec**: The clock period for the design, in nanoseconds. |
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#### Applied Directives |
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These fields indicate which design directives have been applied to specific action points within the kernel: |
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* **Array\_1** to **Array\_22**: Represent directives applied to array-related action points (e.g., `complete_1`). |
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* **OuterLoop\_1** to **OuterLoop\_26** and **InnerLoop\_1\_1** to **InnerLoop\_4\_2**: Capture loop-specific directives such as `pipeline_1` or `unroll_2`. |
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#### Quality of Result Metrics |
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* **Latency\_msec**: Kernel execution latency, measured in milliseconds. |
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* **Synthesis\_Time\_sec**: Total time taken to synthesize the design, in seconds. |
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* **BRAM\_Utilization\_percentage**, **DSP\_Utilization\_percentage**, **FF\_Utilization\_percentage**, **LUT\_Utilization\_percentage**: Resource usage reported as a percentage of the total available on the target FPGA device. |
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* **Speedup**: Performance improvement factor compared to a baseline implementation. |
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* **BRAMs**, **DSPs**, **FFs**, **LUTs**: Calculated absolute resource usage based on utilization percentage and the FPGA's total capacity. |
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## Citation |
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**BibTeX:** |
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## Dataset Card Authors |
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Aggelos Ferikoglou |
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## Dataset Card Contact |
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E-mail: [email protected] |
