| task_categories: | |
| - text-generation | |
| language: | |
| - code | |
| tags: | |
| - hardware | |
| - rtl | |
| - verilog | |
| - systemverilog | |
| - fpga | |
| - asic | |
| - digital-design | |
| - code-generation | |
| pretty_name: Shailja VGen Collection | |
| size_categories: | |
| - 1K<n<10K | |
| # hardware-shailja-vgen | |
| Shailja VGen Collection - 87 Verilog files | |
| ## Dataset Overview | |
| This dataset is part of a comprehensive collection of hardware design datasets for training and evaluating LLMs on Verilog/SystemVerilog code generation and hardware design tasks. | |
| ## Files | |
| - **vgen_files.json**: 87 Verilog files from VGen framework | |
| ## Usage | |
| ```python | |
| from datasets import load_dataset | |
| # Load the dataset | |
| dataset = load_dataset('AbiralArch/hardware-shailja-vgen') | |
| # Access the data | |
| data = dataset['train'] | |
| ``` | |
| ## Citation | |
| If you use this dataset in your research, please cite: | |
| ```bibtex | |
| @dataset{hardware_design_dataset, | |
| title={hardware-shailja-vgen}, | |
| author={Architect-Chips}, | |
| year={2025}, | |
| url={https://huggingface.co/datasets/AbiralArch/hardware-shailja-vgen} | |
| } | |
| ``` | |
| ## License | |
| This dataset is provided for research and educational purposes. Please check individual source licenses. | |
| ## Acknowledgments | |
| This dataset combines data from multiple sources in the hardware design community. We thank all contributors and original dataset creators. | |