system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
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You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scan(float * input, float * output, int len) {
//@@ Load a segment of the input vector into shared memory
__shared__ float sh_input[2048];
int tx = threadIdx.x;
int tx2= tx + blockDim.x;
int bdimx = blockDim.x;
int i = 2*blockIdx.x*blockDim.x + tx;
int start = 2*blockIdx.x*blockDim.x;
int Col1 = start + tx;
int Col2 = start + bdimx + tx;
if( Col2 < len)
{
// Collaborative loading of A
sh_input[tx] = input[ Col1];
sh_input[tx2] = input[ Col2];
}
else if ( Col1 < len)
{ // Control divergence at the edge
sh_input[tx] = input[ Col1];
sh_input[tx2]= 0.0f;
}
else
{ // Control divergence at the edge
sh_input[tx] = 0.0f;
sh_input[tx2]= 0.0f;
}
__syncthreads();
//output[Col1] = sh_input[tx]; output[Col2] = sh_input[tx2];
unsigned int stride; int index;
// @@ Traverse the reduction tree down
for (stride = 1;stride <= 2*bdimx ; stride *= 2)
{
index = (tx +1)* stride*2 -1;
if (index < 2*bdimx)
sh_input[index] += sh_input[index-stride];
__syncthreads();
}
//@@ Traverse the reduction tree up
for ( stride = bdimx/2; stride > 0; stride/=2)
{
__syncthreads();
index = (tx +1)* stride*2 -1;
if (index + stride < 2*bdimx)
sh_input[index+stride] += sh_input[index];
}
//@@ Write the computed sum of the block to the output vector at the
//@@ correct index
__syncthreads();
output[i] = sh_input[tx];
if ( i + bdimx < len)
{
output[i + bdimx] = sh_input[tx2];
}
} | .text
.file "scan.hip"
.globl _Z19__device_stub__scanPfS_i # -- Begin function _Z19__device_stub__scanPfS_i
.p2align 4, 0x90
.type _Z19__device_stub__scanPfS_i,@function
_Z19__device_stub__scanPfS_i: # @_Z19__device_stub__scanPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4scanPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__scanPfS_i, .Lfunc_end0-_Z19__device_stub__scanPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4scanPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4scanPfS_i,@object # @_Z4scanPfS_i
.section .rodata,"a",@progbits
.globl _Z4scanPfS_i
.p2align 3, 0x0
_Z4scanPfS_i:
.quad _Z19__device_stub__scanPfS_i
.size _Z4scanPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4scanPfS_i"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__scanPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4scanPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4scanPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x1c0 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203037824 */
/* 0x001fc800078e00ff */
/*0070*/ IMAD R4, R3, c[0x0][0x0], R0 ; /* 0x0000000003047a24 */
/* 0x002fe400078e0200 */
/*0080*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.WIDE R6, R4.reuse, R9, c[0x0][0x160] ; /* 0x0000580004067625 */
/* 0x040fe200078e0209 */
/*00a0*/ IADD3 R3, R4, c[0x0][0x0], RZ ; /* 0x0000000004037a10 */
/* 0x000fc60007ffe0ff */
/*00b0*/ IMAD R2, R9, c[0x0][0x0], R2 ; /* 0x0000000009027a24 */
/* 0x000fe200078e0202 */
/*00c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*00d0*/ @!P0 BRA 0x160 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*00f0*/ @P0 STS [R0.X4], RZ ; /* 0x000000ff00000388 */
/* 0x0001e80000004800 */
/*0100*/ @P0 STS [R2], RZ ; /* 0x000000ff02000388 */
/* 0x0001e20000000800 */
/*0110*/ @P0 BRA 0x1b0 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0120*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea8000c1e1900 */
/*0130*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0043e80000004800 */
/*0140*/ STS [R2], RZ ; /* 0x000000ff02007388 */
/* 0x0003e20000000800 */
/*0150*/ BRA 0x1b0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.WIDE R8, R3, R9, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fe200078e0209 */
/*0170*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000eaa000c1e1900 */
/*0180*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ee8000c1e1900 */
/*0190*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0041e80000004800 */
/*01a0*/ STS [R2], R9 ; /* 0x0000000902007388 */
/* 0x0081e40000000800 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f25270 */
/*01e0*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0a7624 */
/* 0x000fc800078e00ff */
/*01f0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0200*/ IADD3 R5, R10, 0x1, RZ ; /* 0x000000010a057810 */
/* 0x000fe20007ffe0ff */
/*0210*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fc6000800063f */
/*0220*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fc60003f06070 */
/*0230*/ @!P1 BRA 0x310 ; /* 0x000000d000009947 */
/* 0x000ff40003800000 */
/*0240*/ HFMA2.MMA R6, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff067435 */
/* 0x000fe200000001ff */
/*0250*/ LEA R5, R0, 0x2, 0x1 ; /* 0x0000000200057811 */
/* 0x000fd200078e08ff */
/*0260*/ IMAD R9, R5, R6, -0x1 ; /* 0xffffffff05097424 */
/* 0x001fca00078e0206 */
/*0270*/ ISETP.GE.AND P1, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fda000bf26270 */
/*0280*/ @!P1 IMAD.IADD R7, R9, 0x1, -R6 ; /* 0x0000000109079824 */
/* 0x002fe200078e0a06 */
/*0290*/ @!P1 LDS R8, [R9.X4] ; /* 0x0000000009089984 */
/* 0x000fe20000004800 */
/*02a0*/ IMAD.SHL.U32 R6, R6, 0x2, RZ ; /* 0x0000000206067824 */
/* 0x000fc800078e00ff */
/*02b0*/ @!P1 LDS R7, [R7.X4] ; /* 0x0000000007079984 */
/* 0x000e240000004800 */
/*02c0*/ @!P1 FADD R8, R8, R7 ; /* 0x0000000708089221 */
/* 0x001fca0000000000 */
/*02d0*/ @!P1 STS [R9.X4], R8 ; /* 0x0000000809009388 */
/* 0x0001e80000004800 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02f0*/ ISETP.GT.U32.AND P1, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fda000bf24070 */
/*0300*/ @!P1 BRA 0x260 ; /* 0xffffff5000009947 */
/* 0x001fea000383ffff */
/*0310*/ @!P0 BRA 0x420 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0320*/ LEA.HI R5, R10, c[0x0][0x0], RZ, 0x1 ; /* 0x000000000a057a11 */
/* 0x000fe400078f08ff */
/*0330*/ LEA R10, R0, 0x2, 0x1 ; /* 0x00000002000a7811 */
/* 0x000fe400078e08ff */
/*0340*/ SHF.R.S32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fca0000011405 */
/*0350*/ IMAD R8, R10, R5.reuse, -0x1 ; /* 0xffffffff0a087424 */
/* 0x080fe200078e0205 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0370*/ IADD3 R6, R8, R5, RZ ; /* 0x0000000508067210 */
/* 0x000fc80007ffe0ff */
/*0380*/ ISETP.GE.U32.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x000fda000bf06070 */
/*0390*/ @!P0 IMAD.SHL.U32 R6, R8, 0x4, RZ ; /* 0x0000000408068824 */
/* 0x000fe400078e00ff */
/*03a0*/ @!P0 LDS R8, [R8.X4] ; /* 0x0000000008088984 */
/* 0x000fe60000004800 */
/*03b0*/ @!P0 LEA R6, R5, R6, 0x2 ; /* 0x0000000605068211 */
/* 0x000fe400078e10ff */
/*03c0*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fc60000011605 */
/*03d0*/ @!P0 LDS R7, [R6] ; /* 0x0000000006078984 */
/* 0x003e240000000800 */
/*03e0*/ @!P0 FADD R7, R7, R8 ; /* 0x0000000807078221 */
/* 0x001fca0000000000 */
/*03f0*/ @!P0 STS [R6], R7 ; /* 0x0000000706008388 */
/* 0x0001e20000000800 */
/*0400*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0410*/ @P0 BRA 0x350 ; /* 0xffffff3000000947 */
/* 0x001fea000383ffff */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0430*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*0440*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0450*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*0460*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x003e280000004800 */
/*0470*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0011e6000c101906 */
/*0480*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0490*/ LDS R3, [R2] ; /* 0x0000000002037984 */
/* 0x000e620000000800 */
/*04a0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x001fca0000000f00 */
/*04b0*/ IMAD.WIDE R4, R7, 0x4, R4 ; /* 0x0000000407047825 */
/* 0x000fca00078e0204 */
/*04c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x002fe2000c101906 */
/*04d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04e0*/ BRA 0x4e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4scanPfS_i
.globl _Z4scanPfS_i
.p2align 8
.type _Z4scanPfS_i,@function
_Z4scanPfS_i:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s5
s_lshl_b32 s7, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add3_u32 v3, s7, s5, v0
v_add_nc_u32_e32 v1, s7, v0
s_mov_b32 s7, exec_lo
v_cmpx_le_i32_e64 s4, v3
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_6
s_mov_b32 s8, exec_lo
v_cmpx_le_i32_e64 s4, v1
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v0
s_mov_b32 s9, 0
ds_store_b32 v2, v3
.LBB0_3:
s_or_saveexec_b32 s8, s8
v_mov_b32_e32 v4, s9
s_xor_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_6:
s_or_saveexec_b32 s7, s7
v_ashrrev_i32_e32 v2, 31, v1
s_xor_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_8
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v4, v[3:4], off
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt vmcnt(1)
ds_store_b32 v3, v5
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v3, s5, v0
v_cmp_eq_u16_e64 s6, s6, 0
s_mov_b32 s3, 1
s_lshl_b32 s2, s5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v3
s_and_b32 vcc_lo, exec_lo, s6
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_13
v_lshl_add_u32 v4, v0, 1, 2
s_branch .LBB0_11
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s6
s_lshl_b32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_cmp_gt_u32 s3, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_13
.LBB0_11:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v4, s3
s_mov_b32 s6, exec_lo
v_cmpx_ge_u32_e64 s2, v5
s_cbranch_execz .LBB0_10
v_add_nc_u32_e32 v5, -1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s3, v5
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b32_e32 v6, 2, v6
ds_load_b32 v6, v6
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v7
ds_store_b32 v5, v6
s_branch .LBB0_10
.LBB0_13:
s_cmp_lt_u32 s5, 2
s_cbranch_scc1 .LBB0_18
v_lshl_add_u32 v4, v0, 1, 2
s_mov_b32 s3, s5
s_branch .LBB0_16
.p2align 6
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s7
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s6
s_cbranch_scc0 .LBB0_18
.LBB0_16:
s_lshr_b32 s6, s3, 1
s_mov_b32 s7, exec_lo
v_mad_u32_u24 v6, v4, s6, -1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v5, s6, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v5
s_cbranch_execz .LBB0_15
v_lshlrev_b32_e32 v6, 2, v6
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v6, v6
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v6, v7
ds_store_b32 v5, v6
s_branch .LBB0_15
.LBB0_18:
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_lshlrev_b64 v[4:5], 2, v[1:2]
ds_load_b32 v6, v0
v_add_nc_u32_e32 v0, s5, v1
s_mov_b32 s2, exec_lo
v_add_co_u32 v1, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v5, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v6, off
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB0_20
v_lshlrev_b32_e32 v1, 2, v3
ds_load_b32 v2, v1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4scanPfS_i
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4scanPfS_i, .Lfunc_end0-_Z4scanPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4scanPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4scanPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000df603_00000000-6_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4scanPfS_iPfS_i
.type _Z26__device_stub__Z4scanPfS_iPfS_i, @function
_Z26__device_stub__Z4scanPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4scanPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z4scanPfS_iPfS_i, .-_Z26__device_stub__Z4scanPfS_iPfS_i
.globl _Z4scanPfS_i
.type _Z4scanPfS_i, @function
_Z4scanPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4scanPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4scanPfS_i, .-_Z4scanPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4scanPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4scanPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scan.hip"
.globl _Z19__device_stub__scanPfS_i # -- Begin function _Z19__device_stub__scanPfS_i
.p2align 4, 0x90
.type _Z19__device_stub__scanPfS_i,@function
_Z19__device_stub__scanPfS_i: # @_Z19__device_stub__scanPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4scanPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__scanPfS_i, .Lfunc_end0-_Z19__device_stub__scanPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4scanPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4scanPfS_i,@object # @_Z4scanPfS_i
.section .rodata,"a",@progbits
.globl _Z4scanPfS_i
.p2align 3, 0x0
_Z4scanPfS_i:
.quad _Z19__device_stub__scanPfS_i
.size _Z4scanPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4scanPfS_i"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__scanPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4scanPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
// INSERT KERNEL CODE HERE
__shared__ float sdata[512];
int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int tx = threadIdx.x;
float x = 0;
float y = 0;
if (i < size) {
x = in[i];
}
int secondLoad = i + blockDim.x;
if (secondLoad < size) {
y = in[secondLoad];
}
sdata[tx] = x + y;
__syncthreads();
for (int offset = blockDim.x / 2; offset > 0; offset >>= 1) {
if (tx < offset)
sdata[tx] += sdata[tx + offset];
__syncthreads();
}
if (tx == 0) {
out[blockIdx.x] = sdata[0];
}
} | code for sm_80
Function : _Z9reductionPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0050*/ IMAD.SHL.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007824 */
/* 0x001fc800078e00ff */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0209 */
/*0070*/ IADD3 R4, R0.reuse, c[0x0][0x0], RZ ; /* 0x0000000000047a10 */
/* 0x040fe40007ffe0ff */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0090*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fd60003f26070 */
/*00a0*/ @!P0 MOV R3, 0x4 ; /* 0x0000000400038802 */
/* 0x000fe40000000f00 */
/*00b0*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff059424 */
/* 0x000fc600078e00ff */
/*00c0*/ @!P0 IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000028625 */
/* 0x000fc800078e0203 */
/*00d0*/ @!P1 IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004049625 */
/* 0x000fe200078e0205 */
/*00e0*/ @!P0 LDG.E R7, [R2.64] ; /* 0x0000000602078981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ @!P1 LDG.E R6, [R4.64] ; /* 0x0000000604069981 */
/* 0x000ea2000c1e1900 */
/*0100*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0110*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0120*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*0130*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*0140*/ FADD R6, R7, R6 ; /* 0x0000000607067221 */
/* 0x004fca0000000000 */
/*0150*/ STS [R9.X4], R6 ; /* 0x0000000609007388 */
/* 0x0001e80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @!P1 BRA 0x240 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0180*/ SHF.L.U32 R0, R9, 0x2, RZ ; /* 0x0000000209007819 */
/* 0x001fe200000006ff */
/*0190*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01a0*/ ISETP.GE.AND P1, PT, R9, R3, PT ; /* 0x000000030900720c */
/* 0x000fda0003f26270 */
/*01b0*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x000fe200078e10ff */
/*01c0*/ @!P1 LDS R4, [R9.X4] ; /* 0x0000000009049984 */
/* 0x000fe20000004800 */
/*01d0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*01e0*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*01f0*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0200*/ @!P1 STS [R9.X4], R4 ; /* 0x0000000409009388 */
/* 0x0001e80000004800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0220*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0230*/ @P1 BRA 0x1a0 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*0240*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0250*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0260*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD.WIDE.U32 R2, R8, R3, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fca00078e0003 */
/*0280*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
// INSERT KERNEL CODE HERE
__shared__ float sdata[512];
int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int tx = threadIdx.x;
float x = 0;
float y = 0;
if (i < size) {
x = in[i];
}
int secondLoad = i + blockDim.x;
if (secondLoad < size) {
y = in[secondLoad];
}
sdata[tx] = x + y;
__syncthreads();
for (int offset = blockDim.x / 2; offset > 0; offset >>= 1) {
if (tx < offset)
sdata[tx] += sdata[tx + offset];
__syncthreads();
}
if (tx == 0) {
out[blockIdx.x] = sdata[0];
}
} | .file "tmpxft_00178551_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9reductionPfS_jPfS_j
.type _Z31__device_stub__Z9reductionPfS_jPfS_j, @function
_Z31__device_stub__Z9reductionPfS_jPfS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reductionPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9reductionPfS_jPfS_j, .-_Z31__device_stub__Z9reductionPfS_jPfS_j
.globl _Z9reductionPfS_j
.type _Z9reductionPfS_j, @function
_Z9reductionPfS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9reductionPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9reductionPfS_j, .-_Z9reductionPfS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9reductionPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
// INSERT KERNEL CODE HERE
__shared__ float sdata[512];
int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int tx = threadIdx.x;
float x = 0;
float y = 0;
if (i < size) {
x = in[i];
}
int secondLoad = i + blockDim.x;
if (secondLoad < size) {
y = in[secondLoad];
}
sdata[tx] = x + y;
__syncthreads();
for (int offset = blockDim.x / 2; offset > 0; offset >>= 1) {
if (tx < offset)
sdata[tx] += sdata[tx + offset];
__syncthreads();
}
if (tx == 0) {
out[blockIdx.x] = sdata[0];
}
} | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
// INSERT KERNEL CODE HERE
__shared__ float sdata[512];
int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int tx = threadIdx.x;
float x = 0;
float y = 0;
if (i < size) {
x = in[i];
}
int secondLoad = i + blockDim.x;
if (secondLoad < size) {
y = in[secondLoad];
}
sdata[tx] = x + y;
__syncthreads();
for (int offset = blockDim.x / 2; offset > 0; offset >>= 1) {
if (tx < offset)
sdata[tx] += sdata[tx + offset];
__syncthreads();
}
if (tx == 0) {
out[blockIdx.x] = sdata[0];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
// INSERT KERNEL CODE HERE
__shared__ float sdata[512];
int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int tx = threadIdx.x;
float x = 0;
float y = 0;
if (i < size) {
x = in[i];
}
int secondLoad = i + blockDim.x;
if (secondLoad < size) {
y = in[secondLoad];
}
sdata[tx] = x + y;
__syncthreads();
for (int offset = blockDim.x / 2; offset > 0; offset >>= 1) {
if (tx < offset)
sdata[tx] += sdata[tx + offset];
__syncthreads();
}
if (tx == 0) {
out[blockIdx.x] = sdata[0];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPfS_j
.globl _Z9reductionPfS_j
.p2align 8
.type _Z9reductionPfS_j,@function
_Z9reductionPfS_j:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s15, s3
v_lshl_add_u32 v1, s7, 1, v0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[1:2], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
v_dual_add_f32 v2, v4, v3 :: v_dual_lshlrev_b32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_5
.LBB0_9:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPfS_j
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPfS_j, .Lfunc_end0-_Z9reductionPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
// INSERT KERNEL CODE HERE
__shared__ float sdata[512];
int i = blockIdx.x * 2 * blockDim.x + threadIdx.x;
int tx = threadIdx.x;
float x = 0;
float y = 0;
if (i < size) {
x = in[i];
}
int secondLoad = i + blockDim.x;
if (secondLoad < size) {
y = in[secondLoad];
}
sdata[tx] = x + y;
__syncthreads();
for (int offset = blockDim.x / 2; offset > 0; offset >>= 1) {
if (tx < offset)
sdata[tx] += sdata[tx + offset];
__syncthreads();
}
if (tx == 0) {
out[blockIdx.x] = sdata[0];
}
} | .text
.file "kernel.hip"
.globl _Z24__device_stub__reductionPfS_j # -- Begin function _Z24__device_stub__reductionPfS_j
.p2align 4, 0x90
.type _Z24__device_stub__reductionPfS_j,@function
_Z24__device_stub__reductionPfS_j: # @_Z24__device_stub__reductionPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reductionPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPfS_j, .Lfunc_end0-_Z24__device_stub__reductionPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPfS_j,@object # @_Z9reductionPfS_j
.section .rodata,"a",@progbits
.globl _Z9reductionPfS_j
.p2align 3, 0x0
_Z9reductionPfS_j:
.quad _Z24__device_stub__reductionPfS_j
.size _Z9reductionPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9reductionPfS_j"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9reductionPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0050*/ IMAD.SHL.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007824 */
/* 0x001fc800078e00ff */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0209 */
/*0070*/ IADD3 R4, R0.reuse, c[0x0][0x0], RZ ; /* 0x0000000000047a10 */
/* 0x040fe40007ffe0ff */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0090*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fd60003f26070 */
/*00a0*/ @!P0 MOV R3, 0x4 ; /* 0x0000000400038802 */
/* 0x000fe40000000f00 */
/*00b0*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff059424 */
/* 0x000fc600078e00ff */
/*00c0*/ @!P0 IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000028625 */
/* 0x000fc800078e0203 */
/*00d0*/ @!P1 IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004049625 */
/* 0x000fe200078e0205 */
/*00e0*/ @!P0 LDG.E R7, [R2.64] ; /* 0x0000000602078981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ @!P1 LDG.E R6, [R4.64] ; /* 0x0000000604069981 */
/* 0x000ea2000c1e1900 */
/*0100*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0110*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*0120*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*0130*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*0140*/ FADD R6, R7, R6 ; /* 0x0000000607067221 */
/* 0x004fca0000000000 */
/*0150*/ STS [R9.X4], R6 ; /* 0x0000000609007388 */
/* 0x0001e80000004800 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ @!P1 BRA 0x240 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0180*/ SHF.L.U32 R0, R9, 0x2, RZ ; /* 0x0000000209007819 */
/* 0x001fe200000006ff */
/*0190*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01a0*/ ISETP.GE.AND P1, PT, R9, R3, PT ; /* 0x000000030900720c */
/* 0x000fda0003f26270 */
/*01b0*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x000fe200078e10ff */
/*01c0*/ @!P1 LDS R4, [R9.X4] ; /* 0x0000000009049984 */
/* 0x000fe20000004800 */
/*01d0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*01e0*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*01f0*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*0200*/ @!P1 STS [R9.X4], R4 ; /* 0x0000000409009388 */
/* 0x0001e80000004800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0220*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0230*/ @P1 BRA 0x1a0 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*0240*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*0250*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0260*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD.WIDE.U32 R2, R8, R3, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x000fca00078e0003 */
/*0280*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPfS_j
.globl _Z9reductionPfS_j
.p2align 8
.type _Z9reductionPfS_j,@function
_Z9reductionPfS_j:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s7, s15, s3
v_lshl_add_u32 v1, s7, 1, v0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v4, v[4:5], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[1:2], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt vmcnt(0)
v_dual_add_f32 v2, v4, v3 :: v_dual_lshlrev_b32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_5
.LBB0_9:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPfS_j
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPfS_j, .Lfunc_end0-_Z9reductionPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00178551_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9reductionPfS_jPfS_j
.type _Z31__device_stub__Z9reductionPfS_jPfS_j, @function
_Z31__device_stub__Z9reductionPfS_jPfS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reductionPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9reductionPfS_jPfS_j, .-_Z31__device_stub__Z9reductionPfS_jPfS_j
.globl _Z9reductionPfS_j
.type _Z9reductionPfS_j, @function
_Z9reductionPfS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9reductionPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9reductionPfS_j, .-_Z9reductionPfS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9reductionPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z24__device_stub__reductionPfS_j # -- Begin function _Z24__device_stub__reductionPfS_j
.p2align 4, 0x90
.type _Z24__device_stub__reductionPfS_j,@function
_Z24__device_stub__reductionPfS_j: # @_Z24__device_stub__reductionPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reductionPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPfS_j, .Lfunc_end0-_Z24__device_stub__reductionPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPfS_j,@object # @_Z9reductionPfS_j
.section .rodata,"a",@progbits
.globl _Z9reductionPfS_j
.p2align 3, 0x0
_Z9reductionPfS_j:
.quad _Z24__device_stub__reductionPfS_j
.size _Z9reductionPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9reductionPfS_j"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__
void hello_kernel() {
printf("hello world from cuda thread %d\n", int(threadIdx.x));
}
int main(void) {
hello_kernel<<<1, 32>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z12hello_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__
void hello_kernel() {
printf("hello world from cuda thread %d\n", int(threadIdx.x));
}
int main(void) {
hello_kernel<<<1, 32>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0015df80_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12hello_kernelvv
.type _Z31__device_stub__Z12hello_kernelvv, @function
_Z31__device_stub__Z12hello_kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12hello_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12hello_kernelvv, .-_Z31__device_stub__Z12hello_kernelvv
.globl _Z12hello_kernelv
.type _Z12hello_kernelv, @function
_Z12hello_kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12hello_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12hello_kernelv, .-_Z12hello_kernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12hello_kernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12hello_kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12hello_kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__
void hello_kernel() {
printf("hello world from cuda thread %d\n", int(threadIdx.x));
}
int main(void) {
hello_kernel<<<1, 32>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__
void hello_kernel() {
printf("hello world from cuda thread %d\n", int(threadIdx.x));
}
int main(void) {
hello_kernel<<<1, 32>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__
void hello_kernel() {
printf("hello world from cuda thread %d\n", int(threadIdx.x));
}
int main(void) {
hello_kernel<<<1, 32>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "hello.hip"
.globl _Z27__device_stub__hello_kernelv # -- Begin function _Z27__device_stub__hello_kernelv
.p2align 4, 0x90
.type _Z27__device_stub__hello_kernelv,@function
_Z27__device_stub__hello_kernelv: # @_Z27__device_stub__hello_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12hello_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__hello_kernelv, .Lfunc_end0-_Z27__device_stub__hello_kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12hello_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12hello_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12hello_kernelv,@object # @_Z12hello_kernelv
.section .rodata,"a",@progbits
.globl _Z12hello_kernelv
.p2align 3, 0x0
_Z12hello_kernelv:
.quad _Z27__device_stub__hello_kernelv
.size _Z12hello_kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12hello_kernelv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__hello_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12hello_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015df80_00000000-6_hello.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12hello_kernelvv
.type _Z31__device_stub__Z12hello_kernelvv, @function
_Z31__device_stub__Z12hello_kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12hello_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12hello_kernelvv, .-_Z31__device_stub__Z12hello_kernelvv
.globl _Z12hello_kernelv
.type _Z12hello_kernelv, @function
_Z12hello_kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12hello_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12hello_kernelv, .-_Z12hello_kernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12hello_kernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12hello_kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12hello_kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello.hip"
.globl _Z27__device_stub__hello_kernelv # -- Begin function _Z27__device_stub__hello_kernelv
.p2align 4, 0x90
.type _Z27__device_stub__hello_kernelv,@function
_Z27__device_stub__hello_kernelv: # @_Z27__device_stub__hello_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12hello_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__hello_kernelv, .Lfunc_end0-_Z27__device_stub__hello_kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12hello_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12hello_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12hello_kernelv,@object # @_Z12hello_kernelv
.section .rodata,"a",@progbits
.globl _Z12hello_kernelv
.p2align 3, 0x0
_Z12hello_kernelv:
.quad _Z27__device_stub__hello_kernelv
.size _Z12hello_kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12hello_kernelv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__hello_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12hello_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdio>
#include <string>
#define TOGG(k) ( ( ( (k) & 1 ) << 5 ) )
#define RAN(charac) ( 65 + ( charac % 26 ) + TOGG ( charac ) )
using namespace std;
__global__
void RunLengthEncodingComputation (char *orig, int *_encoXst, int n) {
int index = ( (blockIdx.x * blockDim.x) + threadIdx.x );
index <<= 7;
if(orig[index] == orig[index-1])
while(index < n && orig[index] == orig[index-1])
++index;
for (int i = index; i < fminf(index + 128, n); )
{
char temp = orig[i];
int t_ = i;
while (i < n && temp == orig[i])
++i;
_encoXst[t_] = i;
}
}
int main() {
int n;
cin >> n;
char *s = new char[n];
int i = 0;
for( ; i < n; ) {
char in = RAN ( rand() );
int loop = rand() & 63, k = i;
while(i < min(k+loop, n))
s[i++] = in;
}
s[i] = '\0';
fprintf(fopen("input.txt", "w"), "%s", s);
char *cudas;
int *_encoXst, *_inter = new int[n];
int threads = (1 << 7);
int blocks = ( ( n>>14 ) + ( ( n & ( (1<<14)-1 ) ) != 0 ) );
cout << threads << " : " << blocks << endl;
cudaMalloc (&cudas, n*sizeof(char));
cudaMalloc (&cudas, n*sizeof(char));
cudaMalloc (&_encoXst, n*sizeof(int));
cudaMemcpy (cudas, s, n*sizeof(char), cudaMemcpyHostToDevice);
RunLengthEncodingComputation <<<blocks, threads>>> (cudas, _encoXst, n);
cudaDeviceSynchronize();
cudaMemcpy(_inter, _encoXst, n*sizeof(int), cudaMemcpyDeviceToHost);
string ans;
int sum = 0;
for(int i = 0; i < n; i = _inter[i]) {
ans += s[i] + to_string(_inter[i]-i);
sum += _inter[i]-i;
}
// cout << ans << endl;
fprintf(fopen("output.txt", "w"), "%s", ans.c_str());
int length_ans = ans.length();
printf("Length: %d\nCompressed Length: %d\nCompression Achievement: %f\n", sum, length_ans, (float)(sum+length_ans-1)/(length_ans));
} | code for sm_80
Function : _Z28RunLengthEncodingComputationPcPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD.SHL.U32 R7, R0, 0x80, RZ ; /* 0x0000008000077824 */
/* 0x000fca00078e00ff */
/*0060*/ IADD3 R2, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007027a10 */
/* 0x000fc80007f1e0ff */
/*0070*/ LEA.HI.X.SX32 R3, R7, c[0x0][0x164], 0x1, P0 ; /* 0x0000590007037a11 */
/* 0x000fca00000f0eff */
/*0080*/ LDG.E.U8 R0, [R2.64+-0x1] ; /* 0xffffff0402007981 */
/* 0x000ea8000c1e1100 */
/*0090*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1100 */
/*00a0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ I2F R9, c[0x0][0x170] ; /* 0x00005c0000097b06 */
/* 0x000e220000201400 */
/*00c0*/ BSSY B0, 0x180 ; /* 0x000000b000007945 */
/* 0x000fe40003800000 */
/*00d0*/ ISETP.NE.OR P0, PT, R5, R0, P0 ; /* 0x000000000500720c */
/* 0x004fda0000705670 */
/*00e0*/ @P0 BRA 0x170 ; /* 0x0000008000000947 */
/* 0x001fea0003800000 */
/*00f0*/ IADD3 R2, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007027a10 */
/* 0x000fc80007f1e0ff */
/*0100*/ LEA.HI.X.SX32 R3, R7, c[0x0][0x164], 0x1, P0 ; /* 0x0000590007037a11 */
/* 0x000fca00000f0eff */
/*0110*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*0120*/ ISETP.NE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x004fda0003f05270 */
/*0130*/ @P0 BRA 0x170 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0150*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fda0003f06270 */
/*0160*/ @!P0 BRA 0xf0 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R0, R7, 0x80, RZ ; /* 0x0000008007007810 */
/* 0x000fe20007ffe0ff */
/*0190*/ I2F R2, R7 ; /* 0x0000000700027306 */
/* 0x000ff00000201400 */
/*01a0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000e240000201400 */
/*01b0*/ FMNMX R9, R0, R9, PT ; /* 0x0000000900097209 */
/* 0x001fc80003800000 */
/*01c0*/ FSETP.GT.AND P0, PT, R9, R2, PT ; /* 0x000000020900720b */
/* 0x000fda0003f04000 */
/*01d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe20003f06270 */
/*01f0*/ BSSY B0, 0x2f0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0200*/ SHF.R.S32.HI R11, RZ, 0x1f, R7.reuse ; /* 0x0000001fff0b7819 */
/* 0x100fe20000011407 */
/*0210*/ IMAD.MOV.U32 R0, RZ, RZ, R7 ; /* 0x000000ffff007224 */
/* 0x000fd400078e0007 */
/*0220*/ @P0 BRA 0x2e0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R2, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007027a10 */
/* 0x000fc80007f1e0ff */
/*0240*/ IADD3.X R3, R11, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000b037a10 */
/* 0x000fca00007fe4ff */
/*0250*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000168000c1e1100 */
/*0260*/ IADD3 R2, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007027a10 */
/* 0x001fc80007f1e0ff */
/*0270*/ LEA.HI.X.SX32 R3, R7, c[0x0][0x164], 0x1, P0 ; /* 0x0000590007037a11 */
/* 0x000fca00000f0eff */
/*0280*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*0290*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x024fda0003f05270 */
/*02a0*/ @P0 BRA 0x2e0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*02b0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*02c0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fda0003f06270 */
/*02d0*/ @!P0 BRA 0x260 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0300*/ LEA.HI.X R3, R0, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe400000f140b */
/*0310*/ I2F R0, R7 ; /* 0x0000000700007306 */
/* 0x000e260000201400 */
/*0320*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e2000c101904 */
/*0330*/ FSETP.GT.AND P0, PT, R9, R0, PT ; /* 0x000000000900720b */
/* 0x001fda0003f04000 */
/*0340*/ @P0 BRA 0x1e0 ; /* 0xfffffe9000000947 */
/* 0x002fea000383ffff */
/*0350*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0360*/ BRA 0x360; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdio>
#include <string>
#define TOGG(k) ( ( ( (k) & 1 ) << 5 ) )
#define RAN(charac) ( 65 + ( charac % 26 ) + TOGG ( charac ) )
using namespace std;
__global__
void RunLengthEncodingComputation (char *orig, int *_encoXst, int n) {
int index = ( (blockIdx.x * blockDim.x) + threadIdx.x );
index <<= 7;
if(orig[index] == orig[index-1])
while(index < n && orig[index] == orig[index-1])
++index;
for (int i = index; i < fminf(index + 128, n); )
{
char temp = orig[i];
int t_ = i;
while (i < n && temp == orig[i])
++i;
_encoXst[t_] = i;
}
}
int main() {
int n;
cin >> n;
char *s = new char[n];
int i = 0;
for( ; i < n; ) {
char in = RAN ( rand() );
int loop = rand() & 63, k = i;
while(i < min(k+loop, n))
s[i++] = in;
}
s[i] = '\0';
fprintf(fopen("input.txt", "w"), "%s", s);
char *cudas;
int *_encoXst, *_inter = new int[n];
int threads = (1 << 7);
int blocks = ( ( n>>14 ) + ( ( n & ( (1<<14)-1 ) ) != 0 ) );
cout << threads << " : " << blocks << endl;
cudaMalloc (&cudas, n*sizeof(char));
cudaMalloc (&cudas, n*sizeof(char));
cudaMalloc (&_encoXst, n*sizeof(int));
cudaMemcpy (cudas, s, n*sizeof(char), cudaMemcpyHostToDevice);
RunLengthEncodingComputation <<<blocks, threads>>> (cudas, _encoXst, n);
cudaDeviceSynchronize();
cudaMemcpy(_inter, _encoXst, n*sizeof(int), cudaMemcpyDeviceToHost);
string ans;
int sum = 0;
for(int i = 0; i < n; i = _inter[i]) {
ans += s[i] + to_string(_inter[i]-i);
sum += _inter[i]-i;
}
// cout << ans << endl;
fprintf(fopen("output.txt", "w"), "%s", ans.c_str());
int length_ans = ans.length();
printf("Length: %d\nCompressed Length: %d\nCompression Achievement: %f\n", sum, length_ans, (float)(sum+length_ans-1)/(length_ans));
} | .file "tmpxft_000d5518_00000000-6_RunLengthEncoding.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z28RunLengthEncodingComputationPcPiiPcPii
.type _Z51__device_stub__Z28RunLengthEncodingComputationPcPiiPcPii, @function
_Z51__device_stub__Z28RunLengthEncodingComputationPcPiiPcPii:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28RunLengthEncodingComputationPcPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z51__device_stub__Z28RunLengthEncodingComputationPcPiiPcPii, .-_Z51__device_stub__Z28RunLengthEncodingComputationPcPiiPcPii
.globl _Z28RunLengthEncodingComputationPcPii
.type _Z28RunLengthEncodingComputationPcPii, @function
_Z28RunLengthEncodingComputationPcPii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z28RunLengthEncodingComputationPcPiiPcPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z28RunLengthEncodingComputationPcPii, .-_Z28RunLengthEncodingComputationPcPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.LC1:
.string "input.txt"
.LC2:
.string "%s"
.LC3:
.string " : "
.LC4:
.string "basic_string::append"
.LC5:
.string "output.txt"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Length: %d\nCompressed Length: %d\nCompression Achievement: %f\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3669
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $408, %rsp
.cfi_def_cfa_offset 464
movq %fs:40, %rax
movq %rax, 392(%rsp)
xorl %eax, %eax
leaq 36(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
.LEHB0:
call _ZNSirsERi@PLT
movslq 36(%rsp), %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
cmpl $0, 36(%rsp)
jle .L55
movl $0, %ebp
movq %rax, %r12
.L15:
call rand@PLT
movl %eax, %r13d
call rand@PLT
movl %eax, %ebx
sall $5, %ebx
andl $32, %ebx
movslq %r13d, %rdx
imulq $1321528399, %rdx, %rdx
sarq $35, %rdx
movl %r13d, %eax
sarl $31, %eax
subl %eax, %edx
imull $26, %edx, %edx
subl %edx, %r13d
leal 65(%rbx,%r13), %ebx
call rand@PLT
movl 36(%rsp), %esi
andl $63, %eax
movl %eax, %ecx
addl %ebp, %ecx
cmpl %esi, %ecx
cmovg %esi, %ecx
cmpl %ebp, %ecx
jle .L13
movslq %ebp, %rax
addq %r12, %rax
movl %ecx, %edx
subl %ebp, %edx
addq %rax, %rdx
.L14:
movb %bl, (%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L14
movl %ecx, %ebp
.L13:
cmpl %ebp, %esi
jg .L15
.L12:
movslq %ebp, %rbp
movq 8(%rsp), %r14
movb $0, (%r14,%rbp)
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rdi
movq %r14, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
movslq 36(%rsp), %rax
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L16
leaq 0(,%rax,4), %rdi
call _Znam@PLT
movq %rax, 16(%rsp)
movl 36(%rsp), %eax
testl $16383, %eax
setne %bl
movzbl %bl, %ebx
sarl $14, %eax
addl %eax, %ebx
movl $128, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movslq 36(%rsp), %rsi
leaq 40(%rsp), %rbp
movq %rbp, %rdi
call cudaMalloc@PLT
movslq 36(%rsp), %rsi
movq %rbp, %rdi
call cudaMalloc@PLT
movslq 36(%rsp), %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movslq 36(%rsp), %rdx
movl $1, %ecx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %ebx, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L74
.L17:
call cudaDeviceSynchronize@PLT
movslq 36(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rax
movq %rax, 80(%rsp)
movq $0, 88(%rsp)
movb $0, 96(%rsp)
cmpl $0, 36(%rsp)
jle .L56
movl $0, %r13d
movl $0, 28(%rsp)
leaq 112(%rsp), %rax
movq %rax, (%rsp)
jmp .L49
.L55:
movl $0, %ebp
jmp .L12
.L16:
movq 392(%rsp), %rax
subq %fs:40, %rax
je .L19
call __stack_chk_fail@PLT
.L19:
call __cxa_throw_bad_array_new_length@PLT
.L74:
movl 36(%rsp), %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z51__device_stub__Z28RunLengthEncodingComputationPcPiiPcPii
.LEHE0:
jmp .L17
.L57:
movl $1, %ebx
.L24:
leaq 128(%rsp), %rax
movq %rax, 112(%rsp)
leal 1(%rbx,%r12), %esi
movl $45, %edx
movq (%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructEmc@PLT
movzbl %r12b, %r12d
addq 112(%rsp), %r12
movabsq $3688503277381496880, %rax
movabsq $3976738051646829616, %rdx
movq %rax, 176(%rsp)
movq %rdx, 184(%rsp)
movabsq $3544667369688283184, %rax
movabsq $3832902143785906737, %rdx
movq %rax, 192(%rsp)
movq %rdx, 200(%rsp)
movabsq $4121136918051239473, %rax
movabsq $3689066235924983858, %rdx
movq %rax, 208(%rsp)
movq %rdx, 216(%rsp)
movabsq $3977301010190316594, %rax
movabsq $3545230328231770162, %rdx
movq %rax, 224(%rsp)
movq %rdx, 232(%rsp)
movabsq $3833465102329393715, %rax
movabsq $4121699876594726451, %rdx
movq %rax, 240(%rsp)
movq %rdx, 248(%rsp)
movabsq $3689629194468470836, %rax
movabsq $3977863968733803572, %rdx
movq %rax, 256(%rsp)
movq %rdx, 264(%rsp)
movabsq $3545793286775257140, %rax
movabsq $3834028060872880693, %rdx
movq %rax, 272(%rsp)
movq %rdx, 280(%rsp)
movabsq $4122262835138213429, %rax
movabsq $3690192153011957814, %rdx
movq %rax, 288(%rsp)
movq %rdx, 296(%rsp)
movabsq $3978426927277290550, %rax
movabsq $3546356245318744118, %rdx
movq %rax, 304(%rsp)
movq %rdx, 312(%rsp)
movabsq $3834591019416367671, %rax
movabsq $4122825793681700407, %rdx
movq %rax, 320(%rsp)
movq %rdx, 328(%rsp)
movabsq $3690755111555444792, %rax
movabsq $3978989885820777528, %rdx
movq %rax, 336(%rsp)
movq %rdx, 344(%rsp)
movabsq $3546919203862231096, %rax
movabsq $3835153977959854649, %rdx
movq %rax, 352(%rsp)
movq %rdx, 360(%rsp)
movabsq $4122263930388298034, %rax
movabsq $16106987313379638, %rdx
movq %rax, 361(%rsp)
movq %rdx, 369(%rsp)
cmpl $99, %ebp
ja .L34
.L30:
addl %ebp, %ebp
leal 1(%rbp), %eax
movzbl 176(%rsp,%rax), %eax
movb %al, 1(%r12)
movl %ebp, %ebp
movzbl 176(%rsp,%rbp), %ebp
.L36:
movb %bpl, (%r12)
movq 8(%rsp), %rax
movsbl (%rax,%r14), %r8d
movl $1, %ecx
movl $0, %edx
movl $0, %esi
movq (%rsp), %rdi
.LEHB1:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE14_M_replace_auxEmmmc@PLT
.LEHE1:
jmp .L75
.L58:
movl $1, %ebx
.L25:
addl $2, %ebx
.L32:
leaq 128(%rsp), %rax
movq %rax, 112(%rsp)
leal (%r12,%rbx), %esi
movl $45, %edx
movq (%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructEmc@PLT
movzbl %r12b, %r12d
addq 112(%rsp), %r12
movabsq $3688503277381496880, %rax
movabsq $3976738051646829616, %rdx
movq %rax, 176(%rsp)
movq %rdx, 184(%rsp)
movabsq $3544667369688283184, %rax
movabsq $3832902143785906737, %rdx
movq %rax, 192(%rsp)
movq %rdx, 200(%rsp)
movabsq $4121136918051239473, %rax
movabsq $3689066235924983858, %rdx
movq %rax, 208(%rsp)
movq %rdx, 216(%rsp)
movabsq $3977301010190316594, %rax
movabsq $3545230328231770162, %rdx
movq %rax, 224(%rsp)
movq %rdx, 232(%rsp)
movabsq $3833465102329393715, %rax
movabsq $4121699876594726451, %rdx
movq %rax, 240(%rsp)
movq %rdx, 248(%rsp)
movabsq $3689629194468470836, %rax
movabsq $3977863968733803572, %rdx
movq %rax, 256(%rsp)
movq %rdx, 264(%rsp)
movabsq $3545793286775257140, %rax
movabsq $3834028060872880693, %rdx
movq %rax, 272(%rsp)
movq %rdx, 280(%rsp)
movabsq $4122262835138213429, %rax
movabsq $3690192153011957814, %rdx
movq %rax, 288(%rsp)
movq %rdx, 296(%rsp)
movabsq $3978426927277290550, %rax
movabsq $3546356245318744118, %rdx
movq %rax, 304(%rsp)
movq %rdx, 312(%rsp)
movabsq $3834591019416367671, %rax
movabsq $4122825793681700407, %rdx
movq %rax, 320(%rsp)
movq %rdx, 328(%rsp)
movabsq $3690755111555444792, %rax
movabsq $3978989885820777528, %rdx
movq %rax, 336(%rsp)
movq %rdx, 344(%rsp)
movabsq $3546919203862231096, %rax
movabsq $3835153977959854649, %rdx
movq %rax, 352(%rsp)
movq %rdx, 360(%rsp)
movabsq $4122263930388298034, %rax
movabsq $16106987313379638, %rdx
movq %rax, 361(%rsp)
movq %rdx, 369(%rsp)
subl $1, %ebx
.L34:
movl %ebp, %edx
imulq $1374389535, %rdx, %rdx
shrq $37, %rdx
imull $100, %edx, %ecx
movl %ebp, %eax
subl %ecx, %eax
addl %eax, %eax
movl %ebp, %ecx
movl %edx, %ebp
movl %ebx, %edx
leal 1(%rax), %esi
movzbl 176(%rsp,%rsi), %esi
movb %sil, (%r12,%rdx)
leal -1(%rbx), %edx
movl %eax, %eax
movzbl 176(%rsp,%rax), %eax
movb %al, (%r12,%rdx)
subl $2, %ebx
cmpl $9999, %ecx
ja .L34
cmpl $999, %ecx
ja .L30
.L35:
addl $48, %ebp
jmp .L36
.L59:
movl $1, %ebx
jmp .L26
.L75:
leaq 160(%rsp), %rdx
movq %rdx, 144(%rsp)
movq (%rax), %rdx
leaq 16(%rax), %rcx
cmpq %rcx, %rdx
je .L76
movq %rdx, 144(%rsp)
movq 16(%rax), %rdx
movq %rdx, 160(%rsp)
.L44:
movq 8(%rax), %rdx
movq %rdx, 152(%rsp)
movq %rcx, (%rax)
movq $0, 8(%rax)
movb $0, 16(%rax)
movq 144(%rsp), %rsi
movabsq $4611686018427387903, %rax
subq 88(%rsp), %rax
cmpq %rdx, %rax
jb .L77
leaq 80(%rsp), %rdi
.LEHB2:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L78
.L76:
leaq 160(%rsp), %r8
movq 8(%rax), %rdi
leaq 1(%rdi), %rsi
movq %r8, %r9
movq %rcx, %rdx
cmpl $8, %esi
jnb .L79
.L38:
movl $0, %edi
testb $4, %sil
je .L41
movl (%rdx), %edi
movl %edi, (%r9)
movl $4, %edi
.L41:
testb $2, %sil
je .L42
movzwl (%rdx,%rdi), %r8d
movw %r8w, (%r9,%rdi)
addq $2, %rdi
.L42:
testb $1, %sil
je .L44
movzbl (%rdx,%rdi), %edx
movb %dl, (%r9,%rdi)
jmp .L44
.L79:
movl %esi, %r10d
andl $-8, %r10d
movl $0, %edx
.L39:
movl %edx, %edi
movq (%rcx,%rdi), %r9
movq %r9, (%r8,%rdi)
addl $8, %edx
cmpl %r10d, %edx
jb .L39
movl %edx, %edx
leaq (%r8,%rdx), %r9
addq %rcx, %rdx
jmp .L38
.L77:
movq 392(%rsp), %rax
subq %fs:40, %rax
jne .L80
leaq .LC4(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.LEHE2:
.L62:
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L51:
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L52:
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 392(%rsp), %rax
subq %fs:40, %rax
je .L53
call __stack_chk_fail@PLT
.L80:
call __stack_chk_fail@PLT
.L78:
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .L47
movq 160(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L47:
movq 112(%rsp), %rdi
leaq 128(%rsp), %rax
cmpq %rax, %rdi
je .L48
movq 128(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L48:
movl (%r15), %eax
movl %eax, %edx
subl %r13d, %edx
addl %edx, 28(%rsp)
cmpl 36(%rsp), %eax
jge .L20
movl %eax, %r13d
.L49:
movslq %r13d, %r14
movq 16(%rsp), %rax
leaq (%rax,%r14,4), %r15
movl (%r15), %eax
subl %r13d, %eax
movl %eax, %r12d
shrl $31, %r12d
movl %eax, %ebp
negl %ebp
cmovs %eax, %ebp
cmpl $9, %ebp
jbe .L23
cmpl $99, %ebp
jbe .L57
cmpl $999, %ebp
jbe .L58
cmpl $9999, %ebp
jbe .L59
movl %ebp, %eax
movl $1, %ebx
movabsq $3777893186295716171, %rcx
.L27:
movl %eax, %eax
mulq %rcx
shrq $11, %rdx
movl %edx, %eax
addl $4, %ebx
cmpl $9, %edx
jbe .L32
cmpl $99, %edx
jbe .L24
cmpl $999, %edx
jbe .L25
cmpl $9999, %edx
ja .L27
.L26:
addl $3, %ebx
jmp .L32
.L56:
movl $0, 28(%rsp)
.L20:
movq 80(%rsp), %rbx
leaq .LC0(%rip), %rsi
leaq .LC5(%rip), %rdi
.LEHB3:
call fopen@PLT
movq %rax, %rdi
movq %rbx, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
movq 88(%rsp), %rax
movl %eax, %ecx
movl 28(%rsp), %edi
leal -1(%rdi,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl %edi, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.LEHE3:
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 392(%rsp), %rax
subq %fs:40, %rax
jne .L81
movl $0, %eax
addq $408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L51
.L63:
endbr64
movq %rax, %rbx
jmp .L52
.L53:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L23:
leaq 112(%rsp), %rdi
leaq 128(%rsp), %rax
movq %rax, 112(%rsp)
leal 1(%r12), %esi
movl %esi, %esi
movl $45, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructEmc@PLT
movzbl %r12b, %r12d
addq 112(%rsp), %r12
jmp .L35
.L81:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3669:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3669-.LLSDACSB3669
.LLSDACSB3669:
.uleb128 .LEHB0-.LFB3669
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3669
.uleb128 .LEHE1-.LEHB1
.uleb128 .L61-.LFB3669
.uleb128 0
.uleb128 .LEHB2-.LFB3669
.uleb128 .LEHE2-.LEHB2
.uleb128 .L62-.LFB3669
.uleb128 0
.uleb128 .LEHB3-.LFB3669
.uleb128 .LEHE3-.LEHB3
.uleb128 .L63-.LFB3669
.uleb128 0
.uleb128 .LEHB4-.LFB3669
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3669:
.text
.size main, .-main
.section .rodata.str1.8
.align 8
.LC7:
.string "_Z28RunLengthEncodingComputationPcPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z28RunLengthEncodingComputationPcPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdio>
#include <string>
#define TOGG(k) ( ( ( (k) & 1 ) << 5 ) )
#define RAN(charac) ( 65 + ( charac % 26 ) + TOGG ( charac ) )
using namespace std;
__global__
void RunLengthEncodingComputation (char *orig, int *_encoXst, int n) {
int index = ( (blockIdx.x * blockDim.x) + threadIdx.x );
index <<= 7;
if(orig[index] == orig[index-1])
while(index < n && orig[index] == orig[index-1])
++index;
for (int i = index; i < fminf(index + 128, n); )
{
char temp = orig[i];
int t_ = i;
while (i < n && temp == orig[i])
++i;
_encoXst[t_] = i;
}
}
int main() {
int n;
cin >> n;
char *s = new char[n];
int i = 0;
for( ; i < n; ) {
char in = RAN ( rand() );
int loop = rand() & 63, k = i;
while(i < min(k+loop, n))
s[i++] = in;
}
s[i] = '\0';
fprintf(fopen("input.txt", "w"), "%s", s);
char *cudas;
int *_encoXst, *_inter = new int[n];
int threads = (1 << 7);
int blocks = ( ( n>>14 ) + ( ( n & ( (1<<14)-1 ) ) != 0 ) );
cout << threads << " : " << blocks << endl;
cudaMalloc (&cudas, n*sizeof(char));
cudaMalloc (&cudas, n*sizeof(char));
cudaMalloc (&_encoXst, n*sizeof(int));
cudaMemcpy (cudas, s, n*sizeof(char), cudaMemcpyHostToDevice);
RunLengthEncodingComputation <<<blocks, threads>>> (cudas, _encoXst, n);
cudaDeviceSynchronize();
cudaMemcpy(_inter, _encoXst, n*sizeof(int), cudaMemcpyDeviceToHost);
string ans;
int sum = 0;
for(int i = 0; i < n; i = _inter[i]) {
ans += s[i] + to_string(_inter[i]-i);
sum += _inter[i]-i;
}
// cout << ans << endl;
fprintf(fopen("output.txt", "w"), "%s", ans.c_str());
int length_ans = ans.length();
printf("Length: %d\nCompressed Length: %d\nCompression Achievement: %f\n", sum, length_ans, (float)(sum+length_ans-1)/(length_ans));
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <string>
#define TOGG(k) ( ( ( (k) & 1 ) << 5 ) )
#define RAN(charac) ( 65 + ( charac % 26 ) + TOGG ( charac ) )
using namespace std;
__global__
void RunLengthEncodingComputation (char *orig, int *_encoXst, int n) {
int index = ( (blockIdx.x * blockDim.x) + threadIdx.x );
index <<= 7;
if(orig[index] == orig[index-1])
while(index < n && orig[index] == orig[index-1])
++index;
for (int i = index; i < fminf(index + 128, n); )
{
char temp = orig[i];
int t_ = i;
while (i < n && temp == orig[i])
++i;
_encoXst[t_] = i;
}
}
int main() {
int n;
cin >> n;
char *s = new char[n];
int i = 0;
for( ; i < n; ) {
char in = RAN ( rand() );
int loop = rand() & 63, k = i;
while(i < min(k+loop, n))
s[i++] = in;
}
s[i] = '\0';
fprintf(fopen("input.txt", "w"), "%s", s);
char *cudas;
int *_encoXst, *_inter = new int[n];
int threads = (1 << 7);
int blocks = ( ( n>>14 ) + ( ( n & ( (1<<14)-1 ) ) != 0 ) );
cout << threads << " : " << blocks << endl;
hipMalloc (&cudas, n*sizeof(char));
hipMalloc (&cudas, n*sizeof(char));
hipMalloc (&_encoXst, n*sizeof(int));
hipMemcpy (cudas, s, n*sizeof(char), hipMemcpyHostToDevice);
RunLengthEncodingComputation <<<blocks, threads>>> (cudas, _encoXst, n);
hipDeviceSynchronize();
hipMemcpy(_inter, _encoXst, n*sizeof(int), hipMemcpyDeviceToHost);
string ans;
int sum = 0;
for(int i = 0; i < n; i = _inter[i]) {
ans += s[i] + to_string(_inter[i]-i);
sum += _inter[i]-i;
}
// cout << ans << endl;
fprintf(fopen("output.txt", "w"), "%s", ans.c_str());
int length_ans = ans.length();
printf("Length: %d\nCompressed Length: %d\nCompression Achievement: %f\n", sum, length_ans, (float)(sum+length_ans-1)/(length_ans));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <string>
#define TOGG(k) ( ( ( (k) & 1 ) << 5 ) )
#define RAN(charac) ( 65 + ( charac % 26 ) + TOGG ( charac ) )
using namespace std;
__global__
void RunLengthEncodingComputation (char *orig, int *_encoXst, int n) {
int index = ( (blockIdx.x * blockDim.x) + threadIdx.x );
index <<= 7;
if(orig[index] == orig[index-1])
while(index < n && orig[index] == orig[index-1])
++index;
for (int i = index; i < fminf(index + 128, n); )
{
char temp = orig[i];
int t_ = i;
while (i < n && temp == orig[i])
++i;
_encoXst[t_] = i;
}
}
int main() {
int n;
cin >> n;
char *s = new char[n];
int i = 0;
for( ; i < n; ) {
char in = RAN ( rand() );
int loop = rand() & 63, k = i;
while(i < min(k+loop, n))
s[i++] = in;
}
s[i] = '\0';
fprintf(fopen("input.txt", "w"), "%s", s);
char *cudas;
int *_encoXst, *_inter = new int[n];
int threads = (1 << 7);
int blocks = ( ( n>>14 ) + ( ( n & ( (1<<14)-1 ) ) != 0 ) );
cout << threads << " : " << blocks << endl;
hipMalloc (&cudas, n*sizeof(char));
hipMalloc (&cudas, n*sizeof(char));
hipMalloc (&_encoXst, n*sizeof(int));
hipMemcpy (cudas, s, n*sizeof(char), hipMemcpyHostToDevice);
RunLengthEncodingComputation <<<blocks, threads>>> (cudas, _encoXst, n);
hipDeviceSynchronize();
hipMemcpy(_inter, _encoXst, n*sizeof(int), hipMemcpyDeviceToHost);
string ans;
int sum = 0;
for(int i = 0; i < n; i = _inter[i]) {
ans += s[i] + to_string(_inter[i]-i);
sum += _inter[i]-i;
}
// cout << ans << endl;
fprintf(fopen("output.txt", "w"), "%s", ans.c_str());
int length_ans = ans.length();
printf("Length: %d\nCompressed Length: %d\nCompression Achievement: %f\n", sum, length_ans, (float)(sum+length_ans-1)/(length_ans));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28RunLengthEncodingComputationPcPii
.globl _Z28RunLengthEncodingComputationPcPii
.p2align 8
.type _Z28RunLengthEncodingComputationPcPii,@function
_Z28RunLengthEncodingComputationPcPii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
v_add_lshl_u32 v0, s15, v0, 7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v2, vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_clause 0x1
global_load_u8 v4, v[2:3], off
global_load_u8 v2, v[2:3], off offset:-1
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, v4, v2
s_and_b32 s3, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_b32 s10, exec_lo, s9
v_mov_b32_e32 v0, s6
s_or_b32 s7, s10, s7
s_and_not1_b32 s3, s3, exec_lo
s_and_b32 s10, s8, exec_lo
s_or_b32 s3, s3, s10
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
s_or_b32 s8, s8, exec_lo
s_or_b32 s9, s9, exec_lo
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
s_clause 0x1
global_load_u8 v0, v[3:4], off
global_load_u8 v3, v[3:4], off offset:-1
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, v0, v3
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_2
v_add_co_u32 v3, vcc_lo, v1, 1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
s_and_not1_b32 s9, s9, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s6, v3
s_and_not1_b32 s8, s8, exec_lo
s_and_b32 s11, vcc_lo, exec_lo
s_or_b32 s9, s9, s11
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s7, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s7
v_mov_b32_e32 v0, v1
s_or_b32 exec_lo, exec_lo, s3
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v1, 0x80, v0
v_cvt_f32_i32_e32 v2, s6
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v1
v_min_f32_e32 v7, v1, v2
v_cvt_f32_i32_e32 v1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f32_e32 v7, v1
s_cbranch_execz .LBB0_19
s_load_b64 s[2:3], s[0:1], 0x8
s_mov_b32 s1, 0
s_branch .LBB0_12
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s7
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_cvt_f32_i32_e32 v3, v0
v_cmp_ngt_f32_e32 vcc_lo, v7, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s2, v1
v_add_co_ci_u32_e64 v2, s0, s3, v2, s0
s_or_b32 s1, vcc_lo, s1
global_store_b32 v[1:2], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_19
.LBB0_12:
v_ashrrev_i32_e32 v2, 31, v0
v_mov_b32_e32 v1, v0
s_mov_b32 s0, exec_lo
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB0_11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_mov_b32_e32 v6, v2
s_mov_b32 s8, 0
v_mov_b32_e32 v5, v1
global_load_u8 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v8, 0xff, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_15
.p2align 6
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_b32 s11, exec_lo, s10
v_mov_b32_e32 v0, s6
s_or_b32 s8, s11, s8
s_and_not1_b32 s7, s7, exec_lo
s_and_b32 s11, s9, exec_lo
s_or_b32 s7, s7, s11
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_17
.LBB0_15:
v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
s_or_b32 s9, s9, exec_lo
s_or_b32 s10, s10, exec_lo
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
global_load_u8 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u16_e64 v8, v0
s_cbranch_execz .LBB0_14
v_add_co_u32 v5, vcc_lo, v3, 1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
s_and_not1_b32 s10, s10, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s6, v5
s_and_not1_b32 s9, s9, exec_lo
s_and_b32 s12, vcc_lo, exec_lo
s_or_b32 s10, s10, s12
s_branch .LBB0_14
.LBB0_17:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s8, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s7, exec_lo, s8
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, v3
s_branch .LBB0_10
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28RunLengthEncodingComputationPcPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28RunLengthEncodingComputationPcPii, .Lfunc_end0-_Z28RunLengthEncodingComputationPcPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28RunLengthEncodingComputationPcPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28RunLengthEncodingComputationPcPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdio>
#include <string>
#define TOGG(k) ( ( ( (k) & 1 ) << 5 ) )
#define RAN(charac) ( 65 + ( charac % 26 ) + TOGG ( charac ) )
using namespace std;
__global__
void RunLengthEncodingComputation (char *orig, int *_encoXst, int n) {
int index = ( (blockIdx.x * blockDim.x) + threadIdx.x );
index <<= 7;
if(orig[index] == orig[index-1])
while(index < n && orig[index] == orig[index-1])
++index;
for (int i = index; i < fminf(index + 128, n); )
{
char temp = orig[i];
int t_ = i;
while (i < n && temp == orig[i])
++i;
_encoXst[t_] = i;
}
}
int main() {
int n;
cin >> n;
char *s = new char[n];
int i = 0;
for( ; i < n; ) {
char in = RAN ( rand() );
int loop = rand() & 63, k = i;
while(i < min(k+loop, n))
s[i++] = in;
}
s[i] = '\0';
fprintf(fopen("input.txt", "w"), "%s", s);
char *cudas;
int *_encoXst, *_inter = new int[n];
int threads = (1 << 7);
int blocks = ( ( n>>14 ) + ( ( n & ( (1<<14)-1 ) ) != 0 ) );
cout << threads << " : " << blocks << endl;
hipMalloc (&cudas, n*sizeof(char));
hipMalloc (&cudas, n*sizeof(char));
hipMalloc (&_encoXst, n*sizeof(int));
hipMemcpy (cudas, s, n*sizeof(char), hipMemcpyHostToDevice);
RunLengthEncodingComputation <<<blocks, threads>>> (cudas, _encoXst, n);
hipDeviceSynchronize();
hipMemcpy(_inter, _encoXst, n*sizeof(int), hipMemcpyDeviceToHost);
string ans;
int sum = 0;
for(int i = 0; i < n; i = _inter[i]) {
ans += s[i] + to_string(_inter[i]-i);
sum += _inter[i]-i;
}
// cout << ans << endl;
fprintf(fopen("output.txt", "w"), "%s", ans.c_str());
int length_ans = ans.length();
printf("Length: %d\nCompressed Length: %d\nCompression Achievement: %f\n", sum, length_ans, (float)(sum+length_ans-1)/(length_ans));
} | .text
.file "RunLengthEncoding.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z43__device_stub__RunLengthEncodingComputationPcPii # -- Begin function _Z43__device_stub__RunLengthEncodingComputationPcPii
.p2align 4, 0x90
.type _Z43__device_stub__RunLengthEncodingComputationPcPii,@function
_Z43__device_stub__RunLengthEncodingComputationPcPii: # @_Z43__device_stub__RunLengthEncodingComputationPcPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28RunLengthEncodingComputationPcPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z43__device_stub__RunLengthEncodingComputationPcPii, .Lfunc_end0-_Z43__device_stub__RunLengthEncodingComputationPcPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
leaq 12(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movslq 12(%rsp), %r14
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Znam
movq %rax, 56(%rsp) # 8-byte Spill
xorl %ebx, %ebx
testq %r14, %r14
jg .LBB1_3
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_2: # %.loopexit67
# in Loop: Header=BB1_3 Depth=1
cmpl 12(%rsp), %ebx
jge .LBB1_6
.LBB1_3: # %.lr.ph89
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
.cfi_escape 0x2e, 0x00
callq rand
movl %eax, %ebp
.cfi_escape 0x2e, 0x00
callq rand
movl %eax, %r14d
.cfi_escape 0x2e, 0x00
callq rand
andl $63, %eax
addl %ebx, %eax
movl 12(%rsp), %ecx
cmpl %ecx, %eax
cmovgel %ecx, %eax
cmpl %eax, %ebx
jge .LBB1_2
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB1_3 Depth=1
movslq %ebp, %rcx
imulq $1321528399, %rcx, %rdx # imm = 0x4EC4EC4F
movq %rdx, %rsi
shrq $63, %rsi
sarq $35, %rdx
addl %esi, %edx
leal (%rdx,%rdx,4), %esi
leal (%rsi,%rsi,4), %esi
addl %edx, %esi
subl %esi, %ecx
shll $5, %r14d
andl $32, %r14d
leal (%r14,%rcx), %esi
addl $65, %esi
movslq %ebx, %r14
movq 56(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%r14), %rdi
movl %ebx, %edx
notl %edx
addl %eax, %edx
incq %rdx
.cfi_escape 0x2e, 0x00
movl %eax, %ebp
callq memset@PLT
movslq %ebp, %rax
subq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
decq %rax
cmpq %rax, %r14
jne .LBB1_5
# %bb.1: # %.loopexit67.loopexit
# in Loop: Header=BB1_3 Depth=1
subl %eax, %ebx
jmp .LBB1_2
.LBB1_6: # %._crit_edge.loopexit
movslq %ebx, %rbx
.LBB1_7: # %._crit_edge
movq 56(%rsp), %r14 # 8-byte Reload
movb $0, (%r14,%rbx)
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq %rax, %rsi
callq fputs@PLT
movslq 12(%rsp), %rbx
leaq (,%rbx,4), %rax
testq %rbx, %rbx
movq $-1, %rdi
cmovnsq %rax, %rdi
.cfi_escape 0x2e, 0x00
callq _Znam
movq %rax, %r14
movl %ebx, %ebp
sarl $14, %ebp
andl $16383, %ebx # imm = 0x3FFF
cmpl $1, %ebx
sbbl $-1, %ebp
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $128, %esi
callq _ZNSolsEi
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_71
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_10
# %bb.9:
movzbl 67(%r15), %ecx
jmp .LBB1_11
.LBB1_10:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB1_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movslq 12(%rsp), %rsi
.cfi_escape 0x2e, 0x00
leaq 160(%rsp), %r15
movq %r15, %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
.cfi_escape 0x2e, 0x00
leaq 152(%rsp), %rdi
callq hipMalloc
movq 160(%rsp), %rdi
movslq 12(%rsp), %rdx
.cfi_escape 0x2e, 0x00
movq 56(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movl %ebp, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $128, %rdx
.cfi_escape 0x2e, 0x00
xorl %r15d, %r15d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.12:
movq 160(%rsp), %rax
movq 152(%rsp), %rcx
movl 12(%rsp), %edx
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movl %edx, 108(%rsp)
leaq 192(%rsp), %rax
movq %rax, 16(%rsp)
leaq 184(%rsp), %rax
movq %rax, 24(%rsp)
leaq 108(%rsp), %rax
movq %rax, 32(%rsp)
.cfi_escape 0x2e, 0x00
leaq 112(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 176(%rsp), %rdx
leaq 168(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 16(%rsp), %r9
movl $_Z28RunLengthEncodingComputationPcPii, %edi
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
pushq 184(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_13:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
movq 152(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 32(%rsp), %rax
movq %rax, 16(%rsp)
movq $0, 24(%rsp)
movb $0, 32(%rsp)
cmpl $0, 12(%rsp)
jle .LBB1_19
# %bb.14: # %.lr.ph94
xorl %eax, %eax
movl $3518437209, %edx # imm = 0xD1B71759
xorl %r15d, %r15d
movq %r14, 144(%rsp) # 8-byte Spill
jmp .LBB1_15
.p2align 4, 0x90
.LBB1_60: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit53
# in Loop: Header=BB1_15 Depth=1
movl (%r14,%r13,4), %eax
subl %r13d, %r15d
addl %eax, %r15d
cmpl 12(%rsp), %eax
movl $3518437209, %edx # imm = 0xD1B71759
jge .LBB1_19
.LBB1_15: # =>This Loop Header: Depth=1
# Child Loop BB1_17 Depth 2
# Child Loop BB1_37 Depth 2
movslq %eax, %r13
movl (%r14,%r13,4), %ebx
subl %r13d, %ebx
movl %ebx, %r12d
negl %r12d
cmovsl %ebx, %r12d
movl $1, %r14d
cmpl $10, %r12d
jb .LBB1_27
# %bb.16: # %.lr.ph.i.i.preheader
# in Loop: Header=BB1_15 Depth=1
movl $4, %r14d
movl %r12d, %eax
.p2align 4, 0x90
.LBB1_17: # %.lr.ph.i.i
# Parent Loop BB1_15 Depth=1
# => This Inner Loop Header: Depth=2
cmpl $99, %eax
jbe .LBB1_18
# %bb.22: # in Loop: Header=BB1_17 Depth=2
cmpl $999, %eax # imm = 0x3E7
jbe .LBB1_23
# %bb.24: # in Loop: Header=BB1_17 Depth=2
cmpl $10000, %eax # imm = 0x2710
jb .LBB1_27
# %bb.25: # in Loop: Header=BB1_17 Depth=2
movl %eax, %ecx
imulq %rdx, %rcx
shrq $45, %rcx
addl $4, %r14d
cmpl $99999, %eax # imm = 0x1869F
movl %ecx, %eax
ja .LBB1_17
# %bb.26: # %_ZNSt8__detail14__to_chars_lenIjEEjT_i.exit.i.loopexit
# in Loop: Header=BB1_15 Depth=1
addl $-3, %r14d
jmp .LBB1_27
.LBB1_18: # in Loop: Header=BB1_15 Depth=1
addl $-2, %r14d
jmp .LBB1_27
.LBB1_23: # in Loop: Header=BB1_15 Depth=1
decl %r14d
.p2align 4, 0x90
.LBB1_27: # %_ZNSt8__detail14__to_chars_lenIjEEjT_i.exit.i
# in Loop: Header=BB1_15 Depth=1
movq 56(%rsp), %rax # 8-byte Reload
movzbl (%rax,%r13), %r8d
shrl $31, %ebx
leal (%r14,%rbx), %ebp
leaq 88(%rsp), %rax
movq %rax, 72(%rsp)
cmpl $16, %ebp
jb .LBB1_30
# %bb.28: # in Loop: Header=BB1_15 Depth=1
movq %r15, 64(%rsp) # 8-byte Spill
movq %r13, %r15
movl %r8d, %r13d
leaq 1(%rbp), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp1:
# %bb.29: # %.noexc.i
# in Loop: Header=BB1_15 Depth=1
movq %rax, 72(%rsp)
movq %rbp, 88(%rsp)
movl %r13d, %r8d
movq %r15, %r13
movq 64(%rsp), %r15 # 8-byte Reload
.LBB1_30: # in Loop: Header=BB1_15 Depth=1
testq %rbp, %rbp
je .LBB1_34
# %bb.31: # in Loop: Header=BB1_15 Depth=1
movq 72(%rsp), %rdi
cmpl $1, %ebp
jne .LBB1_33
# %bb.32: # in Loop: Header=BB1_15 Depth=1
movb $45, (%rdi)
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_33: # in Loop: Header=BB1_15 Depth=1
.cfi_escape 0x2e, 0x00
movl $45, %esi
movq %rbp, %rdx
movq %r15, 64(%rsp) # 8-byte Spill
movq %r13, %r15
movl %r8d, %r13d
callq memset@PLT
movl %r13d, %r8d
movq %r15, %r13
movq 64(%rsp), %r15 # 8-byte Reload
.LBB1_34: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEmcRKS3_.exit.i
# in Loop: Header=BB1_15 Depth=1
movq %rbp, 80(%rsp)
movq 72(%rsp), %rax
movb $0, (%rax,%rbp)
movl %ebx, %eax
addq 72(%rsp), %rax
cmpl $100, %r12d
jb .LBB1_35
# %bb.36: # %.lr.ph.preheader.i.i
# in Loop: Header=BB1_15 Depth=1
addl $-2, %r14d
.p2align 4, 0x90
.LBB1_37: # %.lr.ph.i11.i
# Parent Loop BB1_15 Depth=1
# => This Inner Loop Header: Depth=2
leal 1(%r14), %edx
movl %r12d, %ecx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
shrq $37, %rcx
imull $100, %ecx, %esi
movl %r12d, %edi
subl %esi, %edi
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits+1(%rdi,%rdi), %esi
movb %sil, (%rax,%rdx)
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits(%rdi,%rdi), %edx
movl %r14d, %esi
movb %dl, (%rax,%rsi)
addl $-2, %r14d
cmpl $9999, %r12d # imm = 0x270F
movl %ecx, %r12d
ja .LBB1_37
# %bb.38: # %._crit_edge.i.i
# in Loop: Header=BB1_15 Depth=1
cmpl $10, %ecx
jb .LBB1_40
.LBB1_39: # in Loop: Header=BB1_15 Depth=1
movl %ecx, %ecx
leaq (%rcx,%rcx), %rdx
movl %edx, %edx
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits+1(%rdx), %edx
movb %dl, 1(%rax)
movzbl .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits(%rcx,%rcx), %ecx
jmp .LBB1_41
.p2align 4, 0x90
.LBB1_35: # in Loop: Header=BB1_15 Depth=1
movl %r12d, %ecx
cmpl $10, %ecx
jae .LBB1_39
.LBB1_40: # in Loop: Header=BB1_15 Depth=1
orb $48, %cl
.LBB1_41: # %_ZNSt7__cxx119to_stringEi.exit
# in Loop: Header=BB1_15 Depth=1
movq 144(%rsp), %r14 # 8-byte Reload
leaq 128(%rsp), %r12
movb %cl, (%rax)
.Ltmp3:
.cfi_escape 0x2e, 0x00
movsbl %r8b, %ecx
movl $1, %edx
leaq 72(%rsp), %rdi
xorl %esi, %esi
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmmc
.Ltmp4:
# %bb.42: # %.noexc
# in Loop: Header=BB1_15 Depth=1
movq %r12, 112(%rsp)
movq (%rax), %rcx
movq %rax, %rbp
addq $16, %rbp
cmpq %rbp, %rcx
je .LBB1_43
# %bb.44: # %.critedge.i.i44
# in Loop: Header=BB1_15 Depth=1
movq %rcx, 112(%rsp)
movq (%rbp), %rcx
movq %rcx, 128(%rsp)
jmp .LBB1_45
.p2align 4, 0x90
.LBB1_43: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i45
# in Loop: Header=BB1_15 Depth=1
movq 8(%rax), %rdx
incq %rdx
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movq %rbp, %rsi
movq %rax, %rbx
callq memcpy@PLT
movq %rbx, %rax
.LBB1_45: # %_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EES5_OS8_.exit
# in Loop: Header=BB1_15 Depth=1
movq 8(%rax), %rcx
movq %rcx, 120(%rsp)
movq %rbp, (%rax)
movq $0, 8(%rax)
movb $0, 16(%rax)
movq 120(%rsp), %r8
movq 24(%rsp), %rsi
movq %rsi, %rax
movabsq $9223372036854775807, %rcx # imm = 0x7FFFFFFFFFFFFFFF
xorq %rcx, %rax
cmpq %r8, %rax
jb .LBB1_46
# %bb.48: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i
# in Loop: Header=BB1_15 Depth=1
movq 16(%rsp), %rdi
movl $15, %eax
leaq 32(%rsp), %rcx
cmpq %rcx, %rdi
je .LBB1_50
# %bb.49: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i
# in Loop: Header=BB1_15 Depth=1
movq 32(%rsp), %rax
.LBB1_50: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i.i
# in Loop: Header=BB1_15 Depth=1
movq 112(%rsp), %rcx
leaq (%rsi,%r8), %rbx
cmpq %rax, %rbx
jbe .LBB1_51
# %bb.55: # in Loop: Header=BB1_15 Depth=1
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
xorl %edx, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp7:
jmp .LBB1_56
.p2align 4, 0x90
.LBB1_51: # in Loop: Header=BB1_15 Depth=1
testq %r8, %r8
je .LBB1_56
# %bb.52: # in Loop: Header=BB1_15 Depth=1
addq %rsi, %rdi
cmpq $1, %r8
jne .LBB1_54
# %bb.53: # in Loop: Header=BB1_15 Depth=1
movzbl (%rcx), %eax
movb %al, (%rdi)
jmp .LBB1_56
.LBB1_54: # in Loop: Header=BB1_15 Depth=1
.cfi_escape 0x2e, 0x00
movq %rcx, %rsi
movq %r8, %rdx
callq memcpy@PLT
.p2align 4, 0x90
.LBB1_56: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEpLERKS4_.exit
# in Loop: Header=BB1_15 Depth=1
movq %rbx, 24(%rsp)
movq 16(%rsp), %rax
movb $0, (%rax,%rbx)
movq 112(%rsp), %rdi
cmpq %r12, %rdi
je .LBB1_58
# %bb.57: # %.critedge.i.i48
# in Loop: Header=BB1_15 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_58: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit50
# in Loop: Header=BB1_15 Depth=1
movq 72(%rsp), %rdi
leaq 88(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_60
# %bb.59: # %.critedge.i.i51
# in Loop: Header=BB1_15 Depth=1
.cfi_escape 0x2e, 0x00
callq _ZdlPv
jmp .LBB1_60
.LBB1_19: # %._crit_edge95
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %edi
movl $.L.str.1, %esi
callq fopen
movq 16(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movq %rax, %rsi
callq fputs@PLT
movl 24(%rsp), %edx
leal (%r15,%rdx), %eax
decl %eax
cvtsi2ss %eax, %xmm0
cvtsi2ss %edx, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %edi
movl %r15d, %esi
# kill: def $edx killed $edx killed $rdx
movb $1, %al
callq printf
movq 16(%rsp), %rdi
leaq 32(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_21
# %bb.20: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_21: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_46:
.cfi_def_cfa_offset 256
.Ltmp9:
.cfi_escape 0x2e, 0x00
movl $.L.str.10, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp10:
# %bb.47: # %.noexc46
.LBB1_71:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_72:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq __clang_call_terminate
.LBB1_62: # %.loopexit
.Ltmp8:
jmp .LBB1_64
.LBB1_61:
.Ltmp5:
movq %rax, %rbx
jmp .LBB1_66
.LBB1_63: # %.loopexit.split-lp
.Ltmp11:
.LBB1_64:
movq %rax, %rbx
movq 112(%rsp), %rdi
leaq 128(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_66
# %bb.65: # %.critedge.i.i54
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_66: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit56
movq 72(%rsp), %rdi
leaq 88(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_68
# %bb.67: # %.critedge.i.i57
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_68: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit59
movq 16(%rsp), %rdi
leaq 32(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_70
# %bb.69: # %.critedge.i.i60
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_70: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit62
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 1 # On action: 1
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end1-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end2:
.size __clang_call_terminate, .Lfunc_end2-__clang_call_terminate
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmmc,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmmc,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmmc # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmmc
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmmc,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmmc: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmmc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r15
movq %rsi, %r14
movq 8(%rdi), %rcx
movq %rcx, %rdx
subq %rsi, %rdx
jb .LBB3_17
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8_M_checkEmPKc.exit
movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
xorq %rcx, %rax
cmpq %r15, %rax
jb .LBB3_18
# %bb.2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
movq %rdi, %rbx
leaq (%rcx,%r15), %r12
movq (%rdi), %rsi
addq $16, %rdi
movl $15, %eax
cmpq %rdi, %rsi
je .LBB3_4
# %bb.3: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
movq 16(%rbx), %rax
.LBB3_4: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
cmpq %rax, %r12
jbe .LBB3_5
# %bb.11:
movq %rbx, %rdi
movq %r14, %rsi
xorl %edx, %edx
xorl %ecx, %ecx
movq %r15, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.LBB3_12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_moveEPcPKcm.exit.i
testq %r15, %r15
je .LBB3_16
# %bb.13:
addq (%rbx), %r14
cmpq $1, %r15
jne .LBB3_15
# %bb.14:
movb %bpl, (%r14)
jmp .LBB3_16
.LBB3_5:
testq %r15, %r15
je .LBB3_12
# %bb.6:
cmpq %r14, %rcx
je .LBB3_12
# %bb.7:
testq %rdx, %rdx
je .LBB3_12
# %bb.8:
addq %r14, %rsi
leaq (%rsi,%r15), %rdi
cmpq $1, %rdx
jne .LBB3_10
# %bb.9:
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB3_12
.LBB3_15:
movzbl %bpl, %esi
movq %r14, %rdi
movq %r15, %rdx
callq memset@PLT
.LBB3_16: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE14_M_replace_auxEmmmc.exit
movq %r12, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r12)
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_10:
.cfi_def_cfa_offset 48
callq memmove@PLT
jmp .LBB3_12
.LBB3_17:
movl $.L.str.9, %edi
movl $.L.str.6, %esi
movq %r14, %rdx
xorl %eax, %eax
callq _ZSt24__throw_out_of_range_fmtPKcz
.LBB3_18:
movl $.L.str.7, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end3:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmmc, .Lfunc_end3-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6insertEmmc
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_startproc
# %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbp
movq %rcx, 32(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %rbx
movq (%rdi), %r14
movq 8(%rdi), %r12
movq %r8, (%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
subq %rdx, %rbp
leaq 16(%rdi), %rcx
movl $15, %eax
cmpq %rcx, %r14
je .LBB4_2
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
movq 16(%rbx), %rax
.LBB4_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
addq %r12, %rbp
js .LBB4_26
# %bb.3:
cmpq %rax, %rbp
jbe .LBB4_6
# %bb.4:
addq %rax, %rax
cmpq %rax, %rbp
jae .LBB4_6
# %bb.5:
movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF
cmpq %rbp, %rax
cmovbq %rax, %rbp
.LBB4_6:
movq %rbp, %rdi
incq %rdi
js .LBB4_27
# %bb.7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
movq %rcx, 24(%rsp) # 8-byte Spill
callq _Znwm
movq %rax, %r13
testq %r15, %r15
je .LBB4_11
# %bb.8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
cmpq $1, %r15
jne .LBB4_10
# %bb.9:
movzbl (%r14), %eax
movb %al, (%r13)
jmp .LBB4_11
.LBB4_10:
movq %r13, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB4_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
movq %r14, 8(%rsp) # 8-byte Spill
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rax,%r15), %r14
movq 32(%rsp), %rsi # 8-byte Reload
testq %rsi, %rsi
movq (%rsp), %rdx # 8-byte Reload
je .LBB4_18
# %bb.12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
testq %rdx, %rdx
je .LBB4_18
# %bb.13:
je .LBB4_18
# %bb.14:
leaq (%r15,%r13), %rdi
cmpq $1, %rdx
jne .LBB4_16
# %bb.15:
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB4_17
.LBB4_16:
callq memcpy@PLT
.LBB4_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
movq (%rsp), %rdx # 8-byte Reload
.LBB4_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
cmpq %r14, %r12
je .LBB4_23
# %bb.19:
subq %r14, %r12
je .LBB4_23
# %bb.20:
movq %r13, %rdi
addq %r15, %rdi
addq %rdx, %rdi
addq 8(%rsp), %r15 # 8-byte Folded Reload
addq 16(%rsp), %r15 # 8-byte Folded Reload
cmpq $1, %r12
jne .LBB4_22
# %bb.21:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB4_23
.LBB4_22:
movq %r15, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB4_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit27
movq 8(%rsp), %rdi # 8-byte Reload
cmpq 24(%rsp), %rdi # 8-byte Folded Reload
je .LBB4_25
# %bb.24: # %.critedge.i
callq _ZdlPv
.LBB4_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
movq %r13, (%rbx)
movq %rbp, 16(%rbx)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_27:
.cfi_def_cfa_offset 96
callq _ZSt17__throw_bad_allocv
.LBB4_26:
movl $.L.str.8, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end4:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm, .Lfunc_end4-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28RunLengthEncodingComputationPcPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28RunLengthEncodingComputationPcPii,@object # @_Z28RunLengthEncodingComputationPcPii
.section .rodata,"a",@progbits
.globl _Z28RunLengthEncodingComputationPcPii
.p2align 3, 0x0
_Z28RunLengthEncodingComputationPcPii:
.quad _Z43__device_stub__RunLengthEncodingComputationPcPii
.size _Z28RunLengthEncodingComputationPcPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "input.txt"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " : "
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "output.txt"
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Length: %d\nCompressed Length: %d\nCompression Achievement: %f\n"
.size .L.str.5, 62
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "basic_string::insert"
.size .L.str.6, 21
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "basic_string::_M_replace_aux"
.size .L.str.7, 29
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "basic_string::_M_create"
.size .L.str.8, 24
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%s: __pos (which is %zu) > this->size() (which is %zu)"
.size .L.str.9, 55
.type .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits,@object # @__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits
.section .rodata.str1.16,"aMS",@progbits,1
.p2align 4, 0x0
.L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits:
.asciz "00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899"
.size .L__const._ZNSt8__detail18__to_chars_10_implIjEEvPcjT_.__digits, 201
.type .L.str.10,@object # @.str.10
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.10:
.asciz "basic_string::append"
.size .L.str.10, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28RunLengthEncodingComputationPcPii"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__RunLengthEncodingComputationPcPii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z28RunLengthEncodingComputationPcPii
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28RunLengthEncodingComputationPcPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD.SHL.U32 R7, R0, 0x80, RZ ; /* 0x0000008000077824 */
/* 0x000fca00078e00ff */
/*0060*/ IADD3 R2, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007027a10 */
/* 0x000fc80007f1e0ff */
/*0070*/ LEA.HI.X.SX32 R3, R7, c[0x0][0x164], 0x1, P0 ; /* 0x0000590007037a11 */
/* 0x000fca00000f0eff */
/*0080*/ LDG.E.U8 R0, [R2.64+-0x1] ; /* 0xffffff0402007981 */
/* 0x000ea8000c1e1100 */
/*0090*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1100 */
/*00a0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ I2F R9, c[0x0][0x170] ; /* 0x00005c0000097b06 */
/* 0x000e220000201400 */
/*00c0*/ BSSY B0, 0x180 ; /* 0x000000b000007945 */
/* 0x000fe40003800000 */
/*00d0*/ ISETP.NE.OR P0, PT, R5, R0, P0 ; /* 0x000000000500720c */
/* 0x004fda0000705670 */
/*00e0*/ @P0 BRA 0x170 ; /* 0x0000008000000947 */
/* 0x001fea0003800000 */
/*00f0*/ IADD3 R2, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007027a10 */
/* 0x000fc80007f1e0ff */
/*0100*/ LEA.HI.X.SX32 R3, R7, c[0x0][0x164], 0x1, P0 ; /* 0x0000590007037a11 */
/* 0x000fca00000f0eff */
/*0110*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*0120*/ ISETP.NE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x004fda0003f05270 */
/*0130*/ @P0 BRA 0x170 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0150*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fda0003f06270 */
/*0160*/ @!P0 BRA 0xf0 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R0, R7, 0x80, RZ ; /* 0x0000008007007810 */
/* 0x000fe20007ffe0ff */
/*0190*/ I2F R2, R7 ; /* 0x0000000700027306 */
/* 0x000ff00000201400 */
/*01a0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000e240000201400 */
/*01b0*/ FMNMX R9, R0, R9, PT ; /* 0x0000000900097209 */
/* 0x001fc80003800000 */
/*01c0*/ FSETP.GT.AND P0, PT, R9, R2, PT ; /* 0x000000020900720b */
/* 0x000fda0003f04000 */
/*01d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe20003f06270 */
/*01f0*/ BSSY B0, 0x2f0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0200*/ SHF.R.S32.HI R11, RZ, 0x1f, R7.reuse ; /* 0x0000001fff0b7819 */
/* 0x100fe20000011407 */
/*0210*/ IMAD.MOV.U32 R0, RZ, RZ, R7 ; /* 0x000000ffff007224 */
/* 0x000fd400078e0007 */
/*0220*/ @P0 BRA 0x2e0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R2, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007027a10 */
/* 0x000fc80007f1e0ff */
/*0240*/ IADD3.X R3, R11, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000b037a10 */
/* 0x000fca00007fe4ff */
/*0250*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000168000c1e1100 */
/*0260*/ IADD3 R2, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007027a10 */
/* 0x001fc80007f1e0ff */
/*0270*/ LEA.HI.X.SX32 R3, R7, c[0x0][0x164], 0x1, P0 ; /* 0x0000590007037a11 */
/* 0x000fca00000f0eff */
/*0280*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*0290*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x024fda0003f05270 */
/*02a0*/ @P0 BRA 0x2e0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*02b0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*02c0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fda0003f06270 */
/*02d0*/ @!P0 BRA 0x260 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0300*/ LEA.HI.X R3, R0, c[0x0][0x16c], R11, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe400000f140b */
/*0310*/ I2F R0, R7 ; /* 0x0000000700007306 */
/* 0x000e260000201400 */
/*0320*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e2000c101904 */
/*0330*/ FSETP.GT.AND P0, PT, R9, R0, PT ; /* 0x000000000900720b */
/* 0x001fda0003f04000 */
/*0340*/ @P0 BRA 0x1e0 ; /* 0xfffffe9000000947 */
/* 0x002fea000383ffff */
/*0350*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0360*/ BRA 0x360; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28RunLengthEncodingComputationPcPii
.globl _Z28RunLengthEncodingComputationPcPii
.p2align 8
.type _Z28RunLengthEncodingComputationPcPii,@function
_Z28RunLengthEncodingComputationPcPii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
v_add_lshl_u32 v0, s15, v0, 7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v2, vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_clause 0x1
global_load_u8 v4, v[2:3], off
global_load_u8 v2, v[2:3], off offset:-1
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, v4, v2
s_and_b32 s3, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v3, v0
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_b32 s10, exec_lo, s9
v_mov_b32_e32 v0, s6
s_or_b32 s7, s10, s7
s_and_not1_b32 s3, s3, exec_lo
s_and_b32 s10, s8, exec_lo
s_or_b32 s3, s3, s10
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
s_or_b32 s8, s8, exec_lo
s_or_b32 s9, s9, exec_lo
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
s_clause 0x1
global_load_u8 v0, v[3:4], off
global_load_u8 v3, v[3:4], off offset:-1
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, v0, v3
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_2
v_add_co_u32 v3, vcc_lo, v1, 1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
s_and_not1_b32 s9, s9, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s6, v3
s_and_not1_b32 s8, s8, exec_lo
s_and_b32 s11, vcc_lo, exec_lo
s_or_b32 s9, s9, s11
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s7
s_and_saveexec_b32 s7, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s7
v_mov_b32_e32 v0, v1
s_or_b32 exec_lo, exec_lo, s3
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v1, 0x80, v0
v_cvt_f32_i32_e32 v2, s6
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v1
v_min_f32_e32 v7, v1, v2
v_cvt_f32_i32_e32 v1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f32_e32 v7, v1
s_cbranch_execz .LBB0_19
s_load_b64 s[2:3], s[0:1], 0x8
s_mov_b32 s1, 0
s_branch .LBB0_12
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s7
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_cvt_f32_i32_e32 v3, v0
v_cmp_ngt_f32_e32 vcc_lo, v7, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, s2, v1
v_add_co_ci_u32_e64 v2, s0, s3, v2, s0
s_or_b32 s1, vcc_lo, s1
global_store_b32 v[1:2], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_19
.LBB0_12:
v_ashrrev_i32_e32 v2, 31, v0
v_mov_b32_e32 v1, v0
s_mov_b32 s0, exec_lo
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB0_11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_mov_b32_e32 v6, v2
s_mov_b32 s8, 0
v_mov_b32_e32 v5, v1
global_load_u8 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v8, 0xff, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_15
.p2align 6
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_b32 s11, exec_lo, s10
v_mov_b32_e32 v0, s6
s_or_b32 s8, s11, s8
s_and_not1_b32 s7, s7, exec_lo
s_and_b32 s11, s9, exec_lo
s_or_b32 s7, s7, s11
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_17
.LBB0_15:
v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
s_or_b32 s9, s9, exec_lo
s_or_b32 s10, s10, exec_lo
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
global_load_u8 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u16_e64 v8, v0
s_cbranch_execz .LBB0_14
v_add_co_u32 v5, vcc_lo, v3, 1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
s_and_not1_b32 s10, s10, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s6, v5
s_and_not1_b32 s9, s9, exec_lo
s_and_b32 s12, vcc_lo, exec_lo
s_or_b32 s10, s10, s12
s_branch .LBB0_14
.LBB0_17:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s8, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s7, exec_lo, s8
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, v3
s_branch .LBB0_10
.LBB0_19:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28RunLengthEncodingComputationPcPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28RunLengthEncodingComputationPcPii, .Lfunc_end0-_Z28RunLengthEncodingComputationPcPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28RunLengthEncodingComputationPcPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28RunLengthEncodingComputationPcPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void sorted_mean_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* mean_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the mean
value of quantity u for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
double sum_u;
unsigned int n_macroparticles; // in current slice
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
sum_u = 0;
n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles == 0) {
mean_u[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
}
mean_u[sid] = sum_u / n_macroparticles;
}
}
}
__global__ void sorted_std_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* cov_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the
standard deviation of quantity u for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
double sum_u, mean_u, l_cov_u, du;
unsigned int n_macroparticles; // in current slice
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
sum_u = 0;
n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles <= 1) {
cov_u[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
}
mean_u = sum_u / n_macroparticles;
l_cov_u = 0;
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
du = u[pid] - mean_u;
l_cov_u += du * du;
}
cov_u[sid] = sqrt(l_cov_u / (n_macroparticles - 1));
}
}
}
__global__ void sorted_cov_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
double* v, // 2nd array of particles
unsigned int n_slices,
double* cov_uv) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the
covariance of the quantities u,v for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
double sum_u = 0.;
double sum_v = 0.;
unsigned int n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles <= 1) {
cov_uv[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
sum_v += v[pid];
}
double mean_u = sum_u / n_macroparticles;
double mean_v = sum_v / n_macroparticles;
double l_cov_u = 0;
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
l_cov_u += (u[pid] - mean_u) * (v[pid] - mean_v);
}
cov_uv[sid] = l_cov_u / (n_macroparticles - 1);
}
}
} | .file "tmpxft_000f3e36_00000000-6_stats.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z21sorted_mean_per_slicePjS_PdjS0_PjS_PdjS0_
.type _Z49__device_stub__Z21sorted_mean_per_slicePjS_PdjS0_PjS_PdjS0_, @function
_Z49__device_stub__Z21sorted_mean_per_slicePjS_PdjS0_PjS_PdjS0_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21sorted_mean_per_slicePjS_PdjS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z21sorted_mean_per_slicePjS_PdjS0_PjS_PdjS0_, .-_Z49__device_stub__Z21sorted_mean_per_slicePjS_PdjS0_PjS_PdjS0_
.globl _Z21sorted_mean_per_slicePjS_PdjS0_
.type _Z21sorted_mean_per_slicePjS_PdjS0_, @function
_Z21sorted_mean_per_slicePjS_PdjS0_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z21sorted_mean_per_slicePjS_PdjS0_PjS_PdjS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21sorted_mean_per_slicePjS_PdjS0_, .-_Z21sorted_mean_per_slicePjS_PdjS0_
.globl _Z48__device_stub__Z20sorted_std_per_slicePjS_PdjS0_PjS_PdjS0_
.type _Z48__device_stub__Z20sorted_std_per_slicePjS_PdjS0_PjS_PdjS0_, @function
_Z48__device_stub__Z20sorted_std_per_slicePjS_PdjS0_PjS_PdjS0_:
.LFB2053:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20sorted_std_per_slicePjS_PdjS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z48__device_stub__Z20sorted_std_per_slicePjS_PdjS0_PjS_PdjS0_, .-_Z48__device_stub__Z20sorted_std_per_slicePjS_PdjS0_PjS_PdjS0_
.globl _Z20sorted_std_per_slicePjS_PdjS0_
.type _Z20sorted_std_per_slicePjS_PdjS0_, @function
_Z20sorted_std_per_slicePjS_PdjS0_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z20sorted_std_per_slicePjS_PdjS0_PjS_PdjS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z20sorted_std_per_slicePjS_PdjS0_, .-_Z20sorted_std_per_slicePjS_PdjS0_
.globl _Z51__device_stub__Z20sorted_cov_per_slicePjS_PdS0_jS0_PjS_PdS0_jS0_
.type _Z51__device_stub__Z20sorted_cov_per_slicePjS_PdS0_jS0_PjS_PdS0_jS0_, @function
_Z51__device_stub__Z20sorted_cov_per_slicePjS_PdS0_jS0_PjS_PdS0_jS0_:
.LFB2055:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20sorted_cov_per_slicePjS_PdS0_jS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z51__device_stub__Z20sorted_cov_per_slicePjS_PdS0_jS0_PjS_PdS0_jS0_, .-_Z51__device_stub__Z20sorted_cov_per_slicePjS_PdS0_jS0_PjS_PdS0_jS0_
.globl _Z20sorted_cov_per_slicePjS_PdS0_jS0_
.type _Z20sorted_cov_per_slicePjS_PdS0_jS0_, @function
_Z20sorted_cov_per_slicePjS_PdS0_jS0_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z20sorted_cov_per_slicePjS_PdS0_jS0_PjS_PdS0_jS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z20sorted_cov_per_slicePjS_PdS0_jS0_, .-_Z20sorted_cov_per_slicePjS_PdS0_jS0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20sorted_cov_per_slicePjS_PdS0_jS0_"
.align 8
.LC1:
.string "_Z20sorted_std_per_slicePjS_PdjS0_"
.align 8
.LC2:
.string "_Z21sorted_mean_per_slicePjS_PdjS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20sorted_cov_per_slicePjS_PdS0_jS0_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z20sorted_std_per_slicePjS_PdjS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21sorted_mean_per_slicePjS_PdjS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void sorted_mean_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* mean_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the mean
value of quantity u for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
double sum_u;
unsigned int n_macroparticles; // in current slice
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
sum_u = 0;
n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles == 0) {
mean_u[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
}
mean_u[sid] = sum_u / n_macroparticles;
}
}
}
__global__ void sorted_std_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* cov_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the
standard deviation of quantity u for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
double sum_u, mean_u, l_cov_u, du;
unsigned int n_macroparticles; // in current slice
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
sum_u = 0;
n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles <= 1) {
cov_u[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
}
mean_u = sum_u / n_macroparticles;
l_cov_u = 0;
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
du = u[pid] - mean_u;
l_cov_u += du * du;
}
cov_u[sid] = sqrt(l_cov_u / (n_macroparticles - 1));
}
}
}
__global__ void sorted_cov_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
double* v, // 2nd array of particles
unsigned int n_slices,
double* cov_uv) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the
covariance of the quantities u,v for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
double sum_u = 0.;
double sum_v = 0.;
unsigned int n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles <= 1) {
cov_uv[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
sum_v += v[pid];
}
double mean_u = sum_u / n_macroparticles;
double mean_v = sum_v / n_macroparticles;
double l_cov_u = 0;
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
l_cov_u += (u[pid] - mean_u) * (v[pid] - mean_v);
}
cov_uv[sid] = l_cov_u / (n_macroparticles - 1);
}
}
} | #include <hip/hip_runtime.h>
__global__ void sorted_mean_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* mean_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the mean
value of quantity u for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
double sum_u;
unsigned int n_macroparticles; // in current slice
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
sum_u = 0;
n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles == 0) {
mean_u[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
}
mean_u[sid] = sum_u / n_macroparticles;
}
}
}
__global__ void sorted_std_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* cov_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the
standard deviation of quantity u for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
double sum_u, mean_u, l_cov_u, du;
unsigned int n_macroparticles; // in current slice
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
sum_u = 0;
n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles <= 1) {
cov_u[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
}
mean_u = sum_u / n_macroparticles;
l_cov_u = 0;
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
du = u[pid] - mean_u;
l_cov_u += du * du;
}
cov_u[sid] = sqrt(l_cov_u / (n_macroparticles - 1));
}
}
}
__global__ void sorted_cov_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
double* v, // 2nd array of particles
unsigned int n_slices,
double* cov_uv) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the
covariance of the quantities u,v for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
double sum_u = 0.;
double sum_v = 0.;
unsigned int n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles <= 1) {
cov_uv[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
sum_v += v[pid];
}
double mean_u = sum_u / n_macroparticles;
double mean_v = sum_v / n_macroparticles;
double l_cov_u = 0;
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
l_cov_u += (u[pid] - mean_u) * (v[pid] - mean_v);
}
cov_uv[sid] = l_cov_u / (n_macroparticles - 1);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void sorted_mean_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* mean_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the mean
value of quantity u for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
double sum_u;
unsigned int n_macroparticles; // in current slice
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
sum_u = 0;
n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles == 0) {
mean_u[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
}
mean_u[sid] = sum_u / n_macroparticles;
}
}
}
__global__ void sorted_std_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* cov_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the
standard deviation of quantity u for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
double sum_u, mean_u, l_cov_u, du;
unsigned int n_macroparticles; // in current slice
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
sum_u = 0;
n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles <= 1) {
cov_u[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
}
mean_u = sum_u / n_macroparticles;
l_cov_u = 0;
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
du = u[pid] - mean_u;
l_cov_u += du * du;
}
cov_u[sid] = sqrt(l_cov_u / (n_macroparticles - 1));
}
}
}
__global__ void sorted_cov_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
double* v, // 2nd array of particles
unsigned int n_slices,
double* cov_uv) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the
covariance of the quantities u,v for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
double sum_u = 0.;
double sum_v = 0.;
unsigned int n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles <= 1) {
cov_uv[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
sum_v += v[pid];
}
double mean_u = sum_u / n_macroparticles;
double mean_v = sum_v / n_macroparticles;
double l_cov_u = 0;
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
l_cov_u += (u[pid] - mean_u) * (v[pid] - mean_v);
}
cov_uv[sid] = l_cov_u / (n_macroparticles - 1);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21sorted_mean_per_slicePjS_PdjS0_
.globl _Z21sorted_mean_per_slicePjS_PdjS0_
.p2align 8
.type _Z21sorted_mean_per_slicePjS_PdjS0_,@function
_Z21sorted_mean_per_slicePjS_PdjS0_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s10, s[0:1], 0x18
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s10, v1
s_cbranch_execz .LBB0_9
s_load_b32 s12, s[2:3], 0x0
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s12, s11
s_mov_b32 s11, 0
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_u32_e32 v[6:7], v0
v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_div_scale_f64 v[12:13], vcc_lo, v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[14:15], v[12:13], v[10:11]
v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
v_div_fixup_f64 v[4:5], v[8:9], v[6:7], v[4:5]
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s12
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s10, v1
v_add_co_u32 v2, s0, s8, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
s_or_b32 s11, vcc_lo, s11
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_9
.LBB0_4:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v3, v[3:4], off
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e64 v0, v3
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_mov_b32 s13, exec_lo
v_cmpx_gt_u32_e64 v0, v3
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s14, 0
v_mov_b32_e32 v8, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[6:7], 3, v[3:4]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
.LBB0_7:
global_load_b64 v[9:10], v[6:7], off
v_add_nc_u32_e32 v8, 1, v8
v_add_co_u32 v6, s0, v6, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
v_cmp_ge_u32_e32 vcc_lo, v8, v0
s_or_b32 s14, vcc_lo, s14
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[9:10]
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s14
s_branch .LBB0_2
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21sorted_mean_per_slicePjS_PdjS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21sorted_mean_per_slicePjS_PdjS0_, .Lfunc_end0-_Z21sorted_mean_per_slicePjS_PdjS0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20sorted_std_per_slicePjS_PdjS0_
.globl _Z20sorted_std_per_slicePjS_PdjS0_
.p2align 8
.type _Z20sorted_std_per_slicePjS_PdjS0_,@function
_Z20sorted_std_per_slicePjS_PdjS0_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s10, s[0:1], 0x18
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s10, v1
s_cbranch_execz .LBB1_13
s_load_b32 s12, s[2:3], 0x0
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s12, s11
s_mov_b32 s11, 0
s_branch .LBB1_4
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v0, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_u32_e32 v[3:4], v0
v_div_scale_f64 v[5:6], null, v[3:4], v[3:4], v[7:8]
v_div_scale_f64 v[13:14], vcc_lo, v[7:8], v[3:4], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[9:10], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[5:6], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[5:6], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[13:14], v[9:10]
v_fma_f64 v[5:6], -v[5:6], v[11:12], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[5:6], v[5:6], v[9:10], v[11:12]
v_div_fixup_f64 v[3:4], v[5:6], v[3:4], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[3:4]
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
v_lshlrev_b32_e32 v0, 8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ldexp_f64 v[3:4], v[3:4], v0
v_cndmask_b32_e64 v0, 0, 0xffffff80, vcc_lo
v_rsq_f64_e32 v[5:6], v[3:4]
v_cmp_class_f64_e64 vcc_lo, v[3:4], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[7:8], v[3:4], v[5:6]
v_mul_f64 v[5:6], v[5:6], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[5:6], v[7:8], 0.5
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_fma_f64 v[5:6], v[5:6], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[7:8], v[7:8], v[3:4]
v_fma_f64 v[7:8], v[9:10], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[7:8], v[7:8], v[3:4]
v_fma_f64 v[5:6], v[9:10], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[6:7], v[5:6], v0
v_dual_cndmask_b32 v5, v7, v4 :: v_dual_cndmask_b32 v4, v6, v3
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s12
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s10, v1
v_add_co_u32 v2, s0, s8, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
s_or_b32 s11, vcc_lo, s11
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB1_13
.LBB1_4:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v11, v[5:6], off
global_load_b32 v3, v[3:4], off
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v0, v11, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_u32_e32 1, v0
s_cbranch_execz .LBB1_3
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s13, exec_lo
v_cmpx_gt_u32_e64 v11, v3
s_cbranch_execz .LBB1_9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 3, v[3:4]
v_mov_b32_e32 v5, 0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v9, v3
s_mov_b32 s14, 0
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
.LBB1_7:
global_load_b64 v[12:13], v[7:8], off
v_add_nc_u32_e32 v9, 1, v9
v_add_co_u32 v7, s0, v7, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
v_cmp_ge_u32_e32 vcc_lo, v9, v11
s_or_b32 s14, vcc_lo, s14
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], v[5:6], v[12:13]
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execnz .LBB1_7
s_or_b32 exec_lo, exec_lo, s14
.LBB1_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, 0
s_mov_b32 s13, exec_lo
v_cmpx_gt_u32_e64 v11, v3
s_cbranch_execz .LBB1_2
v_cvt_f64_u32_e32 v[7:8], v0
s_mov_b32 s14, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[9:10], null, v[7:8], v[7:8], v[5:6]
v_rcp_f64_e32 v[12:13], v[9:10]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[9:10], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_fma_f64 v[14:15], -v[9:10], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_div_scale_f64 v[14:15], vcc_lo, v[5:6], v[7:8], v[5:6]
v_mul_f64 v[16:17], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[9:10], v[16:17], v[14:15]
v_div_fmas_f64 v[9:10], v[9:10], v[12:13], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[5:6], v[9:10], v[7:8], v[5:6]
v_lshlrev_b64 v[9:10], 3, v[3:4]
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v8, 0
v_add_co_u32 v9, vcc_lo, s2, v9
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
.LBB1_11:
global_load_b64 v[12:13], v[9:10], off
v_add_nc_u32_e32 v3, 1, v3
v_add_co_u32 v9, s0, v9, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v10, s0, 0, v10, s0
v_cmp_ge_u32_e32 vcc_lo, v3, v11
s_or_b32 s14, vcc_lo, s14
s_waitcnt vmcnt(0)
v_add_f64 v[12:13], v[12:13], -v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[7:8], v[12:13], v[12:13], v[7:8]
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execnz .LBB1_11
s_or_b32 exec_lo, exec_lo, s14
s_branch .LBB1_2
.LBB1_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20sorted_std_per_slicePjS_PdjS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20sorted_std_per_slicePjS_PdjS0_, .Lfunc_end1-_Z20sorted_std_per_slicePjS_PdjS0_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20sorted_cov_per_slicePjS_PdS0_jS0_
.globl _Z20sorted_cov_per_slicePjS_PdS0_jS0_
.p2align 8
.type _Z20sorted_cov_per_slicePjS_PdS0_jS0_,@function
_Z20sorted_cov_per_slicePjS_PdS0_jS0_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s12, s[0:1], 0x20
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s12, v1
s_cbranch_execz .LBB2_13
s_load_b32 s14, s[2:3], 0x0
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s14, s13
s_mov_b32 s13, 0
s_branch .LBB2_4
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v0, -1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_u32_e32 v[3:4], v0
v_div_scale_f64 v[5:6], null, v[3:4], v[3:4], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[7:8], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[11:12], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[11:12], v[7:8]
v_div_scale_f64 v[11:12], vcc_lo, v[9:10], v[3:4], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[13:14], v[11:12], v[7:8]
v_fma_f64 v[5:6], -v[5:6], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[13:14]
v_div_fixup_f64 v[4:5], v[5:6], v[3:4], v[9:10]
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s14
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s12, v1
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s13, vcc_lo, s13
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB2_13
.LBB2_4:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v15, v[5:6], off
global_load_b32 v3, v[3:4], off
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v0, v15, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_u32_e32 1, v0
s_cbranch_execz .LBB2_3
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
v_cmpx_gt_u32_e64 v15, v3
s_cbranch_execz .LBB2_9
v_lshlrev_b64 v[7:8], 3, v[3:4]
v_mov_b32_e32 v5, 0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v13, v3
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v8, vcc_lo
v_add_co_u32 v11, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v8, vcc_lo
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
.p2align 6
.LBB2_7:
global_load_b64 v[16:17], v[9:10], off
global_load_b64 v[18:19], v[11:12], off
v_add_nc_u32_e32 v13, 1, v13
v_add_co_u32 v9, vcc_lo, v9, 8
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ge_u32_e32 vcc_lo, v13, v15
v_add_co_u32 v11, s0, v11, 8
v_add_co_ci_u32_e64 v12, s0, 0, v12, s0
s_or_b32 s16, vcc_lo, s16
s_waitcnt vmcnt(1)
v_add_f64 v[5:6], v[5:6], v[16:17]
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[7:8], v[18:19]
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB2_7
s_or_b32 exec_lo, exec_lo, s16
.LBB2_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s15
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v10, 0
s_mov_b32 s15, exec_lo
v_cmpx_gt_u32_e64 v15, v3
s_cbranch_execz .LBB2_2
v_cvt_f64_u32_e32 v[9:10], v0
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_scale_f64 v[11:12], null, v[9:10], v[9:10], v[5:6]
v_div_scale_f64 v[13:14], null, v[9:10], v[9:10], v[7:8]
v_div_scale_f64 v[24:25], vcc_lo, v[5:6], v[9:10], v[5:6]
v_rcp_f64_e32 v[16:17], v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[18:19], v[13:14]
s_waitcnt_depctr 0xfff
v_fma_f64 v[20:21], -v[11:12], v[16:17], 1.0
v_fma_f64 v[22:23], -v[13:14], v[18:19], 1.0
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
v_fma_f64 v[20:21], -v[11:12], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[22:23], -v[13:14], v[18:19], 1.0
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_div_scale_f64 v[20:21], s0, v[7:8], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
v_mul_f64 v[22:23], v[24:25], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[26:27], v[20:21], v[18:19]
v_fma_f64 v[11:12], -v[11:12], v[22:23], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[13:14], -v[13:14], v[26:27], v[20:21]
v_div_fmas_f64 v[11:12], v[11:12], v[16:17], v[22:23]
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[13:14], v[13:14], v[18:19], v[26:27]
v_div_fixup_f64 v[5:6], v[11:12], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[7:8], v[13:14], v[9:10], v[7:8]
v_lshlrev_b64 v[13:14], 3, v[3:4]
v_mov_b32_e32 v9, 0
v_mov_b32_e32 v10, 0
v_add_co_u32 v11, vcc_lo, s8, v13
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v14, vcc_lo
v_add_co_u32 v13, vcc_lo, s10, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s11, v14, vcc_lo
.p2align 6
.LBB2_11:
global_load_b64 v[16:17], v[11:12], off
global_load_b64 v[18:19], v[13:14], off
v_add_nc_u32_e32 v3, 1, v3
v_add_co_u32 v11, vcc_lo, v11, 8
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_ge_u32_e32 vcc_lo, v3, v15
v_add_co_u32 v13, s0, v13, 8
v_add_co_ci_u32_e64 v14, s0, 0, v14, s0
s_or_b32 s16, vcc_lo, s16
s_waitcnt vmcnt(1)
v_add_f64 v[16:17], v[16:17], -v[5:6]
s_waitcnt vmcnt(0)
v_add_f64 v[18:19], v[18:19], -v[7:8]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[9:10], v[16:17], v[18:19], v[9:10]
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB2_11
s_or_b32 exec_lo, exec_lo, s16
s_branch .LBB2_2
.LBB2_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20sorted_cov_per_slicePjS_PdS0_jS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 28
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z20sorted_cov_per_slicePjS_PdS0_jS0_, .Lfunc_end2-_Z20sorted_cov_per_slicePjS_PdS0_jS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21sorted_mean_per_slicePjS_PdjS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21sorted_mean_per_slicePjS_PdjS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20sorted_std_per_slicePjS_PdjS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20sorted_std_per_slicePjS_PdjS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20sorted_cov_per_slicePjS_PdS0_jS0_
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z20sorted_cov_per_slicePjS_PdS0_jS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 28
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void sorted_mean_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* mean_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the mean
value of quantity u for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
double sum_u;
unsigned int n_macroparticles; // in current slice
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
sum_u = 0;
n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles == 0) {
mean_u[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
}
mean_u[sid] = sum_u / n_macroparticles;
}
}
}
__global__ void sorted_std_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
unsigned int n_slices,
double* cov_u) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the
standard deviation of quantity u for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
double sum_u, mean_u, l_cov_u, du;
unsigned int n_macroparticles; // in current slice
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
sum_u = 0;
n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles <= 1) {
cov_u[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
}
mean_u = sum_u / n_macroparticles;
l_cov_u = 0;
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
du = u[pid] - mean_u;
l_cov_u += du * du;
}
cov_u[sid] = sqrt(l_cov_u / (n_macroparticles - 1));
}
}
}
__global__ void sorted_cov_per_slice(unsigned int* lower_bounds,
unsigned int* upper_bounds,
double* u, // array of particle quantity sorted by slice
double* v, // 2nd array of particles
unsigned int n_slices,
double* cov_uv) // output array of length n_slices with mean values for each slice
/**
Iterate once through all the particles within the
slicing region and calculate simultaneously the
covariance of the quantities u,v for each slice separately.
Assumes the particle array u to be sorted by slices.
The index arrays lower_bounds and upper_bounds
indicate the start and end indices
within the sorted particle arrays for each slice. The respective
slice id is identical to the index within lower_bounds and
upper_bounds.
*/
{
for (int sid = blockIdx.x * blockDim.x + threadIdx.x;
sid < n_slices;
sid += blockDim.x * gridDim.x)
{
double sum_u = 0.;
double sum_v = 0.;
unsigned int n_macroparticles = upper_bounds[sid] - lower_bounds[sid];
if (n_macroparticles <= 1) {
cov_uv[sid] = 0;
} else {
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
sum_u += u[pid];
sum_v += v[pid];
}
double mean_u = sum_u / n_macroparticles;
double mean_v = sum_v / n_macroparticles;
double l_cov_u = 0;
for (int pid = lower_bounds[sid]; pid < upper_bounds[sid]; pid++)
{
l_cov_u += (u[pid] - mean_u) * (v[pid] - mean_v);
}
cov_uv[sid] = l_cov_u / (n_macroparticles - 1);
}
}
} | .text
.file "stats.hip"
.globl _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_ # -- Begin function _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_
.p2align 4, 0x90
.type _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_,@function
_Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_: # @_Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21sorted_mean_per_slicePjS_PdjS0_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_, .Lfunc_end0-_Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__sorted_std_per_slicePjS_PdjS0_ # -- Begin function _Z35__device_stub__sorted_std_per_slicePjS_PdjS0_
.p2align 4, 0x90
.type _Z35__device_stub__sorted_std_per_slicePjS_PdjS0_,@function
_Z35__device_stub__sorted_std_per_slicePjS_PdjS0_: # @_Z35__device_stub__sorted_std_per_slicePjS_PdjS0_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20sorted_std_per_slicePjS_PdjS0_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z35__device_stub__sorted_std_per_slicePjS_PdjS0_, .Lfunc_end1-_Z35__device_stub__sorted_std_per_slicePjS_PdjS0_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_ # -- Begin function _Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_
.p2align 4, 0x90
.type _Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_,@function
_Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_: # @_Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20sorted_cov_per_slicePjS_PdS0_jS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_, .Lfunc_end2-_Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21sorted_mean_per_slicePjS_PdjS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20sorted_std_per_slicePjS_PdjS0_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20sorted_cov_per_slicePjS_PdS0_jS0_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21sorted_mean_per_slicePjS_PdjS0_,@object # @_Z21sorted_mean_per_slicePjS_PdjS0_
.section .rodata,"a",@progbits
.globl _Z21sorted_mean_per_slicePjS_PdjS0_
.p2align 3, 0x0
_Z21sorted_mean_per_slicePjS_PdjS0_:
.quad _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_
.size _Z21sorted_mean_per_slicePjS_PdjS0_, 8
.type _Z20sorted_std_per_slicePjS_PdjS0_,@object # @_Z20sorted_std_per_slicePjS_PdjS0_
.globl _Z20sorted_std_per_slicePjS_PdjS0_
.p2align 3, 0x0
_Z20sorted_std_per_slicePjS_PdjS0_:
.quad _Z35__device_stub__sorted_std_per_slicePjS_PdjS0_
.size _Z20sorted_std_per_slicePjS_PdjS0_, 8
.type _Z20sorted_cov_per_slicePjS_PdS0_jS0_,@object # @_Z20sorted_cov_per_slicePjS_PdS0_jS0_
.globl _Z20sorted_cov_per_slicePjS_PdS0_jS0_
.p2align 3, 0x0
_Z20sorted_cov_per_slicePjS_PdS0_jS0_:
.quad _Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_
.size _Z20sorted_cov_per_slicePjS_PdS0_jS0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21sorted_mean_per_slicePjS_PdjS0_"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20sorted_std_per_slicePjS_PdjS0_"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z20sorted_cov_per_slicePjS_PdS0_jS0_"
.size .L__unnamed_3, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_
.addrsig_sym _Z35__device_stub__sorted_std_per_slicePjS_PdjS0_
.addrsig_sym _Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21sorted_mean_per_slicePjS_PdjS0_
.addrsig_sym _Z20sorted_std_per_slicePjS_PdjS0_
.addrsig_sym _Z20sorted_cov_per_slicePjS_PdS0_jS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f3e36_00000000-6_stats.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z21sorted_mean_per_slicePjS_PdjS0_PjS_PdjS0_
.type _Z49__device_stub__Z21sorted_mean_per_slicePjS_PdjS0_PjS_PdjS0_, @function
_Z49__device_stub__Z21sorted_mean_per_slicePjS_PdjS0_PjS_PdjS0_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21sorted_mean_per_slicePjS_PdjS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z21sorted_mean_per_slicePjS_PdjS0_PjS_PdjS0_, .-_Z49__device_stub__Z21sorted_mean_per_slicePjS_PdjS0_PjS_PdjS0_
.globl _Z21sorted_mean_per_slicePjS_PdjS0_
.type _Z21sorted_mean_per_slicePjS_PdjS0_, @function
_Z21sorted_mean_per_slicePjS_PdjS0_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z21sorted_mean_per_slicePjS_PdjS0_PjS_PdjS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21sorted_mean_per_slicePjS_PdjS0_, .-_Z21sorted_mean_per_slicePjS_PdjS0_
.globl _Z48__device_stub__Z20sorted_std_per_slicePjS_PdjS0_PjS_PdjS0_
.type _Z48__device_stub__Z20sorted_std_per_slicePjS_PdjS0_PjS_PdjS0_, @function
_Z48__device_stub__Z20sorted_std_per_slicePjS_PdjS0_PjS_PdjS0_:
.LFB2053:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20sorted_std_per_slicePjS_PdjS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z48__device_stub__Z20sorted_std_per_slicePjS_PdjS0_PjS_PdjS0_, .-_Z48__device_stub__Z20sorted_std_per_slicePjS_PdjS0_PjS_PdjS0_
.globl _Z20sorted_std_per_slicePjS_PdjS0_
.type _Z20sorted_std_per_slicePjS_PdjS0_, @function
_Z20sorted_std_per_slicePjS_PdjS0_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z20sorted_std_per_slicePjS_PdjS0_PjS_PdjS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z20sorted_std_per_slicePjS_PdjS0_, .-_Z20sorted_std_per_slicePjS_PdjS0_
.globl _Z51__device_stub__Z20sorted_cov_per_slicePjS_PdS0_jS0_PjS_PdS0_jS0_
.type _Z51__device_stub__Z20sorted_cov_per_slicePjS_PdS0_jS0_PjS_PdS0_jS0_, @function
_Z51__device_stub__Z20sorted_cov_per_slicePjS_PdS0_jS0_PjS_PdS0_jS0_:
.LFB2055:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20sorted_cov_per_slicePjS_PdS0_jS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z51__device_stub__Z20sorted_cov_per_slicePjS_PdS0_jS0_PjS_PdS0_jS0_, .-_Z51__device_stub__Z20sorted_cov_per_slicePjS_PdS0_jS0_PjS_PdS0_jS0_
.globl _Z20sorted_cov_per_slicePjS_PdS0_jS0_
.type _Z20sorted_cov_per_slicePjS_PdS0_jS0_, @function
_Z20sorted_cov_per_slicePjS_PdS0_jS0_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z20sorted_cov_per_slicePjS_PdS0_jS0_PjS_PdS0_jS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z20sorted_cov_per_slicePjS_PdS0_jS0_, .-_Z20sorted_cov_per_slicePjS_PdS0_jS0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20sorted_cov_per_slicePjS_PdS0_jS0_"
.align 8
.LC1:
.string "_Z20sorted_std_per_slicePjS_PdjS0_"
.align 8
.LC2:
.string "_Z21sorted_mean_per_slicePjS_PdjS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20sorted_cov_per_slicePjS_PdS0_jS0_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z20sorted_std_per_slicePjS_PdjS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21sorted_mean_per_slicePjS_PdjS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stats.hip"
.globl _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_ # -- Begin function _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_
.p2align 4, 0x90
.type _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_,@function
_Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_: # @_Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21sorted_mean_per_slicePjS_PdjS0_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_, .Lfunc_end0-_Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__sorted_std_per_slicePjS_PdjS0_ # -- Begin function _Z35__device_stub__sorted_std_per_slicePjS_PdjS0_
.p2align 4, 0x90
.type _Z35__device_stub__sorted_std_per_slicePjS_PdjS0_,@function
_Z35__device_stub__sorted_std_per_slicePjS_PdjS0_: # @_Z35__device_stub__sorted_std_per_slicePjS_PdjS0_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20sorted_std_per_slicePjS_PdjS0_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z35__device_stub__sorted_std_per_slicePjS_PdjS0_, .Lfunc_end1-_Z35__device_stub__sorted_std_per_slicePjS_PdjS0_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_ # -- Begin function _Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_
.p2align 4, 0x90
.type _Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_,@function
_Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_: # @_Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20sorted_cov_per_slicePjS_PdS0_jS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_, .Lfunc_end2-_Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21sorted_mean_per_slicePjS_PdjS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20sorted_std_per_slicePjS_PdjS0_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20sorted_cov_per_slicePjS_PdS0_jS0_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21sorted_mean_per_slicePjS_PdjS0_,@object # @_Z21sorted_mean_per_slicePjS_PdjS0_
.section .rodata,"a",@progbits
.globl _Z21sorted_mean_per_slicePjS_PdjS0_
.p2align 3, 0x0
_Z21sorted_mean_per_slicePjS_PdjS0_:
.quad _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_
.size _Z21sorted_mean_per_slicePjS_PdjS0_, 8
.type _Z20sorted_std_per_slicePjS_PdjS0_,@object # @_Z20sorted_std_per_slicePjS_PdjS0_
.globl _Z20sorted_std_per_slicePjS_PdjS0_
.p2align 3, 0x0
_Z20sorted_std_per_slicePjS_PdjS0_:
.quad _Z35__device_stub__sorted_std_per_slicePjS_PdjS0_
.size _Z20sorted_std_per_slicePjS_PdjS0_, 8
.type _Z20sorted_cov_per_slicePjS_PdS0_jS0_,@object # @_Z20sorted_cov_per_slicePjS_PdS0_jS0_
.globl _Z20sorted_cov_per_slicePjS_PdS0_jS0_
.p2align 3, 0x0
_Z20sorted_cov_per_slicePjS_PdS0_jS0_:
.quad _Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_
.size _Z20sorted_cov_per_slicePjS_PdS0_jS0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21sorted_mean_per_slicePjS_PdjS0_"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20sorted_std_per_slicePjS_PdjS0_"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z20sorted_cov_per_slicePjS_PdS0_jS0_"
.size .L__unnamed_3, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__sorted_mean_per_slicePjS_PdjS0_
.addrsig_sym _Z35__device_stub__sorted_std_per_slicePjS_PdjS0_
.addrsig_sym _Z35__device_stub__sorted_cov_per_slicePjS_PdS0_jS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21sorted_mean_per_slicePjS_PdjS0_
.addrsig_sym _Z20sorted_std_per_slicePjS_PdjS0_
.addrsig_sym _Z20sorted_cov_per_slicePjS_PdS0_jS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Matrix normalization.
* Compile with "nvcc matrixNormCuda.c -lm"
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 8000 /* Matrix size */
int blocks_per_grid = 32;
int threads_per_block = 256;
/* Matrices */
float A[N*N], B[N*N];
/* CUDA arrays */
float *A_d, *B_d;
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
// srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row*N + col] = (float)rand() / 32768.0;
B[row*N + col] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs()
{
int row, col;
int howmuchtoprint = 10;
printf("\nA =\n\t");
for (row = 0; row < howmuchtoprint; row++)
{
for (col = 0; col < howmuchtoprint; col++)
{
printf("%5.2f%s", A[row*N + col], (col < howmuchtoprint - 1) ? ", " : ";\n\t");
}
}
printf("\nB = [");
for (row = 0; row < howmuchtoprint; row ++)
{
for (col = 0; col < howmuchtoprint; col++)
{
printf("%5.2f%s", B[row*N + col], (col < howmuchtoprint - 1 ) ? "; " : "]\n");
}
}
}
/* Kernel function */
__global__ void matrixNorm(float* A_dd, float* B_dd, int N_d) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// __shared__ float mu, sigma;
float mu, sigma;
int row;
if (idx < N_d) {
mu = 0.0;
for (row=0; row < N_d; row++){
mu += A_dd[row*N_d + idx];
}
mu /= N_d;
sigma = 0.0;
for (row=0; row < N_d; row++){
sigma += powf(A_dd[row*N_d + idx] - mu, 2.0);
}
sigma /= N_d;
sigma = sqrt(sigma);
for (row=0; row < N_d; row++) {
if (sigma == 0.0){
B_dd[row*N_d + idx] = 0.0;
}
else{
B_dd[row*N_d + idx] = (A_dd[row*N_d + idx] - mu) / sigma;
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval start, stop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
unsigned long long runtime;
// int col, row;
// float mu, sigma;
/* Initialize A and B */
initialize_inputs();
print_inputs();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&start, &tzdummy);
printf("Computing Parallely.\n");
/*allocating GPU space*/
cudaMalloc((void **) &A_d, N*N*sizeof(float));
cudaMalloc((void **) &B_d, N*N*sizeof(float));
/*transfer data from host to device*/
cudaMemcpy(A_d,A,N*N*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(B_d,B,N*N*sizeof(float),cudaMemcpyHostToDevice);
/* Kernal Matrix Normalization */
matrixNorm<<<blocks_per_grid,threads_per_block>>>(A_d,B_d,N);
//note to self: KERNAL CALLS ARE EXPENSIVE AF
// for (col=0; col < N; col++) {
// mu = 0.0;
// for (row=0; row < N; row++)
// mu += A[row][col];
// mu /= (float) N;
// sigma = 0.0;
// for (row=0; row < N; row++)
// sigma += powf(A[row][col] - mu, 2.0);
// sigma /= (float) N;
// sigma = sqrt(sigma);
// matrixNorm<<<blocks_per_grid,threads_per_block>>>(A_d,B_d,mu,sigma, N);
// }
/*transfer data from device to host*/
cudaMemcpy(B,B_d,N*N*sizeof(float),cudaMemcpyDeviceToHost);
// cudaMemcpy(A,A_d,N*N*sizeof(float),cudaMemcpyDeviceToHost);
/*deallocating GPU space*/
cudaFree(A_d);
cudaFree(B_d);
printf("\n-------Output--------------------------------------------\n");
print_inputs();
/* Stop Clock */
gettimeofday(&stop, &tzdummy);
runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
/* Display timing results */
printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
exit(0);
} | .file "tmpxft_000bdffa_00000000-6_matrixNormCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17initialize_inputsv
.type _Z17initialize_inputsv, @function
_Z17initialize_inputsv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
leaq A(%rip), %rbp
leaq B(%rip), %r12
leaq 256000000(%rbp), %r13
.L4:
movl $0, %ebx
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx)
movl $0x00000000, (%r12,%rbx)
addq $4, %rbx
cmpq $32000, %rbx
jne .L5
addq $32000, %rbp
addq $32000, %r12
cmpq %r13, %rbp
jne .L4
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z17initialize_inputsv, .-_Z17initialize_inputsv
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "\nA =\n\t"
.LC4:
.string ", "
.LC5:
.string "%5.2f%s"
.LC6:
.string "\nB = ["
.LC7:
.string "; "
.LC8:
.string "]\n"
.LC9:
.string ";\n\t"
.text
.globl _Z12print_inputsv
.type _Z12print_inputsv, @function
_Z12print_inputsv:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq A(%rip), %rbp
leaq 320000(%rbp), %r15
movl $0, %r14d
leaq .LC4(%rip), %r13
leaq .LC5(%rip), %r12
jmp .L10
.L23:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r13, %rdx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
.L12:
cmpq $9, %rbx
jne .L23
movl 12(%rsp), %eax
addl $9, %eax
cltq
leaq A(%rip), %rdx
pxor %xmm0, %xmm0
cvtss2sd (%rdx,%rax,4), %xmm0
leaq .LC9(%rip), %rdx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $8000, %r14d
addq $32000, %rbp
cmpq %r15, %rbp
je .L24
.L10:
movl %r14d, 12(%rsp)
movl $0, %ebx
jmp .L12
.L24:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq B(%rip), %rbp
leaq 320000(%rbp), %r15
movl $0, %r14d
leaq .LC7(%rip), %r13
leaq .LC5(%rip), %r12
jmp .L13
.L25:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r13, %rdx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
.L15:
cmpq $9, %rbx
jne .L25
movl 12(%rsp), %eax
addl $9, %eax
cltq
leaq B(%rip), %rdx
pxor %xmm0, %xmm0
cvtss2sd (%rdx,%rax,4), %xmm0
leaq .LC8(%rip), %rdx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $8000, %r14d
addq $32000, %rbp
cmpq %r15, %rbp
je .L26
.L13:
movl %r14d, 12(%rsp)
movl $0, %ebx
jmp .L15
.L26:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12print_inputsv, .-_Z12print_inputsv
.globl _Z33__device_stub__Z10matrixNormPfS_iPfS_i
.type _Z33__device_stub__Z10matrixNormPfS_iPfS_i, @function
_Z33__device_stub__Z10matrixNormPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixNormPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z10matrixNormPfS_iPfS_i, .-_Z33__device_stub__Z10matrixNormPfS_iPfS_i
.globl _Z10matrixNormPfS_i
.type _Z10matrixNormPfS_i, @function
_Z10matrixNormPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10matrixNormPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10matrixNormPfS_i, .-_Z10matrixNormPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "\n---------------------------------------------\n"
.section .rodata.str1.1
.LC11:
.string "Matrix size N = %d"
.LC12:
.string "\nStarting clock.\n\n"
.LC13:
.string "Computing Parallely.\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "\n-------Output--------------------------------------------\n"
.section .rodata.str1.1
.LC16:
.string "Runtime = %g ms.\n"
.LC17:
.string "\nStopped clock."
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call _Z17initialize_inputsv
call _Z12print_inputsv
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8000, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq 32(%rsp), %rdi
call gettimeofday@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256000000, %esi
leaq A_d(%rip), %rdi
call cudaMalloc@PLT
movl $256000000, %esi
leaq B_d(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $256000000, %edx
leaq A(%rip), %rsi
movq A_d(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $256000000, %edx
leaq B(%rip), %rsi
movq B_d(%rip), %rdi
call cudaMemcpy@PLT
movl threads_per_block(%rip), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl blocks_per_grid(%rip), %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L36:
movl $2, %ecx
movl $256000000, %edx
movq B_d(%rip), %rsi
leaq B(%rip), %rdi
call cudaMemcpy@PLT
movq A_d(%rip), %rdi
call cudaFree@PLT
movq B_d(%rip), %rdi
call cudaFree@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z12print_inputsv
leaq 12(%rsp), %rsi
leaq 48(%rsp), %rdi
call gettimeofday@PLT
movq 48(%rsp), %rax
subq 32(%rsp), %rax
imulq $1000000, %rax, %rax
addq 56(%rsp), %rax
subq 40(%rsp), %rax
js .L37
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L38:
divss .LC15(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L41:
movl $8000, %edx
movq B_d(%rip), %rsi
movq A_d(%rip), %rdi
call _Z33__device_stub__Z10matrixNormPfS_iPfS_i
jmp .L36
.L37:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L38
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z10matrixNormPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixNormPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl B_d
.bss
.align 8
.type B_d, @object
.size B_d, 8
B_d:
.zero 8
.globl A_d
.align 8
.type A_d, @object
.size A_d, 8
A_d:
.zero 8
.globl B
.align 32
.type B, @object
.size B, 256000000
B:
.zero 256000000
.globl A
.align 32
.type A, @object
.size A, 256000000
A:
.zero 256000000
.globl threads_per_block
.data
.align 4
.type threads_per_block, @object
.size threads_per_block, 4
threads_per_block:
.long 256
.globl blocks_per_grid
.align 4
.type blocks_per_grid, @object
.size blocks_per_grid, 4
blocks_per_grid:
.long 32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 939524096
.align 4
.LC15:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Matrix normalization.
* Compile with "nvcc matrixNormCuda.c -lm"
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 8000 /* Matrix size */
int blocks_per_grid = 32;
int threads_per_block = 256;
/* Matrices */
float A[N*N], B[N*N];
/* CUDA arrays */
float *A_d, *B_d;
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
// srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row*N + col] = (float)rand() / 32768.0;
B[row*N + col] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs()
{
int row, col;
int howmuchtoprint = 10;
printf("\nA =\n\t");
for (row = 0; row < howmuchtoprint; row++)
{
for (col = 0; col < howmuchtoprint; col++)
{
printf("%5.2f%s", A[row*N + col], (col < howmuchtoprint - 1) ? ", " : ";\n\t");
}
}
printf("\nB = [");
for (row = 0; row < howmuchtoprint; row ++)
{
for (col = 0; col < howmuchtoprint; col++)
{
printf("%5.2f%s", B[row*N + col], (col < howmuchtoprint - 1 ) ? "; " : "]\n");
}
}
}
/* Kernel function */
__global__ void matrixNorm(float* A_dd, float* B_dd, int N_d) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// __shared__ float mu, sigma;
float mu, sigma;
int row;
if (idx < N_d) {
mu = 0.0;
for (row=0; row < N_d; row++){
mu += A_dd[row*N_d + idx];
}
mu /= N_d;
sigma = 0.0;
for (row=0; row < N_d; row++){
sigma += powf(A_dd[row*N_d + idx] - mu, 2.0);
}
sigma /= N_d;
sigma = sqrt(sigma);
for (row=0; row < N_d; row++) {
if (sigma == 0.0){
B_dd[row*N_d + idx] = 0.0;
}
else{
B_dd[row*N_d + idx] = (A_dd[row*N_d + idx] - mu) / sigma;
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval start, stop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
unsigned long long runtime;
// int col, row;
// float mu, sigma;
/* Initialize A and B */
initialize_inputs();
print_inputs();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&start, &tzdummy);
printf("Computing Parallely.\n");
/*allocating GPU space*/
cudaMalloc((void **) &A_d, N*N*sizeof(float));
cudaMalloc((void **) &B_d, N*N*sizeof(float));
/*transfer data from host to device*/
cudaMemcpy(A_d,A,N*N*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(B_d,B,N*N*sizeof(float),cudaMemcpyHostToDevice);
/* Kernal Matrix Normalization */
matrixNorm<<<blocks_per_grid,threads_per_block>>>(A_d,B_d,N);
//note to self: KERNAL CALLS ARE EXPENSIVE AF
// for (col=0; col < N; col++) {
// mu = 0.0;
// for (row=0; row < N; row++)
// mu += A[row][col];
// mu /= (float) N;
// sigma = 0.0;
// for (row=0; row < N; row++)
// sigma += powf(A[row][col] - mu, 2.0);
// sigma /= (float) N;
// sigma = sqrt(sigma);
// matrixNorm<<<blocks_per_grid,threads_per_block>>>(A_d,B_d,mu,sigma, N);
// }
/*transfer data from device to host*/
cudaMemcpy(B,B_d,N*N*sizeof(float),cudaMemcpyDeviceToHost);
// cudaMemcpy(A,A_d,N*N*sizeof(float),cudaMemcpyDeviceToHost);
/*deallocating GPU space*/
cudaFree(A_d);
cudaFree(B_d);
printf("\n-------Output--------------------------------------------\n");
print_inputs();
/* Stop Clock */
gettimeofday(&stop, &tzdummy);
runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
/* Display timing results */
printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
exit(0);
} | /* Matrix normalization.
* Compile with "nvcc matrixNormCuda.c -lm"
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 8000 /* Matrix size */
int blocks_per_grid = 32;
int threads_per_block = 256;
/* Matrices */
float A[N*N], B[N*N];
/* CUDA arrays */
float *A_d, *B_d;
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
// srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row*N + col] = (float)rand() / 32768.0;
B[row*N + col] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs()
{
int row, col;
int howmuchtoprint = 10;
printf("\nA =\n\t");
for (row = 0; row < howmuchtoprint; row++)
{
for (col = 0; col < howmuchtoprint; col++)
{
printf("%5.2f%s", A[row*N + col], (col < howmuchtoprint - 1) ? ", " : ";\n\t");
}
}
printf("\nB = [");
for (row = 0; row < howmuchtoprint; row ++)
{
for (col = 0; col < howmuchtoprint; col++)
{
printf("%5.2f%s", B[row*N + col], (col < howmuchtoprint - 1 ) ? "; " : "]\n");
}
}
}
/* Kernel function */
__global__ void matrixNorm(float* A_dd, float* B_dd, int N_d) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// __shared__ float mu, sigma;
float mu, sigma;
int row;
if (idx < N_d) {
mu = 0.0;
for (row=0; row < N_d; row++){
mu += A_dd[row*N_d + idx];
}
mu /= N_d;
sigma = 0.0;
for (row=0; row < N_d; row++){
sigma += powf(A_dd[row*N_d + idx] - mu, 2.0);
}
sigma /= N_d;
sigma = sqrt(sigma);
for (row=0; row < N_d; row++) {
if (sigma == 0.0){
B_dd[row*N_d + idx] = 0.0;
}
else{
B_dd[row*N_d + idx] = (A_dd[row*N_d + idx] - mu) / sigma;
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval start, stop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
unsigned long long runtime;
// int col, row;
// float mu, sigma;
/* Initialize A and B */
initialize_inputs();
print_inputs();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&start, &tzdummy);
printf("Computing Parallely.\n");
/*allocating GPU space*/
hipMalloc((void **) &A_d, N*N*sizeof(float));
hipMalloc((void **) &B_d, N*N*sizeof(float));
/*transfer data from host to device*/
hipMemcpy(A_d,A,N*N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(B_d,B,N*N*sizeof(float),hipMemcpyHostToDevice);
/* Kernal Matrix Normalization */
matrixNorm<<<blocks_per_grid,threads_per_block>>>(A_d,B_d,N);
//note to self: KERNAL CALLS ARE EXPENSIVE AF
// for (col=0; col < N; col++) {
// mu = 0.0;
// for (row=0; row < N; row++)
// mu += A[row][col];
// mu /= (float) N;
// sigma = 0.0;
// for (row=0; row < N; row++)
// sigma += powf(A[row][col] - mu, 2.0);
// sigma /= (float) N;
// sigma = sqrt(sigma);
// matrixNorm<<<blocks_per_grid,threads_per_block>>>(A_d,B_d,mu,sigma, N);
// }
/*transfer data from device to host*/
hipMemcpy(B,B_d,N*N*sizeof(float),hipMemcpyDeviceToHost);
// cudaMemcpy(A,A_d,N*N*sizeof(float),cudaMemcpyDeviceToHost);
/*deallocating GPU space*/
hipFree(A_d);
hipFree(B_d);
printf("\n-------Output--------------------------------------------\n");
print_inputs();
/* Stop Clock */
gettimeofday(&stop, &tzdummy);
runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
/* Display timing results */
printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
exit(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Matrix normalization.
* Compile with "nvcc matrixNormCuda.c -lm"
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 8000 /* Matrix size */
int blocks_per_grid = 32;
int threads_per_block = 256;
/* Matrices */
float A[N*N], B[N*N];
/* CUDA arrays */
float *A_d, *B_d;
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
// srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row*N + col] = (float)rand() / 32768.0;
B[row*N + col] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs()
{
int row, col;
int howmuchtoprint = 10;
printf("\nA =\n\t");
for (row = 0; row < howmuchtoprint; row++)
{
for (col = 0; col < howmuchtoprint; col++)
{
printf("%5.2f%s", A[row*N + col], (col < howmuchtoprint - 1) ? ", " : ";\n\t");
}
}
printf("\nB = [");
for (row = 0; row < howmuchtoprint; row ++)
{
for (col = 0; col < howmuchtoprint; col++)
{
printf("%5.2f%s", B[row*N + col], (col < howmuchtoprint - 1 ) ? "; " : "]\n");
}
}
}
/* Kernel function */
__global__ void matrixNorm(float* A_dd, float* B_dd, int N_d) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// __shared__ float mu, sigma;
float mu, sigma;
int row;
if (idx < N_d) {
mu = 0.0;
for (row=0; row < N_d; row++){
mu += A_dd[row*N_d + idx];
}
mu /= N_d;
sigma = 0.0;
for (row=0; row < N_d; row++){
sigma += powf(A_dd[row*N_d + idx] - mu, 2.0);
}
sigma /= N_d;
sigma = sqrt(sigma);
for (row=0; row < N_d; row++) {
if (sigma == 0.0){
B_dd[row*N_d + idx] = 0.0;
}
else{
B_dd[row*N_d + idx] = (A_dd[row*N_d + idx] - mu) / sigma;
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval start, stop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
unsigned long long runtime;
// int col, row;
// float mu, sigma;
/* Initialize A and B */
initialize_inputs();
print_inputs();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&start, &tzdummy);
printf("Computing Parallely.\n");
/*allocating GPU space*/
hipMalloc((void **) &A_d, N*N*sizeof(float));
hipMalloc((void **) &B_d, N*N*sizeof(float));
/*transfer data from host to device*/
hipMemcpy(A_d,A,N*N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(B_d,B,N*N*sizeof(float),hipMemcpyHostToDevice);
/* Kernal Matrix Normalization */
matrixNorm<<<blocks_per_grid,threads_per_block>>>(A_d,B_d,N);
//note to self: KERNAL CALLS ARE EXPENSIVE AF
// for (col=0; col < N; col++) {
// mu = 0.0;
// for (row=0; row < N; row++)
// mu += A[row][col];
// mu /= (float) N;
// sigma = 0.0;
// for (row=0; row < N; row++)
// sigma += powf(A[row][col] - mu, 2.0);
// sigma /= (float) N;
// sigma = sqrt(sigma);
// matrixNorm<<<blocks_per_grid,threads_per_block>>>(A_d,B_d,mu,sigma, N);
// }
/*transfer data from device to host*/
hipMemcpy(B,B_d,N*N*sizeof(float),hipMemcpyDeviceToHost);
// cudaMemcpy(A,A_d,N*N*sizeof(float),cudaMemcpyDeviceToHost);
/*deallocating GPU space*/
hipFree(A_d);
hipFree(B_d);
printf("\n-------Output--------------------------------------------\n");
print_inputs();
/* Stop Clock */
gettimeofday(&stop, &tzdummy);
runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
/* Display timing results */
printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
exit(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixNormPfS_i
.globl _Z10matrixNormPfS_i
.p2align 8
.type _Z10matrixNormPfS_i,@function
_Z10matrixNormPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_12
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_4
v_mov_b32_e32 v2, v1
s_mov_b32 s2, s6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s6, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v3
s_cbranch_scc1 .LBB0_3
.LBB0_4:
v_cvt_f32_i32_e32 v4, s6
s_cmp_lt_i32 s6, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v2, null, v4, v4, v0
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v2, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v5, v3
v_div_scale_f32 v5, vcc_lo, v0, v4, v0
v_mul_f32_e32 v6, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v2, v6, v5
v_fmac_f32_e32 v6, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v2, -v2, v6, v5
v_mov_b32_e32 v5, 0
v_div_fmas_f32 v2, v2, v3, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v2, v4, v0
s_cbranch_scc1 .LBB0_7
v_mov_b32_e32 v2, v1
s_mov_b32 s7, 0x3e76c4e1
s_mov_b32 s8, s6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s8, s8, -1
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_nc_u32_e32 v2, s6, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v3, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f32_e64 v6, |v3|
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v6
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f32 v6, v6, v7
v_add_f32_e32 v9, -1.0, v6
v_add_f32_e32 v7, 1.0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v10, v9, v8 :: v_dual_add_f32 v11, -1.0, v7
v_mul_f32_e32 v12, v7, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v6, v11
v_fma_f32 v7, v10, v7, -v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v10, v6
v_add_f32_e32 v6, v12, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v11, v9, v6 :: v_dual_sub_f32 v12, v6, v12
v_sub_f32_e32 v7, v12, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v9, v9, v11
v_sub_f32_e32 v6, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v7, v6
v_add_f32_e32 v6, v11, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v8, v6
v_add_f32_e32 v7, v10, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v7, v7
v_sub_f32_e32 v8, v7, v10
v_sub_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, v7, v7, -v9
v_add_f32_e32 v10, v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v7, v10
v_add_f32_e32 v10, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmaak_f32 v11, s7, v10, 0x3e91f4c4
v_sub_f32_e32 v9, v10, v9
v_dual_fmaak_f32 v11, v10, v11, 0x3ecccdef :: v_dual_sub_f32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v12, v10, v11
v_fma_f32 v9, v10, v11, -v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v8, v11
v_add_f32_e32 v11, v12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v12, v11, v12 :: v_dual_add_f32 v13, 0x3f2aaaaa, v11
v_dual_mul_f32 v14, v7, v10 :: v_dual_sub_f32 v9, v9, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v15, v10, v7, -v14
v_add_f32_e32 v12, 0xbf2aaaaa, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, 0x31739010, v9
v_fmac_f32_e32 v15, v10, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_f32_e32 v11, v11, v12
v_ldexp_f32 v6, v6, 1
v_fmac_f32_e32 v15, v8, v7
v_ldexp_f32 v7, v7, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v14, v15
v_add_f32_e32 v9, v9, v11
v_add_f32_e32 v8, v13, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v11, v13, v8
v_mul_f32_e32 v12, v10, v8
v_sub_f32_e32 v13, v10, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, v9, v11
v_fma_f32 v11, v10, v8, -v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v13, v15, v13
v_fmac_f32_e32 v11, v10, v9
v_frexp_exp_i32_f32_e32 v9, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v13, v8
v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 1.0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, v12, v11
v_cvt_f32_i32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v12, v9, v12
v_dual_mul_f32 v13, 0x3f317218, v8 :: v_dual_add_f32 v10, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v11, v11, v12
v_fma_f32 v12, v8, 0x3f317218, -v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v6, v11
v_dual_fmac_f32 v12, 0xb102e308, v8 :: v_dual_sub_f32 v7, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v9, v7
v_add_f32_e32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v8, v10, v6 :: v_dual_add_f32 v7, v13, v12
v_dual_sub_f32 v10, v8, v10 :: v_dual_add_f32 v9, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v6, v10 :: v_dual_sub_f32 v11, v9, v7
v_sub_f32_e32 v14, v9, v11
v_dual_sub_f32 v8, v8, v11 :: v_dual_sub_f32 v13, v7, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v7, v7, v14 :: v_dual_sub_f32 v12, v12, v13
v_add_f32_e32 v7, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v12, v6
v_sub_f32_e32 v8, v10, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v7, v10, v7
v_sub_f32_e32 v10, v10, v8
v_sub_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v12, v10 :: v_dual_add_f32 v11, v9, v7
v_dual_add_f32 v6, v6, v8 :: v_dual_sub_f32 v9, v11, v9
v_cndmask_b32_e64 v8, 2.0, 1.0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v7, v9
v_add_f32_e32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v11, v6
v_mul_f32_e32 v10, v8, v7
v_sub_f32_e32 v9, v7, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, v8, v7, -v10
v_sub_f32_e32 v6, v6, v9
v_cmp_class_f32_e64 vcc_lo, v10, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v6
v_add_f32_e32 v6, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v6, v10, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v9
v_cndmask_b32_e64 v11, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v9|
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v12, v9, v11
v_trunc_f32_e32 v9, v8
v_mul_f32_e32 v13, 0x3fb8aa3b, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v14, v12, 0x3fb8aa3b, -v13
v_rndne_f32_e32 v15, v13
v_dual_fmac_f32 v14, 0x32a5705f, v12 :: v_dual_sub_f32 v13, v13, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f32_e32 v13, v13, v14
v_sub_f32_e32 v6, v6, v10
v_cvt_i32_f32_e32 v10, v15
v_exp_f32_e32 v13, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_sub_f32_e32 v6, v7, v6
s_waitcnt_depctr 0xfff
v_ldexp_f32 v7, v13, v10
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v12
v_dual_mul_f32 v10, 0.5, v8 :: v_dual_cndmask_b32 v7, 0, v7
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_trunc_f32_e32 v13, v10
v_dual_add_f32 v6, v11, v6 :: v_dual_cndmask_b32 v7, 0x7f800000, v7
v_cmp_eq_f32_e32 vcc_lo, v9, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_neq_f32_e64 s2, v13, v10
v_fma_f32 v6, v7, v6, v7
v_cmp_eq_f32_e64 s3, 0x7f800000, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
v_cndmask_b32_e64 v8, 1.0, v3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v6, v6, v7, s3
v_cmp_eq_f32_e64 s3, 0, v3
v_bfi_b32 v6, 0x7fffffff, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v7, 0x7f800000, 0, s3
v_cndmask_b32_e64 v8, 0, v3, s2
v_cmp_class_f32_e64 s2, v3, 0x204
v_cndmask_b32_e32 v9, 0x7fc00000, v6, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfi_b32 v7, 0x7fffffff, v7, v8
v_cndmask_b32_e32 v6, v6, v9, vcc_lo
s_or_b32 vcc_lo, s3, s2
s_cmp_lg_u32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v3, v3
v_cndmask_b32_e32 v3, 0x7fc00000, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v5, v3
s_cbranch_scc1 .LBB0_6
.LBB0_7:
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v2, null, v4, v4, v5
v_div_scale_f32 v7, vcc_lo, v5, v4, v5
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v2, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v6, v3
v_mul_f32_e32 v6, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v2, v6, v7
v_fmac_f32_e32 v6, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v6, v7
v_div_fmas_f32 v2, v2, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v2, v4, v5
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v3, v2
v_fma_f32 v7, -v5, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v3, v3, v4, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v7
v_cndmask_b32_e64 v3, v3, v5, s2
s_load_b64 s[2:3], s[0:1], 0x8
s_mov_b32 s1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x37800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v3, v2, vcc_lo
v_cmp_neq_f32_e64 s0, 0, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_nc_u32_e32 v1, s6, v1
s_add_i32 s1, s1, -1
s_cmp_lg_u32 s1, 0
global_store_b32 v[2:3], v5, off
s_cbranch_scc0 .LBB0_12
.LBB0_10:
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_and_saveexec_b32 s7, s0
s_cbranch_execz .LBB0_9
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v5, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v6, null, v4, v4, v5
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v7
v_div_scale_f32 v8, vcc_lo, v5, v4, v5
v_mul_f32_e32 v9, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v6, v9, v8
v_fmac_f32_e32 v9, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v6, v9, v8
v_div_fmas_f32 v6, v6, v7, v9
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v5, v6, v4, v5
s_branch .LBB0_9
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixNormPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixNormPfS_i, .Lfunc_end0-_Z10matrixNormPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixNormPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrixNormPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Matrix normalization.
* Compile with "nvcc matrixNormCuda.c -lm"
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 8000 /* Matrix size */
int blocks_per_grid = 32;
int threads_per_block = 256;
/* Matrices */
float A[N*N], B[N*N];
/* CUDA arrays */
float *A_d, *B_d;
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
// srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row*N + col] = (float)rand() / 32768.0;
B[row*N + col] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs()
{
int row, col;
int howmuchtoprint = 10;
printf("\nA =\n\t");
for (row = 0; row < howmuchtoprint; row++)
{
for (col = 0; col < howmuchtoprint; col++)
{
printf("%5.2f%s", A[row*N + col], (col < howmuchtoprint - 1) ? ", " : ";\n\t");
}
}
printf("\nB = [");
for (row = 0; row < howmuchtoprint; row ++)
{
for (col = 0; col < howmuchtoprint; col++)
{
printf("%5.2f%s", B[row*N + col], (col < howmuchtoprint - 1 ) ? "; " : "]\n");
}
}
}
/* Kernel function */
__global__ void matrixNorm(float* A_dd, float* B_dd, int N_d) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// __shared__ float mu, sigma;
float mu, sigma;
int row;
if (idx < N_d) {
mu = 0.0;
for (row=0; row < N_d; row++){
mu += A_dd[row*N_d + idx];
}
mu /= N_d;
sigma = 0.0;
for (row=0; row < N_d; row++){
sigma += powf(A_dd[row*N_d + idx] - mu, 2.0);
}
sigma /= N_d;
sigma = sqrt(sigma);
for (row=0; row < N_d; row++) {
if (sigma == 0.0){
B_dd[row*N_d + idx] = 0.0;
}
else{
B_dd[row*N_d + idx] = (A_dd[row*N_d + idx] - mu) / sigma;
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval start, stop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
unsigned long long runtime;
// int col, row;
// float mu, sigma;
/* Initialize A and B */
initialize_inputs();
print_inputs();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&start, &tzdummy);
printf("Computing Parallely.\n");
/*allocating GPU space*/
hipMalloc((void **) &A_d, N*N*sizeof(float));
hipMalloc((void **) &B_d, N*N*sizeof(float));
/*transfer data from host to device*/
hipMemcpy(A_d,A,N*N*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(B_d,B,N*N*sizeof(float),hipMemcpyHostToDevice);
/* Kernal Matrix Normalization */
matrixNorm<<<blocks_per_grid,threads_per_block>>>(A_d,B_d,N);
//note to self: KERNAL CALLS ARE EXPENSIVE AF
// for (col=0; col < N; col++) {
// mu = 0.0;
// for (row=0; row < N; row++)
// mu += A[row][col];
// mu /= (float) N;
// sigma = 0.0;
// for (row=0; row < N; row++)
// sigma += powf(A[row][col] - mu, 2.0);
// sigma /= (float) N;
// sigma = sqrt(sigma);
// matrixNorm<<<blocks_per_grid,threads_per_block>>>(A_d,B_d,mu,sigma, N);
// }
/*transfer data from device to host*/
hipMemcpy(B,B_d,N*N*sizeof(float),hipMemcpyDeviceToHost);
// cudaMemcpy(A,A_d,N*N*sizeof(float),cudaMemcpyDeviceToHost);
/*deallocating GPU space*/
hipFree(A_d);
hipFree(B_d);
printf("\n-------Output--------------------------------------------\n");
print_inputs();
/* Stop Clock */
gettimeofday(&stop, &tzdummy);
runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
/* Display timing results */
printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
exit(0);
} | .text
.file "matrixNormCuda.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17initialize_inputsv
.LCPI0_0:
.long 0x38000000 # float 3.05175781E-5
.text
.globl _Z17initialize_inputsv
.p2align 4, 0x90
.type _Z17initialize_inputsv,@function
_Z17initialize_inputsv: # @_Z17initialize_inputsv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
movq $-32000, %r15 # imm = 0x8300
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, A+32000(%rbx,%r15)
movl $0, B+32000(%rbx,%r15)
addq $4, %r15
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %r14
addq $32000, %rbx # imm = 0x7D00
cmpq $8000, %r14 # imm = 0x1F40
jne .LBB0_1
# %bb.4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z17initialize_inputsv, .Lfunc_end0-_Z17initialize_inputsv
.cfi_endproc
# -- End function
.globl _Z12print_inputsv # -- Begin function _Z12print_inputsv
.p2align 4, 0x90
.type _Z12print_inputsv,@function
_Z12print_inputsv: # @_Z12print_inputsv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $A, %r14d
movl $.L.str.3, %r15d
.p2align 4, 0x90
.LBB1_1: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movq $-10, %r12
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss 40(%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
incq %r12
movl $.L.str.2, %esi
cmoveq %r15, %rsi
movl $.L.str.1, %edi
movb $1, %al
callq printf
testq %r12, %r12
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rbx
addq $32000, %r14 # imm = 0x7D00
cmpq $10, %rbx
jne .LBB1_1
# %bb.4:
xorl %ebx, %ebx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $B, %r14d
movl $.L.str.6, %r15d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
movq $-10, %r12
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movss 40(%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
incq %r12
movl $.L.str.5, %esi
cmoveq %r15, %rsi
movl $.L.str.1, %edi
movb $1, %al
callq printf
testq %r12, %r12
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %rbx
addq $32000, %r14 # imm = 0x7D00
cmpq $10, %rbx
jne .LBB1_5
# %bb.8:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12print_inputsv, .Lfunc_end1-_Z12print_inputsv
.cfi_endproc
# -- End function
.globl _Z25__device_stub__matrixNormPfS_i # -- Begin function _Z25__device_stub__matrixNormPfS_i
.p2align 4, 0x90
.type _Z25__device_stub__matrixNormPfS_i,@function
_Z25__device_stub__matrixNormPfS_i: # @_Z25__device_stub__matrixNormPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixNormPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z25__device_stub__matrixNormPfS_i, .Lfunc_end2-_Z25__device_stub__matrixNormPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x38000000 # float 3.05175781E-5
.LCPI3_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
movq $-32000, %r15 # imm = 0x8300
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, A+32000(%rbx,%r15)
movl $0, B+32000(%rbx,%r15)
addq $4, %r15
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %r14
addq $32000, %rbx # imm = 0x7D00
cmpq $8000, %r14 # imm = 0x1F40
jne .LBB3_1
# %bb.4: # %_Z17initialize_inputsv.exit
callq _Z12print_inputsv
movl $.Lstr.4, %edi
callq puts@PLT
movl $.L.str.8, %edi
movl $8000, %esi # imm = 0x1F40
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
leaq 112(%rsp), %rdi
leaq 104(%rsp), %rsi
callq gettimeofday
movl $.Lstr.2, %edi
callq puts@PLT
movl $A_d, %edi
movl $256000000, %esi # imm = 0xF424000
callq hipMalloc
movl $B_d, %edi
movl $256000000, %esi # imm = 0xF424000
callq hipMalloc
movq A_d(%rip), %rdi
movl $A, %esi
movl $256000000, %edx # imm = 0xF424000
movl $1, %ecx
callq hipMemcpy
movq B_d(%rip), %rdi
movl $B, %esi
movl $256000000, %edx # imm = 0xF424000
movl $1, %ecx
callq hipMemcpy
movl blocks_per_grid(%rip), %edi
movl threads_per_block(%rip), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq A_d(%rip), %rax
movq B_d(%rip), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movl $8000, 12(%rsp) # imm = 0x1F40
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
leaq 12(%rsp), %rax
movq %rax, 32(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10matrixNormPfS_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq B_d(%rip), %rsi
movl $B, %edi
movl $256000000, %edx # imm = 0xF424000
movl $2, %ecx
callq hipMemcpy
movq A_d(%rip), %rdi
callq hipFree
movq B_d(%rip), %rdi
callq hipFree
movl $.Lstr.3, %edi
callq puts@PLT
callq _Z12print_inputsv
leaq 16(%rsp), %rdi
leaq 104(%rsp), %rsi
callq gettimeofday
movq 16(%rsp), %rcx
movq 24(%rsp), %rax
subq 112(%rsp), %rcx
imulq $1000000, %rcx, %rcx # imm = 0xF4240
subq 120(%rsp), %rax
addq %rcx, %rax
js .LBB3_7
# %bb.8:
cvtsi2ss %rax, %xmm0
jmp .LBB3_9
.LBB3_7:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB3_9:
divss .LCPI3_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.4, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixNormPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type blocks_per_grid,@object # @blocks_per_grid
.data
.globl blocks_per_grid
.p2align 2, 0x0
blocks_per_grid:
.long 32 # 0x20
.size blocks_per_grid, 4
.type threads_per_block,@object # @threads_per_block
.globl threads_per_block
.p2align 2, 0x0
threads_per_block:
.long 256 # 0x100
.size threads_per_block, 4
.type A,@object # @A
.bss
.globl A
.p2align 4, 0x0
A:
.zero 256000000
.size A, 256000000
.type B,@object # @B
.globl B
.p2align 4, 0x0
B:
.zero 256000000
.size B, 256000000
.type A_d,@object # @A_d
.globl A_d
.p2align 3, 0x0
A_d:
.quad 0
.size A_d, 8
.type B_d,@object # @B_d
.globl B_d
.p2align 3, 0x0
B_d:
.quad 0
.size B_d, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nA =\n\t"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%5.2f%s"
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ", "
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nB = ["
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "]\n"
.size .L.str.6, 3
.type _Z10matrixNormPfS_i,@object # @_Z10matrixNormPfS_i
.section .rodata,"a",@progbits
.globl _Z10matrixNormPfS_i
.p2align 3, 0x0
_Z10matrixNormPfS_i:
.quad _Z25__device_stub__matrixNormPfS_i
.size _Z10matrixNormPfS_i, 8
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz "Matrix size N = %d"
.size .L.str.8, 19
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Runtime = %g ms.\n"
.size .L.str.12, 18
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\nStopped clock."
.size .L.str.13, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrixNormPfS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\nStarting clock.\n"
.size .Lstr.1, 18
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Computing Parallely."
.size .Lstr.2, 21
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n-------Output--------------------------------------------"
.size .Lstr.3, 59
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\n---------------------------------------------"
.size .Lstr.4, 47
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixNormPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym A
.addrsig_sym B
.addrsig_sym A_d
.addrsig_sym B_d
.addrsig_sym _Z10matrixNormPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bdffa_00000000-6_matrixNormCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17initialize_inputsv
.type _Z17initialize_inputsv, @function
_Z17initialize_inputsv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
leaq A(%rip), %rbp
leaq B(%rip), %r12
leaq 256000000(%rbp), %r13
.L4:
movl $0, %ebx
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx)
movl $0x00000000, (%r12,%rbx)
addq $4, %rbx
cmpq $32000, %rbx
jne .L5
addq $32000, %rbp
addq $32000, %r12
cmpq %r13, %rbp
jne .L4
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z17initialize_inputsv, .-_Z17initialize_inputsv
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "\nA =\n\t"
.LC4:
.string ", "
.LC5:
.string "%5.2f%s"
.LC6:
.string "\nB = ["
.LC7:
.string "; "
.LC8:
.string "]\n"
.LC9:
.string ";\n\t"
.text
.globl _Z12print_inputsv
.type _Z12print_inputsv, @function
_Z12print_inputsv:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq A(%rip), %rbp
leaq 320000(%rbp), %r15
movl $0, %r14d
leaq .LC4(%rip), %r13
leaq .LC5(%rip), %r12
jmp .L10
.L23:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r13, %rdx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
.L12:
cmpq $9, %rbx
jne .L23
movl 12(%rsp), %eax
addl $9, %eax
cltq
leaq A(%rip), %rdx
pxor %xmm0, %xmm0
cvtss2sd (%rdx,%rax,4), %xmm0
leaq .LC9(%rip), %rdx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $8000, %r14d
addq $32000, %rbp
cmpq %r15, %rbp
je .L24
.L10:
movl %r14d, 12(%rsp)
movl $0, %ebx
jmp .L12
.L24:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq B(%rip), %rbp
leaq 320000(%rbp), %r15
movl $0, %r14d
leaq .LC7(%rip), %r13
leaq .LC5(%rip), %r12
jmp .L13
.L25:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r13, %rdx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
.L15:
cmpq $9, %rbx
jne .L25
movl 12(%rsp), %eax
addl $9, %eax
cltq
leaq B(%rip), %rdx
pxor %xmm0, %xmm0
cvtss2sd (%rdx,%rax,4), %xmm0
leaq .LC8(%rip), %rdx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $8000, %r14d
addq $32000, %rbp
cmpq %r15, %rbp
je .L26
.L13:
movl %r14d, 12(%rsp)
movl $0, %ebx
jmp .L15
.L26:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12print_inputsv, .-_Z12print_inputsv
.globl _Z33__device_stub__Z10matrixNormPfS_iPfS_i
.type _Z33__device_stub__Z10matrixNormPfS_iPfS_i, @function
_Z33__device_stub__Z10matrixNormPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixNormPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z10matrixNormPfS_iPfS_i, .-_Z33__device_stub__Z10matrixNormPfS_iPfS_i
.globl _Z10matrixNormPfS_i
.type _Z10matrixNormPfS_i, @function
_Z10matrixNormPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10matrixNormPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10matrixNormPfS_i, .-_Z10matrixNormPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "\n---------------------------------------------\n"
.section .rodata.str1.1
.LC11:
.string "Matrix size N = %d"
.LC12:
.string "\nStarting clock.\n\n"
.LC13:
.string "Computing Parallely.\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "\n-------Output--------------------------------------------\n"
.section .rodata.str1.1
.LC16:
.string "Runtime = %g ms.\n"
.LC17:
.string "\nStopped clock."
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
call _Z17initialize_inputsv
call _Z12print_inputsv
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8000, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq 32(%rsp), %rdi
call gettimeofday@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $256000000, %esi
leaq A_d(%rip), %rdi
call cudaMalloc@PLT
movl $256000000, %esi
leaq B_d(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $256000000, %edx
leaq A(%rip), %rsi
movq A_d(%rip), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $256000000, %edx
leaq B(%rip), %rsi
movq B_d(%rip), %rdi
call cudaMemcpy@PLT
movl threads_per_block(%rip), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl blocks_per_grid(%rip), %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L36:
movl $2, %ecx
movl $256000000, %edx
movq B_d(%rip), %rsi
leaq B(%rip), %rdi
call cudaMemcpy@PLT
movq A_d(%rip), %rdi
call cudaFree@PLT
movq B_d(%rip), %rdi
call cudaFree@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z12print_inputsv
leaq 12(%rsp), %rsi
leaq 48(%rsp), %rdi
call gettimeofday@PLT
movq 48(%rsp), %rax
subq 32(%rsp), %rax
imulq $1000000, %rax, %rax
addq 56(%rsp), %rax
subq 40(%rsp), %rax
js .L37
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L38:
divss .LC15(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L41:
movl $8000, %edx
movq B_d(%rip), %rsi
movq A_d(%rip), %rdi
call _Z33__device_stub__Z10matrixNormPfS_iPfS_i
jmp .L36
.L37:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L38
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z10matrixNormPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixNormPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl B_d
.bss
.align 8
.type B_d, @object
.size B_d, 8
B_d:
.zero 8
.globl A_d
.align 8
.type A_d, @object
.size A_d, 8
A_d:
.zero 8
.globl B
.align 32
.type B, @object
.size B, 256000000
B:
.zero 256000000
.globl A
.align 32
.type A, @object
.size A, 256000000
A:
.zero 256000000
.globl threads_per_block
.data
.align 4
.type threads_per_block, @object
.size threads_per_block, 4
threads_per_block:
.long 256
.globl blocks_per_grid
.align 4
.type blocks_per_grid, @object
.size blocks_per_grid, 4
blocks_per_grid:
.long 32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 939524096
.align 4
.LC15:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixNormCuda.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17initialize_inputsv
.LCPI0_0:
.long 0x38000000 # float 3.05175781E-5
.text
.globl _Z17initialize_inputsv
.p2align 4, 0x90
.type _Z17initialize_inputsv,@function
_Z17initialize_inputsv: # @_Z17initialize_inputsv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
movq $-32000, %r15 # imm = 0x8300
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, A+32000(%rbx,%r15)
movl $0, B+32000(%rbx,%r15)
addq $4, %r15
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %r14
addq $32000, %rbx # imm = 0x7D00
cmpq $8000, %r14 # imm = 0x1F40
jne .LBB0_1
# %bb.4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z17initialize_inputsv, .Lfunc_end0-_Z17initialize_inputsv
.cfi_endproc
# -- End function
.globl _Z12print_inputsv # -- Begin function _Z12print_inputsv
.p2align 4, 0x90
.type _Z12print_inputsv,@function
_Z12print_inputsv: # @_Z12print_inputsv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $A, %r14d
movl $.L.str.3, %r15d
.p2align 4, 0x90
.LBB1_1: # %.preheader23
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movq $-10, %r12
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss 40(%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
incq %r12
movl $.L.str.2, %esi
cmoveq %r15, %rsi
movl $.L.str.1, %edi
movb $1, %al
callq printf
testq %r12, %r12
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rbx
addq $32000, %r14 # imm = 0x7D00
cmpq $10, %rbx
jne .LBB1_1
# %bb.4:
xorl %ebx, %ebx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $B, %r14d
movl $.L.str.6, %r15d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
movq $-10, %r12
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movss 40(%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
incq %r12
movl $.L.str.5, %esi
cmoveq %r15, %rsi
movl $.L.str.1, %edi
movb $1, %al
callq printf
testq %r12, %r12
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %rbx
addq $32000, %r14 # imm = 0x7D00
cmpq $10, %rbx
jne .LBB1_5
# %bb.8:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12print_inputsv, .Lfunc_end1-_Z12print_inputsv
.cfi_endproc
# -- End function
.globl _Z25__device_stub__matrixNormPfS_i # -- Begin function _Z25__device_stub__matrixNormPfS_i
.p2align 4, 0x90
.type _Z25__device_stub__matrixNormPfS_i,@function
_Z25__device_stub__matrixNormPfS_i: # @_Z25__device_stub__matrixNormPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixNormPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z25__device_stub__matrixNormPfS_i, .Lfunc_end2-_Z25__device_stub__matrixNormPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x38000000 # float 3.05175781E-5
.LCPI3_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
movq $-32000, %r15 # imm = 0x8300
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, A+32000(%rbx,%r15)
movl $0, B+32000(%rbx,%r15)
addq $4, %r15
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %r14
addq $32000, %rbx # imm = 0x7D00
cmpq $8000, %r14 # imm = 0x1F40
jne .LBB3_1
# %bb.4: # %_Z17initialize_inputsv.exit
callq _Z12print_inputsv
movl $.Lstr.4, %edi
callq puts@PLT
movl $.L.str.8, %edi
movl $8000, %esi # imm = 0x1F40
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
leaq 112(%rsp), %rdi
leaq 104(%rsp), %rsi
callq gettimeofday
movl $.Lstr.2, %edi
callq puts@PLT
movl $A_d, %edi
movl $256000000, %esi # imm = 0xF424000
callq hipMalloc
movl $B_d, %edi
movl $256000000, %esi # imm = 0xF424000
callq hipMalloc
movq A_d(%rip), %rdi
movl $A, %esi
movl $256000000, %edx # imm = 0xF424000
movl $1, %ecx
callq hipMemcpy
movq B_d(%rip), %rdi
movl $B, %esi
movl $256000000, %edx # imm = 0xF424000
movl $1, %ecx
callq hipMemcpy
movl blocks_per_grid(%rip), %edi
movl threads_per_block(%rip), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq A_d(%rip), %rax
movq B_d(%rip), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movl $8000, 12(%rsp) # imm = 0x1F40
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
leaq 12(%rsp), %rax
movq %rax, 32(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10matrixNormPfS_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq B_d(%rip), %rsi
movl $B, %edi
movl $256000000, %edx # imm = 0xF424000
movl $2, %ecx
callq hipMemcpy
movq A_d(%rip), %rdi
callq hipFree
movq B_d(%rip), %rdi
callq hipFree
movl $.Lstr.3, %edi
callq puts@PLT
callq _Z12print_inputsv
leaq 16(%rsp), %rdi
leaq 104(%rsp), %rsi
callq gettimeofday
movq 16(%rsp), %rcx
movq 24(%rsp), %rax
subq 112(%rsp), %rcx
imulq $1000000, %rcx, %rcx # imm = 0xF4240
subq 120(%rsp), %rax
addq %rcx, %rax
js .LBB3_7
# %bb.8:
cvtsi2ss %rax, %xmm0
jmp .LBB3_9
.LBB3_7:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB3_9:
divss .LCPI3_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.4, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixNormPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type blocks_per_grid,@object # @blocks_per_grid
.data
.globl blocks_per_grid
.p2align 2, 0x0
blocks_per_grid:
.long 32 # 0x20
.size blocks_per_grid, 4
.type threads_per_block,@object # @threads_per_block
.globl threads_per_block
.p2align 2, 0x0
threads_per_block:
.long 256 # 0x100
.size threads_per_block, 4
.type A,@object # @A
.bss
.globl A
.p2align 4, 0x0
A:
.zero 256000000
.size A, 256000000
.type B,@object # @B
.globl B
.p2align 4, 0x0
B:
.zero 256000000
.size B, 256000000
.type A_d,@object # @A_d
.globl A_d
.p2align 3, 0x0
A_d:
.quad 0
.size A_d, 8
.type B_d,@object # @B_d
.globl B_d
.p2align 3, 0x0
B_d:
.quad 0
.size B_d, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nA =\n\t"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%5.2f%s"
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ", "
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nB = ["
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "]\n"
.size .L.str.6, 3
.type _Z10matrixNormPfS_i,@object # @_Z10matrixNormPfS_i
.section .rodata,"a",@progbits
.globl _Z10matrixNormPfS_i
.p2align 3, 0x0
_Z10matrixNormPfS_i:
.quad _Z25__device_stub__matrixNormPfS_i
.size _Z10matrixNormPfS_i, 8
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz "Matrix size N = %d"
.size .L.str.8, 19
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Runtime = %g ms.\n"
.size .L.str.12, 18
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\nStopped clock."
.size .L.str.13, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrixNormPfS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\nStarting clock.\n"
.size .Lstr.1, 18
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Computing Parallely."
.size .Lstr.2, 21
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n-------Output--------------------------------------------"
.size .Lstr.3, 59
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\n---------------------------------------------"
.size .Lstr.4, 47
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixNormPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym A
.addrsig_sym B
.addrsig_sym A_d
.addrsig_sym B_d
.addrsig_sym _Z10matrixNormPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void to3d_point(float *depth, float *points3d)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int w = gridDim.x * TILE_DIM;
int h = w / 2;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
{
int iw = x;
int ih = y + j;
float depth_point = depth[ ih*w + iw ] * 128.0;
float phi = ((float)(ih) + 0.5) / float(h) * M_PI;
float theta = ((float)(iw) + 0.5) / float(w) * 2 * M_PI + M_PI;
points3d[(ih * w + iw) * 4 + 0] = depth_point * sin(phi) * cos(theta);
points3d[(ih * w + iw) * 4 + 1] = depth_point * sin(phi) * sin(theta);
points3d[(ih * w + iw) * 4 + 2] = depth_point * cos(phi);
points3d[(ih * w + iw) * 4 + 3] = 1;
}
} | .file "tmpxft_001612d6_00000000-6_to3d_point.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10to3d_pointPfS_PfS_
.type _Z32__device_stub__Z10to3d_pointPfS_PfS_, @function
_Z32__device_stub__Z10to3d_pointPfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10to3d_pointPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10to3d_pointPfS_PfS_, .-_Z32__device_stub__Z10to3d_pointPfS_PfS_
.globl _Z10to3d_pointPfS_
.type _Z10to3d_pointPfS_, @function
_Z10to3d_pointPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10to3d_pointPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10to3d_pointPfS_, .-_Z10to3d_pointPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10to3d_pointPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10to3d_pointPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void to3d_point(float *depth, float *points3d)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int w = gridDim.x * TILE_DIM;
int h = w / 2;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
{
int iw = x;
int ih = y + j;
float depth_point = depth[ ih*w + iw ] * 128.0;
float phi = ((float)(ih) + 0.5) / float(h) * M_PI;
float theta = ((float)(iw) + 0.5) / float(w) * 2 * M_PI + M_PI;
points3d[(ih * w + iw) * 4 + 0] = depth_point * sin(phi) * cos(theta);
points3d[(ih * w + iw) * 4 + 1] = depth_point * sin(phi) * sin(theta);
points3d[(ih * w + iw) * 4 + 2] = depth_point * cos(phi);
points3d[(ih * w + iw) * 4 + 3] = 1;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void to3d_point(float *depth, float *points3d)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int w = gridDim.x * TILE_DIM;
int h = w / 2;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
{
int iw = x;
int ih = y + j;
float depth_point = depth[ ih*w + iw ] * 128.0;
float phi = ((float)(ih) + 0.5) / float(h) * M_PI;
float theta = ((float)(iw) + 0.5) / float(w) * 2 * M_PI + M_PI;
points3d[(ih * w + iw) * 4 + 0] = depth_point * sin(phi) * cos(theta);
points3d[(ih * w + iw) * 4 + 1] = depth_point * sin(phi) * sin(theta);
points3d[(ih * w + iw) * 4 + 2] = depth_point * cos(phi);
points3d[(ih * w + iw) * 4 + 3] = 1;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void to3d_point(float *depth, float *points3d)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int w = gridDim.x * TILE_DIM;
int h = w / 2;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
{
int iw = x;
int ih = y + j;
float depth_point = depth[ ih*w + iw ] * 128.0;
float phi = ((float)(ih) + 0.5) / float(h) * M_PI;
float theta = ((float)(iw) + 0.5) / float(w) * 2 * M_PI + M_PI;
points3d[(ih * w + iw) * 4 + 0] = depth_point * sin(phi) * cos(theta);
points3d[(ih * w + iw) * 4 + 1] = depth_point * sin(phi) * sin(theta);
points3d[(ih * w + iw) * 4 + 2] = depth_point * cos(phi);
points3d[(ih * w + iw) * 4 + 3] = 1;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10to3d_pointPfS_
.globl _Z10to3d_pointPfS_
.p2align 8
.type _Z10to3d_pointPfS_,@function
_Z10to3d_pointPfS_:
v_and_b32_e32 v13, 0x3ff, v0
s_lshl_b32 s12, s14, 5
s_load_b32 s13, s[0:1], 0x10
s_mov_b32 s9, 0x400921fb
s_mov_b32 s8, 0x54442d18
v_add_nc_u32_e32 v1, s12, v13
s_mov_b32 s10, 0x7fffff
s_mov_b32 s11, 0x37d75334
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s14, -8
v_cvt_f32_i32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s15, 5, v0
v_cvt_f64_f32_e32 v[1:2], v1
s_waitcnt lgkmcnt(0)
s_lshl_b32 s4, s13, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v3, s4
v_cvt_f64_f32_e32 v[3:4], v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], v[1:2], 0.5
v_div_scale_f64 v[5:6], null, v[3:4], v[3:4], v[1:2]
v_div_scale_f64 v[11:12], vcc_lo, v[1:2], v[3:4], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[7:8], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[9:10], v[11:12], v[7:8]
v_fma_f64 v[5:6], -v[5:6], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[9:10]
v_div_fixup_f64 v[1:2], v[5:6], v[3:4], v[1:2]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], v[1:2], v[1:2]
v_fma_f64 v[1:2], v[1:2], s[8:9], s[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v11, v[1:2]
v_and_b32_e32 v12, 0x7fffffff, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_or_b32 v14, v12, s10, 0x800000
v_lshrrev_b32_e32 v8, 23, v12
v_mad_u64_u32 v[1:2], null, v14, 0xfe5163ab, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, 0xffffff88, v8
v_cmp_lt_u32_e32 vcc_lo, 63, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, v14, 0x3c439041, v[2:3]
v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
v_mov_b32_e32 v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v14, 0xdb629599, v[2:3]
v_dual_mov_b32 v2, v6 :: v_dual_cndmask_b32 v1, v5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, v14, 0xf534ddc0, v[2:3]
v_add_nc_u32_e32 v10, v10, v9
v_cmp_lt_u32_e64 s2, 31, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v2, v7
v_cndmask_b32_e32 v4, v6, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, 0, 0xffffffe0, s2
v_mad_u64_u32 v[7:8], null, v14, 0xfc2757d1, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v1, v4, v1, s2
v_dual_mov_b32 v2, v8 :: v_dual_add_nc_u32 v15, v15, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v15
v_mad_u64_u32 v[8:9], null, v14, 0x4e441529, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v2, v9
v_mad_u64_u32 v[9:10], null, v14, 0xa2f9836e, v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v3, v8, v6 :: v_dual_add_nc_u32 v2, v2, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v9, v9, v7 :: v_dual_cndmask_b32 v8, v10, v8
v_cndmask_b32_e32 v7, v7, v5, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v9, v3, s2
v_cndmask_b32_e64 v8, v8, v9, s2
s_delay_alu instid0(VALU_DEP_4)
v_cndmask_b32_e64 v3, v3, v7, s2
v_sub_nc_u32_e32 v9, 32, v2
v_cndmask_b32_e64 v7, v7, v4, s2
s_ashr_i32 s2, s4, 1
s_load_b128 s[4:7], s[0:1], 0x0
v_cndmask_b32_e64 v8, v8, v6, s3
v_cndmask_b32_e64 v6, v6, v3, s3
v_cndmask_b32_e64 v3, v3, v7, s3
v_cndmask_b32_e64 v1, v7, v1, s3
s_mov_b32 s3, 0xb94c1982
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v10, v8, v6, v9
v_alignbit_b32 v5, v6, v3, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v10, v8, vcc_lo
v_cndmask_b32_e32 v4, v5, v6, vcc_lo
v_alignbit_b32 v8, v3, v1, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v5, v2, 29, 1
v_alignbit_b32 v6, v2, v4, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v3, v8, v3, vcc_lo
v_cmp_gt_f32_e64 vcc_lo, 0x48000000, |v11|
v_sub_nc_u32_e32 v7, 0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v4, v4, v3, 30
v_alignbit_b32 v1, v3, v1, 30
v_xor_b32_e32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v3, v4, v7
v_xor_b32_e32 v1, v1, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v8, v6
v_min_u32_e32 v8, 32, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, 31, v8
v_lshlrev_b32_e32 v10, 23, v8
v_alignbit_b32 v6, v6, v3, v4
v_alignbit_b32 v1, v3, v1, v4
v_lshrrev_b32_e32 v4, 29, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v3, v6, v1, 9
v_lshlrev_b32_e32 v4, 31, v4
v_lshrrev_b32_e32 v6, 9, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_clz_i32_u32_e32 v7, v3
v_or_b32_e32 v9, 0.5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v7, 32, v7
v_sub_nc_u32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v14, 31, v7
v_alignbit_b32 v1, v3, v1, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_or_b32_e32 v3, v6, v9
v_add_lshl_u32 v6, v7, v8, 23
v_mul_f32_e64 v7, 0x3f22f983, |v11|
v_lshrrev_b32_e32 v1, 9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v1, v1, v6
v_rndne_f32_e32 v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, 0x33000000, v1
v_fma_f32 v9, v6, 0xbfc90fda, |v11|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v9, 0xb3a22168, v6
v_or_b32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, 0xa7c234c4, v6
v_mul_f32_e32 v8, 0x3fc90fda, v3
v_cvt_i32_f32_e32 v6, v6
v_fma_f32 v7, v3, 0x3fc90fda, -v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, 0x33a22168, v3
v_fmac_f32_e32 v7, 0x3fc90fda, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v1, v8, v7
v_lshrrev_b32_e32 v7, 30, v2
v_cndmask_b32_e32 v3, v1, v9, vcc_lo
v_cvt_f32_i32_e32 v1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v4, v3, v3
v_add_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_f32_e32 v[1:2], v1
v_fmaak_f32 v8, s3, v4, 0x3c0881c4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_fmaak_f32 v7, v4, v8, 0xbe2aaa9d
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v9, s11, v4, 0xbab64f3b :: v_dual_mul_f32 v6, v4, v7
v_fmaak_f32 v8, v4, v9, 0x3d2aabf7
v_mul_lo_u32 v9, s13, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v3, v3, v6
v_dual_fmaak_f32 v7, v4, v8, 0xbf000004 :: v_dual_and_b32 v8, 1, v5
v_xor_b32_e32 v6, v12, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v4, v4, v7, 1.0
v_cmp_eq_u32_e32 vcc_lo, 0, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, -v3, v4, vcc_lo
v_dual_cndmask_b32 v3, v4, v3 :: v_dual_lshlrev_b32 v4, 5, v9
v_cmp_class_f32_e64 vcc_lo, v11, 0x1f8
v_lshlrev_b32_e32 v5, 30, v5
v_and_b32_e32 v5, 0x80000000, v5
s_delay_alu instid0(VALU_DEP_1)
v_xor_b32_e32 v8, v5, v7
v_xor3_b32 v5, v6, v5, v3
v_add3_u32 v3, v13, v4, s12
v_mov_b32_e32 v7, 1.0
s_lshl_b32 s12, s13, 10
v_cndmask_b32_e32 v8, 0x7fc00000, v8, vcc_lo
v_cndmask_b32_e32 v9, 0x7fc00000, v5, vcc_lo
v_lshl_or_b32 v5, v3, 2, 3
s_lshl_b32 s13, s13, 8
s_branch .LBB0_2
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mul_f32 v4, v13, v13 :: v_dual_add_nc_u32 v3, s13, v3
s_add_i32 s14, s14, 8
v_and_b32_e32 v12, 1, v14
s_cmp_gt_u32 s14, 23
v_fmaak_f32 v6, s3, v4, 0x3c0881c4
v_lshlrev_b32_e32 v14, 30, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e64 s0, 0, v12
v_fmaak_f32 v6, v4, v6, 0xbe2aaa9d
v_fmaak_f32 v11, s11, v4, 0xbab64f3b
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_and_b32_e32 v14, 0x80000000, v14
v_mul_f32_e32 v6, v4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v11, v4, v11, 0x3d2aabf7
v_fmac_f32_e32 v13, v13, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmaak_f32 v11, v4, v11, 0xbf000004
v_ashrrev_i32_e32 v6, 31, v5
v_fma_f32 v4, v4, v11, 1.0
v_add_nc_u32_e32 v11, -1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, -v13, v4, s0
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v14, v4
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_lshlrev_b64 v[13:14], 2, v[5:6]
v_add_nc_u32_e32 v5, s12, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v4, 0x7fc00000, v4, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
v_add_co_u32 v13, vcc_lo, s6, v13
s_delay_alu instid0(VALU_DEP_4)
v_mul_f32_e32 v4, v10, v4
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
s_clause 0x1
global_store_b32 v[11:12], v4, off
global_store_b32 v[13:14], v7, off
s_cbranch_scc1 .LBB0_14
.LBB0_2:
v_add3_u32 v4, v0, s14, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v4, v4
v_cvt_f64_f32_e32 v[10:11], v4
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[11:12], v[10:11], 0.5
v_div_scale_f64 v[13:14], null, v[1:2], v[1:2], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[15:16], v[13:14]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
v_lshlrev_b64 v[17:18], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v17, vcc_lo, s4, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
v_div_scale_f64 v[19:20], vcc_lo, v[11:12], v[1:2], v[11:12]
global_load_b32 v10, v[17:18], off
v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
v_mul_f64 v[17:18], v[19:20], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], -v[13:14], v[17:18], v[19:20]
v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[11:12], v[13:14], v[1:2], v[11:12]
v_mul_f64 v[11:12], v[11:12], s[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v4, v[11:12]
v_and_b32_e32 v11, 0x7fffffff, v4
v_cmp_ngt_f32_e64 s15, 0x48000000, |v4|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s15
s_xor_b32 s2, exec_lo, s0
s_cbranch_execz .LBB0_4
v_and_or_b32 v6, v11, s10, 0x800000
v_mov_b32_e32 v14, 0
v_lshrrev_b32_e32 v19, 23, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[12:13], null, v6, 0xfe5163ab, 0
v_add_nc_u32_e32 v20, 0xffffff88, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v20
v_mad_u64_u32 v[15:16], null, v6, 0x3c439041, v[13:14]
v_cndmask_b32_e64 v21, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v13, v16
v_add_nc_u32_e32 v21, v21, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[16:17], null, v6, 0xdb629599, v[13:14]
v_cmp_lt_u32_e64 s0, 31, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v22, 0, 0xffffffe0, s0
v_dual_mov_b32 v13, v17 :: v_dual_cndmask_b32 v12, v16, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v22, v22, v21
v_mad_u64_u32 v[17:18], null, v6, 0xf534ddc0, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s1, 31, v22
v_mov_b32_e32 v13, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v15, v17, v15, vcc_lo
v_mad_u64_u32 v[18:19], null, v6, 0xfc2757d1, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v13, v19
v_mad_u64_u32 v[19:20], null, v6, 0x4e441529, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v13, v20
v_mad_u64_u32 v[20:21], null, v6, 0xa2f9836e, v[13:14]
v_cndmask_b32_e64 v6, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v13, v19, v17 :: v_dual_add_nc_u32 v6, v6, v22
v_dual_cndmask_b32 v14, v20, v18 :: v_dual_cndmask_b32 v19, v21, v19
v_cndmask_b32_e32 v18, v18, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v6
v_cndmask_b32_e64 v17, v14, v13, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v14, v19, v14, s0
v_cndmask_b32_e64 v13, v13, v18, s0
v_sub_nc_u32_e32 v19, 32, v6
v_cndmask_b32_e64 v18, v18, v15, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v14, v14, v17, s1
v_cndmask_b32_e64 v17, v17, v13, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v13, v13, v18, s1
v_alignbit_b32 v20, v14, v17, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v16, v17, v13, v19
v_cndmask_b32_e32 v6, v20, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v14, v16, v17, vcc_lo
v_cndmask_b32_e64 v12, v15, v12, s0
v_bfe_u32 v15, v6, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v16, v6, v14, 30
v_cndmask_b32_e64 v12, v18, v12, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v17, 0, v15
v_alignbit_b32 v18, v13, v12, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v16, v16, v17
v_cndmask_b32_e32 v13, v18, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_clz_i32_u32_e32 v18, v16
v_alignbit_b32 v14, v14, v13, 30
v_alignbit_b32 v12, v13, v12, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_min_u32_e32 v18, 32, v18
v_xor_b32_e32 v13, v14, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v12, v12, v17
v_sub_nc_u32_e32 v14, 31, v18
v_lshlrev_b32_e32 v20, 23, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_alignbit_b32 v16, v16, v13, v14
v_alignbit_b32 v12, v13, v12, v14
v_lshrrev_b32_e32 v14, 29, v6
v_lshrrev_b32_e32 v6, 30, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v16, v12, 9
v_lshlrev_b32_e32 v14, 31, v14
v_lshrrev_b32_e32 v16, 9, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_clz_i32_u32_e32 v17, v13
v_or_b32_e32 v19, 0.5, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v17, 32, v17
v_sub_nc_u32_e32 v19, v19, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v21, 31, v17
v_alignbit_b32 v12, v13, v12, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v13, v16, v19
v_add_lshl_u32 v16, v17, v18, 23
v_lshrrev_b32_e32 v12, 9, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v17, 0x3fc90fda, v13
v_sub_nc_u32_e32 v12, v12, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v16, v13, 0x3fc90fda, -v17
v_add_nc_u32_e32 v12, 0x33000000, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v16, 0x33a22168, v13 :: v_dual_add_nc_u32 v13, v15, v6
v_or_b32_e32 v12, v12, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v16, 0x3fc90fda, v12
v_add_f32_e32 v12, v17, v16
.LBB0_4:
s_or_saveexec_b32 s0, s2
v_mul_f32_e64 v6, 0x3f22f983, |v4|
s_xor_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v13, v6
v_fma_f32 v12, v13, 0xbfc90fda, |v4|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, 0xb3a22168, v13
v_fmac_f32_e32 v12, 0xa7c234c4, v13
v_cvt_i32_f32_e32 v13, v13
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mul_f32 v14, v12, v12 :: v_dual_and_b32 v17, 1, v13
s_waitcnt vmcnt(0)
v_mul_f32_e32 v10, 0x43000000, v10
v_lshlrev_b32_e32 v18, 30, v13
v_xor_b32_e32 v13, v11, v4
v_fmaak_f32 v15, s3, v14, 0x3c0881c4
v_cmp_eq_u32_e32 vcc_lo, 0, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v15, v14, v15, 0xbe2aaa9d
v_dual_fmaak_f32 v16, s11, v14, 0xbab64f3b :: v_dual_mul_f32 v15, v14, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v16, v14, v16, 0x3d2aabf7
v_dual_fmac_f32 v12, v12, v15 :: v_dual_and_b32 v15, 0x80000000, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v16, v14, v16, 0xbf000004
v_fma_f32 v14, v14, v16, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v12, v14, v12, vcc_lo
v_add_nc_u32_e32 v14, -3, v5
v_cmp_class_f32_e64 vcc_lo, v4, 0x1f8
v_xor3_b32 v12, v15, v12, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v15, 31, v14
v_cndmask_b32_e32 v12, 0x7fc00000, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[14:15], 2, v[14:15]
v_mul_f32_e32 v12, v10, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v14, s0, s6, v14
v_add_co_ci_u32_e64 v15, s0, s7, v15, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_mul_f32_e32 v16, v12, v8
v_lshrrev_b32_e32 v12, 23, v11
v_and_or_b32 v11, v11, s10, 0x800000
global_store_b32 v[14:15], v16, off
s_and_saveexec_b32 s0, s15
s_xor_b32 s16, exec_lo, s0
s_cbranch_execz .LBB0_8
v_mad_u64_u32 v[14:15], null, v11, 0xfe5163ab, 0
v_mov_b32_e32 v16, 0
v_add_nc_u32_e32 v22, 0xffffff88, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[17:18], null, v11, 0x3c439041, v[15:16]
v_cmp_lt_u32_e64 s0, 63, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v23, 0, 0xffffffc0, s0
v_mov_b32_e32 v15, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v23, v23, v22
v_mad_u64_u32 v[18:19], null, v11, 0xdb629599, v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s1, 31, v23
v_mov_b32_e32 v15, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v14, v18, v14, s0
v_cndmask_b32_e64 v24, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[19:20], null, v11, 0xf534ddc0, v[15:16]
v_add_nc_u32_e32 v24, v24, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e64 s2, 31, v24
v_mov_b32_e32 v15, v20
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v17, v19, v17, s0
v_mad_u64_u32 v[20:21], null, v11, 0xfc2757d1, v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v14, v17, v14, s1
v_mov_b32_e32 v15, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[21:22], null, v11, 0x4e441529, v[15:16]
v_mov_b32_e32 v15, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[22:23], null, v11, 0xa2f9836e, v[15:16]
v_cndmask_b32_e64 v15, 0, 0xffffffe0, s2
v_cndmask_b32_e64 v16, v21, v19, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v15, v15, v24
v_cndmask_b32_e64 v22, v22, v20, s0
v_cndmask_b32_e64 v21, v23, v21, s0
v_cndmask_b32_e64 v20, v20, v18, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e64 s0, 0, v15
v_cndmask_b32_e64 v19, v22, v16, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v21, v21, v22, s1
v_cndmask_b32_e64 v16, v16, v20, s1
v_sub_nc_u32_e32 v22, 32, v15
v_cndmask_b32_e64 v20, v20, v17, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v21, v21, v19, s2
v_cndmask_b32_e64 v19, v19, v16, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v16, v16, v20, s2
v_cndmask_b32_e64 v14, v20, v14, s2
v_alignbit_b32 v23, v21, v19, v22
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v18, v19, v16, v22
v_cndmask_b32_e64 v15, v23, v21, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v21, v16, v14, v22
v_cndmask_b32_e64 v17, v18, v19, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v18, v15, 29, 1
v_cndmask_b32_e64 v16, v21, v16, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v19, v15, v17, 30
v_sub_nc_u32_e32 v20, 0, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v17, v17, v16, 30
v_alignbit_b32 v14, v16, v14, 30
v_xor_b32_e32 v19, v19, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v16, v17, v20
v_xor_b32_e32 v14, v14, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v21, v19
v_min_u32_e32 v21, 32, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v17, 31, v21
v_lshlrev_b32_e32 v23, 23, v21
v_alignbit_b32 v19, v19, v16, v17
v_alignbit_b32 v14, v16, v14, v17
v_lshrrev_b32_e32 v17, 29, v15
v_lshrrev_b32_e32 v15, 30, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v16, v19, v14, 9
v_lshlrev_b32_e32 v17, 31, v17
v_lshrrev_b32_e32 v19, 9, v19
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v15, v18, v15
v_clz_i32_u32_e32 v20, v16
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v22, 0.5, v17
v_min_u32_e32 v20, 32, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v22, v22, v23
v_sub_nc_u32_e32 v24, 31, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v14, v16, v14, v24
v_or_b32_e32 v16, v19, v22
v_add_lshl_u32 v19, v20, v21, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v14, 9, v14
v_mul_f32_e32 v20, 0x3fc90fda, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v14, v14, v19
v_fma_f32 v19, v16, 0x3fc90fda, -v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v14, 0x33000000, v14
v_fmac_f32_e32 v19, 0x33a22168, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v14, v14, v17
v_fmac_f32_e32 v19, 0x3fc90fda, v14
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v14, v20, v19
.LBB0_8:
s_and_not1_saveexec_b32 s0, s16
v_rndne_f32_e32 v15, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v14, v15, 0xbfc90fda, |v4|
v_fmac_f32_e32 v14, 0xb3a22168, v15
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v14, 0xa7c234c4, v15
v_cvt_i32_f32_e32 v15, v15
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mul_f32 v16, v14, v14 :: v_dual_and_b32 v19, 1, v15
v_lshlrev_b32_e32 v15, 30, v15
v_fmaak_f32 v17, s3, v16, 0x3c0881c4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e64 s0, 0, v19
v_and_b32_e32 v15, 0x80000000, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v17, v16, v17, 0xbe2aaa9d
v_dual_fmaak_f32 v18, s11, v16, 0xbab64f3b :: v_dual_mul_f32 v17, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v18, v16, v18, 0x3d2aabf7
v_fmac_f32_e32 v14, v14, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v18, v16, v18, 0xbf000004
v_fma_f32 v16, v16, v18, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v14, v16, v14, s0
v_xor3_b32 v14, v15, v14, v13
v_add_nc_u32_e32 v13, -2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v15, 0x7fc00000, v14, vcc_lo
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v15, v10, v15
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v15, v15, v9
v_add_co_u32 v13, s0, s6, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v14, s0, s7, v14, s0
global_store_b32 v[13:14], v15, off
s_and_saveexec_b32 s0, s15
s_xor_b32 s15, exec_lo, s0
s_cbranch_execz .LBB0_12
v_mad_u64_u32 v[13:14], null, v11, 0xfe5163ab, 0
v_dual_mov_b32 v15, 0 :: v_dual_add_nc_u32 v4, 0xffffff88, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s0, 63, v4
v_mad_u64_u32 v[16:17], null, v11, 0x3c439041, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v6, 0, 0xffffffc0, s0
v_mov_b32_e32 v14, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v6, v4
v_mad_u64_u32 v[17:18], null, v11, 0xdb629599, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s1, 31, v4
v_cndmask_b32_e64 v6, 0, 0xffffffe0, s1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v14, v18
v_cndmask_b32_e64 v13, v17, v13, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, v6, v4
v_mad_u64_u32 v[18:19], null, v11, 0xf534ddc0, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s2, 31, v4
v_mov_b32_e32 v14, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v6, 0, 0xffffffe0, s2
v_mad_u64_u32 v[19:20], null, v11, 0xfc2757d1, v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, v6, v4
v_cndmask_b32_e64 v6, v18, v16, s0
v_mov_b32_e32 v14, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[20:21], null, v11, 0x4e441529, v[14:15]
v_mov_b32_e32 v14, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[21:22], null, v11, 0xa2f9836e, v[14:15]
v_cndmask_b32_e64 v11, v20, v18, s0
v_cndmask_b32_e64 v15, v19, v17, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v21, v19, s0
v_cndmask_b32_e64 v14, v22, v20, s0
v_cmp_eq_u32_e64 s0, 0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v16, v12, v11, s1
v_cndmask_b32_e64 v12, v14, v12, s1
v_cndmask_b32_e64 v11, v11, v15, s1
v_sub_nc_u32_e32 v14, 32, v4
v_cndmask_b32_e64 v15, v15, v6, s1
v_cndmask_b32_e64 v6, v6, v13, s1
v_cndmask_b32_e64 v12, v12, v16, s2
v_cndmask_b32_e64 v16, v16, v11, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v11, v11, v15, s2
v_cndmask_b32_e64 v6, v15, v6, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v18, v12, v16, v14
v_alignbit_b32 v17, v16, v11, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v14, v11, v6, v14
v_cndmask_b32_e64 v4, v18, v12, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v12, v17, v16, s0
v_cndmask_b32_e64 v11, v14, v11, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v16, v4, 29, 1
v_alignbit_b32 v13, v4, v12, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_alignbit_b32 v12, v12, v11, 30
v_alignbit_b32 v6, v11, v6, 30
v_sub_nc_u32_e32 v15, 0, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v13, v13, v15
v_xor_b32_e32 v11, v12, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v6, v6, v15
v_clz_i32_u32_e32 v14, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v14, 32, v14
v_sub_nc_u32_e32 v12, 31, v14
v_lshlrev_b32_e32 v18, 23, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v13, v11, v12
v_alignbit_b32 v6, v11, v6, v12
v_lshrrev_b32_e32 v12, 29, v4
v_lshrrev_b32_e32 v4, 30, v4
v_alignbit_b32 v11, v13, v6, 9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v12, 31, v12
v_lshrrev_b32_e32 v13, 9, v13
v_clz_i32_u32_e32 v15, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v17, 0.5, v12
v_min_u32_e32 v15, 32, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v17, v17, v18
v_sub_nc_u32_e32 v19, 31, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v6, v11, v6, v19
v_or_b32_e32 v11, v13, v17
v_add_lshl_u32 v13, v15, v14, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v6, 9, v6
v_mul_f32_e32 v14, 0x3fc90fda, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v6, v13
v_fma_f32 v13, v11, 0x3fc90fda, -v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, 0x33000000, v6
v_fmac_f32_e32 v13, 0x33a22168, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v6, v6, v12
v_fmac_f32_e32 v13, 0x3fc90fda, v6
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v13, v14, v13 :: v_dual_add_nc_u32 v14, v16, v4
.LBB0_12:
s_and_not1_saveexec_b32 s0, s15
s_cbranch_execz .LBB0_1
v_rndne_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v13, v6, 0xbfc90fda, |v4|
v_cvt_i32_f32_e32 v14, v6
v_fmac_f32_e32 v13, 0xb3a22168, v6
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v13, 0xa7c234c4, v6
s_branch .LBB0_1
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10to3d_pointPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10to3d_pointPfS_, .Lfunc_end0-_Z10to3d_pointPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10to3d_pointPfS_
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z10to3d_pointPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void to3d_point(float *depth, float *points3d)
{
int x = blockIdx.x * TILE_DIM + threadIdx.x;
int y = blockIdx.y * TILE_DIM + threadIdx.y;
int w = gridDim.x * TILE_DIM;
int h = w / 2;
for (int j = 0; j < TILE_DIM; j+= BLOCK_ROWS)
{
int iw = x;
int ih = y + j;
float depth_point = depth[ ih*w + iw ] * 128.0;
float phi = ((float)(ih) + 0.5) / float(h) * M_PI;
float theta = ((float)(iw) + 0.5) / float(w) * 2 * M_PI + M_PI;
points3d[(ih * w + iw) * 4 + 0] = depth_point * sin(phi) * cos(theta);
points3d[(ih * w + iw) * 4 + 1] = depth_point * sin(phi) * sin(theta);
points3d[(ih * w + iw) * 4 + 2] = depth_point * cos(phi);
points3d[(ih * w + iw) * 4 + 3] = 1;
}
} | .text
.file "to3d_point.hip"
.globl _Z25__device_stub__to3d_pointPfS_ # -- Begin function _Z25__device_stub__to3d_pointPfS_
.p2align 4, 0x90
.type _Z25__device_stub__to3d_pointPfS_,@function
_Z25__device_stub__to3d_pointPfS_: # @_Z25__device_stub__to3d_pointPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10to3d_pointPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__to3d_pointPfS_, .Lfunc_end0-_Z25__device_stub__to3d_pointPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10to3d_pointPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10to3d_pointPfS_,@object # @_Z10to3d_pointPfS_
.section .rodata,"a",@progbits
.globl _Z10to3d_pointPfS_
.p2align 3, 0x0
_Z10to3d_pointPfS_:
.quad _Z25__device_stub__to3d_pointPfS_
.size _Z10to3d_pointPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10to3d_pointPfS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__to3d_pointPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10to3d_pointPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001612d6_00000000-6_to3d_point.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10to3d_pointPfS_PfS_
.type _Z32__device_stub__Z10to3d_pointPfS_PfS_, @function
_Z32__device_stub__Z10to3d_pointPfS_PfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10to3d_pointPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10to3d_pointPfS_PfS_, .-_Z32__device_stub__Z10to3d_pointPfS_PfS_
.globl _Z10to3d_pointPfS_
.type _Z10to3d_pointPfS_, @function
_Z10to3d_pointPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10to3d_pointPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10to3d_pointPfS_, .-_Z10to3d_pointPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10to3d_pointPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10to3d_pointPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "to3d_point.hip"
.globl _Z25__device_stub__to3d_pointPfS_ # -- Begin function _Z25__device_stub__to3d_pointPfS_
.p2align 4, 0x90
.type _Z25__device_stub__to3d_pointPfS_,@function
_Z25__device_stub__to3d_pointPfS_: # @_Z25__device_stub__to3d_pointPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10to3d_pointPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__to3d_pointPfS_, .Lfunc_end0-_Z25__device_stub__to3d_pointPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10to3d_pointPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10to3d_pointPfS_,@object # @_Z10to3d_pointPfS_
.section .rodata,"a",@progbits
.globl _Z10to3d_pointPfS_
.p2align 3, 0x0
_Z10to3d_pointPfS_:
.quad _Z25__device_stub__to3d_pointPfS_
.size _Z10to3d_pointPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10to3d_pointPfS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__to3d_pointPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10to3d_pointPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<bits/stdc++.h>
using namespace std;
const int THREADS_PER_BLOCK = 1024;
const int BLOCKS = 50;
const int MAXN = 16;
const int INF = 1e9;
const int MIN_EDGE_WEIGHT = 1;
const int MAX_EDGE_WEIGHT = 10;
long long factorial[MAXN+1];
__managed__ int block_optimal_values[BLOCKS];
// __managed__ int block_optimal_paths[BLOCKS][MAXN+1];
__managed__ int block_optimal_permutation[BLOCKS];
/////////////////// Host Functions ///////////////////
__host__ int random(int l, int r) {
return l + rand()%(r-l+1);
}
__host__ void precompute_factorial() {
factorial[0] = 1;
for(int i=1;i<=MAXN;i++)
{
factorial[i] = i * factorial[i-1];
}
}
__host__ void assign_edge_weights(int* matrix, int N) {
for (int i = 0 ; i < N ; i++) {
for (int j = i+1 ; j < N ; j++) {
matrix[i*N + j] = random(MIN_EDGE_WEIGHT,MAX_EDGE_WEIGHT);
matrix[j*N + i] = matrix[i*N + j];
}
matrix[i*N + i] = 0;
}
}
__host__ void print_matrix(int* matrix, int N) {
for(int i=0; i<N; i++) {
for(int j=0; j<N; j++) {
cout << matrix[i*N + j] << " ";
}
printf("\n");
}
}
/////////////////// Device Functions ///////////////////
__device__ void swap(int &a, int &b) {
int temp = a;
a = b;
b = temp;
}
__host__ __device__ long long fact(int n) {
long long ans = 1;
for(int i=1;i<=n;i++) {
ans *= i;
}
return ans;
}
__device__ bool nxt_permutation(int *arr, int n) {
bool nxt_permutation_possible = false;
int fi = -1;
for(int i=n-2;i>=0;i--) {
if(arr[i+1] > arr[i]) {
nxt_permutation_possible = true;
fi = i;
break;
}
}
if(!nxt_permutation_possible)return false;
int next_greater_ele = arr[fi+1], next_greater_ele_ind = fi+1;
for(int i=fi+2;i<n;i++) {
if(arr[i] > arr[fi] && arr[i] < next_greater_ele) {
next_greater_ele = arr[i];
next_greater_ele_ind = i;
}
}
swap(arr[fi],arr[next_greater_ele_ind]);
//Reverse
int li = fi+1, ri = n-1;
while(li < ri) {
swap(arr[li],arr[ri]);
li++;
ri--;
}
return true;
}
__device__ int find_path_cost(int* matrix, int* arr, int arrsize, int n) {
int cost = 0;
for(int i=1; i<arrsize; i++) {
int to = arr[i];
int from = arr[i-1];
cost += matrix[to*n + from];
}
return cost;
}
/////////////////// Global Functions ///////////////////
//Input array should be sorted
__host__ __device__ bool nth_permutation(int *arr, int arrsize, long long n) {
if(n>fact(arrsize))return false;
// Assuming arrSize = N+1
bool taken[MAXN];
for(int i=0; i<arrsize; i++) taken[i] = false;
int *ans = new int[arrsize];
for(int i=0; i<arrsize; i++) {
int cn = 1;
long long cval = fact(arrsize-1-i);
while(cval<n) {
cn++;
cval=(long long)cn*cval;
cval=(long long)cval/(cn-1);
}
long long pval = cval*(cn-1)/cn;
n -= pval;
for(int j=0; j<arrsize; j++) {
if(!taken[j]) {
cn--;
if(cn==0) {
ans[i] = arr[j];
taken[j] = true;
break;
}
}
}
}
for(int i=0; i<arrsize; i++) {
arr[i] = ans[i];
}
free(ans);
return true;
}
__global__ void tsp_cuda(int* matrix, int* path, long long* factorials, int N) {
__shared__ int thread_optimal_values[THREADS_PER_BLOCK];
// __shared__ int* thread_optimal_paths[THREADS_PER_BLOCK];
__shared__ int thread_optimal_permutation[THREADS_PER_BLOCK];
int thread = threadIdx.x + blockIdx.x * blockDim.x;
thread_optimal_values[threadIdx.x] = INF;
// thread_optimal_paths[threadIdx.x] = new int[N+1];
long long iter_per_thread = factorials[N-1] / (BLOCKS * THREADS_PER_BLOCK);
int arr[MAXN-1];
for (int i = 1; i < N; i++) arr[i-1] = path[i];
long long start_perm = (thread * iter_per_thread) + 1;
thread_optimal_permutation[threadIdx.x] = start_perm;
nth_permutation(arr, N-1, start_perm);
// Last thread of all handles the permutations not entirely divisible by the total threads in all blocks
if (thread == (BLOCKS * THREADS_PER_BLOCK) - 1) {
iter_per_thread += factorials[N-1] % (BLOCKS * THREADS_PER_BLOCK);
}
long long iter = 0;
do {
int temp_path[MAXN+1];
temp_path[0] = 0;
for (int i = 1; i < N; i++) temp_path[i] = arr[i-1];
temp_path[N] = 0;
int val = find_path_cost(matrix, temp_path, N+1, N);
if(val < thread_optimal_values[threadIdx.x])
{
thread_optimal_values[threadIdx.x] = val;
// for (int i = 0; i < N+1; i++) thread_optimal_paths[threadIdx.x][i] = temp_path[i];
thread_optimal_permutation[threadIdx.x] = start_perm + iter;
}
iter++;
nxt_permutation(arr, N-1);
} while (iter < iter_per_thread);
__syncthreads();
if (threadIdx.x == 0) {
int optimal_cost = INF;
for (int i = 0; i < THREADS_PER_BLOCK; i++) {
if (thread_optimal_values[i] < optimal_cost) {
optimal_cost = thread_optimal_values[i];
block_optimal_values[blockIdx.x] = thread_optimal_values[i];
// for (int j = 0; j < N+1; j++) {
// block_optimal_paths[blockIdx.x][j] = thread_optimal_paths[i][j];
// }
block_optimal_permutation[blockIdx.x] = thread_optimal_permutation[i];
}
}
}
}
//////////////////////////////////////////////////////////////
int main(int argc, char **argv) {
const int N = stoi(argv[1]);
precompute_factorial();
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int* matrix = new int[N*N];
int path[N+1];
path[0] = 0;
path[N] = 0;
for (int i = 1; i < N; i++) path[i] = i;
assign_edge_weights(matrix, N);
// print_matrix(matrix, N);
for (int i = 0; i < BLOCKS; i++){
block_optimal_values[i] = INF;
}
int *dev_matrix, *dev_path;
long long *dev_factorial;
int mat_size = N*N*sizeof(int);
int path_size = (N+1)*sizeof(int);
int factorial_size = (MAXN+1)*sizeof(long long);
cudaMalloc((void **)&dev_matrix, mat_size);
cudaMalloc((void **)&dev_path, path_size);
cudaMalloc((void **)&dev_factorial, factorial_size);
cudaEventRecord(start);
// Copy inputs from host to device
cudaMemcpy(dev_matrix, matrix, mat_size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_path, path, path_size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_factorial, factorial, factorial_size, cudaMemcpyHostToDevice);
cudaDeviceSetLimit(cudaLimitMallocHeapSize, 128*1024*1024);
// Launch the TSP kernel
tsp_cuda<<<BLOCKS, THREADS_PER_BLOCK>>>(dev_matrix, dev_path, dev_factorial, N);
cudaDeviceSynchronize();
cudaDeviceSynchronize();
int optimal_cost = INF;
long long optimal_permutation;
for (int i = 0; i < BLOCKS; i++) {
if (block_optimal_values[i] < optimal_cost) {
optimal_cost = block_optimal_values[i];
// for (int j = 0; j < N+1; j++) {
// path[j] = block_optimal_paths[i][j];
// }
optimal_permutation = block_optimal_permutation[i];
}
}
int arr[MAXN-1];
for (int i = 1; i < N; i++) arr[i-1] = path[i];
nth_permutation(arr, N-1, optimal_permutation);
for (int i = 1; i < N; i++) path[i] = arr[i-1];
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("%f\n", milliseconds*0.001);
// printing the minimum cost path
printf("Minimum Cost Path: ");
for (int i = 0; i < N+1; i++) {
printf("%d ", path[i]);
}
printf("\n");
// printing the minimum cost path
int cost = 0;
for(int i=1; i<N+1; i++) {
cost += matrix[path[i]*N + path[i-1]];
}
printf("Path cost: %d \n", cost);
// printing the run-time
// printf("Time taken: %f s\n", milliseconds*0.001);
cudaFree(dev_matrix);
cudaFree(dev_path);
cudaFree(dev_factorial);
} | .file "tmpxft_001bb513_00000000-6_tsp_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10871:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10871:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6randomii
.type _Z6randomii, @function
_Z6randomii:
.LFB10859:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebp
movl %esi, %ebx
call rand@PLT
subl %ebp, %ebx
leal 1(%rbx), %esi
cltd
idivl %esi
leal (%rdx,%rbp), %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10859:
.size _Z6randomii, .-_Z6randomii
.globl _Z20precompute_factorialv
.type _Z20precompute_factorialv, @function
_Z20precompute_factorialv:
.LFB10860:
.cfi_startproc
endbr64
movq $1, factorial(%rip)
movl $1, %eax
leaq factorial(%rip), %rsi
leaq -8(%rsi), %rcx
.L6:
movq %rax, %rdx
imulq (%rcx,%rax,8), %rdx
movq %rdx, (%rsi,%rax,8)
addq $1, %rax
cmpq $17, %rax
jne .L6
ret
.cfi_endproc
.LFE10860:
.size _Z20precompute_factorialv, .-_Z20precompute_factorialv
.globl _Z19assign_edge_weightsPii
.type _Z19assign_edge_weightsPii, @function
_Z19assign_edge_weightsPii:
.LFB10861:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movl %esi, 20(%rsp)
testl %esi, %esi
jle .L8
movslq %esi, %r13
leaq 1(%r13), %rax
movq %rax, 24(%rsp)
salq $2, %r13
leaq 0(%r13,%rdi), %rax
movq %rax, 32(%rsp)
movl $0, %r15d
movl $0, %eax
addq $4, %rdi
movq %rdi, 40(%rsp)
.L12:
leal 1(%rax), %r14d
movl 20(%rsp), %esi
cmpl %r14d, %esi
je .L10
leaq 0(,%r15,4), %rbp
movq 40(%rsp), %rax
leaq (%rax,%rbp), %rbx
movq 32(%rsp), %rax
addq %rax, %rbp
leal -1(%rsi), %eax
subl %r14d, %eax
addq %r15, %rax
movq 8(%rsp), %rdi
leaq 8(%rdi,%rax,4), %r12
.L11:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, (%rbx)
movl %eax, 0(%rbp)
addq $4, %rbx
addq %r13, %rbp
cmpq %r12, %rbx
jne .L11
movq 8(%rsp), %rax
movl $0, (%rax,%r15,4)
movq 24(%rsp), %rax
addq %rax, %r15
movl %r14d, %eax
jmp .L12
.L10:
imull %eax, %r14d
addl %r14d, %eax
cltq
movq 8(%rsp), %rdi
movl $0, (%rdi,%rax,4)
.L8:
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10861:
.size _Z19assign_edge_weightsPii, .-_Z19assign_edge_weightsPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.LC1:
.string "\n"
.text
.globl _Z12print_matrixPii
.type _Z12print_matrixPii, @function
_Z12print_matrixPii:
.LFB10862:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 4(%rsp)
testl %esi, %esi
jle .L15
movl %esi, %eax
cltq
leaq 0(,%rax,4), %r15
leaq (%rdi,%r15), %rbp
negq %rax
salq $2, %rax
movq %rax, 8(%rsp)
movl $0, %r14d
leaq _ZSt4cout(%rip), %r13
leaq .LC0(%rip), %r12
.L17:
movq 8(%rsp), %rax
leaq 0(%rbp,%rax), %rbx
.L18:
movl (%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L18
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 4(%rsp)
jne .L17
.L15:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10862:
.size _Z12print_matrixPii, .-_Z12print_matrixPii
.globl _Z4swapRiS_
.type _Z4swapRiS_, @function
_Z4swapRiS_:
.LFB10863:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE10863:
.size _Z4swapRiS_, .-_Z4swapRiS_
.globl _Z4facti
.type _Z4facti, @function
_Z4facti:
.LFB10864:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L26
leal 1(%rdi), %ecx
movl $1, %eax
movl $1, %edx
.L25:
imulq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rax
jne .L25
.L23:
movq %rdx, %rax
ret
.L26:
movl $1, %edx
jmp .L23
.cfi_endproc
.LFE10864:
.size _Z4facti, .-_Z4facti
.globl _Z15nxt_permutationPii
.type _Z15nxt_permutationPii, @function
_Z15nxt_permutationPii:
.LFB10865:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE10865:
.size _Z15nxt_permutationPii, .-_Z15nxt_permutationPii
.globl _Z14find_path_costPiS_ii
.type _Z14find_path_costPiS_ii, @function
_Z14find_path_costPiS_ii:
.LFB10866:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE10866:
.size _Z14find_path_costPiS_ii, .-_Z14find_path_costPiS_ii
.globl _Z15nth_permutationPiix
.type _Z15nth_permutationPiix, @function
_Z15nth_permutationPiix:
.LFB10867:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movl %esi, %ebx
movl %esi, 4(%rsp)
movq %rdx, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %edi
call _Z4facti
cmpq %rbp, %rax
jl .L49
testl %ebx, %ebx
jle .L34
leaq 16(%rsp), %rax
movslq %ebx, %rdx
addq %rax, %rdx
.L35:
movb $0, (%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L35
movl 4(%rsp), %r13d
movslq %r13d, %rbx
leaq 0(,%rbx,4), %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call _Znam@PLT
movq %rax, %r15
testl %r13d, %r13d
jle .L45
movl $1, %r13d
leaq 16(%rsp), %r12
jmp .L43
.L62:
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L37
call __stack_chk_fail@PLT
.L37:
call __cxa_throw_bad_array_new_length@PLT
.L50:
movl $1, %ecx
jmp .L38
.L40:
addq $1, %rax
cmpq %rbx, %rax
je .L41
.L42:
cmpb $0, (%rax,%r12)
jne .L40
subl $1, %ecx
jne .L40
cltq
movl (%r14,%rax,4), %edx
movl %edx, -4(%r15,%r13,4)
movb $1, 16(%rsp,%rax)
.L41:
leaq 1(%r13), %rax
cmpq %r13, %rbx
je .L60
movq %rax, %r13
.L43:
movl 4(%rsp), %edi
subl %r13d, %edi
call _Z4facti
movq %rax, %rdx
cmpq %rbp, %rax
jge .L50
movl $2, %ecx
.L39:
movq %rdx, %rax
imulq %rcx, %rax
leaq -1(%rcx), %rsi
cqto
idivq %rsi
movq %rax, %rdx
movq %rcx, %rsi
addq $1, %rcx
cmpq %rbp, %rax
jl .L39
movl %esi, %ecx
.L38:
leal -1(%rcx), %eax
cltq
imulq %rdx, %rax
movslq %ecx, %rsi
cqto
idivq %rsi
subq %rax, %rbp
movl $0, %eax
jmp .L42
.L60:
movl $0, %eax
.L44:
movl (%r15,%rax), %edx
movl %edx, (%r14,%rax)
addq $4, %rax
movq 8(%rsp), %rdi
cmpq %rdi, %rax
jne .L44
.L45:
movq %r15, %rdi
call free@PLT
movl $1, %eax
.L32:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L61
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movl $0, %eax
jmp .L32
.L34:
movslq 4(%rsp), %rax
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L62
leaq 0(,%rax,4), %rdi
call _Znam@PLT
movq %rax, %r15
jmp .L45
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10867:
.size _Z15nth_permutationPiix, .-_Z15nth_permutationPiix
.globl _Z32__device_stub__Z8tsp_cudaPiS_PxiPiS_Pxi
.type _Z32__device_stub__Z8tsp_cudaPiS_PxiPiS_Pxi, @function
_Z32__device_stub__Z8tsp_cudaPiS_PxiPiS_Pxi:
.LFB10893:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L67
.L63:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8tsp_cudaPiS_Pxi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L63
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10893:
.size _Z32__device_stub__Z8tsp_cudaPiS_PxiPiS_Pxi, .-_Z32__device_stub__Z8tsp_cudaPiS_PxiPiS_Pxi
.globl _Z8tsp_cudaPiS_Pxi
.type _Z8tsp_cudaPiS_Pxi, @function
_Z8tsp_cudaPiS_Pxi:
.LFB10894:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8tsp_cudaPiS_PxiPiS_Pxi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10894:
.size _Z8tsp_cudaPiS_Pxi, .-_Z8tsp_cudaPiS_Pxi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "basic_string: construction from null is not valid"
.section .rodata.str1.1
.LC3:
.string "stoi"
.LC4:
.string "%d "
.LC5:
.string "Path cost: %d \n"
.LC8:
.string "%f\n"
.LC9:
.string "Minimum Cost Path: "
.text
.globl main
.type main, @function
main:
.LFB10868:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA10868
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $200, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movq 8(%rsi), %r12
leaq -112(%rbp), %rax
movq %rax, -128(%rbp)
testq %r12, %r12
je .L125
movq %r12, %rdi
call strlen@PLT
movq %rax, %rbx
movq %rax, -144(%rbp)
cmpq $15, %rax
ja .L126
cmpq $1, %rax
jne .L76
movzbl (%r12), %eax
movb %al, -112(%rbp)
.L77:
movq -144(%rbp), %rax
movq %rax, -120(%rbp)
movq -128(%rbp), %rdx
movb $0, (%rdx,%rax)
movq -128(%rbp), %r13
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r12d
movl $0, (%rax)
leaq -144(%rbp), %rsi
movl $10, %edx
movq %r13, %rdi
call __isoc23_strtol@PLT
movq %rax, -224(%rbp)
cmpq -144(%rbp), %r13
je .L127
movl (%rbx), %edx
cmpl $34, %edx
je .L80
movl $2147483648, %eax
movq -224(%rbp), %rsi
addq %rsi, %rax
shrq $32, %rax
jne .L80
movl -224(%rbp), %r15d
testl %edx, %edx
jne .L83
movl %r12d, (%rbx)
.L83:
leaq -128(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
call _Z20precompute_factorialv
leaq -200(%rbp), %rdi
.LEHB0:
call cudaEventCreate@PLT
leaq -192(%rbp), %rdi
call cudaEventCreate@PLT
movq -224(%rbp), %rbx
movl %ebx, %r12d
imull %ebx, %r12d
movslq %r12d, %rdi
salq $2, %rdi
call _Znam@PLT
movq %rax, -216(%rbp)
movl %ebx, %eax
addl $1, %eax
movl %eax, -228(%rbp)
cltq
leaq 15(,%rax,4), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L84:
cmpq %rdx, %rsp
je .L85
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L84
.L125:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L128
leaq .LC2(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L128:
call __stack_chk_fail@PLT
.L126:
leaq -144(%rbp), %rsi
leaq -128(%rbp), %rdi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
.LEHE0:
movq %rax, %rdi
movq %rax, -128(%rbp)
movq -144(%rbp), %rax
movq %rax, -112(%rbp)
.L75:
movq %rbx, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L77
.L76:
testq %rax, %rax
je .L77
leaq -112(%rbp), %rdi
jmp .L75
.L127:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L129
leaq .LC3(%rip), %rdi
.LEHB1:
call _ZSt24__throw_invalid_argumentPKc@PLT
.L129:
call __stack_chk_fail@PLT
.L80:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L130
leaq .LC3(%rip), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE1:
.L112:
endbr64
movq %rax, %r13
cmpl $0, (%rbx)
jne .L90
movl %r12d, (%rbx)
.L90:
leaq -128(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L91
call __stack_chk_fail@PLT
.L130:
call __stack_chk_fail@PLT
.L85:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L86
orq $0, -8(%rsp,%rax)
.L86:
leaq 3(%rsp), %r13
movq %r13, %rax
shrq $2, %rax
andq $-4, %r13
movl $0, 0(,%rax,4)
movq -224(%rbp), %rcx
movslq %ecx, %rax
movl $0, 0(%r13,%rax,4)
movl %ecx, %edx
movl $1, %eax
cmpl $1, %ecx
jle .L88
.L92:
movl %eax, 0(%r13,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L92
.L88:
movl %r15d, %esi
movq -216(%rbp), %rdi
call _Z19assign_edge_weightsPii
movl $0, %ebx
jmp .L94
.L91:
movq %r13, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.L93:
movslq %ebx, %rdx
movq _ZL20block_optimal_values(%rip), %rax
movl $1000000000, (%rax,%rdx,4)
addl $1, %ebx
cmpl $50, %ebx
je .L131
.L94:
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
jne .L93
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L93
.L131:
sall $2, %r12d
movslq %r12d, %rbx
leaq -184(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl -228(%rbp), %eax
sall $2, %eax
movslq %eax, %r12
leaq -176(%rbp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq -168(%rbp), %rdi
movl $136, %esi
call cudaMalloc@PLT
movl $0, %esi
movq -200(%rbp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbx, %rdx
movq -216(%rbp), %rsi
movq -184(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq -176(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $136, %edx
leaq factorial(%rip), %rsi
movq -168(%rbp), %rdi
call cudaMemcpy@PLT
movl $134217728, %esi
movl $2, %edi
call cudaDeviceSetLimit@PLT
movl $1024, -144(%rbp)
movl $1, -140(%rbp)
movl $1, -136(%rbp)
movl $50, -156(%rbp)
movl $1, -152(%rbp)
movl $1, -148(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -144(%rbp), %rdx
movl $1, %ecx
movq -156(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L132
.L95:
call cudaDeviceSynchronize@PLT
call cudaDeviceSynchronize@PLT
movl $0, %ebx
movl $1000000000, %r12d
jmp .L100
.L132:
movl %r15d, %ecx
movq -168(%rbp), %rdx
movq -176(%rbp), %rsi
movq -184(%rbp), %rdi
call _Z32__device_stub__Z8tsp_cudaPiS_PxiPiS_Pxi
jmp .L95
.L135:
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
movslq %ebx, %rax
movq _ZL20block_optimal_values(%rip), %rdx
movl (%rdx,%rax,4), %eax
cmpl %r12d, %eax
jge .L97
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
jne .L98
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
movslq %ebx, %rdx
movq _ZL20block_optimal_values(%rip), %rcx
movl (%rcx,%rdx,4), %r12d
testb %al, %al
jne .L99
movq _ZL32__nv_fatbinhandle_for_managed_rt(%rip), %rdi
call __cudaInitModule@PLT
movb %al, _ZL22__nv_inited_managed_rt(%rip)
jmp .L99
.L134:
movq -224(%rbp), %rax
cmpl $1, %eax
jle .L101
movl %eax, %ecx
movl $1, %eax
.L102:
movl 0(%r13,%rax,4), %edx
movl %edx, -132(%rbp,%rax,4)
addq $1, %rax
cmpq %rcx, %rax
jne .L102
movq -224(%rbp), %rbx
leal -1(%rbx), %esi
leaq -128(%rbp), %rdi
movq %r14, %rdx
call _Z15nth_permutationPiix
leal -1(%rbx), %ecx
movl $0, %eax
.L103:
movl -128(%rbp,%rax,4), %edx
movl %edx, 4(%r13,%rax,4)
addq $1, %rax
cmpq %rax, %rcx
jne .L103
movl $0, %esi
movq -192(%rbp), %rdi
call cudaEventRecord@PLT
movq -192(%rbp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, -144(%rbp)
leaq -144(%rbp), %rdi
movq -192(%rbp), %rdx
movq -200(%rbp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd -144(%rbp), %xmm0
mulsd .LC7(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L108:
movl $0, %ebx
leaq .LC4(%rip), %r12
.L105:
movl 0(%r13,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, %r15d
jge .L105
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -224(%rbp), %rax
testl %eax, %eax
jle .L111
movq %r13, %rdx
movl %eax, %eax
leaq 0(%r13,%rax,4), %rsi
movl $0, %ecx
.L107:
movl %r15d, %eax
imull 4(%rdx), %eax
addl (%rdx), %eax
cltq
movq -216(%rbp), %rdi
addl (%rdi,%rax,4), %ecx
addq $4, %rdx
cmpq %rsi, %rdx
jne .L107
.L106:
movl %ecx, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -184(%rbp), %rdi
call cudaFree@PLT
movq -176(%rbp), %rdi
call cudaFree@PLT
movq -168(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L133
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L111:
.cfi_restore_state
movl $0, %ecx
jmp .L106
.L101:
movq -224(%rbp), %rbx
leal -1(%rbx), %esi
leaq -128(%rbp), %rdi
movq %r14, %rdx
call _Z15nth_permutationPiix
movl $0, %esi
movq -192(%rbp), %rdi
call cudaEventRecord@PLT
movq -192(%rbp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, -144(%rbp)
leaq -144(%rbp), %rdi
movq -192(%rbp), %rdx
movq -200(%rbp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd -144(%rbp), %xmm0
mulsd .LC7(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jns .L108
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.LEHE2:
movl $0, %ecx
jmp .L106
.L98:
movl %eax, %r12d
.L99:
movslq %ebx, %rax
movq _ZL25block_optimal_permutation(%rip), %rdx
movslq (%rdx,%rax,4), %r14
.L97:
addl $1, %ebx
cmpl $50, %ebx
je .L134
.L100:
cmpb $0, _ZL22__nv_inited_managed_rt(%rip)
je .L135
movslq %ebx, %rax
movq _ZL20block_optimal_values(%rip), %rdx
movl (%rdx,%rax,4), %eax
cmpl %r12d, %eax
jl .L98
jmp .L97
.L133:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10868:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA10868:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE10868-.LLSDACSB10868
.LLSDACSB10868:
.uleb128 .LEHB0-.LFB10868
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB10868
.uleb128 .LEHE1-.LEHB1
.uleb128 .L112-.LFB10868
.uleb128 0
.uleb128 .LEHB2-.LFB10868
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE10868:
.text
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z8tsp_cudaPiS_Pxi"
.LC11:
.string "block_optimal_values"
.LC12:
.string "block_optimal_permutation"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10896:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
movq %rax, _ZL32__nv_fatbinhandle_for_managed_rt(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z8tsp_cudaPiS_Pxi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $200, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL20block_optimal_values(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterManagedVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $200, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL25block_optimal_permutation(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterManagedVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10896:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section __nv_managed_data__,"aw"
.align 8
.type _ZL25block_optimal_permutation, @object
.size _ZL25block_optimal_permutation, 8
_ZL25block_optimal_permutation:
.zero 8
.align 8
.type _ZL20block_optimal_values, @object
.size _ZL20block_optimal_values, 8
_ZL20block_optimal_values:
.zero 8
.globl factorial
.bss
.align 32
.type factorial, @object
.size factorial, 136
factorial:
.zero 136
.local _ZL32__nv_fatbinhandle_for_managed_rt
.comm _ZL32__nv_fatbinhandle_for_managed_rt,8,8
.local _ZL22__nv_inited_managed_rt
.comm _ZL22__nv_inited_managed_rt,1,1
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long -755914244
.long 1062232653
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<bits/stdc++.h>
using namespace std;
const int THREADS_PER_BLOCK = 1024;
const int BLOCKS = 50;
const int MAXN = 16;
const int INF = 1e9;
const int MIN_EDGE_WEIGHT = 1;
const int MAX_EDGE_WEIGHT = 10;
long long factorial[MAXN+1];
__managed__ int block_optimal_values[BLOCKS];
// __managed__ int block_optimal_paths[BLOCKS][MAXN+1];
__managed__ int block_optimal_permutation[BLOCKS];
/////////////////// Host Functions ///////////////////
__host__ int random(int l, int r) {
return l + rand()%(r-l+1);
}
__host__ void precompute_factorial() {
factorial[0] = 1;
for(int i=1;i<=MAXN;i++)
{
factorial[i] = i * factorial[i-1];
}
}
__host__ void assign_edge_weights(int* matrix, int N) {
for (int i = 0 ; i < N ; i++) {
for (int j = i+1 ; j < N ; j++) {
matrix[i*N + j] = random(MIN_EDGE_WEIGHT,MAX_EDGE_WEIGHT);
matrix[j*N + i] = matrix[i*N + j];
}
matrix[i*N + i] = 0;
}
}
__host__ void print_matrix(int* matrix, int N) {
for(int i=0; i<N; i++) {
for(int j=0; j<N; j++) {
cout << matrix[i*N + j] << " ";
}
printf("\n");
}
}
/////////////////// Device Functions ///////////////////
__device__ void swap(int &a, int &b) {
int temp = a;
a = b;
b = temp;
}
__host__ __device__ long long fact(int n) {
long long ans = 1;
for(int i=1;i<=n;i++) {
ans *= i;
}
return ans;
}
__device__ bool nxt_permutation(int *arr, int n) {
bool nxt_permutation_possible = false;
int fi = -1;
for(int i=n-2;i>=0;i--) {
if(arr[i+1] > arr[i]) {
nxt_permutation_possible = true;
fi = i;
break;
}
}
if(!nxt_permutation_possible)return false;
int next_greater_ele = arr[fi+1], next_greater_ele_ind = fi+1;
for(int i=fi+2;i<n;i++) {
if(arr[i] > arr[fi] && arr[i] < next_greater_ele) {
next_greater_ele = arr[i];
next_greater_ele_ind = i;
}
}
swap(arr[fi],arr[next_greater_ele_ind]);
//Reverse
int li = fi+1, ri = n-1;
while(li < ri) {
swap(arr[li],arr[ri]);
li++;
ri--;
}
return true;
}
__device__ int find_path_cost(int* matrix, int* arr, int arrsize, int n) {
int cost = 0;
for(int i=1; i<arrsize; i++) {
int to = arr[i];
int from = arr[i-1];
cost += matrix[to*n + from];
}
return cost;
}
/////////////////// Global Functions ///////////////////
//Input array should be sorted
__host__ __device__ bool nth_permutation(int *arr, int arrsize, long long n) {
if(n>fact(arrsize))return false;
// Assuming arrSize = N+1
bool taken[MAXN];
for(int i=0; i<arrsize; i++) taken[i] = false;
int *ans = new int[arrsize];
for(int i=0; i<arrsize; i++) {
int cn = 1;
long long cval = fact(arrsize-1-i);
while(cval<n) {
cn++;
cval=(long long)cn*cval;
cval=(long long)cval/(cn-1);
}
long long pval = cval*(cn-1)/cn;
n -= pval;
for(int j=0; j<arrsize; j++) {
if(!taken[j]) {
cn--;
if(cn==0) {
ans[i] = arr[j];
taken[j] = true;
break;
}
}
}
}
for(int i=0; i<arrsize; i++) {
arr[i] = ans[i];
}
free(ans);
return true;
}
__global__ void tsp_cuda(int* matrix, int* path, long long* factorials, int N) {
__shared__ int thread_optimal_values[THREADS_PER_BLOCK];
// __shared__ int* thread_optimal_paths[THREADS_PER_BLOCK];
__shared__ int thread_optimal_permutation[THREADS_PER_BLOCK];
int thread = threadIdx.x + blockIdx.x * blockDim.x;
thread_optimal_values[threadIdx.x] = INF;
// thread_optimal_paths[threadIdx.x] = new int[N+1];
long long iter_per_thread = factorials[N-1] / (BLOCKS * THREADS_PER_BLOCK);
int arr[MAXN-1];
for (int i = 1; i < N; i++) arr[i-1] = path[i];
long long start_perm = (thread * iter_per_thread) + 1;
thread_optimal_permutation[threadIdx.x] = start_perm;
nth_permutation(arr, N-1, start_perm);
// Last thread of all handles the permutations not entirely divisible by the total threads in all blocks
if (thread == (BLOCKS * THREADS_PER_BLOCK) - 1) {
iter_per_thread += factorials[N-1] % (BLOCKS * THREADS_PER_BLOCK);
}
long long iter = 0;
do {
int temp_path[MAXN+1];
temp_path[0] = 0;
for (int i = 1; i < N; i++) temp_path[i] = arr[i-1];
temp_path[N] = 0;
int val = find_path_cost(matrix, temp_path, N+1, N);
if(val < thread_optimal_values[threadIdx.x])
{
thread_optimal_values[threadIdx.x] = val;
// for (int i = 0; i < N+1; i++) thread_optimal_paths[threadIdx.x][i] = temp_path[i];
thread_optimal_permutation[threadIdx.x] = start_perm + iter;
}
iter++;
nxt_permutation(arr, N-1);
} while (iter < iter_per_thread);
__syncthreads();
if (threadIdx.x == 0) {
int optimal_cost = INF;
for (int i = 0; i < THREADS_PER_BLOCK; i++) {
if (thread_optimal_values[i] < optimal_cost) {
optimal_cost = thread_optimal_values[i];
block_optimal_values[blockIdx.x] = thread_optimal_values[i];
// for (int j = 0; j < N+1; j++) {
// block_optimal_paths[blockIdx.x][j] = thread_optimal_paths[i][j];
// }
block_optimal_permutation[blockIdx.x] = thread_optimal_permutation[i];
}
}
}
}
//////////////////////////////////////////////////////////////
int main(int argc, char **argv) {
const int N = stoi(argv[1]);
precompute_factorial();
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int* matrix = new int[N*N];
int path[N+1];
path[0] = 0;
path[N] = 0;
for (int i = 1; i < N; i++) path[i] = i;
assign_edge_weights(matrix, N);
// print_matrix(matrix, N);
for (int i = 0; i < BLOCKS; i++){
block_optimal_values[i] = INF;
}
int *dev_matrix, *dev_path;
long long *dev_factorial;
int mat_size = N*N*sizeof(int);
int path_size = (N+1)*sizeof(int);
int factorial_size = (MAXN+1)*sizeof(long long);
cudaMalloc((void **)&dev_matrix, mat_size);
cudaMalloc((void **)&dev_path, path_size);
cudaMalloc((void **)&dev_factorial, factorial_size);
cudaEventRecord(start);
// Copy inputs from host to device
cudaMemcpy(dev_matrix, matrix, mat_size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_path, path, path_size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_factorial, factorial, factorial_size, cudaMemcpyHostToDevice);
cudaDeviceSetLimit(cudaLimitMallocHeapSize, 128*1024*1024);
// Launch the TSP kernel
tsp_cuda<<<BLOCKS, THREADS_PER_BLOCK>>>(dev_matrix, dev_path, dev_factorial, N);
cudaDeviceSynchronize();
cudaDeviceSynchronize();
int optimal_cost = INF;
long long optimal_permutation;
for (int i = 0; i < BLOCKS; i++) {
if (block_optimal_values[i] < optimal_cost) {
optimal_cost = block_optimal_values[i];
// for (int j = 0; j < N+1; j++) {
// path[j] = block_optimal_paths[i][j];
// }
optimal_permutation = block_optimal_permutation[i];
}
}
int arr[MAXN-1];
for (int i = 1; i < N; i++) arr[i-1] = path[i];
nth_permutation(arr, N-1, optimal_permutation);
for (int i = 1; i < N; i++) path[i] = arr[i-1];
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("%f\n", milliseconds*0.001);
// printing the minimum cost path
printf("Minimum Cost Path: ");
for (int i = 0; i < N+1; i++) {
printf("%d ", path[i]);
}
printf("\n");
// printing the minimum cost path
int cost = 0;
for(int i=1; i<N+1; i++) {
cost += matrix[path[i]*N + path[i-1]];
}
printf("Path cost: %d \n", cost);
// printing the run-time
// printf("Time taken: %f s\n", milliseconds*0.001);
cudaFree(dev_matrix);
cudaFree(dev_path);
cudaFree(dev_factorial);
} | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
const int THREADS_PER_BLOCK = 1024;
const int BLOCKS = 50;
const int MAXN = 16;
const int INF = 1e9;
const int MIN_EDGE_WEIGHT = 1;
const int MAX_EDGE_WEIGHT = 10;
long long factorial[MAXN+1];
__managed__ int block_optimal_values[BLOCKS];
// __managed__ int block_optimal_paths[BLOCKS][MAXN+1];
__managed__ int block_optimal_permutation[BLOCKS];
/////////////////// Host Functions ///////////////////
__host__ int random(int l, int r) {
return l + rand()%(r-l+1);
}
__host__ void precompute_factorial() {
factorial[0] = 1;
for(int i=1;i<=MAXN;i++)
{
factorial[i] = i * factorial[i-1];
}
}
__host__ void assign_edge_weights(int* matrix, int N) {
for (int i = 0 ; i < N ; i++) {
for (int j = i+1 ; j < N ; j++) {
matrix[i*N + j] = random(MIN_EDGE_WEIGHT,MAX_EDGE_WEIGHT);
matrix[j*N + i] = matrix[i*N + j];
}
matrix[i*N + i] = 0;
}
}
__host__ void print_matrix(int* matrix, int N) {
for(int i=0; i<N; i++) {
for(int j=0; j<N; j++) {
cout << matrix[i*N + j] << " ";
}
printf("\n");
}
}
/////////////////// Device Functions ///////////////////
__device__ void swap(int &a, int &b) {
int temp = a;
a = b;
b = temp;
}
__host__ __device__ long long fact(int n) {
long long ans = 1;
for(int i=1;i<=n;i++) {
ans *= i;
}
return ans;
}
__device__ bool nxt_permutation(int *arr, int n) {
bool nxt_permutation_possible = false;
int fi = -1;
for(int i=n-2;i>=0;i--) {
if(arr[i+1] > arr[i]) {
nxt_permutation_possible = true;
fi = i;
break;
}
}
if(!nxt_permutation_possible)return false;
int next_greater_ele = arr[fi+1], next_greater_ele_ind = fi+1;
for(int i=fi+2;i<n;i++) {
if(arr[i] > arr[fi] && arr[i] < next_greater_ele) {
next_greater_ele = arr[i];
next_greater_ele_ind = i;
}
}
swap(arr[fi],arr[next_greater_ele_ind]);
//Reverse
int li = fi+1, ri = n-1;
while(li < ri) {
swap(arr[li],arr[ri]);
li++;
ri--;
}
return true;
}
__device__ int find_path_cost(int* matrix, int* arr, int arrsize, int n) {
int cost = 0;
for(int i=1; i<arrsize; i++) {
int to = arr[i];
int from = arr[i-1];
cost += matrix[to*n + from];
}
return cost;
}
/////////////////// Global Functions ///////////////////
//Input array should be sorted
__host__ __device__ bool nth_permutation(int *arr, int arrsize, long long n) {
if(n>fact(arrsize))return false;
// Assuming arrSize = N+1
bool taken[MAXN];
for(int i=0; i<arrsize; i++) taken[i] = false;
int *ans = new int[arrsize];
for(int i=0; i<arrsize; i++) {
int cn = 1;
long long cval = fact(arrsize-1-i);
while(cval<n) {
cn++;
cval=(long long)cn*cval;
cval=(long long)cval/(cn-1);
}
long long pval = cval*(cn-1)/cn;
n -= pval;
for(int j=0; j<arrsize; j++) {
if(!taken[j]) {
cn--;
if(cn==0) {
ans[i] = arr[j];
taken[j] = true;
break;
}
}
}
}
for(int i=0; i<arrsize; i++) {
arr[i] = ans[i];
}
free(ans);
return true;
}
__global__ void tsp_cuda(int* matrix, int* path, long long* factorials, int N) {
__shared__ int thread_optimal_values[THREADS_PER_BLOCK];
// __shared__ int* thread_optimal_paths[THREADS_PER_BLOCK];
__shared__ int thread_optimal_permutation[THREADS_PER_BLOCK];
int thread = threadIdx.x + blockIdx.x * blockDim.x;
thread_optimal_values[threadIdx.x] = INF;
// thread_optimal_paths[threadIdx.x] = new int[N+1];
long long iter_per_thread = factorials[N-1] / (BLOCKS * THREADS_PER_BLOCK);
int arr[MAXN-1];
for (int i = 1; i < N; i++) arr[i-1] = path[i];
long long start_perm = (thread * iter_per_thread) + 1;
thread_optimal_permutation[threadIdx.x] = start_perm;
nth_permutation(arr, N-1, start_perm);
// Last thread of all handles the permutations not entirely divisible by the total threads in all blocks
if (thread == (BLOCKS * THREADS_PER_BLOCK) - 1) {
iter_per_thread += factorials[N-1] % (BLOCKS * THREADS_PER_BLOCK);
}
long long iter = 0;
do {
int temp_path[MAXN+1];
temp_path[0] = 0;
for (int i = 1; i < N; i++) temp_path[i] = arr[i-1];
temp_path[N] = 0;
int val = find_path_cost(matrix, temp_path, N+1, N);
if(val < thread_optimal_values[threadIdx.x])
{
thread_optimal_values[threadIdx.x] = val;
// for (int i = 0; i < N+1; i++) thread_optimal_paths[threadIdx.x][i] = temp_path[i];
thread_optimal_permutation[threadIdx.x] = start_perm + iter;
}
iter++;
nxt_permutation(arr, N-1);
} while (iter < iter_per_thread);
__syncthreads();
if (threadIdx.x == 0) {
int optimal_cost = INF;
for (int i = 0; i < THREADS_PER_BLOCK; i++) {
if (thread_optimal_values[i] < optimal_cost) {
optimal_cost = thread_optimal_values[i];
block_optimal_values[blockIdx.x] = thread_optimal_values[i];
// for (int j = 0; j < N+1; j++) {
// block_optimal_paths[blockIdx.x][j] = thread_optimal_paths[i][j];
// }
block_optimal_permutation[blockIdx.x] = thread_optimal_permutation[i];
}
}
}
}
//////////////////////////////////////////////////////////////
int main(int argc, char **argv) {
const int N = stoi(argv[1]);
precompute_factorial();
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int* matrix = new int[N*N];
int path[N+1];
path[0] = 0;
path[N] = 0;
for (int i = 1; i < N; i++) path[i] = i;
assign_edge_weights(matrix, N);
// print_matrix(matrix, N);
for (int i = 0; i < BLOCKS; i++){
block_optimal_values[i] = INF;
}
int *dev_matrix, *dev_path;
long long *dev_factorial;
int mat_size = N*N*sizeof(int);
int path_size = (N+1)*sizeof(int);
int factorial_size = (MAXN+1)*sizeof(long long);
hipMalloc((void **)&dev_matrix, mat_size);
hipMalloc((void **)&dev_path, path_size);
hipMalloc((void **)&dev_factorial, factorial_size);
hipEventRecord(start);
// Copy inputs from host to device
hipMemcpy(dev_matrix, matrix, mat_size, hipMemcpyHostToDevice);
hipMemcpy(dev_path, path, path_size, hipMemcpyHostToDevice);
hipMemcpy(dev_factorial, factorial, factorial_size, hipMemcpyHostToDevice);
hipDeviceSetLimit(hipLimitMallocHeapSize, 128*1024*1024);
// Launch the TSP kernel
tsp_cuda<<<BLOCKS, THREADS_PER_BLOCK>>>(dev_matrix, dev_path, dev_factorial, N);
hipDeviceSynchronize();
hipDeviceSynchronize();
int optimal_cost = INF;
long long optimal_permutation;
for (int i = 0; i < BLOCKS; i++) {
if (block_optimal_values[i] < optimal_cost) {
optimal_cost = block_optimal_values[i];
// for (int j = 0; j < N+1; j++) {
// path[j] = block_optimal_paths[i][j];
// }
optimal_permutation = block_optimal_permutation[i];
}
}
int arr[MAXN-1];
for (int i = 1; i < N; i++) arr[i-1] = path[i];
nth_permutation(arr, N-1, optimal_permutation);
for (int i = 1; i < N; i++) path[i] = arr[i-1];
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("%f\n", milliseconds*0.001);
// printing the minimum cost path
printf("Minimum Cost Path: ");
for (int i = 0; i < N+1; i++) {
printf("%d ", path[i]);
}
printf("\n");
// printing the minimum cost path
int cost = 0;
for(int i=1; i<N+1; i++) {
cost += matrix[path[i]*N + path[i-1]];
}
printf("Path cost: %d \n", cost);
// printing the run-time
// printf("Time taken: %f s\n", milliseconds*0.001);
hipFree(dev_matrix);
hipFree(dev_path);
hipFree(dev_factorial);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
const int THREADS_PER_BLOCK = 1024;
const int BLOCKS = 50;
const int MAXN = 16;
const int INF = 1e9;
const int MIN_EDGE_WEIGHT = 1;
const int MAX_EDGE_WEIGHT = 10;
long long factorial[MAXN+1];
__managed__ int block_optimal_values[BLOCKS];
// __managed__ int block_optimal_paths[BLOCKS][MAXN+1];
__managed__ int block_optimal_permutation[BLOCKS];
/////////////////// Host Functions ///////////////////
__host__ int random(int l, int r) {
return l + rand()%(r-l+1);
}
__host__ void precompute_factorial() {
factorial[0] = 1;
for(int i=1;i<=MAXN;i++)
{
factorial[i] = i * factorial[i-1];
}
}
__host__ void assign_edge_weights(int* matrix, int N) {
for (int i = 0 ; i < N ; i++) {
for (int j = i+1 ; j < N ; j++) {
matrix[i*N + j] = random(MIN_EDGE_WEIGHT,MAX_EDGE_WEIGHT);
matrix[j*N + i] = matrix[i*N + j];
}
matrix[i*N + i] = 0;
}
}
__host__ void print_matrix(int* matrix, int N) {
for(int i=0; i<N; i++) {
for(int j=0; j<N; j++) {
cout << matrix[i*N + j] << " ";
}
printf("\n");
}
}
/////////////////// Device Functions ///////////////////
__device__ void swap(int &a, int &b) {
int temp = a;
a = b;
b = temp;
}
__host__ __device__ long long fact(int n) {
long long ans = 1;
for(int i=1;i<=n;i++) {
ans *= i;
}
return ans;
}
__device__ bool nxt_permutation(int *arr, int n) {
bool nxt_permutation_possible = false;
int fi = -1;
for(int i=n-2;i>=0;i--) {
if(arr[i+1] > arr[i]) {
nxt_permutation_possible = true;
fi = i;
break;
}
}
if(!nxt_permutation_possible)return false;
int next_greater_ele = arr[fi+1], next_greater_ele_ind = fi+1;
for(int i=fi+2;i<n;i++) {
if(arr[i] > arr[fi] && arr[i] < next_greater_ele) {
next_greater_ele = arr[i];
next_greater_ele_ind = i;
}
}
swap(arr[fi],arr[next_greater_ele_ind]);
//Reverse
int li = fi+1, ri = n-1;
while(li < ri) {
swap(arr[li],arr[ri]);
li++;
ri--;
}
return true;
}
__device__ int find_path_cost(int* matrix, int* arr, int arrsize, int n) {
int cost = 0;
for(int i=1; i<arrsize; i++) {
int to = arr[i];
int from = arr[i-1];
cost += matrix[to*n + from];
}
return cost;
}
/////////////////// Global Functions ///////////////////
//Input array should be sorted
__host__ __device__ bool nth_permutation(int *arr, int arrsize, long long n) {
if(n>fact(arrsize))return false;
// Assuming arrSize = N+1
bool taken[MAXN];
for(int i=0; i<arrsize; i++) taken[i] = false;
int *ans = new int[arrsize];
for(int i=0; i<arrsize; i++) {
int cn = 1;
long long cval = fact(arrsize-1-i);
while(cval<n) {
cn++;
cval=(long long)cn*cval;
cval=(long long)cval/(cn-1);
}
long long pval = cval*(cn-1)/cn;
n -= pval;
for(int j=0; j<arrsize; j++) {
if(!taken[j]) {
cn--;
if(cn==0) {
ans[i] = arr[j];
taken[j] = true;
break;
}
}
}
}
for(int i=0; i<arrsize; i++) {
arr[i] = ans[i];
}
free(ans);
return true;
}
__global__ void tsp_cuda(int* matrix, int* path, long long* factorials, int N) {
__shared__ int thread_optimal_values[THREADS_PER_BLOCK];
// __shared__ int* thread_optimal_paths[THREADS_PER_BLOCK];
__shared__ int thread_optimal_permutation[THREADS_PER_BLOCK];
int thread = threadIdx.x + blockIdx.x * blockDim.x;
thread_optimal_values[threadIdx.x] = INF;
// thread_optimal_paths[threadIdx.x] = new int[N+1];
long long iter_per_thread = factorials[N-1] / (BLOCKS * THREADS_PER_BLOCK);
int arr[MAXN-1];
for (int i = 1; i < N; i++) arr[i-1] = path[i];
long long start_perm = (thread * iter_per_thread) + 1;
thread_optimal_permutation[threadIdx.x] = start_perm;
nth_permutation(arr, N-1, start_perm);
// Last thread of all handles the permutations not entirely divisible by the total threads in all blocks
if (thread == (BLOCKS * THREADS_PER_BLOCK) - 1) {
iter_per_thread += factorials[N-1] % (BLOCKS * THREADS_PER_BLOCK);
}
long long iter = 0;
do {
int temp_path[MAXN+1];
temp_path[0] = 0;
for (int i = 1; i < N; i++) temp_path[i] = arr[i-1];
temp_path[N] = 0;
int val = find_path_cost(matrix, temp_path, N+1, N);
if(val < thread_optimal_values[threadIdx.x])
{
thread_optimal_values[threadIdx.x] = val;
// for (int i = 0; i < N+1; i++) thread_optimal_paths[threadIdx.x][i] = temp_path[i];
thread_optimal_permutation[threadIdx.x] = start_perm + iter;
}
iter++;
nxt_permutation(arr, N-1);
} while (iter < iter_per_thread);
__syncthreads();
if (threadIdx.x == 0) {
int optimal_cost = INF;
for (int i = 0; i < THREADS_PER_BLOCK; i++) {
if (thread_optimal_values[i] < optimal_cost) {
optimal_cost = thread_optimal_values[i];
block_optimal_values[blockIdx.x] = thread_optimal_values[i];
// for (int j = 0; j < N+1; j++) {
// block_optimal_paths[blockIdx.x][j] = thread_optimal_paths[i][j];
// }
block_optimal_permutation[blockIdx.x] = thread_optimal_permutation[i];
}
}
}
}
//////////////////////////////////////////////////////////////
int main(int argc, char **argv) {
const int N = stoi(argv[1]);
precompute_factorial();
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int* matrix = new int[N*N];
int path[N+1];
path[0] = 0;
path[N] = 0;
for (int i = 1; i < N; i++) path[i] = i;
assign_edge_weights(matrix, N);
// print_matrix(matrix, N);
for (int i = 0; i < BLOCKS; i++){
block_optimal_values[i] = INF;
}
int *dev_matrix, *dev_path;
long long *dev_factorial;
int mat_size = N*N*sizeof(int);
int path_size = (N+1)*sizeof(int);
int factorial_size = (MAXN+1)*sizeof(long long);
hipMalloc((void **)&dev_matrix, mat_size);
hipMalloc((void **)&dev_path, path_size);
hipMalloc((void **)&dev_factorial, factorial_size);
hipEventRecord(start);
// Copy inputs from host to device
hipMemcpy(dev_matrix, matrix, mat_size, hipMemcpyHostToDevice);
hipMemcpy(dev_path, path, path_size, hipMemcpyHostToDevice);
hipMemcpy(dev_factorial, factorial, factorial_size, hipMemcpyHostToDevice);
hipDeviceSetLimit(hipLimitMallocHeapSize, 128*1024*1024);
// Launch the TSP kernel
tsp_cuda<<<BLOCKS, THREADS_PER_BLOCK>>>(dev_matrix, dev_path, dev_factorial, N);
hipDeviceSynchronize();
hipDeviceSynchronize();
int optimal_cost = INF;
long long optimal_permutation;
for (int i = 0; i < BLOCKS; i++) {
if (block_optimal_values[i] < optimal_cost) {
optimal_cost = block_optimal_values[i];
// for (int j = 0; j < N+1; j++) {
// path[j] = block_optimal_paths[i][j];
// }
optimal_permutation = block_optimal_permutation[i];
}
}
int arr[MAXN-1];
for (int i = 1; i < N; i++) arr[i-1] = path[i];
nth_permutation(arr, N-1, optimal_permutation);
for (int i = 1; i < N; i++) path[i] = arr[i-1];
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("%f\n", milliseconds*0.001);
// printing the minimum cost path
printf("Minimum Cost Path: ");
for (int i = 0; i < N+1; i++) {
printf("%d ", path[i]);
}
printf("\n");
// printing the minimum cost path
int cost = 0;
for(int i=1; i<N+1; i++) {
cost += matrix[path[i]*N + path[i-1]];
}
printf("Path cost: %d \n", cost);
// printing the run-time
// printf("Time taken: %f s\n", milliseconds*0.001);
hipFree(dev_matrix);
hipFree(dev_path);
hipFree(dev_factorial);
} | .text
.file "tsp_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z6randomii # -- Begin function _Z6randomii
.p2align 4, 0x90
.type _Z6randomii,@function
_Z6randomii: # @_Z6randomii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
callq rand
subl %ebp, %ebx
incl %ebx
cltd
idivl %ebx
addl %edx, %ebp
movl %ebp, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6randomii, .Lfunc_end0-_Z6randomii
.cfi_endproc
# -- End function
.globl _Z20precompute_factorialv # -- Begin function _Z20precompute_factorialv
.p2align 4, 0x90
.type _Z20precompute_factorialv,@function
_Z20precompute_factorialv: # @_Z20precompute_factorialv
.cfi_startproc
# %bb.0:
movq $1, factorial(%rip)
movl $1, %eax
movl $1, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
imulq %rcx, %rax
movq %rax, factorial(,%rcx,8)
incq %rcx
cmpq $17, %rcx
jne .LBB1_1
# %bb.2:
retq
.Lfunc_end1:
.size _Z20precompute_factorialv, .Lfunc_end1-_Z20precompute_factorialv
.cfi_endproc
# -- End function
.globl _Z19assign_edge_weightsPii # -- Begin function _Z19assign_edge_weightsPii
.p2align 4, 0x90
.type _Z19assign_edge_weightsPii,@function
_Z19assign_edge_weightsPii: # @_Z19assign_edge_weightsPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $esi killed $esi def $rsi
movq %rdi, 16(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.lr.ph28
movq 24(%rsp), %rax # 8-byte Reload
leal 1(%rax), %ecx
movl %ecx, 12(%rsp) # 4-byte Spill
movl %eax, %ecx
leaq (,%rcx,4), %r12
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rax,%rcx,4), %rdx
movq %rdx, 40(%rsp) # 8-byte Spill
leaq 4(,%rcx,4), %rdx
movq %rdx, 48(%rsp) # 8-byte Spill
xorl %edx, %edx
movq %rdx, (%rsp) # 8-byte Spill
movq %rcx, %r15
movq %rax, 32(%rsp) # 8-byte Spill
xorl %ebp, %ebp
movq %rcx, 56(%rsp) # 8-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
imull 12(%rsp), %ebp # 4-byte Folded Reload
movslq %ebp, %rax
movq 16(%rsp), %rcx # 8-byte Reload
movl $0, (%rcx,%rax,4)
addq $4, 32(%rsp) # 8-byte Folded Spill
movq (%rsp), %rax # 8-byte Reload
addl 24(%rsp), %eax # 4-byte Folded Reload
movq %rax, (%rsp) # 8-byte Spill
movq 48(%rsp), %rax # 8-byte Reload
addq %rax, 40(%rsp) # 8-byte Folded Spill
decq %r15
movq 64(%rsp), %rax # 8-byte Reload
movq %rax, %rbp
movq 56(%rsp), %rcx # 8-byte Reload
cmpq %rcx, %rax
je .LBB2_6
.LBB2_2: # =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
leaq 1(%rbp), %rax
movq %rax, 64(%rsp) # 8-byte Spill
cmpq %rcx, %rax
jae .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl (%rsp), %eax # 4-byte Reload
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
movl $1, %r14d
movq 40(%rsp), %rbx # 8-byte Reload
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r13,%r14,4)
movl %eax, (%rbx)
incq %r14
addq %r12, %rbx
cmpq %r14, %r15
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge29
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z19assign_edge_weightsPii, .Lfunc_end2-_Z19assign_edge_weightsPii
.cfi_endproc
# -- End function
.globl _Z12print_matrixPii # -- Begin function _Z12print_matrixPii
.p2align 4, 0x90
.type _Z12print_matrixPii,@function
_Z12print_matrixPii: # @_Z12print_matrixPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbp,%r14,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq %r14, %r15
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB3_2
.LBB3_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12print_matrixPii, .Lfunc_end3-_Z12print_matrixPii
.cfi_endproc
# -- End function
.globl _Z4facti # -- Begin function _Z4facti
.p2align 4, 0x90
.type _Z4facti,@function
_Z4facti: # @_Z4facti
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
testl %edi, %edi
jle .LBB4_1
# %bb.3: # %.lr.ph.preheader
incl %edi
movl $1, %ecx
movl $1, %eax
.p2align 4, 0x90
.LBB4_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
imulq %rcx, %rax
incq %rcx
cmpq %rcx, %rdi
jne .LBB4_4
# %bb.2: # %._crit_edge
retq
.LBB4_1:
movl $1, %eax
retq
.Lfunc_end4:
.size _Z4facti, .Lfunc_end4-_Z4facti
.cfi_endproc
# -- End function
.globl _Z15nth_permutationPiix # -- Begin function _Z15nth_permutationPiix
.p2align 4, 0x90
.type _Z15nth_permutationPiix,@function
_Z15nth_permutationPiix: # @_Z15nth_permutationPiix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movl %esi, %r15d
movq %rdi, %r14
testl %esi, %esi
jle .LBB5_1
# %bb.2: # %.lr.ph.preheader.i
leal 1(%r15), %eax
movl $1, %ecx
movl $1, %ebp
.p2align 4, 0x90
.LBB5_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
imulq %rcx, %rbp
incq %rcx
cmpq %rcx, %rax
jne .LBB5_3
# %bb.4: # %_Z4facti.exit
cmpq %rbx, %rbp
jge .LBB5_5
jmp .LBB5_22
.LBB5_1:
movl $1, %ebp
cmpq %rbx, %rbp
jl .LBB5_22
.LBB5_5:
movl %r15d, %r12d
testl %r15d, %r15d
jle .LBB5_7
# %bb.6: # %.lr.ph.preheader
movq %rsp, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
.LBB5_7: # %._crit_edge
movslq %r15d, %rax
shlq $2, %rax
testl %r15d, %r15d
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %r13
testl %r15d, %r15d
jle .LBB5_19
# %bb.8: # %.lr.ph81
xorl %esi, %esi
movl %r15d, %edi
movq %rbx, %r8
jmp .LBB5_9
.p2align 4, 0x90
.LBB5_24: # %.loopexit
# in Loop: Header=BB5_9 Depth=1
incq %rsi
decl %edi
cmpq %r12, %rsi
je .LBB5_19
.LBB5_9: # =>This Loop Header: Depth=1
# Child Loop BB5_11 Depth 2
# Child Loop BB5_14 Depth 2
# Child Loop BB5_16 Depth 2
movl %edi, %edi
movl %esi, %ecx
subl %r15d, %ecx
movl $1, %eax
cmpl $-2, %ecx
jg .LBB5_12
# %bb.10: # %.lr.ph.preheader.i54
# in Loop: Header=BB5_9 Depth=1
movl $1, %ecx
.p2align 4, 0x90
.LBB5_11: # %.lr.ph.i56
# Parent Loop BB5_9 Depth=1
# => This Inner Loop Header: Depth=2
imulq %rcx, %rax
incq %rcx
cmpq %rcx, %rdi
jne .LBB5_11
.LBB5_12: # %_Z4facti.exit62
# in Loop: Header=BB5_9 Depth=1
movl $1, %r9d
cmpq %r8, %rax
jge .LBB5_15
# %bb.13: # %.lr.ph69.preheader
# in Loop: Header=BB5_9 Depth=1
movl $1, %r9d
.p2align 4, 0x90
.LBB5_14: # %.lr.ph69
# Parent Loop BB5_9 Depth=1
# => This Inner Loop Header: Depth=2
movq %r9, %rcx
incq %r9
imulq %r9, %rax
cqto
idivq %rcx
cmpq %r8, %rax
jl .LBB5_14
.LBB5_15: # %._crit_edge70
# in Loop: Header=BB5_9 Depth=1
leal -1(%r9), %ecx
movslq %ecx, %rcx
imulq %rax, %rcx
movl %r9d, %r10d
movq %rcx, %rax
cqto
idivq %r10
subq %rax, %r8
xorl %eax, %eax
jmp .LBB5_16
.p2align 4, 0x90
.LBB5_23: # in Loop: Header=BB5_16 Depth=2
incq %rax
cmpq %rax, %r12
je .LBB5_24
.LBB5_16: # %.lr.ph76
# Parent Loop BB5_9 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $0, (%rsp,%rax)
jne .LBB5_23
# %bb.17: # in Loop: Header=BB5_16 Depth=2
decl %r9d
jne .LBB5_23
# %bb.18: # in Loop: Header=BB5_9 Depth=1
movl (%r14,%rax,4), %ecx
movl %ecx, (%r13,%rsi,4)
movb $1, (%rsp,%rax)
jmp .LBB5_24
.LBB5_19: # %.preheader
testl %r15d, %r15d
jle .LBB5_21
# %bb.20: # %.lr.ph83.preheader
shlq $2, %r12
movq %r14, %rdi
movq %r13, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB5_21: # %._crit_edge84
movq %r13, %rdi
callq free
.LBB5_22:
cmpq %rbx, %rbp
setge %al
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z15nth_permutationPiix, .Lfunc_end5-_Z15nth_permutationPiix
.cfi_endproc
# -- End function
.globl _Z23__device_stub__tsp_cudaPiS_Pxi # -- Begin function _Z23__device_stub__tsp_cudaPiS_Pxi
.p2align 4, 0x90
.type _Z23__device_stub__tsp_cudaPiS_Pxi,@function
_Z23__device_stub__tsp_cudaPiS_Pxi: # @_Z23__device_stub__tsp_cudaPiS_Pxi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8tsp_cudaPiS_Pxi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z23__device_stub__tsp_cudaPiS_Pxi, .Lfunc_end6-_Z23__device_stub__tsp_cudaPiS_Pxi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI7_0:
.quad 0x3f50624dd2f1a9fc # double 0.001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $296, %rsp # imm = 0x128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq 8(%rsi), %rbx
leaq -192(%rbp), %r12
movq %r12, -208(%rbp)
testq %rbx, %rbx
je .LBB7_55
# %bb.1:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq strlen
movq %rax, %r14
cmpq $16, %rax
jb .LBB7_5
# %bb.2:
testq %r14, %r14
js .LBB7_56
# %bb.3:
movq %r14, %rdi
incq %rdi
js .LBB7_57
# %bb.4: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
.cfi_escape 0x2e, 0x00
callq _Znwm
movq %rax, -208(%rbp)
movq %r14, -192(%rbp)
.LBB7_5:
testq %r14, %r14
je .LBB7_9
# %bb.6:
movq -208(%rbp), %rdi
cmpq $1, %r14
jne .LBB7_8
# %bb.7:
movzbl (%rbx), %eax
movb %al, (%rdi)
jmp .LBB7_9
.LBB7_8:
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB7_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
movq %r14, -200(%rbp)
movq -208(%rbp), %rax
movb $0, (%rax,%r14)
movq -208(%rbp), %r15
.cfi_escape 0x2e, 0x00
callq __errno_location
movq %rax, %r14
movl (%rax), %r13d
movl $0, (%rax)
.cfi_escape 0x2e, 0x00
leaq -56(%rbp), %rsi
movq %r15, %rdi
movl $10, %edx
callq __isoc23_strtol
cmpq %r15, -56(%rbp)
je .LBB7_10
# %bb.17:
movslq %eax, %rcx
cmpq %rax, %rcx
jne .LBB7_19
# %bb.18:
movq %rax, %r15
movl (%r14), %eax
cmpl $34, %eax
je .LBB7_19
# %bb.21:
testl %eax, %eax
jne .LBB7_23
# %bb.22:
movl %r13d, (%r14)
.LBB7_23: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit
movq -208(%rbp), %rdi
cmpq %r12, %rdi
je .LBB7_25
# %bb.24: # %.critedge.i.i83
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB7_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq $1, factorial(%rip)
movl $1, %eax
movl $1, %ecx
.p2align 4, 0x90
.LBB7_26: # =>This Inner Loop Header: Depth=1
imulq %rcx, %rax
movq %rax, factorial(,%rcx,8)
incq %rcx
cmpq $17, %rcx
jne .LBB7_26
# %bb.27: # %_Z20precompute_factorialv.exit
.cfi_escape 0x2e, 0x00
leaq -144(%rbp), %rdi
callq hipEventCreate
.cfi_escape 0x2e, 0x00
leaq -104(%rbp), %rdi
callq hipEventCreate
movl %r15d, %eax
imull %eax, %eax
movq %rax, -216(%rbp) # 8-byte Spill
leaq (,%rax,4), %rdi
.cfi_escape 0x2e, 0x00
callq _Znam
movq %rax, %r14
movq %rsp, -232(%rbp) # 8-byte Spill
leal 1(%r15), %ecx
.cfi_escape 0x2e, 0x00
movq %rsp, %rax
movq %rcx, -64(%rbp) # 8-byte Spill
leaq 15(,%rcx,4), %rcx
andq $-16, %rcx
movq %rax, %rdx
subq %rcx, %rdx
movq %rdx, %rsp
negq %rcx
movl $0, (%rax,%rcx)
movslq %r15d, %rax
movl $0, (%rdx,%rax,4)
cmpl $2, %r15d
jl .LBB7_30
# %bb.28: # %.lr.ph.preheader
movl %r15d, %eax
movl $1, %ecx
.p2align 4, 0x90
.LBB7_29: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB7_29
.LBB7_30: # %._crit_edge
movq %rdx, -224(%rbp) # 8-byte Spill
testl %r15d, %r15d
movq %r14, -120(%rbp) # 8-byte Spill
jle .LBB7_31
# %bb.50: # %.lr.ph28.i
movl %r15d, %eax
leaq (,%rax,4), %r13
leaq (%r14,%rax,4), %rcx
movq %rcx, -136(%rbp) # 8-byte Spill
leaq 4(,%rax,4), %rcx
movq %rcx, -240(%rbp) # 8-byte Spill
xorl %ecx, %ecx
movq %rcx, -72(%rbp) # 8-byte Spill
movq %rax, %r12
movq %r14, -128(%rbp) # 8-byte Spill
xorl %edx, %edx
movq %r15, -256(%rbp) # 8-byte Spill
movq %rax, -248(%rbp) # 8-byte Spill
jmp .LBB7_51
.p2align 4, 0x90
.LBB7_54: # %._crit_edge.i
# in Loop: Header=BB7_51 Depth=1
movq -264(%rbp), %rax # 8-byte Reload
imull -64(%rbp), %eax # 4-byte Folded Reload
cltq
movq -120(%rbp), %r14 # 8-byte Reload
movl $0, (%r14,%rax,4)
addq $4, -128(%rbp) # 8-byte Folded Spill
movq -256(%rbp), %r15 # 8-byte Reload
movq -72(%rbp), %rax # 8-byte Reload
addl %r15d, %eax
movq %rax, -72(%rbp) # 8-byte Spill
decq %r12
movq -240(%rbp), %rax # 8-byte Reload
addq %rax, -136(%rbp) # 8-byte Folded Spill
movq -272(%rbp), %rcx # 8-byte Reload
movq %rcx, %rdx
movq -248(%rbp), %rax # 8-byte Reload
cmpq %rax, %rcx
je .LBB7_31
.LBB7_51: # =>This Loop Header: Depth=1
# Child Loop BB7_53 Depth 2
movq %rdx, -264(%rbp) # 8-byte Spill
leaq 1(%rdx), %rcx
movq %rcx, -272(%rbp) # 8-byte Spill
cmpq %rax, %rcx
jae .LBB7_54
# %bb.52: # %.lr.ph.i
# in Loop: Header=BB7_51 Depth=1
movl -72(%rbp), %eax # 4-byte Reload
movq -128(%rbp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
movl $1, %r14d
movq -136(%rbp), %rbx # 8-byte Reload
.p2align 4, 0x90
.LBB7_53: # Parent Loop BB7_51 Depth=1
# => This Inner Loop Header: Depth=2
.cfi_escape 0x2e, 0x00
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r15,%r14,4)
movl %eax, (%rbx)
incq %r14
addq %r13, %rbx
cmpq %r14, %r12
jne .LBB7_53
jmp .LBB7_54
.LBB7_31: # %_Z19assign_edge_weightsPii.exit.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB7_32: # %_Z19assign_edge_weightsPii.exit
# =>This Inner Loop Header: Depth=1
movq block_optimal_values(%rip), %rcx
movl $1000000000, (%rcx,%rax,4) # imm = 0x3B9ACA00
incq %rax
cmpq $50, %rax
jne .LBB7_32
# %bb.33:
movq -216(%rbp), %rcx # 8-byte Reload
shll $2, %ecx
movq -64(%rbp), %rax # 8-byte Reload
leal (,%rax,4), %ebx
movslq %ecx, %r12
.cfi_escape 0x2e, 0x00
leaq -96(%rbp), %rdi
movq %r12, %rsi
callq hipMalloc
movslq %ebx, %rbx
.cfi_escape 0x2e, 0x00
leaq -88(%rbp), %rdi
movq %rbx, %rsi
callq hipMalloc
.cfi_escape 0x2e, 0x00
leaq -80(%rbp), %rdi
movl $136, %esi
callq hipMalloc
movq -144(%rbp), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
movq -96(%rbp), %rdi
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq -88(%rbp), %rdi
.cfi_escape 0x2e, 0x00
movq -224(%rbp), %r13 # 8-byte Reload
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq -80(%rbp), %rdi
.cfi_escape 0x2e, 0x00
movl $factorial, %esi
movl $136, %edx
movl $1, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
movl $134217728, %esi # imm = 0x8000000
movl $2, %edi
callq hipDeviceSetLimit
movabsq $4294967346, %rdi # imm = 0x100000032
leaq 974(%rdi), %rdx
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_35
# %bb.34:
movq -96(%rbp), %rax
movq -88(%rbp), %rcx
movq -80(%rbp), %rdx
movq %rax, -328(%rbp)
movq %rcx, -320(%rbp)
movq %rdx, -312(%rbp)
movl %r15d, -108(%rbp)
leaq -328(%rbp), %rax
movq %rax, -208(%rbp)
leaq -320(%rbp), %rax
movq %rax, -200(%rbp)
leaq -312(%rbp), %rax
movq %rax, -192(%rbp)
leaq -108(%rbp), %rax
movq %rax, -184(%rbp)
.cfi_escape 0x2e, 0x00
leaq -56(%rbp), %rdi
leaq -304(%rbp), %rsi
leaq -288(%rbp), %rdx
leaq -280(%rbp), %rcx
callq __hipPopCallConfiguration
movq -56(%rbp), %rsi
movl -48(%rbp), %edx
movq -304(%rbp), %rcx
movl -296(%rbp), %r8d
.cfi_escape 0x2e, 0x10
leaq -208(%rbp), %r9
movl $_Z8tsp_cudaPiS_Pxi, %edi
pushq -280(%rbp)
pushq -288(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB7_35:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
movl $1000000000, %edx # imm = 0x3B9ACA00
xorl %eax, %eax
movq block_optimal_values(%rip), %rcx
# implicit-def: $r12
jmp .LBB7_36
.p2align 4, 0x90
.LBB7_38: # in Loop: Header=BB7_36 Depth=1
incq %rax
cmpq $50, %rax
je .LBB7_39
.LBB7_36: # =>This Inner Loop Header: Depth=1
movl (%rcx,%rax,4), %esi
cmpl %edx, %esi
jge .LBB7_38
# %bb.37: # in Loop: Header=BB7_36 Depth=1
movq block_optimal_permutation(%rip), %rdx
movslq (%rdx,%rax,4), %r12
movl %esi, %edx
jmp .LBB7_38
.LBB7_39:
cmpl $2, %r15d
jl .LBB7_41
# %bb.40: # %.lr.ph103.preheader
leaq 4(%r13), %rsi
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
leaq (%rax,%r15,4), %rdx
andq %rax, %rdx
.cfi_escape 0x2e, 0x00
leaq -208(%rbp), %rdi
callq memcpy@PLT
.LBB7_41: # %._crit_edge104
leal -1(%r15), %esi
.cfi_escape 0x2e, 0x00
leaq -208(%rbp), %rdi
movq %r12, %rdx
callq _Z15nth_permutationPiix
cmpl $2, %r15d
jl .LBB7_43
# %bb.42: # %.lr.ph107.preheader
leaq 4(%r13), %rdi
movabsq $17179869180, %rax # imm = 0x3FFFFFFFC
leaq (%rax,%r15,4), %rdx
andq %rax, %rdx
.cfi_escape 0x2e, 0x00
leaq -208(%rbp), %rsi
callq memcpy@PLT
.LBB7_43: # %._crit_edge108
movq -104(%rbp), %rdi
.cfi_escape 0x2e, 0x00
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq -104(%rbp), %rdi
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
movl $0, -56(%rbp)
movq -144(%rbp), %rsi
movq -104(%rbp), %rdx
.cfi_escape 0x2e, 0x00
leaq -56(%rbp), %rdi
callq hipEventElapsedTime
movss -56(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
mulsd .LCPI7_0(%rip), %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
movb $1, %al
callq printf
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl -64(%rbp), %ebx # 4-byte Reload
testl %r15d, %r15d
js .LBB7_46
# %bb.44: # %.lr.ph112.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB7_45: # %.lr.ph112
# =>This Inner Loop Header: Depth=1
movl (%r13,%r14,4), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %rbx
jne .LBB7_45
.LBB7_46: # %._crit_edge113
.cfi_escape 0x2e, 0x00
movl $10, %edi
callq putchar@PLT
testl %r15d, %r15d
movq -120(%rbp), %rdi # 8-byte Reload
jle .LBB7_49
# %bb.47: # %.lr.ph118.preheader
xorl %r12d, %r12d
movl $1, %eax
movslq %r15d, %rcx
.p2align 4, 0x90
.LBB7_48: # %.lr.ph118
# =>This Inner Loop Header: Depth=1
movslq (%r13,%rax,4), %rdx
imulq %rcx, %rdx
movslq -4(%r13,%rax,4), %rsi
addq %rdx, %rsi
addl (%rdi,%rsi,4), %r12d
incq %rax
cmpq %rax, %rbx
jne .LBB7_48
.LBB7_49: # %._crit_edge119
.cfi_escape 0x2e, 0x00
movl $.L.str.5, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movq -96(%rbp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq -88(%rbp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq -80(%rbp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq -232(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB7_57: # %.noexc11.i
.cfi_def_cfa %rbp, 16
.cfi_escape 0x2e, 0x00
callq _ZSt17__throw_bad_allocv
.LBB7_55: # %.noexc
.cfi_escape 0x2e, 0x00
movl $.L.str.7, %edi
callq _ZSt19__throw_logic_errorPKc
.LBB7_10:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp3:
# %bb.11:
.LBB7_19: # %.critedge.i.i
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $.L.str.6, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp1:
# %bb.20:
.LBB7_56: # %.noexc.i
.cfi_escape 0x2e, 0x00
movl $.L.str.8, %edi
callq _ZSt20__throw_length_errorPKc
.LBB7_12:
.Ltmp4:
movq %rax, %rbx
cmpl $0, (%r14)
jne .LBB7_14
# %bb.13:
movl %r13d, (%r14)
.LBB7_14: # %_ZZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_EN11_Save_errnoD2Ev.exit.i.i
movq -208(%rbp), %rdi
cmpq %r12, %rdi
je .LBB7_16
# %bb.15: # %.critedge.i.i87
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB7_16: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit89
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table7:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp2-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp2 # Call between .Ltmp2 and .Ltmp1
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Lfunc_end7-.Ltmp1 # Call between .Ltmp1 and .Lfunc_end7
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8tsp_cudaPiS_Pxi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $block_optimal_values, %esi
movl $block_optimal_values.managed, %edx
movl $.L__unnamed_2, %ecx
movl $200, %r8d
movq %rbx, %rdi
movl $16, %r9d
callq __hipRegisterManagedVar
movl $block_optimal_permutation, %esi
movl $block_optimal_permutation.managed, %edx
movl $.L__unnamed_3, %ecx
movl $200, %r8d
movq %rbx, %rdi
movl $16, %r9d
callq __hipRegisterManagedVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type factorial,@object # @factorial
.bss
.globl factorial
.p2align 4, 0x0
factorial:
.zero 136
.size factorial, 136
.type block_optimal_values.managed,@object # @block_optimal_values.managed
.local block_optimal_values.managed
.comm block_optimal_values.managed,200,16
.type block_optimal_permutation.managed,@object # @block_optimal_permutation.managed
.local block_optimal_permutation.managed
.comm block_optimal_permutation.managed,200,16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type _Z8tsp_cudaPiS_Pxi,@object # @_Z8tsp_cudaPiS_Pxi
.section .rodata,"a",@progbits
.globl _Z8tsp_cudaPiS_Pxi
.p2align 3, 0x0
_Z8tsp_cudaPiS_Pxi:
.quad _Z23__device_stub__tsp_cudaPiS_Pxi
.size _Z8tsp_cudaPiS_Pxi, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "%f\n"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Minimum Cost Path: "
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d "
.size .L.str.4, 4
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Path cost: %d \n"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "stoi"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "basic_string: construction from null is not valid"
.size .L.str.7, 50
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "basic_string::_M_create"
.size .L.str.8, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8tsp_cudaPiS_Pxi"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "block_optimal_values"
.size .L__unnamed_2, 21
.type block_optimal_values,@object # @block_optimal_values
.local block_optimal_values
.comm block_optimal_values,8,8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "block_optimal_permutation"
.size .L__unnamed_3, 26
.type block_optimal_permutation,@object # @block_optimal_permutation
.local block_optimal_permutation
.comm block_optimal_permutation,8,8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__tsp_cudaPiS_Pxi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym factorial
.addrsig_sym block_optimal_values.managed
.addrsig_sym block_optimal_permutation.managed
.addrsig_sym _ZSt4cout
.addrsig_sym _Z8tsp_cudaPiS_Pxi
.addrsig_sym block_optimal_values
.addrsig_sym block_optimal_permutation
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand.h>
#include <sys/time.h>
#include <math.h>
__global__ void kernel(int* count_d, float* randomnums)
{
int i;
double x,y,z;
int tid = blockDim.x * blockIdx.x + threadIdx.x;
i = tid;
int xidx = 0, yidx = 0;
xidx = (i+i);
yidx = (xidx+1);
x = randomnums[xidx];
y = randomnums[yidx];
z = 1/sqrt(2*M_PI) * exp(-0.5*pow(x,2));
if (y<=z)
count_d[tid] = 1;
else
count_d[tid] = 0;
}
void CUDAErrorCheck()
{
cudaError_t error = cudaGetLastError();
if (error != cudaSuccess)
{
printf("CUDA error : %s (%d)\n", cudaGetErrorString(error), error);
exit(0);
}
}
int main(int argc,char* argv[])
{
int niter = atoi(argv[1]);
int repetitions = 3;
int j = 0;
for (j=0; j<repetitions; j++)
{
float *randomnums;
double phi;
cudaMalloc((void**)&randomnums, (2*niter)*sizeof(float));
// Use CuRand to generate an array of random numbers on the device
int status;
curandGenerator_t gen;
status = curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_MRG32K3A);
status |= curandSetPseudoRandomGeneratorSeed(gen, 2138+j);
// status |= curandSetPseudoRandomGeneratorSeed(gen, 4294967296ULL^time(NULL));
status |= curandGenerateUniform(gen, randomnums, (2*niter));
status |= curandDestroyGenerator(gen);
if (status != CURAND_STATUS_SUCCESS)
{
printf("CuRand Failure\n");
exit(EXIT_FAILURE);
}
int threads = 1000;
int blocks = 100;
int* count_d;
int *count = (int*)malloc(blocks*threads*sizeof(int));
unsigned int reducedcount = 0;
cudaMalloc((void**)&count_d, (blocks*threads)*sizeof(int));
CUDAErrorCheck();
struct timeval begin, end;
gettimeofday(&begin, NULL);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
//one point per thread
kernel <<<blocks, threads>>> (count_d, randomnums);
cudaDeviceSynchronize();
CUDAErrorCheck();
cudaMemcpy(count, count_d, blocks*threads*sizeof(int), cudaMemcpyDeviceToHost);
int i = 0;
//reduce array into int
for(i = 0; i<niter; i++)
reducedcount += count[i];
cudaEventRecord(stop, 0);
float elapsedTime = 0;
cudaEventElapsedTime(&elapsedTime, start, stop);
gettimeofday(&end, NULL);
double elapsed = (end.tv_sec - begin.tv_sec) + ((end.tv_usec - begin.tv_usec)/1000000.0);
cudaFree(randomnums);
cudaFree(count_d);
free(count);
cudaEventDestroy(start);
cudaEventDestroy(stop);
phi = ((double)reducedcount/niter)*1.0 + 0.5;
printf("CUDA - area to left of 1 on standard normal: %f\n", phi);
//printf("runtime: %f\n", elapsedTime);
printf("runtime: %f\n", elapsed);
//printf("runtime: %f\n", seconds);
}
return 0;
} | code for sm_80
Function : _Z6kernelPiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.SHL.U32 R6, R2, 0x2, RZ ; /* 0x0000000202067824 */
/* 0x000fc800078e00ff */
/*0070*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fca00078e0207 */
/*0080*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R26, [R6.64+0x4] ; /* 0x00000404061a7981 */
/* 0x000162000c1e1900 */
/*00a0*/ BSSY B0, 0xf0 ; /* 0x0000004000007945 */
/* 0x000fe20003800000 */
/*00b0*/ MOV R0, 0xe0 ; /* 0x000000e000007802 */
/* 0x000fe20000000f00 */
/*00c0*/ F2F.F64.F32 R4, R3 ; /* 0x0000000300047310 */
/* 0x00406c0000201800 */
/*00d0*/ CALL.REL.NOINC 0x550 ; /* 0x0000047000007944 */
/* 0x023fea0003c00000 */
/*00e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00f0*/ DADD R6, R4, 2 ; /* 0x4000000004067429 */
/* 0x000e220000000000 */
/*0100*/ FSETP.NEU.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fe20003f0d000 */
/*0110*/ BSSY B0, 0x230 ; /* 0x0000011000007945 */
/* 0x000ff00003800000 */
/*0120*/ LOP3.LUT R6, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007067812 */
/* 0x001fe200078ec0ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff077224 */
/* 0x000fc600078e000f */
/*0140*/ ISETP.NE.AND P1, PT, R6, 0x7ff00000, PT ; /* 0x7ff000000600780c */
/* 0x000fe20003f25270 */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000e */
/*0160*/ @!P0 CS2R R6, SRZ ; /* 0x0000000000068805 */
/* 0x000fd6000001ff00 */
/*0170*/ @P1 BRA 0x220 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0180*/ DSETP.GTU.AND P0, PT, |R4|, +INF , PT ; /* 0x7ff000000400742a */
/* 0x000e1c0003f0c200 */
/*0190*/ @P0 BRA 0x210 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*01a0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*01b0*/ LOP3.LUT R4, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05047812 */
/* 0x000fc800078ec0ff */
/*01c0*/ ISETP.NE.OR P0, PT, R4, 0x7ff00000, P0 ; /* 0x7ff000000400780c */
/* 0x000fda0000705670 */
/*01d0*/ @P0 BRA 0x220 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe400078e00ff */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff077424 */
/* 0x000fe200078e00ff */
/*0200*/ BRA 0x220 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0210*/ DADD R6, R4, 2 ; /* 0x4000000004067429 */
/* 0x00004c0000000000 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ DMUL R6, R6, -0.5 ; /* 0xbfe0000006067828 */
/* 0x002e620000000000 */
/*0240*/ FSETP.NEU.AND P0, PT, R3, 1, PT ; /* 0x3f8000000300780b */
/* 0x000fe20003f0d000 */
/*0250*/ IMAD.MOV.U32 R8, RZ, RZ, 0x652b82fe ; /* 0x652b82feff087424 */
/* 0x000fe200078e00ff */
/*0260*/ F2F.F64.F32 R26, R26 ; /* 0x0000001a001a7310 */
/* 0x000ea20000201800 */
/*0270*/ IMAD.MOV.U32 R9, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff097424 */
/* 0x000fe200078e00ff */
/*0280*/ BSSY B0, 0x4e0 ; /* 0x0000025000007945 */
/* 0x000fe20003800000 */
/*0290*/ IMAD.MOV.U32 R12, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff0c7424 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff0d7424 */
/* 0x000fc400078e00ff */
/*02b0*/ FSEL R4, R6, RZ, P0 ; /* 0x000000ff06047208 */
/* 0x003fe40000000000 */
/*02c0*/ FSEL R5, R7, -1.75, P0 ; /* 0xbfe0000007057808 */
/* 0x000fc80000000000 */
/*02d0*/ FSETP.GEU.AND P0, PT, |R5|, 4.1917929649353027344, PT ; /* 0x4086232b0500780b */
/* 0x000fe40003f0e200 */
/*02e0*/ DFMA R6, R4, R8, 6.75539944105574400000e+15 ; /* 0x433800000406742b */
/* 0x000e0c0000000008 */
/*02f0*/ DADD R8, R6, -6.75539944105574400000e+15 ; /* 0xc338000006087429 */
/* 0x001e0c0000000000 */
/*0300*/ DFMA R10, R8, c[0x2][0x0], R4 ; /* 0x00800000080a7a2b */
/* 0x001e0c0000000004 */
/*0310*/ DFMA R8, R8, c[0x2][0x8], R10 ; /* 0x0080020008087a2b */
/* 0x001e0c000000000a */
/*0320*/ DFMA R10, R8, R12, c[0x2][0x10] ; /* 0x00800400080a762b */
/* 0x001e0c000000000c */
/*0330*/ DFMA R10, R8, R10, c[0x2][0x18] ; /* 0x00800600080a762b */
/* 0x001e0c000000000a */
/*0340*/ DFMA R10, R8, R10, c[0x2][0x20] ; /* 0x00800800080a762b */
/* 0x001e0c000000000a */
/*0350*/ DFMA R10, R8, R10, c[0x2][0x28] ; /* 0x00800a00080a762b */
/* 0x001e0c000000000a */
/*0360*/ DFMA R10, R8, R10, c[0x2][0x30] ; /* 0x00800c00080a762b */
/* 0x001e0c000000000a */
/*0370*/ DFMA R10, R8, R10, c[0x2][0x38] ; /* 0x00800e00080a762b */
/* 0x001e0c000000000a */
/*0380*/ DFMA R10, R8, R10, c[0x2][0x40] ; /* 0x00801000080a762b */
/* 0x001e0c000000000a */
/*0390*/ DFMA R10, R8, R10, c[0x2][0x48] ; /* 0x00801200080a762b */
/* 0x001e0c000000000a */
/*03a0*/ DFMA R10, R8, R10, c[0x2][0x50] ; /* 0x00801400080a762b */
/* 0x001e0c000000000a */
/*03b0*/ DFMA R10, R8, R10, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c000000000a */
/*03c0*/ DFMA R10, R8, R10, 1 ; /* 0x3ff00000080a742b */
/* 0x001e14000000000a */
/*03d0*/ IMAD R9, R6, 0x100000, R11 ; /* 0x0010000006097824 */
/* 0x001fe400078e020b */
/*03e0*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000a */
/*03f0*/ @!P0 BRA 0x4d0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0400*/ FSETP.GEU.AND P1, PT, |R5|, 4.2275390625, PT ; /* 0x408748000500780b */
/* 0x004fe20003f2e200 */
/*0410*/ DADD R8, R4, +INF ; /* 0x7ff0000004087429 */
/* 0x000fc80000000000 */
/*0420*/ DSETP.GEU.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x000e0c0003f0e000 */
/*0430*/ FSEL R8, R8, RZ, P0 ; /* 0x000000ff08087208 */
/* 0x001fe40000000000 */
/*0440*/ @!P1 LEA.HI R0, R6, R6, RZ, 0x1 ; /* 0x0000000606009211 */
/* 0x000fe200078f08ff */
/*0450*/ @!P1 IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff049224 */
/* 0x000fe200078e000a */
/*0460*/ FSEL R9, R9, RZ, P0 ; /* 0x000000ff09097208 */
/* 0x000fe40000000000 */
/*0470*/ @!P1 SHF.R.S32.HI R5, RZ, 0x1, R0 ; /* 0x00000001ff059819 */
/* 0x000fca0000011400 */
/*0480*/ @!P1 IMAD.IADD R6, R6, 0x1, -R5 ; /* 0x0000000106069824 */
/* 0x000fe400078e0a05 */
/*0490*/ @!P1 IMAD R5, R5, 0x100000, R11 ; /* 0x0010000005059824 */
/* 0x000fc600078e020b */
/*04a0*/ @!P1 LEA R7, R6, 0x3ff00000, 0x14 ; /* 0x3ff0000006079811 */
/* 0x000fe200078ea0ff */
/*04b0*/ @!P1 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff069224 */
/* 0x000fcc00078e00ff */
/*04c0*/ @!P1 DMUL R8, R4, R6 ; /* 0x0000000604089228 */
/* 0x00004c0000000000 */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*04e0*/ DMUL R8, R8, c[0x2][0x58] ; /* 0x0080160008087a28 */
/* 0x002e620000000000 */
/*04f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0500*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*0510*/ DSETP.GE.AND P0, PT, R8, R26, PT ; /* 0x0000001a0800722a */
/* 0x002e4c0003f06000 */
/*0520*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x003fca0004000000 */
/*0530*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0540*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0550*/ DADD R8, -RZ, |R4| ; /* 0x00000000ff087229 */
/* 0x000e220000000504 */
/*0560*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*0570*/ IMAD.MOV.U32 R12, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff0c7424 */
/* 0x000fe400078e00ff */
/*0580*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff0d7424 */
/* 0x000fca00078e00ff */
/*0590*/ SHF.R.U32.HI R27, RZ, 0x14, R9 ; /* 0x00000014ff1b7819 */
/* 0x001fc80000011609 */
/*05a0*/ ISETP.NE.AND P0, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fda0003f05270 */
/*05b0*/ @!P0 DMUL R6, R8, 1.80143985094819840000e+16 ; /* 0x4350000008068828 */
/* 0x000e140000000000 */
/*05c0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff098224 */
/* 0x001fe200078e0007 */
/*05d0*/ @!P0 MOV R8, R6 ; /* 0x0000000600088202 */
/* 0x000fe40000000f00 */
/*05e0*/ @!P0 LEA.HI R27, R7, 0xffffffca, RZ, 0xc ; /* 0xffffffca071b8811 */
/* 0x000fe200078f60ff */
/*05f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x43300000 ; /* 0x43300000ff077424 */
/* 0x000fe200078e00ff */
/*0600*/ LOP3.LUT R9, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09097812 */
/* 0x000fe200078ec0ff */
/*0610*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0008 */
/*0620*/ IADD3 R6, R27, -0x3ff, RZ ; /* 0xfffffc011b067810 */
/* 0x000fe40007ffe0ff */
/*0630*/ LOP3.LUT R19, R9, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000009137812 */
/* 0x000fc800078efcff */
/*0640*/ ISETP.GE.U32.AND P1, PT, R19, 0x3ff6a09f, PT ; /* 0x3ff6a09f1300780c */
/* 0x000fda0003f26070 */
/*0650*/ @P1 IADD3 R9, R19, -0x100000, RZ ; /* 0xfff0000013091810 */
/* 0x000fe40007ffe0ff */
/*0660*/ @P1 IADD3 R6, R27, -0x3fe, RZ ; /* 0xfffffc021b061810 */
/* 0x000fc60007ffe0ff */
/*0670*/ @P1 IMAD.MOV.U32 R19, RZ, RZ, R9 ; /* 0x000000ffff131224 */
/* 0x000fe200078e0009 */
/*0680*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000006067812 */
/* 0x000fca00078e3cff */
/*0690*/ DADD R10, R18, 1 ; /* 0x3ff00000120a7429 */
/* 0x000e080000000000 */
/*06a0*/ DADD R18, R18, -1 ; /* 0xbff0000012127429 */
/* 0x000fe40000000000 */
/*06b0*/ MUFU.RCP64H R17, R11 ; /* 0x0000000b00117308 */
/* 0x001e240000001800 */
/*06c0*/ DFMA R8, -R10, R16, 1 ; /* 0x3ff000000a08742b */
/* 0x001e0c0000000110 */
/*06d0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*06e0*/ DFMA R16, R16, R8, R16 ; /* 0x000000081010722b */
/* 0x001e0c0000000010 */
/*06f0*/ DMUL R8, R16, R18 ; /* 0x0000001210087228 */
/* 0x001e0c0000000000 */
/*0700*/ DFMA R8, R16, R18, R8 ; /* 0x000000121008722b */
/* 0x001e0c0000000008 */
/*0710*/ DMUL R20, R8, R8 ; /* 0x0000000808147228 */
/* 0x001e080000000000 */
/*0720*/ DADD R10, R18, -R8 ; /* 0x00000000120a7229 */
/* 0x000fc80000000808 */
/*0730*/ DFMA R12, R20, R12, c[0x2][0x60] ; /* 0x00801800140c762b */
/* 0x001e0c000000000c */
/*0740*/ DFMA R12, R20, R12, c[0x2][0x68] ; /* 0x00801a00140c762b */
/* 0x001e0c000000000c */
/*0750*/ DFMA R12, R20, R12, c[0x2][0x70] ; /* 0x00801c00140c762b */
/* 0x001e0c000000000c */
/*0760*/ DFMA R12, R20, R12, c[0x2][0x78] ; /* 0x00801e00140c762b */
/* 0x001e0c000000000c */
/*0770*/ DFMA R12, R20, R12, c[0x2][0x80] ; /* 0x00802000140c762b */
/* 0x001e0c000000000c */
/*0780*/ DFMA R22, R20, R12, c[0x2][0x88] ; /* 0x008022001416762b */
/* 0x001e08000000000c */
/*0790*/ DADD R12, R10, R10 ; /* 0x000000000a0c7229 */
/* 0x000e48000000000a */
/*07a0*/ DFMA R10, R20, R22, c[0x2][0x90] ; /* 0x00802400140a762b */
/* 0x001e080000000016 */
/*07b0*/ DFMA R18, R18, -R8, R12 ; /* 0x800000081212722b */
/* 0x002fc8000000000c */
/*07c0*/ DADD R14, -R10, c[0x2][0x90] ; /* 0x008024000a0e7629 */
/* 0x001e080000000100 */
/*07d0*/ DMUL R12, R8, R8 ; /* 0x00000008080c7228 */
/* 0x000e480000000000 */
/*07e0*/ DFMA R22, R20, R22, R14 ; /* 0x000000161416722b */
/* 0x001e08000000000e */
/*07f0*/ DMUL R16, R16, R18 ; /* 0x0000001210107228 */
/* 0x000e880000000000 */
/*0800*/ DMUL R14, R8, R12 ; /* 0x0000000c080e7228 */
/* 0x002e480000000000 */
/*0810*/ DADD R22, RZ, R22 ; /* 0x00000000ff167229 */
/* 0x001e240000000016 */
/*0820*/ IADD3 R25, R17, 0x100000, RZ ; /* 0x0010000011197810 */
/* 0x004fe20007ffe0ff */
/*0830*/ IMAD.MOV.U32 R24, RZ, RZ, R16 ; /* 0x000000ffff187224 */
/* 0x000fe200078e0010 */
/*0840*/ DFMA R18, R8, R8, -R12 ; /* 0x000000080812722b */
/* 0x000fc8000000080c */
/*0850*/ DFMA R20, R8, R12, -R14 ; /* 0x0000000c0814722b */
/* 0x002e48000000080e */
/*0860*/ DADD R22, R22, c[0x2][0x98] ; /* 0x0080260016167629 */
/* 0x001e080000000000 */
/*0870*/ DFMA R20, R16, R12, R20 ; /* 0x0000000c1014722b */
/* 0x002fc80000000014 */
/*0880*/ DFMA R18, R8, R24, R18 ; /* 0x000000180812722b */
/* 0x000e480000000012 */
/*0890*/ DADD R12, R10, R22 ; /* 0x000000000a0c7229 */
/* 0x001e080000000016 */
/*08a0*/ DFMA R18, R8, R18, R20 ; /* 0x000000120812722b */
/* 0x002fc80000000014 */
/*08b0*/ DADD R20, R10, -R12 ; /* 0x000000000a147229 */
/* 0x001e08000000080c */
/*08c0*/ DMUL R10, R12, R14 ; /* 0x0000000e0c0a7228 */
/* 0x000e480000000000 */
/*08d0*/ DADD R22, R22, R20 ; /* 0x0000000016167229 */
/* 0x001fc80000000014 */
/*08e0*/ DFMA R20, R12, R14, -R10 ; /* 0x0000000e0c14722b */
/* 0x002e0c000000080a */
/*08f0*/ DFMA R18, R12, R18, R20 ; /* 0x000000120c12722b */
/* 0x001e0c0000000014 */
/*0900*/ DFMA R22, R22, R14, R18 ; /* 0x0000000e1616722b */
/* 0x0010640000000012 */
/*0910*/ MOV R18, 0x69ce2bdf ; /* 0x69ce2bdf00127802 */
/* 0x001fe20000000f00 */
/*0920*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff137424 */
/* 0x000fc600078e00ff */
/*0930*/ DADD R14, R10, R22 ; /* 0x000000000a0e7229 */
/* 0x002e0c0000000016 */
/*0940*/ DADD R12, R8, R14 ; /* 0x00000000080c7229 */
/* 0x001e08000000000e */
/*0950*/ DADD R10, R10, -R14 ; /* 0x000000000a0a7229 */
/* 0x000e48000000080e */
/*0960*/ DADD R8, R8, -R12 ; /* 0x0000000008087229 */
/* 0x001e08000000080c */
/*0970*/ DADD R10, R22, R10 ; /* 0x00000000160a7229 */
/* 0x002fc8000000000a */
/*0980*/ DADD R8, R14, R8 ; /* 0x000000000e087229 */
/* 0x001e0c0000000008 */
/*0990*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x001e0c0000000008 */
/*09a0*/ DADD R16, R16, R8 ; /* 0x0000000010107229 */
/* 0x001e080000000008 */
/*09b0*/ DADD R8, R6, c[0x2][0xa0] ; /* 0x0080280006087629 */
/* 0x000fc80000000000 */
/*09c0*/ DADD R10, R12, R16 ; /* 0x000000000c0a7229 */
/* 0x001e0c0000000010 */
/*09d0*/ DFMA R6, R8, c[0x2][0xa8], R10 ; /* 0x00802a0008067a2b */
/* 0x001e08000000000a */
/*09e0*/ DADD R12, R12, -R10 ; /* 0x000000000c0c7229 */
/* 0x000e48000000080a */
/*09f0*/ DFMA R14, -R8, c[0x2][0xa8], R6 ; /* 0x00802a00080e7a2b */
/* 0x001e080000000106 */
/*0a00*/ DADD R12, R16, R12 ; /* 0x00000000100c7229 */
/* 0x002fc8000000000c */
/*0a10*/ DADD R14, -R10, R14 ; /* 0x000000000a0e7229 */
/* 0x001e0c000000010e */
/*0a20*/ DADD R12, R12, -R14 ; /* 0x000000000c0c7229 */
/* 0x001e0c000000080e */
/*0a30*/ DFMA R12, R8, c[0x2][0xb0], R12 ; /* 0x00802c00080c7a2b */
/* 0x001e0c000000000c */
/*0a40*/ DADD R8, R6, R12 ; /* 0x0000000006087229 */
/* 0x001e0c000000000c */
/*0a50*/ DADD R10, R6, -R8 ; /* 0x00000000060a7229 */
/* 0x001e080000000808 */
/*0a60*/ DMUL R6, R8, 2 ; /* 0x4000000008067828 */
/* 0x000e480000000000 */
/*0a70*/ DADD R10, R12, R10 ; /* 0x000000000c0a7229 */
/* 0x0011e4000000000a */
/*0a80*/ IMAD.MOV.U32 R12, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0c7424 */
/* 0x001fe400078e00ff */
/*0a90*/ DFMA R8, R8, 2, -R6 ; /* 0x400000000808782b */
/* 0x002e220000000806 */
/*0aa0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0d7424 */
/* 0x000fca00078e00ff */
/*0ab0*/ DFMA R8, R10, 2, R8 ; /* 0x400000000a08782b */
/* 0x001e0c0000000008 */
/*0ac0*/ DADD R10, R6, R8 ; /* 0x00000000060a7229 */
/* 0x001e0c0000000008 */
/*0ad0*/ DFMA R12, R10, R12, 6.75539944105574400000e+15 ; /* 0x433800000a0c742b */
/* 0x001e08000000000c */
/*0ae0*/ FSETP.GEU.AND P0, PT, |R11|, 4.1917929649353027344, PT ; /* 0x4086232b0b00780b */
/* 0x000fe40003f0e200 */
/*0af0*/ DADD R14, R12, -6.75539944105574400000e+15 ; /* 0xc33800000c0e7429 */
/* 0x001e0c0000000000 */
/*0b00*/ DFMA R16, R14, c[0x2][0x0], R10 ; /* 0x008000000e107a2b */
/* 0x001e0c000000000a */
/*0b10*/ DFMA R14, R14, c[0x2][0x8], R16 ; /* 0x008002000e0e7a2b */
/* 0x001e0c0000000010 */
/*0b20*/ DFMA R16, R14, R18, c[0x2][0x10] ; /* 0x008004000e10762b */
/* 0x001e0c0000000012 */
/*0b30*/ DFMA R16, R14, R16, c[0x2][0x18] ; /* 0x008006000e10762b */
/* 0x001e0c0000000010 */
/*0b40*/ DFMA R16, R14, R16, c[0x2][0x20] ; /* 0x008008000e10762b */
/* 0x001e0c0000000010 */
/*0b50*/ DFMA R16, R14, R16, c[0x2][0x28] ; /* 0x00800a000e10762b */
/* 0x001e0c0000000010 */
/*0b60*/ DFMA R16, R14, R16, c[0x2][0x30] ; /* 0x00800c000e10762b */
/* 0x001e0c0000000010 */
/*0b70*/ DFMA R16, R14, R16, c[0x2][0x38] ; /* 0x00800e000e10762b */
/* 0x001e0c0000000010 */
/*0b80*/ DFMA R16, R14, R16, c[0x2][0x40] ; /* 0x008010000e10762b */
/* 0x001e0c0000000010 */
/*0b90*/ DFMA R16, R14, R16, c[0x2][0x48] ; /* 0x008012000e10762b */
/* 0x001e0c0000000010 */
/*0ba0*/ DFMA R16, R14, R16, c[0x2][0x50] ; /* 0x008014000e10762b */
/* 0x001e0c0000000010 */
/*0bb0*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e0c0000000010 */
/*0bc0*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e140000000010 */
/*0bd0*/ IMAD R15, R12, 0x100000, R17 ; /* 0x001000000c0f7824 */
/* 0x001fe400078e0211 */
/*0be0*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0010 */
/*0bf0*/ @!P0 BRA 0xcc0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0c00*/ FSETP.GEU.AND P1, PT, |R11|, 4.2275390625, PT ; /* 0x408748000b00780b */
/* 0x000fe20003f2e200 */
/*0c10*/ DADD R14, R10, +INF ; /* 0x7ff000000a0e7429 */
/* 0x000fc80000000000 */
/*0c20*/ DSETP.GEU.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00722a */
/* 0x000e0c0003f0e000 */
/*0c30*/ FSEL R14, R14, RZ, P0 ; /* 0x000000ff0e0e7208 */
/* 0x001fe40000000000 */
/*0c40*/ @!P1 LEA.HI R13, R12, R12, RZ, 0x1 ; /* 0x0000000c0c0d9211 */
/* 0x000fe400078f08ff */
/*0c50*/ FSEL R15, R15, RZ, P0 ; /* 0x000000ff0f0f7208 */
/* 0x000fe40000000000 */
/*0c60*/ @!P1 SHF.R.S32.HI R13, RZ, 0x1, R13 ; /* 0x00000001ff0d9819 */
/* 0x000fca000001140d */
/*0c70*/ @!P1 IMAD.IADD R12, R12, 0x1, -R13 ; /* 0x000000010c0c9824 */
/* 0x000fe400078e0a0d */
/*0c80*/ @!P1 IMAD R17, R13, 0x100000, R17 ; /* 0x001000000d119824 */
/* 0x000fc600078e0211 */
/*0c90*/ @!P1 LEA R13, R12, 0x3ff00000, 0x14 ; /* 0x3ff000000c0d9811 */
/* 0x000fe200078ea0ff */
/*0ca0*/ @!P1 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c9224 */
/* 0x000fcc00078e00ff */
/*0cb0*/ @!P1 DMUL R14, R16, R12 ; /* 0x0000000c100e9228 */
/* 0x0000540000000000 */
/*0cc0*/ LOP3.LUT R12, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0f0c7812 */
/* 0x003fe200078ec0ff */
/*0cd0*/ DADD R6, R6, -R10 ; /* 0x0000000006067229 */
/* 0x000e06000000080a */
/*0ce0*/ ISETP.NE.AND P0, PT, R12, 0x7ff00000, PT ; /* 0x7ff000000c00780c */
/* 0x000fc60003f05270 */
/*0cf0*/ DADD R6, R8, R6 ; /* 0x0000000008067229 */
/* 0x001e220000000006 */
/*0d00*/ ISETP.EQ.AND P0, PT, R14, RZ, !P0 ; /* 0x000000ff0e00720c */
/* 0x000fda0004702270 */
/*0d10*/ @!P0 DFMA R14, R6, R14, R14 ; /* 0x0000000e060e822b */
/* 0x001064000000000e */
/*0d20*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0000 */
/*0d30*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0d40*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff2b006007950 */
/* 0x002fea0003c3ffff */
/*0d50*/ BRA 0xd50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand.h>
#include <sys/time.h>
#include <math.h>
__global__ void kernel(int* count_d, float* randomnums)
{
int i;
double x,y,z;
int tid = blockDim.x * blockIdx.x + threadIdx.x;
i = tid;
int xidx = 0, yidx = 0;
xidx = (i+i);
yidx = (xidx+1);
x = randomnums[xidx];
y = randomnums[yidx];
z = 1/sqrt(2*M_PI) * exp(-0.5*pow(x,2));
if (y<=z)
count_d[tid] = 1;
else
count_d[tid] = 0;
}
void CUDAErrorCheck()
{
cudaError_t error = cudaGetLastError();
if (error != cudaSuccess)
{
printf("CUDA error : %s (%d)\n", cudaGetErrorString(error), error);
exit(0);
}
}
int main(int argc,char* argv[])
{
int niter = atoi(argv[1]);
int repetitions = 3;
int j = 0;
for (j=0; j<repetitions; j++)
{
float *randomnums;
double phi;
cudaMalloc((void**)&randomnums, (2*niter)*sizeof(float));
// Use CuRand to generate an array of random numbers on the device
int status;
curandGenerator_t gen;
status = curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_MRG32K3A);
status |= curandSetPseudoRandomGeneratorSeed(gen, 2138+j);
// status |= curandSetPseudoRandomGeneratorSeed(gen, 4294967296ULL^time(NULL));
status |= curandGenerateUniform(gen, randomnums, (2*niter));
status |= curandDestroyGenerator(gen);
if (status != CURAND_STATUS_SUCCESS)
{
printf("CuRand Failure\n");
exit(EXIT_FAILURE);
}
int threads = 1000;
int blocks = 100;
int* count_d;
int *count = (int*)malloc(blocks*threads*sizeof(int));
unsigned int reducedcount = 0;
cudaMalloc((void**)&count_d, (blocks*threads)*sizeof(int));
CUDAErrorCheck();
struct timeval begin, end;
gettimeofday(&begin, NULL);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
//one point per thread
kernel <<<blocks, threads>>> (count_d, randomnums);
cudaDeviceSynchronize();
CUDAErrorCheck();
cudaMemcpy(count, count_d, blocks*threads*sizeof(int), cudaMemcpyDeviceToHost);
int i = 0;
//reduce array into int
for(i = 0; i<niter; i++)
reducedcount += count[i];
cudaEventRecord(stop, 0);
float elapsedTime = 0;
cudaEventElapsedTime(&elapsedTime, start, stop);
gettimeofday(&end, NULL);
double elapsed = (end.tv_sec - begin.tv_sec) + ((end.tv_usec - begin.tv_usec)/1000000.0);
cudaFree(randomnums);
cudaFree(count_d);
free(count);
cudaEventDestroy(start);
cudaEventDestroy(stop);
phi = ((double)reducedcount/niter)*1.0 + 0.5;
printf("CUDA - area to left of 1 on standard normal: %f\n", phi);
//printf("runtime: %f\n", elapsedTime);
printf("runtime: %f\n", elapsed);
//printf("runtime: %f\n", seconds);
}
return 0;
} | .file "tmpxft_0012b45c_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error : %s (%d)\n"
.text
.globl _Z14CUDAErrorCheckv
.type _Z14CUDAErrorCheckv, @function
_Z14CUDAErrorCheckv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14CUDAErrorCheckv, .-_Z14CUDAErrorCheckv
.globl _Z27__device_stub__Z6kernelPiPfPiPf
.type _Z27__device_stub__Z6kernelPiPfPiPf, @function
_Z27__device_stub__Z6kernelPiPfPiPf:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z27__device_stub__Z6kernelPiPfPiPf, .-_Z27__device_stub__Z6kernelPiPfPiPf
.globl _Z6kernelPiPf
.type _Z6kernelPiPf, @function
_Z6kernelPiPf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPiPfPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6kernelPiPf, .-_Z6kernelPiPf
.section .rodata.str1.1
.LC1:
.string "CuRand Failure\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "CUDA - area to left of 1 on standard normal: %f\n"
.section .rodata.str1.1
.LC6:
.string "runtime: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r13d
leal (%rax,%rax), %r14d
movslq %r14d, %r14
leaq 0(,%r14,4), %rcx
movq %rcx, 8(%rsp)
leal -1(%rax), %eax
movl $2138, %r12d
leaq 4(,%rax,4), %r15
jmp .L22
.L28:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L17:
call cudaDeviceSynchronize@PLT
call _Z14CUDAErrorCheckv
movl $2, %ecx
movl $400000, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L18
movq %rbp, %rax
leaq (%r15,%rbp), %rdx
.L19:
addl (%rax), %ebx
addq $4, %rax
cmpq %rdx, %rax
jne .L19
.L18:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $0x00000000, 68(%rsp)
leaq 68(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 104(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
movq 96(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, (%rsp)
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movl %ebx, %ebx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
divsd %xmm1, %xmm0
addsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %r12
cmpq $2141, %r12
je .L27
.L22:
leaq 24(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $121, %esi
call curandCreateGenerator@PLT
movl %eax, %ebp
movq %r12, %rsi
movq 32(%rsp), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
orl %eax, %ebp
movq %r14, %rdx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call curandGenerateUniform@PLT
orl %ebp, %eax
movl %eax, %ebx
movq 32(%rsp), %rdi
call curandDestroyGenerator@PLT
orl %eax, %ebx
jne .L28
movl $400000, %edi
call malloc@PLT
movq %rax, %rbp
leaq 40(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
call _Z14CUDAErrorCheckv
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1000, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $100, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z27__device_stub__Z6kernelPiPfPiPf
jmp .L17
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z6kernelPiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.align 8
.LC4:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand.h>
#include <sys/time.h>
#include <math.h>
__global__ void kernel(int* count_d, float* randomnums)
{
int i;
double x,y,z;
int tid = blockDim.x * blockIdx.x + threadIdx.x;
i = tid;
int xidx = 0, yidx = 0;
xidx = (i+i);
yidx = (xidx+1);
x = randomnums[xidx];
y = randomnums[yidx];
z = 1/sqrt(2*M_PI) * exp(-0.5*pow(x,2));
if (y<=z)
count_d[tid] = 1;
else
count_d[tid] = 0;
}
void CUDAErrorCheck()
{
cudaError_t error = cudaGetLastError();
if (error != cudaSuccess)
{
printf("CUDA error : %s (%d)\n", cudaGetErrorString(error), error);
exit(0);
}
}
int main(int argc,char* argv[])
{
int niter = atoi(argv[1]);
int repetitions = 3;
int j = 0;
for (j=0; j<repetitions; j++)
{
float *randomnums;
double phi;
cudaMalloc((void**)&randomnums, (2*niter)*sizeof(float));
// Use CuRand to generate an array of random numbers on the device
int status;
curandGenerator_t gen;
status = curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_MRG32K3A);
status |= curandSetPseudoRandomGeneratorSeed(gen, 2138+j);
// status |= curandSetPseudoRandomGeneratorSeed(gen, 4294967296ULL^time(NULL));
status |= curandGenerateUniform(gen, randomnums, (2*niter));
status |= curandDestroyGenerator(gen);
if (status != CURAND_STATUS_SUCCESS)
{
printf("CuRand Failure\n");
exit(EXIT_FAILURE);
}
int threads = 1000;
int blocks = 100;
int* count_d;
int *count = (int*)malloc(blocks*threads*sizeof(int));
unsigned int reducedcount = 0;
cudaMalloc((void**)&count_d, (blocks*threads)*sizeof(int));
CUDAErrorCheck();
struct timeval begin, end;
gettimeofday(&begin, NULL);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
//one point per thread
kernel <<<blocks, threads>>> (count_d, randomnums);
cudaDeviceSynchronize();
CUDAErrorCheck();
cudaMemcpy(count, count_d, blocks*threads*sizeof(int), cudaMemcpyDeviceToHost);
int i = 0;
//reduce array into int
for(i = 0; i<niter; i++)
reducedcount += count[i];
cudaEventRecord(stop, 0);
float elapsedTime = 0;
cudaEventElapsedTime(&elapsedTime, start, stop);
gettimeofday(&end, NULL);
double elapsed = (end.tv_sec - begin.tv_sec) + ((end.tv_usec - begin.tv_usec)/1000000.0);
cudaFree(randomnums);
cudaFree(count_d);
free(count);
cudaEventDestroy(start);
cudaEventDestroy(stop);
phi = ((double)reducedcount/niter)*1.0 + 0.5;
printf("CUDA - area to left of 1 on standard normal: %f\n", phi);
//printf("runtime: %f\n", elapsedTime);
printf("runtime: %f\n", elapsed);
//printf("runtime: %f\n", seconds);
}
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <sys/time.h>
#include <math.h>
__global__ void kernel(int* count_d, float* randomnums)
{
int i;
double x,y,z;
int tid = blockDim.x * blockIdx.x + threadIdx.x;
i = tid;
int xidx = 0, yidx = 0;
xidx = (i+i);
yidx = (xidx+1);
x = randomnums[xidx];
y = randomnums[yidx];
z = 1/sqrt(2*M_PI) * exp(-0.5*pow(x,2));
if (y<=z)
count_d[tid] = 1;
else
count_d[tid] = 0;
}
void CUDAErrorCheck()
{
hipError_t error = hipGetLastError();
if (error != hipSuccess)
{
printf("CUDA error : %s (%d)\n", hipGetErrorString(error), error);
exit(0);
}
}
int main(int argc,char* argv[])
{
int niter = atoi(argv[1]);
int repetitions = 3;
int j = 0;
for (j=0; j<repetitions; j++)
{
float *randomnums;
double phi;
hipMalloc((void**)&randomnums, (2*niter)*sizeof(float));
// Use CuRand to generate an array of random numbers on the device
int status;
hiprandGenerator_t gen;
status = hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_MRG32K3A);
status |= hiprandSetPseudoRandomGeneratorSeed(gen, 2138+j);
// status |= curandSetPseudoRandomGeneratorSeed(gen, 4294967296ULL^time(NULL));
status |= hiprandGenerateUniform(gen, randomnums, (2*niter));
status |= hiprandDestroyGenerator(gen);
if (status != HIPRAND_STATUS_SUCCESS)
{
printf("CuRand Failure\n");
exit(EXIT_FAILURE);
}
int threads = 1000;
int blocks = 100;
int* count_d;
int *count = (int*)malloc(blocks*threads*sizeof(int));
unsigned int reducedcount = 0;
hipMalloc((void**)&count_d, (blocks*threads)*sizeof(int));
CUDAErrorCheck();
struct timeval begin, end;
gettimeofday(&begin, NULL);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
//one point per thread
kernel <<<blocks, threads>>> (count_d, randomnums);
hipDeviceSynchronize();
CUDAErrorCheck();
hipMemcpy(count, count_d, blocks*threads*sizeof(int), hipMemcpyDeviceToHost);
int i = 0;
//reduce array into int
for(i = 0; i<niter; i++)
reducedcount += count[i];
hipEventRecord(stop, 0);
float elapsedTime = 0;
hipEventElapsedTime(&elapsedTime, start, stop);
gettimeofday(&end, NULL);
double elapsed = (end.tv_sec - begin.tv_sec) + ((end.tv_usec - begin.tv_usec)/1000000.0);
hipFree(randomnums);
hipFree(count_d);
free(count);
hipEventDestroy(start);
hipEventDestroy(stop);
phi = ((double)reducedcount/niter)*1.0 + 0.5;
printf("CUDA - area to left of 1 on standard normal: %f\n", phi);
//printf("runtime: %f\n", elapsedTime);
printf("runtime: %f\n", elapsed);
//printf("runtime: %f\n", seconds);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <sys/time.h>
#include <math.h>
__global__ void kernel(int* count_d, float* randomnums)
{
int i;
double x,y,z;
int tid = blockDim.x * blockIdx.x + threadIdx.x;
i = tid;
int xidx = 0, yidx = 0;
xidx = (i+i);
yidx = (xidx+1);
x = randomnums[xidx];
y = randomnums[yidx];
z = 1/sqrt(2*M_PI) * exp(-0.5*pow(x,2));
if (y<=z)
count_d[tid] = 1;
else
count_d[tid] = 0;
}
void CUDAErrorCheck()
{
hipError_t error = hipGetLastError();
if (error != hipSuccess)
{
printf("CUDA error : %s (%d)\n", hipGetErrorString(error), error);
exit(0);
}
}
int main(int argc,char* argv[])
{
int niter = atoi(argv[1]);
int repetitions = 3;
int j = 0;
for (j=0; j<repetitions; j++)
{
float *randomnums;
double phi;
hipMalloc((void**)&randomnums, (2*niter)*sizeof(float));
// Use CuRand to generate an array of random numbers on the device
int status;
hiprandGenerator_t gen;
status = hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_MRG32K3A);
status |= hiprandSetPseudoRandomGeneratorSeed(gen, 2138+j);
// status |= curandSetPseudoRandomGeneratorSeed(gen, 4294967296ULL^time(NULL));
status |= hiprandGenerateUniform(gen, randomnums, (2*niter));
status |= hiprandDestroyGenerator(gen);
if (status != HIPRAND_STATUS_SUCCESS)
{
printf("CuRand Failure\n");
exit(EXIT_FAILURE);
}
int threads = 1000;
int blocks = 100;
int* count_d;
int *count = (int*)malloc(blocks*threads*sizeof(int));
unsigned int reducedcount = 0;
hipMalloc((void**)&count_d, (blocks*threads)*sizeof(int));
CUDAErrorCheck();
struct timeval begin, end;
gettimeofday(&begin, NULL);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
//one point per thread
kernel <<<blocks, threads>>> (count_d, randomnums);
hipDeviceSynchronize();
CUDAErrorCheck();
hipMemcpy(count, count_d, blocks*threads*sizeof(int), hipMemcpyDeviceToHost);
int i = 0;
//reduce array into int
for(i = 0; i<niter; i++)
reducedcount += count[i];
hipEventRecord(stop, 0);
float elapsedTime = 0;
hipEventElapsedTime(&elapsedTime, start, stop);
gettimeofday(&end, NULL);
double elapsed = (end.tv_sec - begin.tv_sec) + ((end.tv_usec - begin.tv_usec)/1000000.0);
hipFree(randomnums);
hipFree(count_d);
free(count);
hipEventDestroy(start);
hipEventDestroy(stop);
phi = ((double)reducedcount/niter)*1.0 + 0.5;
printf("CUDA - area to left of 1 on standard normal: %f\n", phi);
//printf("runtime: %f\n", elapsedTime);
printf("runtime: %f\n", elapsed);
//printf("runtime: %f\n", seconds);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiPf
.globl _Z6kernelPiPf
.p2align 8
.type _Z6kernelPiPf,@function
_Z6kernelPiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s1, 0x3fe55555
s_mov_b32 s0, 0x55555555
s_mov_b32 s3, 0x3fba6564
s_mov_b32 s9, 0x3ff71547
s_mov_b32 s8, 0x652b82fe
s_mov_b32 s11, 0x3e928af3
s_mov_b32 s10, 0xfca7ab0c
s_mov_b32 s13, 0x3e5ade15
s_mov_b32 s12, 0x6a5dcb37
s_mov_b32 s14, 0x623fde64
s_mov_b32 s17, 0x3efa0199
s_mov_b32 s16, 0x7c89e6b0
s_mov_b32 s19, 0x3f2a01a0
s_mov_b32 s18, 0x14761f6e
s_mov_b32 s21, 0x3f56c16c
s_mov_b32 s20, 0x1852b7b0
s_mov_b32 s23, 0x3f811111
s_mov_b32 s22, 0x11122322
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mov_b32 s25, 0x3fa55555
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, 0x968915a9
s_mov_b32 s15, 0x3ec71dee
s_mov_b32 s24, 0x555502a1
s_mov_b32 s27, 0x3fc55555
s_mov_b32 s26, 0x55555511
s_mov_b32 s29, 0x3fe00000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 1, v1
s_mov_b32 s28, 11
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_or_b32_e32 v2, 1, v2
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_mov_b32 s7, 0x3fbdee67
s_mov_b32 s6, 0x4222de17
global_load_b32 v24, v[2:3], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e64 v[2:3], |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f64_e32 v[4:5], v[2:3]
v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[4:5]
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v6
v_add_f64 v[6:7], v[4:5], 1.0
v_add_f64 v[12:13], v[4:5], -1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
v_add_f64 v[14:15], v[6:7], -1.0
v_add_f64 v[4:5], v[4:5], -v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
v_mul_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[6:7], v[10:11]
v_fma_f64 v[6:7], v[10:11], v[6:7], -v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[10:11], v[4:5], v[6:7]
v_add_f64 v[6:7], v[16:17], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[12:13], -v[6:7]
v_add_f64 v[16:17], v[6:7], -v[16:17]
v_add_f64 v[12:13], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[16:17], -v[4:5]
v_add_f64 v[6:7], v[12:13], -v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[4:5], v[14:15], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[8:9], v[4:5]
v_add_f64 v[6:7], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[6:7], -v[10:11]
v_mul_f64 v[10:11], v[6:7], v[6:7]
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], v[6:7], v[6:7], -v[10:11]
v_add_f64 v[12:13], v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[12:13], v[8:9]
v_add_f64 v[12:13], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], s[6:7], s[2:3]
s_mov_b32 s3, 0x3fbe25e4
s_mov_b32 s2, 0x3abe935a
v_add_f64 v[10:11], v[12:13], -v[10:11]
v_mul_f64 v[20:21], v[6:7], v[12:13]
s_mov_b32 s7, 0x3c7abc9e
s_mov_b32 s6, 0x3b39803f
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[2:3]
s_mov_b32 s3, 0x3fc110ef
s_mov_b32 s2, 0x47e6c9c2
v_add_f64 v[8:9], v[8:9], -v[10:11]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[2:3]
s_mov_b32 s3, 0x3fc3b13b
s_mov_b32 s2, 0xcfa74449
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[2:3]
s_mov_b32 s3, 0x3fc745d1
s_mov_b32 s2, 0x71bf3c30
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[2:3]
s_mov_b32 s3, 0x3fcc71c7
s_mov_b32 s2, 0x1c7792ce
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[2:3]
s_mov_b32 s3, 0x3fd24924
s_mov_b32 s2, 0x924920da
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[2:3]
s_mov_b32 s3, 0x3fd99999
s_mov_b32 s2, 0x9999999c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[2:3]
s_mov_b32 s3, 0x3fe62e42
s_mov_b32 s2, 0xfefa39ef
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[12:13], v[14:15]
v_fma_f64 v[10:11], v[12:13], v[14:15], -v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[8:9], v[14:15], v[10:11]
v_add_f64 v[14:15], v[16:17], v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[18:19], v[14:15], s[0:1]
v_add_f64 v[16:17], v[14:15], -v[16:17]
s_mov_b32 s1, 0xbfe55555
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_f64 v[22:23], v[18:19], s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], -v[16:17]
v_fma_f64 v[16:17], v[12:13], v[6:7], -v[20:21]
s_mov_b32 s1, 0x3c8543b0
s_mov_b32 s0, 0xd5df274d
v_add_f64 v[14:15], v[14:15], -v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], s[0:1]
v_fma_f64 v[12:13], v[12:13], v[4:5], v[16:17]
v_ldexp_f64 v[4:5], v[4:5], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], v[14:15]
v_fma_f64 v[8:9], v[8:9], v[6:7], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[12:13], v[18:19], v[10:11]
v_add_f64 v[14:15], v[20:21], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[16:17], v[18:19], -v[12:13]
v_mul_f64 v[18:19], v[14:15], v[12:13]
v_add_f64 v[20:21], v[14:15], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], v[16:17]
v_fma_f64 v[16:17], v[14:15], v[12:13], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[8:9], -v[20:21]
v_fma_f64 v[10:11], v[14:15], v[10:11], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[8:9], v[8:9], v[12:13], v[10:11]
v_frexp_exp_i32_f64_e32 v10, v[2:3]
v_ldexp_f64 v[2:3], v[6:7], 1
v_add_f64 v[6:7], v[18:19], v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
v_cvt_f64_i32_e32 v[10:11], v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[2:3], v[6:7]
v_add_f64 v[14:15], v[6:7], -v[18:19]
v_mul_f64 v[16:17], v[10:11], s[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[2:3], v[12:13], -v[2:3]
v_add_f64 v[8:9], v[8:9], -v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[10:11], s[2:3], -v[16:17]
s_mov_b32 s3, 0xbfe62e42
v_add_f64 v[2:3], v[6:7], -v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], v[8:9]
v_fma_f64 v[6:7], v[10:11], s[6:7], v[14:15]
s_mov_b32 s7, 0xbc7abc9e
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[4:5], v[2:3]
v_add_f64 v[4:5], v[16:17], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[12:13], v[2:3]
v_add_f64 v[16:17], v[4:5], -v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[4:5], v[8:9]
v_add_f64 v[12:13], v[8:9], -v[12:13]
v_add_f64 v[6:7], v[6:7], -v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[10:11], -v[4:5]
v_add_f64 v[2:3], v[2:3], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[18:19], v[10:11], -v[14:15]
v_add_f64 v[8:9], v[8:9], -v[14:15]
v_add_f64 v[12:13], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[18:19]
v_add_f64 v[4:5], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[12:13], -v[6:7]
v_add_f64 v[4:5], v[12:13], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[12:13], -v[8:9]
v_add_f64 v[2:3], v[2:3], -v[8:9]
v_add_f64 v[14:15], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], -v[12:13]
v_add_f64 v[8:9], v[14:15], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], v[6:7]
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[4:5]
v_add_f64 v[4:5], v[14:15], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[4:5], -v[14:15]
v_add_f64 v[8:9], v[4:5], v[4:5]
v_add_f64 v[2:3], v[2:3], -v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], v[4:5], 2.0, -v[8:9]
v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x204
v_fma_f64 v[2:3], v[2:3], 2.0, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[8:9], v[2:3]
v_dual_cndmask_b32 v7, v5, v9 :: v_dual_cndmask_b32 v6, v4, v8
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_delay_alu instid0(VALU_DEP_2)
v_mul_f64 v[10:11], v[6:7], s[8:9]
v_cmp_nlt_f64_e64 s0, 0x40900000, v[6:7]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[6:7]|
v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[6:7]
v_add_f64 v[2:3], v[2:3], -v[4:5]
v_rndne_f64_e32 v[10:11], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_fma_f64 v[12:13], v[10:11], s[2:3], v[6:7]
v_cvt_i32_f64_e32 v16, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[10:11], s[6:7], v[12:13]
v_fma_f64 v[14:15], v[12:13], s[12:13], s[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[14:15]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[18:19]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[22:23]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[24:25]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[26:27]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], 1.0
v_fma_f64 v[10:11], v[12:13], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[8:9], v[10:11], v16
v_cndmask_b32_e64 v4, 0x7ff00000, v9, s0
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v5, 0, v4, s1
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
s_and_b32 vcc_lo, s1, s0
v_cmp_neq_f32_e64 s0, 0, v0
v_cndmask_b32_e32 v4, 0, v8, vcc_lo
s_mov_b32 s1, 0x3fd98845
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[4:5], v[2:3], v[4:5]
v_cmp_class_f64_e64 vcc_lo, v[4:5], 0x204
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v2, v2, v4
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v0|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], |v[2:3]|, -0.5
v_cndmask_b32_e32 v3, 0xfff00000, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
s_and_b32 vcc_lo, s0, vcc_lo
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, 0x80000000, v3, s0
s_mov_b32 s0, 0x33d43651
v_mul_f64 v[4:5], v[2:3], s[8:9]
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[4:5], v[4:5]
v_fma_f64 v[6:7], v[4:5], s[2:3], v[2:3]
v_cvt_i32_f64_e32 v0, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[4:5], s[6:7], v[6:7]
v_fma_f64 v[8:9], v[6:7], s[12:13], s[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[14:15]
v_fma_f64 v[8:9], v[6:7], v[8:9], s[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[18:19]
v_fma_f64 v[8:9], v[6:7], v[8:9], s[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[22:23]
v_fma_f64 v[8:9], v[6:7], v[8:9], s[24:25]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[26:27]
v_fma_f64 v[8:9], v[6:7], v[8:9], s[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
v_fma_f64 v[4:5], v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v0
v_mul_f64 v[4:5], v[4:5], s[0:1]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_cndmask_b32_e32 v7, 0x7ff00000, v5, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v24
s_and_b32 vcc_lo, s0, vcc_lo
v_cndmask_b32_e32 v2, 0, v4, vcc_lo
v_cndmask_b32_e64 v3, 0, v7, s0
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_ge_f64_e32 vcc_lo, v[2:3], v[5:6]
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 30
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiPf, .Lfunc_end0-_Z6kernelPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiPf
.private_segment_fixed_size: 0
.sgpr_count: 32
.sgpr_spill_count: 0
.symbol: _Z6kernelPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <sys/time.h>
#include <math.h>
__global__ void kernel(int* count_d, float* randomnums)
{
int i;
double x,y,z;
int tid = blockDim.x * blockIdx.x + threadIdx.x;
i = tid;
int xidx = 0, yidx = 0;
xidx = (i+i);
yidx = (xidx+1);
x = randomnums[xidx];
y = randomnums[yidx];
z = 1/sqrt(2*M_PI) * exp(-0.5*pow(x,2));
if (y<=z)
count_d[tid] = 1;
else
count_d[tid] = 0;
}
void CUDAErrorCheck()
{
hipError_t error = hipGetLastError();
if (error != hipSuccess)
{
printf("CUDA error : %s (%d)\n", hipGetErrorString(error), error);
exit(0);
}
}
int main(int argc,char* argv[])
{
int niter = atoi(argv[1]);
int repetitions = 3;
int j = 0;
for (j=0; j<repetitions; j++)
{
float *randomnums;
double phi;
hipMalloc((void**)&randomnums, (2*niter)*sizeof(float));
// Use CuRand to generate an array of random numbers on the device
int status;
hiprandGenerator_t gen;
status = hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_MRG32K3A);
status |= hiprandSetPseudoRandomGeneratorSeed(gen, 2138+j);
// status |= curandSetPseudoRandomGeneratorSeed(gen, 4294967296ULL^time(NULL));
status |= hiprandGenerateUniform(gen, randomnums, (2*niter));
status |= hiprandDestroyGenerator(gen);
if (status != HIPRAND_STATUS_SUCCESS)
{
printf("CuRand Failure\n");
exit(EXIT_FAILURE);
}
int threads = 1000;
int blocks = 100;
int* count_d;
int *count = (int*)malloc(blocks*threads*sizeof(int));
unsigned int reducedcount = 0;
hipMalloc((void**)&count_d, (blocks*threads)*sizeof(int));
CUDAErrorCheck();
struct timeval begin, end;
gettimeofday(&begin, NULL);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
//one point per thread
kernel <<<blocks, threads>>> (count_d, randomnums);
hipDeviceSynchronize();
CUDAErrorCheck();
hipMemcpy(count, count_d, blocks*threads*sizeof(int), hipMemcpyDeviceToHost);
int i = 0;
//reduce array into int
for(i = 0; i<niter; i++)
reducedcount += count[i];
hipEventRecord(stop, 0);
float elapsedTime = 0;
hipEventElapsedTime(&elapsedTime, start, stop);
gettimeofday(&end, NULL);
double elapsed = (end.tv_sec - begin.tv_sec) + ((end.tv_usec - begin.tv_usec)/1000000.0);
hipFree(randomnums);
hipFree(count_d);
free(count);
hipEventDestroy(start);
hipEventDestroy(stop);
phi = ((double)reducedcount/niter)*1.0 + 0.5;
printf("CUDA - area to left of 1 on standard normal: %f\n", phi);
//printf("runtime: %f\n", elapsedTime);
printf("runtime: %f\n", elapsed);
//printf("runtime: %f\n", seconds);
}
return 0;
} | .text
.file "cuda.hip"
.globl _Z21__device_stub__kernelPiPf # -- Begin function _Z21__device_stub__kernelPiPf
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiPf,@function
_Z21__device_stub__kernelPiPf: # @_Z21__device_stub__kernelPiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiPf, .Lfunc_end0-_Z21__device_stub__kernelPiPf
.cfi_endproc
# -- End function
.globl _Z14CUDAErrorCheckv # -- Begin function _Z14CUDAErrorCheckv
.p2align 4, 0x90
.type _Z14CUDAErrorCheckv,@function
_Z14CUDAErrorCheckv: # @_Z14CUDAErrorCheckv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
callq hipGetLastError
testl %eax, %eax
jne .LBB1_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size _Z14CUDAErrorCheckv, .Lfunc_end1-_Z14CUDAErrorCheckv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI2_1:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967396, %rbx # imm = 0x100000064
movq 8(%rsi), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
addl %eax, %eax
cltq
movq %rax, 104(%rsp) # 8-byte Spill
leaq (,%rax,4), %rax
movq %rax, 96(%rsp) # 8-byte Spill
cvtsi2sd %r14d, %xmm0
movsd %xmm0, 88(%rsp) # 8-byte Spill
movl %r14d, %r15d
leaq 900(%rbx), %r13
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_10: # in Loop: Header=BB2_1 Depth=1
xorl %ebx, %ebx
.LBB2_13: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $0, 48(%rsp)
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 64(%rsp), %rax
movq 72(%rsp), %rcx
subq 168(%rsp), %rax
cvtsi2sd %rax, %xmm0
subq 176(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 112(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbp, %rdi
callq free
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movl %ebx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd 88(%rsp), %xmm0 # 8-byte Folded Reload
addsd .LCPI2_1(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl $.L.str.3, %edi
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
incq %r12
cmpq $3, %r12
je .LBB2_14
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_12 Depth 2
leaq 40(%rsp), %rdi
movq 96(%rsp), %rsi # 8-byte Reload
callq hipMalloc
leaq 32(%rsp), %rdi
movl $402, %esi # imm = 0x192
callq hiprandCreateGenerator
movl %eax, %ebx
movq 32(%rsp), %rdi
leaq 2138(%r12), %rsi
callq hiprandSetPseudoRandomGeneratorSeed
movl %eax, %ebp
orl %ebx, %ebp
movq 32(%rsp), %rdi
movq 40(%rsp), %rsi
movq 104(%rsp), %rdx # 8-byte Reload
callq hiprandGenerateUniform
movl %eax, %ebx
orl %ebp, %ebx
movq 32(%rsp), %rdi
callq hiprandDestroyGenerator
orl %ebx, %eax
jne .LBB2_15
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbp
movl $400000, %esi # imm = 0x61A80
leaq 24(%rsp), %rdi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_3
# %bb.5: # %_Z14CUDAErrorCheckv.exit
# in Loop: Header=BB2_1 Depth=1
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967396, %rdi # imm = 0x100000064
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6: # in Loop: Header=BB2_1 Depth=1
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
leaq 160(%rsp), %rax
movq %rax, 64(%rsp)
leaq 152(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
movl $_Z6kernelPiPf, %edi
leaq 64(%rsp), %r9
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7: # in Loop: Header=BB2_1 Depth=1
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB2_8
# %bb.9: # %_Z14CUDAErrorCheckv.exit37
# in Loop: Header=BB2_1 Depth=1
movq 24(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
testl %r14d, %r14d
jle .LBB2_10
# %bb.11: # %.lr.ph.preheader
# in Loop: Header=BB2_1 Depth=1
xorl %eax, %eax
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_12: # %.lr.ph
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
addl (%rbp,%rax,4), %ebx
incq %rax
cmpq %rax, %r15
jne .LBB2_12
jmp .LBB2_13
.LBB2_14:
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 240
movl %eax, %edi
movl %eax, %ebx
jmp .LBB2_4
.LBB2_3:
movl %eax, %ebx
movl %eax, %edi
.LBB2_4:
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.LBB2_15:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiPf,@object # @_Z6kernelPiPf
.section .rodata,"a",@progbits
.globl _Z6kernelPiPf
.p2align 3, 0x0
_Z6kernelPiPf:
.quad _Z21__device_stub__kernelPiPf
.size _Z6kernelPiPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error : %s (%d)\n"
.size .L.str, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA - area to left of 1 on standard normal: %f\n"
.size .L.str.2, 49
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "runtime: %f\n"
.size .L.str.3, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiPf"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CuRand Failure"
.size .Lstr, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012b45c_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error : %s (%d)\n"
.text
.globl _Z14CUDAErrorCheckv
.type _Z14CUDAErrorCheckv, @function
_Z14CUDAErrorCheckv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebx, %ecx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14CUDAErrorCheckv, .-_Z14CUDAErrorCheckv
.globl _Z27__device_stub__Z6kernelPiPfPiPf
.type _Z27__device_stub__Z6kernelPiPfPiPf, @function
_Z27__device_stub__Z6kernelPiPfPiPf:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z27__device_stub__Z6kernelPiPfPiPf, .-_Z27__device_stub__Z6kernelPiPfPiPf
.globl _Z6kernelPiPf
.type _Z6kernelPiPf, @function
_Z6kernelPiPf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPiPfPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6kernelPiPf, .-_Z6kernelPiPf
.section .rodata.str1.1
.LC1:
.string "CuRand Failure\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "CUDA - area to left of 1 on standard normal: %f\n"
.section .rodata.str1.1
.LC6:
.string "runtime: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r13d
leal (%rax,%rax), %r14d
movslq %r14d, %r14
leaq 0(,%r14,4), %rcx
movq %rcx, 8(%rsp)
leal -1(%rax), %eax
movl $2138, %r12d
leaq 4(,%rax,4), %r15
jmp .L22
.L28:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L17:
call cudaDeviceSynchronize@PLT
call _Z14CUDAErrorCheckv
movl $2, %ecx
movl $400000, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L18
movq %rbp, %rax
leaq (%r15,%rbp), %rdx
.L19:
addl (%rax), %ebx
addq $4, %rax
cmpq %rdx, %rax
jne .L19
.L18:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $0x00000000, 68(%rsp)
leaq 68(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 104(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
movq 96(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, (%rsp)
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movl %ebx, %ebx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
divsd %xmm1, %xmm0
addsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %r12
cmpq $2141, %r12
je .L27
.L22:
leaq 24(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $121, %esi
call curandCreateGenerator@PLT
movl %eax, %ebp
movq %r12, %rsi
movq 32(%rsp), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
orl %eax, %ebp
movq %r14, %rdx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call curandGenerateUniform@PLT
orl %ebp, %eax
movl %eax, %ebx
movq 32(%rsp), %rdi
call curandDestroyGenerator@PLT
orl %eax, %ebx
jne .L28
movl $400000, %edi
call malloc@PLT
movq %rax, %rbp
leaq 40(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
call _Z14CUDAErrorCheckv
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1000, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $100, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 68(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z27__device_stub__Z6kernelPiPfPiPf
jmp .L17
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z6kernelPiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.align 8
.LC4:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda.hip"
.globl _Z21__device_stub__kernelPiPf # -- Begin function _Z21__device_stub__kernelPiPf
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiPf,@function
_Z21__device_stub__kernelPiPf: # @_Z21__device_stub__kernelPiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPiPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiPf, .Lfunc_end0-_Z21__device_stub__kernelPiPf
.cfi_endproc
# -- End function
.globl _Z14CUDAErrorCheckv # -- Begin function _Z14CUDAErrorCheckv
.p2align 4, 0x90
.type _Z14CUDAErrorCheckv,@function
_Z14CUDAErrorCheckv: # @_Z14CUDAErrorCheckv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
callq hipGetLastError
testl %eax, %eax
jne .LBB1_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size _Z14CUDAErrorCheckv, .Lfunc_end1-_Z14CUDAErrorCheckv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI2_1:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967396, %rbx # imm = 0x100000064
movq 8(%rsi), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
addl %eax, %eax
cltq
movq %rax, 104(%rsp) # 8-byte Spill
leaq (,%rax,4), %rax
movq %rax, 96(%rsp) # 8-byte Spill
cvtsi2sd %r14d, %xmm0
movsd %xmm0, 88(%rsp) # 8-byte Spill
movl %r14d, %r15d
leaq 900(%rbx), %r13
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_10: # in Loop: Header=BB2_1 Depth=1
xorl %ebx, %ebx
.LBB2_13: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $0, 48(%rsp)
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 64(%rsp), %rax
movq 72(%rsp), %rcx
subq 168(%rsp), %rax
cvtsi2sd %rax, %xmm0
subq 176(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 112(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbp, %rdi
callq free
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movl %ebx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd 88(%rsp), %xmm0 # 8-byte Folded Reload
addsd .LCPI2_1(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movl $.L.str.3, %edi
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
incq %r12
cmpq $3, %r12
je .LBB2_14
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_12 Depth 2
leaq 40(%rsp), %rdi
movq 96(%rsp), %rsi # 8-byte Reload
callq hipMalloc
leaq 32(%rsp), %rdi
movl $402, %esi # imm = 0x192
callq hiprandCreateGenerator
movl %eax, %ebx
movq 32(%rsp), %rdi
leaq 2138(%r12), %rsi
callq hiprandSetPseudoRandomGeneratorSeed
movl %eax, %ebp
orl %ebx, %ebp
movq 32(%rsp), %rdi
movq 40(%rsp), %rsi
movq 104(%rsp), %rdx # 8-byte Reload
callq hiprandGenerateUniform
movl %eax, %ebx
orl %ebp, %ebx
movq 32(%rsp), %rdi
callq hiprandDestroyGenerator
orl %ebx, %eax
jne .LBB2_15
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbp
movl $400000, %esi # imm = 0x61A80
leaq 24(%rsp), %rdi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_3
# %bb.5: # %_Z14CUDAErrorCheckv.exit
# in Loop: Header=BB2_1 Depth=1
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967396, %rdi # imm = 0x100000064
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6: # in Loop: Header=BB2_1 Depth=1
movq 24(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
leaq 160(%rsp), %rax
movq %rax, 64(%rsp)
leaq 152(%rsp), %rax
movq %rax, 72(%rsp)
leaq 48(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
movl $_Z6kernelPiPf, %edi
leaq 64(%rsp), %r9
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7: # in Loop: Header=BB2_1 Depth=1
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB2_8
# %bb.9: # %_Z14CUDAErrorCheckv.exit37
# in Loop: Header=BB2_1 Depth=1
movq 24(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
testl %r14d, %r14d
jle .LBB2_10
# %bb.11: # %.lr.ph.preheader
# in Loop: Header=BB2_1 Depth=1
xorl %eax, %eax
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_12: # %.lr.ph
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
addl (%rbp,%rax,4), %ebx
incq %rax
cmpq %rax, %r15
jne .LBB2_12
jmp .LBB2_13
.LBB2_14:
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 240
movl %eax, %edi
movl %eax, %ebx
jmp .LBB2_4
.LBB2_3:
movl %eax, %ebx
movl %eax, %edi
.LBB2_4:
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
movl %ebx, %edx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.LBB2_15:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiPf,@object # @_Z6kernelPiPf
.section .rodata,"a",@progbits
.globl _Z6kernelPiPf
.p2align 3, 0x0
_Z6kernelPiPf:
.quad _Z21__device_stub__kernelPiPf
.size _Z6kernelPiPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error : %s (%d)\n"
.size .L.str, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA - area to left of 1 on standard normal: %f\n"
.size .L.str.2, 49
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "runtime: %f\n"
.size .L.str.3, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiPf"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CuRand Failure"
.size .Lstr, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <string>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <malloc.h>
#include <vector>
#include <iostream>
#include <fstream>
#include <functional>
#include <algorithm>
#include <ctime>
#define ACCURACY 0.01
#define NUM_OF_GPU_THREADS 2
#define BLOCK_SIZE 32
#define NUM_OF_GPU_BLOCKS 4
#define MAX 3
#define MIN 0
//
//__global__ void addKernel(int *c, const int *a, const int *b)
//{
// int i = threadIdx.x;
// c[i] = a[i] + b[i];
//}
//
//int main()
//{
// const int arraySize = 5;
// const int a[arraySize] = { 1, 2, 3, 4, 5 };
// const int b[arraySize] = { 10, 20, 30, 40, 50 };
// int c[arraySize] = { 0 };
//
// // Add vectors in parallel.
// cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addWithCuda failed!");
// return 1;
// }
//
// printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
//
// // cudaDeviceReset must be called before exiting in order for profiling and
// // tracing tools such as Nsight and Visual Profiler to show complete traces.
// cudaStatus = cudaDeviceReset();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceReset failed!");
// return 1;
// }
//
// return 0;
//}
//
//// Helper function for using CUDA to add vectors in parallel.
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
//{
// int *dev_a = 0;
// int *dev_b = 0;
// int *dev_c = 0;
// cudaError_t cudaStatus;
//
// // Choose which GPU to run on, change this on a multi-GPU system.
// cudaStatus = cudaSetDevice(0);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
// }
//
// // Allocate GPU buffers for three vectors (two input, one output) .
// cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// // Copy input vectors from host memory to GPU buffers.
// cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// // Launch a kernel on the GPU with one thread for each element.
// addKernel << <1, size >> > (dev_c, dev_a, dev_b);
//
// // Check for any errors launching the kernel
// cudaStatus = cudaGetLastError();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// goto Error;
// }
//
// // cudaDeviceSynchronize waits for the kernel to finish, and returns
// // any errors encountered during the launch.
// cudaStatus = cudaDeviceSynchronize();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
// goto Error;
// }
//
// // Copy output vector from GPU buffer to host memory.
// cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
//Error:
// cudaFree(dev_c);
// cudaFree(dev_a);
// cudaFree(dev_b);
//
// return cudaStatus;
//}
void checkError(cudaError_t err, int line) {
if (cudaSuccess != err) {
std::cerr << "Error " << cudaGetErrorName(err) << " happenend: " << cudaGetErrorString(err) << " at line " << line << std::endl;
exit(-1);
}
}
//void matrixInit(float * matrix, int size) {
// for (int i = 0; i < size; ++i) {
// matrix[i] = rand() % (MAX - MIN + 1) + MIN;
// }
//}
__global__ void sgemmKernel(float * cudaA, float * cudaB, float * cudaC, int m, int n, int k, float alpha, float beta) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ float A[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float B[BLOCK_SIZE][BLOCK_SIZE];
int row = bx * BLOCK_SIZE + tx;
int col = by * BLOCK_SIZE + ty;
float sum = 0;
for (int i = 0; i < gridDim.y; i++) {
int a_col = i * BLOCK_SIZE + ty;
int a_row = row;
if (a_row < m && a_col < k) {
A[tx][ty] = cudaA[a_row + a_col * m];
}
int b_col = col;
int b_row = i * BLOCK_SIZE + tx;
if (b_row < k && b_col < n){
B[tx][ty] = cudaB[b_row * n + b_col];
}
__syncthreads();
if (row < m && col < n) {
int j_end = ((i + 1) * BLOCK_SIZE < k) ? BLOCK_SIZE : k - i * BLOCK_SIZE;
for (int j = 0; j < j_end; j++) {
sum += A[tx][j] * B[j][ty];
}
}
__syncthreads();
}
if (row < m && col < n) {
cudaC[row + col * m] = 0;
cudaC[row + col * m] = cudaC[row + col * m] * beta + sum * alpha;
}
}
bool readColMajorMatrixFile(const char *fn, int &nr_row, int &nr_col, std::vector<float>&v)
{
std::cerr << "Opening file:" << fn << std::endl;
std::fstream f(fn, std::fstream::in);
if (!f.good()) {
return false;
}
// Read # of rows and cols
f >> nr_row;
f >> nr_col;
float data;
std::cerr << "Matrix dimension: " << nr_row << "x" << nr_col << std::endl;
while (f.good()) {
f >> data;
v.push_back(data);
}
v.pop_back(); // remove the duplicated last element
return true;
}
bool writeColMajorMatrixFile(const char *fn, int nr_row, int nr_col, std::vector<float>&v)
{
std::cerr << "Opening file:" << fn << " for write." << std::endl;
std::fstream f(fn, std::fstream::out);
if (!f.good()) {
return false;
}
// Read # of rows and cols
f << nr_row << " " << nr_col << " ";
std::cerr << "Matrix dimension: " << nr_row << "x" << nr_col << std::endl;
for (int i = 0; i < v.size(); ++i) {
f << v[i] << ' ';
}
f << "\n";
return true;
}
void basicSgemm(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
if ((transa != 'N') && (transa != 'n')) {
std::cerr << "unsupported value of 'transa' in regtileSgemm()" << std::endl;
return;
}
if ((transb != 'T') && (transb != 't')) {
std::cerr << "unsupported value of 'transb' in regtileSgemm()" << std::endl;
return;
}
for (int mm = 0; mm < m; ++mm) {
for (int nn = 0; nn < n; ++nn) {
float c = 0.0f;
for (int i = 0; i < k; ++i) {
float a = A[mm + i * lda];
float b = B[nn + i * ldb];
c += a * b;
}
C[mm + nn * ldc] = C[mm + nn * ldc] * beta + alpha * c;
}
}
}
void basicSgemm_par(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
float *cudaA, *cudaB, *cudaC;
int sizeA = m * k * sizeof(float), sizeB = k * n * sizeof(float), sizeC = m * n * sizeof(float);
if ((transa != 'N') && (transa != 'n')) {
std::cerr << "unsupported value of 'transa' in regtileSgemm()" << std::endl;
return;
}
if ((transb != 'T') && (transb != 't')) {
std::cerr << "unsupported value of 'transb' in regtileSgemm()" << std::endl;
return;
}
checkError(cudaMalloc(&cudaA, sizeA), __LINE__);
checkError(cudaMemcpy(cudaA, A, sizeA, cudaMemcpyHostToDevice), __LINE__);
checkError(cudaMalloc(&cudaB, sizeB), __LINE__);
checkError(cudaMemcpy(cudaB, B, sizeB, cudaMemcpyHostToDevice), __LINE__);
checkError(cudaMalloc(&cudaC, sizeC), __LINE__);
dim3 dimGrid((m + BLOCK_SIZE - 1) / BLOCK_SIZE, (n + BLOCK_SIZE - 1) / BLOCK_SIZE);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
sgemmKernel <<< dimGrid, dimBlock >>> (cudaA, cudaB, cudaC, m, n, k, alpha, beta);
checkError(cudaMemcpy(C, cudaC, sizeC, cudaMemcpyDeviceToHost), __LINE__);
checkError(cudaFree(cudaA), __LINE__);
checkError(cudaFree(cudaB), __LINE__);
checkError(cudaFree(cudaC), __LINE__);
}
int main(int argc, char *argv[]) {
int matArow, matAcol;
int matBrow, matBcol;
std::vector<float> matA;
std::vector<float> matBT;
//int m, n, k;
float timeSeq = 0.0f, timePar = 0.0f;
cudaEvent_t start = cudaEvent_t();
checkError(cudaEventCreate(&start), __LINE__);
cudaEvent_t stop = cudaEvent_t();
checkError(cudaEventCreate(&stop), __LINE__);
if (argc != 4)
{
fprintf(stderr, "Expecting three input filenames\n");
exit(-1);
}
/* Read in data */
// load A
readColMajorMatrixFile(argv[1], matArow, matAcol, matA);
// load B^T
readColMajorMatrixFile(argv[2], matBcol, matBrow, matBT);
/*m = std::stoi(argv[1]);
n = std::stoi(argv[2]);
k = std::stoi(argv[3]);
// A - m*k
// B - k*n
// C - m*n
matArow = m;
matAcol = k;
matBrow = k;
matBcol = n;
// allocate space for A and B
//matrixInit(&matA.front(), m*k);
//matrixInit(&matBT.front(), k*n);*/
// allocate space for C and D
std::vector<float> matC(matArow * matBcol);
std::vector<float> matD(matArow * matBcol);
//clock_t begin = clock();
cudaEventRecord(start, 0);
// Use standard sgemm interface
basicSgemm('N', 'T', matArow, matBcol, matAcol, 1.0f, &matA.front(), matArow, &matBT.front(), matBcol, 0.0f, &matC.front(), matArow);
clock_t end = clock();
//timeSeq = float(end - begin) / CLOCKS_PER_SEC;
checkError(cudaEventRecord(stop, 0), __LINE__);
checkError(cudaEventSynchronize(stop), __LINE__);
checkError(cudaEventElapsedTime(&timeSeq, start, stop), __LINE__);
timeSeq /= 1000;
cudaEventRecord(start, 0);
// Use parallel sgemm interface
basicSgemm_par('N', 'T', matArow, matBcol, matAcol, 1.0f, &matA.front(), matArow, &matBT.front(), matBcol, 0.0f, &matD.front(), matArow);
checkError(cudaEventRecord(stop, 0), __LINE__);
checkError(cudaEventSynchronize(stop), __LINE__);
checkError(cudaEventElapsedTime(&timePar, start, stop), __LINE__);
timePar /= 1000;
checkError(cudaEventDestroy(start), __LINE__);
checkError(cudaEventDestroy(stop), __LINE__);
writeColMajorMatrixFile(argv[3], matArow, matBcol, matC);
std::function<bool(double, double)> comparator = [](double left, double right) {
// Lambda function to compare 2 doubles with ACCURACY
return fabs(left - right) < ACCURACY;
};
std::cerr << "********************DZ3Z1**********************" << std::endl;
std::cerr << "Elapsed time - SEQ: " << timeSeq << "." << std::endl;
std::cerr << "Elapsed time - PAR: " << timePar << "." << std::endl;
std::cerr << (std::equal(matC.begin(), matC.end(), matD.begin(), comparator) ? "TEST PASSED" : "TEST FAILED") << std::endl;
std::cerr << "***********************************************" << std::endl;
return 0;
} | code for sm_80
Function : _Z11sgemmKernelPfS_S_iiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x10], PT ; /* 0x00000400ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0070*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0080*/ LEA R3, R3, R0, 0x5 ; /* 0x0000000003037211 */
/* 0x001fe200078e28ff */
/*0090*/ IMAD R4, R5, 0x20, R2 ; /* 0x0000002005047824 */
/* 0x002fe200078e0202 */
/*00a0*/ @!P0 BRA 0xb20 ; /* 0x00000a7000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.SHL.U32 R5, R0, 0x80, RZ ; /* 0x0000008000057824 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe20003f26270 */
/*00d0*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*00e0*/ LEA R6, R2.reuse, 0x1100, 0x2 ; /* 0x0000110002067811 */
/* 0x040fe200078e10ff */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.LT.AND P1, PT, R3, c[0x0][0x178], !P1 ; /* 0x00005e0003007a0c */
/* 0x000fe20004f21270 */
/*0110*/ IMAD R12, R2, 0x4, R5 ; /* 0x00000004020c7824 */
/* 0x000fe200078e0205 */
/*0120*/ IADD3 R13, R5, 0x8, RZ ; /* 0x00000008050d7810 */
/* 0x000fe20007ffe0ff */
/*0130*/ ULDC UR5, c[0x0][0x180] ; /* 0x0000600000057ab9 */
/* 0x000fc40000000800 */
/*0140*/ ULOP3.LUT UR5, URZ, UR5, URZ, 0x33, !UPT ; /* 0x000000053f057292 */
/* 0x000fe4000f8e333f */
/*0150*/ SHF.L.U32 R11, R7, 0x5, RZ ; /* 0x00000005070b7819 */
/* 0x000fca00000006ff */
/*0160*/ IMAD.IADD R8, R11.reuse, 0x1, R2 ; /* 0x000000010b087824 */
/* 0x040fe400078e0202 */
/*0170*/ IMAD.IADD R15, R11, 0x1, R0 ; /* 0x000000010b0f7824 */
/* 0x000fc600078e0200 */
/*0180*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x180], PT ; /* 0x0000600008007a0c */
/* 0x000fe40003f06270 */
/*0190*/ ISETP.GE.AND P2, PT, R15, c[0x0][0x180], PT ; /* 0x000060000f007a0c */
/* 0x000fe40003f46270 */
/*01a0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe40000706670 */
/*01b0*/ ISETP.GE.OR P2, PT, R4, c[0x0][0x17c], P2 ; /* 0x00005f0004007a0c */
/* 0x000fd60001746670 */
/*01c0*/ @!P0 MOV R9, 0x4 ; /* 0x0000000400098802 */
/* 0x000fe20000000f00 */
/*01d0*/ @!P0 IMAD R8, R8, c[0x0][0x178], R3 ; /* 0x00005e0008088a24 */
/* 0x000fe400078e0203 */
/*01e0*/ @!P2 IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff11a424 */
/* 0x000fe400078e00ff */
/*01f0*/ @!P0 IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008088625 */
/* 0x000fc800078e0209 */
/*0200*/ @!P2 IMAD R14, R15, c[0x0][0x17c], R4 ; /* 0x00005f000f0eaa24 */
/* 0x000fe400078e0204 */
/*0210*/ @!P0 LDG.E R9, [R8.64] ; /* 0x0000000808098981 */
/* 0x000ea4000c1e1900 */
/*0220*/ @!P2 IMAD.WIDE R14, R14, R17, c[0x0][0x168] ; /* 0x00005a000e0ea625 */
/* 0x000fcc00078e0211 */
/*0230*/ @!P2 LDG.E R15, [R14.64] ; /* 0x000000080e0fa981 */
/* 0x000ee2000c1e1900 */
/*0240*/ IADD3 R10, R11, 0x20, RZ ; /* 0x000000200b0a7810 */
/* 0x000fe20007ffe0ff */
/*0250*/ BSSY B0, 0xb00 ; /* 0x000008a000007945 */
/* 0x000fe20003800000 */
/*0260*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0270*/ @!P0 STS [R12], R9 ; /* 0x000000090c008388 */
/* 0x0041e20000000800 */
/*0280*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x180], PT ; /* 0x000060000b007a0c */
/* 0x000fc80003f06270 */
/*0290*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x180], P0 ; /* 0x000060000a007a0c */
/* 0x000fc80000706270 */
/*02a0*/ PLOP3.LUT P0, PT, P1, P0, PT, 0x8a, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20000f01172 */
/*02b0*/ @!P2 STS [R12+0x1000], R15 ; /* 0x0010000f0c00a388 */
/* 0x0081e80000000800 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ ISETP.GE.U32.AND P2, PT, R7, c[0x0][0x10], PT ; /* 0x0000040007007a0c */
/* 0x000fce0003f46070 */
/*02e0*/ @P0 BRA 0xaf0 ; /* 0x0000080000000947 */
/* 0x000fea0003800000 */
/*02f0*/ IADD3 R8, -R11, -0x21, RZ ; /* 0xffffffdf0b087810 */
/* 0x001fe20007ffe1ff */
/*0300*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc60008000000 */
/*0310*/ IMNMX R9, R8, UR5, !PT ; /* 0x0000000508097c17 */
/* 0x000fc8000f800200 */
/*0320*/ LOP3.LUT R8, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff087212 */
/* 0x000fca00078e33ff */
/*0330*/ IMAD.IADD R8, R8, 0x1, -R11 ; /* 0x0000000108087824 */
/* 0x000fca00078e0a0b */
/*0340*/ IADD3 R10, R8.reuse, -0x1, RZ ; /* 0xffffffff080a7810 */
/* 0x040fe40007ffe0ff */
/*0350*/ LOP3.LUT R14, R8, 0x3, RZ, 0xc0, !PT ; /* 0x00000003080e7812 */
/* 0x000fe400078ec0ff */
/*0360*/ ISETP.GE.U32.AND P0, PT, R10, 0x3, PT ; /* 0x000000030a00780c */
/* 0x000fda0003f06070 */
/*0370*/ @!P0 BRA 0xa00 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*0380*/ IADD3 R11, R14, R9, R11 ; /* 0x000000090e0b7210 */
/* 0x000fe20007ffe00b */
/*0390*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*03a0*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000d */
/*03b0*/ IADD3 R15, -R11, RZ, RZ ; /* 0x000000ff0b0f7210 */
/* 0x000fe20007ffe1ff */
/*03c0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0006 */
/*03d0*/ ISETP.GT.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fda0003f04270 */
/*03e0*/ @!P0 BRA 0x900 ; /* 0x0000051000008947 */
/* 0x000fea0003800000 */
/*03f0*/ IADD3 R10, R15, -0x1, RZ ; /* 0xffffffff0f0a7810 */
/* 0x000fe40007ffe0ff */
/*0400*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0410*/ ISETP.GT.AND P3, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fda0003f64270 */
/*0420*/ @!P3 BRA 0x720 ; /* 0x000002f00000b947 */
/* 0x000fea0003800000 */
/*0430*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0440*/ LDS R22, [R8+-0x100] ; /* 0xffff000008167984 */
/* 0x000fe20000000800 */
/*0450*/ IADD3 R15, R15, -0x10, RZ ; /* 0xfffffff00f0f7810 */
/* 0x000fe20007ffe0ff */
/*0460*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*0470*/ LDS.64 R16, [R9+-0x8] ; /* 0xfffff80009107984 */
/* 0x000e220000000a00 */
/*0480*/ ISETP.GT.AND P3, PT, R15, 0xd, PT ; /* 0x0000000d0f00780c */
/* 0x000fc60003f64270 */
/*0490*/ LDS R25, [R8+-0x80] ; /* 0xffff800008197984 */
/* 0x000e680000000800 */
/*04a0*/ LDS R27, [R8] ; /* 0x00000000081b7984 */
/* 0x000fe80000000800 */
/*04b0*/ LDS.64 R10, [R9] ; /* 0x00000000090a7984 */
/* 0x000ea80000000a00 */
/*04c0*/ LDS R20, [R8+0x80] ; /* 0x0000800008147984 */
/* 0x000ee80000000800 */
/*04d0*/ LDS R23, [R8+0x100] ; /* 0x0001000008177984 */
/* 0x000fe80000000800 */
/*04e0*/ LDS.64 R18, [R9+0x8] ; /* 0x0000080009127984 */
/* 0x000f280000000a00 */
/*04f0*/ LDS R24, [R8+0x180] ; /* 0x0001800008187984 */
/* 0x000f620000000800 */
/*0500*/ FFMA R16, R22, R16, R21 ; /* 0x0000001016107223 */
/* 0x001fc60000000015 */
/*0510*/ LDS R22, [R8+0x280] ; /* 0x0002800008167984 */
/* 0x000fe20000000800 */
/*0520*/ FFMA R21, R25, R17, R16 ; /* 0x0000001119157223 */
/* 0x002fc60000000010 */
/*0530*/ LDS R25, [R8+0x200] ; /* 0x0002000008197984 */
/* 0x000fe80000000800 */
/*0540*/ LDS.64 R16, [R9+0x10] ; /* 0x0000100009107984 */
/* 0x000e220000000a00 */
/*0550*/ FFMA R10, R27, R10, R21 ; /* 0x0000000a1b0a7223 */
/* 0x004fc60000000015 */
/*0560*/ LDS R21, [R8+0x300] ; /* 0x0003000008157984 */
/* 0x000fe20000000800 */
/*0570*/ FFMA R26, R20, R11, R10 ; /* 0x0000000b141a7223 */
/* 0x008fc6000000000a */
/*0580*/ LDS.64 R10, [R9+0x18] ; /* 0x00001800090a7984 */
/* 0x000e680000000a00 */
/*0590*/ LDS R20, [R8+0x380] ; /* 0x0003800008147984 */
/* 0x000ea20000000800 */
/*05a0*/ FFMA R18, R23, R18, R26 ; /* 0x0000001217127223 */
/* 0x010fc6000000001a */
/*05b0*/ LDS R23, [R8+0x400] ; /* 0x0004000008177984 */
/* 0x000fe20000000800 */
/*05c0*/ FFMA R24, R24, R19, R18 ; /* 0x0000001318187223 */
/* 0x020fc60000000012 */
/*05d0*/ LDS.64 R18, [R9+0x20] ; /* 0x0000200009127984 */
/* 0x000ee20000000a00 */
/*05e0*/ FFMA R16, R25, R16, R24 ; /* 0x0000001019107223 */
/* 0x001fc60000000018 */
/*05f0*/ LDS R24, [R8+0x480] ; /* 0x0004800008187984 */
/* 0x000e220000000800 */
/*0600*/ FFMA R22, R22, R17, R16 ; /* 0x0000001116167223 */
/* 0x000fc60000000010 */
/*0610*/ LDS R25, [R8+0x500] ; /* 0x0005000008197984 */
/* 0x000fe20000000800 */
/*0620*/ FFMA R10, R21, R10, R22 ; /* 0x0000000a150a7223 */
/* 0x002fc60000000016 */
/*0630*/ LDS.64 R16, [R9+0x28] ; /* 0x0000280009107984 */
/* 0x000e620000000a00 */
/*0640*/ FFMA R26, R20, R11, R10 ; /* 0x0000000b141a7223 */
/* 0x004fc6000000000a */
/*0650*/ LDS R22, [R8+0x580] ; /* 0x0005800008167984 */
/* 0x000ea80000000800 */
/*0660*/ LDS R21, [R8+0x600] ; /* 0x0006000008157984 */
/* 0x000fe20000000800 */
/*0670*/ FFMA R18, R23, R18, R26 ; /* 0x0000001217127223 */
/* 0x008fc6000000001a */
/*0680*/ LDS.64 R10, [R9+0x30] ; /* 0x00003000090a7984 */
/* 0x0007280000000a00 */
/*0690*/ LDS R20, [R8+0x680] ; /* 0x0006800008147984 */
/* 0x000b220000000800 */
/*06a0*/ IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009097810 */
/* 0x008fe40007ffe0ff */
/*06b0*/ IADD3 R8, R8, 0x800, RZ ; /* 0x0000080008087810 */
/* 0x020fe20007ffe0ff */
/*06c0*/ FFMA R18, R24, R19, R18 ; /* 0x0000001318127223 */
/* 0x001fc80000000012 */
/*06d0*/ FFMA R16, R25, R16, R18 ; /* 0x0000001019107223 */
/* 0x002fc80000000012 */
/*06e0*/ FFMA R16, R22, R17, R16 ; /* 0x0000001116107223 */
/* 0x004fc80000000010 */
/*06f0*/ FFMA R21, R21, R10, R16 ; /* 0x0000000a15157223 */
/* 0x010fc80000000010 */
/*0700*/ FFMA R21, R20, R11, R21 ; /* 0x0000000b14157223 */
/* 0x000fe20000000015 */
/*0710*/ @P3 BRA 0x440 ; /* 0xfffffd2000003947 */
/* 0x000fea000383ffff */
/*0720*/ IADD3 R10, R15, -0x1, RZ ; /* 0xffffffff0f0a7810 */
/* 0x000fc80007ffe0ff */
/*0730*/ ISETP.GT.AND P3, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f64270 */
/*0740*/ @!P3 BRA 0x8e0 ; /* 0x000001900000b947 */
/* 0x000fea0003800000 */
/*0750*/ LDS R22, [R8+-0x100] ; /* 0xffff000008167984 */
/* 0x000fe20000000800 */
/*0760*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0770*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0780*/ IADD3 R15, R15, -0x8, RZ ; /* 0xfffffff80f0f7810 */
/* 0x000fe20007ffe0ff */
/*0790*/ LDS.64 R18, [R9+-0x8] ; /* 0xfffff80009127984 */
/* 0x000e280000000a00 */
/*07a0*/ LDS R24, [R8+-0x80] ; /* 0xffff800008187984 */
/* 0x000e680000000800 */
/*07b0*/ LDS R23, [R8] ; /* 0x0000000008177984 */
/* 0x000fe80000000800 */
/*07c0*/ LDS.64 R16, [R9] ; /* 0x0000000009107984 */
/* 0x000ea80000000a00 */
/*07d0*/ LDS R20, [R8+0x80] ; /* 0x0000800008147984 */
/* 0x000ee80000000800 */
/*07e0*/ LDS R25, [R8+0x100] ; /* 0x0001000008197984 */
/* 0x000fe80000000800 */
/*07f0*/ LDS.64 R10, [R9+0x8] ; /* 0x00000800090a7984 */
/* 0x000f220000000a00 */
/*0800*/ FFMA R18, R22, R18, R21 ; /* 0x0000001216127223 */
/* 0x001fc60000000015 */
/*0810*/ LDS R22, [R8+0x180] ; /* 0x0001800008167984 */
/* 0x000e220000000800 */
/*0820*/ FFMA R26, R24, R19, R18 ; /* 0x00000013181a7223 */
/* 0x002fc60000000012 */
/*0830*/ LDS R21, [R8+0x200] ; /* 0x0002000008157984 */
/* 0x000fe80000000800 */
/*0840*/ LDS.64 R18, [R9+0x10] ; /* 0x0000100009127984 */
/* 0x0003620000000a00 */
/*0850*/ FFMA R16, R23, R16, R26 ; /* 0x0000001017107223 */
/* 0x004fc6000000001a */
/*0860*/ LDS R24, [R8+0x280] ; /* 0x0002800008187984 */
/* 0x0005620000000800 */
/*0870*/ FFMA R16, R20, R17, R16 ; /* 0x0000001114107223 */
/* 0x008fe20000000010 */
/*0880*/ IADD3 R9, R9, 0x20, RZ ; /* 0x0000002009097810 */
/* 0x002fe40007ffe0ff */
/*0890*/ IADD3 R8, R8, 0x400, RZ ; /* 0x0000040008087810 */
/* 0x004fe20007ffe0ff */
/*08a0*/ FFMA R10, R25, R10, R16 ; /* 0x0000000a190a7223 */
/* 0x010fc80000000010 */
/*08b0*/ FFMA R10, R22, R11, R10 ; /* 0x0000000b160a7223 */
/* 0x001fc8000000000a */
/*08c0*/ FFMA R21, R21, R18, R10 ; /* 0x0000001215157223 */
/* 0x020fc8000000000a */
/*08d0*/ FFMA R21, R24, R19, R21 ; /* 0x0000001318157223 */
/* 0x000fe40000000015 */
/*08e0*/ ISETP.NE.OR P0, PT, R15, 0x1, P0 ; /* 0x000000010f00780c */
/* 0x000fda0000705670 */
/*08f0*/ @!P0 BRA 0xa00 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0900*/ LDS R18, [R8+-0x100] ; /* 0xffff000008127984 */
/* 0x000fe20000000800 */
/*0910*/ IADD3 R15, R15, -0x4, RZ ; /* 0xfffffffc0f0f7810 */
/* 0x000fe20007ffe0ff */
/*0920*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0930*/ LDS.64 R10, [R9+-0x8] ; /* 0xfffff800090a7984 */
/* 0x000e220000000a00 */
/*0940*/ ISETP.NE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fc60003f05270 */
/*0950*/ LDS R19, [R8+-0x80] ; /* 0xffff800008137984 */
/* 0x000e680000000800 */
/*0960*/ LDS R20, [R8] ; /* 0x0000000008147984 */
/* 0x000fe80000000800 */
/*0970*/ LDS.64 R16, [R9] ; /* 0x0000000009107984 */
/* 0x0004e80000000a00 */
/*0980*/ LDS R22, [R8+0x80] ; /* 0x0000800008167984 */
/* 0x0009620000000800 */
/*0990*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x004fc40007ffe0ff */
/*09a0*/ IADD3 R8, R8, 0x200, RZ ; /* 0x0000020008087810 */
/* 0x010fe20007ffe0ff */
/*09b0*/ FFMA R10, R18, R10, R21 ; /* 0x0000000a120a7223 */
/* 0x001fc80000000015 */
/*09c0*/ FFMA R11, R19, R11, R10 ; /* 0x0000000b130b7223 */
/* 0x002fc8000000000a */
/*09d0*/ FFMA R16, R20, R16, R11 ; /* 0x0000001014107223 */
/* 0x008fc8000000000b */
/*09e0*/ FFMA R21, R22, R17, R16 ; /* 0x0000001116157223 */
/* 0x020fe20000000010 */
/*09f0*/ @P0 BRA 0x900 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0a00*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fda0003f05270 */
/*0a10*/ @!P0 BRA 0xaf0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0a20*/ MOV R8, UR4 ; /* 0x0000000400087c02 */
/* 0x000fe20008000f00 */
/*0a30*/ ULEA UR6, UR4, 0x1000, 0x7 ; /* 0x0000100004067891 */
/* 0x000fe2000f8e383f */
/*0a40*/ ISETP.NE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fc60003f05270 */
/*0a50*/ IMAD R8, R8, 0x4, R5 ; /* 0x0000000408087824 */
/* 0x000fca00078e0205 */
/*0a60*/ LDS R15, [R2.X4+UR6] ; /* 0x00000006020f7984 */
/* 0x000fe80008004800 */
/*0a70*/ LDS.128 R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000c00 */
/*0a80*/ FFMA R21, R15, R8, R21 ; /* 0x000000080f157223 */
/* 0x001fe20000000015 */
/*0a90*/ @!P0 BRA 0xaf0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ ISETP.NE.AND P0, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fe20003f05270 */
/*0ab0*/ LDS R8, [R2.X4+UR6+0x80] ; /* 0x0000800602087984 */
/* 0x000e180008004800 */
/*0ac0*/ @P0 LDS R11, [R2.X4+UR6+0x100] ; /* 0x00010006020b0984 */
/* 0x000e620008004800 */
/*0ad0*/ FFMA R21, R8, R9, R21 ; /* 0x0000000908157223 */
/* 0x001fc80000000015 */
/*0ae0*/ @P0 FFMA R21, R11, R10, R21 ; /* 0x0000000a0b150223 */
/* 0x002fe40000000015 */
/*0af0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0b00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b10*/ @!P2 BRA 0x150 ; /* 0xfffff6300000a947 */
/* 0x000fea000383ffff */
/*0b20*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fc80003f06270 */
/*0b30*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0b40*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0b60*/ FMUL R21, R21, c[0x0][0x184] ; /* 0x0000610015157a20 */
/* 0x000fe40000400000 */
/*0b70*/ IMAD R3, R4, c[0x0][0x178], R3 ; /* 0x00005e0004037a24 */
/* 0x000fe400078e0203 */
/*0b80*/ FFMA R21, RZ, c[0x0][0x188], R21 ; /* 0x00006200ff157a23 */
/* 0x000fca0000000015 */
/*0b90*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0ba0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101908 */
/*0bb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bc0*/ BRA 0xbc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <string>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <malloc.h>
#include <vector>
#include <iostream>
#include <fstream>
#include <functional>
#include <algorithm>
#include <ctime>
#define ACCURACY 0.01
#define NUM_OF_GPU_THREADS 2
#define BLOCK_SIZE 32
#define NUM_OF_GPU_BLOCKS 4
#define MAX 3
#define MIN 0
//
//__global__ void addKernel(int *c, const int *a, const int *b)
//{
// int i = threadIdx.x;
// c[i] = a[i] + b[i];
//}
//
//int main()
//{
// const int arraySize = 5;
// const int a[arraySize] = { 1, 2, 3, 4, 5 };
// const int b[arraySize] = { 10, 20, 30, 40, 50 };
// int c[arraySize] = { 0 };
//
// // Add vectors in parallel.
// cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addWithCuda failed!");
// return 1;
// }
//
// printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
//
// // cudaDeviceReset must be called before exiting in order for profiling and
// // tracing tools such as Nsight and Visual Profiler to show complete traces.
// cudaStatus = cudaDeviceReset();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceReset failed!");
// return 1;
// }
//
// return 0;
//}
//
//// Helper function for using CUDA to add vectors in parallel.
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
//{
// int *dev_a = 0;
// int *dev_b = 0;
// int *dev_c = 0;
// cudaError_t cudaStatus;
//
// // Choose which GPU to run on, change this on a multi-GPU system.
// cudaStatus = cudaSetDevice(0);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
// }
//
// // Allocate GPU buffers for three vectors (two input, one output) .
// cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// // Copy input vectors from host memory to GPU buffers.
// cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// // Launch a kernel on the GPU with one thread for each element.
// addKernel << <1, size >> > (dev_c, dev_a, dev_b);
//
// // Check for any errors launching the kernel
// cudaStatus = cudaGetLastError();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// goto Error;
// }
//
// // cudaDeviceSynchronize waits for the kernel to finish, and returns
// // any errors encountered during the launch.
// cudaStatus = cudaDeviceSynchronize();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
// goto Error;
// }
//
// // Copy output vector from GPU buffer to host memory.
// cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
//Error:
// cudaFree(dev_c);
// cudaFree(dev_a);
// cudaFree(dev_b);
//
// return cudaStatus;
//}
void checkError(cudaError_t err, int line) {
if (cudaSuccess != err) {
std::cerr << "Error " << cudaGetErrorName(err) << " happenend: " << cudaGetErrorString(err) << " at line " << line << std::endl;
exit(-1);
}
}
//void matrixInit(float * matrix, int size) {
// for (int i = 0; i < size; ++i) {
// matrix[i] = rand() % (MAX - MIN + 1) + MIN;
// }
//}
__global__ void sgemmKernel(float * cudaA, float * cudaB, float * cudaC, int m, int n, int k, float alpha, float beta) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ float A[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float B[BLOCK_SIZE][BLOCK_SIZE];
int row = bx * BLOCK_SIZE + tx;
int col = by * BLOCK_SIZE + ty;
float sum = 0;
for (int i = 0; i < gridDim.y; i++) {
int a_col = i * BLOCK_SIZE + ty;
int a_row = row;
if (a_row < m && a_col < k) {
A[tx][ty] = cudaA[a_row + a_col * m];
}
int b_col = col;
int b_row = i * BLOCK_SIZE + tx;
if (b_row < k && b_col < n){
B[tx][ty] = cudaB[b_row * n + b_col];
}
__syncthreads();
if (row < m && col < n) {
int j_end = ((i + 1) * BLOCK_SIZE < k) ? BLOCK_SIZE : k - i * BLOCK_SIZE;
for (int j = 0; j < j_end; j++) {
sum += A[tx][j] * B[j][ty];
}
}
__syncthreads();
}
if (row < m && col < n) {
cudaC[row + col * m] = 0;
cudaC[row + col * m] = cudaC[row + col * m] * beta + sum * alpha;
}
}
bool readColMajorMatrixFile(const char *fn, int &nr_row, int &nr_col, std::vector<float>&v)
{
std::cerr << "Opening file:" << fn << std::endl;
std::fstream f(fn, std::fstream::in);
if (!f.good()) {
return false;
}
// Read # of rows and cols
f >> nr_row;
f >> nr_col;
float data;
std::cerr << "Matrix dimension: " << nr_row << "x" << nr_col << std::endl;
while (f.good()) {
f >> data;
v.push_back(data);
}
v.pop_back(); // remove the duplicated last element
return true;
}
bool writeColMajorMatrixFile(const char *fn, int nr_row, int nr_col, std::vector<float>&v)
{
std::cerr << "Opening file:" << fn << " for write." << std::endl;
std::fstream f(fn, std::fstream::out);
if (!f.good()) {
return false;
}
// Read # of rows and cols
f << nr_row << " " << nr_col << " ";
std::cerr << "Matrix dimension: " << nr_row << "x" << nr_col << std::endl;
for (int i = 0; i < v.size(); ++i) {
f << v[i] << ' ';
}
f << "\n";
return true;
}
void basicSgemm(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
if ((transa != 'N') && (transa != 'n')) {
std::cerr << "unsupported value of 'transa' in regtileSgemm()" << std::endl;
return;
}
if ((transb != 'T') && (transb != 't')) {
std::cerr << "unsupported value of 'transb' in regtileSgemm()" << std::endl;
return;
}
for (int mm = 0; mm < m; ++mm) {
for (int nn = 0; nn < n; ++nn) {
float c = 0.0f;
for (int i = 0; i < k; ++i) {
float a = A[mm + i * lda];
float b = B[nn + i * ldb];
c += a * b;
}
C[mm + nn * ldc] = C[mm + nn * ldc] * beta + alpha * c;
}
}
}
void basicSgemm_par(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
float *cudaA, *cudaB, *cudaC;
int sizeA = m * k * sizeof(float), sizeB = k * n * sizeof(float), sizeC = m * n * sizeof(float);
if ((transa != 'N') && (transa != 'n')) {
std::cerr << "unsupported value of 'transa' in regtileSgemm()" << std::endl;
return;
}
if ((transb != 'T') && (transb != 't')) {
std::cerr << "unsupported value of 'transb' in regtileSgemm()" << std::endl;
return;
}
checkError(cudaMalloc(&cudaA, sizeA), __LINE__);
checkError(cudaMemcpy(cudaA, A, sizeA, cudaMemcpyHostToDevice), __LINE__);
checkError(cudaMalloc(&cudaB, sizeB), __LINE__);
checkError(cudaMemcpy(cudaB, B, sizeB, cudaMemcpyHostToDevice), __LINE__);
checkError(cudaMalloc(&cudaC, sizeC), __LINE__);
dim3 dimGrid((m + BLOCK_SIZE - 1) / BLOCK_SIZE, (n + BLOCK_SIZE - 1) / BLOCK_SIZE);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
sgemmKernel <<< dimGrid, dimBlock >>> (cudaA, cudaB, cudaC, m, n, k, alpha, beta);
checkError(cudaMemcpy(C, cudaC, sizeC, cudaMemcpyDeviceToHost), __LINE__);
checkError(cudaFree(cudaA), __LINE__);
checkError(cudaFree(cudaB), __LINE__);
checkError(cudaFree(cudaC), __LINE__);
}
int main(int argc, char *argv[]) {
int matArow, matAcol;
int matBrow, matBcol;
std::vector<float> matA;
std::vector<float> matBT;
//int m, n, k;
float timeSeq = 0.0f, timePar = 0.0f;
cudaEvent_t start = cudaEvent_t();
checkError(cudaEventCreate(&start), __LINE__);
cudaEvent_t stop = cudaEvent_t();
checkError(cudaEventCreate(&stop), __LINE__);
if (argc != 4)
{
fprintf(stderr, "Expecting three input filenames\n");
exit(-1);
}
/* Read in data */
// load A
readColMajorMatrixFile(argv[1], matArow, matAcol, matA);
// load B^T
readColMajorMatrixFile(argv[2], matBcol, matBrow, matBT);
/*m = std::stoi(argv[1]);
n = std::stoi(argv[2]);
k = std::stoi(argv[3]);
// A - m*k
// B - k*n
// C - m*n
matArow = m;
matAcol = k;
matBrow = k;
matBcol = n;
// allocate space for A and B
//matrixInit(&matA.front(), m*k);
//matrixInit(&matBT.front(), k*n);*/
// allocate space for C and D
std::vector<float> matC(matArow * matBcol);
std::vector<float> matD(matArow * matBcol);
//clock_t begin = clock();
cudaEventRecord(start, 0);
// Use standard sgemm interface
basicSgemm('N', 'T', matArow, matBcol, matAcol, 1.0f, &matA.front(), matArow, &matBT.front(), matBcol, 0.0f, &matC.front(), matArow);
clock_t end = clock();
//timeSeq = float(end - begin) / CLOCKS_PER_SEC;
checkError(cudaEventRecord(stop, 0), __LINE__);
checkError(cudaEventSynchronize(stop), __LINE__);
checkError(cudaEventElapsedTime(&timeSeq, start, stop), __LINE__);
timeSeq /= 1000;
cudaEventRecord(start, 0);
// Use parallel sgemm interface
basicSgemm_par('N', 'T', matArow, matBcol, matAcol, 1.0f, &matA.front(), matArow, &matBT.front(), matBcol, 0.0f, &matD.front(), matArow);
checkError(cudaEventRecord(stop, 0), __LINE__);
checkError(cudaEventSynchronize(stop), __LINE__);
checkError(cudaEventElapsedTime(&timePar, start, stop), __LINE__);
timePar /= 1000;
checkError(cudaEventDestroy(start), __LINE__);
checkError(cudaEventDestroy(stop), __LINE__);
writeColMajorMatrixFile(argv[3], matArow, matBcol, matC);
std::function<bool(double, double)> comparator = [](double left, double right) {
// Lambda function to compare 2 doubles with ACCURACY
return fabs(left - right) < ACCURACY;
};
std::cerr << "********************DZ3Z1**********************" << std::endl;
std::cerr << "Elapsed time - SEQ: " << timeSeq << "." << std::endl;
std::cerr << "Elapsed time - PAR: " << timePar << "." << std::endl;
std::cerr << (std::equal(matC.begin(), matC.end(), matD.begin(), comparator) ? "TEST PASSED" : "TEST FAILED") << std::endl;
std::cerr << "***********************************************" << std::endl;
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <string>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <malloc.h>
#include <vector>
#include <iostream>
#include <fstream>
#include <functional>
#include <algorithm>
#include <ctime>
#define ACCURACY 0.01
#define NUM_OF_GPU_THREADS 2
#define BLOCK_SIZE 32
#define NUM_OF_GPU_BLOCKS 4
#define MAX 3
#define MIN 0
//
//__global__ void addKernel(int *c, const int *a, const int *b)
//{
// int i = threadIdx.x;
// c[i] = a[i] + b[i];
//}
//
//int main()
//{
// const int arraySize = 5;
// const int a[arraySize] = { 1, 2, 3, 4, 5 };
// const int b[arraySize] = { 10, 20, 30, 40, 50 };
// int c[arraySize] = { 0 };
//
// // Add vectors in parallel.
// cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addWithCuda failed!");
// return 1;
// }
//
// printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
//
// // cudaDeviceReset must be called before exiting in order for profiling and
// // tracing tools such as Nsight and Visual Profiler to show complete traces.
// cudaStatus = cudaDeviceReset();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceReset failed!");
// return 1;
// }
//
// return 0;
//}
//
//// Helper function for using CUDA to add vectors in parallel.
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
//{
// int *dev_a = 0;
// int *dev_b = 0;
// int *dev_c = 0;
// cudaError_t cudaStatus;
//
// // Choose which GPU to run on, change this on a multi-GPU system.
// cudaStatus = cudaSetDevice(0);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
// }
//
// // Allocate GPU buffers for three vectors (two input, one output) .
// cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// // Copy input vectors from host memory to GPU buffers.
// cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// // Launch a kernel on the GPU with one thread for each element.
// addKernel << <1, size >> > (dev_c, dev_a, dev_b);
//
// // Check for any errors launching the kernel
// cudaStatus = cudaGetLastError();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// goto Error;
// }
//
// // cudaDeviceSynchronize waits for the kernel to finish, and returns
// // any errors encountered during the launch.
// cudaStatus = cudaDeviceSynchronize();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
// goto Error;
// }
//
// // Copy output vector from GPU buffer to host memory.
// cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
//Error:
// cudaFree(dev_c);
// cudaFree(dev_a);
// cudaFree(dev_b);
//
// return cudaStatus;
//}
void checkError(hipError_t err, int line) {
if (hipSuccess != err) {
std::cerr << "Error " << hipGetErrorName(err) << " happenend: " << hipGetErrorString(err) << " at line " << line << std::endl;
exit(-1);
}
}
//void matrixInit(float * matrix, int size) {
// for (int i = 0; i < size; ++i) {
// matrix[i] = rand() % (MAX - MIN + 1) + MIN;
// }
//}
__global__ void sgemmKernel(float * cudaA, float * cudaB, float * cudaC, int m, int n, int k, float alpha, float beta) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ float A[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float B[BLOCK_SIZE][BLOCK_SIZE];
int row = bx * BLOCK_SIZE + tx;
int col = by * BLOCK_SIZE + ty;
float sum = 0;
for (int i = 0; i < gridDim.y; i++) {
int a_col = i * BLOCK_SIZE + ty;
int a_row = row;
if (a_row < m && a_col < k) {
A[tx][ty] = cudaA[a_row + a_col * m];
}
int b_col = col;
int b_row = i * BLOCK_SIZE + tx;
if (b_row < k && b_col < n){
B[tx][ty] = cudaB[b_row * n + b_col];
}
__syncthreads();
if (row < m && col < n) {
int j_end = ((i + 1) * BLOCK_SIZE < k) ? BLOCK_SIZE : k - i * BLOCK_SIZE;
for (int j = 0; j < j_end; j++) {
sum += A[tx][j] * B[j][ty];
}
}
__syncthreads();
}
if (row < m && col < n) {
cudaC[row + col * m] = 0;
cudaC[row + col * m] = cudaC[row + col * m] * beta + sum * alpha;
}
}
bool readColMajorMatrixFile(const char *fn, int &nr_row, int &nr_col, std::vector<float>&v)
{
std::cerr << "Opening file:" << fn << std::endl;
std::fstream f(fn, std::fstream::in);
if (!f.good()) {
return false;
}
// Read # of rows and cols
f >> nr_row;
f >> nr_col;
float data;
std::cerr << "Matrix dimension: " << nr_row << "x" << nr_col << std::endl;
while (f.good()) {
f >> data;
v.push_back(data);
}
v.pop_back(); // remove the duplicated last element
return true;
}
bool writeColMajorMatrixFile(const char *fn, int nr_row, int nr_col, std::vector<float>&v)
{
std::cerr << "Opening file:" << fn << " for write." << std::endl;
std::fstream f(fn, std::fstream::out);
if (!f.good()) {
return false;
}
// Read # of rows and cols
f << nr_row << " " << nr_col << " ";
std::cerr << "Matrix dimension: " << nr_row << "x" << nr_col << std::endl;
for (int i = 0; i < v.size(); ++i) {
f << v[i] << ' ';
}
f << "\n";
return true;
}
void basicSgemm(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
if ((transa != 'N') && (transa != 'n')) {
std::cerr << "unsupported value of 'transa' in regtileSgemm()" << std::endl;
return;
}
if ((transb != 'T') && (transb != 't')) {
std::cerr << "unsupported value of 'transb' in regtileSgemm()" << std::endl;
return;
}
for (int mm = 0; mm < m; ++mm) {
for (int nn = 0; nn < n; ++nn) {
float c = 0.0f;
for (int i = 0; i < k; ++i) {
float a = A[mm + i * lda];
float b = B[nn + i * ldb];
c += a * b;
}
C[mm + nn * ldc] = C[mm + nn * ldc] * beta + alpha * c;
}
}
}
void basicSgemm_par(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
float *cudaA, *cudaB, *cudaC;
int sizeA = m * k * sizeof(float), sizeB = k * n * sizeof(float), sizeC = m * n * sizeof(float);
if ((transa != 'N') && (transa != 'n')) {
std::cerr << "unsupported value of 'transa' in regtileSgemm()" << std::endl;
return;
}
if ((transb != 'T') && (transb != 't')) {
std::cerr << "unsupported value of 'transb' in regtileSgemm()" << std::endl;
return;
}
checkError(hipMalloc(&cudaA, sizeA), __LINE__);
checkError(hipMemcpy(cudaA, A, sizeA, hipMemcpyHostToDevice), __LINE__);
checkError(hipMalloc(&cudaB, sizeB), __LINE__);
checkError(hipMemcpy(cudaB, B, sizeB, hipMemcpyHostToDevice), __LINE__);
checkError(hipMalloc(&cudaC, sizeC), __LINE__);
dim3 dimGrid((m + BLOCK_SIZE - 1) / BLOCK_SIZE, (n + BLOCK_SIZE - 1) / BLOCK_SIZE);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
sgemmKernel <<< dimGrid, dimBlock >>> (cudaA, cudaB, cudaC, m, n, k, alpha, beta);
checkError(hipMemcpy(C, cudaC, sizeC, hipMemcpyDeviceToHost), __LINE__);
checkError(hipFree(cudaA), __LINE__);
checkError(hipFree(cudaB), __LINE__);
checkError(hipFree(cudaC), __LINE__);
}
int main(int argc, char *argv[]) {
int matArow, matAcol;
int matBrow, matBcol;
std::vector<float> matA;
std::vector<float> matBT;
//int m, n, k;
float timeSeq = 0.0f, timePar = 0.0f;
hipEvent_t start = hipEvent_t();
checkError(hipEventCreate(&start), __LINE__);
hipEvent_t stop = hipEvent_t();
checkError(hipEventCreate(&stop), __LINE__);
if (argc != 4)
{
fprintf(stderr, "Expecting three input filenames\n");
exit(-1);
}
/* Read in data */
// load A
readColMajorMatrixFile(argv[1], matArow, matAcol, matA);
// load B^T
readColMajorMatrixFile(argv[2], matBcol, matBrow, matBT);
/*m = std::stoi(argv[1]);
n = std::stoi(argv[2]);
k = std::stoi(argv[3]);
// A - m*k
// B - k*n
// C - m*n
matArow = m;
matAcol = k;
matBrow = k;
matBcol = n;
// allocate space for A and B
//matrixInit(&matA.front(), m*k);
//matrixInit(&matBT.front(), k*n);*/
// allocate space for C and D
std::vector<float> matC(matArow * matBcol);
std::vector<float> matD(matArow * matBcol);
//clock_t begin = clock();
hipEventRecord(start, 0);
// Use standard sgemm interface
basicSgemm('N', 'T', matArow, matBcol, matAcol, 1.0f, &matA.front(), matArow, &matBT.front(), matBcol, 0.0f, &matC.front(), matArow);
clock_t end = clock();
//timeSeq = float(end - begin) / CLOCKS_PER_SEC;
checkError(hipEventRecord(stop, 0), __LINE__);
checkError(hipEventSynchronize(stop), __LINE__);
checkError(hipEventElapsedTime(&timeSeq, start, stop), __LINE__);
timeSeq /= 1000;
hipEventRecord(start, 0);
// Use parallel sgemm interface
basicSgemm_par('N', 'T', matArow, matBcol, matAcol, 1.0f, &matA.front(), matArow, &matBT.front(), matBcol, 0.0f, &matD.front(), matArow);
checkError(hipEventRecord(stop, 0), __LINE__);
checkError(hipEventSynchronize(stop), __LINE__);
checkError(hipEventElapsedTime(&timePar, start, stop), __LINE__);
timePar /= 1000;
checkError(hipEventDestroy(start), __LINE__);
checkError(hipEventDestroy(stop), __LINE__);
writeColMajorMatrixFile(argv[3], matArow, matBcol, matC);
std::function<bool(double, double)> comparator = [](double left, double right) {
// Lambda function to compare 2 doubles with ACCURACY
return fabs(left - right) < ACCURACY;
};
std::cerr << "********************DZ3Z1**********************" << std::endl;
std::cerr << "Elapsed time - SEQ: " << timeSeq << "." << std::endl;
std::cerr << "Elapsed time - PAR: " << timePar << "." << std::endl;
std::cerr << (std::equal(matC.begin(), matC.end(), matD.begin(), comparator) ? "TEST PASSED" : "TEST FAILED") << std::endl;
std::cerr << "***********************************************" << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <string>
#include <math.h>
#include <stdlib.h>
#include <string.h>
#include <malloc.h>
#include <vector>
#include <iostream>
#include <fstream>
#include <functional>
#include <algorithm>
#include <ctime>
#define ACCURACY 0.01
#define NUM_OF_GPU_THREADS 2
#define BLOCK_SIZE 32
#define NUM_OF_GPU_BLOCKS 4
#define MAX 3
#define MIN 0
//
//__global__ void addKernel(int *c, const int *a, const int *b)
//{
// int i = threadIdx.x;
// c[i] = a[i] + b[i];
//}
//
//int main()
//{
// const int arraySize = 5;
// const int a[arraySize] = { 1, 2, 3, 4, 5 };
// const int b[arraySize] = { 10, 20, 30, 40, 50 };
// int c[arraySize] = { 0 };
//
// // Add vectors in parallel.
// cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addWithCuda failed!");
// return 1;
// }
//
// printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
//
// // cudaDeviceReset must be called before exiting in order for profiling and
// // tracing tools such as Nsight and Visual Profiler to show complete traces.
// cudaStatus = cudaDeviceReset();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceReset failed!");
// return 1;
// }
//
// return 0;
//}
//
//// Helper function for using CUDA to add vectors in parallel.
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
//{
// int *dev_a = 0;
// int *dev_b = 0;
// int *dev_c = 0;
// cudaError_t cudaStatus;
//
// // Choose which GPU to run on, change this on a multi-GPU system.
// cudaStatus = cudaSetDevice(0);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
// }
//
// // Allocate GPU buffers for three vectors (two input, one output) .
// cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// // Copy input vectors from host memory to GPU buffers.
// cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// // Launch a kernel on the GPU with one thread for each element.
// addKernel << <1, size >> > (dev_c, dev_a, dev_b);
//
// // Check for any errors launching the kernel
// cudaStatus = cudaGetLastError();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// goto Error;
// }
//
// // cudaDeviceSynchronize waits for the kernel to finish, and returns
// // any errors encountered during the launch.
// cudaStatus = cudaDeviceSynchronize();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
// goto Error;
// }
//
// // Copy output vector from GPU buffer to host memory.
// cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
//Error:
// cudaFree(dev_c);
// cudaFree(dev_a);
// cudaFree(dev_b);
//
// return cudaStatus;
//}
void checkError(hipError_t err, int line) {
if (hipSuccess != err) {
std::cerr << "Error " << hipGetErrorName(err) << " happenend: " << hipGetErrorString(err) << " at line " << line << std::endl;
exit(-1);
}
}
//void matrixInit(float * matrix, int size) {
// for (int i = 0; i < size; ++i) {
// matrix[i] = rand() % (MAX - MIN + 1) + MIN;
// }
//}
__global__ void sgemmKernel(float * cudaA, float * cudaB, float * cudaC, int m, int n, int k, float alpha, float beta) {
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
__shared__ float A[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float B[BLOCK_SIZE][BLOCK_SIZE];
int row = bx * BLOCK_SIZE + tx;
int col = by * BLOCK_SIZE + ty;
float sum = 0;
for (int i = 0; i < gridDim.y; i++) {
int a_col = i * BLOCK_SIZE + ty;
int a_row = row;
if (a_row < m && a_col < k) {
A[tx][ty] = cudaA[a_row + a_col * m];
}
int b_col = col;
int b_row = i * BLOCK_SIZE + tx;
if (b_row < k && b_col < n){
B[tx][ty] = cudaB[b_row * n + b_col];
}
__syncthreads();
if (row < m && col < n) {
int j_end = ((i + 1) * BLOCK_SIZE < k) ? BLOCK_SIZE : k - i * BLOCK_SIZE;
for (int j = 0; j < j_end; j++) {
sum += A[tx][j] * B[j][ty];
}
}
__syncthreads();
}
if (row < m && col < n) {
cudaC[row + col * m] = 0;
cudaC[row + col * m] = cudaC[row + col * m] * beta + sum * alpha;
}
}
bool readColMajorMatrixFile(const char *fn, int &nr_row, int &nr_col, std::vector<float>&v)
{
std::cerr << "Opening file:" << fn << std::endl;
std::fstream f(fn, std::fstream::in);
if (!f.good()) {
return false;
}
// Read # of rows and cols
f >> nr_row;
f >> nr_col;
float data;
std::cerr << "Matrix dimension: " << nr_row << "x" << nr_col << std::endl;
while (f.good()) {
f >> data;
v.push_back(data);
}
v.pop_back(); // remove the duplicated last element
return true;
}
bool writeColMajorMatrixFile(const char *fn, int nr_row, int nr_col, std::vector<float>&v)
{
std::cerr << "Opening file:" << fn << " for write." << std::endl;
std::fstream f(fn, std::fstream::out);
if (!f.good()) {
return false;
}
// Read # of rows and cols
f << nr_row << " " << nr_col << " ";
std::cerr << "Matrix dimension: " << nr_row << "x" << nr_col << std::endl;
for (int i = 0; i < v.size(); ++i) {
f << v[i] << ' ';
}
f << "\n";
return true;
}
void basicSgemm(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
if ((transa != 'N') && (transa != 'n')) {
std::cerr << "unsupported value of 'transa' in regtileSgemm()" << std::endl;
return;
}
if ((transb != 'T') && (transb != 't')) {
std::cerr << "unsupported value of 'transb' in regtileSgemm()" << std::endl;
return;
}
for (int mm = 0; mm < m; ++mm) {
for (int nn = 0; nn < n; ++nn) {
float c = 0.0f;
for (int i = 0; i < k; ++i) {
float a = A[mm + i * lda];
float b = B[nn + i * ldb];
c += a * b;
}
C[mm + nn * ldc] = C[mm + nn * ldc] * beta + alpha * c;
}
}
}
void basicSgemm_par(char transa, char transb, int m, int n, int k, float alpha, const float *A, int lda, const float *B, int ldb, float beta, float *C, int ldc)
{
float *cudaA, *cudaB, *cudaC;
int sizeA = m * k * sizeof(float), sizeB = k * n * sizeof(float), sizeC = m * n * sizeof(float);
if ((transa != 'N') && (transa != 'n')) {
std::cerr << "unsupported value of 'transa' in regtileSgemm()" << std::endl;
return;
}
if ((transb != 'T') && (transb != 't')) {
std::cerr << "unsupported value of 'transb' in regtileSgemm()" << std::endl;
return;
}
checkError(hipMalloc(&cudaA, sizeA), __LINE__);
checkError(hipMemcpy(cudaA, A, sizeA, hipMemcpyHostToDevice), __LINE__);
checkError(hipMalloc(&cudaB, sizeB), __LINE__);
checkError(hipMemcpy(cudaB, B, sizeB, hipMemcpyHostToDevice), __LINE__);
checkError(hipMalloc(&cudaC, sizeC), __LINE__);
dim3 dimGrid((m + BLOCK_SIZE - 1) / BLOCK_SIZE, (n + BLOCK_SIZE - 1) / BLOCK_SIZE);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
sgemmKernel <<< dimGrid, dimBlock >>> (cudaA, cudaB, cudaC, m, n, k, alpha, beta);
checkError(hipMemcpy(C, cudaC, sizeC, hipMemcpyDeviceToHost), __LINE__);
checkError(hipFree(cudaA), __LINE__);
checkError(hipFree(cudaB), __LINE__);
checkError(hipFree(cudaC), __LINE__);
}
int main(int argc, char *argv[]) {
int matArow, matAcol;
int matBrow, matBcol;
std::vector<float> matA;
std::vector<float> matBT;
//int m, n, k;
float timeSeq = 0.0f, timePar = 0.0f;
hipEvent_t start = hipEvent_t();
checkError(hipEventCreate(&start), __LINE__);
hipEvent_t stop = hipEvent_t();
checkError(hipEventCreate(&stop), __LINE__);
if (argc != 4)
{
fprintf(stderr, "Expecting three input filenames\n");
exit(-1);
}
/* Read in data */
// load A
readColMajorMatrixFile(argv[1], matArow, matAcol, matA);
// load B^T
readColMajorMatrixFile(argv[2], matBcol, matBrow, matBT);
/*m = std::stoi(argv[1]);
n = std::stoi(argv[2]);
k = std::stoi(argv[3]);
// A - m*k
// B - k*n
// C - m*n
matArow = m;
matAcol = k;
matBrow = k;
matBcol = n;
// allocate space for A and B
//matrixInit(&matA.front(), m*k);
//matrixInit(&matBT.front(), k*n);*/
// allocate space for C and D
std::vector<float> matC(matArow * matBcol);
std::vector<float> matD(matArow * matBcol);
//clock_t begin = clock();
hipEventRecord(start, 0);
// Use standard sgemm interface
basicSgemm('N', 'T', matArow, matBcol, matAcol, 1.0f, &matA.front(), matArow, &matBT.front(), matBcol, 0.0f, &matC.front(), matArow);
clock_t end = clock();
//timeSeq = float(end - begin) / CLOCKS_PER_SEC;
checkError(hipEventRecord(stop, 0), __LINE__);
checkError(hipEventSynchronize(stop), __LINE__);
checkError(hipEventElapsedTime(&timeSeq, start, stop), __LINE__);
timeSeq /= 1000;
hipEventRecord(start, 0);
// Use parallel sgemm interface
basicSgemm_par('N', 'T', matArow, matBcol, matAcol, 1.0f, &matA.front(), matArow, &matBT.front(), matBcol, 0.0f, &matD.front(), matArow);
checkError(hipEventRecord(stop, 0), __LINE__);
checkError(hipEventSynchronize(stop), __LINE__);
checkError(hipEventElapsedTime(&timePar, start, stop), __LINE__);
timePar /= 1000;
checkError(hipEventDestroy(start), __LINE__);
checkError(hipEventDestroy(stop), __LINE__);
writeColMajorMatrixFile(argv[3], matArow, matBcol, matC);
std::function<bool(double, double)> comparator = [](double left, double right) {
// Lambda function to compare 2 doubles with ACCURACY
return fabs(left - right) < ACCURACY;
};
std::cerr << "********************DZ3Z1**********************" << std::endl;
std::cerr << "Elapsed time - SEQ: " << timeSeq << "." << std::endl;
std::cerr << "Elapsed time - PAR: " << timePar << "." << std::endl;
std::cerr << (std::equal(matC.begin(), matC.end(), matD.begin(), comparator) ? "TEST PASSED" : "TEST FAILED") << std::endl;
std::cerr << "***********************************************" << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11sgemmKernelPfS_S_iiiff
.globl _Z11sgemmKernelPfS_S_iiiff
.p2align 8
.type _Z11sgemmKernelPfS_S_iiiff,@function
_Z11sgemmKernelPfS_S_iiiff:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x34
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s14, 5, v3
v_lshl_add_u32 v1, s15, 5, v4
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s9, v1
s_cmp_eq_u32 s10, 0
s_cbranch_scc1 .LBB0_11
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s12, s[0:1], 0x20
v_lshlrev_b32_e32 v2, 2, v4
v_lshlrev_b32_e32 v5, 7, v3
s_and_b32 s13, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v6, 0x1000, v2
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, v5, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v8, v6, v5
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s11, s11, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_12
.LBB0_3:
s_lshl_b32 s14, s11, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, s14, v4
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s3, s12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s15, s3
s_cbranch_execz .LBB0_5
v_mad_u64_u32 v[10:11], null, v9, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[9:10], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s3, s4, v9
v_add_co_ci_u32_e64 v10, s3, s5, v10, s3
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v9
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v9, s14, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s3, s12, v9
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s15, s3
s_cbranch_execz .LBB0_7
v_mad_u64_u32 v[10:11], null, v9, s9, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[9:10], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s3, s6, v9
v_add_co_ci_u32_e64 v10, s3, s7, v10, s3
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v9
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s15
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s13
s_cbranch_execz .LBB0_2
s_add_i32 s15, s14, 32
s_sub_i32 s14, s12, s14
s_cmp_ge_i32 s15, s12
s_cselect_b32 s14, s14, 32
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s14, 1
s_cbranch_scc1 .LBB0_2
v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v5
s_mov_b32 s15, 0
.LBB0_10:
ds_load_b32 v11, v10
ds_load_b32 v12, v9
v_add_nc_u32_e32 v10, 4, v10
v_add_nc_u32_e32 v9, 0x80, v9
s_add_i32 s15, s15, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s15, s14
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v11, v12
s_cbranch_scc1 .LBB0_10
s_branch .LBB0_2
.LBB0_11:
v_mov_b32_e32 v2, 0
.LBB0_12:
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_14
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v2, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_fmac_f32_e64 v2, s3, 0
global_store_b32 v[0:1], v2, off
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11sgemmKernelPfS_S_iiiff
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11sgemmKernelPfS_S_iiiff, .Lfunc_end0-_Z11sgemmKernelPfS_S_iiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11sgemmKernelPfS_S_iiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11sgemmKernelPfS_S_iiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11sgemmKernelPfS_S_iiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x10], PT ; /* 0x00000400ff007a0c */
/* 0x000fe20003f05270 */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0070*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0080*/ LEA R3, R3, R0, 0x5 ; /* 0x0000000003037211 */
/* 0x001fe200078e28ff */
/*0090*/ IMAD R4, R5, 0x20, R2 ; /* 0x0000002005047824 */
/* 0x002fe200078e0202 */
/*00a0*/ @!P0 BRA 0xb20 ; /* 0x00000a7000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.SHL.U32 R5, R0, 0x80, RZ ; /* 0x0000008000057824 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe20003f26270 */
/*00d0*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*00e0*/ LEA R6, R2.reuse, 0x1100, 0x2 ; /* 0x0000110002067811 */
/* 0x040fe200078e10ff */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.LT.AND P1, PT, R3, c[0x0][0x178], !P1 ; /* 0x00005e0003007a0c */
/* 0x000fe20004f21270 */
/*0110*/ IMAD R12, R2, 0x4, R5 ; /* 0x00000004020c7824 */
/* 0x000fe200078e0205 */
/*0120*/ IADD3 R13, R5, 0x8, RZ ; /* 0x00000008050d7810 */
/* 0x000fe20007ffe0ff */
/*0130*/ ULDC UR5, c[0x0][0x180] ; /* 0x0000600000057ab9 */
/* 0x000fc40000000800 */
/*0140*/ ULOP3.LUT UR5, URZ, UR5, URZ, 0x33, !UPT ; /* 0x000000053f057292 */
/* 0x000fe4000f8e333f */
/*0150*/ SHF.L.U32 R11, R7, 0x5, RZ ; /* 0x00000005070b7819 */
/* 0x000fca00000006ff */
/*0160*/ IMAD.IADD R8, R11.reuse, 0x1, R2 ; /* 0x000000010b087824 */
/* 0x040fe400078e0202 */
/*0170*/ IMAD.IADD R15, R11, 0x1, R0 ; /* 0x000000010b0f7824 */
/* 0x000fc600078e0200 */
/*0180*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x180], PT ; /* 0x0000600008007a0c */
/* 0x000fe40003f06270 */
/*0190*/ ISETP.GE.AND P2, PT, R15, c[0x0][0x180], PT ; /* 0x000060000f007a0c */
/* 0x000fe40003f46270 */
/*01a0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe40000706670 */
/*01b0*/ ISETP.GE.OR P2, PT, R4, c[0x0][0x17c], P2 ; /* 0x00005f0004007a0c */
/* 0x000fd60001746670 */
/*01c0*/ @!P0 MOV R9, 0x4 ; /* 0x0000000400098802 */
/* 0x000fe20000000f00 */
/*01d0*/ @!P0 IMAD R8, R8, c[0x0][0x178], R3 ; /* 0x00005e0008088a24 */
/* 0x000fe400078e0203 */
/*01e0*/ @!P2 IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff11a424 */
/* 0x000fe400078e00ff */
/*01f0*/ @!P0 IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008088625 */
/* 0x000fc800078e0209 */
/*0200*/ @!P2 IMAD R14, R15, c[0x0][0x17c], R4 ; /* 0x00005f000f0eaa24 */
/* 0x000fe400078e0204 */
/*0210*/ @!P0 LDG.E R9, [R8.64] ; /* 0x0000000808098981 */
/* 0x000ea4000c1e1900 */
/*0220*/ @!P2 IMAD.WIDE R14, R14, R17, c[0x0][0x168] ; /* 0x00005a000e0ea625 */
/* 0x000fcc00078e0211 */
/*0230*/ @!P2 LDG.E R15, [R14.64] ; /* 0x000000080e0fa981 */
/* 0x000ee2000c1e1900 */
/*0240*/ IADD3 R10, R11, 0x20, RZ ; /* 0x000000200b0a7810 */
/* 0x000fe20007ffe0ff */
/*0250*/ BSSY B0, 0xb00 ; /* 0x000008a000007945 */
/* 0x000fe20003800000 */
/*0260*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0270*/ @!P0 STS [R12], R9 ; /* 0x000000090c008388 */
/* 0x0041e20000000800 */
/*0280*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x180], PT ; /* 0x000060000b007a0c */
/* 0x000fc80003f06270 */
/*0290*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x180], P0 ; /* 0x000060000a007a0c */
/* 0x000fc80000706270 */
/*02a0*/ PLOP3.LUT P0, PT, P1, P0, PT, 0x8a, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20000f01172 */
/*02b0*/ @!P2 STS [R12+0x1000], R15 ; /* 0x0010000f0c00a388 */
/* 0x0081e80000000800 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ ISETP.GE.U32.AND P2, PT, R7, c[0x0][0x10], PT ; /* 0x0000040007007a0c */
/* 0x000fce0003f46070 */
/*02e0*/ @P0 BRA 0xaf0 ; /* 0x0000080000000947 */
/* 0x000fea0003800000 */
/*02f0*/ IADD3 R8, -R11, -0x21, RZ ; /* 0xffffffdf0b087810 */
/* 0x001fe20007ffe1ff */
/*0300*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc60008000000 */
/*0310*/ IMNMX R9, R8, UR5, !PT ; /* 0x0000000508097c17 */
/* 0x000fc8000f800200 */
/*0320*/ LOP3.LUT R8, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff087212 */
/* 0x000fca00078e33ff */
/*0330*/ IMAD.IADD R8, R8, 0x1, -R11 ; /* 0x0000000108087824 */
/* 0x000fca00078e0a0b */
/*0340*/ IADD3 R10, R8.reuse, -0x1, RZ ; /* 0xffffffff080a7810 */
/* 0x040fe40007ffe0ff */
/*0350*/ LOP3.LUT R14, R8, 0x3, RZ, 0xc0, !PT ; /* 0x00000003080e7812 */
/* 0x000fe400078ec0ff */
/*0360*/ ISETP.GE.U32.AND P0, PT, R10, 0x3, PT ; /* 0x000000030a00780c */
/* 0x000fda0003f06070 */
/*0370*/ @!P0 BRA 0xa00 ; /* 0x0000068000008947 */
/* 0x000fea0003800000 */
/*0380*/ IADD3 R11, R14, R9, R11 ; /* 0x000000090e0b7210 */
/* 0x000fe20007ffe00b */
/*0390*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*03a0*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000d */
/*03b0*/ IADD3 R15, -R11, RZ, RZ ; /* 0x000000ff0b0f7210 */
/* 0x000fe20007ffe1ff */
/*03c0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0006 */
/*03d0*/ ISETP.GT.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fda0003f04270 */
/*03e0*/ @!P0 BRA 0x900 ; /* 0x0000051000008947 */
/* 0x000fea0003800000 */
/*03f0*/ IADD3 R10, R15, -0x1, RZ ; /* 0xffffffff0f0a7810 */
/* 0x000fe40007ffe0ff */
/*0400*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0410*/ ISETP.GT.AND P3, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fda0003f64270 */
/*0420*/ @!P3 BRA 0x720 ; /* 0x000002f00000b947 */
/* 0x000fea0003800000 */
/*0430*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0440*/ LDS R22, [R8+-0x100] ; /* 0xffff000008167984 */
/* 0x000fe20000000800 */
/*0450*/ IADD3 R15, R15, -0x10, RZ ; /* 0xfffffff00f0f7810 */
/* 0x000fe20007ffe0ff */
/*0460*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*0470*/ LDS.64 R16, [R9+-0x8] ; /* 0xfffff80009107984 */
/* 0x000e220000000a00 */
/*0480*/ ISETP.GT.AND P3, PT, R15, 0xd, PT ; /* 0x0000000d0f00780c */
/* 0x000fc60003f64270 */
/*0490*/ LDS R25, [R8+-0x80] ; /* 0xffff800008197984 */
/* 0x000e680000000800 */
/*04a0*/ LDS R27, [R8] ; /* 0x00000000081b7984 */
/* 0x000fe80000000800 */
/*04b0*/ LDS.64 R10, [R9] ; /* 0x00000000090a7984 */
/* 0x000ea80000000a00 */
/*04c0*/ LDS R20, [R8+0x80] ; /* 0x0000800008147984 */
/* 0x000ee80000000800 */
/*04d0*/ LDS R23, [R8+0x100] ; /* 0x0001000008177984 */
/* 0x000fe80000000800 */
/*04e0*/ LDS.64 R18, [R9+0x8] ; /* 0x0000080009127984 */
/* 0x000f280000000a00 */
/*04f0*/ LDS R24, [R8+0x180] ; /* 0x0001800008187984 */
/* 0x000f620000000800 */
/*0500*/ FFMA R16, R22, R16, R21 ; /* 0x0000001016107223 */
/* 0x001fc60000000015 */
/*0510*/ LDS R22, [R8+0x280] ; /* 0x0002800008167984 */
/* 0x000fe20000000800 */
/*0520*/ FFMA R21, R25, R17, R16 ; /* 0x0000001119157223 */
/* 0x002fc60000000010 */
/*0530*/ LDS R25, [R8+0x200] ; /* 0x0002000008197984 */
/* 0x000fe80000000800 */
/*0540*/ LDS.64 R16, [R9+0x10] ; /* 0x0000100009107984 */
/* 0x000e220000000a00 */
/*0550*/ FFMA R10, R27, R10, R21 ; /* 0x0000000a1b0a7223 */
/* 0x004fc60000000015 */
/*0560*/ LDS R21, [R8+0x300] ; /* 0x0003000008157984 */
/* 0x000fe20000000800 */
/*0570*/ FFMA R26, R20, R11, R10 ; /* 0x0000000b141a7223 */
/* 0x008fc6000000000a */
/*0580*/ LDS.64 R10, [R9+0x18] ; /* 0x00001800090a7984 */
/* 0x000e680000000a00 */
/*0590*/ LDS R20, [R8+0x380] ; /* 0x0003800008147984 */
/* 0x000ea20000000800 */
/*05a0*/ FFMA R18, R23, R18, R26 ; /* 0x0000001217127223 */
/* 0x010fc6000000001a */
/*05b0*/ LDS R23, [R8+0x400] ; /* 0x0004000008177984 */
/* 0x000fe20000000800 */
/*05c0*/ FFMA R24, R24, R19, R18 ; /* 0x0000001318187223 */
/* 0x020fc60000000012 */
/*05d0*/ LDS.64 R18, [R9+0x20] ; /* 0x0000200009127984 */
/* 0x000ee20000000a00 */
/*05e0*/ FFMA R16, R25, R16, R24 ; /* 0x0000001019107223 */
/* 0x001fc60000000018 */
/*05f0*/ LDS R24, [R8+0x480] ; /* 0x0004800008187984 */
/* 0x000e220000000800 */
/*0600*/ FFMA R22, R22, R17, R16 ; /* 0x0000001116167223 */
/* 0x000fc60000000010 */
/*0610*/ LDS R25, [R8+0x500] ; /* 0x0005000008197984 */
/* 0x000fe20000000800 */
/*0620*/ FFMA R10, R21, R10, R22 ; /* 0x0000000a150a7223 */
/* 0x002fc60000000016 */
/*0630*/ LDS.64 R16, [R9+0x28] ; /* 0x0000280009107984 */
/* 0x000e620000000a00 */
/*0640*/ FFMA R26, R20, R11, R10 ; /* 0x0000000b141a7223 */
/* 0x004fc6000000000a */
/*0650*/ LDS R22, [R8+0x580] ; /* 0x0005800008167984 */
/* 0x000ea80000000800 */
/*0660*/ LDS R21, [R8+0x600] ; /* 0x0006000008157984 */
/* 0x000fe20000000800 */
/*0670*/ FFMA R18, R23, R18, R26 ; /* 0x0000001217127223 */
/* 0x008fc6000000001a */
/*0680*/ LDS.64 R10, [R9+0x30] ; /* 0x00003000090a7984 */
/* 0x0007280000000a00 */
/*0690*/ LDS R20, [R8+0x680] ; /* 0x0006800008147984 */
/* 0x000b220000000800 */
/*06a0*/ IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009097810 */
/* 0x008fe40007ffe0ff */
/*06b0*/ IADD3 R8, R8, 0x800, RZ ; /* 0x0000080008087810 */
/* 0x020fe20007ffe0ff */
/*06c0*/ FFMA R18, R24, R19, R18 ; /* 0x0000001318127223 */
/* 0x001fc80000000012 */
/*06d0*/ FFMA R16, R25, R16, R18 ; /* 0x0000001019107223 */
/* 0x002fc80000000012 */
/*06e0*/ FFMA R16, R22, R17, R16 ; /* 0x0000001116107223 */
/* 0x004fc80000000010 */
/*06f0*/ FFMA R21, R21, R10, R16 ; /* 0x0000000a15157223 */
/* 0x010fc80000000010 */
/*0700*/ FFMA R21, R20, R11, R21 ; /* 0x0000000b14157223 */
/* 0x000fe20000000015 */
/*0710*/ @P3 BRA 0x440 ; /* 0xfffffd2000003947 */
/* 0x000fea000383ffff */
/*0720*/ IADD3 R10, R15, -0x1, RZ ; /* 0xffffffff0f0a7810 */
/* 0x000fc80007ffe0ff */
/*0730*/ ISETP.GT.AND P3, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f64270 */
/*0740*/ @!P3 BRA 0x8e0 ; /* 0x000001900000b947 */
/* 0x000fea0003800000 */
/*0750*/ LDS R22, [R8+-0x100] ; /* 0xffff000008167984 */
/* 0x000fe20000000800 */
/*0760*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0770*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0780*/ IADD3 R15, R15, -0x8, RZ ; /* 0xfffffff80f0f7810 */
/* 0x000fe20007ffe0ff */
/*0790*/ LDS.64 R18, [R9+-0x8] ; /* 0xfffff80009127984 */
/* 0x000e280000000a00 */
/*07a0*/ LDS R24, [R8+-0x80] ; /* 0xffff800008187984 */
/* 0x000e680000000800 */
/*07b0*/ LDS R23, [R8] ; /* 0x0000000008177984 */
/* 0x000fe80000000800 */
/*07c0*/ LDS.64 R16, [R9] ; /* 0x0000000009107984 */
/* 0x000ea80000000a00 */
/*07d0*/ LDS R20, [R8+0x80] ; /* 0x0000800008147984 */
/* 0x000ee80000000800 */
/*07e0*/ LDS R25, [R8+0x100] ; /* 0x0001000008197984 */
/* 0x000fe80000000800 */
/*07f0*/ LDS.64 R10, [R9+0x8] ; /* 0x00000800090a7984 */
/* 0x000f220000000a00 */
/*0800*/ FFMA R18, R22, R18, R21 ; /* 0x0000001216127223 */
/* 0x001fc60000000015 */
/*0810*/ LDS R22, [R8+0x180] ; /* 0x0001800008167984 */
/* 0x000e220000000800 */
/*0820*/ FFMA R26, R24, R19, R18 ; /* 0x00000013181a7223 */
/* 0x002fc60000000012 */
/*0830*/ LDS R21, [R8+0x200] ; /* 0x0002000008157984 */
/* 0x000fe80000000800 */
/*0840*/ LDS.64 R18, [R9+0x10] ; /* 0x0000100009127984 */
/* 0x0003620000000a00 */
/*0850*/ FFMA R16, R23, R16, R26 ; /* 0x0000001017107223 */
/* 0x004fc6000000001a */
/*0860*/ LDS R24, [R8+0x280] ; /* 0x0002800008187984 */
/* 0x0005620000000800 */
/*0870*/ FFMA R16, R20, R17, R16 ; /* 0x0000001114107223 */
/* 0x008fe20000000010 */
/*0880*/ IADD3 R9, R9, 0x20, RZ ; /* 0x0000002009097810 */
/* 0x002fe40007ffe0ff */
/*0890*/ IADD3 R8, R8, 0x400, RZ ; /* 0x0000040008087810 */
/* 0x004fe20007ffe0ff */
/*08a0*/ FFMA R10, R25, R10, R16 ; /* 0x0000000a190a7223 */
/* 0x010fc80000000010 */
/*08b0*/ FFMA R10, R22, R11, R10 ; /* 0x0000000b160a7223 */
/* 0x001fc8000000000a */
/*08c0*/ FFMA R21, R21, R18, R10 ; /* 0x0000001215157223 */
/* 0x020fc8000000000a */
/*08d0*/ FFMA R21, R24, R19, R21 ; /* 0x0000001318157223 */
/* 0x000fe40000000015 */
/*08e0*/ ISETP.NE.OR P0, PT, R15, 0x1, P0 ; /* 0x000000010f00780c */
/* 0x000fda0000705670 */
/*08f0*/ @!P0 BRA 0xa00 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0900*/ LDS R18, [R8+-0x100] ; /* 0xffff000008127984 */
/* 0x000fe20000000800 */
/*0910*/ IADD3 R15, R15, -0x4, RZ ; /* 0xfffffffc0f0f7810 */
/* 0x000fe20007ffe0ff */
/*0920*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0930*/ LDS.64 R10, [R9+-0x8] ; /* 0xfffff800090a7984 */
/* 0x000e220000000a00 */
/*0940*/ ISETP.NE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fc60003f05270 */
/*0950*/ LDS R19, [R8+-0x80] ; /* 0xffff800008137984 */
/* 0x000e680000000800 */
/*0960*/ LDS R20, [R8] ; /* 0x0000000008147984 */
/* 0x000fe80000000800 */
/*0970*/ LDS.64 R16, [R9] ; /* 0x0000000009107984 */
/* 0x0004e80000000a00 */
/*0980*/ LDS R22, [R8+0x80] ; /* 0x0000800008167984 */
/* 0x0009620000000800 */
/*0990*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x004fc40007ffe0ff */
/*09a0*/ IADD3 R8, R8, 0x200, RZ ; /* 0x0000020008087810 */
/* 0x010fe20007ffe0ff */
/*09b0*/ FFMA R10, R18, R10, R21 ; /* 0x0000000a120a7223 */
/* 0x001fc80000000015 */
/*09c0*/ FFMA R11, R19, R11, R10 ; /* 0x0000000b130b7223 */
/* 0x002fc8000000000a */
/*09d0*/ FFMA R16, R20, R16, R11 ; /* 0x0000001014107223 */
/* 0x008fc8000000000b */
/*09e0*/ FFMA R21, R22, R17, R16 ; /* 0x0000001116157223 */
/* 0x020fe20000000010 */
/*09f0*/ @P0 BRA 0x900 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0a00*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fda0003f05270 */
/*0a10*/ @!P0 BRA 0xaf0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0a20*/ MOV R8, UR4 ; /* 0x0000000400087c02 */
/* 0x000fe20008000f00 */
/*0a30*/ ULEA UR6, UR4, 0x1000, 0x7 ; /* 0x0000100004067891 */
/* 0x000fe2000f8e383f */
/*0a40*/ ISETP.NE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fc60003f05270 */
/*0a50*/ IMAD R8, R8, 0x4, R5 ; /* 0x0000000408087824 */
/* 0x000fca00078e0205 */
/*0a60*/ LDS R15, [R2.X4+UR6] ; /* 0x00000006020f7984 */
/* 0x000fe80008004800 */
/*0a70*/ LDS.128 R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000c00 */
/*0a80*/ FFMA R21, R15, R8, R21 ; /* 0x000000080f157223 */
/* 0x001fe20000000015 */
/*0a90*/ @!P0 BRA 0xaf0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ ISETP.NE.AND P0, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fe20003f05270 */
/*0ab0*/ LDS R8, [R2.X4+UR6+0x80] ; /* 0x0000800602087984 */
/* 0x000e180008004800 */
/*0ac0*/ @P0 LDS R11, [R2.X4+UR6+0x100] ; /* 0x00010006020b0984 */
/* 0x000e620008004800 */
/*0ad0*/ FFMA R21, R8, R9, R21 ; /* 0x0000000908157223 */
/* 0x001fc80000000015 */
/*0ae0*/ @P0 FFMA R21, R11, R10, R21 ; /* 0x0000000a0b150223 */
/* 0x002fe40000000015 */
/*0af0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0b00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b10*/ @!P2 BRA 0x150 ; /* 0xfffff6300000a947 */
/* 0x000fea000383ffff */
/*0b20*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fc80003f06270 */
/*0b30*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0b40*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0b60*/ FMUL R21, R21, c[0x0][0x184] ; /* 0x0000610015157a20 */
/* 0x000fe40000400000 */
/*0b70*/ IMAD R3, R4, c[0x0][0x178], R3 ; /* 0x00005e0004037a24 */
/* 0x000fe400078e0203 */
/*0b80*/ FFMA R21, RZ, c[0x0][0x188], R21 ; /* 0x00006200ff157a23 */
/* 0x000fca0000000015 */
/*0b90*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0ba0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101908 */
/*0bb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bc0*/ BRA 0xbc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11sgemmKernelPfS_S_iiiff
.globl _Z11sgemmKernelPfS_S_iiiff
.p2align 8
.type _Z11sgemmKernelPfS_S_iiiff,@function
_Z11sgemmKernelPfS_S_iiiff:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x34
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v0, s14, 5, v3
v_lshl_add_u32 v1, s15, 5, v4
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s9, v1
s_cmp_eq_u32 s10, 0
s_cbranch_scc1 .LBB0_11
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s12, s[0:1], 0x20
v_lshlrev_b32_e32 v2, 2, v4
v_lshlrev_b32_e32 v5, 7, v3
s_and_b32 s13, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v6, 0x1000, v2
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v7, v5, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v8, v6, v5
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s11, s11, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_12
.LBB0_3:
s_lshl_b32 s14, s11, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, s14, v4
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s3, s12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, vcc_lo, s3
s_and_saveexec_b32 s15, s3
s_cbranch_execz .LBB0_5
v_mad_u64_u32 v[10:11], null, v9, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[9:10], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s3, s4, v9
v_add_co_ci_u32_e64 v10, s3, s5, v10, s3
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v9
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v9, s14, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s3, s12, v9
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s15, s3
s_cbranch_execz .LBB0_7
v_mad_u64_u32 v[10:11], null, v9, s9, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[9:10], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s3, s6, v9
v_add_co_ci_u32_e64 v10, s3, s7, v10, s3
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v9
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s15
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s13
s_cbranch_execz .LBB0_2
s_add_i32 s15, s14, 32
s_sub_i32 s14, s12, s14
s_cmp_ge_i32 s15, s12
s_cselect_b32 s14, s14, 32
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s14, 1
s_cbranch_scc1 .LBB0_2
v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v10, v5
s_mov_b32 s15, 0
.LBB0_10:
ds_load_b32 v11, v10
ds_load_b32 v12, v9
v_add_nc_u32_e32 v10, 4, v10
v_add_nc_u32_e32 v9, 0x80, v9
s_add_i32 s15, s15, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s15, s14
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v11, v12
s_cbranch_scc1 .LBB0_10
s_branch .LBB0_2
.LBB0_11:
v_mov_b32_e32 v2, 0
.LBB0_12:
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_14
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v2, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_fmac_f32_e64 v2, s3, 0
global_store_b32 v[0:1], v2, off
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11sgemmKernelPfS_S_iiiff
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11sgemmKernelPfS_S_iiiff, .Lfunc_end0-_Z11sgemmKernelPfS_S_iiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11sgemmKernelPfS_S_iiiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11sgemmKernelPfS_S_iiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include "../../include/layers/inner_product_layer.h"
//
//#include "../../include/util/math_function_ptr.h"
//
//namespace BigBang {
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Forward_GPU(const Tensor<dtype>* bottom, Tensor<dtype>* top) {
// bigbang_gpu_gemm<dtype>(false, false, bottom_row_, weights_column_, bottom_column_, 1.,
// bottom->gpu_data(), weights_->gpu_data(), 0., top->mutable_gpu_data());
//}
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Backward_GPU(const Tensor<dtype>* top, Tensor<dtype>* bottom) {
// const dtype* bottom_data = bottom->gpu_data();
// const dtype* top_diff_data = top->gpu_diff_data();
// //get the delta
// bigbang_gpu_gemm<dtype>(false, true, top_row_, weights_column, top_column_, 1., top_diff_data,
// weights_->gpu_data(), 0, bottom->mutable_gpu_diff_data());
// UpdateParams_GPU(bottom_data, top_diff_data);
//}
//
//template<typename dtype>
//void InnerProductLayer<dtype>::UpdateParams_GPU(const dtype* bottom_data, const dtype* delta) {
// //update the biases
// if (use_biases_) {
// dtype* biases_mutable_diff_data = biases_->mutable_gpu_data();
// bigbang_gpu_column_sum_plus(delta, bottom_row_, biases_row_, biases_mutable_diff_data);
// bigbang_gpu_minus(biases_->gpu_data(), biases_mutable_diff_data, biases_row_, alpha_ / bottom_row_,
// biases_->mutable_gpu_data());
// }
//
// //update the weights
// dtype* weights_diff_data = weights_->mutable_gpu_diff_data();
// cudaMemset(weights_diff_data, 0, sizeof(dtype)*weights_row_*weights_column_);
// /*bigbang_cpu_gemm(bottom_data, bottom_row_, bottom_column_, true, delta, top_row_, top_column_,
// false, alpha_ / bottom_row_, (dtype*)nullptr, 0, 0, false, weights_diff_data);*/
// bigbang_gpu_gemm<dtype>(true, false, bottom_row_, top_column_, bottom_column_, alpha_ / bottom_row_,
// bottom_data, delta, 0, weights_diff_data);
// bigbang_gpu_minus(weights_->gpu_data(), weights_diff_data, weights_row_*weights_column_,
// static_cast<dtype>(1.0), weights_->mutable_gpu_data());
//}
//
//
//
//} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include "../../include/layers/inner_product_layer.h"
//
//#include "../../include/util/math_function_ptr.h"
//
//namespace BigBang {
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Forward_GPU(const Tensor<dtype>* bottom, Tensor<dtype>* top) {
// bigbang_gpu_gemm<dtype>(false, false, bottom_row_, weights_column_, bottom_column_, 1.,
// bottom->gpu_data(), weights_->gpu_data(), 0., top->mutable_gpu_data());
//}
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Backward_GPU(const Tensor<dtype>* top, Tensor<dtype>* bottom) {
// const dtype* bottom_data = bottom->gpu_data();
// const dtype* top_diff_data = top->gpu_diff_data();
// //get the delta
// bigbang_gpu_gemm<dtype>(false, true, top_row_, weights_column, top_column_, 1., top_diff_data,
// weights_->gpu_data(), 0, bottom->mutable_gpu_diff_data());
// UpdateParams_GPU(bottom_data, top_diff_data);
//}
//
//template<typename dtype>
//void InnerProductLayer<dtype>::UpdateParams_GPU(const dtype* bottom_data, const dtype* delta) {
// //update the biases
// if (use_biases_) {
// dtype* biases_mutable_diff_data = biases_->mutable_gpu_data();
// bigbang_gpu_column_sum_plus(delta, bottom_row_, biases_row_, biases_mutable_diff_data);
// bigbang_gpu_minus(biases_->gpu_data(), biases_mutable_diff_data, biases_row_, alpha_ / bottom_row_,
// biases_->mutable_gpu_data());
// }
//
// //update the weights
// dtype* weights_diff_data = weights_->mutable_gpu_diff_data();
// cudaMemset(weights_diff_data, 0, sizeof(dtype)*weights_row_*weights_column_);
// /*bigbang_cpu_gemm(bottom_data, bottom_row_, bottom_column_, true, delta, top_row_, top_column_,
// false, alpha_ / bottom_row_, (dtype*)nullptr, 0, 0, false, weights_diff_data);*/
// bigbang_gpu_gemm<dtype>(true, false, bottom_row_, top_column_, bottom_column_, alpha_ / bottom_row_,
// bottom_data, delta, 0, weights_diff_data);
// bigbang_gpu_minus(weights_->gpu_data(), weights_diff_data, weights_row_*weights_column_,
// static_cast<dtype>(1.0), weights_->mutable_gpu_data());
//}
//
//
//
//} | .file "tmpxft_001151a9_00000000-6_inner_product_layer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include "../../include/layers/inner_product_layer.h"
//
//#include "../../include/util/math_function_ptr.h"
//
//namespace BigBang {
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Forward_GPU(const Tensor<dtype>* bottom, Tensor<dtype>* top) {
// bigbang_gpu_gemm<dtype>(false, false, bottom_row_, weights_column_, bottom_column_, 1.,
// bottom->gpu_data(), weights_->gpu_data(), 0., top->mutable_gpu_data());
//}
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Backward_GPU(const Tensor<dtype>* top, Tensor<dtype>* bottom) {
// const dtype* bottom_data = bottom->gpu_data();
// const dtype* top_diff_data = top->gpu_diff_data();
// //get the delta
// bigbang_gpu_gemm<dtype>(false, true, top_row_, weights_column, top_column_, 1., top_diff_data,
// weights_->gpu_data(), 0, bottom->mutable_gpu_diff_data());
// UpdateParams_GPU(bottom_data, top_diff_data);
//}
//
//template<typename dtype>
//void InnerProductLayer<dtype>::UpdateParams_GPU(const dtype* bottom_data, const dtype* delta) {
// //update the biases
// if (use_biases_) {
// dtype* biases_mutable_diff_data = biases_->mutable_gpu_data();
// bigbang_gpu_column_sum_plus(delta, bottom_row_, biases_row_, biases_mutable_diff_data);
// bigbang_gpu_minus(biases_->gpu_data(), biases_mutable_diff_data, biases_row_, alpha_ / bottom_row_,
// biases_->mutable_gpu_data());
// }
//
// //update the weights
// dtype* weights_diff_data = weights_->mutable_gpu_diff_data();
// cudaMemset(weights_diff_data, 0, sizeof(dtype)*weights_row_*weights_column_);
// /*bigbang_cpu_gemm(bottom_data, bottom_row_, bottom_column_, true, delta, top_row_, top_column_,
// false, alpha_ / bottom_row_, (dtype*)nullptr, 0, 0, false, weights_diff_data);*/
// bigbang_gpu_gemm<dtype>(true, false, bottom_row_, top_column_, bottom_column_, alpha_ / bottom_row_,
// bottom_data, delta, 0, weights_diff_data);
// bigbang_gpu_minus(weights_->gpu_data(), weights_diff_data, weights_row_*weights_column_,
// static_cast<dtype>(1.0), weights_->mutable_gpu_data());
//}
//
//
//
//} | #include <hip/hip_runtime.h>
//#include "../../include/layers/inner_product_layer.h"
//
//#include "../../include/util/math_function_ptr.h"
//
//namespace BigBang {
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Forward_GPU(const Tensor<dtype>* bottom, Tensor<dtype>* top) {
// bigbang_gpu_gemm<dtype>(false, false, bottom_row_, weights_column_, bottom_column_, 1.,
// bottom->gpu_data(), weights_->gpu_data(), 0., top->mutable_gpu_data());
//}
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Backward_GPU(const Tensor<dtype>* top, Tensor<dtype>* bottom) {
// const dtype* bottom_data = bottom->gpu_data();
// const dtype* top_diff_data = top->gpu_diff_data();
// //get the delta
// bigbang_gpu_gemm<dtype>(false, true, top_row_, weights_column, top_column_, 1., top_diff_data,
// weights_->gpu_data(), 0, bottom->mutable_gpu_diff_data());
// UpdateParams_GPU(bottom_data, top_diff_data);
//}
//
//template<typename dtype>
//void InnerProductLayer<dtype>::UpdateParams_GPU(const dtype* bottom_data, const dtype* delta) {
// //update the biases
// if (use_biases_) {
// dtype* biases_mutable_diff_data = biases_->mutable_gpu_data();
// bigbang_gpu_column_sum_plus(delta, bottom_row_, biases_row_, biases_mutable_diff_data);
// bigbang_gpu_minus(biases_->gpu_data(), biases_mutable_diff_data, biases_row_, alpha_ / bottom_row_,
// biases_->mutable_gpu_data());
// }
//
// //update the weights
// dtype* weights_diff_data = weights_->mutable_gpu_diff_data();
// cudaMemset(weights_diff_data, 0, sizeof(dtype)*weights_row_*weights_column_);
// /*bigbang_cpu_gemm(bottom_data, bottom_row_, bottom_column_, true, delta, top_row_, top_column_,
// false, alpha_ / bottom_row_, (dtype*)nullptr, 0, 0, false, weights_diff_data);*/
// bigbang_gpu_gemm<dtype>(true, false, bottom_row_, top_column_, bottom_column_, alpha_ / bottom_row_,
// bottom_data, delta, 0, weights_diff_data);
// bigbang_gpu_minus(weights_->gpu_data(), weights_diff_data, weights_row_*weights_column_,
// static_cast<dtype>(1.0), weights_->mutable_gpu_data());
//}
//
//
//
//} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#include "../../include/layers/inner_product_layer.h"
//
//#include "../../include/util/math_function_ptr.h"
//
//namespace BigBang {
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Forward_GPU(const Tensor<dtype>* bottom, Tensor<dtype>* top) {
// bigbang_gpu_gemm<dtype>(false, false, bottom_row_, weights_column_, bottom_column_, 1.,
// bottom->gpu_data(), weights_->gpu_data(), 0., top->mutable_gpu_data());
//}
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Backward_GPU(const Tensor<dtype>* top, Tensor<dtype>* bottom) {
// const dtype* bottom_data = bottom->gpu_data();
// const dtype* top_diff_data = top->gpu_diff_data();
// //get the delta
// bigbang_gpu_gemm<dtype>(false, true, top_row_, weights_column, top_column_, 1., top_diff_data,
// weights_->gpu_data(), 0, bottom->mutable_gpu_diff_data());
// UpdateParams_GPU(bottom_data, top_diff_data);
//}
//
//template<typename dtype>
//void InnerProductLayer<dtype>::UpdateParams_GPU(const dtype* bottom_data, const dtype* delta) {
// //update the biases
// if (use_biases_) {
// dtype* biases_mutable_diff_data = biases_->mutable_gpu_data();
// bigbang_gpu_column_sum_plus(delta, bottom_row_, biases_row_, biases_mutable_diff_data);
// bigbang_gpu_minus(biases_->gpu_data(), biases_mutable_diff_data, biases_row_, alpha_ / bottom_row_,
// biases_->mutable_gpu_data());
// }
//
// //update the weights
// dtype* weights_diff_data = weights_->mutable_gpu_diff_data();
// cudaMemset(weights_diff_data, 0, sizeof(dtype)*weights_row_*weights_column_);
// /*bigbang_cpu_gemm(bottom_data, bottom_row_, bottom_column_, true, delta, top_row_, top_column_,
// false, alpha_ / bottom_row_, (dtype*)nullptr, 0, 0, false, weights_diff_data);*/
// bigbang_gpu_gemm<dtype>(true, false, bottom_row_, top_column_, bottom_column_, alpha_ / bottom_row_,
// bottom_data, delta, 0, weights_diff_data);
// bigbang_gpu_minus(weights_->gpu_data(), weights_diff_data, weights_row_*weights_column_,
// static_cast<dtype>(1.0), weights_->mutable_gpu_data());
//}
//
//
//
//} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#include "../../include/layers/inner_product_layer.h"
//
//#include "../../include/util/math_function_ptr.h"
//
//namespace BigBang {
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Forward_GPU(const Tensor<dtype>* bottom, Tensor<dtype>* top) {
// bigbang_gpu_gemm<dtype>(false, false, bottom_row_, weights_column_, bottom_column_, 1.,
// bottom->gpu_data(), weights_->gpu_data(), 0., top->mutable_gpu_data());
//}
//
//template<typename dtype>
//void InnerProductLayer<dtype>::Backward_GPU(const Tensor<dtype>* top, Tensor<dtype>* bottom) {
// const dtype* bottom_data = bottom->gpu_data();
// const dtype* top_diff_data = top->gpu_diff_data();
// //get the delta
// bigbang_gpu_gemm<dtype>(false, true, top_row_, weights_column, top_column_, 1., top_diff_data,
// weights_->gpu_data(), 0, bottom->mutable_gpu_diff_data());
// UpdateParams_GPU(bottom_data, top_diff_data);
//}
//
//template<typename dtype>
//void InnerProductLayer<dtype>::UpdateParams_GPU(const dtype* bottom_data, const dtype* delta) {
// //update the biases
// if (use_biases_) {
// dtype* biases_mutable_diff_data = biases_->mutable_gpu_data();
// bigbang_gpu_column_sum_plus(delta, bottom_row_, biases_row_, biases_mutable_diff_data);
// bigbang_gpu_minus(biases_->gpu_data(), biases_mutable_diff_data, biases_row_, alpha_ / bottom_row_,
// biases_->mutable_gpu_data());
// }
//
// //update the weights
// dtype* weights_diff_data = weights_->mutable_gpu_diff_data();
// cudaMemset(weights_diff_data, 0, sizeof(dtype)*weights_row_*weights_column_);
// /*bigbang_cpu_gemm(bottom_data, bottom_row_, bottom_column_, true, delta, top_row_, top_column_,
// false, alpha_ / bottom_row_, (dtype*)nullptr, 0, 0, false, weights_diff_data);*/
// bigbang_gpu_gemm<dtype>(true, false, bottom_row_, top_column_, bottom_column_, alpha_ / bottom_row_,
// bottom_data, delta, 0, weights_diff_data);
// bigbang_gpu_minus(weights_->gpu_data(), weights_diff_data, weights_row_*weights_column_,
// static_cast<dtype>(1.0), weights_->mutable_gpu_data());
//}
//
//
//
//} | .text
.file "inner_product_layer.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001151a9_00000000-6_inner_product_layer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "inner_product_layer.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void f(int * A, int *B) {
int tid = threadIdx.x;
int diff = (B - A);
int x = B[tid];
int y = A[tid + diff - 1];
B[tid] = x + y;
} | code for sm_80
Function : _Z1fPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ MOV R3, c[0x0][0x168] ; /* 0x00005a0000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff007624 */
/* 0x000fe200078e00ff */
/*0040*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IADD3 R3, P0, R3, -c[0x0][0x160], RZ ; /* 0x8000580003037a10 */
/* 0x000fc80007f1e0ff */
/*0070*/ IADD3.X R0, R0, ~c[0x0][0x164], RZ, P0, !PT ; /* 0x8000590000007a10 */
/* 0x000fc800007fe4ff */
/*0080*/ SHF.R.U64 R3, R3, 0x2, R0 ; /* 0x0000000203037819 */
/* 0x000fc80000001200 */
/*0090*/ IADD3 R4, R2.reuse, -0x1, R3 ; /* 0xffffffff02047810 */
/* 0x041fe20007ffe003 */
/*00a0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000eaa000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ IMAD.IADD R7, R0, 0x1, R5 ; /* 0x0000000100077824 */
/* 0x004fca00078e0205 */
/*00f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void f(int * A, int *B) {
int tid = threadIdx.x;
int diff = (B - A);
int x = B[tid];
int y = A[tid + diff - 1];
B[tid] = x + y;
} | .file "tmpxft_00045e9a_00000000-6_new_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z1fPiS_PiS_
.type _Z22__device_stub__Z1fPiS_PiS_, @function
_Z22__device_stub__Z1fPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z1fPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z22__device_stub__Z1fPiS_PiS_, .-_Z22__device_stub__Z1fPiS_PiS_
.globl _Z1fPiS_
.type _Z1fPiS_, @function
_Z1fPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z1fPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z1fPiS_, .-_Z1fPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1fPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1fPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void f(int * A, int *B) {
int tid = threadIdx.x;
int diff = (B - A);
int x = B[tid];
int y = A[tid + diff - 1];
B[tid] = x + y;
} | #include <hip/hip_runtime.h>
__global__ void f(int * A, int *B) {
int tid = threadIdx.x;
int diff = (B - A);
int x = B[tid];
int y = A[tid + diff - 1];
B[tid] = x + y;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void f(int * A, int *B) {
int tid = threadIdx.x;
int diff = (B - A);
int x = B[tid];
int y = A[tid + diff - 1];
B[tid] = x + y;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1fPiS_
.globl _Z1fPiS_
.p2align 8
.type _Z1fPiS_,@function
_Z1fPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_sub_u32 s4, s2, s0
s_subb_u32 s5, s3, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_alignbit_b32 v1, s5, s4, 2
v_add_nc_u32_e32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v3, s[2:3]
global_load_b32 v0, v[0:1], off offset:-4
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v2
global_store_b32 v3, v0, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1fPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1fPiS_, .Lfunc_end0-_Z1fPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1fPiS_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z1fPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void f(int * A, int *B) {
int tid = threadIdx.x;
int diff = (B - A);
int x = B[tid];
int y = A[tid + diff - 1];
B[tid] = x + y;
} | .text
.file "new_test.hip"
.globl _Z16__device_stub__fPiS_ # -- Begin function _Z16__device_stub__fPiS_
.p2align 4, 0x90
.type _Z16__device_stub__fPiS_,@function
_Z16__device_stub__fPiS_: # @_Z16__device_stub__fPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z1fPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z16__device_stub__fPiS_, .Lfunc_end0-_Z16__device_stub__fPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1fPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1fPiS_,@object # @_Z1fPiS_
.section .rodata,"a",@progbits
.globl _Z1fPiS_
.p2align 3, 0x0
_Z1fPiS_:
.quad _Z16__device_stub__fPiS_
.size _Z1fPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1fPiS_"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__fPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1fPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z1fPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ MOV R3, c[0x0][0x168] ; /* 0x00005a0000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff007624 */
/* 0x000fe200078e00ff */
/*0040*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0060*/ IADD3 R3, P0, R3, -c[0x0][0x160], RZ ; /* 0x8000580003037a10 */
/* 0x000fc80007f1e0ff */
/*0070*/ IADD3.X R0, R0, ~c[0x0][0x164], RZ, P0, !PT ; /* 0x8000590000007a10 */
/* 0x000fc800007fe4ff */
/*0080*/ SHF.R.U64 R3, R3, 0x2, R0 ; /* 0x0000000203037819 */
/* 0x000fc80000001200 */
/*0090*/ IADD3 R4, R2.reuse, -0x1, R3 ; /* 0xffffffff02047810 */
/* 0x041fe20007ffe003 */
/*00a0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000eaa000c1e1900 */
/*00d0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ IMAD.IADD R7, R0, 0x1, R5 ; /* 0x0000000100077824 */
/* 0x004fca00078e0205 */
/*00f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1fPiS_
.globl _Z1fPiS_
.p2align 8
.type _Z1fPiS_,@function
_Z1fPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_sub_u32 s4, s2, s0
s_subb_u32 s5, s3, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_alignbit_b32 v1, s5, s4, 2
v_add_nc_u32_e32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_load_b32 v2, v3, s[2:3]
global_load_b32 v0, v[0:1], off offset:-4
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v2
global_store_b32 v3, v0, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1fPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1fPiS_, .Lfunc_end0-_Z1fPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1fPiS_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z1fPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00045e9a_00000000-6_new_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z1fPiS_PiS_
.type _Z22__device_stub__Z1fPiS_PiS_, @function
_Z22__device_stub__Z1fPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z1fPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z22__device_stub__Z1fPiS_PiS_, .-_Z22__device_stub__Z1fPiS_PiS_
.globl _Z1fPiS_
.type _Z1fPiS_, @function
_Z1fPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z1fPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z1fPiS_, .-_Z1fPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1fPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1fPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "new_test.hip"
.globl _Z16__device_stub__fPiS_ # -- Begin function _Z16__device_stub__fPiS_
.p2align 4, 0x90
.type _Z16__device_stub__fPiS_,@function
_Z16__device_stub__fPiS_: # @_Z16__device_stub__fPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z1fPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z16__device_stub__fPiS_, .Lfunc_end0-_Z16__device_stub__fPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1fPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1fPiS_,@object # @_Z1fPiS_
.section .rodata,"a",@progbits
.globl _Z1fPiS_
.p2align 3, 0x0
_Z1fPiS_:
.quad _Z16__device_stub__fPiS_
.size _Z1fPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1fPiS_"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__fPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1fPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void computeSquare(int *d_in, int *d_out) {
int index = threadIdx.x;
d_out[index] = d_in[index] * d_in[index];
} | code for sm_80
Function : _Z13computeSquarePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD R7, R2, R2, RZ ; /* 0x0000000202077224 */
/* 0x004fca00078e02ff */
/*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void computeSquare(int *d_in, int *d_out) {
int index = threadIdx.x;
d_out[index] = d_in[index] * d_in[index];
} | .file "tmpxft_001b0173_00000000-6_computeSquare.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13computeSquarePiS_PiS_
.type _Z35__device_stub__Z13computeSquarePiS_PiS_, @function
_Z35__device_stub__Z13computeSquarePiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13computeSquarePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z13computeSquarePiS_PiS_, .-_Z35__device_stub__Z13computeSquarePiS_PiS_
.globl _Z13computeSquarePiS_
.type _Z13computeSquarePiS_, @function
_Z13computeSquarePiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13computeSquarePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13computeSquarePiS_, .-_Z13computeSquarePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13computeSquarePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13computeSquarePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void computeSquare(int *d_in, int *d_out) {
int index = threadIdx.x;
d_out[index] = d_in[index] * d_in[index];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeSquare(int *d_in, int *d_out) {
int index = threadIdx.x;
d_out[index] = d_in[index] * d_in[index];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeSquare(int *d_in, int *d_out) {
int index = threadIdx.x;
d_out[index] = d_in[index] * d_in[index];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13computeSquarePiS_
.globl _Z13computeSquarePiS_
.p2align 8
.type _Z13computeSquarePiS_,@function
_Z13computeSquarePiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13computeSquarePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13computeSquarePiS_, .Lfunc_end0-_Z13computeSquarePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13computeSquarePiS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z13computeSquarePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void computeSquare(int *d_in, int *d_out) {
int index = threadIdx.x;
d_out[index] = d_in[index] * d_in[index];
} | .text
.file "computeSquare.hip"
.globl _Z28__device_stub__computeSquarePiS_ # -- Begin function _Z28__device_stub__computeSquarePiS_
.p2align 4, 0x90
.type _Z28__device_stub__computeSquarePiS_,@function
_Z28__device_stub__computeSquarePiS_: # @_Z28__device_stub__computeSquarePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13computeSquarePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__computeSquarePiS_, .Lfunc_end0-_Z28__device_stub__computeSquarePiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13computeSquarePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13computeSquarePiS_,@object # @_Z13computeSquarePiS_
.section .rodata,"a",@progbits
.globl _Z13computeSquarePiS_
.p2align 3, 0x0
_Z13computeSquarePiS_:
.quad _Z28__device_stub__computeSquarePiS_
.size _Z13computeSquarePiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13computeSquarePiS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__computeSquarePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13computeSquarePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13computeSquarePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD R7, R2, R2, RZ ; /* 0x0000000202077224 */
/* 0x004fca00078e02ff */
/*0080*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13computeSquarePiS_
.globl _Z13computeSquarePiS_
.p2align 8
.type _Z13computeSquarePiS_,@function
_Z13computeSquarePiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v1
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13computeSquarePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13computeSquarePiS_, .Lfunc_end0-_Z13computeSquarePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13computeSquarePiS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z13computeSquarePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b0173_00000000-6_computeSquare.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13computeSquarePiS_PiS_
.type _Z35__device_stub__Z13computeSquarePiS_PiS_, @function
_Z35__device_stub__Z13computeSquarePiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13computeSquarePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z13computeSquarePiS_PiS_, .-_Z35__device_stub__Z13computeSquarePiS_PiS_
.globl _Z13computeSquarePiS_
.type _Z13computeSquarePiS_, @function
_Z13computeSquarePiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13computeSquarePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13computeSquarePiS_, .-_Z13computeSquarePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13computeSquarePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13computeSquarePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "computeSquare.hip"
.globl _Z28__device_stub__computeSquarePiS_ # -- Begin function _Z28__device_stub__computeSquarePiS_
.p2align 4, 0x90
.type _Z28__device_stub__computeSquarePiS_,@function
_Z28__device_stub__computeSquarePiS_: # @_Z28__device_stub__computeSquarePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13computeSquarePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__computeSquarePiS_, .Lfunc_end0-_Z28__device_stub__computeSquarePiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13computeSquarePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13computeSquarePiS_,@object # @_Z13computeSquarePiS_
.section .rodata,"a",@progbits
.globl _Z13computeSquarePiS_
.p2align 3, 0x0
_Z13computeSquarePiS_:
.quad _Z28__device_stub__computeSquarePiS_
.size _Z13computeSquarePiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13computeSquarePiS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__computeSquarePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13computeSquarePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#define KERNEL_SIZE 3
#define BLOCK_SIZE 512
typedef signed int pixel_channel;
typedef unsigned long resolution;
__constant__ pixel_channel kernel_cuda[KERNEL_SIZE * KERNEL_SIZE];
pixel_channel kernel_host[KERNEL_SIZE * KERNEL_SIZE] = { -1, -1, -1,
-1, 9, -1,
-1, -1, -1 };
__global__ void Pixel_Shared_Convolution(pixel_channel *channel_cuda, pixel_channel *rezult_cuda, resolution width, resolution lineQuantity)
{
__shared__ pixel_channel sharedMemory [3][BLOCK_SIZE + 2];
for(long line = 1; line < lineQuantity; line++)
{
long temp = blockIdx.x * BLOCK_SIZE + threadIdx.x;
sharedMemory [0][threadIdx.x + 1] = channel_cuda[temp + width * (line - 1)];
sharedMemory [1][threadIdx.x + 1] = channel_cuda[temp + width * line];
sharedMemory [2][threadIdx.x + 1] = channel_cuda[temp + width * (line + 1)];
if(threadIdx.x == 0)
{
if(blockIdx.x != 0)
temp--;
sharedMemory [0][0] = channel_cuda[temp + width * (line-1)];
sharedMemory [1][0] = channel_cuda[temp + width * line];
sharedMemory [2][0] = channel_cuda[temp + width * (line+1)];
}
if(threadIdx.x == (BLOCK_SIZE - 1))
{
temp++;
sharedMemory [0][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line - 1)];
sharedMemory [1][BLOCK_SIZE + 1] = channel_cuda[temp + width * line];
sharedMemory [2][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line + 1)];
}
__syncthreads();
long Sum = 0;
for (int i = 0; i < KERNEL_SIZE; i++)
for (int j = 0; j < KERNEL_SIZE; j++)
Sum += sharedMemory[j][threadIdx.x + i] * kernel_cuda[i * 3 + j];
if (Sum < 0)
Sum = 0;
if (Sum > 255)
Sum = 255;
__syncthreads();
if((blockIdx.x * BLOCK_SIZE + threadIdx.x) > width)
continue;
rezult_cuda[blockIdx.x * BLOCK_SIZE + threadIdx.x + width * line] = Sum;
}
__syncthreads();
return;
}
extern "C" __host__ pixel_channel** asyncConvolution(pixel_channel **image, resolution width, resolution height)
{
pixel_channel **channel_cuda;
channel_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));
pixel_channel **rezult_cuda;
rezult_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));
resolution size = width * height;
cudaHostRegister(image[0], (size + BLOCK_SIZE) * sizeof(pixel_channel), cudaHostRegisterMapped);
cudaHostRegister(image[1], (size + BLOCK_SIZE) * sizeof(pixel_channel), cudaHostRegisterMapped);
cudaHostRegister(image[2], (size + BLOCK_SIZE) * sizeof(pixel_channel), cudaHostRegisterMapped);
cudaMalloc((void **)& rezult_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMalloc((void **)& rezult_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMalloc((void **)& rezult_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMalloc((void **)& channel_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));;
cudaMalloc((void **)& channel_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMalloc((void **)& channel_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMemcpyToSymbol(kernel_cuda, kernel_host, 9 * sizeof(pixel_channel), 0, cudaMemcpyHostToDevice);
resolution block_count = 0;
if(((width - 2)%BLOCK_SIZE) == 0)
block_count = (width - 2)/BLOCK_SIZE;
else
block_count = (width - 2)/BLOCK_SIZE + 1;
dim3 gridSize = dim3(block_count, 1, 1);
dim3 blockSize = dim3(BLOCK_SIZE, 1, 1);
cudaStream_t stream[3];
for(int i = 0; i < 3; i++)
{
cudaStreamCreate(&stream[i]);
cudaMemcpyAsync(channel_cuda[i], image[i], size*sizeof(pixel_channel), cudaMemcpyHostToDevice, stream[i]);
Pixel_Shared_Convolution<<<gridSize, blockSize, 0, stream[i]>>>(channel_cuda[i], rezult_cuda[i], width, height);
cudaMemcpyAsync(image[i], rezult_cuda[i], size*sizeof(pixel_channel), cudaMemcpyDeviceToHost,stream[i]);
cudaStreamDestroy(stream[i]);
}
for(int i=0;i<3;i++)
{
cudaFree(rezult_cuda[i]);
cudaFree(channel_cuda[i]);
}
cudaDeviceReset();
return image;
} | code for sm_80
Function : _Z24Pixel_Shared_ConvolutionPiS_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe400078e00ff */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x000fc600078e00ff */
/*0030*/ ISETP.GE.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fc80003f06070 */
/*0040*/ ISETP.GE.U32.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0003f06100 */
/*0050*/ @!P0 BRA 0x860 ; /* 0x0000080000008947 */
/* 0x000fea0003800000 */
/*0060*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0070*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0090*/ USHF.L.U32 UR7, UR4, 0x2, URZ ; /* 0x0000000204077899 */
/* 0x000fe2000800063f */
/*00a0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00b0*/ UMOV UR8, 0x2 ; /* 0x0000000200087882 */
/* 0x000fe20000000000 */
/*00c0*/ IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; /* 0x00000001ff167424 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR10, c[0x0][0x168] ; /* 0x00005a00000a7ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e00ff */
/*00f0*/ USHF.L.U64.HI UR8, UR4, UR8, UR5 ; /* 0x0000000804087299 */
/* 0x000fe40008010205 */
/*0100*/ UIADD3 UR5, UP0, UR7, UR10, URZ ; /* 0x0000000a07057290 */
/* 0x000fc4000ff1e03f */
/*0110*/ UMOV UR9, 0x4 ; /* 0x0000000400097882 */
/* 0x000fe40000000000 */
/*0120*/ UIADD3.X UR6, UR8, UR11, URZ, UP0, !UPT ; /* 0x0000000b08067290 */
/* 0x000fe400087fe43f */
/*0130*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0140*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0150*/ ISETP.NE.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720c */
/* 0x041fe20003f05270 */
/*0160*/ IMAD R18, R3, 0x200, R0 ; /* 0x0000020003127824 */
/* 0x002fc600078e0200 */
/*0170*/ SEL R5, RZ, 0xffffffff, !P0 ; /* 0xffffffffff057807 */
/* 0x000fe20004000000 */
/*0180*/ IMAD.WIDE.U32 R20, R18, 0x4, RZ ; /* 0x0000000412147825 */
/* 0x000fc600078e00ff */
/*0190*/ IADD3 R24, P0, R18, R5, RZ ; /* 0x0000000512187210 */
/* 0x000fe20007f1e0ff */
/*01a0*/ IMAD.MOV.U32 R19, RZ, RZ, R20 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0014 */
/*01b0*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0202 */
/*01c0*/ IMAD.X R20, RZ, RZ, R5, P0 ; /* 0x000000ffff147224 */
/* 0x000fe400000e0605 */
/*01d0*/ ISETP.NE.AND P1, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f25270 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0012 */
/*01f0*/ ISETP.NE.AND P0, PT, R0, 0x1ff, PT ; /* 0x000001ff0000780c */
/* 0x000fe20003f05270 */
/*0200*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0210*/ IADD3 R12, P2, R19, c[0x0][0x160], RZ ; /* 0x00005800130c7a10 */
/* 0x000fc80007f5e0ff */
/*0220*/ IADD3.X R13, R21, c[0x0][0x164], RZ, P2, !PT ; /* 0x00005900150d7a10 */
/* 0x000fe400017fe4ff */
/*0230*/ IADD3 R14, P3, R12, UR7, RZ ; /* 0x000000070c0e7c10 */
/* 0x000fc6000ff7e0ff */
/*0240*/ @!P1 IMAD.MOV.U32 R4, RZ, RZ, R24 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0018 */
/*0250*/ @!P1 IADD3 R16, P2, R2, R19, RZ ; /* 0x0000001302109210 */
/* 0x000fe20007f5e0ff */
/*0260*/ @!P1 IMAD.MOV.U32 R9, RZ, RZ, R20 ; /* 0x000000ffff099224 */
/* 0x000fe200078e0014 */
/*0270*/ IADD3.X R15, R13, UR8, RZ, P3, !PT ; /* 0x000000080d0f7c10 */
/* 0x000fe20009ffe4ff */
/*0280*/ LDG.E R23, [R12.64] ; /* 0x0000000a0c177981 */
/* 0x0000a2000c1e1900 */
/*0290*/ @!P0 LEA R8, P4, R4.reuse, UR9, 0x2 ; /* 0x0000000904088c11 */
/* 0x040fe2000f8810ff */
/*02a0*/ @!P1 IMAD.X R17, R3, 0x1, R21, P2 ; /* 0x0000000103119824 */
/* 0x000fe400010e0615 */
/*02b0*/ LDG.E R25, [R14.64] ; /* 0x0000000a0e197981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ @!P0 LEA.HI.X R9, R4, UR4, R9, 0x2, P4 ; /* 0x0000000404098c11 */
/* 0x000fe4000a0f1409 */
/*02d0*/ IADD3 R4, P3, R14, UR7, RZ ; /* 0x000000070e047c10 */
/* 0x000fc4000ff7e0ff */
/*02e0*/ @!P1 IADD3 R6, P2, R16, UR7, RZ ; /* 0x0000000710069c10 */
/* 0x000fe4000ff5e0ff */
/*02f0*/ IADD3.X R5, R15, UR8, RZ, P3, !PT ; /* 0x000000080f057c10 */
/* 0x000fe20009ffe4ff */
/*0300*/ @!P1 LDG.E R16, [R16.64] ; /* 0x0000000a10109981 */
/* 0x000f22000c1e1900 */
/*0310*/ @!P0 IADD3 R8, P3, R8, c[0x0][0x160], RZ ; /* 0x0000580008088a10 */
/* 0x000fe40007f7e0ff */
/*0320*/ @!P1 IADD3.X R7, R17, UR8, RZ, P2, !PT ; /* 0x0000000811079c10 */
/* 0x000fe400097fe4ff */
/*0330*/ @!P1 IADD3 R10, P2, R6, UR7, RZ ; /* 0x00000007060a9c10 */
/* 0x000fe2000ff5e0ff */
/*0340*/ LDG.E R5, [R4.64] ; /* 0x0000000a04057981 */
/* 0x000f62000c1e1900 */
/*0350*/ @!P0 IADD3.X R9, R9, c[0x0][0x164], RZ, P3, !PT ; /* 0x0000590009098a10 */
/* 0x000fc40001ffe4ff */
/*0360*/ @!P0 IADD3 R12, P3, R8, UR7, RZ ; /* 0x00000007080c8c10 */
/* 0x001fe2000ff7e0ff */
/*0370*/ @!P1 LDG.E R6, [R6.64] ; /* 0x0000000a06069981 */
/* 0x000f22000c1e1900 */
/*0380*/ @!P1 IADD3.X R11, R7, UR8, RZ, P2, !PT ; /* 0x00000008070b9c10 */
/* 0x000fe400097fe4ff */
/*0390*/ @!P0 IADD3.X R13, R9, UR8, RZ, P3, !PT ; /* 0x00000008090d8c10 */
/* 0x000fe20009ffe4ff */
/*03a0*/ @!P0 LDG.E R8, [R8.64] ; /* 0x0000000a08088981 */
/* 0x000f22000c1e1900 */
/*03b0*/ @!P0 IADD3 R14, P2, R12, UR7, RZ ; /* 0x000000070c0e8c10 */
/* 0x002fc6000ff5e0ff */
/*03c0*/ @!P1 LDG.E R10, [R10.64] ; /* 0x0000000a0a0a9981 */
/* 0x000f22000c1e1900 */
/*03d0*/ @!P0 IADD3.X R15, R13, UR8, RZ, P2, !PT ; /* 0x000000080d0f8c10 */
/* 0x000fc600097fe4ff */
/*03e0*/ @!P0 LDG.E R12, [R12.64] ; /* 0x0000000a0c0c8981 */
/* 0x000f28000c1e1900 */
/*03f0*/ @!P0 LDG.E R14, [R14.64] ; /* 0x0000000a0e0e8981 */
/* 0x000f22000c1e1900 */
/*0400*/ IADD3 R22, P2, R22, 0x1, RZ ; /* 0x0000000116167810 */
/* 0x000fe20007f5e0ff */
/*0410*/ BSSY B0, 0x800 ; /* 0x000003e000007945 */
/* 0x000fe80003800000 */
/*0420*/ IMAD.X R26, RZ, RZ, R26, P2 ; /* 0x000000ffff1a7224 */
/* 0x000fe200010e061a */
/*0430*/ STS [R0.X4+0x4], R23 ; /* 0x0000041700007388 */
/* 0x004fe80000004800 */
/*0440*/ STS [R0.X4+0x80c], R25 ; /* 0x00080c1900007388 */
/* 0x008fe80000004800 */
/*0450*/ STS [R0.X4+0x1014], R5 ; /* 0x0010140500007388 */
/* 0x020fe80000004800 */
/*0460*/ @!P1 STS [RZ], R16 ; /* 0x00000010ff009388 */
/* 0x010fe80000000800 */
/*0470*/ @!P1 STS [0x808], R6 ; /* 0x00080806ff009388 */
/* 0x000fe80000000800 */
/*0480*/ @!P1 STS [0x1010], R10 ; /* 0x0010100aff009388 */
/* 0x000fe80000000800 */
/*0490*/ @!P0 STS [0x804], R8 ; /* 0x00080408ff008388 */
/* 0x000fe80000000800 */
/*04a0*/ @!P0 STS [0x100c], R12 ; /* 0x00100c0cff008388 */
/* 0x000fe80000000800 */
/*04b0*/ @!P0 STS [0x1814], R14 ; /* 0x0018140eff008388 */
/* 0x000fe80000000800 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04d0*/ LDS R9, [R0.X4] ; /* 0x0000000000097984 */
/* 0x000e280000004800 */
/*04e0*/ LDS R11, [R0.X4+0x808] ; /* 0x00080800000b7984 */
/* 0x000e680000004800 */
/*04f0*/ LDS R13, [R0.X4+0x1010] ; /* 0x00101000000d7984 */
/* 0x000ea80000004800 */
/*0500*/ LDS R15, [R0.X4+0x4] ; /* 0x00000400000f7984 */
/* 0x000ee80000004800 */
/*0510*/ LDS R16, [R0.X4+0x80c] ; /* 0x00080c0000107984 */
/* 0x000f280000004800 */
/*0520*/ LDS R7, [R0.X4+0x1014] ; /* 0x0010140000077984 */
/* 0x000f680000004800 */
/*0530*/ LDS R6, [R0.X4+0x8] ; /* 0x0000080000067984 */
/* 0x000f680000004800 */
/*0540*/ LDS R5, [R0.X4+0x810] ; /* 0x0008100000057984 */
/* 0x000f680000004800 */
/*0550*/ LDS R4, [R0.X4+0x1018] ; /* 0x0010180000047984 */
/* 0x000f620000004800 */
/*0560*/ IMAD R9, R9, c[0x3][0x0], RZ ; /* 0x00c0000009097a24 */
/* 0x001fc400078e02ff */
/*0570*/ IMAD R8, R11, c[0x3][0x4], RZ ; /* 0x00c001000b087a24 */
/* 0x002fe400078e02ff */
/*0580*/ IMAD R13, R13, c[0x3][0x8], RZ ; /* 0x00c002000d0d7a24 */
/* 0x004fe200078e02ff */
/*0590*/ SHF.R.S32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fe20000011409 */
/*05a0*/ IMAD R15, R15, c[0x3][0xc], RZ ; /* 0x00c003000f0f7a24 */
/* 0x008fe200078e02ff */
/*05b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*05c0*/ IADD3 R11, P0, P1, R13, R9, R8.reuse ; /* 0x000000090d0b7210 */
/* 0x100fe2000791e008 */
/*05d0*/ IMAD R16, R16, c[0x3][0x10], RZ ; /* 0x00c0040010107a24 */
/* 0x010fe200078e02ff */
/*05e0*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fe40000011408 */
/*05f0*/ SHF.R.S32.HI R13, RZ, 0x1f, R13 ; /* 0x0000001fff0d7819 */
/* 0x000fc8000001140d */
/*0600*/ IADD3.X R9, R13, R10, R9, P0, P1 ; /* 0x0000000a0d097210 */
/* 0x000fe400007e2409 */
/*0610*/ IADD3 R8, P0, P1, R16, R11, R15.reuse ; /* 0x0000000b10087210 */
/* 0x100fe4000791e00f */
/*0620*/ SHF.R.S32.HI R15, RZ, 0x1f, R15 ; /* 0x0000001fff0f7819 */
/* 0x000fe4000001140f */
/*0630*/ SHF.R.S32.HI R16, RZ, 0x1f, R16 ; /* 0x0000001fff107819 */
/* 0x000fc80000011410 */
/*0640*/ IADD3.X R15, R16, R9, R15, P0, P1 ; /* 0x00000009100f7210 */
/* 0x000fe400007e240f */
/*0650*/ ISETP.GT.U32.AND P1, PT, R18, c[0x0][0x170], PT ; /* 0x00005c0012007a0c */
/* 0x000fe20003f24070 */
/*0660*/ IMAD R7, R7, c[0x3][0x14], RZ ; /* 0x00c0050007077a24 */
/* 0x020fe400078e02ff */
/*0670*/ IMAD R6, R6, c[0x3][0x18], RZ ; /* 0x00c0060006067a24 */
/* 0x000fe200078e02ff */
/*0680*/ ISETP.GT.U32.AND.EX P1, PT, RZ, c[0x0][0x174], PT, P1 ; /* 0x00005d00ff007a0c */
/* 0x000fe20003f24110 */
/*0690*/ IMAD R5, R5, c[0x3][0x1c], RZ ; /* 0x00c0070005057a24 */
/* 0x000fe400078e02ff */
/*06a0*/ IMAD R4, R4, c[0x3][0x20], RZ ; /* 0x00c0080004047a24 */
/* 0x000fe200078e02ff */
/*06b0*/ IADD3 R8, P0, P3, R6, R8, R7 ; /* 0x0000000806087210 */
/* 0x000fc40007b1e007 */
/*06c0*/ SHF.R.S32.HI R7, RZ, 0x1f, R7 ; /* 0x0000001fff077819 */
/* 0x000fe40000011407 */
/*06d0*/ SHF.R.S32.HI R6, RZ, 0x1f, R6 ; /* 0x0000001fff067819 */
/* 0x000fc80000011406 */
/*06e0*/ IADD3.X R6, R6, R15, R7, P0, P3 ; /* 0x0000000f06067210 */
/* 0x000fe400007e6407 */
/*06f0*/ IADD3 R7, P3, P4, R4, R8, R5.reuse ; /* 0x0000000804077210 */
/* 0x100fe40007c7e005 */
/*0700*/ SHF.R.S32.HI R5, RZ, 0x1f, R5 ; /* 0x0000001fff057819 */
/* 0x000fe40000011405 */
/*0710*/ SHF.R.S32.HI R4, RZ, 0x1f, R4 ; /* 0x0000001fff047819 */
/* 0x000fe40000011404 */
/*0720*/ ISETP.GE.U32.AND P0, PT, R22, c[0x0][0x178], PT ; /* 0x00005e0016007a0c */
/* 0x000fe40003f06070 */
/*0730*/ IADD3.X R5, R4, R6, R5, P3, P4 ; /* 0x0000000604057210 */
/* 0x000fe20001fe8405 */
/*0740*/ @P1 BRA 0x7f0 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0750*/ ISETP.GT.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f24070 */
/*0760*/ IADD3 R4, P2, R19, UR5, RZ ; /* 0x0000000513047c10 */
/* 0x000fc4000ff5e0ff */
/*0770*/ ISETP.GT.AND.EX P1, PT, R5, RZ, PT, P1 ; /* 0x000000ff0500720c */
/* 0x000fc80003f24310 */
/*0780*/ SEL R7, R7, RZ, P1 ; /* 0x000000ff07077207 */
/* 0x000fe40000800000 */
/*0790*/ SEL R5, R5, RZ, P1 ; /* 0x000000ff05057207 */
/* 0x000fe40000800000 */
/*07a0*/ ISETP.LT.U32.AND P1, PT, R7, 0xff, PT ; /* 0x000000ff0700780c */
/* 0x000fc80003f21070 */
/*07b0*/ ISETP.LT.AND.EX P1, PT, R5, RZ, PT, P1 ; /* 0x000000ff0500720c */
/* 0x000fe40003f21310 */
/*07c0*/ IADD3.X R5, R21, UR6, RZ, P2, !PT ; /* 0x0000000615057c10 */
/* 0x000fe400097fe4ff */
/*07d0*/ SEL R7, R7, 0xff, P1 ; /* 0x000000ff07077807 */
/* 0x000fca0000800000 */
/*07e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.GE.U32.AND.EX P0, PT, R26, c[0x0][0x17c], PT, P0 ; /* 0x00005f001a007a0c */
/* 0x000fe20003f06100 */
/*0810*/ UIADD3 UR9, UP0, UR9, UR7, URZ ; /* 0x0000000709097290 */
/* 0x000fe2000ff1e03f */
/*0820*/ IADD3 R19, P1, R19, UR7, RZ ; /* 0x0000000713137c10 */
/* 0x000fc6000ff3e0ff */
/*0830*/ UIADD3.X UR4, UR4, UR8, URZ, UP0, !UPT ; /* 0x0000000804047290 */
/* 0x000fe200087fe43f */
/*0840*/ IADD3.X R21, R21, UR8, RZ, P1, !PT ; /* 0x0000000815157c10 */
/* 0x000fce0008ffe4ff */
/*0850*/ @!P0 BRA 0x1d0 ; /* 0xfffff97000008947 */
/* 0x000fea000383ffff */
/*0860*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0870*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0880*/ BRA 0x880; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#define KERNEL_SIZE 3
#define BLOCK_SIZE 512
typedef signed int pixel_channel;
typedef unsigned long resolution;
__constant__ pixel_channel kernel_cuda[KERNEL_SIZE * KERNEL_SIZE];
pixel_channel kernel_host[KERNEL_SIZE * KERNEL_SIZE] = { -1, -1, -1,
-1, 9, -1,
-1, -1, -1 };
__global__ void Pixel_Shared_Convolution(pixel_channel *channel_cuda, pixel_channel *rezult_cuda, resolution width, resolution lineQuantity)
{
__shared__ pixel_channel sharedMemory [3][BLOCK_SIZE + 2];
for(long line = 1; line < lineQuantity; line++)
{
long temp = blockIdx.x * BLOCK_SIZE + threadIdx.x;
sharedMemory [0][threadIdx.x + 1] = channel_cuda[temp + width * (line - 1)];
sharedMemory [1][threadIdx.x + 1] = channel_cuda[temp + width * line];
sharedMemory [2][threadIdx.x + 1] = channel_cuda[temp + width * (line + 1)];
if(threadIdx.x == 0)
{
if(blockIdx.x != 0)
temp--;
sharedMemory [0][0] = channel_cuda[temp + width * (line-1)];
sharedMemory [1][0] = channel_cuda[temp + width * line];
sharedMemory [2][0] = channel_cuda[temp + width * (line+1)];
}
if(threadIdx.x == (BLOCK_SIZE - 1))
{
temp++;
sharedMemory [0][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line - 1)];
sharedMemory [1][BLOCK_SIZE + 1] = channel_cuda[temp + width * line];
sharedMemory [2][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line + 1)];
}
__syncthreads();
long Sum = 0;
for (int i = 0; i < KERNEL_SIZE; i++)
for (int j = 0; j < KERNEL_SIZE; j++)
Sum += sharedMemory[j][threadIdx.x + i] * kernel_cuda[i * 3 + j];
if (Sum < 0)
Sum = 0;
if (Sum > 255)
Sum = 255;
__syncthreads();
if((blockIdx.x * BLOCK_SIZE + threadIdx.x) > width)
continue;
rezult_cuda[blockIdx.x * BLOCK_SIZE + threadIdx.x + width * line] = Sum;
}
__syncthreads();
return;
}
extern "C" __host__ pixel_channel** asyncConvolution(pixel_channel **image, resolution width, resolution height)
{
pixel_channel **channel_cuda;
channel_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));
pixel_channel **rezult_cuda;
rezult_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));
resolution size = width * height;
cudaHostRegister(image[0], (size + BLOCK_SIZE) * sizeof(pixel_channel), cudaHostRegisterMapped);
cudaHostRegister(image[1], (size + BLOCK_SIZE) * sizeof(pixel_channel), cudaHostRegisterMapped);
cudaHostRegister(image[2], (size + BLOCK_SIZE) * sizeof(pixel_channel), cudaHostRegisterMapped);
cudaMalloc((void **)& rezult_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMalloc((void **)& rezult_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMalloc((void **)& rezult_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMalloc((void **)& channel_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));;
cudaMalloc((void **)& channel_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMalloc((void **)& channel_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMemcpyToSymbol(kernel_cuda, kernel_host, 9 * sizeof(pixel_channel), 0, cudaMemcpyHostToDevice);
resolution block_count = 0;
if(((width - 2)%BLOCK_SIZE) == 0)
block_count = (width - 2)/BLOCK_SIZE;
else
block_count = (width - 2)/BLOCK_SIZE + 1;
dim3 gridSize = dim3(block_count, 1, 1);
dim3 blockSize = dim3(BLOCK_SIZE, 1, 1);
cudaStream_t stream[3];
for(int i = 0; i < 3; i++)
{
cudaStreamCreate(&stream[i]);
cudaMemcpyAsync(channel_cuda[i], image[i], size*sizeof(pixel_channel), cudaMemcpyHostToDevice, stream[i]);
Pixel_Shared_Convolution<<<gridSize, blockSize, 0, stream[i]>>>(channel_cuda[i], rezult_cuda[i], width, height);
cudaMemcpyAsync(image[i], rezult_cuda[i], size*sizeof(pixel_channel), cudaMemcpyDeviceToHost,stream[i]);
cudaStreamDestroy(stream[i]);
}
for(int i=0;i<3;i++)
{
cudaFree(rezult_cuda[i]);
cudaFree(channel_cuda[i]);
}
cudaDeviceReset();
return image;
} | .file "tmpxft_001510bc_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm
.type _Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm, @function
_Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24Pixel_Shared_ConvolutionPiS_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm, .-_Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm
.globl _Z24Pixel_Shared_ConvolutionPiS_mm
.type _Z24Pixel_Shared_ConvolutionPiS_mm, @function
_Z24Pixel_Shared_ConvolutionPiS_mm:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z24Pixel_Shared_ConvolutionPiS_mm, .-_Z24Pixel_Shared_ConvolutionPiS_mm
.globl asyncConvolution
.type asyncConvolution, @function
asyncConvolution:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rdi, %rbp
movq %rdi, 24(%rsp)
movq %rsi, %r12
movq %rsi, 32(%rsp)
movq %rdx, %rbx
movq %rdx, 40(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $24, %edi
call malloc@PLT
movq %rax, %r14
movl $24, %edi
call malloc@PLT
movq %rax, %r15
movq %r12, %rax
imulq %rbx, %rax
leaq 2048(,%rax,4), %rbx
movq 0(%rbp), %rdi
movl $2, %edx
movq %rbx, %rsi
call cudaHostRegister@PLT
movq 8(%rbp), %rdi
movl $2, %edx
movq %rbx, %rsi
call cudaHostRegister@PLT
movq 16(%rbp), %rdi
movl $2, %edx
movq %rbx, %rsi
call cudaHostRegister@PLT
movq %rbx, %rsi
movq %r15, %rdi
call cudaMalloc@PLT
leaq 8(%r15), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%r15), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %rbx, %rsi
movq %r14, %rdi
call cudaMalloc@PLT
leaq 8(%r14), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%r14), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %r8d
movl $0, %ecx
movl $36, %edx
leaq kernel_host(%rip), %rsi
leaq _ZL11kernel_cuda(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq -2(%r12), %rdx
movq %rdx, %rcx
shrq $9, %rcx
movq %rcx, %rax
addq $1, %rax
testl $511, %edx
cmove %rcx, %rax
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $512, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
leaq -2048(%rbx), %rax
movq %rax, 8(%rsp)
leaq 96(%rsp), %rbx
movq %r14, %r13
movq %r15, %r12
leaq 120(%rsp), %rax
movq %rax, 16(%rsp)
movq %r14, 48(%rsp)
movq %r15, 56(%rsp)
jmp .L15
.L14:
movq (%r12), %rsi
movq (%r15), %rdi
movq (%r14), %r8
movl $2, %ecx
movq 8(%rsp), %rdx
call cudaMemcpyAsync@PLT
movq (%r14), %rdi
call cudaStreamDestroy@PLT
addq $8, %rbx
addq $8, %rbp
addq $8, %r13
addq $8, %r12
movq 16(%rsp), %rax
cmpq %rax, %rbx
je .L21
.L15:
movq %rbx, %r14
movq %rbx, %rdi
call cudaStreamCreate@PLT
movq %rbp, %r15
movq 0(%rbp), %rsi
movq 0(%r13), %rdi
movq (%rbx), %r8
movl $1, %ecx
movq 8(%rsp), %rdx
call cudaMemcpyAsync@PLT
movl 92(%rsp), %ecx
movq (%rbx), %r9
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movq (%r12), %rsi
movq 0(%r13), %rdi
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
call _Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm
jmp .L14
.L21:
movq 48(%rsp), %r14
movq 56(%rsp), %r15
movl $0, %ebx
.L16:
movq (%r15,%rbx), %rdi
call cudaFree@PLT
movq (%r14,%rbx), %rdi
call cudaFree@PLT
addq $8, %rbx
cmpq $24, %rbx
jne .L16
call cudaDeviceReset@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
movq 24(%rsp), %rax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size asyncConvolution, .-asyncConvolution
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24Pixel_Shared_ConvolutionPiS_mm"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "kernel_cuda"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24Pixel_Shared_ConvolutionPiS_mm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11kernel_cuda(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl kernel_host
.data
.align 32
.type kernel_host, @object
.size kernel_host, 36
kernel_host:
.long -1
.long -1
.long -1
.long -1
.long 9
.long -1
.long -1
.long -1
.long -1
.local _ZL11kernel_cuda
.comm _ZL11kernel_cuda,36,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#define KERNEL_SIZE 3
#define BLOCK_SIZE 512
typedef signed int pixel_channel;
typedef unsigned long resolution;
__constant__ pixel_channel kernel_cuda[KERNEL_SIZE * KERNEL_SIZE];
pixel_channel kernel_host[KERNEL_SIZE * KERNEL_SIZE] = { -1, -1, -1,
-1, 9, -1,
-1, -1, -1 };
__global__ void Pixel_Shared_Convolution(pixel_channel *channel_cuda, pixel_channel *rezult_cuda, resolution width, resolution lineQuantity)
{
__shared__ pixel_channel sharedMemory [3][BLOCK_SIZE + 2];
for(long line = 1; line < lineQuantity; line++)
{
long temp = blockIdx.x * BLOCK_SIZE + threadIdx.x;
sharedMemory [0][threadIdx.x + 1] = channel_cuda[temp + width * (line - 1)];
sharedMemory [1][threadIdx.x + 1] = channel_cuda[temp + width * line];
sharedMemory [2][threadIdx.x + 1] = channel_cuda[temp + width * (line + 1)];
if(threadIdx.x == 0)
{
if(blockIdx.x != 0)
temp--;
sharedMemory [0][0] = channel_cuda[temp + width * (line-1)];
sharedMemory [1][0] = channel_cuda[temp + width * line];
sharedMemory [2][0] = channel_cuda[temp + width * (line+1)];
}
if(threadIdx.x == (BLOCK_SIZE - 1))
{
temp++;
sharedMemory [0][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line - 1)];
sharedMemory [1][BLOCK_SIZE + 1] = channel_cuda[temp + width * line];
sharedMemory [2][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line + 1)];
}
__syncthreads();
long Sum = 0;
for (int i = 0; i < KERNEL_SIZE; i++)
for (int j = 0; j < KERNEL_SIZE; j++)
Sum += sharedMemory[j][threadIdx.x + i] * kernel_cuda[i * 3 + j];
if (Sum < 0)
Sum = 0;
if (Sum > 255)
Sum = 255;
__syncthreads();
if((blockIdx.x * BLOCK_SIZE + threadIdx.x) > width)
continue;
rezult_cuda[blockIdx.x * BLOCK_SIZE + threadIdx.x + width * line] = Sum;
}
__syncthreads();
return;
}
extern "C" __host__ pixel_channel** asyncConvolution(pixel_channel **image, resolution width, resolution height)
{
pixel_channel **channel_cuda;
channel_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));
pixel_channel **rezult_cuda;
rezult_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));
resolution size = width * height;
cudaHostRegister(image[0], (size + BLOCK_SIZE) * sizeof(pixel_channel), cudaHostRegisterMapped);
cudaHostRegister(image[1], (size + BLOCK_SIZE) * sizeof(pixel_channel), cudaHostRegisterMapped);
cudaHostRegister(image[2], (size + BLOCK_SIZE) * sizeof(pixel_channel), cudaHostRegisterMapped);
cudaMalloc((void **)& rezult_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMalloc((void **)& rezult_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMalloc((void **)& rezult_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMalloc((void **)& channel_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));;
cudaMalloc((void **)& channel_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMalloc((void **)& channel_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));
cudaMemcpyToSymbol(kernel_cuda, kernel_host, 9 * sizeof(pixel_channel), 0, cudaMemcpyHostToDevice);
resolution block_count = 0;
if(((width - 2)%BLOCK_SIZE) == 0)
block_count = (width - 2)/BLOCK_SIZE;
else
block_count = (width - 2)/BLOCK_SIZE + 1;
dim3 gridSize = dim3(block_count, 1, 1);
dim3 blockSize = dim3(BLOCK_SIZE, 1, 1);
cudaStream_t stream[3];
for(int i = 0; i < 3; i++)
{
cudaStreamCreate(&stream[i]);
cudaMemcpyAsync(channel_cuda[i], image[i], size*sizeof(pixel_channel), cudaMemcpyHostToDevice, stream[i]);
Pixel_Shared_Convolution<<<gridSize, blockSize, 0, stream[i]>>>(channel_cuda[i], rezult_cuda[i], width, height);
cudaMemcpyAsync(image[i], rezult_cuda[i], size*sizeof(pixel_channel), cudaMemcpyDeviceToHost,stream[i]);
cudaStreamDestroy(stream[i]);
}
for(int i=0;i<3;i++)
{
cudaFree(rezult_cuda[i]);
cudaFree(channel_cuda[i]);
}
cudaDeviceReset();
return image;
} | #include <hip/hip_runtime.h>
#define KERNEL_SIZE 3
#define BLOCK_SIZE 512
typedef signed int pixel_channel;
typedef unsigned long resolution;
__constant__ pixel_channel kernel_cuda[KERNEL_SIZE * KERNEL_SIZE];
pixel_channel kernel_host[KERNEL_SIZE * KERNEL_SIZE] = { -1, -1, -1,
-1, 9, -1,
-1, -1, -1 };
__global__ void Pixel_Shared_Convolution(pixel_channel *channel_cuda, pixel_channel *rezult_cuda, resolution width, resolution lineQuantity)
{
__shared__ pixel_channel sharedMemory [3][BLOCK_SIZE + 2];
for(long line = 1; line < lineQuantity; line++)
{
long temp = blockIdx.x * BLOCK_SIZE + threadIdx.x;
sharedMemory [0][threadIdx.x + 1] = channel_cuda[temp + width * (line - 1)];
sharedMemory [1][threadIdx.x + 1] = channel_cuda[temp + width * line];
sharedMemory [2][threadIdx.x + 1] = channel_cuda[temp + width * (line + 1)];
if(threadIdx.x == 0)
{
if(blockIdx.x != 0)
temp--;
sharedMemory [0][0] = channel_cuda[temp + width * (line-1)];
sharedMemory [1][0] = channel_cuda[temp + width * line];
sharedMemory [2][0] = channel_cuda[temp + width * (line+1)];
}
if(threadIdx.x == (BLOCK_SIZE - 1))
{
temp++;
sharedMemory [0][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line - 1)];
sharedMemory [1][BLOCK_SIZE + 1] = channel_cuda[temp + width * line];
sharedMemory [2][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line + 1)];
}
__syncthreads();
long Sum = 0;
for (int i = 0; i < KERNEL_SIZE; i++)
for (int j = 0; j < KERNEL_SIZE; j++)
Sum += sharedMemory[j][threadIdx.x + i] * kernel_cuda[i * 3 + j];
if (Sum < 0)
Sum = 0;
if (Sum > 255)
Sum = 255;
__syncthreads();
if((blockIdx.x * BLOCK_SIZE + threadIdx.x) > width)
continue;
rezult_cuda[blockIdx.x * BLOCK_SIZE + threadIdx.x + width * line] = Sum;
}
__syncthreads();
return;
}
extern "C" __host__ pixel_channel** asyncConvolution(pixel_channel **image, resolution width, resolution height)
{
pixel_channel **channel_cuda;
channel_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));
pixel_channel **rezult_cuda;
rezult_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));
resolution size = width * height;
hipHostRegister(image[0], (size + BLOCK_SIZE) * sizeof(pixel_channel), hipHostRegisterMapped);
hipHostRegister(image[1], (size + BLOCK_SIZE) * sizeof(pixel_channel), hipHostRegisterMapped);
hipHostRegister(image[2], (size + BLOCK_SIZE) * sizeof(pixel_channel), hipHostRegisterMapped);
hipMalloc((void **)& rezult_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMalloc((void **)& rezult_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMalloc((void **)& rezult_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMalloc((void **)& channel_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));;
hipMalloc((void **)& channel_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMalloc((void **)& channel_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMemcpyToSymbol(HIP_SYMBOL(kernel_cuda), kernel_host, 9 * sizeof(pixel_channel), 0, hipMemcpyHostToDevice);
resolution block_count = 0;
if(((width - 2)%BLOCK_SIZE) == 0)
block_count = (width - 2)/BLOCK_SIZE;
else
block_count = (width - 2)/BLOCK_SIZE + 1;
dim3 gridSize = dim3(block_count, 1, 1);
dim3 blockSize = dim3(BLOCK_SIZE, 1, 1);
hipStream_t stream[3];
for(int i = 0; i < 3; i++)
{
hipStreamCreate(&stream[i]);
hipMemcpyAsync(channel_cuda[i], image[i], size*sizeof(pixel_channel), hipMemcpyHostToDevice, stream[i]);
Pixel_Shared_Convolution<<<gridSize, blockSize, 0, stream[i]>>>(channel_cuda[i], rezult_cuda[i], width, height);
hipMemcpyAsync(image[i], rezult_cuda[i], size*sizeof(pixel_channel), hipMemcpyDeviceToHost,stream[i]);
hipStreamDestroy(stream[i]);
}
for(int i=0;i<3;i++)
{
hipFree(rezult_cuda[i]);
hipFree(channel_cuda[i]);
}
hipDeviceReset();
return image;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define KERNEL_SIZE 3
#define BLOCK_SIZE 512
typedef signed int pixel_channel;
typedef unsigned long resolution;
__constant__ pixel_channel kernel_cuda[KERNEL_SIZE * KERNEL_SIZE];
pixel_channel kernel_host[KERNEL_SIZE * KERNEL_SIZE] = { -1, -1, -1,
-1, 9, -1,
-1, -1, -1 };
__global__ void Pixel_Shared_Convolution(pixel_channel *channel_cuda, pixel_channel *rezult_cuda, resolution width, resolution lineQuantity)
{
__shared__ pixel_channel sharedMemory [3][BLOCK_SIZE + 2];
for(long line = 1; line < lineQuantity; line++)
{
long temp = blockIdx.x * BLOCK_SIZE + threadIdx.x;
sharedMemory [0][threadIdx.x + 1] = channel_cuda[temp + width * (line - 1)];
sharedMemory [1][threadIdx.x + 1] = channel_cuda[temp + width * line];
sharedMemory [2][threadIdx.x + 1] = channel_cuda[temp + width * (line + 1)];
if(threadIdx.x == 0)
{
if(blockIdx.x != 0)
temp--;
sharedMemory [0][0] = channel_cuda[temp + width * (line-1)];
sharedMemory [1][0] = channel_cuda[temp + width * line];
sharedMemory [2][0] = channel_cuda[temp + width * (line+1)];
}
if(threadIdx.x == (BLOCK_SIZE - 1))
{
temp++;
sharedMemory [0][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line - 1)];
sharedMemory [1][BLOCK_SIZE + 1] = channel_cuda[temp + width * line];
sharedMemory [2][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line + 1)];
}
__syncthreads();
long Sum = 0;
for (int i = 0; i < KERNEL_SIZE; i++)
for (int j = 0; j < KERNEL_SIZE; j++)
Sum += sharedMemory[j][threadIdx.x + i] * kernel_cuda[i * 3 + j];
if (Sum < 0)
Sum = 0;
if (Sum > 255)
Sum = 255;
__syncthreads();
if((blockIdx.x * BLOCK_SIZE + threadIdx.x) > width)
continue;
rezult_cuda[blockIdx.x * BLOCK_SIZE + threadIdx.x + width * line] = Sum;
}
__syncthreads();
return;
}
extern "C" __host__ pixel_channel** asyncConvolution(pixel_channel **image, resolution width, resolution height)
{
pixel_channel **channel_cuda;
channel_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));
pixel_channel **rezult_cuda;
rezult_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));
resolution size = width * height;
hipHostRegister(image[0], (size + BLOCK_SIZE) * sizeof(pixel_channel), hipHostRegisterMapped);
hipHostRegister(image[1], (size + BLOCK_SIZE) * sizeof(pixel_channel), hipHostRegisterMapped);
hipHostRegister(image[2], (size + BLOCK_SIZE) * sizeof(pixel_channel), hipHostRegisterMapped);
hipMalloc((void **)& rezult_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMalloc((void **)& rezult_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMalloc((void **)& rezult_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMalloc((void **)& channel_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));;
hipMalloc((void **)& channel_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMalloc((void **)& channel_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMemcpyToSymbol(HIP_SYMBOL(kernel_cuda), kernel_host, 9 * sizeof(pixel_channel), 0, hipMemcpyHostToDevice);
resolution block_count = 0;
if(((width - 2)%BLOCK_SIZE) == 0)
block_count = (width - 2)/BLOCK_SIZE;
else
block_count = (width - 2)/BLOCK_SIZE + 1;
dim3 gridSize = dim3(block_count, 1, 1);
dim3 blockSize = dim3(BLOCK_SIZE, 1, 1);
hipStream_t stream[3];
for(int i = 0; i < 3; i++)
{
hipStreamCreate(&stream[i]);
hipMemcpyAsync(channel_cuda[i], image[i], size*sizeof(pixel_channel), hipMemcpyHostToDevice, stream[i]);
Pixel_Shared_Convolution<<<gridSize, blockSize, 0, stream[i]>>>(channel_cuda[i], rezult_cuda[i], width, height);
hipMemcpyAsync(image[i], rezult_cuda[i], size*sizeof(pixel_channel), hipMemcpyDeviceToHost,stream[i]);
hipStreamDestroy(stream[i]);
}
for(int i=0;i<3;i++)
{
hipFree(rezult_cuda[i]);
hipFree(channel_cuda[i]);
}
hipDeviceReset();
return image;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24Pixel_Shared_ConvolutionPiS_mm
.globl _Z24Pixel_Shared_ConvolutionPiS_mm
.p2align 8
.type _Z24Pixel_Shared_ConvolutionPiS_mm,@function
_Z24Pixel_Shared_ConvolutionPiS_mm:
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_lt_u64_e64 s2, s[8:9], 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_13
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_lshl_add_u32 v1, s15, 9, v0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v7, 2, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_cmp_eq_u32_e64 s0, 0x1ff, v0
v_mov_b32_e32 v16, 0
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_nc_u32_e32 v0, 4, v7
v_add_nc_u32_e32 v8, 0x80c, v7
v_add_nc_u32_e32 v9, 0x1014, v7
s_waitcnt lgkmcnt(0)
s_add_u32 s3, s4, 4
s_addc_u32 s16, s5, 0
s_cmp_lg_u32 s15, 0
v_add_co_u32 v12, s2, s6, v5
s_cselect_b32 s1, -1, 0
v_add_co_ci_u32_e64 v13, s2, s7, v6, s2
v_cndmask_b32_e64 v3, 0, 1, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_co_u32 v3, s1, v1, v3
v_sub_co_ci_u32_e64 v4, null, 0, 0, s1
v_add_co_u32 v10, s1, s4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v11, s1, s5, v6, s1
v_lshlrev_b64 v[14:15], 2, v[3:4]
v_cmp_ge_u64_e64 s1, s[10:11], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v14, s2, s4, v14
v_add_co_ci_u32_e64 v15, s2, s5, v15, s2
s_mov_b64 s[4:5], 1
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s12
s_cmp_eq_u64 s[4:5], s[8:9]
s_cbranch_scc1 .LBB0_13
.LBB0_3:
s_add_u32 s2, s4, -1
s_addc_u32 s12, s5, -1
s_mul_i32 s6, s2, s11
s_mul_hi_u32 s7, s2, s10
s_mul_i32 s12, s12, s10
s_add_i32 s6, s7, s6
s_mul_i32 s13, s4, s11
s_mul_hi_u32 s14, s4, s10
s_add_i32 s7, s6, s12
s_add_i32 s12, s14, s13
s_mul_i32 s13, s5, s10
s_mul_i32 s6, s2, s10
s_add_i32 s15, s12, s13
s_mul_i32 s14, s4, s10
s_lshl_b64 s[12:13], s[6:7], 2
s_lshl_b64 s[6:7], s[14:15], 2
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_mul_i32 s2, s4, s11
s_mul_hi_u32 s14, s4, s10
s_mul_i32 s15, s5, s10
s_add_i32 s14, s14, s2
v_add_co_u32 v5, s2, v10, s12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s2, s13, v11, s2
s_add_i32 s15, s14, s15
s_mul_i32 s14, s4, s10
v_add_co_u32 v17, s2, v10, s6
s_lshl_b64 s[14:15], s[14:15], 2
v_add_co_ci_u32_e64 v18, s2, s7, v11, s2
v_add_co_u32 v19, s2, v10, s14
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v20, s2, s15, v11, s2
s_clause 0x2
global_load_b32 v21, v[5:6], off
global_load_b32 v17, v[17:18], off
global_load_b32 v18, v[19:20], off
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
s_waitcnt vmcnt(2)
ds_store_b32 v0, v21
s_waitcnt vmcnt(1)
ds_store_b32 v8, v17
s_waitcnt vmcnt(0)
ds_store_b32 v9, v18
s_and_saveexec_b32 s17, vcc_lo
s_cbranch_execz .LBB0_5
v_add_co_u32 v5, s2, v14, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s2, s13, v15, s2
v_add_co_u32 v17, s2, v14, s6
v_add_co_ci_u32_e64 v18, s2, s7, v15, s2
v_add_co_u32 v19, s2, v14, s14
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v20, s2, s15, v15, s2
s_clause 0x2
global_load_b32 v21, v[5:6], off
global_load_b32 v17, v[17:18], off
global_load_b32 v18, v[19:20], off
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_waitcnt vmcnt(2)
ds_store_b32 v16, v21
s_waitcnt vmcnt(1)
ds_store_b32 v16, v17 offset:2056
s_waitcnt vmcnt(0)
ds_store_b32 v16, v18 offset:4112
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s17
s_and_saveexec_b32 s17, s0
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v19, s2, s3, v5
v_add_co_ci_u32_e64 v20, s2, s16, v6, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s2, v19, s12
v_add_co_ci_u32_e64 v6, s2, s13, v20, s2
v_add_co_u32 v17, s2, v19, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v18, s2, s7, v20, s2
v_add_co_u32 v19, s2, v19, s14
v_add_co_ci_u32_e64 v20, s2, s15, v20, s2
s_clause 0x2
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[17:18], off
global_load_b32 v17, v[19:20], off
s_waitcnt vmcnt(2)
ds_store_b32 v16, v5 offset:2052
s_waitcnt vmcnt(1)
ds_store_b32 v16, v6 offset:4108
s_waitcnt vmcnt(0)
ds_store_b32 v16, v17 offset:6164
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s17
v_mov_b32_e32 v5, 0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v17, v7
s_mov_b32 s17, 0
s_getpc_b64 s[12:13]
s_add_u32 s12, s12, kernel_cuda@rel32@lo+4
s_addc_u32 s13, s13, kernel_cuda@rel32@hi+12
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.p2align 6
.LBB0_8:
v_mov_b32_e32 v18, v17
s_mov_b64 s[14:15], 0
.p2align 6
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s12, s14
s_addc_u32 s19, s13, s15
ds_load_b32 v19, v18
s_load_b32 s2, s[18:19], 0x0
v_add_nc_u32_e32 v18, 0x808, v18
s_add_u32 s14, s14, 4
s_addc_u32 s15, s15, 0
s_cmp_eq_u32 s14, 12
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v19, s2, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v20, 31, v19
v_add_co_u32 v5, s2, v5, v19
v_add_co_ci_u32_e64 v6, s2, v6, v20, s2
s_cbranch_scc0 .LBB0_9
s_add_i32 s17, s17, 1
v_add_nc_u32_e32 v17, 4, v17
s_add_u32 s12, s12, 12
s_addc_u32 s13, s13, 0
s_cmp_eq_u32 s17, 3
s_cbranch_scc0 .LBB0_8
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s12, s1
s_cbranch_execz .LBB0_2
v_cmp_lt_i64_e64 s2, 0, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, 0, v6, s2
v_cndmask_b32_e64 v5, 0, v5, s2
v_cmp_gt_u64_e64 s2, 0xff, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v17, 0xff, v5, s2
v_add_co_u32 v5, s2, v12, s6
v_add_co_ci_u32_e64 v6, s2, s7, v13, s2
global_store_b32 v[5:6], v17, off
s_branch .LBB0_2
.LBB0_13:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24Pixel_Shared_ConvolutionPiS_mm
.amdhsa_group_segment_fixed_size 6168
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24Pixel_Shared_ConvolutionPiS_mm, .Lfunc_end0-_Z24Pixel_Shared_ConvolutionPiS_mm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected kernel_cuda
.type kernel_cuda,@object
.section .bss,"aw",@nobits
.globl kernel_cuda
.p2align 4, 0x0
kernel_cuda:
.zero 36
.size kernel_cuda, 36
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym kernel_cuda
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 6168
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24Pixel_Shared_ConvolutionPiS_mm
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z24Pixel_Shared_ConvolutionPiS_mm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define KERNEL_SIZE 3
#define BLOCK_SIZE 512
typedef signed int pixel_channel;
typedef unsigned long resolution;
__constant__ pixel_channel kernel_cuda[KERNEL_SIZE * KERNEL_SIZE];
pixel_channel kernel_host[KERNEL_SIZE * KERNEL_SIZE] = { -1, -1, -1,
-1, 9, -1,
-1, -1, -1 };
__global__ void Pixel_Shared_Convolution(pixel_channel *channel_cuda, pixel_channel *rezult_cuda, resolution width, resolution lineQuantity)
{
__shared__ pixel_channel sharedMemory [3][BLOCK_SIZE + 2];
for(long line = 1; line < lineQuantity; line++)
{
long temp = blockIdx.x * BLOCK_SIZE + threadIdx.x;
sharedMemory [0][threadIdx.x + 1] = channel_cuda[temp + width * (line - 1)];
sharedMemory [1][threadIdx.x + 1] = channel_cuda[temp + width * line];
sharedMemory [2][threadIdx.x + 1] = channel_cuda[temp + width * (line + 1)];
if(threadIdx.x == 0)
{
if(blockIdx.x != 0)
temp--;
sharedMemory [0][0] = channel_cuda[temp + width * (line-1)];
sharedMemory [1][0] = channel_cuda[temp + width * line];
sharedMemory [2][0] = channel_cuda[temp + width * (line+1)];
}
if(threadIdx.x == (BLOCK_SIZE - 1))
{
temp++;
sharedMemory [0][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line - 1)];
sharedMemory [1][BLOCK_SIZE + 1] = channel_cuda[temp + width * line];
sharedMemory [2][BLOCK_SIZE + 1] = channel_cuda[temp + width * (line + 1)];
}
__syncthreads();
long Sum = 0;
for (int i = 0; i < KERNEL_SIZE; i++)
for (int j = 0; j < KERNEL_SIZE; j++)
Sum += sharedMemory[j][threadIdx.x + i] * kernel_cuda[i * 3 + j];
if (Sum < 0)
Sum = 0;
if (Sum > 255)
Sum = 255;
__syncthreads();
if((blockIdx.x * BLOCK_SIZE + threadIdx.x) > width)
continue;
rezult_cuda[blockIdx.x * BLOCK_SIZE + threadIdx.x + width * line] = Sum;
}
__syncthreads();
return;
}
extern "C" __host__ pixel_channel** asyncConvolution(pixel_channel **image, resolution width, resolution height)
{
pixel_channel **channel_cuda;
channel_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));
pixel_channel **rezult_cuda;
rezult_cuda = (pixel_channel**)malloc(3*sizeof(pixel_channel*));
resolution size = width * height;
hipHostRegister(image[0], (size + BLOCK_SIZE) * sizeof(pixel_channel), hipHostRegisterMapped);
hipHostRegister(image[1], (size + BLOCK_SIZE) * sizeof(pixel_channel), hipHostRegisterMapped);
hipHostRegister(image[2], (size + BLOCK_SIZE) * sizeof(pixel_channel), hipHostRegisterMapped);
hipMalloc((void **)& rezult_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMalloc((void **)& rezult_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMalloc((void **)& rezult_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMalloc((void **)& channel_cuda[0], (size + BLOCK_SIZE) * sizeof(pixel_channel));;
hipMalloc((void **)& channel_cuda[1], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMalloc((void **)& channel_cuda[2], (size + BLOCK_SIZE) * sizeof(pixel_channel));
hipMemcpyToSymbol(HIP_SYMBOL(kernel_cuda), kernel_host, 9 * sizeof(pixel_channel), 0, hipMemcpyHostToDevice);
resolution block_count = 0;
if(((width - 2)%BLOCK_SIZE) == 0)
block_count = (width - 2)/BLOCK_SIZE;
else
block_count = (width - 2)/BLOCK_SIZE + 1;
dim3 gridSize = dim3(block_count, 1, 1);
dim3 blockSize = dim3(BLOCK_SIZE, 1, 1);
hipStream_t stream[3];
for(int i = 0; i < 3; i++)
{
hipStreamCreate(&stream[i]);
hipMemcpyAsync(channel_cuda[i], image[i], size*sizeof(pixel_channel), hipMemcpyHostToDevice, stream[i]);
Pixel_Shared_Convolution<<<gridSize, blockSize, 0, stream[i]>>>(channel_cuda[i], rezult_cuda[i], width, height);
hipMemcpyAsync(image[i], rezult_cuda[i], size*sizeof(pixel_channel), hipMemcpyDeviceToHost,stream[i]);
hipStreamDestroy(stream[i]);
}
for(int i=0;i<3;i++)
{
hipFree(rezult_cuda[i]);
hipFree(channel_cuda[i]);
}
hipDeviceReset();
return image;
} | .text
.file "cuda.hip"
.globl _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm # -- Begin function _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
.p2align 4, 0x90
.type _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm,@function
_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm: # @_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24Pixel_Shared_ConvolutionPiS_mm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm, .Lfunc_end0-_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
.cfi_endproc
# -- End function
.globl asyncConvolution # -- Begin function asyncConvolution
.p2align 4, 0x90
.type asyncConvolution,@function
asyncConvolution: # @asyncConvolution
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r12
movq %rsi, %r13
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, %rbx
movl $24, %edi
callq malloc
movq %rax, %r14
movl $24, %edi
callq malloc
movq %rax, %r15
movq (%rbx), %rdi
movq %r12, 16(%rsp) # 8-byte Spill
imulq %r12, %r13
leaq 2048(,%r13,4), %r12
shlq $2, %r13
movq %r12, %rsi
movl $2, %edx
callq hipHostRegister
movq 8(%rbx), %rdi
movq %r12, %rsi
movl $2, %edx
callq hipHostRegister
movq 16(%rbx), %rdi
movq %r12, %rsi
movl $2, %edx
callq hipHostRegister
movq %r15, %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%r15), %rdi
movq %r12, %rsi
callq hipMalloc
movq %r15, %rdi
addq $16, %rdi
movq %r12, %rsi
callq hipMalloc
movq %r14, %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%r14), %rdi
movq %r12, %rsi
callq hipMalloc
movq %r14, %rdi
addq $16, %rdi
movq %r12, %rsi
callq hipMalloc
xorl %ebp, %ebp
movl $kernel_cuda, %edi
movl $kernel_host, %esi
movl $36, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq 8(%rsp), %rax # 8-byte Reload
leaq -2(%rax), %r12
movl %r12d, %eax
andl $511, %eax # imm = 0x1FF
shrq $9, %r12
cmpq $1, %rax
sbbl $-1, %r12d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
addq $512, %rax # imm = 0x200
movq %rax, 24(%rsp) # 8-byte Spill
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq (%rbx,%rbp), %rdi
movq (%r15,%rbp), %rsi
movq 112(%rsp,%rbp), %r8
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpyAsync
movq 112(%rsp,%rbp), %rdi
callq hipStreamDestroy
addq $8, %rbp
cmpq $24, %rbp
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbp), %rdi
addq $112, %rdi
callq hipStreamCreate
movq (%r14,%rbp), %rdi
movq (%rbx,%rbp), %rsi
movq 112(%rsp,%rbp), %r8
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 112(%rsp,%rbp), %r9
movq %r12, %rdi
movl $1, %esi
movq 24(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq (%r14,%rbp), %rax
movq (%r15,%rbp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movq %rax, 88(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movq %rax, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z24Pixel_Shared_ConvolutionPiS_mm, %edi
leaq 144(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_3
.LBB1_4: # %.preheader.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%r15,%r12,8), %rdi
callq hipFree
movq (%r14,%r12,8), %rdi
callq hipFree
incq %r12
cmpq $3, %r12
jne .LBB1_5
# %bb.6:
callq hipDeviceReset
movq %rbx, %rax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size asyncConvolution, .Lfunc_end1-asyncConvolution
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24Pixel_Shared_ConvolutionPiS_mm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $kernel_cuda, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel_cuda,@object # @kernel_cuda
.local kernel_cuda
.comm kernel_cuda,36,16
.type kernel_host,@object # @kernel_host
.data
.globl kernel_host
.p2align 4, 0x0
kernel_host:
.long 4294967295 # 0xffffffff
.long 4294967295 # 0xffffffff
.long 4294967295 # 0xffffffff
.long 4294967295 # 0xffffffff
.long 9 # 0x9
.long 4294967295 # 0xffffffff
.long 4294967295 # 0xffffffff
.long 4294967295 # 0xffffffff
.long 4294967295 # 0xffffffff
.size kernel_host, 36
.type _Z24Pixel_Shared_ConvolutionPiS_mm,@object # @_Z24Pixel_Shared_ConvolutionPiS_mm
.section .rodata,"a",@progbits
.globl _Z24Pixel_Shared_ConvolutionPiS_mm
.p2align 3, 0x0
_Z24Pixel_Shared_ConvolutionPiS_mm:
.quad _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
.size _Z24Pixel_Shared_ConvolutionPiS_mm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24Pixel_Shared_ConvolutionPiS_mm"
.size .L__unnamed_1, 35
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "kernel_cuda"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel_cuda
.addrsig_sym kernel_host
.addrsig_sym _Z24Pixel_Shared_ConvolutionPiS_mm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24Pixel_Shared_ConvolutionPiS_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe400078e00ff */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x000fc600078e00ff */
/*0030*/ ISETP.GE.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fc80003f06070 */
/*0040*/ ISETP.GE.U32.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0003f06100 */
/*0050*/ @!P0 BRA 0x860 ; /* 0x0000080000008947 */
/* 0x000fea0003800000 */
/*0060*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0070*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0090*/ USHF.L.U32 UR7, UR4, 0x2, URZ ; /* 0x0000000204077899 */
/* 0x000fe2000800063f */
/*00a0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00b0*/ UMOV UR8, 0x2 ; /* 0x0000000200087882 */
/* 0x000fe20000000000 */
/*00c0*/ IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; /* 0x00000001ff167424 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR10, c[0x0][0x168] ; /* 0x00005a00000a7ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ IMAD.MOV.U32 R26, RZ, RZ, RZ ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e00ff */
/*00f0*/ USHF.L.U64.HI UR8, UR4, UR8, UR5 ; /* 0x0000000804087299 */
/* 0x000fe40008010205 */
/*0100*/ UIADD3 UR5, UP0, UR7, UR10, URZ ; /* 0x0000000a07057290 */
/* 0x000fc4000ff1e03f */
/*0110*/ UMOV UR9, 0x4 ; /* 0x0000000400097882 */
/* 0x000fe40000000000 */
/*0120*/ UIADD3.X UR6, UR8, UR11, URZ, UP0, !UPT ; /* 0x0000000b08067290 */
/* 0x000fe400087fe43f */
/*0130*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0140*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0150*/ ISETP.NE.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720c */
/* 0x041fe20003f05270 */
/*0160*/ IMAD R18, R3, 0x200, R0 ; /* 0x0000020003127824 */
/* 0x002fc600078e0200 */
/*0170*/ SEL R5, RZ, 0xffffffff, !P0 ; /* 0xffffffffff057807 */
/* 0x000fe20004000000 */
/*0180*/ IMAD.WIDE.U32 R20, R18, 0x4, RZ ; /* 0x0000000412147825 */
/* 0x000fc600078e00ff */
/*0190*/ IADD3 R24, P0, R18, R5, RZ ; /* 0x0000000512187210 */
/* 0x000fe20007f1e0ff */
/*01a0*/ IMAD.MOV.U32 R19, RZ, RZ, R20 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0014 */
/*01b0*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0202 */
/*01c0*/ IMAD.X R20, RZ, RZ, R5, P0 ; /* 0x000000ffff147224 */
/* 0x000fe400000e0605 */
/*01d0*/ ISETP.NE.AND P1, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f25270 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0012 */
/*01f0*/ ISETP.NE.AND P0, PT, R0, 0x1ff, PT ; /* 0x000001ff0000780c */
/* 0x000fe20003f05270 */
/*0200*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0210*/ IADD3 R12, P2, R19, c[0x0][0x160], RZ ; /* 0x00005800130c7a10 */
/* 0x000fc80007f5e0ff */
/*0220*/ IADD3.X R13, R21, c[0x0][0x164], RZ, P2, !PT ; /* 0x00005900150d7a10 */
/* 0x000fe400017fe4ff */
/*0230*/ IADD3 R14, P3, R12, UR7, RZ ; /* 0x000000070c0e7c10 */
/* 0x000fc6000ff7e0ff */
/*0240*/ @!P1 IMAD.MOV.U32 R4, RZ, RZ, R24 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0018 */
/*0250*/ @!P1 IADD3 R16, P2, R2, R19, RZ ; /* 0x0000001302109210 */
/* 0x000fe20007f5e0ff */
/*0260*/ @!P1 IMAD.MOV.U32 R9, RZ, RZ, R20 ; /* 0x000000ffff099224 */
/* 0x000fe200078e0014 */
/*0270*/ IADD3.X R15, R13, UR8, RZ, P3, !PT ; /* 0x000000080d0f7c10 */
/* 0x000fe20009ffe4ff */
/*0280*/ LDG.E R23, [R12.64] ; /* 0x0000000a0c177981 */
/* 0x0000a2000c1e1900 */
/*0290*/ @!P0 LEA R8, P4, R4.reuse, UR9, 0x2 ; /* 0x0000000904088c11 */
/* 0x040fe2000f8810ff */
/*02a0*/ @!P1 IMAD.X R17, R3, 0x1, R21, P2 ; /* 0x0000000103119824 */
/* 0x000fe400010e0615 */
/*02b0*/ LDG.E R25, [R14.64] ; /* 0x0000000a0e197981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ @!P0 LEA.HI.X R9, R4, UR4, R9, 0x2, P4 ; /* 0x0000000404098c11 */
/* 0x000fe4000a0f1409 */
/*02d0*/ IADD3 R4, P3, R14, UR7, RZ ; /* 0x000000070e047c10 */
/* 0x000fc4000ff7e0ff */
/*02e0*/ @!P1 IADD3 R6, P2, R16, UR7, RZ ; /* 0x0000000710069c10 */
/* 0x000fe4000ff5e0ff */
/*02f0*/ IADD3.X R5, R15, UR8, RZ, P3, !PT ; /* 0x000000080f057c10 */
/* 0x000fe20009ffe4ff */
/*0300*/ @!P1 LDG.E R16, [R16.64] ; /* 0x0000000a10109981 */
/* 0x000f22000c1e1900 */
/*0310*/ @!P0 IADD3 R8, P3, R8, c[0x0][0x160], RZ ; /* 0x0000580008088a10 */
/* 0x000fe40007f7e0ff */
/*0320*/ @!P1 IADD3.X R7, R17, UR8, RZ, P2, !PT ; /* 0x0000000811079c10 */
/* 0x000fe400097fe4ff */
/*0330*/ @!P1 IADD3 R10, P2, R6, UR7, RZ ; /* 0x00000007060a9c10 */
/* 0x000fe2000ff5e0ff */
/*0340*/ LDG.E R5, [R4.64] ; /* 0x0000000a04057981 */
/* 0x000f62000c1e1900 */
/*0350*/ @!P0 IADD3.X R9, R9, c[0x0][0x164], RZ, P3, !PT ; /* 0x0000590009098a10 */
/* 0x000fc40001ffe4ff */
/*0360*/ @!P0 IADD3 R12, P3, R8, UR7, RZ ; /* 0x00000007080c8c10 */
/* 0x001fe2000ff7e0ff */
/*0370*/ @!P1 LDG.E R6, [R6.64] ; /* 0x0000000a06069981 */
/* 0x000f22000c1e1900 */
/*0380*/ @!P1 IADD3.X R11, R7, UR8, RZ, P2, !PT ; /* 0x00000008070b9c10 */
/* 0x000fe400097fe4ff */
/*0390*/ @!P0 IADD3.X R13, R9, UR8, RZ, P3, !PT ; /* 0x00000008090d8c10 */
/* 0x000fe20009ffe4ff */
/*03a0*/ @!P0 LDG.E R8, [R8.64] ; /* 0x0000000a08088981 */
/* 0x000f22000c1e1900 */
/*03b0*/ @!P0 IADD3 R14, P2, R12, UR7, RZ ; /* 0x000000070c0e8c10 */
/* 0x002fc6000ff5e0ff */
/*03c0*/ @!P1 LDG.E R10, [R10.64] ; /* 0x0000000a0a0a9981 */
/* 0x000f22000c1e1900 */
/*03d0*/ @!P0 IADD3.X R15, R13, UR8, RZ, P2, !PT ; /* 0x000000080d0f8c10 */
/* 0x000fc600097fe4ff */
/*03e0*/ @!P0 LDG.E R12, [R12.64] ; /* 0x0000000a0c0c8981 */
/* 0x000f28000c1e1900 */
/*03f0*/ @!P0 LDG.E R14, [R14.64] ; /* 0x0000000a0e0e8981 */
/* 0x000f22000c1e1900 */
/*0400*/ IADD3 R22, P2, R22, 0x1, RZ ; /* 0x0000000116167810 */
/* 0x000fe20007f5e0ff */
/*0410*/ BSSY B0, 0x800 ; /* 0x000003e000007945 */
/* 0x000fe80003800000 */
/*0420*/ IMAD.X R26, RZ, RZ, R26, P2 ; /* 0x000000ffff1a7224 */
/* 0x000fe200010e061a */
/*0430*/ STS [R0.X4+0x4], R23 ; /* 0x0000041700007388 */
/* 0x004fe80000004800 */
/*0440*/ STS [R0.X4+0x80c], R25 ; /* 0x00080c1900007388 */
/* 0x008fe80000004800 */
/*0450*/ STS [R0.X4+0x1014], R5 ; /* 0x0010140500007388 */
/* 0x020fe80000004800 */
/*0460*/ @!P1 STS [RZ], R16 ; /* 0x00000010ff009388 */
/* 0x010fe80000000800 */
/*0470*/ @!P1 STS [0x808], R6 ; /* 0x00080806ff009388 */
/* 0x000fe80000000800 */
/*0480*/ @!P1 STS [0x1010], R10 ; /* 0x0010100aff009388 */
/* 0x000fe80000000800 */
/*0490*/ @!P0 STS [0x804], R8 ; /* 0x00080408ff008388 */
/* 0x000fe80000000800 */
/*04a0*/ @!P0 STS [0x100c], R12 ; /* 0x00100c0cff008388 */
/* 0x000fe80000000800 */
/*04b0*/ @!P0 STS [0x1814], R14 ; /* 0x0018140eff008388 */
/* 0x000fe80000000800 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04d0*/ LDS R9, [R0.X4] ; /* 0x0000000000097984 */
/* 0x000e280000004800 */
/*04e0*/ LDS R11, [R0.X4+0x808] ; /* 0x00080800000b7984 */
/* 0x000e680000004800 */
/*04f0*/ LDS R13, [R0.X4+0x1010] ; /* 0x00101000000d7984 */
/* 0x000ea80000004800 */
/*0500*/ LDS R15, [R0.X4+0x4] ; /* 0x00000400000f7984 */
/* 0x000ee80000004800 */
/*0510*/ LDS R16, [R0.X4+0x80c] ; /* 0x00080c0000107984 */
/* 0x000f280000004800 */
/*0520*/ LDS R7, [R0.X4+0x1014] ; /* 0x0010140000077984 */
/* 0x000f680000004800 */
/*0530*/ LDS R6, [R0.X4+0x8] ; /* 0x0000080000067984 */
/* 0x000f680000004800 */
/*0540*/ LDS R5, [R0.X4+0x810] ; /* 0x0008100000057984 */
/* 0x000f680000004800 */
/*0550*/ LDS R4, [R0.X4+0x1018] ; /* 0x0010180000047984 */
/* 0x000f620000004800 */
/*0560*/ IMAD R9, R9, c[0x3][0x0], RZ ; /* 0x00c0000009097a24 */
/* 0x001fc400078e02ff */
/*0570*/ IMAD R8, R11, c[0x3][0x4], RZ ; /* 0x00c001000b087a24 */
/* 0x002fe400078e02ff */
/*0580*/ IMAD R13, R13, c[0x3][0x8], RZ ; /* 0x00c002000d0d7a24 */
/* 0x004fe200078e02ff */
/*0590*/ SHF.R.S32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fe20000011409 */
/*05a0*/ IMAD R15, R15, c[0x3][0xc], RZ ; /* 0x00c003000f0f7a24 */
/* 0x008fe200078e02ff */
/*05b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*05c0*/ IADD3 R11, P0, P1, R13, R9, R8.reuse ; /* 0x000000090d0b7210 */
/* 0x100fe2000791e008 */
/*05d0*/ IMAD R16, R16, c[0x3][0x10], RZ ; /* 0x00c0040010107a24 */
/* 0x010fe200078e02ff */
/*05e0*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fe40000011408 */
/*05f0*/ SHF.R.S32.HI R13, RZ, 0x1f, R13 ; /* 0x0000001fff0d7819 */
/* 0x000fc8000001140d */
/*0600*/ IADD3.X R9, R13, R10, R9, P0, P1 ; /* 0x0000000a0d097210 */
/* 0x000fe400007e2409 */
/*0610*/ IADD3 R8, P0, P1, R16, R11, R15.reuse ; /* 0x0000000b10087210 */
/* 0x100fe4000791e00f */
/*0620*/ SHF.R.S32.HI R15, RZ, 0x1f, R15 ; /* 0x0000001fff0f7819 */
/* 0x000fe4000001140f */
/*0630*/ SHF.R.S32.HI R16, RZ, 0x1f, R16 ; /* 0x0000001fff107819 */
/* 0x000fc80000011410 */
/*0640*/ IADD3.X R15, R16, R9, R15, P0, P1 ; /* 0x00000009100f7210 */
/* 0x000fe400007e240f */
/*0650*/ ISETP.GT.U32.AND P1, PT, R18, c[0x0][0x170], PT ; /* 0x00005c0012007a0c */
/* 0x000fe20003f24070 */
/*0660*/ IMAD R7, R7, c[0x3][0x14], RZ ; /* 0x00c0050007077a24 */
/* 0x020fe400078e02ff */
/*0670*/ IMAD R6, R6, c[0x3][0x18], RZ ; /* 0x00c0060006067a24 */
/* 0x000fe200078e02ff */
/*0680*/ ISETP.GT.U32.AND.EX P1, PT, RZ, c[0x0][0x174], PT, P1 ; /* 0x00005d00ff007a0c */
/* 0x000fe20003f24110 */
/*0690*/ IMAD R5, R5, c[0x3][0x1c], RZ ; /* 0x00c0070005057a24 */
/* 0x000fe400078e02ff */
/*06a0*/ IMAD R4, R4, c[0x3][0x20], RZ ; /* 0x00c0080004047a24 */
/* 0x000fe200078e02ff */
/*06b0*/ IADD3 R8, P0, P3, R6, R8, R7 ; /* 0x0000000806087210 */
/* 0x000fc40007b1e007 */
/*06c0*/ SHF.R.S32.HI R7, RZ, 0x1f, R7 ; /* 0x0000001fff077819 */
/* 0x000fe40000011407 */
/*06d0*/ SHF.R.S32.HI R6, RZ, 0x1f, R6 ; /* 0x0000001fff067819 */
/* 0x000fc80000011406 */
/*06e0*/ IADD3.X R6, R6, R15, R7, P0, P3 ; /* 0x0000000f06067210 */
/* 0x000fe400007e6407 */
/*06f0*/ IADD3 R7, P3, P4, R4, R8, R5.reuse ; /* 0x0000000804077210 */
/* 0x100fe40007c7e005 */
/*0700*/ SHF.R.S32.HI R5, RZ, 0x1f, R5 ; /* 0x0000001fff057819 */
/* 0x000fe40000011405 */
/*0710*/ SHF.R.S32.HI R4, RZ, 0x1f, R4 ; /* 0x0000001fff047819 */
/* 0x000fe40000011404 */
/*0720*/ ISETP.GE.U32.AND P0, PT, R22, c[0x0][0x178], PT ; /* 0x00005e0016007a0c */
/* 0x000fe40003f06070 */
/*0730*/ IADD3.X R5, R4, R6, R5, P3, P4 ; /* 0x0000000604057210 */
/* 0x000fe20001fe8405 */
/*0740*/ @P1 BRA 0x7f0 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0750*/ ISETP.GT.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f24070 */
/*0760*/ IADD3 R4, P2, R19, UR5, RZ ; /* 0x0000000513047c10 */
/* 0x000fc4000ff5e0ff */
/*0770*/ ISETP.GT.AND.EX P1, PT, R5, RZ, PT, P1 ; /* 0x000000ff0500720c */
/* 0x000fc80003f24310 */
/*0780*/ SEL R7, R7, RZ, P1 ; /* 0x000000ff07077207 */
/* 0x000fe40000800000 */
/*0790*/ SEL R5, R5, RZ, P1 ; /* 0x000000ff05057207 */
/* 0x000fe40000800000 */
/*07a0*/ ISETP.LT.U32.AND P1, PT, R7, 0xff, PT ; /* 0x000000ff0700780c */
/* 0x000fc80003f21070 */
/*07b0*/ ISETP.LT.AND.EX P1, PT, R5, RZ, PT, P1 ; /* 0x000000ff0500720c */
/* 0x000fe40003f21310 */
/*07c0*/ IADD3.X R5, R21, UR6, RZ, P2, !PT ; /* 0x0000000615057c10 */
/* 0x000fe400097fe4ff */
/*07d0*/ SEL R7, R7, 0xff, P1 ; /* 0x000000ff07077807 */
/* 0x000fca0000800000 */
/*07e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.GE.U32.AND.EX P0, PT, R26, c[0x0][0x17c], PT, P0 ; /* 0x00005f001a007a0c */
/* 0x000fe20003f06100 */
/*0810*/ UIADD3 UR9, UP0, UR9, UR7, URZ ; /* 0x0000000709097290 */
/* 0x000fe2000ff1e03f */
/*0820*/ IADD3 R19, P1, R19, UR7, RZ ; /* 0x0000000713137c10 */
/* 0x000fc6000ff3e0ff */
/*0830*/ UIADD3.X UR4, UR4, UR8, URZ, UP0, !UPT ; /* 0x0000000804047290 */
/* 0x000fe200087fe43f */
/*0840*/ IADD3.X R21, R21, UR8, RZ, P1, !PT ; /* 0x0000000815157c10 */
/* 0x000fce0008ffe4ff */
/*0850*/ @!P0 BRA 0x1d0 ; /* 0xfffff97000008947 */
/* 0x000fea000383ffff */
/*0860*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0870*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0880*/ BRA 0x880; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24Pixel_Shared_ConvolutionPiS_mm
.globl _Z24Pixel_Shared_ConvolutionPiS_mm
.p2align 8
.type _Z24Pixel_Shared_ConvolutionPiS_mm,@function
_Z24Pixel_Shared_ConvolutionPiS_mm:
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_lt_u64_e64 s2, s[8:9], 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_13
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_lshl_add_u32 v1, s15, 9, v0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v7, 2, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_cmp_eq_u32_e64 s0, 0x1ff, v0
v_mov_b32_e32 v16, 0
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_nc_u32_e32 v0, 4, v7
v_add_nc_u32_e32 v8, 0x80c, v7
v_add_nc_u32_e32 v9, 0x1014, v7
s_waitcnt lgkmcnt(0)
s_add_u32 s3, s4, 4
s_addc_u32 s16, s5, 0
s_cmp_lg_u32 s15, 0
v_add_co_u32 v12, s2, s6, v5
s_cselect_b32 s1, -1, 0
v_add_co_ci_u32_e64 v13, s2, s7, v6, s2
v_cndmask_b32_e64 v3, 0, 1, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_co_u32 v3, s1, v1, v3
v_sub_co_ci_u32_e64 v4, null, 0, 0, s1
v_add_co_u32 v10, s1, s4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v11, s1, s5, v6, s1
v_lshlrev_b64 v[14:15], 2, v[3:4]
v_cmp_ge_u64_e64 s1, s[10:11], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v14, s2, s4, v14
v_add_co_ci_u32_e64 v15, s2, s5, v15, s2
s_mov_b64 s[4:5], 1
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s12
s_cmp_eq_u64 s[4:5], s[8:9]
s_cbranch_scc1 .LBB0_13
.LBB0_3:
s_add_u32 s2, s4, -1
s_addc_u32 s12, s5, -1
s_mul_i32 s6, s2, s11
s_mul_hi_u32 s7, s2, s10
s_mul_i32 s12, s12, s10
s_add_i32 s6, s7, s6
s_mul_i32 s13, s4, s11
s_mul_hi_u32 s14, s4, s10
s_add_i32 s7, s6, s12
s_add_i32 s12, s14, s13
s_mul_i32 s13, s5, s10
s_mul_i32 s6, s2, s10
s_add_i32 s15, s12, s13
s_mul_i32 s14, s4, s10
s_lshl_b64 s[12:13], s[6:7], 2
s_lshl_b64 s[6:7], s[14:15], 2
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_mul_i32 s2, s4, s11
s_mul_hi_u32 s14, s4, s10
s_mul_i32 s15, s5, s10
s_add_i32 s14, s14, s2
v_add_co_u32 v5, s2, v10, s12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s2, s13, v11, s2
s_add_i32 s15, s14, s15
s_mul_i32 s14, s4, s10
v_add_co_u32 v17, s2, v10, s6
s_lshl_b64 s[14:15], s[14:15], 2
v_add_co_ci_u32_e64 v18, s2, s7, v11, s2
v_add_co_u32 v19, s2, v10, s14
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v20, s2, s15, v11, s2
s_clause 0x2
global_load_b32 v21, v[5:6], off
global_load_b32 v17, v[17:18], off
global_load_b32 v18, v[19:20], off
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
s_waitcnt vmcnt(2)
ds_store_b32 v0, v21
s_waitcnt vmcnt(1)
ds_store_b32 v8, v17
s_waitcnt vmcnt(0)
ds_store_b32 v9, v18
s_and_saveexec_b32 s17, vcc_lo
s_cbranch_execz .LBB0_5
v_add_co_u32 v5, s2, v14, s12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s2, s13, v15, s2
v_add_co_u32 v17, s2, v14, s6
v_add_co_ci_u32_e64 v18, s2, s7, v15, s2
v_add_co_u32 v19, s2, v14, s14
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v20, s2, s15, v15, s2
s_clause 0x2
global_load_b32 v21, v[5:6], off
global_load_b32 v17, v[17:18], off
global_load_b32 v18, v[19:20], off
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_waitcnt vmcnt(2)
ds_store_b32 v16, v21
s_waitcnt vmcnt(1)
ds_store_b32 v16, v17 offset:2056
s_waitcnt vmcnt(0)
ds_store_b32 v16, v18 offset:4112
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s17
s_and_saveexec_b32 s17, s0
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v19, s2, s3, v5
v_add_co_ci_u32_e64 v20, s2, s16, v6, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s2, v19, s12
v_add_co_ci_u32_e64 v6, s2, s13, v20, s2
v_add_co_u32 v17, s2, v19, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v18, s2, s7, v20, s2
v_add_co_u32 v19, s2, v19, s14
v_add_co_ci_u32_e64 v20, s2, s15, v20, s2
s_clause 0x2
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[17:18], off
global_load_b32 v17, v[19:20], off
s_waitcnt vmcnt(2)
ds_store_b32 v16, v5 offset:2052
s_waitcnt vmcnt(1)
ds_store_b32 v16, v6 offset:4108
s_waitcnt vmcnt(0)
ds_store_b32 v16, v17 offset:6164
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s17
v_mov_b32_e32 v5, 0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v17, v7
s_mov_b32 s17, 0
s_getpc_b64 s[12:13]
s_add_u32 s12, s12, kernel_cuda@rel32@lo+4
s_addc_u32 s13, s13, kernel_cuda@rel32@hi+12
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.p2align 6
.LBB0_8:
v_mov_b32_e32 v18, v17
s_mov_b64 s[14:15], 0
.p2align 6
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s18, s12, s14
s_addc_u32 s19, s13, s15
ds_load_b32 v19, v18
s_load_b32 s2, s[18:19], 0x0
v_add_nc_u32_e32 v18, 0x808, v18
s_add_u32 s14, s14, 4
s_addc_u32 s15, s15, 0
s_cmp_eq_u32 s14, 12
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v19, s2, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v20, 31, v19
v_add_co_u32 v5, s2, v5, v19
v_add_co_ci_u32_e64 v6, s2, v6, v20, s2
s_cbranch_scc0 .LBB0_9
s_add_i32 s17, s17, 1
v_add_nc_u32_e32 v17, 4, v17
s_add_u32 s12, s12, 12
s_addc_u32 s13, s13, 0
s_cmp_eq_u32 s17, 3
s_cbranch_scc0 .LBB0_8
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s12, s1
s_cbranch_execz .LBB0_2
v_cmp_lt_i64_e64 s2, 0, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, 0, v6, s2
v_cndmask_b32_e64 v5, 0, v5, s2
v_cmp_gt_u64_e64 s2, 0xff, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v17, 0xff, v5, s2
v_add_co_u32 v5, s2, v12, s6
v_add_co_ci_u32_e64 v6, s2, s7, v13, s2
global_store_b32 v[5:6], v17, off
s_branch .LBB0_2
.LBB0_13:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24Pixel_Shared_ConvolutionPiS_mm
.amdhsa_group_segment_fixed_size 6168
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24Pixel_Shared_ConvolutionPiS_mm, .Lfunc_end0-_Z24Pixel_Shared_ConvolutionPiS_mm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected kernel_cuda
.type kernel_cuda,@object
.section .bss,"aw",@nobits
.globl kernel_cuda
.p2align 4, 0x0
kernel_cuda:
.zero 36
.size kernel_cuda, 36
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym kernel_cuda
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 6168
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24Pixel_Shared_ConvolutionPiS_mm
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z24Pixel_Shared_ConvolutionPiS_mm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001510bc_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm
.type _Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm, @function
_Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24Pixel_Shared_ConvolutionPiS_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm, .-_Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm
.globl _Z24Pixel_Shared_ConvolutionPiS_mm
.type _Z24Pixel_Shared_ConvolutionPiS_mm, @function
_Z24Pixel_Shared_ConvolutionPiS_mm:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z24Pixel_Shared_ConvolutionPiS_mm, .-_Z24Pixel_Shared_ConvolutionPiS_mm
.globl asyncConvolution
.type asyncConvolution, @function
asyncConvolution:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rdi, %rbp
movq %rdi, 24(%rsp)
movq %rsi, %r12
movq %rsi, 32(%rsp)
movq %rdx, %rbx
movq %rdx, 40(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $24, %edi
call malloc@PLT
movq %rax, %r14
movl $24, %edi
call malloc@PLT
movq %rax, %r15
movq %r12, %rax
imulq %rbx, %rax
leaq 2048(,%rax,4), %rbx
movq 0(%rbp), %rdi
movl $2, %edx
movq %rbx, %rsi
call cudaHostRegister@PLT
movq 8(%rbp), %rdi
movl $2, %edx
movq %rbx, %rsi
call cudaHostRegister@PLT
movq 16(%rbp), %rdi
movl $2, %edx
movq %rbx, %rsi
call cudaHostRegister@PLT
movq %rbx, %rsi
movq %r15, %rdi
call cudaMalloc@PLT
leaq 8(%r15), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%r15), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %rbx, %rsi
movq %r14, %rdi
call cudaMalloc@PLT
leaq 8(%r14), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%r14), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %r8d
movl $0, %ecx
movl $36, %edx
leaq kernel_host(%rip), %rsi
leaq _ZL11kernel_cuda(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq -2(%r12), %rdx
movq %rdx, %rcx
shrq $9, %rcx
movq %rcx, %rax
addq $1, %rax
testl $511, %edx
cmove %rcx, %rax
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $512, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
leaq -2048(%rbx), %rax
movq %rax, 8(%rsp)
leaq 96(%rsp), %rbx
movq %r14, %r13
movq %r15, %r12
leaq 120(%rsp), %rax
movq %rax, 16(%rsp)
movq %r14, 48(%rsp)
movq %r15, 56(%rsp)
jmp .L15
.L14:
movq (%r12), %rsi
movq (%r15), %rdi
movq (%r14), %r8
movl $2, %ecx
movq 8(%rsp), %rdx
call cudaMemcpyAsync@PLT
movq (%r14), %rdi
call cudaStreamDestroy@PLT
addq $8, %rbx
addq $8, %rbp
addq $8, %r13
addq $8, %r12
movq 16(%rsp), %rax
cmpq %rax, %rbx
je .L21
.L15:
movq %rbx, %r14
movq %rbx, %rdi
call cudaStreamCreate@PLT
movq %rbp, %r15
movq 0(%rbp), %rsi
movq 0(%r13), %rdi
movq (%rbx), %r8
movl $1, %ecx
movq 8(%rsp), %rdx
call cudaMemcpyAsync@PLT
movl 92(%rsp), %ecx
movq (%rbx), %r9
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movq (%r12), %rsi
movq 0(%r13), %rdi
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
call _Z48__device_stub__Z24Pixel_Shared_ConvolutionPiS_mmPiS_mm
jmp .L14
.L21:
movq 48(%rsp), %r14
movq 56(%rsp), %r15
movl $0, %ebx
.L16:
movq (%r15,%rbx), %rdi
call cudaFree@PLT
movq (%r14,%rbx), %rdi
call cudaFree@PLT
addq $8, %rbx
cmpq $24, %rbx
jne .L16
call cudaDeviceReset@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
movq 24(%rsp), %rax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size asyncConvolution, .-asyncConvolution
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24Pixel_Shared_ConvolutionPiS_mm"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "kernel_cuda"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24Pixel_Shared_ConvolutionPiS_mm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11kernel_cuda(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl kernel_host
.data
.align 32
.type kernel_host, @object
.size kernel_host, 36
kernel_host:
.long -1
.long -1
.long -1
.long -1
.long 9
.long -1
.long -1
.long -1
.long -1
.local _ZL11kernel_cuda
.comm _ZL11kernel_cuda,36,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda.hip"
.globl _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm # -- Begin function _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
.p2align 4, 0x90
.type _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm,@function
_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm: # @_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24Pixel_Shared_ConvolutionPiS_mm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm, .Lfunc_end0-_Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
.cfi_endproc
# -- End function
.globl asyncConvolution # -- Begin function asyncConvolution
.p2align 4, 0x90
.type asyncConvolution,@function
asyncConvolution: # @asyncConvolution
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r12
movq %rsi, %r13
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, %rbx
movl $24, %edi
callq malloc
movq %rax, %r14
movl $24, %edi
callq malloc
movq %rax, %r15
movq (%rbx), %rdi
movq %r12, 16(%rsp) # 8-byte Spill
imulq %r12, %r13
leaq 2048(,%r13,4), %r12
shlq $2, %r13
movq %r12, %rsi
movl $2, %edx
callq hipHostRegister
movq 8(%rbx), %rdi
movq %r12, %rsi
movl $2, %edx
callq hipHostRegister
movq 16(%rbx), %rdi
movq %r12, %rsi
movl $2, %edx
callq hipHostRegister
movq %r15, %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%r15), %rdi
movq %r12, %rsi
callq hipMalloc
movq %r15, %rdi
addq $16, %rdi
movq %r12, %rsi
callq hipMalloc
movq %r14, %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%r14), %rdi
movq %r12, %rsi
callq hipMalloc
movq %r14, %rdi
addq $16, %rdi
movq %r12, %rsi
callq hipMalloc
xorl %ebp, %ebp
movl $kernel_cuda, %edi
movl $kernel_host, %esi
movl $36, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq 8(%rsp), %rax # 8-byte Reload
leaq -2(%rax), %r12
movl %r12d, %eax
andl $511, %eax # imm = 0x1FF
shrq $9, %r12
cmpq $1, %rax
sbbl $-1, %r12d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
addq $512, %rax # imm = 0x200
movq %rax, 24(%rsp) # 8-byte Spill
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movq (%rbx,%rbp), %rdi
movq (%r15,%rbp), %rsi
movq 112(%rsp,%rbp), %r8
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpyAsync
movq 112(%rsp,%rbp), %rdi
callq hipStreamDestroy
addq $8, %rbp
cmpq $24, %rbp
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbp), %rdi
addq $112, %rdi
callq hipStreamCreate
movq (%r14,%rbp), %rdi
movq (%rbx,%rbp), %rsi
movq 112(%rsp,%rbp), %r8
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 112(%rsp,%rbp), %r9
movq %r12, %rdi
movl $1, %esi
movq 24(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movq (%r14,%rbp), %rax
movq (%r15,%rbp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movq %rax, 88(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movq %rax, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z24Pixel_Shared_ConvolutionPiS_mm, %edi
leaq 144(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_3
.LBB1_4: # %.preheader.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%r15,%r12,8), %rdi
callq hipFree
movq (%r14,%r12,8), %rdi
callq hipFree
incq %r12
cmpq $3, %r12
jne .LBB1_5
# %bb.6:
callq hipDeviceReset
movq %rbx, %rax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size asyncConvolution, .Lfunc_end1-asyncConvolution
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24Pixel_Shared_ConvolutionPiS_mm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $kernel_cuda, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel_cuda,@object # @kernel_cuda
.local kernel_cuda
.comm kernel_cuda,36,16
.type kernel_host,@object # @kernel_host
.data
.globl kernel_host
.p2align 4, 0x0
kernel_host:
.long 4294967295 # 0xffffffff
.long 4294967295 # 0xffffffff
.long 4294967295 # 0xffffffff
.long 4294967295 # 0xffffffff
.long 9 # 0x9
.long 4294967295 # 0xffffffff
.long 4294967295 # 0xffffffff
.long 4294967295 # 0xffffffff
.long 4294967295 # 0xffffffff
.size kernel_host, 36
.type _Z24Pixel_Shared_ConvolutionPiS_mm,@object # @_Z24Pixel_Shared_ConvolutionPiS_mm
.section .rodata,"a",@progbits
.globl _Z24Pixel_Shared_ConvolutionPiS_mm
.p2align 3, 0x0
_Z24Pixel_Shared_ConvolutionPiS_mm:
.quad _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
.size _Z24Pixel_Shared_ConvolutionPiS_mm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24Pixel_Shared_ConvolutionPiS_mm"
.size .L__unnamed_1, 35
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "kernel_cuda"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__Pixel_Shared_ConvolutionPiS_mm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel_cuda
.addrsig_sym kernel_host
.addrsig_sym _Z24Pixel_Shared_ConvolutionPiS_mm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* The code is described in this paper: Ouyang M, Sorting sixteen
* numbers. Proceedings of IEEE High Performance Extreme Computing
* Conference (HPEC), 2015, 1-6.
*
* Copyright (c) 2015 Ming Ouyang
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#define NoOP 0xFFFFFFFFu
#define TwoTo16 0x00010000u
#define BlockSize 256
#define min(x,y) ((x) < (y) ? (x) : (y))
#define max(x,y) ((x) > (y) ? (x) : (y))
int deviceNum = 0;
int dataSize = 16 * TwoTo16;
int *data, *sorted, *gpuData;
void initGPU(void) {
cudaSetDevice(deviceNum);
cudaMalloc((void**) &gpuData, sizeof(int) * dataSize);
}
void init(int argc, char *argv[]) {
unsigned i, j, k, tmp;
int c;
while ((c = getopt(argc, argv, "d:")) != -1)
switch (c) {
case 'd':
sscanf(optarg, "%d", &deviceNum);
break;
default:
break;
}
data = (int*) malloc(sizeof(int) * dataSize);
sorted = (int*) malloc(sizeof(int) * dataSize);
j = 0;
for (i = 0; i < TwoTo16; i++) {
tmp = i;
for (k = 0; k < 16; k++) {
data[j++] = tmp & 0x00000001u;
tmp = tmp >> 1;
}
}
initGPU();
}
void verify(void) {
unsigned i, j, k, count;
count = 0;
for (i = 0; i < TwoTo16; i++) {
for (j = 0; j < 15; j++) {
if (sorted[i * 16 + j] > sorted[i * 16 + j + 1]) {
printf("not sorted %d:", i);
for (k = 0; k < 16; k++)
printf(" %d", sorted[i * 16 + k]);
printf("\n");
if (count++ == 10)
exit(1);
}
}
}
}
__device__ inline void IntComparator(int &A, int &B) {
int t;
if (A > B) {
t = A;
A = B;
B = t;
}
}
__device__ inline void UnsignedComparator(unsigned &A, unsigned &B) {
unsigned t;
if (A > B) {
t = A;
A = B;
B = t;
}
}
//Nvidia's implementation of Batcher's sorting network
__global__ void nvidiaBatcher(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned pos, size, stride, offset;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
__syncthreads();
#pragma unroll
for (size = 2; size <= 16; size <<= 1) {
stride = size >> 1;
offset = threadIdx.x & (stride - 1);
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
IntComparator(sX[pos], sX[pos + stride]);
stride >>= 1;
for (; stride > 0; stride >>= 1) {
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
if (offset >= stride) //divergent computation
IntComparator(sX[pos - stride], sX[pos]);
}
}
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
//divergent computation in Nvidia's implementation is removed
__global__ void newBatcher(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned pos, size, stride, offset;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
__syncthreads();
#pragma unroll
for (size = 2; size <= 16; size <<= 1) {
stride = size >> 1;
offset = threadIdx.x & (stride - 1);
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
IntComparator(sX[pos], sX[pos+stride]);
stride >>= 1;
for (; stride > 0; stride >>= 1) {
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
//non-divergent computation
IntComparator(sX[pos - stride * (offset >= stride ? 1 : 0)], sX[pos]);
}
}
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
//Van Voorhis's optimal sorting network for 16 numbers
__global__ void VanVoorhis(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned wire1, wire2, our16tuple;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
our16tuple = (threadIdx.x >> 3) << 4;
__syncthreads();
//step I
wire1 = ((threadIdx.x & 7) << 1) + our16tuple;
wire2 = wire1 + 1;
IntComparator(sX[wire1], sX[wire2]);
//step II
wire1 = (((threadIdx.x & 6) << 1) | (threadIdx.x & 1)) + our16tuple;
wire2 = wire1 + 2;
IntComparator(sX[wire1], sX[wire2]);
//step III
wire1 = (((threadIdx.x & 4) << 1) | (threadIdx.x & 3)) + our16tuple;
wire2 = wire1 + 4;
IntComparator(sX[wire1], sX[wire2]);
//step IV
wire1 = (threadIdx.x & 7) + our16tuple;
wire2 = wire1 + 8;
IntComparator(sX[wire1], sX[wire2]);
//step V
wire1 = threadIdx.x & 7;
wire1 = (wire1 == 2) ? 13 : wire1;
wire2 = ((wire1 << 1) & 10) | ((wire1 >> 1) & 5);
wire2 = (wire1 == wire2) ? (wire2 ^ 15) : wire2;
wire1 += our16tuple;
wire2 += our16tuple;
IntComparator(sX[wire1], sX[wire2]);
//step VI
wire1 = threadIdx.x & 7;
wire2 = ((wire1 << 1) - (wire1 & 1)) << (!(wire1 >> 2));
wire2 = (wire1 == 0) ? 15 : wire2;
wire2 = (wire1 == 1) ? 4 : wire2;
if (wire1 == 4){
wire1 = wire1 ^ 15;
wire2 = wire1 + 3;
}
wire1 += our16tuple;
wire2 += our16tuple;
IntComparator(sX[wire1], sX[wire2]);
//step VII
wire1 = (((threadIdx.x & 6) << 1) | (threadIdx.x & 1) | 2) + our16tuple;
wire2 = (((((threadIdx.x & 6) << 1) | (threadIdx.x & 1) | 2) + 2) & 15)
+ our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
//step VIII
wire1 = ((threadIdx.x & 7) << 1) + 1 + our16tuple;
wire2 = ((((threadIdx.x & 7) << 1) + 4) & 15) + our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
//step IX
wire1 = ((threadIdx.x & 7) << 1) + 1 + our16tuple;
wire2 = ((((threadIdx.x & 7) << 1) + 2) & 15) + our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
int main(int argc, char *argv[]) {
cudaEvent_t start;
cudaEvent_t stop;
float msec;
init(argc, argv);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(gpuData, data, sizeof(int) * dataSize, cudaMemcpyHostToDevice);
cudaEventRecord(start, NULL);
nvidiaBatcher <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
cudaDeviceSynchronize();
cudaEventRecord(stop, NULL);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&msec, start, stop);
printf("Nvd Batcher, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
cudaMemcpy(sorted, gpuData, sizeof(int) * dataSize, cudaMemcpyDeviceToHost);
verify();
cudaMemcpy(gpuData, data, sizeof(int) * dataSize, cudaMemcpyHostToDevice);
cudaEventRecord(start, NULL);
VanVoorhis <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
cudaDeviceSynchronize();
cudaEventRecord(stop, NULL);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&msec, start, stop);
printf("Van Voorhis, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
cudaMemcpy(sorted, gpuData, sizeof(int) * dataSize, cudaMemcpyDeviceToHost);
verify();
cudaMemcpy(gpuData, data, sizeof(int) * dataSize, cudaMemcpyHostToDevice);
cudaEventRecord(start, NULL);
newBatcher <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
cudaDeviceSynchronize();
cudaEventRecord(stop, NULL);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&msec, start, stop);
printf("new Batcher, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
cudaMemcpy(sorted, gpuData, sizeof(int) * dataSize, cudaMemcpyDeviceToHost);
verify();
return 0;
} | .file "tmpxft_0014b71e_00000000-6_sort16.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2078:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7initGPUv
.type _Z7initGPUv, @function
_Z7initGPUv:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl deviceNum(%rip), %edi
call cudaSetDevice@PLT
movslq dataSize(%rip), %rsi
salq $2, %rsi
leaq gpuData(%rip), %rdi
call cudaMalloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _Z7initGPUv, .-_Z7initGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "d:"
.text
.globl _Z4initiPPc
.type _Z4initiPPc, @function
_Z4initiPPc:
.LFB2071:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %r12d
movq %rsi, %rbx
leaq .LC1(%rip), %rbp
.L7:
movq %rbp, %rdx
movq %rbx, %rsi
movl %r12d, %edi
call getopt@PLT
cmpl $-1, %eax
je .L15
cmpl $100, %eax
jne .L7
leaq deviceNum(%rip), %rdx
leaq .LC0(%rip), %rsi
movq optarg(%rip), %rdi
movl $0, %eax
call __isoc23_sscanf@PLT
jmp .L7
.L15:
movslq dataSize(%rip), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, data(%rip)
movq %rbx, %rdi
call malloc@PLT
movq %rax, sorted(%rip)
movl $16, %r8d
movl $0, %r9d
jmp .L9
.L16:
addl $1, %r9d
addl $16, %r8d
cmpl $1048592, %r8d
je .L11
.L9:
leal -16(%r8), %eax
movl %r9d, %ecx
.L10:
movl %eax, %edx
addl $1, %eax
movl %edx, %edx
movl %ecx, %edi
andl $1, %edi
movq data(%rip), %rsi
movl %edi, (%rsi,%rdx,4)
shrl %ecx
cmpl %eax, %r8d
jne .L10
jmp .L16
.L11:
call _Z7initGPUv
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z4initiPPc, .-_Z4initiPPc
.section .rodata.str1.1
.LC2:
.string "not sorted %d:"
.LC3:
.string " %d"
.LC4:
.string "\n"
.text
.globl _Z6verifyv
.type _Z6verifyv, @function
_Z6verifyv:
.LFB2072:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $64, %r12d
movl $60, %r14d
movl $0, %r15d
movl $0, 4(%rsp)
leaq .LC3(%rip), %r13
jmp .L18
.L29:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal 1(%r15), %eax
cmpl $10, %r15d
je .L27
movl %eax, %r15d
.L19:
cmpq %r14, %rbp
je .L28
.L21:
movq sorted(%rip), %rax
movl (%rax,%rbp), %edx
addq $4, %rbp
cmpl (%rax,%rbp), %edx
jle .L19
movl 4(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rbx
.L20:
movq sorted(%rip), %rax
movl (%rax,%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
jmp .L29
.L27:
movl $1, %edi
call exit@PLT
.L28:
addl $1, 4(%rsp)
movl 4(%rsp), %eax
addq $64, %r14
addq $64, %r12
cmpl $65536, %eax
je .L17
.L18:
leaq -64(%r12), %rax
movq %rax, 8(%rsp)
movq %rax, %rbp
jmp .L21
.L17:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _Z6verifyv, .-_Z6verifyv
.globl _Z33__device_stub__Z13nvidiaBatcherPiPi
.type _Z33__device_stub__Z13nvidiaBatcherPiPi, @function
_Z33__device_stub__Z13nvidiaBatcherPiPi:
.LFB2100:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13nvidiaBatcherPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z33__device_stub__Z13nvidiaBatcherPiPi, .-_Z33__device_stub__Z13nvidiaBatcherPiPi
.globl _Z13nvidiaBatcherPi
.type _Z13nvidiaBatcherPi, @function
_Z13nvidiaBatcherPi:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13nvidiaBatcherPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z13nvidiaBatcherPi, .-_Z13nvidiaBatcherPi
.globl _Z30__device_stub__Z10newBatcherPiPi
.type _Z30__device_stub__Z10newBatcherPiPi, @function
_Z30__device_stub__Z10newBatcherPiPi:
.LFB2102:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L42
.L38:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10newBatcherPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L38
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2102:
.size _Z30__device_stub__Z10newBatcherPiPi, .-_Z30__device_stub__Z10newBatcherPiPi
.globl _Z10newBatcherPi
.type _Z10newBatcherPi, @function
_Z10newBatcherPi:
.LFB2103:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10newBatcherPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _Z10newBatcherPi, .-_Z10newBatcherPi
.globl _Z30__device_stub__Z10VanVoorhisPiPi
.type _Z30__device_stub__Z10VanVoorhisPiPi, @function
_Z30__device_stub__Z10VanVoorhisPiPi:
.LFB2104:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L50
.L46:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10VanVoorhisPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L46
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2104:
.size _Z30__device_stub__Z10VanVoorhisPiPi, .-_Z30__device_stub__Z10VanVoorhisPiPi
.globl _Z10VanVoorhisPi
.type _Z10VanVoorhisPi, @function
_Z10VanVoorhisPi:
.LFB2105:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10VanVoorhisPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2105:
.size _Z10VanVoorhisPi, .-_Z10VanVoorhisPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Nvd Batcher, blocksize %d, device %d, %.3f ms\n"
.align 8
.LC6:
.string "Van Voorhis, blocksize %d, device %d, %.3f ms\n"
.align 8
.LC7:
.string "new Batcher, blocksize %d, device %d, %.3f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2075:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call _Z4initiPPc
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movslq dataSize(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq data(%rip), %rsi
movq gpuData(%rip), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl dataSize(%rip), %edx
leal 511(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L60
.L55:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movl deviceNum(%rip), %ecx
movl $256, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq dataSize(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq gpuData(%rip), %rsi
movq sorted(%rip), %rdi
call cudaMemcpy@PLT
call _Z6verifyv
movslq dataSize(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq data(%rip), %rsi
movq gpuData(%rip), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl dataSize(%rip), %edx
leal 511(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L56:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movl deviceNum(%rip), %ecx
movl $256, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq dataSize(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq gpuData(%rip), %rsi
movq sorted(%rip), %rdi
call cudaMemcpy@PLT
call _Z6verifyv
movslq dataSize(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq data(%rip), %rsi
movq gpuData(%rip), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl dataSize(%rip), %edx
leal 511(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L57:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movl deviceNum(%rip), %ecx
movl $256, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq dataSize(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq gpuData(%rip), %rsi
movq sorted(%rip), %rdi
call cudaMemcpy@PLT
call _Z6verifyv
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
movq gpuData(%rip), %rdi
call _Z33__device_stub__Z13nvidiaBatcherPiPi
jmp .L55
.L61:
movq gpuData(%rip), %rdi
call _Z30__device_stub__Z10VanVoorhisPiPi
jmp .L56
.L62:
movq gpuData(%rip), %rdi
call _Z30__device_stub__Z10newBatcherPiPi
jmp .L57
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2075:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z10VanVoorhisPi"
.LC9:
.string "_Z10newBatcherPi"
.LC10:
.string "_Z13nvidiaBatcherPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2107:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10VanVoorhisPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10newBatcherPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z13nvidiaBatcherPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl gpuData
.bss
.align 8
.type gpuData, @object
.size gpuData, 8
gpuData:
.zero 8
.globl sorted
.align 8
.type sorted, @object
.size sorted, 8
sorted:
.zero 8
.globl data
.align 8
.type data, @object
.size data, 8
data:
.zero 8
.globl dataSize
.data
.align 4
.type dataSize, @object
.size dataSize, 4
dataSize:
.long 1048576
.globl deviceNum
.bss
.align 4
.type deviceNum, @object
.size deviceNum, 4
deviceNum:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* The code is described in this paper: Ouyang M, Sorting sixteen
* numbers. Proceedings of IEEE High Performance Extreme Computing
* Conference (HPEC), 2015, 1-6.
*
* Copyright (c) 2015 Ming Ouyang
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#define NoOP 0xFFFFFFFFu
#define TwoTo16 0x00010000u
#define BlockSize 256
#define min(x,y) ((x) < (y) ? (x) : (y))
#define max(x,y) ((x) > (y) ? (x) : (y))
int deviceNum = 0;
int dataSize = 16 * TwoTo16;
int *data, *sorted, *gpuData;
void initGPU(void) {
cudaSetDevice(deviceNum);
cudaMalloc((void**) &gpuData, sizeof(int) * dataSize);
}
void init(int argc, char *argv[]) {
unsigned i, j, k, tmp;
int c;
while ((c = getopt(argc, argv, "d:")) != -1)
switch (c) {
case 'd':
sscanf(optarg, "%d", &deviceNum);
break;
default:
break;
}
data = (int*) malloc(sizeof(int) * dataSize);
sorted = (int*) malloc(sizeof(int) * dataSize);
j = 0;
for (i = 0; i < TwoTo16; i++) {
tmp = i;
for (k = 0; k < 16; k++) {
data[j++] = tmp & 0x00000001u;
tmp = tmp >> 1;
}
}
initGPU();
}
void verify(void) {
unsigned i, j, k, count;
count = 0;
for (i = 0; i < TwoTo16; i++) {
for (j = 0; j < 15; j++) {
if (sorted[i * 16 + j] > sorted[i * 16 + j + 1]) {
printf("not sorted %d:", i);
for (k = 0; k < 16; k++)
printf(" %d", sorted[i * 16 + k]);
printf("\n");
if (count++ == 10)
exit(1);
}
}
}
}
__device__ inline void IntComparator(int &A, int &B) {
int t;
if (A > B) {
t = A;
A = B;
B = t;
}
}
__device__ inline void UnsignedComparator(unsigned &A, unsigned &B) {
unsigned t;
if (A > B) {
t = A;
A = B;
B = t;
}
}
//Nvidia's implementation of Batcher's sorting network
__global__ void nvidiaBatcher(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned pos, size, stride, offset;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
__syncthreads();
#pragma unroll
for (size = 2; size <= 16; size <<= 1) {
stride = size >> 1;
offset = threadIdx.x & (stride - 1);
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
IntComparator(sX[pos], sX[pos + stride]);
stride >>= 1;
for (; stride > 0; stride >>= 1) {
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
if (offset >= stride) //divergent computation
IntComparator(sX[pos - stride], sX[pos]);
}
}
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
//divergent computation in Nvidia's implementation is removed
__global__ void newBatcher(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned pos, size, stride, offset;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
__syncthreads();
#pragma unroll
for (size = 2; size <= 16; size <<= 1) {
stride = size >> 1;
offset = threadIdx.x & (stride - 1);
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
IntComparator(sX[pos], sX[pos+stride]);
stride >>= 1;
for (; stride > 0; stride >>= 1) {
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
//non-divergent computation
IntComparator(sX[pos - stride * (offset >= stride ? 1 : 0)], sX[pos]);
}
}
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
//Van Voorhis's optimal sorting network for 16 numbers
__global__ void VanVoorhis(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned wire1, wire2, our16tuple;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
our16tuple = (threadIdx.x >> 3) << 4;
__syncthreads();
//step I
wire1 = ((threadIdx.x & 7) << 1) + our16tuple;
wire2 = wire1 + 1;
IntComparator(sX[wire1], sX[wire2]);
//step II
wire1 = (((threadIdx.x & 6) << 1) | (threadIdx.x & 1)) + our16tuple;
wire2 = wire1 + 2;
IntComparator(sX[wire1], sX[wire2]);
//step III
wire1 = (((threadIdx.x & 4) << 1) | (threadIdx.x & 3)) + our16tuple;
wire2 = wire1 + 4;
IntComparator(sX[wire1], sX[wire2]);
//step IV
wire1 = (threadIdx.x & 7) + our16tuple;
wire2 = wire1 + 8;
IntComparator(sX[wire1], sX[wire2]);
//step V
wire1 = threadIdx.x & 7;
wire1 = (wire1 == 2) ? 13 : wire1;
wire2 = ((wire1 << 1) & 10) | ((wire1 >> 1) & 5);
wire2 = (wire1 == wire2) ? (wire2 ^ 15) : wire2;
wire1 += our16tuple;
wire2 += our16tuple;
IntComparator(sX[wire1], sX[wire2]);
//step VI
wire1 = threadIdx.x & 7;
wire2 = ((wire1 << 1) - (wire1 & 1)) << (!(wire1 >> 2));
wire2 = (wire1 == 0) ? 15 : wire2;
wire2 = (wire1 == 1) ? 4 : wire2;
if (wire1 == 4){
wire1 = wire1 ^ 15;
wire2 = wire1 + 3;
}
wire1 += our16tuple;
wire2 += our16tuple;
IntComparator(sX[wire1], sX[wire2]);
//step VII
wire1 = (((threadIdx.x & 6) << 1) | (threadIdx.x & 1) | 2) + our16tuple;
wire2 = (((((threadIdx.x & 6) << 1) | (threadIdx.x & 1) | 2) + 2) & 15)
+ our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
//step VIII
wire1 = ((threadIdx.x & 7) << 1) + 1 + our16tuple;
wire2 = ((((threadIdx.x & 7) << 1) + 4) & 15) + our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
//step IX
wire1 = ((threadIdx.x & 7) << 1) + 1 + our16tuple;
wire2 = ((((threadIdx.x & 7) << 1) + 2) & 15) + our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
int main(int argc, char *argv[]) {
cudaEvent_t start;
cudaEvent_t stop;
float msec;
init(argc, argv);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMemcpy(gpuData, data, sizeof(int) * dataSize, cudaMemcpyHostToDevice);
cudaEventRecord(start, NULL);
nvidiaBatcher <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
cudaDeviceSynchronize();
cudaEventRecord(stop, NULL);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&msec, start, stop);
printf("Nvd Batcher, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
cudaMemcpy(sorted, gpuData, sizeof(int) * dataSize, cudaMemcpyDeviceToHost);
verify();
cudaMemcpy(gpuData, data, sizeof(int) * dataSize, cudaMemcpyHostToDevice);
cudaEventRecord(start, NULL);
VanVoorhis <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
cudaDeviceSynchronize();
cudaEventRecord(stop, NULL);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&msec, start, stop);
printf("Van Voorhis, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
cudaMemcpy(sorted, gpuData, sizeof(int) * dataSize, cudaMemcpyDeviceToHost);
verify();
cudaMemcpy(gpuData, data, sizeof(int) * dataSize, cudaMemcpyHostToDevice);
cudaEventRecord(start, NULL);
newBatcher <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
cudaDeviceSynchronize();
cudaEventRecord(stop, NULL);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&msec, start, stop);
printf("new Batcher, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
cudaMemcpy(sorted, gpuData, sizeof(int) * dataSize, cudaMemcpyDeviceToHost);
verify();
return 0;
} | /* The code is described in this paper: Ouyang M, Sorting sixteen
* numbers. Proceedings of IEEE High Performance Extreme Computing
* Conference (HPEC), 2015, 1-6.
*
* Copyright (c) 2015 Ming Ouyang
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#define NoOP 0xFFFFFFFFu
#define TwoTo16 0x00010000u
#define BlockSize 256
#define min(x,y) ((x) < (y) ? (x) : (y))
#define max(x,y) ((x) > (y) ? (x) : (y))
int deviceNum = 0;
int dataSize = 16 * TwoTo16;
int *data, *sorted, *gpuData;
void initGPU(void) {
hipSetDevice(deviceNum);
hipMalloc((void**) &gpuData, sizeof(int) * dataSize);
}
void init(int argc, char *argv[]) {
unsigned i, j, k, tmp;
int c;
while ((c = getopt(argc, argv, "d:")) != -1)
switch (c) {
case 'd':
sscanf(optarg, "%d", &deviceNum);
break;
default:
break;
}
data = (int*) malloc(sizeof(int) * dataSize);
sorted = (int*) malloc(sizeof(int) * dataSize);
j = 0;
for (i = 0; i < TwoTo16; i++) {
tmp = i;
for (k = 0; k < 16; k++) {
data[j++] = tmp & 0x00000001u;
tmp = tmp >> 1;
}
}
initGPU();
}
void verify(void) {
unsigned i, j, k, count;
count = 0;
for (i = 0; i < TwoTo16; i++) {
for (j = 0; j < 15; j++) {
if (sorted[i * 16 + j] > sorted[i * 16 + j + 1]) {
printf("not sorted %d:", i);
for (k = 0; k < 16; k++)
printf(" %d", sorted[i * 16 + k]);
printf("\n");
if (count++ == 10)
exit(1);
}
}
}
}
__device__ inline void IntComparator(int &A, int &B) {
int t;
if (A > B) {
t = A;
A = B;
B = t;
}
}
__device__ inline void UnsignedComparator(unsigned &A, unsigned &B) {
unsigned t;
if (A > B) {
t = A;
A = B;
B = t;
}
}
//Nvidia's implementation of Batcher's sorting network
__global__ void nvidiaBatcher(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned pos, size, stride, offset;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
__syncthreads();
#pragma unroll
for (size = 2; size <= 16; size <<= 1) {
stride = size >> 1;
offset = threadIdx.x & (stride - 1);
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
IntComparator(sX[pos], sX[pos + stride]);
stride >>= 1;
for (; stride > 0; stride >>= 1) {
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
if (offset >= stride) //divergent computation
IntComparator(sX[pos - stride], sX[pos]);
}
}
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
//divergent computation in Nvidia's implementation is removed
__global__ void newBatcher(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned pos, size, stride, offset;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
__syncthreads();
#pragma unroll
for (size = 2; size <= 16; size <<= 1) {
stride = size >> 1;
offset = threadIdx.x & (stride - 1);
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
IntComparator(sX[pos], sX[pos+stride]);
stride >>= 1;
for (; stride > 0; stride >>= 1) {
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
//non-divergent computation
IntComparator(sX[pos - stride * (offset >= stride ? 1 : 0)], sX[pos]);
}
}
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
//Van Voorhis's optimal sorting network for 16 numbers
__global__ void VanVoorhis(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned wire1, wire2, our16tuple;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
our16tuple = (threadIdx.x >> 3) << 4;
__syncthreads();
//step I
wire1 = ((threadIdx.x & 7) << 1) + our16tuple;
wire2 = wire1 + 1;
IntComparator(sX[wire1], sX[wire2]);
//step II
wire1 = (((threadIdx.x & 6) << 1) | (threadIdx.x & 1)) + our16tuple;
wire2 = wire1 + 2;
IntComparator(sX[wire1], sX[wire2]);
//step III
wire1 = (((threadIdx.x & 4) << 1) | (threadIdx.x & 3)) + our16tuple;
wire2 = wire1 + 4;
IntComparator(sX[wire1], sX[wire2]);
//step IV
wire1 = (threadIdx.x & 7) + our16tuple;
wire2 = wire1 + 8;
IntComparator(sX[wire1], sX[wire2]);
//step V
wire1 = threadIdx.x & 7;
wire1 = (wire1 == 2) ? 13 : wire1;
wire2 = ((wire1 << 1) & 10) | ((wire1 >> 1) & 5);
wire2 = (wire1 == wire2) ? (wire2 ^ 15) : wire2;
wire1 += our16tuple;
wire2 += our16tuple;
IntComparator(sX[wire1], sX[wire2]);
//step VI
wire1 = threadIdx.x & 7;
wire2 = ((wire1 << 1) - (wire1 & 1)) << (!(wire1 >> 2));
wire2 = (wire1 == 0) ? 15 : wire2;
wire2 = (wire1 == 1) ? 4 : wire2;
if (wire1 == 4){
wire1 = wire1 ^ 15;
wire2 = wire1 + 3;
}
wire1 += our16tuple;
wire2 += our16tuple;
IntComparator(sX[wire1], sX[wire2]);
//step VII
wire1 = (((threadIdx.x & 6) << 1) | (threadIdx.x & 1) | 2) + our16tuple;
wire2 = (((((threadIdx.x & 6) << 1) | (threadIdx.x & 1) | 2) + 2) & 15)
+ our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
//step VIII
wire1 = ((threadIdx.x & 7) << 1) + 1 + our16tuple;
wire2 = ((((threadIdx.x & 7) << 1) + 4) & 15) + our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
//step IX
wire1 = ((threadIdx.x & 7) << 1) + 1 + our16tuple;
wire2 = ((((threadIdx.x & 7) << 1) + 2) & 15) + our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
int main(int argc, char *argv[]) {
hipEvent_t start;
hipEvent_t stop;
float msec;
init(argc, argv);
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(gpuData, data, sizeof(int) * dataSize, hipMemcpyHostToDevice);
hipEventRecord(start, NULL);
nvidiaBatcher <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
hipDeviceSynchronize();
hipEventRecord(stop, NULL);
hipEventSynchronize(stop);
hipEventElapsedTime(&msec, start, stop);
printf("Nvd Batcher, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
hipMemcpy(sorted, gpuData, sizeof(int) * dataSize, hipMemcpyDeviceToHost);
verify();
hipMemcpy(gpuData, data, sizeof(int) * dataSize, hipMemcpyHostToDevice);
hipEventRecord(start, NULL);
VanVoorhis <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
hipDeviceSynchronize();
hipEventRecord(stop, NULL);
hipEventSynchronize(stop);
hipEventElapsedTime(&msec, start, stop);
printf("Van Voorhis, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
hipMemcpy(sorted, gpuData, sizeof(int) * dataSize, hipMemcpyDeviceToHost);
verify();
hipMemcpy(gpuData, data, sizeof(int) * dataSize, hipMemcpyHostToDevice);
hipEventRecord(start, NULL);
newBatcher <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
hipDeviceSynchronize();
hipEventRecord(stop, NULL);
hipEventSynchronize(stop);
hipEventElapsedTime(&msec, start, stop);
printf("new Batcher, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
hipMemcpy(sorted, gpuData, sizeof(int) * dataSize, hipMemcpyDeviceToHost);
verify();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* The code is described in this paper: Ouyang M, Sorting sixteen
* numbers. Proceedings of IEEE High Performance Extreme Computing
* Conference (HPEC), 2015, 1-6.
*
* Copyright (c) 2015 Ming Ouyang
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#define NoOP 0xFFFFFFFFu
#define TwoTo16 0x00010000u
#define BlockSize 256
#define min(x,y) ((x) < (y) ? (x) : (y))
#define max(x,y) ((x) > (y) ? (x) : (y))
int deviceNum = 0;
int dataSize = 16 * TwoTo16;
int *data, *sorted, *gpuData;
void initGPU(void) {
hipSetDevice(deviceNum);
hipMalloc((void**) &gpuData, sizeof(int) * dataSize);
}
void init(int argc, char *argv[]) {
unsigned i, j, k, tmp;
int c;
while ((c = getopt(argc, argv, "d:")) != -1)
switch (c) {
case 'd':
sscanf(optarg, "%d", &deviceNum);
break;
default:
break;
}
data = (int*) malloc(sizeof(int) * dataSize);
sorted = (int*) malloc(sizeof(int) * dataSize);
j = 0;
for (i = 0; i < TwoTo16; i++) {
tmp = i;
for (k = 0; k < 16; k++) {
data[j++] = tmp & 0x00000001u;
tmp = tmp >> 1;
}
}
initGPU();
}
void verify(void) {
unsigned i, j, k, count;
count = 0;
for (i = 0; i < TwoTo16; i++) {
for (j = 0; j < 15; j++) {
if (sorted[i * 16 + j] > sorted[i * 16 + j + 1]) {
printf("not sorted %d:", i);
for (k = 0; k < 16; k++)
printf(" %d", sorted[i * 16 + k]);
printf("\n");
if (count++ == 10)
exit(1);
}
}
}
}
__device__ inline void IntComparator(int &A, int &B) {
int t;
if (A > B) {
t = A;
A = B;
B = t;
}
}
__device__ inline void UnsignedComparator(unsigned &A, unsigned &B) {
unsigned t;
if (A > B) {
t = A;
A = B;
B = t;
}
}
//Nvidia's implementation of Batcher's sorting network
__global__ void nvidiaBatcher(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned pos, size, stride, offset;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
__syncthreads();
#pragma unroll
for (size = 2; size <= 16; size <<= 1) {
stride = size >> 1;
offset = threadIdx.x & (stride - 1);
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
IntComparator(sX[pos], sX[pos + stride]);
stride >>= 1;
for (; stride > 0; stride >>= 1) {
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
if (offset >= stride) //divergent computation
IntComparator(sX[pos - stride], sX[pos]);
}
}
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
//divergent computation in Nvidia's implementation is removed
__global__ void newBatcher(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned pos, size, stride, offset;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
__syncthreads();
#pragma unroll
for (size = 2; size <= 16; size <<= 1) {
stride = size >> 1;
offset = threadIdx.x & (stride - 1);
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
IntComparator(sX[pos], sX[pos+stride]);
stride >>= 1;
for (; stride > 0; stride >>= 1) {
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
//non-divergent computation
IntComparator(sX[pos - stride * (offset >= stride ? 1 : 0)], sX[pos]);
}
}
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
//Van Voorhis's optimal sorting network for 16 numbers
__global__ void VanVoorhis(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned wire1, wire2, our16tuple;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
our16tuple = (threadIdx.x >> 3) << 4;
__syncthreads();
//step I
wire1 = ((threadIdx.x & 7) << 1) + our16tuple;
wire2 = wire1 + 1;
IntComparator(sX[wire1], sX[wire2]);
//step II
wire1 = (((threadIdx.x & 6) << 1) | (threadIdx.x & 1)) + our16tuple;
wire2 = wire1 + 2;
IntComparator(sX[wire1], sX[wire2]);
//step III
wire1 = (((threadIdx.x & 4) << 1) | (threadIdx.x & 3)) + our16tuple;
wire2 = wire1 + 4;
IntComparator(sX[wire1], sX[wire2]);
//step IV
wire1 = (threadIdx.x & 7) + our16tuple;
wire2 = wire1 + 8;
IntComparator(sX[wire1], sX[wire2]);
//step V
wire1 = threadIdx.x & 7;
wire1 = (wire1 == 2) ? 13 : wire1;
wire2 = ((wire1 << 1) & 10) | ((wire1 >> 1) & 5);
wire2 = (wire1 == wire2) ? (wire2 ^ 15) : wire2;
wire1 += our16tuple;
wire2 += our16tuple;
IntComparator(sX[wire1], sX[wire2]);
//step VI
wire1 = threadIdx.x & 7;
wire2 = ((wire1 << 1) - (wire1 & 1)) << (!(wire1 >> 2));
wire2 = (wire1 == 0) ? 15 : wire2;
wire2 = (wire1 == 1) ? 4 : wire2;
if (wire1 == 4){
wire1 = wire1 ^ 15;
wire2 = wire1 + 3;
}
wire1 += our16tuple;
wire2 += our16tuple;
IntComparator(sX[wire1], sX[wire2]);
//step VII
wire1 = (((threadIdx.x & 6) << 1) | (threadIdx.x & 1) | 2) + our16tuple;
wire2 = (((((threadIdx.x & 6) << 1) | (threadIdx.x & 1) | 2) + 2) & 15)
+ our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
//step VIII
wire1 = ((threadIdx.x & 7) << 1) + 1 + our16tuple;
wire2 = ((((threadIdx.x & 7) << 1) + 4) & 15) + our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
//step IX
wire1 = ((threadIdx.x & 7) << 1) + 1 + our16tuple;
wire2 = ((((threadIdx.x & 7) << 1) + 2) & 15) + our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
int main(int argc, char *argv[]) {
hipEvent_t start;
hipEvent_t stop;
float msec;
init(argc, argv);
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(gpuData, data, sizeof(int) * dataSize, hipMemcpyHostToDevice);
hipEventRecord(start, NULL);
nvidiaBatcher <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
hipDeviceSynchronize();
hipEventRecord(stop, NULL);
hipEventSynchronize(stop);
hipEventElapsedTime(&msec, start, stop);
printf("Nvd Batcher, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
hipMemcpy(sorted, gpuData, sizeof(int) * dataSize, hipMemcpyDeviceToHost);
verify();
hipMemcpy(gpuData, data, sizeof(int) * dataSize, hipMemcpyHostToDevice);
hipEventRecord(start, NULL);
VanVoorhis <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
hipDeviceSynchronize();
hipEventRecord(stop, NULL);
hipEventSynchronize(stop);
hipEventElapsedTime(&msec, start, stop);
printf("Van Voorhis, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
hipMemcpy(sorted, gpuData, sizeof(int) * dataSize, hipMemcpyDeviceToHost);
verify();
hipMemcpy(gpuData, data, sizeof(int) * dataSize, hipMemcpyHostToDevice);
hipEventRecord(start, NULL);
newBatcher <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
hipDeviceSynchronize();
hipEventRecord(stop, NULL);
hipEventSynchronize(stop);
hipEventElapsedTime(&msec, start, stop);
printf("new Batcher, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
hipMemcpy(sorted, gpuData, sizeof(int) * dataSize, hipMemcpyDeviceToHost);
verify();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13nvidiaBatcherPi
.globl _Z13nvidiaBatcherPi
.p2align 8
.type _Z13nvidiaBatcherPi,@function
_Z13nvidiaBatcherPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v1, s15, 9, v0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v7, 2, v0
v_lshlrev_b32_e32 v9, 3, v0
v_lshlrev_b32_e32 v8, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, 0x100, v1
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v6, vcc_lo
s_mov_b32 s0, exec_lo
s_clause 0x1
global_load_b32 v5, v[1:2], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v7, v5, v6 offset1:4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[5:6], v9 offset1:1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v5, v6
s_cbranch_execz .LBB0_2
v_or_b32_e32 v10, 4, v9
ds_store_b32 v9, v6
ds_store_b32 v10, v5
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_and_b32_e32 v9, 1, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v8, v9
v_lshlrev_b32_e32 v10, 2, v5
ds_load_2addr_b32 v[5:6], v10 offset1:2
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v5, v6
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v11, 8, v10
ds_store_b32 v10, v6
ds_store_b32 v11, v5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s0, exec_lo
v_cmpx_ne_u32_e32 0, v9
s_cbranch_execz .LBB0_7
v_lshlrev_b32_e32 v5, 2, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v6, -4, v5
ds_load_b32 v9, v6
ds_load_b32 v10, v5
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v9, v10
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
ds_store_b32 v6, v10
ds_store_b32 v5, v9
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
v_and_b32_e32 v10, 3, v0
s_mov_b32 s0, 2
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v8, v10
v_lshlrev_b32_e32 v9, 2, v5
ds_load_2addr_b32 v[5:6], v9 offset1:4
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v5, v6
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v11, 16, v9
ds_store_b32 v9, v6
ds_store_b32 v11, v5
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v9, 0x400, v7
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_11
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s1
s_lshr_b32 s1, s0, 1
s_cmp_gt_u32 s0, 1
s_mov_b32 s0, s1
s_cbranch_scc0 .LBB0_14
.LBB0_11:
s_mov_b32 s1, exec_lo
v_cmpx_le_u32_e64 s0, v10
s_cbranch_execz .LBB0_10
s_add_i32 s2, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v5, s2, v0
v_sub_nc_u32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s0, v6
v_lshlrev_b32_e32 v6, 2, v6
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v11, v5
ds_load_b32 v12, v6
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v11, v12
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_10
ds_store_b32 v5, v12
ds_store_b32 v6, v11
s_branch .LBB0_10
.LBB0_14:
s_set_inst_prefetch_distance 0x2
v_and_b32_e32 v10, 7, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v8, v10
v_lshlrev_b32_e32 v11, 2, v5
ds_load_2addr_b32 v[5:6], v11 offset1:8
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v5, v6
s_cbranch_execz .LBB0_16
v_add_nc_u32_e32 v12, 32, v11
ds_store_b32 v11, v6
ds_store_b32 v12, v5
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s0, 4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_18
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_lshr_b32 s1, s0, 1
s_cmp_gt_u32 s0, 1
s_mov_b32 s0, s1
s_cbranch_scc0 .LBB0_21
.LBB0_18:
s_mov_b32 s1, exec_lo
v_cmpx_le_u32_e64 s0, v10
s_cbranch_execz .LBB0_17
s_add_i32 s2, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v5, s2, v0
v_sub_nc_u32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s0, v6
v_lshlrev_b32_e32 v6, 2, v6
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v11, v5
ds_load_b32 v12, v6
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v11, v12
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_17
ds_store_b32 v5, v12
ds_store_b32 v6, v11
s_branch .LBB0_17
.LBB0_21:
s_set_inst_prefetch_distance 0x2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v0, v7
ds_load_b32 v5, v9
s_waitcnt lgkmcnt(1)
global_store_b32 v[1:2], v0, off
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13nvidiaBatcherPi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13nvidiaBatcherPi, .Lfunc_end0-_Z13nvidiaBatcherPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10newBatcherPi
.globl _Z10newBatcherPi
.p2align 8
.type _Z10newBatcherPi,@function
_Z10newBatcherPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v1, s15, 9, v0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v7, 2, v0
v_lshlrev_b32_e32 v9, 3, v0
v_lshlrev_b32_e32 v8, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, 0x100, v1
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v6, vcc_lo
s_mov_b32 s0, exec_lo
s_clause 0x1
global_load_b32 v5, v[1:2], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v7, v5, v6 offset1:4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_2addr_b32 v[5:6], v9 offset1:1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v5, v6
s_cbranch_execz .LBB1_2
v_or_b32_e32 v10, 4, v9
ds_store_b32 v9, v6
ds_store_b32 v10, v5
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s0
v_and_b32_e32 v5, 1, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v8, v5
v_lshlrev_b32_e32 v10, 2, v9
ds_load_2addr_b32 v[5:6], v10 offset1:2
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v5, v6
s_cbranch_execz .LBB1_4
v_add_nc_u32_e32 v11, 8, v10
ds_store_b32 v10, v6
ds_store_b32 v11, v5
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b32_e32 v5, 2, v9
v_lshlrev_b32_e32 v6, 2, v8
s_mov_b32 s0, exec_lo
ds_load_b32 v9, v5
ds_load_b32 v10, v6
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v9, v10
s_cbranch_execz .LBB1_6
ds_store_b32 v5, v10
ds_store_b32 v6, v9
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s0
v_and_b32_e32 v10, 3, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v8, v10
v_lshlrev_b32_e32 v9, 2, v5
ds_load_2addr_b32 v[5:6], v9 offset1:4
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v5, v6
s_cbranch_execz .LBB1_8
v_add_nc_u32_e32 v11, 16, v9
ds_store_b32 v9, v6
ds_store_b32 v11, v5
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v9, 0x400, v7
s_mov_b32 s0, 2
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_10
.p2align 6
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s1
s_lshr_b32 s1, s0, 1
s_cmp_gt_u32 s0, 1
s_mov_b32 s0, s1
s_cbranch_scc0 .LBB1_12
.LBB1_10:
s_add_i32 s1, s0, -1
v_cmp_le_u32_e32 vcc_lo, s0, v10
v_and_b32_e32 v5, s1, v0
s_mov_b32 s1, exec_lo
v_cndmask_b32_e64 v6, 0, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v11, v8, v5
v_sub_nc_u32_e32 v5, v11, v6
v_lshlrev_b32_e32 v6, 2, v11
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v11, v5
ds_load_b32 v12, v6
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v11, v12
s_cbranch_execz .LBB1_9
ds_store_b32 v5, v12
ds_store_b32 v6, v11
s_branch .LBB1_9
.LBB1_12:
s_set_inst_prefetch_distance 0x2
v_and_b32_e32 v10, 7, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v8, v10
v_lshlrev_b32_e32 v11, 2, v5
ds_load_2addr_b32 v[5:6], v11 offset1:8
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v5, v6
s_cbranch_execz .LBB1_14
v_add_nc_u32_e32 v12, 32, v11
ds_store_b32 v11, v6
ds_store_b32 v12, v5
.LBB1_14:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s0, 4
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_16
.p2align 6
.LBB1_15:
s_or_b32 exec_lo, exec_lo, s1
s_lshr_b32 s1, s0, 1
s_cmp_gt_u32 s0, 1
s_mov_b32 s0, s1
s_cbranch_scc0 .LBB1_18
.LBB1_16:
s_add_i32 s1, s0, -1
v_cmp_le_u32_e32 vcc_lo, s0, v10
v_and_b32_e32 v5, s1, v0
s_mov_b32 s1, exec_lo
v_cndmask_b32_e64 v6, 0, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v11, v8, v5
v_sub_nc_u32_e32 v5, v11, v6
v_lshlrev_b32_e32 v6, 2, v11
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v11, v5
ds_load_b32 v12, v6
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v11, v12
s_cbranch_execz .LBB1_15
ds_store_b32 v5, v12
ds_store_b32 v6, v11
s_branch .LBB1_15
.LBB1_18:
s_set_inst_prefetch_distance 0x2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v0, v7
ds_load_b32 v5, v9
s_waitcnt lgkmcnt(1)
global_store_b32 v[1:2], v0, off
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10newBatcherPi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10newBatcherPi, .Lfunc_end1-_Z10newBatcherPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10VanVoorhisPi
.globl _Z10VanVoorhisPi
.p2align 8
.type _Z10VanVoorhisPi,@function
_Z10VanVoorhisPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v1, s15, 9, v0
v_mov_b32_e32 v2, 0
v_lshlrev_b32_e32 v8, 1, v0
v_lshlrev_b32_e32 v7, 2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, 0x100, v1
v_lshlrev_b32_e32 v10, 2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v6, vcc_lo
v_lshlrev_b32_e32 v5, 3, v0
s_clause 0x1
global_load_b32 v6, v[1:2], off
global_load_b32 v9, v[3:4], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v7, v6, v9 offset1:4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v6, v5
ds_load_b32 v10, v10 offset:4
v_or_b32_e32 v9, 1, v8
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v6, v10
s_cbranch_execz .LBB2_2
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v11, 2, v9
ds_store_b32 v5, v10
ds_store_b32 v11, v6
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s0
v_and_b32_e32 v13, 1, v0
v_and_b32_e32 v10, 0x7f0, v8
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_or_b32 v11, v8, 12, v13
v_or_b32_e32 v12, v11, v10
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v14, 2, v12
v_or_b32_e32 v12, 2, v12
ds_load_2addr_b32 v[5:6], v14 offset1:2
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v5, v6
s_cbranch_execz .LBB2_4
v_lshlrev_b32_e32 v15, 2, v12
ds_store_b32 v14, v6
ds_store_b32 v15, v5
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s0
v_and_b32_e32 v5, 8, v8
v_and_b32_e32 v6, 3, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or3_b32 v5, v5, v6, v10
v_lshlrev_b32_e32 v14, 2, v5
ds_load_2addr_b32 v[5:6], v14 offset1:4
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v5, v6
s_cbranch_execz .LBB2_6
v_add_nc_u32_e32 v15, 16, v14
ds_store_b32 v14, v6
ds_store_b32 v15, v5
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s0
v_and_b32_e32 v0, 7, v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v5, v10, v0
v_lshlrev_b32_e32 v14, 2, v5
ds_load_2addr_b32 v[5:6], v14 offset1:8
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v5, v6
s_cbranch_execz .LBB2_8
v_add_nc_u32_e32 v15, 32, v14
ds_store_b32 v14, v6
ds_store_b32 v15, v5
.LBB2_8:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_ne_u32_e32 vcc_lo, 2, v0
s_mov_b32 s0, exec_lo
v_cndmask_b32_e32 v5, 13, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v6, 1, v5
v_and_b32_e32 v6, 5, v6
v_lshlrev_b32_e32 v14, 1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_or_b32 v6, v14, 10, v6
v_xor_b32_e32 v14, 15, v6
v_cmp_eq_u32_e32 vcc_lo, v5, v6
v_or_b32_e32 v5, v5, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v6, v6, v14 :: v_dual_lshlrev_b32 v5, 2, v5
v_or_b32_e32 v6, v6, v10
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 2, v6
ds_load_b32 v14, v5
ds_load_b32 v15, v6
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v14, v15
s_cbranch_execz .LBB2_10
ds_store_b32 v5, v15
ds_store_b32 v6, v14
.LBB2_10:
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b32_e32 v5, 1, v0
v_cmp_gt_u32_e32 vcc_lo, 4, v0
v_cmp_ne_u32_e64 s0, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v5, v13
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v0
v_lshlrev_b32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, 15, v5, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 4, v0
v_cndmask_b32_e64 v6, v0, 11, vcc_lo
v_cndmask_b32_e64 v0, 4, v5, s0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v5, v6, v10
v_cndmask_b32_e64 v6, v0, 14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v0, 2, v5
v_add_lshl_u32 v5, v6, v10, 2
ds_load_b32 v6, v0
ds_load_b32 v13, v5
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v6, v13
s_cbranch_execz .LBB2_12
ds_store_b32 v0, v13
ds_store_b32 v5, v6
.LBB2_12:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, 4, v11
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_or_b32 v0, v0, 13, v10
v_min_u32_e32 v5, v12, v0
v_max_u32_e32 v6, v12, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v0, 2, v5
v_lshlrev_b32_e32 v5, 2, v6
ds_load_b32 v6, v0
ds_load_b32 v11, v5
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v6, v11
s_cbranch_execz .LBB2_14
ds_store_b32 v0, v11
ds_store_b32 v5, v6
.LBB2_14:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, 4, v8
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_or_b32 v0, v0, 14, v10
v_cmp_lt_u32_e32 vcc_lo, v8, v0
v_dual_cndmask_b32 v5, v0, v9 :: v_dual_cndmask_b32 v6, v9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v0, 2, v5
v_lshlrev_b32_e32 v5, 2, v6
ds_load_b32 v6, v0
ds_load_b32 v11, v5
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v6, v11
s_cbranch_execz .LBB2_16
ds_store_b32 v0, v11
ds_store_b32 v5, v6
.LBB2_16:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, 2, v8
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_or_b32 v0, v0, 14, v10
v_cmp_lt_u32_e32 vcc_lo, v8, v0
v_dual_cndmask_b32 v5, v0, v9 :: v_dual_cndmask_b32 v0, v9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b32_e32 v6, 2, v0
v_add_nc_u32_e32 v0, 0x400, v7
ds_load_b32 v8, v5
ds_load_b32 v9, v6
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 v8, v9
s_cbranch_execz .LBB2_18
ds_store_b32 v5, v9
ds_store_b32 v6, v8
.LBB2_18:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v5, v7
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(1)
global_store_b32 v[1:2], v5, off
s_waitcnt lgkmcnt(0)
global_store_b32 v[3:4], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10VanVoorhisPi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z10VanVoorhisPi, .Lfunc_end2-_Z10VanVoorhisPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13nvidiaBatcherPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13nvidiaBatcherPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10newBatcherPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10newBatcherPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10VanVoorhisPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10VanVoorhisPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* The code is described in this paper: Ouyang M, Sorting sixteen
* numbers. Proceedings of IEEE High Performance Extreme Computing
* Conference (HPEC), 2015, 1-6.
*
* Copyright (c) 2015 Ming Ouyang
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#define NoOP 0xFFFFFFFFu
#define TwoTo16 0x00010000u
#define BlockSize 256
#define min(x,y) ((x) < (y) ? (x) : (y))
#define max(x,y) ((x) > (y) ? (x) : (y))
int deviceNum = 0;
int dataSize = 16 * TwoTo16;
int *data, *sorted, *gpuData;
void initGPU(void) {
hipSetDevice(deviceNum);
hipMalloc((void**) &gpuData, sizeof(int) * dataSize);
}
void init(int argc, char *argv[]) {
unsigned i, j, k, tmp;
int c;
while ((c = getopt(argc, argv, "d:")) != -1)
switch (c) {
case 'd':
sscanf(optarg, "%d", &deviceNum);
break;
default:
break;
}
data = (int*) malloc(sizeof(int) * dataSize);
sorted = (int*) malloc(sizeof(int) * dataSize);
j = 0;
for (i = 0; i < TwoTo16; i++) {
tmp = i;
for (k = 0; k < 16; k++) {
data[j++] = tmp & 0x00000001u;
tmp = tmp >> 1;
}
}
initGPU();
}
void verify(void) {
unsigned i, j, k, count;
count = 0;
for (i = 0; i < TwoTo16; i++) {
for (j = 0; j < 15; j++) {
if (sorted[i * 16 + j] > sorted[i * 16 + j + 1]) {
printf("not sorted %d:", i);
for (k = 0; k < 16; k++)
printf(" %d", sorted[i * 16 + k]);
printf("\n");
if (count++ == 10)
exit(1);
}
}
}
}
__device__ inline void IntComparator(int &A, int &B) {
int t;
if (A > B) {
t = A;
A = B;
B = t;
}
}
__device__ inline void UnsignedComparator(unsigned &A, unsigned &B) {
unsigned t;
if (A > B) {
t = A;
A = B;
B = t;
}
}
//Nvidia's implementation of Batcher's sorting network
__global__ void nvidiaBatcher(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned pos, size, stride, offset;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
__syncthreads();
#pragma unroll
for (size = 2; size <= 16; size <<= 1) {
stride = size >> 1;
offset = threadIdx.x & (stride - 1);
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
IntComparator(sX[pos], sX[pos + stride]);
stride >>= 1;
for (; stride > 0; stride >>= 1) {
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
if (offset >= stride) //divergent computation
IntComparator(sX[pos - stride], sX[pos]);
}
}
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
//divergent computation in Nvidia's implementation is removed
__global__ void newBatcher(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned pos, size, stride, offset;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
__syncthreads();
#pragma unroll
for (size = 2; size <= 16; size <<= 1) {
stride = size >> 1;
offset = threadIdx.x & (stride - 1);
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
IntComparator(sX[pos], sX[pos+stride]);
stride >>= 1;
for (; stride > 0; stride >>= 1) {
pos = 2 * threadIdx.x - (threadIdx.x & (stride - 1));
//non-divergent computation
IntComparator(sX[pos - stride * (offset >= stride ? 1 : 0)], sX[pos]);
}
}
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
//Van Voorhis's optimal sorting network for 16 numbers
__global__ void VanVoorhis(int *X) {
__shared__ int sX[BlockSize * 2];
unsigned wire1, wire2, our16tuple;
unsigned base = blockIdx.x * BlockSize * 2 + threadIdx.x;
sX[threadIdx.x] = X[base];
sX[threadIdx.x + BlockSize] = X[base + BlockSize];
our16tuple = (threadIdx.x >> 3) << 4;
__syncthreads();
//step I
wire1 = ((threadIdx.x & 7) << 1) + our16tuple;
wire2 = wire1 + 1;
IntComparator(sX[wire1], sX[wire2]);
//step II
wire1 = (((threadIdx.x & 6) << 1) | (threadIdx.x & 1)) + our16tuple;
wire2 = wire1 + 2;
IntComparator(sX[wire1], sX[wire2]);
//step III
wire1 = (((threadIdx.x & 4) << 1) | (threadIdx.x & 3)) + our16tuple;
wire2 = wire1 + 4;
IntComparator(sX[wire1], sX[wire2]);
//step IV
wire1 = (threadIdx.x & 7) + our16tuple;
wire2 = wire1 + 8;
IntComparator(sX[wire1], sX[wire2]);
//step V
wire1 = threadIdx.x & 7;
wire1 = (wire1 == 2) ? 13 : wire1;
wire2 = ((wire1 << 1) & 10) | ((wire1 >> 1) & 5);
wire2 = (wire1 == wire2) ? (wire2 ^ 15) : wire2;
wire1 += our16tuple;
wire2 += our16tuple;
IntComparator(sX[wire1], sX[wire2]);
//step VI
wire1 = threadIdx.x & 7;
wire2 = ((wire1 << 1) - (wire1 & 1)) << (!(wire1 >> 2));
wire2 = (wire1 == 0) ? 15 : wire2;
wire2 = (wire1 == 1) ? 4 : wire2;
if (wire1 == 4){
wire1 = wire1 ^ 15;
wire2 = wire1 + 3;
}
wire1 += our16tuple;
wire2 += our16tuple;
IntComparator(sX[wire1], sX[wire2]);
//step VII
wire1 = (((threadIdx.x & 6) << 1) | (threadIdx.x & 1) | 2) + our16tuple;
wire2 = (((((threadIdx.x & 6) << 1) | (threadIdx.x & 1) | 2) + 2) & 15)
+ our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
//step VIII
wire1 = ((threadIdx.x & 7) << 1) + 1 + our16tuple;
wire2 = ((((threadIdx.x & 7) << 1) + 4) & 15) + our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
//step IX
wire1 = ((threadIdx.x & 7) << 1) + 1 + our16tuple;
wire2 = ((((threadIdx.x & 7) << 1) + 2) & 15) + our16tuple;
UnsignedComparator(wire1, wire2);
IntComparator(sX[wire1], sX[wire2]);
__syncthreads();
X[base] = sX[threadIdx.x];
X[base + BlockSize] = sX[threadIdx.x + BlockSize];
}
int main(int argc, char *argv[]) {
hipEvent_t start;
hipEvent_t stop;
float msec;
init(argc, argv);
hipEventCreate(&start);
hipEventCreate(&stop);
hipMemcpy(gpuData, data, sizeof(int) * dataSize, hipMemcpyHostToDevice);
hipEventRecord(start, NULL);
nvidiaBatcher <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
hipDeviceSynchronize();
hipEventRecord(stop, NULL);
hipEventSynchronize(stop);
hipEventElapsedTime(&msec, start, stop);
printf("Nvd Batcher, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
hipMemcpy(sorted, gpuData, sizeof(int) * dataSize, hipMemcpyDeviceToHost);
verify();
hipMemcpy(gpuData, data, sizeof(int) * dataSize, hipMemcpyHostToDevice);
hipEventRecord(start, NULL);
VanVoorhis <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
hipDeviceSynchronize();
hipEventRecord(stop, NULL);
hipEventSynchronize(stop);
hipEventElapsedTime(&msec, start, stop);
printf("Van Voorhis, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
hipMemcpy(sorted, gpuData, sizeof(int) * dataSize, hipMemcpyDeviceToHost);
verify();
hipMemcpy(gpuData, data, sizeof(int) * dataSize, hipMemcpyHostToDevice);
hipEventRecord(start, NULL);
newBatcher <<<dataSize / (BlockSize * 2), BlockSize>>> (gpuData);
hipDeviceSynchronize();
hipEventRecord(stop, NULL);
hipEventSynchronize(stop);
hipEventElapsedTime(&msec, start, stop);
printf("new Batcher, blocksize %d, device %d, %.3f ms\n",
BlockSize, deviceNum, msec);
hipMemcpy(sorted, gpuData, sizeof(int) * dataSize, hipMemcpyDeviceToHost);
verify();
return 0;
} | .text
.file "sort16.hip"
.globl _Z7initGPUv # -- Begin function _Z7initGPUv
.p2align 4, 0x90
.type _Z7initGPUv,@function
_Z7initGPUv: # @_Z7initGPUv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl deviceNum(%rip), %edi
callq hipSetDevice
movslq dataSize(%rip), %rsi
shlq $2, %rsi
movl $gpuData, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp hipMalloc # TAILCALL
.Lfunc_end0:
.size _Z7initGPUv, .Lfunc_end0-_Z7initGPUv
.cfi_endproc
# -- End function
.globl _Z4initiPPc # -- Begin function _Z4initiPPc
.p2align 4, 0x90
.type _Z4initiPPc,@function
_Z4initiPPc: # @_Z4initiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_1 Depth=1
movq optarg(%rip), %rdi
movl $.L.str.1, %esi
movl $deviceNum, %edx
xorl %eax, %eax
callq __isoc23_sscanf
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $.L.str, %edx
movl %ebp, %edi
movq %rbx, %rsi
callq getopt
cmpl $100, %eax
je .LBB1_8
# %bb.2: # in Loop: Header=BB1_1 Depth=1
cmpl $-1, %eax
jne .LBB1_1
# %bb.3:
movslq dataSize(%rip), %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %rax, data(%rip)
movq %r14, %rdi
callq malloc
movq %rax, sorted(%rip)
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
xorl %edx, %edx
movl %eax, %esi
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_4 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%rdx), %edi
movl %esi, %r8d
andl $1, %r8d
movl %r8d, (%rbx,%rdi,4)
shrl %esi
incl %edx
cmpl $16, %edx
jne .LBB1_5
# %bb.6: # in Loop: Header=BB1_4 Depth=1
incl %eax
addl %edx, %ecx
cmpl $65536, %eax # imm = 0x10000
jne .LBB1_4
# %bb.7:
movl deviceNum(%rip), %edi
callq hipSetDevice
movslq dataSize(%rip), %rsi
shlq $2, %rsi
movl $gpuData, %edi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp hipMalloc # TAILCALL
.Lfunc_end1:
.size _Z4initiPPc, .Lfunc_end1-_Z4initiPPc
.cfi_endproc
# -- End function
.globl _Z6verifyv # -- Begin function _Z6verifyv
.p2align 4, 0x90
.type _Z6verifyv,@function
_Z6verifyv: # @_Z6verifyv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r14d, %r14d
xorl %ebx, %ebx
xorl %ebp, %ebp
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_8: # in Loop: Header=BB2_1 Depth=1
incq %rbx
addq $64, %r14
cmpq $65536, %rbx # imm = 0x10000
je .LBB2_9
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_4 Depth 3
movq %rbx, %r15
shlq $4, %r15
xorl %r12d, %r12d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_2 Depth=2
incq %r12
cmpq $15, %r12
je .LBB2_8
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
movq sorted(%rip), %rax
movq %r12, %rcx
orq %r15, %rcx
movl (%rax,%rcx,4), %edx
cmpl 4(%rax,%rcx,4), %edx
jle .LBB2_7
# %bb.3: # in Loop: Header=BB2_2 Depth=2
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_2 Depth=2
# => This Inner Loop Header: Depth=3
movq sorted(%rip), %rax
addq %r14, %rax
movl (%rax,%r13,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $16, %r13
jne .LBB2_4
# %bb.5: # in Loop: Header=BB2_2 Depth=2
movl $10, %edi
callq putchar@PLT
cmpl $10, %ebp
je .LBB2_10
# %bb.6: # in Loop: Header=BB2_2 Depth=2
incl %ebp
jmp .LBB2_7
.LBB2_9:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_10:
.cfi_def_cfa_offset 64
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z6verifyv, .Lfunc_end2-_Z6verifyv
.cfi_endproc
# -- End function
.globl _Z28__device_stub__nvidiaBatcherPi # -- Begin function _Z28__device_stub__nvidiaBatcherPi
.p2align 4, 0x90
.type _Z28__device_stub__nvidiaBatcherPi,@function
_Z28__device_stub__nvidiaBatcherPi: # @_Z28__device_stub__nvidiaBatcherPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13nvidiaBatcherPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z28__device_stub__nvidiaBatcherPi, .Lfunc_end3-_Z28__device_stub__nvidiaBatcherPi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__newBatcherPi # -- Begin function _Z25__device_stub__newBatcherPi
.p2align 4, 0x90
.type _Z25__device_stub__newBatcherPi,@function
_Z25__device_stub__newBatcherPi: # @_Z25__device_stub__newBatcherPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10newBatcherPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end4:
.size _Z25__device_stub__newBatcherPi, .Lfunc_end4-_Z25__device_stub__newBatcherPi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__VanVoorhisPi # -- Begin function _Z25__device_stub__VanVoorhisPi
.p2align 4, 0x90
.type _Z25__device_stub__VanVoorhisPi,@function
_Z25__device_stub__VanVoorhisPi: # @_Z25__device_stub__VanVoorhisPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10VanVoorhisPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end5:
.size _Z25__device_stub__VanVoorhisPi, .Lfunc_end5-_Z25__device_stub__VanVoorhisPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967296, %r14 # imm = 0x100000000
callq _Z4initiPPc
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq gpuData(%rip), %rdi
movq data(%rip), %rsi
movslq dataSize(%rip), %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl dataSize(%rip), %eax
leal 511(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
orq %r14, %rdi
leaq 256(%r14), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq gpuData(%rip), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z13nvidiaBatcherPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl deviceNum(%rip), %edx
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movl $256, %esi # imm = 0x100
movb $1, %al
callq printf
movq sorted(%rip), %rdi
movq gpuData(%rip), %rsi
movslq dataSize(%rip), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
callq _Z6verifyv
movq gpuData(%rip), %rdi
movq data(%rip), %rsi
movslq dataSize(%rip), %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl dataSize(%rip), %eax
leal 511(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
orq %r14, %rdi
leaq 256(%r14), %rbx
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_4
# %bb.3:
movq gpuData(%rip), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10VanVoorhisPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl deviceNum(%rip), %edx
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movl $256, %esi # imm = 0x100
movb $1, %al
callq printf
movq sorted(%rip), %rdi
movq gpuData(%rip), %rsi
movslq dataSize(%rip), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
callq _Z6verifyv
movq gpuData(%rip), %rdi
movq data(%rip), %rsi
movslq dataSize(%rip), %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl dataSize(%rip), %eax
leal 511(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
orq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_6
# %bb.5:
movq gpuData(%rip), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10newBatcherPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_6:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl deviceNum(%rip), %edx
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movl $256, %esi # imm = 0x100
movb $1, %al
callq printf
movq sorted(%rip), %rdi
movq gpuData(%rip), %rsi
movslq dataSize(%rip), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
callq _Z6verifyv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13nvidiaBatcherPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10newBatcherPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10VanVoorhisPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type deviceNum,@object # @deviceNum
.bss
.globl deviceNum
.p2align 2, 0x0
deviceNum:
.long 0 # 0x0
.size deviceNum, 4
.type dataSize,@object # @dataSize
.data
.globl dataSize
.p2align 2, 0x0
dataSize:
.long 1048576 # 0x100000
.size dataSize, 4
.type data,@object # @data
.bss
.globl data
.p2align 3, 0x0
data:
.quad 0
.size data, 8
.type sorted,@object # @sorted
.globl sorted
.p2align 3, 0x0
sorted:
.quad 0
.size sorted, 8
.type gpuData,@object # @gpuData
.globl gpuData
.p2align 3, 0x0
gpuData:
.quad 0
.size gpuData, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "d:"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "not sorted %d:"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " %d"
.size .L.str.3, 4
.type _Z13nvidiaBatcherPi,@object # @_Z13nvidiaBatcherPi
.section .rodata,"a",@progbits
.globl _Z13nvidiaBatcherPi
.p2align 3, 0x0
_Z13nvidiaBatcherPi:
.quad _Z28__device_stub__nvidiaBatcherPi
.size _Z13nvidiaBatcherPi, 8
.type _Z10newBatcherPi,@object # @_Z10newBatcherPi
.globl _Z10newBatcherPi
.p2align 3, 0x0
_Z10newBatcherPi:
.quad _Z25__device_stub__newBatcherPi
.size _Z10newBatcherPi, 8
.type _Z10VanVoorhisPi,@object # @_Z10VanVoorhisPi
.globl _Z10VanVoorhisPi
.p2align 3, 0x0
_Z10VanVoorhisPi:
.quad _Z25__device_stub__VanVoorhisPi
.size _Z10VanVoorhisPi, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "Nvd Batcher, blocksize %d, device %d, %.3f ms\n"
.size .L.str.5, 47
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Van Voorhis, blocksize %d, device %d, %.3f ms\n"
.size .L.str.6, 47
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "new Batcher, blocksize %d, device %d, %.3f ms\n"
.size .L.str.7, 47
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13nvidiaBatcherPi"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10newBatcherPi"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10VanVoorhisPi"
.size .L__unnamed_3, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__nvidiaBatcherPi
.addrsig_sym _Z25__device_stub__newBatcherPi
.addrsig_sym _Z25__device_stub__VanVoorhisPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym deviceNum
.addrsig_sym gpuData
.addrsig_sym _Z13nvidiaBatcherPi
.addrsig_sym _Z10newBatcherPi
.addrsig_sym _Z10VanVoorhisPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014b71e_00000000-6_sort16.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2078:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7initGPUv
.type _Z7initGPUv, @function
_Z7initGPUv:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl deviceNum(%rip), %edi
call cudaSetDevice@PLT
movslq dataSize(%rip), %rsi
salq $2, %rsi
leaq gpuData(%rip), %rdi
call cudaMalloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _Z7initGPUv, .-_Z7initGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "d:"
.text
.globl _Z4initiPPc
.type _Z4initiPPc, @function
_Z4initiPPc:
.LFB2071:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %r12d
movq %rsi, %rbx
leaq .LC1(%rip), %rbp
.L7:
movq %rbp, %rdx
movq %rbx, %rsi
movl %r12d, %edi
call getopt@PLT
cmpl $-1, %eax
je .L15
cmpl $100, %eax
jne .L7
leaq deviceNum(%rip), %rdx
leaq .LC0(%rip), %rsi
movq optarg(%rip), %rdi
movl $0, %eax
call __isoc23_sscanf@PLT
jmp .L7
.L15:
movslq dataSize(%rip), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, data(%rip)
movq %rbx, %rdi
call malloc@PLT
movq %rax, sorted(%rip)
movl $16, %r8d
movl $0, %r9d
jmp .L9
.L16:
addl $1, %r9d
addl $16, %r8d
cmpl $1048592, %r8d
je .L11
.L9:
leal -16(%r8), %eax
movl %r9d, %ecx
.L10:
movl %eax, %edx
addl $1, %eax
movl %edx, %edx
movl %ecx, %edi
andl $1, %edi
movq data(%rip), %rsi
movl %edi, (%rsi,%rdx,4)
shrl %ecx
cmpl %eax, %r8d
jne .L10
jmp .L16
.L11:
call _Z7initGPUv
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z4initiPPc, .-_Z4initiPPc
.section .rodata.str1.1
.LC2:
.string "not sorted %d:"
.LC3:
.string " %d"
.LC4:
.string "\n"
.text
.globl _Z6verifyv
.type _Z6verifyv, @function
_Z6verifyv:
.LFB2072:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $64, %r12d
movl $60, %r14d
movl $0, %r15d
movl $0, 4(%rsp)
leaq .LC3(%rip), %r13
jmp .L18
.L29:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal 1(%r15), %eax
cmpl $10, %r15d
je .L27
movl %eax, %r15d
.L19:
cmpq %r14, %rbp
je .L28
.L21:
movq sorted(%rip), %rax
movl (%rax,%rbp), %edx
addq $4, %rbp
cmpl (%rax,%rbp), %edx
jle .L19
movl 4(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rbx
.L20:
movq sorted(%rip), %rax
movl (%rax,%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
jmp .L29
.L27:
movl $1, %edi
call exit@PLT
.L28:
addl $1, 4(%rsp)
movl 4(%rsp), %eax
addq $64, %r14
addq $64, %r12
cmpl $65536, %eax
je .L17
.L18:
leaq -64(%r12), %rax
movq %rax, 8(%rsp)
movq %rax, %rbp
jmp .L21
.L17:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _Z6verifyv, .-_Z6verifyv
.globl _Z33__device_stub__Z13nvidiaBatcherPiPi
.type _Z33__device_stub__Z13nvidiaBatcherPiPi, @function
_Z33__device_stub__Z13nvidiaBatcherPiPi:
.LFB2100:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13nvidiaBatcherPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z33__device_stub__Z13nvidiaBatcherPiPi, .-_Z33__device_stub__Z13nvidiaBatcherPiPi
.globl _Z13nvidiaBatcherPi
.type _Z13nvidiaBatcherPi, @function
_Z13nvidiaBatcherPi:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13nvidiaBatcherPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z13nvidiaBatcherPi, .-_Z13nvidiaBatcherPi
.globl _Z30__device_stub__Z10newBatcherPiPi
.type _Z30__device_stub__Z10newBatcherPiPi, @function
_Z30__device_stub__Z10newBatcherPiPi:
.LFB2102:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L42
.L38:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10newBatcherPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L38
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2102:
.size _Z30__device_stub__Z10newBatcherPiPi, .-_Z30__device_stub__Z10newBatcherPiPi
.globl _Z10newBatcherPi
.type _Z10newBatcherPi, @function
_Z10newBatcherPi:
.LFB2103:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10newBatcherPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _Z10newBatcherPi, .-_Z10newBatcherPi
.globl _Z30__device_stub__Z10VanVoorhisPiPi
.type _Z30__device_stub__Z10VanVoorhisPiPi, @function
_Z30__device_stub__Z10VanVoorhisPiPi:
.LFB2104:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L50
.L46:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10VanVoorhisPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L46
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2104:
.size _Z30__device_stub__Z10VanVoorhisPiPi, .-_Z30__device_stub__Z10VanVoorhisPiPi
.globl _Z10VanVoorhisPi
.type _Z10VanVoorhisPi, @function
_Z10VanVoorhisPi:
.LFB2105:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10VanVoorhisPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2105:
.size _Z10VanVoorhisPi, .-_Z10VanVoorhisPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Nvd Batcher, blocksize %d, device %d, %.3f ms\n"
.align 8
.LC6:
.string "Van Voorhis, blocksize %d, device %d, %.3f ms\n"
.align 8
.LC7:
.string "new Batcher, blocksize %d, device %d, %.3f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2075:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call _Z4initiPPc
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movslq dataSize(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq data(%rip), %rsi
movq gpuData(%rip), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl dataSize(%rip), %edx
leal 511(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L60
.L55:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movl deviceNum(%rip), %ecx
movl $256, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq dataSize(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq gpuData(%rip), %rsi
movq sorted(%rip), %rdi
call cudaMemcpy@PLT
call _Z6verifyv
movslq dataSize(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq data(%rip), %rsi
movq gpuData(%rip), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl dataSize(%rip), %edx
leal 511(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L56:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movl deviceNum(%rip), %ecx
movl $256, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq dataSize(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq gpuData(%rip), %rsi
movq sorted(%rip), %rdi
call cudaMemcpy@PLT
call _Z6verifyv
movslq dataSize(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq data(%rip), %rsi
movq gpuData(%rip), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl dataSize(%rip), %edx
leal 511(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L62
.L57:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movl deviceNum(%rip), %ecx
movl $256, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq dataSize(%rip), %rdx
salq $2, %rdx
movl $2, %ecx
movq gpuData(%rip), %rsi
movq sorted(%rip), %rdi
call cudaMemcpy@PLT
call _Z6verifyv
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L63
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
movq gpuData(%rip), %rdi
call _Z33__device_stub__Z13nvidiaBatcherPiPi
jmp .L55
.L61:
movq gpuData(%rip), %rdi
call _Z30__device_stub__Z10VanVoorhisPiPi
jmp .L56
.L62:
movq gpuData(%rip), %rdi
call _Z30__device_stub__Z10newBatcherPiPi
jmp .L57
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2075:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z10VanVoorhisPi"
.LC9:
.string "_Z10newBatcherPi"
.LC10:
.string "_Z13nvidiaBatcherPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2107:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z10VanVoorhisPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10newBatcherPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z13nvidiaBatcherPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl gpuData
.bss
.align 8
.type gpuData, @object
.size gpuData, 8
gpuData:
.zero 8
.globl sorted
.align 8
.type sorted, @object
.size sorted, 8
sorted:
.zero 8
.globl data
.align 8
.type data, @object
.size data, 8
data:
.zero 8
.globl dataSize
.data
.align 4
.type dataSize, @object
.size dataSize, 4
dataSize:
.long 1048576
.globl deviceNum
.bss
.align 4
.type deviceNum, @object
.size deviceNum, 4
deviceNum:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sort16.hip"
.globl _Z7initGPUv # -- Begin function _Z7initGPUv
.p2align 4, 0x90
.type _Z7initGPUv,@function
_Z7initGPUv: # @_Z7initGPUv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl deviceNum(%rip), %edi
callq hipSetDevice
movslq dataSize(%rip), %rsi
shlq $2, %rsi
movl $gpuData, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp hipMalloc # TAILCALL
.Lfunc_end0:
.size _Z7initGPUv, .Lfunc_end0-_Z7initGPUv
.cfi_endproc
# -- End function
.globl _Z4initiPPc # -- Begin function _Z4initiPPc
.p2align 4, 0x90
.type _Z4initiPPc,@function
_Z4initiPPc: # @_Z4initiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_1 Depth=1
movq optarg(%rip), %rdi
movl $.L.str.1, %esi
movl $deviceNum, %edx
xorl %eax, %eax
callq __isoc23_sscanf
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $.L.str, %edx
movl %ebp, %edi
movq %rbx, %rsi
callq getopt
cmpl $100, %eax
je .LBB1_8
# %bb.2: # in Loop: Header=BB1_1 Depth=1
cmpl $-1, %eax
jne .LBB1_1
# %bb.3:
movslq dataSize(%rip), %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %rax, data(%rip)
movq %r14, %rdi
callq malloc
movq %rax, sorted(%rip)
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
xorl %edx, %edx
movl %eax, %esi
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_4 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%rdx), %edi
movl %esi, %r8d
andl $1, %r8d
movl %r8d, (%rbx,%rdi,4)
shrl %esi
incl %edx
cmpl $16, %edx
jne .LBB1_5
# %bb.6: # in Loop: Header=BB1_4 Depth=1
incl %eax
addl %edx, %ecx
cmpl $65536, %eax # imm = 0x10000
jne .LBB1_4
# %bb.7:
movl deviceNum(%rip), %edi
callq hipSetDevice
movslq dataSize(%rip), %rsi
shlq $2, %rsi
movl $gpuData, %edi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp hipMalloc # TAILCALL
.Lfunc_end1:
.size _Z4initiPPc, .Lfunc_end1-_Z4initiPPc
.cfi_endproc
# -- End function
.globl _Z6verifyv # -- Begin function _Z6verifyv
.p2align 4, 0x90
.type _Z6verifyv,@function
_Z6verifyv: # @_Z6verifyv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r14d, %r14d
xorl %ebx, %ebx
xorl %ebp, %ebp
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_8: # in Loop: Header=BB2_1 Depth=1
incq %rbx
addq $64, %r14
cmpq $65536, %rbx # imm = 0x10000
je .LBB2_9
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_4 Depth 3
movq %rbx, %r15
shlq $4, %r15
xorl %r12d, %r12d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_2 Depth=2
incq %r12
cmpq $15, %r12
je .LBB2_8
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
movq sorted(%rip), %rax
movq %r12, %rcx
orq %r15, %rcx
movl (%rax,%rcx,4), %edx
cmpl 4(%rax,%rcx,4), %edx
jle .LBB2_7
# %bb.3: # in Loop: Header=BB2_2 Depth=2
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_2 Depth=2
# => This Inner Loop Header: Depth=3
movq sorted(%rip), %rax
addq %r14, %rax
movl (%rax,%r13,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incq %r13
cmpq $16, %r13
jne .LBB2_4
# %bb.5: # in Loop: Header=BB2_2 Depth=2
movl $10, %edi
callq putchar@PLT
cmpl $10, %ebp
je .LBB2_10
# %bb.6: # in Loop: Header=BB2_2 Depth=2
incl %ebp
jmp .LBB2_7
.LBB2_9:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_10:
.cfi_def_cfa_offset 64
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z6verifyv, .Lfunc_end2-_Z6verifyv
.cfi_endproc
# -- End function
.globl _Z28__device_stub__nvidiaBatcherPi # -- Begin function _Z28__device_stub__nvidiaBatcherPi
.p2align 4, 0x90
.type _Z28__device_stub__nvidiaBatcherPi,@function
_Z28__device_stub__nvidiaBatcherPi: # @_Z28__device_stub__nvidiaBatcherPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13nvidiaBatcherPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z28__device_stub__nvidiaBatcherPi, .Lfunc_end3-_Z28__device_stub__nvidiaBatcherPi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__newBatcherPi # -- Begin function _Z25__device_stub__newBatcherPi
.p2align 4, 0x90
.type _Z25__device_stub__newBatcherPi,@function
_Z25__device_stub__newBatcherPi: # @_Z25__device_stub__newBatcherPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10newBatcherPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end4:
.size _Z25__device_stub__newBatcherPi, .Lfunc_end4-_Z25__device_stub__newBatcherPi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__VanVoorhisPi # -- Begin function _Z25__device_stub__VanVoorhisPi
.p2align 4, 0x90
.type _Z25__device_stub__VanVoorhisPi,@function
_Z25__device_stub__VanVoorhisPi: # @_Z25__device_stub__VanVoorhisPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10VanVoorhisPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end5:
.size _Z25__device_stub__VanVoorhisPi, .Lfunc_end5-_Z25__device_stub__VanVoorhisPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967296, %r14 # imm = 0x100000000
callq _Z4initiPPc
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq gpuData(%rip), %rdi
movq data(%rip), %rsi
movslq dataSize(%rip), %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl dataSize(%rip), %eax
leal 511(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
orq %r14, %rdi
leaq 256(%r14), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq gpuData(%rip), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z13nvidiaBatcherPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl deviceNum(%rip), %edx
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movl $256, %esi # imm = 0x100
movb $1, %al
callq printf
movq sorted(%rip), %rdi
movq gpuData(%rip), %rsi
movslq dataSize(%rip), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
callq _Z6verifyv
movq gpuData(%rip), %rdi
movq data(%rip), %rsi
movslq dataSize(%rip), %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl dataSize(%rip), %eax
leal 511(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
orq %r14, %rdi
leaq 256(%r14), %rbx
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_4
# %bb.3:
movq gpuData(%rip), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10VanVoorhisPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_4:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl deviceNum(%rip), %edx
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movl $256, %esi # imm = 0x100
movb $1, %al
callq printf
movq sorted(%rip), %rdi
movq gpuData(%rip), %rsi
movslq dataSize(%rip), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
callq _Z6verifyv
movq gpuData(%rip), %rdi
movq data(%rip), %rsi
movslq dataSize(%rip), %rdx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl dataSize(%rip), %eax
leal 511(%rax), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
orq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_6
# %bb.5:
movq gpuData(%rip), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10newBatcherPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_6:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl deviceNum(%rip), %edx
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movl $256, %esi # imm = 0x100
movb $1, %al
callq printf
movq sorted(%rip), %rdi
movq gpuData(%rip), %rsi
movslq dataSize(%rip), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
callq _Z6verifyv
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13nvidiaBatcherPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10newBatcherPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10VanVoorhisPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type deviceNum,@object # @deviceNum
.bss
.globl deviceNum
.p2align 2, 0x0
deviceNum:
.long 0 # 0x0
.size deviceNum, 4
.type dataSize,@object # @dataSize
.data
.globl dataSize
.p2align 2, 0x0
dataSize:
.long 1048576 # 0x100000
.size dataSize, 4
.type data,@object # @data
.bss
.globl data
.p2align 3, 0x0
data:
.quad 0
.size data, 8
.type sorted,@object # @sorted
.globl sorted
.p2align 3, 0x0
sorted:
.quad 0
.size sorted, 8
.type gpuData,@object # @gpuData
.globl gpuData
.p2align 3, 0x0
gpuData:
.quad 0
.size gpuData, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "d:"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "not sorted %d:"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " %d"
.size .L.str.3, 4
.type _Z13nvidiaBatcherPi,@object # @_Z13nvidiaBatcherPi
.section .rodata,"a",@progbits
.globl _Z13nvidiaBatcherPi
.p2align 3, 0x0
_Z13nvidiaBatcherPi:
.quad _Z28__device_stub__nvidiaBatcherPi
.size _Z13nvidiaBatcherPi, 8
.type _Z10newBatcherPi,@object # @_Z10newBatcherPi
.globl _Z10newBatcherPi
.p2align 3, 0x0
_Z10newBatcherPi:
.quad _Z25__device_stub__newBatcherPi
.size _Z10newBatcherPi, 8
.type _Z10VanVoorhisPi,@object # @_Z10VanVoorhisPi
.globl _Z10VanVoorhisPi
.p2align 3, 0x0
_Z10VanVoorhisPi:
.quad _Z25__device_stub__VanVoorhisPi
.size _Z10VanVoorhisPi, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "Nvd Batcher, blocksize %d, device %d, %.3f ms\n"
.size .L.str.5, 47
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Van Voorhis, blocksize %d, device %d, %.3f ms\n"
.size .L.str.6, 47
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "new Batcher, blocksize %d, device %d, %.3f ms\n"
.size .L.str.7, 47
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13nvidiaBatcherPi"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10newBatcherPi"
.size .L__unnamed_2, 17
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10VanVoorhisPi"
.size .L__unnamed_3, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__nvidiaBatcherPi
.addrsig_sym _Z25__device_stub__newBatcherPi
.addrsig_sym _Z25__device_stub__VanVoorhisPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym deviceNum
.addrsig_sym gpuData
.addrsig_sym _Z13nvidiaBatcherPi
.addrsig_sym _Z10newBatcherPi
.addrsig_sym _Z10VanVoorhisPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Multiple GPU version of cuFFT_check that uses multiple GPU's
// This program creates a real-valued 3D function sin(x)*cos(y)*cos(z) and then
// takes the forward and inverse Fourier Transform, with the necessary scaling included.
// The output of this process should match the input function
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <complex.h>
// includes, project
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define NX 512
#define NY 512
#define NZ 512
#define NZ2 (NZ/2+1)
#define NN (NX*NY*NZ)
#define L (2*M_PI)
#define TX 8
#define TY 8
#define TZ 8
int divUp(int a, int b) { return (a + b - 1) / b; }
__device__
int idxClip(int idx, int idxMax){
return idx > (idxMax - 1) ? (idxMax - 1) : (idx < 0 ? 0 : idx);
}
__device__
int flatten(int col, int row, int stack, int width, int height, int depth){
return idxClip(stack, depth) + idxClip(row, height)*depth + idxClip(col, width)*depth*height;
// Note: using column-major indexing format
}
__global__
void initialize(double *f1, double *f2)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const int j = blockIdx.y * blockDim.y + threadIdx.y;
const int k = blockIdx.z * blockDim.z + threadIdx.z;
// if ((i >= NX) || (j >= NY) || (k >= NZ)) return;
const int idx = flatten(i, j, k, NX, NY, NZ);
// Initialize array
f1[idx] = 0.5+0.5;
f2[idx] = 2.5*2.0;
return;
}
void initialize_singleGPU(double *f1, double *f2)
{
// Launch CUDA kernel to initialize velocity field
const dim3 blockSize(TX, TY, TZ);
const dim3 gridSize(divUp(NX, TX), divUp(NY, TY), divUp(NZ, TZ));
initialize<<<gridSize, blockSize>>>(f1, f2);
return;
}
void initialize_multiGPU(const int GPUnum, double *f1, double *f2)
{
int i, idx, NX_per_GPU;
// Split data according to number of GPUs
NX_per_GPU = NX/GPUnum; // This is not a good solution long-term; needs more work for arbitrary grid sizes/nGPUs
printf(" The number of divisions in the X-direction is %d\n", NX_per_GPU);
// Launch CUDA kernel to initialize velocity field
const dim3 blockSize(TX, TY, TZ);
const dim3 gridSize(divUp(NX_per_GPU, TX), divUp(NY, TY), divUp(NZ, TZ));
for (i = 0; i<GPUnum; ++i){
cudaSetDevice(i);
idx = i*NX_per_GPU*NY*NZ; // sets the index value of the data to send to each gpu
initialize<<<gridSize, blockSize>>>(&f1[idx], &f2[idx]);
}
return;
}
int main (void)
{
int i, j, k, idx;
// Declare variables
double *u;
double *u_fft;
// Allocate memory for arrays
cudaMallocManaged(&u, sizeof(double)*NN );
cudaMallocManaged(&u_fft, sizeof(double)*NN );
// Perform kernel calculation using only one GPU first:
cudaSetDevice(0);
initialize_singleGPU(u, u_fft);
cudaDeviceSynchronize();
double result1 = 0.0;
for (i = 0; i < NX; ++i ){
for (j = 0; j<NY; ++j){
for (k = 0; k<NZ; ++k){
idx = k + j*NZ + i*NY*NZ;
result1 += u[idx] + u_fft[idx];
}
}
}
// Set GPU's to use and list device properties
int nGPUs = 2, deviceNum[nGPUs];
for(i = 0; i<nGPUs; ++i)
{
deviceNum[i] = i;
cudaSetDevice(deviceNum[i]);
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, deviceNum[i]);
printf(" Device name: %s\n", prop.name);
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
}
initialize_multiGPU(nGPUs, u, u_fft);
// Synchronize both GPUs in order to print reports
for (i = 0; i<nGPUs; ++i){
cudaSetDevice(deviceNum[i]);
cudaDeviceSynchronize();
}
double result2 = 0.0;
for (i = 0; i < NX; ++i ){
for (j = 0; j<NY; ++j){
for (k = 0; k<NZ; ++k){
idx = k + j*NZ + i*NY*NZ;
result2 += u[idx] + u_fft[idx];
}
}
}
printf("The value of f1 is %d, which should equal to 6*NX*NY*NZ, %d\n", (int)result1, NN + 5*NN);
printf("The value of f2 is %d, which should equal to 6*NX*NY*NZ, %d\n", (int)result2, NN + 5*NN);
cudaFree(u);
cudaFree(u_fft);
return 0;
} | code for sm_80
Function : _Z10initializePdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R9, 0x40140000 ; /* 0x4014000000097802 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0090*/ S2R R4, SR_CTAID.Z ; /* 0x0000000000047919 */
/* 0x000ea80000002700 */
/*00a0*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000ea20000002300 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00c0*/ ISETP.GE.AND P2, PT, R0, 0x200, PT ; /* 0x000002000000780c */
/* 0x000fe40003f46270 */
/*00d0*/ IMNMX R0, RZ, R0, !PT ; /* 0x00000000ff007217 */
/* 0x000fe20007800200 */
/*00e0*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x002fe400078e0205 */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.SHL.U32 R0, R0, 0x40000, RZ ; /* 0x0004000000007824 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.AND P1, PT, R2, 0x200, PT ; /* 0x000002000200780c */
/* 0x000fe40003f26270 */
/*0120*/ IMNMX R2, RZ, R2, !PT ; /* 0x00000002ff027217 */
/* 0x000fe20007800200 */
/*0130*/ IMAD R3, R4, c[0x0][0x8], R7 ; /* 0x0000020004037a24 */
/* 0x004fe200078e0207 */
/*0140*/ SEL R0, R0, 0x7fc0000, !P2 ; /* 0x07fc000000007807 */
/* 0x000fe20005000000 */
/*0150*/ HFMA2.MMA R7, -RZ, RZ, 1.984375, 0 ; /* 0x3ff00000ff077435 */
/* 0x000fe200000001ff */
/*0160*/ SHF.L.U32 R2, R2, 0x9, RZ ; /* 0x0000000902027819 */
/* 0x000fc400000006ff */
/*0170*/ ISETP.GE.AND P0, PT, R3, 0x200, PT ; /* 0x000002000300780c */
/* 0x000fe40003f06270 */
/*0180*/ IMNMX R3, RZ, R3, !PT ; /* 0x00000003ff037217 */
/* 0x000fe40007800200 */
/*0190*/ SEL R2, R2, 0x3fe00, !P1 ; /* 0x0003fe0002027807 */
/* 0x000fe40004800000 */
/*01a0*/ SEL R3, R3, 0x1ff, !P0 ; /* 0x000001ff03037807 */
/* 0x000fc80004000000 */
/*01b0*/ IADD3 R0, R2, R0, R3 ; /* 0x0000000002007210 */
/* 0x000fca0007ffe003 */
/*01c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*01d0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e0205 */
/*01e0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101b04 */
/*01f0*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x000fe2000c101b04 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Multiple GPU version of cuFFT_check that uses multiple GPU's
// This program creates a real-valued 3D function sin(x)*cos(y)*cos(z) and then
// takes the forward and inverse Fourier Transform, with the necessary scaling included.
// The output of this process should match the input function
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <complex.h>
// includes, project
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define NX 512
#define NY 512
#define NZ 512
#define NZ2 (NZ/2+1)
#define NN (NX*NY*NZ)
#define L (2*M_PI)
#define TX 8
#define TY 8
#define TZ 8
int divUp(int a, int b) { return (a + b - 1) / b; }
__device__
int idxClip(int idx, int idxMax){
return idx > (idxMax - 1) ? (idxMax - 1) : (idx < 0 ? 0 : idx);
}
__device__
int flatten(int col, int row, int stack, int width, int height, int depth){
return idxClip(stack, depth) + idxClip(row, height)*depth + idxClip(col, width)*depth*height;
// Note: using column-major indexing format
}
__global__
void initialize(double *f1, double *f2)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const int j = blockIdx.y * blockDim.y + threadIdx.y;
const int k = blockIdx.z * blockDim.z + threadIdx.z;
// if ((i >= NX) || (j >= NY) || (k >= NZ)) return;
const int idx = flatten(i, j, k, NX, NY, NZ);
// Initialize array
f1[idx] = 0.5+0.5;
f2[idx] = 2.5*2.0;
return;
}
void initialize_singleGPU(double *f1, double *f2)
{
// Launch CUDA kernel to initialize velocity field
const dim3 blockSize(TX, TY, TZ);
const dim3 gridSize(divUp(NX, TX), divUp(NY, TY), divUp(NZ, TZ));
initialize<<<gridSize, blockSize>>>(f1, f2);
return;
}
void initialize_multiGPU(const int GPUnum, double *f1, double *f2)
{
int i, idx, NX_per_GPU;
// Split data according to number of GPUs
NX_per_GPU = NX/GPUnum; // This is not a good solution long-term; needs more work for arbitrary grid sizes/nGPUs
printf(" The number of divisions in the X-direction is %d\n", NX_per_GPU);
// Launch CUDA kernel to initialize velocity field
const dim3 blockSize(TX, TY, TZ);
const dim3 gridSize(divUp(NX_per_GPU, TX), divUp(NY, TY), divUp(NZ, TZ));
for (i = 0; i<GPUnum; ++i){
cudaSetDevice(i);
idx = i*NX_per_GPU*NY*NZ; // sets the index value of the data to send to each gpu
initialize<<<gridSize, blockSize>>>(&f1[idx], &f2[idx]);
}
return;
}
int main (void)
{
int i, j, k, idx;
// Declare variables
double *u;
double *u_fft;
// Allocate memory for arrays
cudaMallocManaged(&u, sizeof(double)*NN );
cudaMallocManaged(&u_fft, sizeof(double)*NN );
// Perform kernel calculation using only one GPU first:
cudaSetDevice(0);
initialize_singleGPU(u, u_fft);
cudaDeviceSynchronize();
double result1 = 0.0;
for (i = 0; i < NX; ++i ){
for (j = 0; j<NY; ++j){
for (k = 0; k<NZ; ++k){
idx = k + j*NZ + i*NY*NZ;
result1 += u[idx] + u_fft[idx];
}
}
}
// Set GPU's to use and list device properties
int nGPUs = 2, deviceNum[nGPUs];
for(i = 0; i<nGPUs; ++i)
{
deviceNum[i] = i;
cudaSetDevice(deviceNum[i]);
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, deviceNum[i]);
printf(" Device name: %s\n", prop.name);
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
}
initialize_multiGPU(nGPUs, u, u_fft);
// Synchronize both GPUs in order to print reports
for (i = 0; i<nGPUs; ++i){
cudaSetDevice(deviceNum[i]);
cudaDeviceSynchronize();
}
double result2 = 0.0;
for (i = 0; i < NX; ++i ){
for (j = 0; j<NY; ++j){
for (k = 0; k<NZ; ++k){
idx = k + j*NZ + i*NY*NZ;
result2 += u[idx] + u_fft[idx];
}
}
}
printf("The value of f1 is %d, which should equal to 6*NX*NY*NZ, %d\n", (int)result1, NN + 5*NN);
printf("The value of f2 is %d, which should equal to 6*NX*NY*NZ, %d\n", (int)result2, NN + 5*NN);
cudaFree(u);
cudaFree(u_fft);
return 0;
} | .file "tmpxft_001a55f0_00000000-6_Multi_GPU_Test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5divUpii
.type _Z5divUpii, @function
_Z5divUpii:
.LFB3970:
.cfi_startproc
endbr64
leal -1(%rsi,%rdi), %eax
cltd
idivl %esi
ret
.cfi_endproc
.LFE3970:
.size _Z5divUpii, .-_Z5divUpii
.globl _Z7idxClipii
.type _Z7idxClipii, @function
_Z7idxClipii:
.LFB3971:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3971:
.size _Z7idxClipii, .-_Z7idxClipii
.globl _Z7flatteniiiiii
.type _Z7flatteniiiiii, @function
_Z7flatteniiiiii:
.LFB3972:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3972:
.size _Z7flatteniiiiii, .-_Z7flatteniiiiii
.globl _Z32__device_stub__Z10initializePdS_PdS_
.type _Z32__device_stub__Z10initializePdS_PdS_, @function
_Z32__device_stub__Z10initializePdS_PdS_:
.LFB4000:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10initializePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4000:
.size _Z32__device_stub__Z10initializePdS_PdS_, .-_Z32__device_stub__Z10initializePdS_PdS_
.globl _Z10initializePdS_
.type _Z10initializePdS_, @function
_Z10initializePdS_:
.LFB4001:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10initializePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4001:
.size _Z10initializePdS_, .-_Z10initializePdS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string " The number of divisions in the X-direction is %d\n"
.text
.globl _Z19initialize_multiGPUiPdS_
.type _Z19initialize_multiGPUiPdS_, @function
_Z19initialize_multiGPUiPdS_:
.LFB3974:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %r13d
movq %rsi, %r14
movq %rdx, %r15
movl $512, %eax
movl $0, %edx
idivl %edi
movl %eax, %r12d
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8, 8(%rsp)
movl $8, 12(%rsp)
movl $8, 16(%rsp)
leal 14(%r12), %eax
movl %r12d, %edx
addl $7, %edx
cmovns %edx, %eax
sarl $3, %eax
movl %eax, 20(%rsp)
movl $64, 24(%rsp)
movl $64, 28(%rsp)
testl %r13d, %r13d
jle .L16
sall $18, %r12d
movl $0, %ebp
movl $0, %ebx
jmp .L19
.L18:
addl $1, %ebx
addl %r12d, %ebp
cmpl %ebx, %r13d
je .L16
.L19:
movl %ebx, %edi
call cudaSetDevice@PLT
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movslq %ebp, %rdi
salq $3, %rdi
leaq (%r15,%rdi), %rsi
addq %r14, %rdi
call _Z32__device_stub__Z10initializePdS_PdS_
jmp .L18
.L16:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3974:
.size _Z19initialize_multiGPUiPdS_, .-_Z19initialize_multiGPUiPdS_
.globl _Z20initialize_singleGPUPdS_
.type _Z20initialize_singleGPUPdS_, @function
_Z20initialize_singleGPUPdS_:
.LFB3973:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movl $8, 8(%rsp)
movl $8, 12(%rsp)
movl $64, 20(%rsp)
movl $64, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $8, %ecx
movq 20(%rsp), %rdi
movl $64, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L22:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq %rbp, %rsi
movq %rbx, %rdi
call _Z32__device_stub__Z10initializePdS_PdS_
jmp .L22
.cfi_endproc
.LFE3973:
.size _Z20initialize_singleGPUPdS_, .-_Z20initialize_singleGPUPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string " Device name: %s\n"
.section .rodata.str1.8
.align 8
.LC3:
.string " Memory Clock Rate (KHz): %d\n"
.align 8
.LC4:
.string " Memory Bus Width (bits): %d\n"
.align 8
.LC6:
.string " Peak Memory Bandwidth (GB/s): %f\n\n"
.align 8
.LC7:
.string "The value of f1 is %d, which should equal to 6*NX*NY*NZ, %d\n"
.align 8
.LC8:
.string "The value of f2 is %d, which should equal to 6*NX*NY*NZ, %d\n"
.text
.globl main
.type main, @function
main:
.LFB3975:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1096, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
movl $0, %edi
call cudaSetDevice@PLT
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z20initialize_singleGPUPdS_
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rsi
movq 32(%rsp), %rcx
movl $4096, %r9d
movl $0, %r8d
movq $0x000000000, 8(%rsp)
.L27:
movq %r8, %rdi
salq $21, %rdi
addq $2101248, %rdi
movq %r9, %rdx
.L31:
leaq -4096(%rdx), %rax
.L28:
movsd (%rsi,%rax), %xmm0
addsd (%rcx,%rax), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $8, %rax
cmpq %rdx, %rax
jne .L28
addq $4096, %rdx
cmpq %rdi, %rdx
jne .L31
addq $1, %r8
addq $2097152, %r9
cmpq $512, %r8
jne .L27
movl $0, %ebx
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r12
.L30:
movl %ebx, 40(%rsp,%rbx,4)
movl %ebx, %edi
call cudaSetDevice@PLT
leaq 48(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 656(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 660(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 656(%rsp), %xmm0
addsd %xmm0, %xmm0
movl 660(%rsp), %edx
leal 7(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $3, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd %xmm1, %xmm0
divsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $2, %rbx
jne .L30
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movl $2, %edi
call _Z19initialize_multiGPUiPdS_
movl 40(%rsp), %edi
call cudaSetDevice@PLT
call cudaDeviceSynchronize@PLT
movl 44(%rsp), %edi
call cudaSetDevice@PLT
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rsi
movq 32(%rsp), %rcx
movl $4096, %r9d
movl $0, %r8d
movq $0x000000000, (%rsp)
.L32:
movq %r8, %rdi
salq $21, %rdi
addq $2101248, %rdi
movq %r9, %rdx
.L36:
leaq -4096(%rdx), %rax
.L33:
movsd (%rsi,%rax), %xmm0
addsd (%rcx,%rax), %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
addq $8, %rax
cmpq %rdx, %rax
jne .L33
addq $4096, %rdx
cmpq %rdi, %rdx
jne .L36
addq $1, %r8
addq $2097152, %r9
cmpq $512, %r8
jne .L32
cvttsd2sil 8(%rsp), %edx
movl $805306368, %ecx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cvttsd2sil (%rsp), %edx
movl $805306368, %ecx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z10initializePdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4003:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializePdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4003:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Multiple GPU version of cuFFT_check that uses multiple GPU's
// This program creates a real-valued 3D function sin(x)*cos(y)*cos(z) and then
// takes the forward and inverse Fourier Transform, with the necessary scaling included.
// The output of this process should match the input function
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <complex.h>
// includes, project
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define NX 512
#define NY 512
#define NZ 512
#define NZ2 (NZ/2+1)
#define NN (NX*NY*NZ)
#define L (2*M_PI)
#define TX 8
#define TY 8
#define TZ 8
int divUp(int a, int b) { return (a + b - 1) / b; }
__device__
int idxClip(int idx, int idxMax){
return idx > (idxMax - 1) ? (idxMax - 1) : (idx < 0 ? 0 : idx);
}
__device__
int flatten(int col, int row, int stack, int width, int height, int depth){
return idxClip(stack, depth) + idxClip(row, height)*depth + idxClip(col, width)*depth*height;
// Note: using column-major indexing format
}
__global__
void initialize(double *f1, double *f2)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const int j = blockIdx.y * blockDim.y + threadIdx.y;
const int k = blockIdx.z * blockDim.z + threadIdx.z;
// if ((i >= NX) || (j >= NY) || (k >= NZ)) return;
const int idx = flatten(i, j, k, NX, NY, NZ);
// Initialize array
f1[idx] = 0.5+0.5;
f2[idx] = 2.5*2.0;
return;
}
void initialize_singleGPU(double *f1, double *f2)
{
// Launch CUDA kernel to initialize velocity field
const dim3 blockSize(TX, TY, TZ);
const dim3 gridSize(divUp(NX, TX), divUp(NY, TY), divUp(NZ, TZ));
initialize<<<gridSize, blockSize>>>(f1, f2);
return;
}
void initialize_multiGPU(const int GPUnum, double *f1, double *f2)
{
int i, idx, NX_per_GPU;
// Split data according to number of GPUs
NX_per_GPU = NX/GPUnum; // This is not a good solution long-term; needs more work for arbitrary grid sizes/nGPUs
printf(" The number of divisions in the X-direction is %d\n", NX_per_GPU);
// Launch CUDA kernel to initialize velocity field
const dim3 blockSize(TX, TY, TZ);
const dim3 gridSize(divUp(NX_per_GPU, TX), divUp(NY, TY), divUp(NZ, TZ));
for (i = 0; i<GPUnum; ++i){
cudaSetDevice(i);
idx = i*NX_per_GPU*NY*NZ; // sets the index value of the data to send to each gpu
initialize<<<gridSize, blockSize>>>(&f1[idx], &f2[idx]);
}
return;
}
int main (void)
{
int i, j, k, idx;
// Declare variables
double *u;
double *u_fft;
// Allocate memory for arrays
cudaMallocManaged(&u, sizeof(double)*NN );
cudaMallocManaged(&u_fft, sizeof(double)*NN );
// Perform kernel calculation using only one GPU first:
cudaSetDevice(0);
initialize_singleGPU(u, u_fft);
cudaDeviceSynchronize();
double result1 = 0.0;
for (i = 0; i < NX; ++i ){
for (j = 0; j<NY; ++j){
for (k = 0; k<NZ; ++k){
idx = k + j*NZ + i*NY*NZ;
result1 += u[idx] + u_fft[idx];
}
}
}
// Set GPU's to use and list device properties
int nGPUs = 2, deviceNum[nGPUs];
for(i = 0; i<nGPUs; ++i)
{
deviceNum[i] = i;
cudaSetDevice(deviceNum[i]);
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, deviceNum[i]);
printf(" Device name: %s\n", prop.name);
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
}
initialize_multiGPU(nGPUs, u, u_fft);
// Synchronize both GPUs in order to print reports
for (i = 0; i<nGPUs; ++i){
cudaSetDevice(deviceNum[i]);
cudaDeviceSynchronize();
}
double result2 = 0.0;
for (i = 0; i < NX; ++i ){
for (j = 0; j<NY; ++j){
for (k = 0; k<NZ; ++k){
idx = k + j*NZ + i*NY*NZ;
result2 += u[idx] + u_fft[idx];
}
}
}
printf("The value of f1 is %d, which should equal to 6*NX*NY*NZ, %d\n", (int)result1, NN + 5*NN);
printf("The value of f2 is %d, which should equal to 6*NX*NY*NZ, %d\n", (int)result2, NN + 5*NN);
cudaFree(u);
cudaFree(u_fft);
return 0;
} | // Multiple GPU version of cuFFT_check that uses multiple GPU's
// This program creates a real-valued 3D function sin(x)*cos(y)*cos(z) and then
// takes the forward and inverse Fourier Transform, with the necessary scaling included.
// The output of this process should match the input function
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <complex.h>
// includes, project
#include <hip/hip_runtime.h>
#define NX 512
#define NY 512
#define NZ 512
#define NZ2 (NZ/2+1)
#define NN (NX*NY*NZ)
#define L (2*M_PI)
#define TX 8
#define TY 8
#define TZ 8
int divUp(int a, int b) { return (a + b - 1) / b; }
__device__
int idxClip(int idx, int idxMax){
return idx > (idxMax - 1) ? (idxMax - 1) : (idx < 0 ? 0 : idx);
}
__device__
int flatten(int col, int row, int stack, int width, int height, int depth){
return idxClip(stack, depth) + idxClip(row, height)*depth + idxClip(col, width)*depth*height;
// Note: using column-major indexing format
}
__global__
void initialize(double *f1, double *f2)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const int j = blockIdx.y * blockDim.y + threadIdx.y;
const int k = blockIdx.z * blockDim.z + threadIdx.z;
// if ((i >= NX) || (j >= NY) || (k >= NZ)) return;
const int idx = flatten(i, j, k, NX, NY, NZ);
// Initialize array
f1[idx] = 0.5+0.5;
f2[idx] = 2.5*2.0;
return;
}
void initialize_singleGPU(double *f1, double *f2)
{
// Launch CUDA kernel to initialize velocity field
const dim3 blockSize(TX, TY, TZ);
const dim3 gridSize(divUp(NX, TX), divUp(NY, TY), divUp(NZ, TZ));
initialize<<<gridSize, blockSize>>>(f1, f2);
return;
}
void initialize_multiGPU(const int GPUnum, double *f1, double *f2)
{
int i, idx, NX_per_GPU;
// Split data according to number of GPUs
NX_per_GPU = NX/GPUnum; // This is not a good solution long-term; needs more work for arbitrary grid sizes/nGPUs
printf(" The number of divisions in the X-direction is %d\n", NX_per_GPU);
// Launch CUDA kernel to initialize velocity field
const dim3 blockSize(TX, TY, TZ);
const dim3 gridSize(divUp(NX_per_GPU, TX), divUp(NY, TY), divUp(NZ, TZ));
for (i = 0; i<GPUnum; ++i){
hipSetDevice(i);
idx = i*NX_per_GPU*NY*NZ; // sets the index value of the data to send to each gpu
initialize<<<gridSize, blockSize>>>(&f1[idx], &f2[idx]);
}
return;
}
int main (void)
{
int i, j, k, idx;
// Declare variables
double *u;
double *u_fft;
// Allocate memory for arrays
hipMallocManaged(&u, sizeof(double)*NN );
hipMallocManaged(&u_fft, sizeof(double)*NN );
// Perform kernel calculation using only one GPU first:
hipSetDevice(0);
initialize_singleGPU(u, u_fft);
hipDeviceSynchronize();
double result1 = 0.0;
for (i = 0; i < NX; ++i ){
for (j = 0; j<NY; ++j){
for (k = 0; k<NZ; ++k){
idx = k + j*NZ + i*NY*NZ;
result1 += u[idx] + u_fft[idx];
}
}
}
// Set GPU's to use and list device properties
int nGPUs = 2, deviceNum[nGPUs];
for(i = 0; i<nGPUs; ++i)
{
deviceNum[i] = i;
hipSetDevice(deviceNum[i]);
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, deviceNum[i]);
printf(" Device name: %s\n", prop.name);
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
}
initialize_multiGPU(nGPUs, u, u_fft);
// Synchronize both GPUs in order to print reports
for (i = 0; i<nGPUs; ++i){
hipSetDevice(deviceNum[i]);
hipDeviceSynchronize();
}
double result2 = 0.0;
for (i = 0; i < NX; ++i ){
for (j = 0; j<NY; ++j){
for (k = 0; k<NZ; ++k){
idx = k + j*NZ + i*NY*NZ;
result2 += u[idx] + u_fft[idx];
}
}
}
printf("The value of f1 is %d, which should equal to 6*NX*NY*NZ, %d\n", (int)result1, NN + 5*NN);
printf("The value of f2 is %d, which should equal to 6*NX*NY*NZ, %d\n", (int)result2, NN + 5*NN);
hipFree(u);
hipFree(u_fft);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Multiple GPU version of cuFFT_check that uses multiple GPU's
// This program creates a real-valued 3D function sin(x)*cos(y)*cos(z) and then
// takes the forward and inverse Fourier Transform, with the necessary scaling included.
// The output of this process should match the input function
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <complex.h>
// includes, project
#include <hip/hip_runtime.h>
#define NX 512
#define NY 512
#define NZ 512
#define NZ2 (NZ/2+1)
#define NN (NX*NY*NZ)
#define L (2*M_PI)
#define TX 8
#define TY 8
#define TZ 8
int divUp(int a, int b) { return (a + b - 1) / b; }
__device__
int idxClip(int idx, int idxMax){
return idx > (idxMax - 1) ? (idxMax - 1) : (idx < 0 ? 0 : idx);
}
__device__
int flatten(int col, int row, int stack, int width, int height, int depth){
return idxClip(stack, depth) + idxClip(row, height)*depth + idxClip(col, width)*depth*height;
// Note: using column-major indexing format
}
__global__
void initialize(double *f1, double *f2)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const int j = blockIdx.y * blockDim.y + threadIdx.y;
const int k = blockIdx.z * blockDim.z + threadIdx.z;
// if ((i >= NX) || (j >= NY) || (k >= NZ)) return;
const int idx = flatten(i, j, k, NX, NY, NZ);
// Initialize array
f1[idx] = 0.5+0.5;
f2[idx] = 2.5*2.0;
return;
}
void initialize_singleGPU(double *f1, double *f2)
{
// Launch CUDA kernel to initialize velocity field
const dim3 blockSize(TX, TY, TZ);
const dim3 gridSize(divUp(NX, TX), divUp(NY, TY), divUp(NZ, TZ));
initialize<<<gridSize, blockSize>>>(f1, f2);
return;
}
void initialize_multiGPU(const int GPUnum, double *f1, double *f2)
{
int i, idx, NX_per_GPU;
// Split data according to number of GPUs
NX_per_GPU = NX/GPUnum; // This is not a good solution long-term; needs more work for arbitrary grid sizes/nGPUs
printf(" The number of divisions in the X-direction is %d\n", NX_per_GPU);
// Launch CUDA kernel to initialize velocity field
const dim3 blockSize(TX, TY, TZ);
const dim3 gridSize(divUp(NX_per_GPU, TX), divUp(NY, TY), divUp(NZ, TZ));
for (i = 0; i<GPUnum; ++i){
hipSetDevice(i);
idx = i*NX_per_GPU*NY*NZ; // sets the index value of the data to send to each gpu
initialize<<<gridSize, blockSize>>>(&f1[idx], &f2[idx]);
}
return;
}
int main (void)
{
int i, j, k, idx;
// Declare variables
double *u;
double *u_fft;
// Allocate memory for arrays
hipMallocManaged(&u, sizeof(double)*NN );
hipMallocManaged(&u_fft, sizeof(double)*NN );
// Perform kernel calculation using only one GPU first:
hipSetDevice(0);
initialize_singleGPU(u, u_fft);
hipDeviceSynchronize();
double result1 = 0.0;
for (i = 0; i < NX; ++i ){
for (j = 0; j<NY; ++j){
for (k = 0; k<NZ; ++k){
idx = k + j*NZ + i*NY*NZ;
result1 += u[idx] + u_fft[idx];
}
}
}
// Set GPU's to use and list device properties
int nGPUs = 2, deviceNum[nGPUs];
for(i = 0; i<nGPUs; ++i)
{
deviceNum[i] = i;
hipSetDevice(deviceNum[i]);
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, deviceNum[i]);
printf(" Device name: %s\n", prop.name);
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
}
initialize_multiGPU(nGPUs, u, u_fft);
// Synchronize both GPUs in order to print reports
for (i = 0; i<nGPUs; ++i){
hipSetDevice(deviceNum[i]);
hipDeviceSynchronize();
}
double result2 = 0.0;
for (i = 0; i < NX; ++i ){
for (j = 0; j<NY; ++j){
for (k = 0; k<NZ; ++k){
idx = k + j*NZ + i*NY*NZ;
result2 += u[idx] + u_fft[idx];
}
}
}
printf("The value of f1 is %d, which should equal to 6*NX*NY*NZ, %d\n", (int)result1, NN + 5*NN);
printf("The value of f2 is %d, which should equal to 6*NX*NY*NZ, %d\n", (int)result2, NN + 5*NN);
hipFree(u);
hipFree(u_fft);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10initializePdS_
.globl _Z10initializePdS_
.p2align 8
.type _Z10initializePdS_,@function
_Z10initializePdS_:
s_load_b64 s[2:3], s[0:1], 0x1c
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s14, s2, v[2:3]
v_mad_u64_u32 v[4:5], null, s13, s4, v[1:2]
s_and_b32 s2, s3, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_med3_i32 v0, v3, 0, 0x1ff
s_load_b128 s[0:3], s[0:1], 0x0
v_med3_i32 v2, v4, 0, 0x1ff
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b32_e32 v0, 9, v0
v_med3_i32 v3, v1, 0, 0x1ff
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 18, v2
v_or3_b32 v0, v3, v0, v2
v_dual_mov_b32 v3, 0x3ff00000 :: v_dual_mov_b32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[4:5], v[2:3], off
v_mov_b32_e32 v3, 0x40140000
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initializePdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10initializePdS_, .Lfunc_end0-_Z10initializePdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initializePdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10initializePdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Multiple GPU version of cuFFT_check that uses multiple GPU's
// This program creates a real-valued 3D function sin(x)*cos(y)*cos(z) and then
// takes the forward and inverse Fourier Transform, with the necessary scaling included.
// The output of this process should match the input function
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <complex.h>
// includes, project
#include <hip/hip_runtime.h>
#define NX 512
#define NY 512
#define NZ 512
#define NZ2 (NZ/2+1)
#define NN (NX*NY*NZ)
#define L (2*M_PI)
#define TX 8
#define TY 8
#define TZ 8
int divUp(int a, int b) { return (a + b - 1) / b; }
__device__
int idxClip(int idx, int idxMax){
return idx > (idxMax - 1) ? (idxMax - 1) : (idx < 0 ? 0 : idx);
}
__device__
int flatten(int col, int row, int stack, int width, int height, int depth){
return idxClip(stack, depth) + idxClip(row, height)*depth + idxClip(col, width)*depth*height;
// Note: using column-major indexing format
}
__global__
void initialize(double *f1, double *f2)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const int j = blockIdx.y * blockDim.y + threadIdx.y;
const int k = blockIdx.z * blockDim.z + threadIdx.z;
// if ((i >= NX) || (j >= NY) || (k >= NZ)) return;
const int idx = flatten(i, j, k, NX, NY, NZ);
// Initialize array
f1[idx] = 0.5+0.5;
f2[idx] = 2.5*2.0;
return;
}
void initialize_singleGPU(double *f1, double *f2)
{
// Launch CUDA kernel to initialize velocity field
const dim3 blockSize(TX, TY, TZ);
const dim3 gridSize(divUp(NX, TX), divUp(NY, TY), divUp(NZ, TZ));
initialize<<<gridSize, blockSize>>>(f1, f2);
return;
}
void initialize_multiGPU(const int GPUnum, double *f1, double *f2)
{
int i, idx, NX_per_GPU;
// Split data according to number of GPUs
NX_per_GPU = NX/GPUnum; // This is not a good solution long-term; needs more work for arbitrary grid sizes/nGPUs
printf(" The number of divisions in the X-direction is %d\n", NX_per_GPU);
// Launch CUDA kernel to initialize velocity field
const dim3 blockSize(TX, TY, TZ);
const dim3 gridSize(divUp(NX_per_GPU, TX), divUp(NY, TY), divUp(NZ, TZ));
for (i = 0; i<GPUnum; ++i){
hipSetDevice(i);
idx = i*NX_per_GPU*NY*NZ; // sets the index value of the data to send to each gpu
initialize<<<gridSize, blockSize>>>(&f1[idx], &f2[idx]);
}
return;
}
int main (void)
{
int i, j, k, idx;
// Declare variables
double *u;
double *u_fft;
// Allocate memory for arrays
hipMallocManaged(&u, sizeof(double)*NN );
hipMallocManaged(&u_fft, sizeof(double)*NN );
// Perform kernel calculation using only one GPU first:
hipSetDevice(0);
initialize_singleGPU(u, u_fft);
hipDeviceSynchronize();
double result1 = 0.0;
for (i = 0; i < NX; ++i ){
for (j = 0; j<NY; ++j){
for (k = 0; k<NZ; ++k){
idx = k + j*NZ + i*NY*NZ;
result1 += u[idx] + u_fft[idx];
}
}
}
// Set GPU's to use and list device properties
int nGPUs = 2, deviceNum[nGPUs];
for(i = 0; i<nGPUs; ++i)
{
deviceNum[i] = i;
hipSetDevice(deviceNum[i]);
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, deviceNum[i]);
printf(" Device name: %s\n", prop.name);
printf(" Memory Clock Rate (KHz): %d\n",
prop.memoryClockRate);
printf(" Memory Bus Width (bits): %d\n",
prop.memoryBusWidth);
printf(" Peak Memory Bandwidth (GB/s): %f\n\n",
2.0*prop.memoryClockRate*(prop.memoryBusWidth/8)/1.0e6);
}
initialize_multiGPU(nGPUs, u, u_fft);
// Synchronize both GPUs in order to print reports
for (i = 0; i<nGPUs; ++i){
hipSetDevice(deviceNum[i]);
hipDeviceSynchronize();
}
double result2 = 0.0;
for (i = 0; i < NX; ++i ){
for (j = 0; j<NY; ++j){
for (k = 0; k<NZ; ++k){
idx = k + j*NZ + i*NY*NZ;
result2 += u[idx] + u_fft[idx];
}
}
}
printf("The value of f1 is %d, which should equal to 6*NX*NY*NZ, %d\n", (int)result1, NN + 5*NN);
printf("The value of f2 is %d, which should equal to 6*NX*NY*NZ, %d\n", (int)result2, NN + 5*NN);
hipFree(u);
hipFree(u_fft);
return 0;
} | .text
.file "Multi_GPU_Test.hip"
.globl _Z5divUpii # -- Begin function _Z5divUpii
.p2align 4, 0x90
.type _Z5divUpii,@function
_Z5divUpii: # @_Z5divUpii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
# kill: def $edi killed $edi def $rdi
leal (%rdi,%rsi), %eax
decl %eax
cltd
idivl %esi
retq
.Lfunc_end0:
.size _Z5divUpii, .Lfunc_end0-_Z5divUpii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__initializePdS_ # -- Begin function _Z25__device_stub__initializePdS_
.p2align 4, 0x90
.type _Z25__device_stub__initializePdS_,@function
_Z25__device_stub__initializePdS_: # @_Z25__device_stub__initializePdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10initializePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__initializePdS_, .Lfunc_end1-_Z25__device_stub__initializePdS_
.cfi_endproc
# -- End function
.globl _Z20initialize_singleGPUPdS_ # -- Begin function _Z20initialize_singleGPUPdS_
.p2align 4, 0x90
.type _Z20initialize_singleGPUPdS_,@function
_Z20initialize_singleGPUPdS_: # @_Z20initialize_singleGPUPdS_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $34359738376, %rdx # imm = 0x800000008
movl $64, %esi
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10initializePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z20initialize_singleGPUPdS_, .Lfunc_end2-_Z20initialize_singleGPUPdS_
.cfi_endproc
# -- End function
.globl _Z19initialize_multiGPUiPdS_ # -- Begin function _Z19initialize_multiGPUiPdS_
.p2align 4, 0x90
.type _Z19initialize_multiGPUiPdS_,@function
_Z19initialize_multiGPUiPdS_: # @_Z19initialize_multiGPUiPdS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 8(%rsp) # 8-byte Spill
movq %rsi, (%rsp) # 8-byte Spill
movl %edi, %ebp
xorl %ebx, %ebx
movl $512, %eax # imm = 0x200
xorl %edx, %edx
idivl %edi
movl %eax, %r15d
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
leal 7(%r15), %ecx
leal 14(%r15), %eax
testl %ecx, %ecx
cmovnsl %ecx, %eax
testl %ebp, %ebp
jle .LBB3_5
# %bb.1: # %.lr.ph
sarl $3, %eax
movabsq $274877906944, %r12 # imm = 0x4000000000
orq %rax, %r12
shll $18, %r15d
movl %ebp, %r14d
movabsq $34359738376, %r13 # imm = 0x800000008
xorl %ebp, %ebp
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
incq %rbp
addl %r15d, %ebx
cmpq %rbp, %r14
je .LBB3_5
.LBB3_2: # =>This Inner Loop Header: Depth=1
movl %ebp, %edi
callq hipSetDevice
movq %r12, %rdi
movl $64, %esi
movq %r13, %rdx
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movslq %ebx, %rax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rcx
movq 8(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,8), %rax
movq %rcx, 72(%rsp)
movq %rax, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z10initializePdS_, %edi
leaq 80(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_4
.LBB3_5: # %._crit_edge
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z19initialize_multiGPUiPdS_, .Lfunc_end3-_Z19initialize_multiGPUiPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $1504, %rsp # imm = 0x5E0
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
leaq -48(%rbp), %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
leaq -40(%rbp), %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
xorl %ebx, %ebx
xorl %edi, %edi
callq hipSetDevice
movq -48(%rbp), %rdi
movq -40(%rbp), %rsi
callq _Z20initialize_singleGPUPdS_
callq hipDeviceSynchronize
movq -48(%rbp), %rax
xorpd %xmm1, %xmm1
movq -40(%rbp), %rcx
.p2align 4, 0x90
.LBB4_1: # %.preheader53
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
# Child Loop BB4_3 Depth 3
movq %rax, %rdx
movq %rcx, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB4_2: # %.preheader52
# Parent Loop BB4_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_3 Depth 3
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_1 Depth=1
# Parent Loop BB4_2 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rdx,%r8,8), %xmm0 # xmm0 = mem[0],zero
addsd (%rsi,%r8,8), %xmm0
addsd %xmm0, %xmm1
incq %r8
cmpq $512, %r8 # imm = 0x200
jne .LBB4_3
# %bb.4: # in Loop: Header=BB4_2 Depth=2
incq %rdi
addq $4096, %rsi # imm = 0x1000
addq $4096, %rdx # imm = 0x1000
cmpq $512, %rdi # imm = 0x200
jne .LBB4_2
# %bb.5: # in Loop: Header=BB4_1 Depth=1
incq %rbx
addq $2097152, %rcx # imm = 0x200000
addq $2097152, %rax # imm = 0x200000
cmpq $512, %rbx # imm = 0x200
jne .LBB4_1
# %bb.6:
movsd %xmm1, -56(%rbp) # 8-byte Spill
movq %rsp, %r15
movq %rsp, %r12
addq $-16, %r12
movq %r12, %rsp
leaq -1528(%rbp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_7: # =>This Inner Loop Header: Depth=1
movl %r14d, (%r12,%r14,4)
movl %r14d, %edi
callq hipSetDevice
movq %rbx, %rdi
movl %r14d, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl -920(%rbp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl -916(%rbp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorps %xmm1, %xmm1
cvtsi2sdl -920(%rbp), %xmm1
addsd %xmm1, %xmm1
movl -916(%rbp), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
mulsd %xmm1, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %r14
cmpq $1, %r14
je .LBB4_7
# %bb.8:
movq -48(%rbp), %rsi
movq -40(%rbp), %rdx
movl $2, %edi
callq _Z19initialize_multiGPUiPdS_
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_9: # =>This Inner Loop Header: Depth=1
movl (%r12,%rbx,4), %edi
callq hipSetDevice
callq hipDeviceSynchronize
incq %rbx
cmpq $1, %rbx
je .LBB4_9
# %bb.10: # %.preheader51
movq -48(%rbp), %rax
xorpd %xmm2, %xmm2
movq -40(%rbp), %rcx
xorl %edx, %edx
movsd -56(%rbp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB4_11: # %.preheader50
# =>This Loop Header: Depth=1
# Child Loop BB4_12 Depth 2
# Child Loop BB4_13 Depth 3
movq %rax, %rsi
movq %rcx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_12: # %.preheader
# Parent Loop BB4_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_13 Depth 3
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB4_13: # Parent Loop BB4_11 Depth=1
# Parent Loop BB4_12 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rsi,%r9,8), %xmm0 # xmm0 = mem[0],zero
addsd (%rdi,%r9,8), %xmm0
addsd %xmm0, %xmm2
incq %r9
cmpq $512, %r9 # imm = 0x200
jne .LBB4_13
# %bb.14: # in Loop: Header=BB4_12 Depth=2
incq %r8
addq $4096, %rdi # imm = 0x1000
addq $4096, %rsi # imm = 0x1000
cmpq $512, %r8 # imm = 0x200
jne .LBB4_12
# %bb.15: # in Loop: Header=BB4_11 Depth=1
incq %rdx
addq $2097152, %rcx # imm = 0x200000
addq $2097152, %rax # imm = 0x200000
cmpq $512, %rdx # imm = 0x200
jne .LBB4_11
# %bb.16:
cvttsd2si %xmm1, %esi
movl $.L.str.5, %edi
movl $805306368, %edx # imm = 0x30000000
xorl %eax, %eax
movsd %xmm2, -56(%rbp) # 8-byte Spill
callq printf
cvttsd2si -56(%rbp), %esi # 8-byte Folded Reload
movl $.L.str.6, %edi
movl $805306368, %edx # imm = 0x30000000
xorl %eax, %eax
callq printf
movq -48(%rbp), %rdi
callq hipFree
movq -40(%rbp), %rdi
callq hipFree
movq %r15, %rsp
xorl %eax, %eax
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializePdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10initializePdS_,@object # @_Z10initializePdS_
.section .rodata,"a",@progbits
.globl _Z10initializePdS_
.p2align 3, 0x0
_Z10initializePdS_:
.quad _Z25__device_stub__initializePdS_
.size _Z10initializePdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " The number of divisions in the X-direction is %d\n"
.size .L.str, 53
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Device name: %s\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Memory Clock Rate (KHz): %d\n"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Memory Bus Width (bits): %d\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Peak Memory Bandwidth (GB/s): %f\n\n"
.size .L.str.4, 37
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "The value of f1 is %d, which should equal to 6*NX*NY*NZ, %d\n"
.size .L.str.5, 61
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "The value of f2 is %d, which should equal to 6*NX*NY*NZ, %d\n"
.size .L.str.6, 61
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10initializePdS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__initializePdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10initializePdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10initializePdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R9, 0x40140000 ; /* 0x4014000000097802 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0080*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0090*/ S2R R4, SR_CTAID.Z ; /* 0x0000000000047919 */
/* 0x000ea80000002700 */
/*00a0*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000ea20000002300 */
/*00b0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00c0*/ ISETP.GE.AND P2, PT, R0, 0x200, PT ; /* 0x000002000000780c */
/* 0x000fe40003f46270 */
/*00d0*/ IMNMX R0, RZ, R0, !PT ; /* 0x00000000ff007217 */
/* 0x000fe20007800200 */
/*00e0*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x002fe400078e0205 */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.SHL.U32 R0, R0, 0x40000, RZ ; /* 0x0004000000007824 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.AND P1, PT, R2, 0x200, PT ; /* 0x000002000200780c */
/* 0x000fe40003f26270 */
/*0120*/ IMNMX R2, RZ, R2, !PT ; /* 0x00000002ff027217 */
/* 0x000fe20007800200 */
/*0130*/ IMAD R3, R4, c[0x0][0x8], R7 ; /* 0x0000020004037a24 */
/* 0x004fe200078e0207 */
/*0140*/ SEL R0, R0, 0x7fc0000, !P2 ; /* 0x07fc000000007807 */
/* 0x000fe20005000000 */
/*0150*/ HFMA2.MMA R7, -RZ, RZ, 1.984375, 0 ; /* 0x3ff00000ff077435 */
/* 0x000fe200000001ff */
/*0160*/ SHF.L.U32 R2, R2, 0x9, RZ ; /* 0x0000000902027819 */
/* 0x000fc400000006ff */
/*0170*/ ISETP.GE.AND P0, PT, R3, 0x200, PT ; /* 0x000002000300780c */
/* 0x000fe40003f06270 */
/*0180*/ IMNMX R3, RZ, R3, !PT ; /* 0x00000003ff037217 */
/* 0x000fe40007800200 */
/*0190*/ SEL R2, R2, 0x3fe00, !P1 ; /* 0x0003fe0002027807 */
/* 0x000fe40004800000 */
/*01a0*/ SEL R3, R3, 0x1ff, !P0 ; /* 0x000001ff03037807 */
/* 0x000fc80004000000 */
/*01b0*/ IADD3 R0, R2, R0, R3 ; /* 0x0000000002007210 */
/* 0x000fca0007ffe003 */
/*01c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*01d0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e0205 */
/*01e0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101b04 */
/*01f0*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x000fe2000c101b04 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10initializePdS_
.globl _Z10initializePdS_
.p2align 8
.type _Z10initializePdS_,@function
_Z10initializePdS_:
s_load_b64 s[2:3], s[0:1], 0x1c
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s14, s2, v[2:3]
v_mad_u64_u32 v[4:5], null, s13, s4, v[1:2]
s_and_b32 s2, s3, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_med3_i32 v0, v3, 0, 0x1ff
s_load_b128 s[0:3], s[0:1], 0x0
v_med3_i32 v2, v4, 0, 0x1ff
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b32_e32 v0, 9, v0
v_med3_i32 v3, v1, 0, 0x1ff
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 18, v2
v_or3_b32 v0, v3, v0, v2
v_dual_mov_b32 v3, 0x3ff00000 :: v_dual_mov_b32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b64 v[4:5], v[2:3], off
v_mov_b32_e32 v3, 0x40140000
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initializePdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10initializePdS_, .Lfunc_end0-_Z10initializePdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initializePdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10initializePdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a55f0_00000000-6_Multi_GPU_Test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5divUpii
.type _Z5divUpii, @function
_Z5divUpii:
.LFB3970:
.cfi_startproc
endbr64
leal -1(%rsi,%rdi), %eax
cltd
idivl %esi
ret
.cfi_endproc
.LFE3970:
.size _Z5divUpii, .-_Z5divUpii
.globl _Z7idxClipii
.type _Z7idxClipii, @function
_Z7idxClipii:
.LFB3971:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3971:
.size _Z7idxClipii, .-_Z7idxClipii
.globl _Z7flatteniiiiii
.type _Z7flatteniiiiii, @function
_Z7flatteniiiiii:
.LFB3972:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3972:
.size _Z7flatteniiiiii, .-_Z7flatteniiiiii
.globl _Z32__device_stub__Z10initializePdS_PdS_
.type _Z32__device_stub__Z10initializePdS_PdS_, @function
_Z32__device_stub__Z10initializePdS_PdS_:
.LFB4000:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10initializePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4000:
.size _Z32__device_stub__Z10initializePdS_PdS_, .-_Z32__device_stub__Z10initializePdS_PdS_
.globl _Z10initializePdS_
.type _Z10initializePdS_, @function
_Z10initializePdS_:
.LFB4001:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10initializePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4001:
.size _Z10initializePdS_, .-_Z10initializePdS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string " The number of divisions in the X-direction is %d\n"
.text
.globl _Z19initialize_multiGPUiPdS_
.type _Z19initialize_multiGPUiPdS_, @function
_Z19initialize_multiGPUiPdS_:
.LFB3974:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %r13d
movq %rsi, %r14
movq %rdx, %r15
movl $512, %eax
movl $0, %edx
idivl %edi
movl %eax, %r12d
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8, 8(%rsp)
movl $8, 12(%rsp)
movl $8, 16(%rsp)
leal 14(%r12), %eax
movl %r12d, %edx
addl $7, %edx
cmovns %edx, %eax
sarl $3, %eax
movl %eax, 20(%rsp)
movl $64, 24(%rsp)
movl $64, 28(%rsp)
testl %r13d, %r13d
jle .L16
sall $18, %r12d
movl $0, %ebp
movl $0, %ebx
jmp .L19
.L18:
addl $1, %ebx
addl %r12d, %ebp
cmpl %ebx, %r13d
je .L16
.L19:
movl %ebx, %edi
call cudaSetDevice@PLT
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movslq %ebp, %rdi
salq $3, %rdi
leaq (%r15,%rdi), %rsi
addq %r14, %rdi
call _Z32__device_stub__Z10initializePdS_PdS_
jmp .L18
.L16:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3974:
.size _Z19initialize_multiGPUiPdS_, .-_Z19initialize_multiGPUiPdS_
.globl _Z20initialize_singleGPUPdS_
.type _Z20initialize_singleGPUPdS_, @function
_Z20initialize_singleGPUPdS_:
.LFB3973:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbx
movq %rsi, %rbp
movl $8, 8(%rsp)
movl $8, 12(%rsp)
movl $64, 20(%rsp)
movl $64, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $8, %ecx
movq 20(%rsp), %rdi
movl $64, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L22:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq %rbp, %rsi
movq %rbx, %rdi
call _Z32__device_stub__Z10initializePdS_PdS_
jmp .L22
.cfi_endproc
.LFE3973:
.size _Z20initialize_singleGPUPdS_, .-_Z20initialize_singleGPUPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string " Device name: %s\n"
.section .rodata.str1.8
.align 8
.LC3:
.string " Memory Clock Rate (KHz): %d\n"
.align 8
.LC4:
.string " Memory Bus Width (bits): %d\n"
.align 8
.LC6:
.string " Peak Memory Bandwidth (GB/s): %f\n\n"
.align 8
.LC7:
.string "The value of f1 is %d, which should equal to 6*NX*NY*NZ, %d\n"
.align 8
.LC8:
.string "The value of f2 is %d, which should equal to 6*NX*NY*NZ, %d\n"
.text
.globl main
.type main, @function
main:
.LFB3975:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1096, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $1073741824, %esi
call cudaMallocManaged@PLT
movl $0, %edi
call cudaSetDevice@PLT
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z20initialize_singleGPUPdS_
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rsi
movq 32(%rsp), %rcx
movl $4096, %r9d
movl $0, %r8d
movq $0x000000000, 8(%rsp)
.L27:
movq %r8, %rdi
salq $21, %rdi
addq $2101248, %rdi
movq %r9, %rdx
.L31:
leaq -4096(%rdx), %rax
.L28:
movsd (%rsi,%rax), %xmm0
addsd (%rcx,%rax), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $8, %rax
cmpq %rdx, %rax
jne .L28
addq $4096, %rdx
cmpq %rdi, %rdx
jne .L31
addq $1, %r8
addq $2097152, %r9
cmpq $512, %r8
jne .L27
movl $0, %ebx
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r12
.L30:
movl %ebx, 40(%rsp,%rbx,4)
movl %ebx, %edi
call cudaSetDevice@PLT
leaq 48(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 656(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 660(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 656(%rsp), %xmm0
addsd %xmm0, %xmm0
movl 660(%rsp), %edx
leal 7(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $3, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
mulsd %xmm1, %xmm0
divsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $2, %rbx
jne .L30
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movl $2, %edi
call _Z19initialize_multiGPUiPdS_
movl 40(%rsp), %edi
call cudaSetDevice@PLT
call cudaDeviceSynchronize@PLT
movl 44(%rsp), %edi
call cudaSetDevice@PLT
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rsi
movq 32(%rsp), %rcx
movl $4096, %r9d
movl $0, %r8d
movq $0x000000000, (%rsp)
.L32:
movq %r8, %rdi
salq $21, %rdi
addq $2101248, %rdi
movq %r9, %rdx
.L36:
leaq -4096(%rdx), %rax
.L33:
movsd (%rsi,%rax), %xmm0
addsd (%rcx,%rax), %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
addq $8, %rax
cmpq %rdx, %rax
jne .L33
addq $4096, %rdx
cmpq %rdi, %rdx
jne .L36
addq $1, %r8
addq $2097152, %r9
cmpq $512, %r8
jne .L32
cvttsd2sil 8(%rsp), %edx
movl $805306368, %ecx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cvttsd2sil (%rsp), %edx
movl $805306368, %ecx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z10initializePdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4003:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializePdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4003:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Multi_GPU_Test.hip"
.globl _Z5divUpii # -- Begin function _Z5divUpii
.p2align 4, 0x90
.type _Z5divUpii,@function
_Z5divUpii: # @_Z5divUpii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
# kill: def $edi killed $edi def $rdi
leal (%rdi,%rsi), %eax
decl %eax
cltd
idivl %esi
retq
.Lfunc_end0:
.size _Z5divUpii, .Lfunc_end0-_Z5divUpii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__initializePdS_ # -- Begin function _Z25__device_stub__initializePdS_
.p2align 4, 0x90
.type _Z25__device_stub__initializePdS_,@function
_Z25__device_stub__initializePdS_: # @_Z25__device_stub__initializePdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10initializePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__initializePdS_, .Lfunc_end1-_Z25__device_stub__initializePdS_
.cfi_endproc
# -- End function
.globl _Z20initialize_singleGPUPdS_ # -- Begin function _Z20initialize_singleGPUPdS_
.p2align 4, 0x90
.type _Z20initialize_singleGPUPdS_,@function
_Z20initialize_singleGPUPdS_: # @_Z20initialize_singleGPUPdS_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $34359738376, %rdx # imm = 0x800000008
movl $64, %esi
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10initializePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z20initialize_singleGPUPdS_, .Lfunc_end2-_Z20initialize_singleGPUPdS_
.cfi_endproc
# -- End function
.globl _Z19initialize_multiGPUiPdS_ # -- Begin function _Z19initialize_multiGPUiPdS_
.p2align 4, 0x90
.type _Z19initialize_multiGPUiPdS_,@function
_Z19initialize_multiGPUiPdS_: # @_Z19initialize_multiGPUiPdS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 8(%rsp) # 8-byte Spill
movq %rsi, (%rsp) # 8-byte Spill
movl %edi, %ebp
xorl %ebx, %ebx
movl $512, %eax # imm = 0x200
xorl %edx, %edx
idivl %edi
movl %eax, %r15d
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
leal 7(%r15), %ecx
leal 14(%r15), %eax
testl %ecx, %ecx
cmovnsl %ecx, %eax
testl %ebp, %ebp
jle .LBB3_5
# %bb.1: # %.lr.ph
sarl $3, %eax
movabsq $274877906944, %r12 # imm = 0x4000000000
orq %rax, %r12
shll $18, %r15d
movl %ebp, %r14d
movabsq $34359738376, %r13 # imm = 0x800000008
xorl %ebp, %ebp
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
incq %rbp
addl %r15d, %ebx
cmpq %rbp, %r14
je .LBB3_5
.LBB3_2: # =>This Inner Loop Header: Depth=1
movl %ebp, %edi
callq hipSetDevice
movq %r12, %rdi
movl $64, %esi
movq %r13, %rdx
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movslq %ebx, %rax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rcx
movq 8(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,8), %rax
movq %rcx, 72(%rsp)
movq %rax, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z10initializePdS_, %edi
leaq 80(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_4
.LBB3_5: # %._crit_edge
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z19initialize_multiGPUiPdS_, .Lfunc_end3-_Z19initialize_multiGPUiPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $1504, %rsp # imm = 0x5E0
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
leaq -48(%rbp), %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
leaq -40(%rbp), %rdi
movl $1073741824, %esi # imm = 0x40000000
movl $1, %edx
callq hipMallocManaged
xorl %ebx, %ebx
xorl %edi, %edi
callq hipSetDevice
movq -48(%rbp), %rdi
movq -40(%rbp), %rsi
callq _Z20initialize_singleGPUPdS_
callq hipDeviceSynchronize
movq -48(%rbp), %rax
xorpd %xmm1, %xmm1
movq -40(%rbp), %rcx
.p2align 4, 0x90
.LBB4_1: # %.preheader53
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
# Child Loop BB4_3 Depth 3
movq %rax, %rdx
movq %rcx, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB4_2: # %.preheader52
# Parent Loop BB4_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_3 Depth 3
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_1 Depth=1
# Parent Loop BB4_2 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rdx,%r8,8), %xmm0 # xmm0 = mem[0],zero
addsd (%rsi,%r8,8), %xmm0
addsd %xmm0, %xmm1
incq %r8
cmpq $512, %r8 # imm = 0x200
jne .LBB4_3
# %bb.4: # in Loop: Header=BB4_2 Depth=2
incq %rdi
addq $4096, %rsi # imm = 0x1000
addq $4096, %rdx # imm = 0x1000
cmpq $512, %rdi # imm = 0x200
jne .LBB4_2
# %bb.5: # in Loop: Header=BB4_1 Depth=1
incq %rbx
addq $2097152, %rcx # imm = 0x200000
addq $2097152, %rax # imm = 0x200000
cmpq $512, %rbx # imm = 0x200
jne .LBB4_1
# %bb.6:
movsd %xmm1, -56(%rbp) # 8-byte Spill
movq %rsp, %r15
movq %rsp, %r12
addq $-16, %r12
movq %r12, %rsp
leaq -1528(%rbp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_7: # =>This Inner Loop Header: Depth=1
movl %r14d, (%r12,%r14,4)
movl %r14d, %edi
callq hipSetDevice
movq %rbx, %rdi
movl %r14d, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl -920(%rbp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl -916(%rbp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorps %xmm1, %xmm1
cvtsi2sdl -920(%rbp), %xmm1
addsd %xmm1, %xmm1
movl -916(%rbp), %eax
leal 7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $3, %ecx
xorps %xmm0, %xmm0
cvtsi2sd %ecx, %xmm0
mulsd %xmm1, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
incq %r14
cmpq $1, %r14
je .LBB4_7
# %bb.8:
movq -48(%rbp), %rsi
movq -40(%rbp), %rdx
movl $2, %edi
callq _Z19initialize_multiGPUiPdS_
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_9: # =>This Inner Loop Header: Depth=1
movl (%r12,%rbx,4), %edi
callq hipSetDevice
callq hipDeviceSynchronize
incq %rbx
cmpq $1, %rbx
je .LBB4_9
# %bb.10: # %.preheader51
movq -48(%rbp), %rax
xorpd %xmm2, %xmm2
movq -40(%rbp), %rcx
xorl %edx, %edx
movsd -56(%rbp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB4_11: # %.preheader50
# =>This Loop Header: Depth=1
# Child Loop BB4_12 Depth 2
# Child Loop BB4_13 Depth 3
movq %rax, %rsi
movq %rcx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB4_12: # %.preheader
# Parent Loop BB4_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_13 Depth 3
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB4_13: # Parent Loop BB4_11 Depth=1
# Parent Loop BB4_12 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rsi,%r9,8), %xmm0 # xmm0 = mem[0],zero
addsd (%rdi,%r9,8), %xmm0
addsd %xmm0, %xmm2
incq %r9
cmpq $512, %r9 # imm = 0x200
jne .LBB4_13
# %bb.14: # in Loop: Header=BB4_12 Depth=2
incq %r8
addq $4096, %rdi # imm = 0x1000
addq $4096, %rsi # imm = 0x1000
cmpq $512, %r8 # imm = 0x200
jne .LBB4_12
# %bb.15: # in Loop: Header=BB4_11 Depth=1
incq %rdx
addq $2097152, %rcx # imm = 0x200000
addq $2097152, %rax # imm = 0x200000
cmpq $512, %rdx # imm = 0x200
jne .LBB4_11
# %bb.16:
cvttsd2si %xmm1, %esi
movl $.L.str.5, %edi
movl $805306368, %edx # imm = 0x30000000
xorl %eax, %eax
movsd %xmm2, -56(%rbp) # 8-byte Spill
callq printf
cvttsd2si -56(%rbp), %esi # 8-byte Folded Reload
movl $.L.str.6, %edi
movl $805306368, %edx # imm = 0x30000000
xorl %eax, %eax
callq printf
movq -48(%rbp), %rdi
callq hipFree
movq -40(%rbp), %rdi
callq hipFree
movq %r15, %rsp
xorl %eax, %eax
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializePdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10initializePdS_,@object # @_Z10initializePdS_
.section .rodata,"a",@progbits
.globl _Z10initializePdS_
.p2align 3, 0x0
_Z10initializePdS_:
.quad _Z25__device_stub__initializePdS_
.size _Z10initializePdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " The number of divisions in the X-direction is %d\n"
.size .L.str, 53
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Device name: %s\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Memory Clock Rate (KHz): %d\n"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Memory Bus Width (bits): %d\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Peak Memory Bandwidth (GB/s): %f\n\n"
.size .L.str.4, 37
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "The value of f1 is %d, which should equal to 6*NX*NY*NZ, %d\n"
.size .L.str.5, 61
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "The value of f2 is %d, which should equal to 6*NX*NY*NZ, %d\n"
.size .L.str.6, 61
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10initializePdS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__initializePdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10initializePdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <cassert>
#include <iostream>
using namespace std;
const int Tile_size = 2;
// Compute C = A * B
//*************************************************************
//Kernel for shared memory/ Tiled execution
__global__ void matrixMul(double *A, double *X, double *B, long rows, long cols){
int tid= threadIdx.x + blockIdx.x * blockDim.x;
double sum= 0;
if(tid < rows){
for(int i=0; i < cols; i++){
sum += X[i] * A[(i * rows) + tid];
}
B[tid]=sum;
}
}
//*************************************************************
void Print_Mat(int Row,int Col,double * Mat){//Function To print the Matrix
for(int i=0; i < Row; ++i){
for(int j=0; j < Col; ++j){
cout << Mat[i * Row + j] << " ";
}
cout << endl;
}
}//Function close
//*************************************************************
//Normal CPU Matrix Multiplication
void matMultiplyOnHost(float * A, float * B, float * C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns){
for (int i=0; i < numARows; i ++){
for (int j= 0; j < numAColumns; j++){
C[i*numCColumns + j ] = 0.0;
for (int k = 0; k < numCColumns; k++){
C[i*numCColumns + j ] += A[i*numAColumns + k] * B [k*numBColumns + j];
}
}
}
}
//*************************************************************
extern "C++" void generate_b_gpu(double *hostA, double *hostX, double *hostB, long cols, long rows) {
double *deviceA;
double *deviceB;
double *deviceX;
// Allocating GPU memory
assert(cudaSuccess == cudaMalloc((void **)&deviceA, sizeof(double)*cols*rows));
assert(cudaSuccess == cudaMalloc((void **)&deviceB, sizeof(double)*rows));
assert(cudaSuccess == cudaMalloc((void **)&deviceX, sizeof(double)*rows));
// Copy memory to the GPU
assert(cudaSuccess == cudaMemcpy(deviceA, hostA, sizeof(double)*cols*rows, cudaMemcpyHostToDevice));
assert(cudaSuccess == cudaMemcpy(deviceX, hostX, sizeof(float)*rows, cudaMemcpyHostToDevice));
// Initialize the grid and block dimensions
dim3 dimGrid((1/Tile_size) + 1, (rows/Tile_size) + 1, 1);//Number of Blocks required
dim3 dimBlock(Tile_size, Tile_size, 1);//Number of threads in each block
//@@ Launch the GPU Kernel here
matrixMul<<<dimGrid, dimBlock>>>(deviceA, deviceX, deviceB, rows, cols);
cudaError_t err1 = cudaPeekAtLastError();//To capture last error in function call
cudaDeviceSynchronize();//To synchronize the device
// Copy the results in GPU memory back to the CPU
assert(cudaSuccess == cudaMemcpy(hostB, deviceB, sizeof(float)*rows, cudaMemcpyDeviceToHost));
cout << "GPU A" << endl;
Print_Mat(rows, cols, hostA);
//matMultiplyOnHost(hostA, hostB, hostComputedC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
//printf("\nMatrix C From Host\n");
//Print_Mat(numCRows,numCColumns,hostComputedC);//Function Call
//printf("\n Number of Blocks Created:%d \n",((1/Tile_size) + 1)*((1/Tile_size) + 1));
//printf("\n Number of Threads Per Block: %d \n",(Tile_size*Tile_size));
// Free the GPU memory
assert(cudaSuccess == cudaFree(deviceA));
assert(cudaSuccess == cudaFree(deviceB));
assert(cudaSuccess == cudaFree(deviceX));
//Free the Pointer Memory
//free(hostA);
//free(hostB);
//free(hostX);
} | code for sm_80
Function : _Z9matrixMulPdS_S_ll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011402 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x17c], PT, P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff007624 */
/* 0x000fe200078e00ff */
/*00b0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe4000001ff00 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc80003f06070 */
/*00d0*/ ISETP.GE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0003f06300 */
/*00e0*/ @!P0 BRA 0xf70 ; /* 0x00000e8000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R5, P1, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fe20007f3e0ff */
/*0100*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0110*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe4000001ff00 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*0130*/ IADD3.X R0, R0, -0x1, RZ, P1, !PT ; /* 0xffffffff00007810 */
/* 0x000fc80000ffe4ff */
/*0140*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe40003f06100 */
/*0150*/ LOP3.LUT R0, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304007812 */
/* 0x000fd600078ec0ff */
/*0160*/ @!P0 BRA 0xd80 ; /* 0x00000c1000008947 */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R17, P0, R0, -c[0x0][0x180], RZ ; /* 0x8000600000117a10 */
/* 0x000fe20007f1e0ff */
/*0180*/ UMOV UR6, 0x3 ; /* 0x0000000300067882 */
/* 0x000fe20000000000 */
/*0190*/ LEA R10, P1, R2, c[0x0][0x160], 0x3 ; /* 0x00005800020a7a11 */
/* 0x000fe200078218ff */
/*01a0*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*01c0*/ IMAD.X R16, RZ, RZ, ~c[0x0][0x184], P0 ; /* 0x80006100ff107624 */
/* 0x000fe200000e06ff */
/*01d0*/ USHF.L.U64.HI UR6, UR4, UR6, UR5 ; /* 0x0000000604067299 */
/* 0x000fe20008010205 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*01f0*/ USHF.L.U32 UR5, UR4, 0x3, URZ ; /* 0x0000000304057899 */
/* 0x000fe2000800063f */
/*0200*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0210*/ ISETP.GE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f06270 */
/*0220*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0230*/ LEA.HI.X R11, R2, c[0x0][0x164], R3, 0x3, P1 ; /* 0x00005900020b7a11 */
/* 0x000fd600008f1c03 */
/*0240*/ @P0 BRA 0xbc0 ; /* 0x0000097000000947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R8, P0, RZ, -R17, RZ ; /* 0x80000011ff087210 */
/* 0x000fc80007f1e0ff */
/*0260*/ ISETP.GT.U32.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24070 */
/*0270*/ IMAD.X R8, RZ, RZ, ~R16, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0e10 */
/*0280*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0f070 */
/*0290*/ ISETP.GT.AND.EX P1, PT, R8, RZ, PT, P1 ; /* 0x000000ff0800720c */
/* 0x000fda0003f24310 */
/*02a0*/ @!P1 BRA 0x840 ; /* 0x0000059000009947 */
/* 0x000fea0003800000 */
/*02b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02c0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000804087981 */
/* 0x001ea8000c1e1b00 */
/*02d0*/ LDG.E.64 R20, [R10.64] ; /* 0x000000080a147981 */
/* 0x0000a2000c1e1b00 */
/*02e0*/ IADD3 R28, P1, R10, UR5, RZ ; /* 0x000000050a1c7c10 */
/* 0x000fc6000ff3e0ff */
/*02f0*/ LDG.E.64 R14, [R4.64+0x8] ; /* 0x00000808040e7981 */
/* 0x000ee2000c1e1b00 */
/*0300*/ IADD3.X R29, R11, UR6, RZ, P1, !PT ; /* 0x000000060b1d7c10 */
/* 0x000fe40008ffe4ff */
/*0310*/ IADD3 R26, P1, R28, UR5, RZ ; /* 0x000000051c1a7c10 */
/* 0x000fc6000ff3e0ff */
/*0320*/ LDG.E.64 R18, [R28.64] ; /* 0x000000081c127981 */
/* 0x000ee2000c1e1b00 */
/*0330*/ IADD3.X R27, R29, UR6, RZ, P1, !PT ; /* 0x000000061d1b7c10 */
/* 0x000fe40008ffe4ff */
/*0340*/ IADD3 R24, P1, R26, UR5, RZ ; /* 0x000000051a187c10 */
/* 0x000fe2000ff3e0ff */
/*0350*/ LDG.E.64 R10, [R4.64+0x10] ; /* 0x00001008040a7981 */
/* 0x001f28000c1e1b00 */
/*0360*/ LDG.E.64 R12, [R26.64] ; /* 0x000000081a0c7981 */
/* 0x000f22000c1e1b00 */
/*0370*/ IADD3.X R25, R27, UR6, RZ, P1, !PT ; /* 0x000000061b197c10 */
/* 0x000fe20008ffe4ff */
/*0380*/ DFMA R22, R20, R8, R6 ; /* 0x000000081416722b */
/* 0x0060c40000000006 */
/*0390*/ LDG.E.64 R6, [R4.64+0x18] ; /* 0x0000180804067981 */
/* 0x001ea8000c1e1b00 */
/*03a0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000818087981 */
/* 0x000ea2000c1e1b00 */
/*03b0*/ IADD3 R20, P1, R24, UR5, RZ ; /* 0x0000000518147c10 */
/* 0x000fc8000ff3e0ff */
/*03c0*/ IADD3.X R21, R25, UR6, RZ, P1, !PT ; /* 0x0000000619157c10 */
/* 0x000fe20008ffe4ff */
/*03d0*/ DFMA R28, R18, R14, R22 ; /* 0x0000000e121c722b */
/* 0x0081240000000016 */
/*03e0*/ IADD3 R22, P1, R20, UR5, RZ ; /* 0x0000000514167c10 */
/* 0x001fe2000ff3e0ff */
/*03f0*/ LDG.E.64 R14, [R4.64+0x20] ; /* 0x00002008040e7981 */
/* 0x000ee8000c1e1b00 */
/*0400*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000814127981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IADD3.X R23, R21, UR6, RZ, P1, !PT ; /* 0x0000000615177c10 */
/* 0x000fe20008ffe4ff */
/*0420*/ DFMA R26, R12, R10, R28 ; /* 0x0000000a0c1a722b */
/* 0x010084000000001c */
/*0430*/ IADD3 R28, P1, R22, UR5, RZ ; /* 0x00000005161c7c10 */
/* 0x001fe2000ff3e0ff */
/*0440*/ LDG.E.64 R10, [R4.64+0x28] ; /* 0x00002808040a7981 */
/* 0x000f26000c1e1b00 */
/*0450*/ IADD3.X R29, R23, UR6, RZ, P1, !PT ; /* 0x00000006171d7c10 */
/* 0x000fe20008ffe4ff */
/*0460*/ LDG.E.64 R12, [R22.64] ; /* 0x00000008160c7981 */
/* 0x000122000c1e1b00 */
/*0470*/ DFMA R26, R8, R6, R26 ; /* 0x00000006081a722b */
/* 0x0042c6000000001a */
/*0480*/ LDG.E.64 R6, [R4.64+0x30] ; /* 0x0000300804067981 */
/* 0x002ea8000c1e1b00 */
/*0490*/ LDG.E.64 R8, [R28.64] ; /* 0x000000081c087981 */
/* 0x000ea2000c1e1b00 */
/*04a0*/ IADD3 R24, P1, R28, UR5, RZ ; /* 0x000000051c187c10 */
/* 0x000fc8000ff3e0ff */
/*04b0*/ IADD3.X R25, R29, UR6, RZ, P1, !PT ; /* 0x000000061d197c10 */
/* 0x000fe20008ffe4ff */
/*04c0*/ DFMA R14, R18, R14, R26 ; /* 0x0000000e120e722b */
/* 0x008324000000001a */
/*04d0*/ IADD3 R26, P1, R24, UR5, RZ ; /* 0x00000005181a7c10 */
/* 0x002fe2000ff3e0ff */
/*04e0*/ LDG.E.64 R18, [R4.64+0x38] ; /* 0x0000380804127981 */
/* 0x000ee8000c1e1b00 */
/*04f0*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000818147981 */
/* 0x0002e2000c1e1b00 */
/*0500*/ IADD3.X R27, R25, UR6, RZ, P1, !PT ; /* 0x00000006191b7c10 */
/* 0x000fe40008ffe4ff */
/*0510*/ IADD3 R22, P1, R26, UR5, RZ ; /* 0x000000051a167c10 */
/* 0x001fe2000ff3e0ff */
/*0520*/ DFMA R14, R12, R10, R14 ; /* 0x0000000a0c0e722b */
/* 0x010084000000000e */
/*0530*/ LDG.E.64 R12, [R4.64+0x40] ; /* 0x00004008040c7981 */
/* 0x001f22000c1e1b00 */
/*0540*/ IADD3.X R23, R27, UR6, RZ, P1, !PT ; /* 0x000000061b177c10 */
/* 0x000fc60008ffe4ff */
/*0550*/ LDG.E.64 R10, [R26.64] ; /* 0x000000081a0a7981 */
/* 0x000122000c1e1b00 */
/*0560*/ DFMA R28, R8, R6, R14 ; /* 0x00000006081c722b */
/* 0x0044c6000000000e */
/*0570*/ LDG.E.64 R8, [R4.64+0x48] ; /* 0x0000480804087981 */
/* 0x004ea8000c1e1b00 */
/*0580*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000816067981 */
/* 0x000aa2000c1e1b00 */
/*0590*/ IADD3 R14, P1, R22, UR5, RZ ; /* 0x00000005160e7c10 */
/* 0x000fc8000ff3e0ff */
/*05a0*/ IADD3.X R15, R23, UR6, RZ, P1, !PT ; /* 0x00000006170f7c10 */
/* 0x000fe40008ffe4ff */
/*05b0*/ IADD3 R24, P1, R14, UR5, RZ ; /* 0x000000050e187c10 */
/* 0x002fe2000ff3e0ff */
/*05c0*/ DFMA R28, R20, R18, R28 ; /* 0x00000012141c722b */
/* 0x008324000000001c */
/*05d0*/ LDG.E.64 R20, [R4.64+0x50] ; /* 0x0000500804147981 */
/* 0x002ee8000c1e1b00 */
/*05e0*/ LDG.E.64 R18, [R14.64] ; /* 0x000000080e127981 */
/* 0x0002e2000c1e1b00 */
/*05f0*/ IADD3.X R25, R15, UR6, RZ, P1, !PT ; /* 0x000000060f197c10 */
/* 0x000fc40008ffe4ff */
/*0600*/ IADD3 R26, P1, R24, UR5, RZ ; /* 0x00000005181a7c10 */
/* 0x001fe2000ff3e0ff */
/*0610*/ DFMA R28, R10, R12, R28 ; /* 0x0000000c0a1c722b */
/* 0x0100a4000000001c */
/*0620*/ LDG.E.64 R10, [R4.64+0x58] ; /* 0x00005808040a7981 */
/* 0x001f22000c1e1b00 */
/*0630*/ IADD3.X R27, R25, UR6, RZ, P1, !PT ; /* 0x00000006191b7c10 */
/* 0x000fc60008ffe4ff */
/*0640*/ LDG.E.64 R12, [R24.64] ; /* 0x00000008180c7981 */
/* 0x000f28000c1e1b00 */
/*0650*/ LDG.E.64 R22, [R26.64] ; /* 0x000000081a167981 */
/* 0x020f62000c1e1b00 */
/*0660*/ DFMA R8, R6, R8, R28 ; /* 0x000000080608722b */
/* 0x0040c6000000001c */
/*0670*/ LDG.E.64 R6, [R4.64+0x60] ; /* 0x0000600804067981 */
/* 0x001f62000c1e1b00 */
/*0680*/ IADD3 R28, P1, R26, UR5, RZ ; /* 0x000000051a1c7c10 */
/* 0x000fc8000ff3e0ff */
/*0690*/ IADD3.X R29, R27, UR6, RZ, P1, !PT ; /* 0x000000061b1d7c10 */
/* 0x000fe40008ffe4ff */
/*06a0*/ IADD3 R14, P1, R28, UR5, RZ ; /* 0x000000051c0e7c10 */
/* 0x002fe2000ff3e0ff */
/*06b0*/ DFMA R8, R18, R20, R8 ; /* 0x000000141208722b */
/* 0x0081060000000008 */
/*06c0*/ IADD3.X R15, R29, UR6, RZ, P1, !PT ; /* 0x000000061d0f7c10 */
/* 0x000fe20008ffe4ff */
/*06d0*/ LDG.E.64 R18, [R4.64+0x68] ; /* 0x0000680804127981 */
/* 0x001ea2000c1e1b00 */
/*06e0*/ IADD3 R20, P1, R14, UR5, RZ ; /* 0x000000050e147c10 */
/* 0x000fc6000ff3e0ff */
/*06f0*/ LDG.E.64 R28, [R28.64] ; /* 0x000000081c1c7981 */
/* 0x000ea2000c1e1b00 */
/*0700*/ IADD3.X R21, R15, UR6, RZ, P1, !PT ; /* 0x000000060f157c10 */
/* 0x000fe20008ffe4ff */
/*0710*/ DFMA R10, R12, R10, R8 ; /* 0x0000000a0c0a722b */
/* 0x0101640000000008 */
/*0720*/ LDG.E.64 R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000ee8000c1e1b00 */
/*0730*/ LDG.E.64 R8, [R4.64+0x70] ; /* 0x0000700804087981 */
/* 0x0010e8000c1e1b00 */
/*0740*/ LDG.E.64 R12, [R4.64+0x78] ; /* 0x00007808040c7981 */
/* 0x000122000c1e1b00 */
/*0750*/ DFMA R10, R22, R6, R10 ; /* 0x00000006160a722b */
/* 0x020286000000000a */
/*0760*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000814067981 */
/* 0x002f22000c1e1b00 */
/*0770*/ IADD3 R17, P1, R17, 0x10, RZ ; /* 0x0000001011117810 */
/* 0x000fca0007f3e0ff */
/*0780*/ IMAD.X R16, RZ, RZ, R16, P1 ; /* 0x000000ffff107224 */
/* 0x000fe200008e0610 */
/*0790*/ ISETP.GE.U32.AND P1, PT, R17, -0xc, PT ; /* 0xfffffff41100780c */
/* 0x000fc80003f26070 */
/*07a0*/ ISETP.GE.AND.EX P1, PT, R16, -0x1, PT, P1 ; /* 0xffffffff1000780c */
/* 0x000fe20003f26310 */
/*07b0*/ DFMA R10, R28, R18, R10 ; /* 0x000000121c0a722b */
/* 0x004ee2000000000a */
/*07c0*/ IADD3 R4, P2, R4, 0x80, RZ ; /* 0x0000008004047810 */
/* 0x001fe20007f5e0ff */
/*07d0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc8000fffe03f */
/*07e0*/ DFMA R8, R14, R8, R10 ; /* 0x000000080e08722b */
/* 0x008124000000000a */
/*07f0*/ IADD3 R10, P3, R20, UR5, RZ ; /* 0x00000005140a7c10 */
/* 0x001fe2000ff7e0ff */
/*0800*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fc600010e0605 */
/*0810*/ IADD3.X R11, R21, UR6, RZ, P3, !PT ; /* 0x00000006150b7c10 */
/* 0x000fe20009ffe4ff */
/*0820*/ DFMA R6, R6, R12, R8 ; /* 0x0000000c0606722b */
/* 0x0100620000000008 */
/*0830*/ @!P1 BRA 0x2c0 ; /* 0xfffffa8000009947 */
/* 0x000fea000383ffff */
/*0840*/ IADD3 R8, P2, RZ, -R17, RZ ; /* 0x80000011ff087210 */
/* 0x001fc80007f5e0ff */
/*0850*/ ISETP.GT.U32.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fe20003f24070 */
/*0860*/ IMAD.X R8, RZ, RZ, ~R16, P2 ; /* 0x000000ffff087224 */
/* 0x000fca00010e0e10 */
/*0870*/ ISETP.GT.AND.EX P1, PT, R8, RZ, PT, P1 ; /* 0x000000ff0800720c */
/* 0x000fda0003f24310 */
/*0880*/ @!P1 BRA 0xb90 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*0890*/ IADD3 R18, P0, R10, UR5, RZ ; /* 0x000000050a127c10 */
/* 0x000fe2000ff1e0ff */
/*08a0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000804087981 */
/* 0x000ea8000c1e1b00 */
/*08b0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000080a0c7981 */
/* 0x0000a2000c1e1b00 */
/*08c0*/ IADD3.X R19, R11, UR6, RZ, P0, !PT ; /* 0x000000060b137c10 */
/* 0x000fc600087fe4ff */
/*08d0*/ LDG.E.64 R24, [R4.64+0x8] ; /* 0x0000080804187981 */
/* 0x000ee8000c1e1b00 */
/*08e0*/ LDG.E.64 R22, [R4.64+0x10] ; /* 0x0000100804167981 */
/* 0x000f28000c1e1b00 */
/*08f0*/ LDG.E.64 R10, [R18.64] ; /* 0x00000008120a7981 */
/* 0x001ee2000c1e1b00 */
/*0900*/ IADD3 R20, P0, R18, UR5, RZ ; /* 0x0000000512147c10 */
/* 0x000fc8000ff1e0ff */
/*0910*/ IADD3.X R21, R19, UR6, RZ, P0, !PT ; /* 0x0000000613157c10 */
/* 0x000fe400087fe4ff */
/*0920*/ IADD3 R28, P0, R20, UR5, RZ ; /* 0x00000005141c7c10 */
/* 0x000fc8000ff1e0ff */
/*0930*/ IADD3.X R29, R21, UR6, RZ, P0, !PT ; /* 0x00000006151d7c10 */
/* 0x000fe400087fe4ff */
/*0940*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000814147981 */
/* 0x000f22000c1e1b00 */
/*0950*/ IADD3 R26, P0, R28, UR5, RZ ; /* 0x000000051c1a7c10 */
/* 0x000fc6000ff1e0ff */
/*0960*/ LDG.E.64 R14, [R28.64] ; /* 0x000000081c0e7981 */
/* 0x000f62000c1e1b00 */
/*0970*/ IADD3.X R27, R29, UR6, RZ, P0, !PT ; /* 0x000000061d1b7c10 */
/* 0x000fe200087fe4ff */
/*0980*/ DFMA R12, R12, R8, R6 ; /* 0x000000080c0c722b */
/* 0x0060e40000000006 */
/*0990*/ LDG.E.64 R8, [R4.64+0x18] ; /* 0x0000180804087981 */
/* 0x001f68000c1e1b00 */
/*09a0*/ DFMA R24, R10, R24, R12 ; /* 0x000000180a18722b */
/* 0x008124000000000c */
/*09b0*/ LDG.E.64 R10, [R4.64+0x20] ; /* 0x00002008040a7981 */
/* 0x001ea8000c1e1b00 */
/*09c0*/ LDG.E.64 R12, [R26.64] ; /* 0x000000081a0c7981 */
/* 0x000ea2000c1e1b00 */
/*09d0*/ IADD3 R18, P0, R26, UR5, RZ ; /* 0x000000051a127c10 */
/* 0x000fc8000ff1e0ff */
/*09e0*/ IADD3.X R19, R27, UR6, RZ, P0, !PT ; /* 0x000000061b137c10 */
/* 0x000fe400087fe4ff */
/*09f0*/ IADD3 R6, P0, R18, UR5, RZ ; /* 0x0000000512067c10 */
/* 0x000fe2000ff1e0ff */
/*0a00*/ DFMA R20, R20, R22, R24 ; /* 0x000000161414722b */
/* 0x0101640000000018 */
/*0a10*/ LDG.E.64 R22, [R4.64+0x28] ; /* 0x0000280804167981 */
/* 0x001ee2000c1e1b00 */
/*0a20*/ IADD3.X R7, R19, UR6, RZ, P0, !PT ; /* 0x0000000613077c10 */
/* 0x000fe400087fe4ff */
/*0a30*/ IADD3 R24, P0, R6, UR5, RZ ; /* 0x0000000506187c10 */
/* 0x000fe2000ff1e0ff */
/*0a40*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000812127981 */
/* 0x000ee6000c1e1b00 */
/*0a50*/ IADD3.X R25, R7, UR6, RZ, P0, !PT ; /* 0x0000000607197c10 */
/* 0x000fc400087fe4ff */
/*0a60*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000f22000c1e1b00 */
/*0a70*/ DFMA R14, R14, R8, R20 ; /* 0x000000080e0e722b */
/* 0x0200860000000014 */
/*0a80*/ LDG.E.64 R8, [R4.64+0x30] ; /* 0x0000300804087981 */
/* 0x001126000c1e1b00 */
/*0a90*/ DFMA R10, R12, R10, R14 ; /* 0x0000000a0c0a722b */
/* 0x0042c8000000000e */
/*0aa0*/ LDG.E.64 R14, [R4.64+0x38] ; /* 0x00003808040e7981 */
/* 0x0020a8000c1e1b00 */
/*0ab0*/ LDG.E.64 R12, [R24.64] ; /* 0x00000008180c7981 */
/* 0x000ea2000c1e1b00 */
/*0ac0*/ DFMA R10, R18, R22, R10 ; /* 0x00000016120a722b */
/* 0x008324000000000a */
/*0ad0*/ IADD3 R18, P2, R4, 0x40, RZ ; /* 0x0000004004127810 */
/* 0x002fe40007f5e0ff */
/*0ae0*/ IADD3 R17, P3, R17, 0x8, RZ ; /* 0x0000000811117810 */
/* 0x000fc60007f7e0ff */
/*0af0*/ IMAD.X R19, RZ, RZ, R5, P2 ; /* 0x000000ffff137224 */
/* 0x000fe200010e0605 */
/*0b00*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0b10*/ IMAD.X R16, RZ, RZ, R16, P3 ; /* 0x000000ffff107224 */
/* 0x000fe400018e0610 */
/*0b20*/ IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0012 */
/*0b30*/ IMAD.MOV.U32 R5, RZ, RZ, R19 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0013 */
/*0b40*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0b50*/ DFMA R8, R6, R8, R10 ; /* 0x000000080608722b */
/* 0x0100a4000000000a */
/*0b60*/ IADD3 R10, P1, R24, UR5, RZ ; /* 0x00000005180a7c10 */
/* 0x001fc8000ff3e0ff */
/*0b70*/ IADD3.X R11, R25, UR6, RZ, P1, !PT ; /* 0x00000006190b7c10 */
/* 0x000fe20008ffe4ff */
/*0b80*/ DFMA R6, R12, R14, R8 ; /* 0x0000000e0c06722b */
/* 0x0040480000000008 */
/*0b90*/ ISETP.NE.U32.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fc80003f25070 */
/*0ba0*/ ISETP.NE.OR.EX P0, PT, R16, RZ, P0, P1 ; /* 0x000000ff1000720c */
/* 0x000fda0000705710 */
/*0bb0*/ @!P0 BRA 0xd80 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ LDG.E.64 R20, [R4.64] ; /* 0x0000000804147981 */
/* 0x000ea8000c1e1b00 */
/*0bd0*/ LDG.E.64 R22, [R10.64] ; /* 0x000000080a167981 */
/* 0x0006a2000c1e1b00 */
/*0be0*/ IADD3 R24, P0, R10, UR5, RZ ; /* 0x000000050a187c10 */
/* 0x000fc6000ff1e0ff */
/*0bf0*/ LDG.E.64 R18, [R4.64+0x8] ; /* 0x0000080804127981 */
/* 0x000f22000c1e1b00 */
/*0c00*/ IADD3.X R25, R11, UR6, RZ, P0, !PT ; /* 0x000000060b197c10 */
/* 0x000fe400087fe4ff */
/*0c10*/ IADD3 R26, P0, R24, UR5, RZ ; /* 0x00000005181a7c10 */
/* 0x000fe2000ff1e0ff */
/*0c20*/ LDG.E.64 R12, [R4.64+0x10] ; /* 0x00001008040c7981 */
/* 0x001166000c1e1b00 */
/*0c30*/ IADD3.X R27, R25, UR6, RZ, P0, !PT ; /* 0x00000006191b7c10 */
/* 0x000fe200087fe4ff */
/*0c40*/ LDG.E.64 R14, [R24.64] ; /* 0x00000008180e7981 */
/* 0x000f22000c1e1b00 */
/*0c50*/ IADD3 R8, P0, R26, UR5, RZ ; /* 0x000000051a087c10 */
/* 0x000fc6000ff1e0ff */
/*0c60*/ LDG.E.64 R10, [R26.64] ; /* 0x000000081a0a7981 */
/* 0x008f62000c1e1b00 */
/*0c70*/ IADD3.X R9, R27, UR6, RZ, P0, !PT ; /* 0x000000061b097c10 */
/* 0x000fe400087fe4ff */
/*0c80*/ IADD3 R17, P0, R17, 0x4, RZ ; /* 0x0000000411117810 */
/* 0x000fe20007f1e0ff */
/*0c90*/ DFMA R22, R22, R20, R6 ; /* 0x000000141616722b */
/* 0x0063240000000006 */
/*0ca0*/ LDG.E.64 R20, [R4.64+0x18] ; /* 0x0000180804147981 */
/* 0x0020a8000c1e1b00 */
/*0cb0*/ LDG.E.64 R6, [R8.64] ; /* 0x0000000808067981 */
/* 0x000ea2000c1e1b00 */
/*0cc0*/ IMAD.X R16, RZ, RZ, R16, P0 ; /* 0x000000ffff107224 */
/* 0x000fe200000e0610 */
/*0cd0*/ ISETP.NE.U32.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fc80003f05070 */
/*0ce0*/ ISETP.NE.AND.EX P0, PT, R16, RZ, PT, P0 ; /* 0x000000ff1000720c */
/* 0x000fe20003f05300 */
/*0cf0*/ DFMA R14, R14, R18, R22 ; /* 0x000000120e0e722b */
/* 0x010f620000000016 */
/*0d00*/ IADD3 R4, P1, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fca0007f3e0ff */
/*0d10*/ DFMA R12, R10, R12, R14 ; /* 0x0000000c0a0c722b */
/* 0x0200a4000000000e */
/*0d20*/ IADD3 R10, P2, R8, UR5, RZ ; /* 0x00000005080a7c10 */
/* 0x001fe2000ff5e0ff */
/*0d30*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc6000fffe03f */
/*0d40*/ IADD3.X R11, R9, UR6, RZ, P2, !PT ; /* 0x00000006090b7c10 */
/* 0x000fe200097fe4ff */
/*0d50*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0d60*/ DFMA R6, R6, R20, R12 ; /* 0x000000140606722b */
/* 0x004064000000000c */
/*0d70*/ @P0 BRA 0xbc0 ; /* 0xfffffe4000000947 */
/* 0x003fea000383ffff */
/*0d80*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f05070 */
/*0d90*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0da0*/ @!P0 BRA 0xf70 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0db0*/ USHF.R.S32.HI UR10, URZ, 0x1f, UR4 ; /* 0x0000001f3f0a7899 */
/* 0x000fe20008011404 */
/*0dc0*/ IADD3 R0, P0, RZ, -R0, RZ ; /* 0x80000000ff007210 */
/* 0x000fe20007f1e0ff */
/*0dd0*/ IMAD.U32 R13, RZ, RZ, UR4 ; /* 0x00000004ff0d7e24 */
/* 0x001fe2000f8e00ff */
/*0de0*/ UMOV UR5, 0x8 ; /* 0x0000000800057882 */
/* 0x000fe40000000000 */
/*0df0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0e00*/ IMAD.U32 R14, RZ, RZ, UR10 ; /* 0x0000000aff0e7e24 */
/* 0x000fe2000f8e00ff */
/*0e10*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe2000f8e0206 */
/*0e20*/ IMAD.X R12, RZ, RZ, -0x1, P0 ; /* 0xffffffffff0c7424 */
/* 0x000fe400000e06ff */
/*0e30*/ IMAD R8, R14, c[0x0][0x178], RZ ; /* 0x00005e000e087a24 */
/* 0x001fe400078e02ff */
/*0e40*/ IMAD.WIDE.U32 R4, R13, c[0x0][0x178], R2 ; /* 0x00005e000d047a25 */
/* 0x000fc800078e0002 */
/*0e50*/ IMAD R9, R13, c[0x0][0x17c], R8 ; /* 0x00005f000d097a24 */
/* 0x000fe200078e0208 */
/*0e60*/ LEA R10, P0, R4, c[0x0][0x160], 0x3 ; /* 0x00005800040a7a11 */
/* 0x000fe200078018ff */
/*0e70*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe4000f8e00ff */
/*0e80*/ IMAD.IADD R5, R5, 0x1, R9 ; /* 0x0000000105057824 */
/* 0x000fe400078e0209 */
/*0e90*/ IMAD.U32 R9, RZ, RZ, UR7 ; /* 0x00000007ff097e24 */
/* 0x000fc6000f8e00ff */
/*0ea0*/ LEA.HI.X R11, R4, c[0x0][0x164], R5, 0x3, P0 ; /* 0x00005900040b7a11 */
/* 0x000fc600000f1c05 */
/*0eb0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000ea8000c1e1b00 */
/*0ec0*/ LDG.E.64 R4, [R10.64] ; /* 0x000000080a047981 */
/* 0x000ea2000c1e1b00 */
/*0ed0*/ IADD3 R0, P0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007f1e0ff */
/*0ee0*/ UIADD3 UR6, UP0, UR6, 0x8, URZ ; /* 0x0000000806067890 */
/* 0x000fe2000ff1e03f */
/*0ef0*/ IADD3 R13, P1, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fc60007f3e0ff */
/*0f00*/ IMAD.X R12, RZ, RZ, R12, P0 ; /* 0x000000ffff0c7224 */
/* 0x000fe200000e060c */
/*0f10*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05070 */
/*0f20*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0f30*/ IMAD.X R14, RZ, RZ, R14, P1 ; /* 0x000000ffff0e7224 */
/* 0x000fe400008e060e */
/*0f40*/ ISETP.NE.AND.EX P0, PT, R12, RZ, PT, P0 ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05300 */
/*0f50*/ DFMA R6, R4, R8, R6 ; /* 0x000000080406722b */
/* 0x0060580000000006 */
/*0f60*/ @P0 BRA 0xe30 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0f70*/ LEA R4, P0, R2, c[0x0][0x170], 0x3 ; /* 0x00005c0002047a11 */
/* 0x001fc800078018ff */
/*0f80*/ LEA.HI.X R5, R2, c[0x0][0x174], R3, 0x3, P0 ; /* 0x00005d0002057a11 */
/* 0x000fca00000f1c03 */
/*0f90*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x002fe2000c101b08 */
/*0fa0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fb0*/ BRA 0xfb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <cassert>
#include <iostream>
using namespace std;
const int Tile_size = 2;
// Compute C = A * B
//*************************************************************
//Kernel for shared memory/ Tiled execution
__global__ void matrixMul(double *A, double *X, double *B, long rows, long cols){
int tid= threadIdx.x + blockIdx.x * blockDim.x;
double sum= 0;
if(tid < rows){
for(int i=0; i < cols; i++){
sum += X[i] * A[(i * rows) + tid];
}
B[tid]=sum;
}
}
//*************************************************************
void Print_Mat(int Row,int Col,double * Mat){//Function To print the Matrix
for(int i=0; i < Row; ++i){
for(int j=0; j < Col; ++j){
cout << Mat[i * Row + j] << " ";
}
cout << endl;
}
}//Function close
//*************************************************************
//Normal CPU Matrix Multiplication
void matMultiplyOnHost(float * A, float * B, float * C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns){
for (int i=0; i < numARows; i ++){
for (int j= 0; j < numAColumns; j++){
C[i*numCColumns + j ] = 0.0;
for (int k = 0; k < numCColumns; k++){
C[i*numCColumns + j ] += A[i*numAColumns + k] * B [k*numBColumns + j];
}
}
}
}
//*************************************************************
extern "C++" void generate_b_gpu(double *hostA, double *hostX, double *hostB, long cols, long rows) {
double *deviceA;
double *deviceB;
double *deviceX;
// Allocating GPU memory
assert(cudaSuccess == cudaMalloc((void **)&deviceA, sizeof(double)*cols*rows));
assert(cudaSuccess == cudaMalloc((void **)&deviceB, sizeof(double)*rows));
assert(cudaSuccess == cudaMalloc((void **)&deviceX, sizeof(double)*rows));
// Copy memory to the GPU
assert(cudaSuccess == cudaMemcpy(deviceA, hostA, sizeof(double)*cols*rows, cudaMemcpyHostToDevice));
assert(cudaSuccess == cudaMemcpy(deviceX, hostX, sizeof(float)*rows, cudaMemcpyHostToDevice));
// Initialize the grid and block dimensions
dim3 dimGrid((1/Tile_size) + 1, (rows/Tile_size) + 1, 1);//Number of Blocks required
dim3 dimBlock(Tile_size, Tile_size, 1);//Number of threads in each block
//@@ Launch the GPU Kernel here
matrixMul<<<dimGrid, dimBlock>>>(deviceA, deviceX, deviceB, rows, cols);
cudaError_t err1 = cudaPeekAtLastError();//To capture last error in function call
cudaDeviceSynchronize();//To synchronize the device
// Copy the results in GPU memory back to the CPU
assert(cudaSuccess == cudaMemcpy(hostB, deviceB, sizeof(float)*rows, cudaMemcpyDeviceToHost));
cout << "GPU A" << endl;
Print_Mat(rows, cols, hostA);
//matMultiplyOnHost(hostA, hostB, hostComputedC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
//printf("\nMatrix C From Host\n");
//Print_Mat(numCRows,numCColumns,hostComputedC);//Function Call
//printf("\n Number of Blocks Created:%d \n",((1/Tile_size) + 1)*((1/Tile_size) + 1));
//printf("\n Number of Threads Per Block: %d \n",(Tile_size*Tile_size));
// Free the GPU memory
assert(cudaSuccess == cudaFree(deviceA));
assert(cudaSuccess == cudaFree(deviceB));
assert(cudaSuccess == cudaFree(deviceX));
//Free the Pointer Memory
//free(hostA);
//free(hostB);
//free(hostX);
} | .file "tmpxft_0012c2cb_00000000-6_gpu_mul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z9Print_MatiiPd
.type _Z9Print_MatiiPd, @function
_Z9Print_MatiiPd:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, 8(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 16(%rsp)
testl %edi, %edi
jle .L3
movl $0, %r15d
movl $0, %r14d
movslq %esi, %rax
movq %rax, 24(%rsp)
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r13
jmp .L5
.L14:
call _ZSt16__throw_bad_castv@PLT
.L8:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L9:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r14d
movl 8(%rsp), %eax
addl %eax, %r15d
cmpl %r14d, %eax
je .L3
.L5:
cmpl $0, 12(%rsp)
jle .L11
movslq %r15d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,8), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,8), %r12
.L6:
movsd (%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L6
.L11:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L14
cmpb $0, 56(%rbx)
je .L8
movzbl 67(%rbx), %esi
jmp .L9
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z9Print_MatiiPd, .-_Z9Print_MatiiPd
.globl _Z17matMultiplyOnHostPfS_S_iiiiii
.type _Z17matMultiplyOnHostPfS_S_iiiiii, @function
_Z17matMultiplyOnHostPfS_S_iiiiii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -8(%rsp)
movl %ecx, -12(%rsp)
movl 72(%rsp), %ebx
testl %ecx, %ecx
jle .L15
movq %rdi, %rbp
movq %rdx, %r15
movl %r8d, %r11d
movslq 56(%rsp), %rdi
salq $2, %rdi
movl $0, %r13d
movl $0, %ecx
movl $0, %edx
movslq %ebx, %r14
movq %r15, %r8
movq %r14, %rsi
jmp .L17
.L21:
movslq %ecx, %rax
leaq (%r8,%rax,4), %r10
movq -8(%rsp), %r14
movslq %r13d, %rax
leaq 0(%rbp,%rax,4), %r15
addq %rsi, %rax
leaq 0(%rbp,%rax,4), %r9
movl $0, %r12d
movl %edx, -20(%rsp)
movl %ecx, -16(%rsp)
.L20:
movq %r10, %rcx
movl $0x00000000, (%r10)
testl %ebx, %ebx
jle .L18
movq %r14, %rdx
movq %r15, %rax
.L19:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addq $4, %rax
addq %rdi, %rdx
cmpq %r9, %rax
jne .L19
.L18:
addl $1, %r12d
addq $4, %r10
addq $4, %r14
cmpl %r12d, %r11d
jne .L20
movl -20(%rsp), %edx
movl -16(%rsp), %ecx
.L22:
addl $1, %edx
addl %ebx, %ecx
addl %r11d, %r13d
cmpl %edx, -12(%rsp)
je .L15
.L17:
testl %r11d, %r11d
jg .L21
jmp .L22
.L15:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z17matMultiplyOnHostPfS_S_iiiiii, .-_Z17matMultiplyOnHostPfS_S_iiiiii
.globl _Z34__device_stub__Z9matrixMulPdS_S_llPdS_S_ll
.type _Z34__device_stub__Z9matrixMulPdS_S_llPdS_S_ll, @function
_Z34__device_stub__Z9matrixMulPdS_S_llPdS_S_ll:
.LFB3696:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9matrixMulPdS_S_ll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z34__device_stub__Z9matrixMulPdS_S_llPdS_S_ll, .-_Z34__device_stub__Z9matrixMulPdS_S_llPdS_S_ll
.globl _Z9matrixMulPdS_S_ll
.type _Z9matrixMulPdS_S_ll, @function
_Z9matrixMulPdS_S_ll:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9matrixMulPdS_S_llPdS_S_ll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z9matrixMulPdS_S_ll, .-_Z9matrixMulPdS_S_ll
.section .rodata.str1.1
.LC2:
.string "GPU A"
.text
.globl _Z14generate_b_gpuPdS_S_ll
.type _Z14generate_b_gpuPdS_S_ll, @function
_Z14generate_b_gpuPdS_S_ll:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rcx, %rbp
movq %r8, %rbx
movl $1, 8(%rsp)
movq %r8, %rax
shrq $63, %rax
addq %r8, %rax
sarq %rax
addl $1, %eax
movl %eax, 12(%rsp)
movl $1, 16(%rsp)
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L35:
call cudaPeekAtLastError@PLT
call cudaDeviceSynchronize@PLT
movl $5, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r13
testq %r13, %r13
je .L41
cmpb $0, 56(%r13)
je .L37
movzbl 67(%r13), %esi
.L38:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r12, %rdx
movl %ebp, %esi
movl %ebx, %edi
call _Z9Print_MatiiPd
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movq %rbp, %r8
movq %rbx, %rcx
movl $0, %edx
movl $0, %esi
movl $0, %edi
call _Z34__device_stub__Z9matrixMulPdS_S_llPdS_S_ll
jmp .L35
.L41:
call _ZSt16__throw_bad_castv@PLT
.L37:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L38
.cfi_endproc
.LFE3671:
.size _Z14generate_b_gpuPdS_S_ll, .-_Z14generate_b_gpuPdS_S_ll
.section .rodata.str1.1
.LC3:
.string "_Z9matrixMulPdS_S_ll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPdS_S_ll(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <cassert>
#include <iostream>
using namespace std;
const int Tile_size = 2;
// Compute C = A * B
//*************************************************************
//Kernel for shared memory/ Tiled execution
__global__ void matrixMul(double *A, double *X, double *B, long rows, long cols){
int tid= threadIdx.x + blockIdx.x * blockDim.x;
double sum= 0;
if(tid < rows){
for(int i=0; i < cols; i++){
sum += X[i] * A[(i * rows) + tid];
}
B[tid]=sum;
}
}
//*************************************************************
void Print_Mat(int Row,int Col,double * Mat){//Function To print the Matrix
for(int i=0; i < Row; ++i){
for(int j=0; j < Col; ++j){
cout << Mat[i * Row + j] << " ";
}
cout << endl;
}
}//Function close
//*************************************************************
//Normal CPU Matrix Multiplication
void matMultiplyOnHost(float * A, float * B, float * C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns){
for (int i=0; i < numARows; i ++){
for (int j= 0; j < numAColumns; j++){
C[i*numCColumns + j ] = 0.0;
for (int k = 0; k < numCColumns; k++){
C[i*numCColumns + j ] += A[i*numAColumns + k] * B [k*numBColumns + j];
}
}
}
}
//*************************************************************
extern "C++" void generate_b_gpu(double *hostA, double *hostX, double *hostB, long cols, long rows) {
double *deviceA;
double *deviceB;
double *deviceX;
// Allocating GPU memory
assert(cudaSuccess == cudaMalloc((void **)&deviceA, sizeof(double)*cols*rows));
assert(cudaSuccess == cudaMalloc((void **)&deviceB, sizeof(double)*rows));
assert(cudaSuccess == cudaMalloc((void **)&deviceX, sizeof(double)*rows));
// Copy memory to the GPU
assert(cudaSuccess == cudaMemcpy(deviceA, hostA, sizeof(double)*cols*rows, cudaMemcpyHostToDevice));
assert(cudaSuccess == cudaMemcpy(deviceX, hostX, sizeof(float)*rows, cudaMemcpyHostToDevice));
// Initialize the grid and block dimensions
dim3 dimGrid((1/Tile_size) + 1, (rows/Tile_size) + 1, 1);//Number of Blocks required
dim3 dimBlock(Tile_size, Tile_size, 1);//Number of threads in each block
//@@ Launch the GPU Kernel here
matrixMul<<<dimGrid, dimBlock>>>(deviceA, deviceX, deviceB, rows, cols);
cudaError_t err1 = cudaPeekAtLastError();//To capture last error in function call
cudaDeviceSynchronize();//To synchronize the device
// Copy the results in GPU memory back to the CPU
assert(cudaSuccess == cudaMemcpy(hostB, deviceB, sizeof(float)*rows, cudaMemcpyDeviceToHost));
cout << "GPU A" << endl;
Print_Mat(rows, cols, hostA);
//matMultiplyOnHost(hostA, hostB, hostComputedC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
//printf("\nMatrix C From Host\n");
//Print_Mat(numCRows,numCColumns,hostComputedC);//Function Call
//printf("\n Number of Blocks Created:%d \n",((1/Tile_size) + 1)*((1/Tile_size) + 1));
//printf("\n Number of Threads Per Block: %d \n",(Tile_size*Tile_size));
// Free the GPU memory
assert(cudaSuccess == cudaFree(deviceA));
assert(cudaSuccess == cudaFree(deviceB));
assert(cudaSuccess == cudaFree(deviceX));
//Free the Pointer Memory
//free(hostA);
//free(hostB);
//free(hostX);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <cassert>
#include <iostream>
using namespace std;
const int Tile_size = 2;
// Compute C = A * B
//*************************************************************
//Kernel for shared memory/ Tiled execution
__global__ void matrixMul(double *A, double *X, double *B, long rows, long cols){
int tid= threadIdx.x + blockIdx.x * blockDim.x;
double sum= 0;
if(tid < rows){
for(int i=0; i < cols; i++){
sum += X[i] * A[(i * rows) + tid];
}
B[tid]=sum;
}
}
//*************************************************************
void Print_Mat(int Row,int Col,double * Mat){//Function To print the Matrix
for(int i=0; i < Row; ++i){
for(int j=0; j < Col; ++j){
cout << Mat[i * Row + j] << " ";
}
cout << endl;
}
}//Function close
//*************************************************************
//Normal CPU Matrix Multiplication
void matMultiplyOnHost(float * A, float * B, float * C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns){
for (int i=0; i < numARows; i ++){
for (int j= 0; j < numAColumns; j++){
C[i*numCColumns + j ] = 0.0;
for (int k = 0; k < numCColumns; k++){
C[i*numCColumns + j ] += A[i*numAColumns + k] * B [k*numBColumns + j];
}
}
}
}
//*************************************************************
extern "C++" void generate_b_gpu(double *hostA, double *hostX, double *hostB, long cols, long rows) {
double *deviceA;
double *deviceB;
double *deviceX;
// Allocating GPU memory
assert(hipSuccess == hipMalloc((void **)&deviceA, sizeof(double)*cols*rows));
assert(hipSuccess == hipMalloc((void **)&deviceB, sizeof(double)*rows));
assert(hipSuccess == hipMalloc((void **)&deviceX, sizeof(double)*rows));
// Copy memory to the GPU
assert(hipSuccess == hipMemcpy(deviceA, hostA, sizeof(double)*cols*rows, hipMemcpyHostToDevice));
assert(hipSuccess == hipMemcpy(deviceX, hostX, sizeof(float)*rows, hipMemcpyHostToDevice));
// Initialize the grid and block dimensions
dim3 dimGrid((1/Tile_size) + 1, (rows/Tile_size) + 1, 1);//Number of Blocks required
dim3 dimBlock(Tile_size, Tile_size, 1);//Number of threads in each block
//@@ Launch the GPU Kernel here
matrixMul<<<dimGrid, dimBlock>>>(deviceA, deviceX, deviceB, rows, cols);
hipError_t err1 = hipPeekAtLastError();//To capture last error in function call
hipDeviceSynchronize();//To synchronize the device
// Copy the results in GPU memory back to the CPU
assert(hipSuccess == hipMemcpy(hostB, deviceB, sizeof(float)*rows, hipMemcpyDeviceToHost));
cout << "GPU A" << endl;
Print_Mat(rows, cols, hostA);
//matMultiplyOnHost(hostA, hostB, hostComputedC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
//printf("\nMatrix C From Host\n");
//Print_Mat(numCRows,numCColumns,hostComputedC);//Function Call
//printf("\n Number of Blocks Created:%d \n",((1/Tile_size) + 1)*((1/Tile_size) + 1));
//printf("\n Number of Threads Per Block: %d \n",(Tile_size*Tile_size));
// Free the GPU memory
assert(hipSuccess == hipFree(deviceA));
assert(hipSuccess == hipFree(deviceB));
assert(hipSuccess == hipFree(deviceX));
//Free the Pointer Memory
//free(hostA);
//free(hostB);
//free(hostX);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <cassert>
#include <iostream>
using namespace std;
const int Tile_size = 2;
// Compute C = A * B
//*************************************************************
//Kernel for shared memory/ Tiled execution
__global__ void matrixMul(double *A, double *X, double *B, long rows, long cols){
int tid= threadIdx.x + blockIdx.x * blockDim.x;
double sum= 0;
if(tid < rows){
for(int i=0; i < cols; i++){
sum += X[i] * A[(i * rows) + tid];
}
B[tid]=sum;
}
}
//*************************************************************
void Print_Mat(int Row,int Col,double * Mat){//Function To print the Matrix
for(int i=0; i < Row; ++i){
for(int j=0; j < Col; ++j){
cout << Mat[i * Row + j] << " ";
}
cout << endl;
}
}//Function close
//*************************************************************
//Normal CPU Matrix Multiplication
void matMultiplyOnHost(float * A, float * B, float * C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns){
for (int i=0; i < numARows; i ++){
for (int j= 0; j < numAColumns; j++){
C[i*numCColumns + j ] = 0.0;
for (int k = 0; k < numCColumns; k++){
C[i*numCColumns + j ] += A[i*numAColumns + k] * B [k*numBColumns + j];
}
}
}
}
//*************************************************************
extern "C++" void generate_b_gpu(double *hostA, double *hostX, double *hostB, long cols, long rows) {
double *deviceA;
double *deviceB;
double *deviceX;
// Allocating GPU memory
assert(hipSuccess == hipMalloc((void **)&deviceA, sizeof(double)*cols*rows));
assert(hipSuccess == hipMalloc((void **)&deviceB, sizeof(double)*rows));
assert(hipSuccess == hipMalloc((void **)&deviceX, sizeof(double)*rows));
// Copy memory to the GPU
assert(hipSuccess == hipMemcpy(deviceA, hostA, sizeof(double)*cols*rows, hipMemcpyHostToDevice));
assert(hipSuccess == hipMemcpy(deviceX, hostX, sizeof(float)*rows, hipMemcpyHostToDevice));
// Initialize the grid and block dimensions
dim3 dimGrid((1/Tile_size) + 1, (rows/Tile_size) + 1, 1);//Number of Blocks required
dim3 dimBlock(Tile_size, Tile_size, 1);//Number of threads in each block
//@@ Launch the GPU Kernel here
matrixMul<<<dimGrid, dimBlock>>>(deviceA, deviceX, deviceB, rows, cols);
hipError_t err1 = hipPeekAtLastError();//To capture last error in function call
hipDeviceSynchronize();//To synchronize the device
// Copy the results in GPU memory back to the CPU
assert(hipSuccess == hipMemcpy(hostB, deviceB, sizeof(float)*rows, hipMemcpyDeviceToHost));
cout << "GPU A" << endl;
Print_Mat(rows, cols, hostA);
//matMultiplyOnHost(hostA, hostB, hostComputedC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
//printf("\nMatrix C From Host\n");
//Print_Mat(numCRows,numCColumns,hostComputedC);//Function Call
//printf("\n Number of Blocks Created:%d \n",((1/Tile_size) + 1)*((1/Tile_size) + 1));
//printf("\n Number of Threads Per Block: %d \n",(Tile_size*Tile_size));
// Free the GPU memory
assert(hipSuccess == hipFree(deviceA));
assert(hipSuccess == hipFree(deviceB));
assert(hipSuccess == hipFree(deviceX));
//Free the Pointer Memory
//free(hostA);
//free(hostB);
//free(hostX);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPdS_S_ll
.globl _Z9matrixMulPdS_S_ll
.p2align 8
.type _Z9matrixMulPdS_S_ll,@function
_Z9matrixMulPdS_S_ll:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i64_e64 s[8:9], v[1:2]
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_cmp_lt_i64_e64 s4, s[2:3], 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_lshl_b64 s[4:5], s[8:9], 3
s_mov_b64 s[8:9], 0
.p2align 6
.LBB0_3:
global_load_b64 v[7:8], v[5:6], off
s_load_b64 s[10:11], s[6:7], 0x0
s_add_u32 s8, s8, 1
s_addc_u32 s9, s9, 0
v_add_co_u32 v5, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[3:4], s[10:11], v[7:8], v[3:4]
v_cmp_ge_i64_e64 s10, s[8:9], s[2:3]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s10
s_cbranch_vccz .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPdS_S_ll
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPdS_S_ll, .Lfunc_end0-_Z9matrixMulPdS_S_ll
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPdS_S_ll
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPdS_S_ll.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <cassert>
#include <iostream>
using namespace std;
const int Tile_size = 2;
// Compute C = A * B
//*************************************************************
//Kernel for shared memory/ Tiled execution
__global__ void matrixMul(double *A, double *X, double *B, long rows, long cols){
int tid= threadIdx.x + blockIdx.x * blockDim.x;
double sum= 0;
if(tid < rows){
for(int i=0; i < cols; i++){
sum += X[i] * A[(i * rows) + tid];
}
B[tid]=sum;
}
}
//*************************************************************
void Print_Mat(int Row,int Col,double * Mat){//Function To print the Matrix
for(int i=0; i < Row; ++i){
for(int j=0; j < Col; ++j){
cout << Mat[i * Row + j] << " ";
}
cout << endl;
}
}//Function close
//*************************************************************
//Normal CPU Matrix Multiplication
void matMultiplyOnHost(float * A, float * B, float * C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns){
for (int i=0; i < numARows; i ++){
for (int j= 0; j < numAColumns; j++){
C[i*numCColumns + j ] = 0.0;
for (int k = 0; k < numCColumns; k++){
C[i*numCColumns + j ] += A[i*numAColumns + k] * B [k*numBColumns + j];
}
}
}
}
//*************************************************************
extern "C++" void generate_b_gpu(double *hostA, double *hostX, double *hostB, long cols, long rows) {
double *deviceA;
double *deviceB;
double *deviceX;
// Allocating GPU memory
assert(hipSuccess == hipMalloc((void **)&deviceA, sizeof(double)*cols*rows));
assert(hipSuccess == hipMalloc((void **)&deviceB, sizeof(double)*rows));
assert(hipSuccess == hipMalloc((void **)&deviceX, sizeof(double)*rows));
// Copy memory to the GPU
assert(hipSuccess == hipMemcpy(deviceA, hostA, sizeof(double)*cols*rows, hipMemcpyHostToDevice));
assert(hipSuccess == hipMemcpy(deviceX, hostX, sizeof(float)*rows, hipMemcpyHostToDevice));
// Initialize the grid and block dimensions
dim3 dimGrid((1/Tile_size) + 1, (rows/Tile_size) + 1, 1);//Number of Blocks required
dim3 dimBlock(Tile_size, Tile_size, 1);//Number of threads in each block
//@@ Launch the GPU Kernel here
matrixMul<<<dimGrid, dimBlock>>>(deviceA, deviceX, deviceB, rows, cols);
hipError_t err1 = hipPeekAtLastError();//To capture last error in function call
hipDeviceSynchronize();//To synchronize the device
// Copy the results in GPU memory back to the CPU
assert(hipSuccess == hipMemcpy(hostB, deviceB, sizeof(float)*rows, hipMemcpyDeviceToHost));
cout << "GPU A" << endl;
Print_Mat(rows, cols, hostA);
//matMultiplyOnHost(hostA, hostB, hostComputedC, numARows, numAColumns, numBRows, numBColumns, numCRows, numCColumns);
//printf("\nMatrix C From Host\n");
//Print_Mat(numCRows,numCColumns,hostComputedC);//Function Call
//printf("\n Number of Blocks Created:%d \n",((1/Tile_size) + 1)*((1/Tile_size) + 1));
//printf("\n Number of Threads Per Block: %d \n",(Tile_size*Tile_size));
// Free the GPU memory
assert(hipSuccess == hipFree(deviceA));
assert(hipSuccess == hipFree(deviceB));
assert(hipSuccess == hipFree(deviceX));
//Free the Pointer Memory
//free(hostA);
//free(hostB);
//free(hostX);
} | .text
.file "gpu_mul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__matrixMulPdS_S_ll # -- Begin function _Z24__device_stub__matrixMulPdS_S_ll
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPdS_S_ll,@function
_Z24__device_stub__matrixMulPdS_S_ll: # @_Z24__device_stub__matrixMulPdS_S_ll
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9matrixMulPdS_S_ll, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixMulPdS_S_ll, .Lfunc_end0-_Z24__device_stub__matrixMulPdS_S_ll
.cfi_endproc
# -- End function
.globl _Z9Print_MatiiPd # -- Begin function _Z9Print_MatiiPd
.p2align 4, 0x90
.type _Z9Print_MatiiPd,@function
_Z9Print_MatiiPd: # @_Z9Print_MatiiPd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 8(%rsp) # 8-byte Spill
movl %esi, 4(%rsp) # 4-byte Spill
testl %edi, %edi
jle .LBB1_10
# %bb.1: # %.preheader.lr.ph
movl %edi, %r14d
movl %edi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 4(%rsp), %r13d # 4-byte Reload
xorl %ebx, %ebx
xorl %r12d, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_2 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addl %r14d, %ebx
cmpq 16(%rsp), %r12 # 8-byte Folded Reload
je .LBB1_10
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %ebx, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r15
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%rbp,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbp
cmpq %rbp, %r13
jne .LBB1_4
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r15)
je .LBB1_8
# %bb.7: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r15), %eax
jmp .LBB1_9
.LBB1_10: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z9Print_MatiiPd, .Lfunc_end1-_Z9Print_MatiiPd
.cfi_endproc
# -- End function
.globl _Z17matMultiplyOnHostPfS_S_iiiiii # -- Begin function _Z17matMultiplyOnHostPfS_S_iiiiii
.p2align 4, 0x90
.type _Z17matMultiplyOnHostPfS_S_iiiiii,@function
_Z17matMultiplyOnHostPfS_S_iiiiii: # @_Z17matMultiplyOnHostPfS_S_iiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB2_9
# %bb.1: # %.preheader.lr.ph
movl 72(%rsp), %eax
movslq 56(%rsp), %r9
movslq %eax, %r10
movslq %r8d, %r11
movl %ecx, %ecx
movl %r11d, %ebx
movl %r10d, %r14d
shlq $2, %r11
shlq $2, %r9
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_8: # %._crit_edge30
# in Loop: Header=BB2_2 Depth=1
incq %r15
addq %r11, %rdi
cmpq %rcx, %r15
je .LBB2_9
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_6 Depth 3
testl %r8d, %r8d
jle .LBB2_8
# %bb.3: # %.lr.ph29
# in Loop: Header=BB2_2 Depth=1
movq %r15, %rdx
imulq %r10, %rdx
movq -8(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %r12
movq -16(%rsp), %rsi # 8-byte Reload
xorl %ebp, %ebp
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
incq %rbp
addq $4, %rsi
cmpq %rbx, %rbp
je .LBB2_8
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_6 Depth 3
movl $0, (%r12,%rbp,4)
testl %eax, %eax
jle .LBB2_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB2_4 Depth=2
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rsi, %r13
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r13), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r12,%rbp,4)
incq %rdx
addq %r9, %r13
cmpq %rdx, %r14
jne .LBB2_6
jmp .LBB2_7
.LBB2_9: # %._crit_edge32
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z17matMultiplyOnHostPfS_S_iiiiii, .Lfunc_end2-_Z17matMultiplyOnHostPfS_S_iiiiii
.cfi_endproc
# -- End function
.globl _Z14generate_b_gpuPdS_S_ll # -- Begin function _Z14generate_b_gpuPdS_S_ll
.p2align 4, 0x90
.type _Z14generate_b_gpuPdS_S_ll,@function
_Z14generate_b_gpuPdS_S_ll: # @_Z14generate_b_gpuPdS_S_ll
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r8, %r15
movq %rcx, %r14
movq %rdi, %rbx
movq %r8, %rax
shrq $63, %rax
addq %r8, %rax
andq $-2, %rax
shlq $31, %rax
movabsq $4294967297, %rdi # imm = 0x100000001
addq %rax, %rdi
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %r15, 56(%rsp)
movq %r14, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 120(%rsp), %rax
movq %rax, 72(%rsp)
leaq 112(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9matrixMulPdS_S_ll, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipPeekAtLastError
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB3_5
# %bb.4:
movzbl 67(%r12), %eax
jmp .LBB3_6
.LBB3_5:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl %r15d, %edi
movl %r14d, %esi
movq %rbx, %rdx
callq _Z9Print_MatiiPd
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_7:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z14generate_b_gpuPdS_S_ll, .Lfunc_end3-_Z14generate_b_gpuPdS_S_ll
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPdS_S_ll, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixMulPdS_S_ll,@object # @_Z9matrixMulPdS_S_ll
.section .rodata,"a",@progbits
.globl _Z9matrixMulPdS_S_ll
.p2align 3, 0x0
_Z9matrixMulPdS_S_ll:
.quad _Z24__device_stub__matrixMulPdS_S_ll
.size _Z9matrixMulPdS_S_ll, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU A"
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixMulPdS_S_ll"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPdS_S_ll
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPdS_S_ll
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixMulPdS_S_ll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011402 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x17c], PT, P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff007624 */
/* 0x000fe200078e00ff */
/*00b0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe4000001ff00 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc80003f06070 */
/*00d0*/ ISETP.GE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0003f06300 */
/*00e0*/ @!P0 BRA 0xf70 ; /* 0x00000e8000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R5, P1, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fe20007f3e0ff */
/*0100*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0110*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe4000001ff00 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*0130*/ IADD3.X R0, R0, -0x1, RZ, P1, !PT ; /* 0xffffffff00007810 */
/* 0x000fc80000ffe4ff */
/*0140*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe40003f06100 */
/*0150*/ LOP3.LUT R0, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304007812 */
/* 0x000fd600078ec0ff */
/*0160*/ @!P0 BRA 0xd80 ; /* 0x00000c1000008947 */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R17, P0, R0, -c[0x0][0x180], RZ ; /* 0x8000600000117a10 */
/* 0x000fe20007f1e0ff */
/*0180*/ UMOV UR6, 0x3 ; /* 0x0000000300067882 */
/* 0x000fe20000000000 */
/*0190*/ LEA R10, P1, R2, c[0x0][0x160], 0x3 ; /* 0x00005800020a7a11 */
/* 0x000fe200078218ff */
/*01a0*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*01c0*/ IMAD.X R16, RZ, RZ, ~c[0x0][0x184], P0 ; /* 0x80006100ff107624 */
/* 0x000fe200000e06ff */
/*01d0*/ USHF.L.U64.HI UR6, UR4, UR6, UR5 ; /* 0x0000000604067299 */
/* 0x000fe20008010205 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*01f0*/ USHF.L.U32 UR5, UR4, 0x3, URZ ; /* 0x0000000304057899 */
/* 0x000fe2000800063f */
/*0200*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0210*/ ISETP.GE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f06270 */
/*0220*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0230*/ LEA.HI.X R11, R2, c[0x0][0x164], R3, 0x3, P1 ; /* 0x00005900020b7a11 */
/* 0x000fd600008f1c03 */
/*0240*/ @P0 BRA 0xbc0 ; /* 0x0000097000000947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R8, P0, RZ, -R17, RZ ; /* 0x80000011ff087210 */
/* 0x000fc80007f1e0ff */
/*0260*/ ISETP.GT.U32.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24070 */
/*0270*/ IMAD.X R8, RZ, RZ, ~R16, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0e10 */
/*0280*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0f070 */
/*0290*/ ISETP.GT.AND.EX P1, PT, R8, RZ, PT, P1 ; /* 0x000000ff0800720c */
/* 0x000fda0003f24310 */
/*02a0*/ @!P1 BRA 0x840 ; /* 0x0000059000009947 */
/* 0x000fea0003800000 */
/*02b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02c0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000804087981 */
/* 0x001ea8000c1e1b00 */
/*02d0*/ LDG.E.64 R20, [R10.64] ; /* 0x000000080a147981 */
/* 0x0000a2000c1e1b00 */
/*02e0*/ IADD3 R28, P1, R10, UR5, RZ ; /* 0x000000050a1c7c10 */
/* 0x000fc6000ff3e0ff */
/*02f0*/ LDG.E.64 R14, [R4.64+0x8] ; /* 0x00000808040e7981 */
/* 0x000ee2000c1e1b00 */
/*0300*/ IADD3.X R29, R11, UR6, RZ, P1, !PT ; /* 0x000000060b1d7c10 */
/* 0x000fe40008ffe4ff */
/*0310*/ IADD3 R26, P1, R28, UR5, RZ ; /* 0x000000051c1a7c10 */
/* 0x000fc6000ff3e0ff */
/*0320*/ LDG.E.64 R18, [R28.64] ; /* 0x000000081c127981 */
/* 0x000ee2000c1e1b00 */
/*0330*/ IADD3.X R27, R29, UR6, RZ, P1, !PT ; /* 0x000000061d1b7c10 */
/* 0x000fe40008ffe4ff */
/*0340*/ IADD3 R24, P1, R26, UR5, RZ ; /* 0x000000051a187c10 */
/* 0x000fe2000ff3e0ff */
/*0350*/ LDG.E.64 R10, [R4.64+0x10] ; /* 0x00001008040a7981 */
/* 0x001f28000c1e1b00 */
/*0360*/ LDG.E.64 R12, [R26.64] ; /* 0x000000081a0c7981 */
/* 0x000f22000c1e1b00 */
/*0370*/ IADD3.X R25, R27, UR6, RZ, P1, !PT ; /* 0x000000061b197c10 */
/* 0x000fe20008ffe4ff */
/*0380*/ DFMA R22, R20, R8, R6 ; /* 0x000000081416722b */
/* 0x0060c40000000006 */
/*0390*/ LDG.E.64 R6, [R4.64+0x18] ; /* 0x0000180804067981 */
/* 0x001ea8000c1e1b00 */
/*03a0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000818087981 */
/* 0x000ea2000c1e1b00 */
/*03b0*/ IADD3 R20, P1, R24, UR5, RZ ; /* 0x0000000518147c10 */
/* 0x000fc8000ff3e0ff */
/*03c0*/ IADD3.X R21, R25, UR6, RZ, P1, !PT ; /* 0x0000000619157c10 */
/* 0x000fe20008ffe4ff */
/*03d0*/ DFMA R28, R18, R14, R22 ; /* 0x0000000e121c722b */
/* 0x0081240000000016 */
/*03e0*/ IADD3 R22, P1, R20, UR5, RZ ; /* 0x0000000514167c10 */
/* 0x001fe2000ff3e0ff */
/*03f0*/ LDG.E.64 R14, [R4.64+0x20] ; /* 0x00002008040e7981 */
/* 0x000ee8000c1e1b00 */
/*0400*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000814127981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IADD3.X R23, R21, UR6, RZ, P1, !PT ; /* 0x0000000615177c10 */
/* 0x000fe20008ffe4ff */
/*0420*/ DFMA R26, R12, R10, R28 ; /* 0x0000000a0c1a722b */
/* 0x010084000000001c */
/*0430*/ IADD3 R28, P1, R22, UR5, RZ ; /* 0x00000005161c7c10 */
/* 0x001fe2000ff3e0ff */
/*0440*/ LDG.E.64 R10, [R4.64+0x28] ; /* 0x00002808040a7981 */
/* 0x000f26000c1e1b00 */
/*0450*/ IADD3.X R29, R23, UR6, RZ, P1, !PT ; /* 0x00000006171d7c10 */
/* 0x000fe20008ffe4ff */
/*0460*/ LDG.E.64 R12, [R22.64] ; /* 0x00000008160c7981 */
/* 0x000122000c1e1b00 */
/*0470*/ DFMA R26, R8, R6, R26 ; /* 0x00000006081a722b */
/* 0x0042c6000000001a */
/*0480*/ LDG.E.64 R6, [R4.64+0x30] ; /* 0x0000300804067981 */
/* 0x002ea8000c1e1b00 */
/*0490*/ LDG.E.64 R8, [R28.64] ; /* 0x000000081c087981 */
/* 0x000ea2000c1e1b00 */
/*04a0*/ IADD3 R24, P1, R28, UR5, RZ ; /* 0x000000051c187c10 */
/* 0x000fc8000ff3e0ff */
/*04b0*/ IADD3.X R25, R29, UR6, RZ, P1, !PT ; /* 0x000000061d197c10 */
/* 0x000fe20008ffe4ff */
/*04c0*/ DFMA R14, R18, R14, R26 ; /* 0x0000000e120e722b */
/* 0x008324000000001a */
/*04d0*/ IADD3 R26, P1, R24, UR5, RZ ; /* 0x00000005181a7c10 */
/* 0x002fe2000ff3e0ff */
/*04e0*/ LDG.E.64 R18, [R4.64+0x38] ; /* 0x0000380804127981 */
/* 0x000ee8000c1e1b00 */
/*04f0*/ LDG.E.64 R20, [R24.64] ; /* 0x0000000818147981 */
/* 0x0002e2000c1e1b00 */
/*0500*/ IADD3.X R27, R25, UR6, RZ, P1, !PT ; /* 0x00000006191b7c10 */
/* 0x000fe40008ffe4ff */
/*0510*/ IADD3 R22, P1, R26, UR5, RZ ; /* 0x000000051a167c10 */
/* 0x001fe2000ff3e0ff */
/*0520*/ DFMA R14, R12, R10, R14 ; /* 0x0000000a0c0e722b */
/* 0x010084000000000e */
/*0530*/ LDG.E.64 R12, [R4.64+0x40] ; /* 0x00004008040c7981 */
/* 0x001f22000c1e1b00 */
/*0540*/ IADD3.X R23, R27, UR6, RZ, P1, !PT ; /* 0x000000061b177c10 */
/* 0x000fc60008ffe4ff */
/*0550*/ LDG.E.64 R10, [R26.64] ; /* 0x000000081a0a7981 */
/* 0x000122000c1e1b00 */
/*0560*/ DFMA R28, R8, R6, R14 ; /* 0x00000006081c722b */
/* 0x0044c6000000000e */
/*0570*/ LDG.E.64 R8, [R4.64+0x48] ; /* 0x0000480804087981 */
/* 0x004ea8000c1e1b00 */
/*0580*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000816067981 */
/* 0x000aa2000c1e1b00 */
/*0590*/ IADD3 R14, P1, R22, UR5, RZ ; /* 0x00000005160e7c10 */
/* 0x000fc8000ff3e0ff */
/*05a0*/ IADD3.X R15, R23, UR6, RZ, P1, !PT ; /* 0x00000006170f7c10 */
/* 0x000fe40008ffe4ff */
/*05b0*/ IADD3 R24, P1, R14, UR5, RZ ; /* 0x000000050e187c10 */
/* 0x002fe2000ff3e0ff */
/*05c0*/ DFMA R28, R20, R18, R28 ; /* 0x00000012141c722b */
/* 0x008324000000001c */
/*05d0*/ LDG.E.64 R20, [R4.64+0x50] ; /* 0x0000500804147981 */
/* 0x002ee8000c1e1b00 */
/*05e0*/ LDG.E.64 R18, [R14.64] ; /* 0x000000080e127981 */
/* 0x0002e2000c1e1b00 */
/*05f0*/ IADD3.X R25, R15, UR6, RZ, P1, !PT ; /* 0x000000060f197c10 */
/* 0x000fc40008ffe4ff */
/*0600*/ IADD3 R26, P1, R24, UR5, RZ ; /* 0x00000005181a7c10 */
/* 0x001fe2000ff3e0ff */
/*0610*/ DFMA R28, R10, R12, R28 ; /* 0x0000000c0a1c722b */
/* 0x0100a4000000001c */
/*0620*/ LDG.E.64 R10, [R4.64+0x58] ; /* 0x00005808040a7981 */
/* 0x001f22000c1e1b00 */
/*0630*/ IADD3.X R27, R25, UR6, RZ, P1, !PT ; /* 0x00000006191b7c10 */
/* 0x000fc60008ffe4ff */
/*0640*/ LDG.E.64 R12, [R24.64] ; /* 0x00000008180c7981 */
/* 0x000f28000c1e1b00 */
/*0650*/ LDG.E.64 R22, [R26.64] ; /* 0x000000081a167981 */
/* 0x020f62000c1e1b00 */
/*0660*/ DFMA R8, R6, R8, R28 ; /* 0x000000080608722b */
/* 0x0040c6000000001c */
/*0670*/ LDG.E.64 R6, [R4.64+0x60] ; /* 0x0000600804067981 */
/* 0x001f62000c1e1b00 */
/*0680*/ IADD3 R28, P1, R26, UR5, RZ ; /* 0x000000051a1c7c10 */
/* 0x000fc8000ff3e0ff */
/*0690*/ IADD3.X R29, R27, UR6, RZ, P1, !PT ; /* 0x000000061b1d7c10 */
/* 0x000fe40008ffe4ff */
/*06a0*/ IADD3 R14, P1, R28, UR5, RZ ; /* 0x000000051c0e7c10 */
/* 0x002fe2000ff3e0ff */
/*06b0*/ DFMA R8, R18, R20, R8 ; /* 0x000000141208722b */
/* 0x0081060000000008 */
/*06c0*/ IADD3.X R15, R29, UR6, RZ, P1, !PT ; /* 0x000000061d0f7c10 */
/* 0x000fe20008ffe4ff */
/*06d0*/ LDG.E.64 R18, [R4.64+0x68] ; /* 0x0000680804127981 */
/* 0x001ea2000c1e1b00 */
/*06e0*/ IADD3 R20, P1, R14, UR5, RZ ; /* 0x000000050e147c10 */
/* 0x000fc6000ff3e0ff */
/*06f0*/ LDG.E.64 R28, [R28.64] ; /* 0x000000081c1c7981 */
/* 0x000ea2000c1e1b00 */
/*0700*/ IADD3.X R21, R15, UR6, RZ, P1, !PT ; /* 0x000000060f157c10 */
/* 0x000fe20008ffe4ff */
/*0710*/ DFMA R10, R12, R10, R8 ; /* 0x0000000a0c0a722b */
/* 0x0101640000000008 */
/*0720*/ LDG.E.64 R14, [R14.64] ; /* 0x000000080e0e7981 */
/* 0x000ee8000c1e1b00 */
/*0730*/ LDG.E.64 R8, [R4.64+0x70] ; /* 0x0000700804087981 */
/* 0x0010e8000c1e1b00 */
/*0740*/ LDG.E.64 R12, [R4.64+0x78] ; /* 0x00007808040c7981 */
/* 0x000122000c1e1b00 */
/*0750*/ DFMA R10, R22, R6, R10 ; /* 0x00000006160a722b */
/* 0x020286000000000a */
/*0760*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000814067981 */
/* 0x002f22000c1e1b00 */
/*0770*/ IADD3 R17, P1, R17, 0x10, RZ ; /* 0x0000001011117810 */
/* 0x000fca0007f3e0ff */
/*0780*/ IMAD.X R16, RZ, RZ, R16, P1 ; /* 0x000000ffff107224 */
/* 0x000fe200008e0610 */
/*0790*/ ISETP.GE.U32.AND P1, PT, R17, -0xc, PT ; /* 0xfffffff41100780c */
/* 0x000fc80003f26070 */
/*07a0*/ ISETP.GE.AND.EX P1, PT, R16, -0x1, PT, P1 ; /* 0xffffffff1000780c */
/* 0x000fe20003f26310 */
/*07b0*/ DFMA R10, R28, R18, R10 ; /* 0x000000121c0a722b */
/* 0x004ee2000000000a */
/*07c0*/ IADD3 R4, P2, R4, 0x80, RZ ; /* 0x0000008004047810 */
/* 0x001fe20007f5e0ff */
/*07d0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc8000fffe03f */
/*07e0*/ DFMA R8, R14, R8, R10 ; /* 0x000000080e08722b */
/* 0x008124000000000a */
/*07f0*/ IADD3 R10, P3, R20, UR5, RZ ; /* 0x00000005140a7c10 */
/* 0x001fe2000ff7e0ff */
/*0800*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fc600010e0605 */
/*0810*/ IADD3.X R11, R21, UR6, RZ, P3, !PT ; /* 0x00000006150b7c10 */
/* 0x000fe20009ffe4ff */
/*0820*/ DFMA R6, R6, R12, R8 ; /* 0x0000000c0606722b */
/* 0x0100620000000008 */
/*0830*/ @!P1 BRA 0x2c0 ; /* 0xfffffa8000009947 */
/* 0x000fea000383ffff */
/*0840*/ IADD3 R8, P2, RZ, -R17, RZ ; /* 0x80000011ff087210 */
/* 0x001fc80007f5e0ff */
/*0850*/ ISETP.GT.U32.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fe20003f24070 */
/*0860*/ IMAD.X R8, RZ, RZ, ~R16, P2 ; /* 0x000000ffff087224 */
/* 0x000fca00010e0e10 */
/*0870*/ ISETP.GT.AND.EX P1, PT, R8, RZ, PT, P1 ; /* 0x000000ff0800720c */
/* 0x000fda0003f24310 */
/*0880*/ @!P1 BRA 0xb90 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*0890*/ IADD3 R18, P0, R10, UR5, RZ ; /* 0x000000050a127c10 */
/* 0x000fe2000ff1e0ff */
/*08a0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000804087981 */
/* 0x000ea8000c1e1b00 */
/*08b0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000080a0c7981 */
/* 0x0000a2000c1e1b00 */
/*08c0*/ IADD3.X R19, R11, UR6, RZ, P0, !PT ; /* 0x000000060b137c10 */
/* 0x000fc600087fe4ff */
/*08d0*/ LDG.E.64 R24, [R4.64+0x8] ; /* 0x0000080804187981 */
/* 0x000ee8000c1e1b00 */
/*08e0*/ LDG.E.64 R22, [R4.64+0x10] ; /* 0x0000100804167981 */
/* 0x000f28000c1e1b00 */
/*08f0*/ LDG.E.64 R10, [R18.64] ; /* 0x00000008120a7981 */
/* 0x001ee2000c1e1b00 */
/*0900*/ IADD3 R20, P0, R18, UR5, RZ ; /* 0x0000000512147c10 */
/* 0x000fc8000ff1e0ff */
/*0910*/ IADD3.X R21, R19, UR6, RZ, P0, !PT ; /* 0x0000000613157c10 */
/* 0x000fe400087fe4ff */
/*0920*/ IADD3 R28, P0, R20, UR5, RZ ; /* 0x00000005141c7c10 */
/* 0x000fc8000ff1e0ff */
/*0930*/ IADD3.X R29, R21, UR6, RZ, P0, !PT ; /* 0x00000006151d7c10 */
/* 0x000fe400087fe4ff */
/*0940*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000814147981 */
/* 0x000f22000c1e1b00 */
/*0950*/ IADD3 R26, P0, R28, UR5, RZ ; /* 0x000000051c1a7c10 */
/* 0x000fc6000ff1e0ff */
/*0960*/ LDG.E.64 R14, [R28.64] ; /* 0x000000081c0e7981 */
/* 0x000f62000c1e1b00 */
/*0970*/ IADD3.X R27, R29, UR6, RZ, P0, !PT ; /* 0x000000061d1b7c10 */
/* 0x000fe200087fe4ff */
/*0980*/ DFMA R12, R12, R8, R6 ; /* 0x000000080c0c722b */
/* 0x0060e40000000006 */
/*0990*/ LDG.E.64 R8, [R4.64+0x18] ; /* 0x0000180804087981 */
/* 0x001f68000c1e1b00 */
/*09a0*/ DFMA R24, R10, R24, R12 ; /* 0x000000180a18722b */
/* 0x008124000000000c */
/*09b0*/ LDG.E.64 R10, [R4.64+0x20] ; /* 0x00002008040a7981 */
/* 0x001ea8000c1e1b00 */
/*09c0*/ LDG.E.64 R12, [R26.64] ; /* 0x000000081a0c7981 */
/* 0x000ea2000c1e1b00 */
/*09d0*/ IADD3 R18, P0, R26, UR5, RZ ; /* 0x000000051a127c10 */
/* 0x000fc8000ff1e0ff */
/*09e0*/ IADD3.X R19, R27, UR6, RZ, P0, !PT ; /* 0x000000061b137c10 */
/* 0x000fe400087fe4ff */
/*09f0*/ IADD3 R6, P0, R18, UR5, RZ ; /* 0x0000000512067c10 */
/* 0x000fe2000ff1e0ff */
/*0a00*/ DFMA R20, R20, R22, R24 ; /* 0x000000161414722b */
/* 0x0101640000000018 */
/*0a10*/ LDG.E.64 R22, [R4.64+0x28] ; /* 0x0000280804167981 */
/* 0x001ee2000c1e1b00 */
/*0a20*/ IADD3.X R7, R19, UR6, RZ, P0, !PT ; /* 0x0000000613077c10 */
/* 0x000fe400087fe4ff */
/*0a30*/ IADD3 R24, P0, R6, UR5, RZ ; /* 0x0000000506187c10 */
/* 0x000fe2000ff1e0ff */
/*0a40*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000812127981 */
/* 0x000ee6000c1e1b00 */
/*0a50*/ IADD3.X R25, R7, UR6, RZ, P0, !PT ; /* 0x0000000607197c10 */
/* 0x000fc400087fe4ff */
/*0a60*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000f22000c1e1b00 */
/*0a70*/ DFMA R14, R14, R8, R20 ; /* 0x000000080e0e722b */
/* 0x0200860000000014 */
/*0a80*/ LDG.E.64 R8, [R4.64+0x30] ; /* 0x0000300804087981 */
/* 0x001126000c1e1b00 */
/*0a90*/ DFMA R10, R12, R10, R14 ; /* 0x0000000a0c0a722b */
/* 0x0042c8000000000e */
/*0aa0*/ LDG.E.64 R14, [R4.64+0x38] ; /* 0x00003808040e7981 */
/* 0x0020a8000c1e1b00 */
/*0ab0*/ LDG.E.64 R12, [R24.64] ; /* 0x00000008180c7981 */
/* 0x000ea2000c1e1b00 */
/*0ac0*/ DFMA R10, R18, R22, R10 ; /* 0x00000016120a722b */
/* 0x008324000000000a */
/*0ad0*/ IADD3 R18, P2, R4, 0x40, RZ ; /* 0x0000004004127810 */
/* 0x002fe40007f5e0ff */
/*0ae0*/ IADD3 R17, P3, R17, 0x8, RZ ; /* 0x0000000811117810 */
/* 0x000fc60007f7e0ff */
/*0af0*/ IMAD.X R19, RZ, RZ, R5, P2 ; /* 0x000000ffff137224 */
/* 0x000fe200010e0605 */
/*0b00*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0b10*/ IMAD.X R16, RZ, RZ, R16, P3 ; /* 0x000000ffff107224 */
/* 0x000fe400018e0610 */
/*0b20*/ IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0012 */
/*0b30*/ IMAD.MOV.U32 R5, RZ, RZ, R19 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0013 */
/*0b40*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0b50*/ DFMA R8, R6, R8, R10 ; /* 0x000000080608722b */
/* 0x0100a4000000000a */
/*0b60*/ IADD3 R10, P1, R24, UR5, RZ ; /* 0x00000005180a7c10 */
/* 0x001fc8000ff3e0ff */
/*0b70*/ IADD3.X R11, R25, UR6, RZ, P1, !PT ; /* 0x00000006190b7c10 */
/* 0x000fe20008ffe4ff */
/*0b80*/ DFMA R6, R12, R14, R8 ; /* 0x0000000e0c06722b */
/* 0x0040480000000008 */
/*0b90*/ ISETP.NE.U32.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fc80003f25070 */
/*0ba0*/ ISETP.NE.OR.EX P0, PT, R16, RZ, P0, P1 ; /* 0x000000ff1000720c */
/* 0x000fda0000705710 */
/*0bb0*/ @!P0 BRA 0xd80 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ LDG.E.64 R20, [R4.64] ; /* 0x0000000804147981 */
/* 0x000ea8000c1e1b00 */
/*0bd0*/ LDG.E.64 R22, [R10.64] ; /* 0x000000080a167981 */
/* 0x0006a2000c1e1b00 */
/*0be0*/ IADD3 R24, P0, R10, UR5, RZ ; /* 0x000000050a187c10 */
/* 0x000fc6000ff1e0ff */
/*0bf0*/ LDG.E.64 R18, [R4.64+0x8] ; /* 0x0000080804127981 */
/* 0x000f22000c1e1b00 */
/*0c00*/ IADD3.X R25, R11, UR6, RZ, P0, !PT ; /* 0x000000060b197c10 */
/* 0x000fe400087fe4ff */
/*0c10*/ IADD3 R26, P0, R24, UR5, RZ ; /* 0x00000005181a7c10 */
/* 0x000fe2000ff1e0ff */
/*0c20*/ LDG.E.64 R12, [R4.64+0x10] ; /* 0x00001008040c7981 */
/* 0x001166000c1e1b00 */
/*0c30*/ IADD3.X R27, R25, UR6, RZ, P0, !PT ; /* 0x00000006191b7c10 */
/* 0x000fe200087fe4ff */
/*0c40*/ LDG.E.64 R14, [R24.64] ; /* 0x00000008180e7981 */
/* 0x000f22000c1e1b00 */
/*0c50*/ IADD3 R8, P0, R26, UR5, RZ ; /* 0x000000051a087c10 */
/* 0x000fc6000ff1e0ff */
/*0c60*/ LDG.E.64 R10, [R26.64] ; /* 0x000000081a0a7981 */
/* 0x008f62000c1e1b00 */
/*0c70*/ IADD3.X R9, R27, UR6, RZ, P0, !PT ; /* 0x000000061b097c10 */
/* 0x000fe400087fe4ff */
/*0c80*/ IADD3 R17, P0, R17, 0x4, RZ ; /* 0x0000000411117810 */
/* 0x000fe20007f1e0ff */
/*0c90*/ DFMA R22, R22, R20, R6 ; /* 0x000000141616722b */
/* 0x0063240000000006 */
/*0ca0*/ LDG.E.64 R20, [R4.64+0x18] ; /* 0x0000180804147981 */
/* 0x0020a8000c1e1b00 */
/*0cb0*/ LDG.E.64 R6, [R8.64] ; /* 0x0000000808067981 */
/* 0x000ea2000c1e1b00 */
/*0cc0*/ IMAD.X R16, RZ, RZ, R16, P0 ; /* 0x000000ffff107224 */
/* 0x000fe200000e0610 */
/*0cd0*/ ISETP.NE.U32.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fc80003f05070 */
/*0ce0*/ ISETP.NE.AND.EX P0, PT, R16, RZ, PT, P0 ; /* 0x000000ff1000720c */
/* 0x000fe20003f05300 */
/*0cf0*/ DFMA R14, R14, R18, R22 ; /* 0x000000120e0e722b */
/* 0x010f620000000016 */
/*0d00*/ IADD3 R4, P1, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fca0007f3e0ff */
/*0d10*/ DFMA R12, R10, R12, R14 ; /* 0x0000000c0a0c722b */
/* 0x0200a4000000000e */
/*0d20*/ IADD3 R10, P2, R8, UR5, RZ ; /* 0x00000005080a7c10 */
/* 0x001fe2000ff5e0ff */
/*0d30*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc6000fffe03f */
/*0d40*/ IADD3.X R11, R9, UR6, RZ, P2, !PT ; /* 0x00000006090b7c10 */
/* 0x000fe200097fe4ff */
/*0d50*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0d60*/ DFMA R6, R6, R20, R12 ; /* 0x000000140606722b */
/* 0x004064000000000c */
/*0d70*/ @P0 BRA 0xbc0 ; /* 0xfffffe4000000947 */
/* 0x003fea000383ffff */
/*0d80*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f05070 */
/*0d90*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0da0*/ @!P0 BRA 0xf70 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0db0*/ USHF.R.S32.HI UR10, URZ, 0x1f, UR4 ; /* 0x0000001f3f0a7899 */
/* 0x000fe20008011404 */
/*0dc0*/ IADD3 R0, P0, RZ, -R0, RZ ; /* 0x80000000ff007210 */
/* 0x000fe20007f1e0ff */
/*0dd0*/ IMAD.U32 R13, RZ, RZ, UR4 ; /* 0x00000004ff0d7e24 */
/* 0x001fe2000f8e00ff */
/*0de0*/ UMOV UR5, 0x8 ; /* 0x0000000800057882 */
/* 0x000fe40000000000 */
/*0df0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0e00*/ IMAD.U32 R14, RZ, RZ, UR10 ; /* 0x0000000aff0e7e24 */
/* 0x000fe2000f8e00ff */
/*0e10*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe2000f8e0206 */
/*0e20*/ IMAD.X R12, RZ, RZ, -0x1, P0 ; /* 0xffffffffff0c7424 */
/* 0x000fe400000e06ff */
/*0e30*/ IMAD R8, R14, c[0x0][0x178], RZ ; /* 0x00005e000e087a24 */
/* 0x001fe400078e02ff */
/*0e40*/ IMAD.WIDE.U32 R4, R13, c[0x0][0x178], R2 ; /* 0x00005e000d047a25 */
/* 0x000fc800078e0002 */
/*0e50*/ IMAD R9, R13, c[0x0][0x17c], R8 ; /* 0x00005f000d097a24 */
/* 0x000fe200078e0208 */
/*0e60*/ LEA R10, P0, R4, c[0x0][0x160], 0x3 ; /* 0x00005800040a7a11 */
/* 0x000fe200078018ff */
/*0e70*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe4000f8e00ff */
/*0e80*/ IMAD.IADD R5, R5, 0x1, R9 ; /* 0x0000000105057824 */
/* 0x000fe400078e0209 */
/*0e90*/ IMAD.U32 R9, RZ, RZ, UR7 ; /* 0x00000007ff097e24 */
/* 0x000fc6000f8e00ff */
/*0ea0*/ LEA.HI.X R11, R4, c[0x0][0x164], R5, 0x3, P0 ; /* 0x00005900040b7a11 */
/* 0x000fc600000f1c05 */
/*0eb0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000ea8000c1e1b00 */
/*0ec0*/ LDG.E.64 R4, [R10.64] ; /* 0x000000080a047981 */
/* 0x000ea2000c1e1b00 */
/*0ed0*/ IADD3 R0, P0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007f1e0ff */
/*0ee0*/ UIADD3 UR6, UP0, UR6, 0x8, URZ ; /* 0x0000000806067890 */
/* 0x000fe2000ff1e03f */
/*0ef0*/ IADD3 R13, P1, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fc60007f3e0ff */
/*0f00*/ IMAD.X R12, RZ, RZ, R12, P0 ; /* 0x000000ffff0c7224 */
/* 0x000fe200000e060c */
/*0f10*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05070 */
/*0f20*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0f30*/ IMAD.X R14, RZ, RZ, R14, P1 ; /* 0x000000ffff0e7224 */
/* 0x000fe400008e060e */
/*0f40*/ ISETP.NE.AND.EX P0, PT, R12, RZ, PT, P0 ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05300 */
/*0f50*/ DFMA R6, R4, R8, R6 ; /* 0x000000080406722b */
/* 0x0060580000000006 */
/*0f60*/ @P0 BRA 0xe30 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0f70*/ LEA R4, P0, R2, c[0x0][0x170], 0x3 ; /* 0x00005c0002047a11 */
/* 0x001fc800078018ff */
/*0f80*/ LEA.HI.X R5, R2, c[0x0][0x174], R3, 0x3, P0 ; /* 0x00005d0002057a11 */
/* 0x000fca00000f1c03 */
/*0f90*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x002fe2000c101b08 */
/*0fa0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fb0*/ BRA 0xfb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPdS_S_ll
.globl _Z9matrixMulPdS_S_ll
.p2align 8
.type _Z9matrixMulPdS_S_ll,@function
_Z9matrixMulPdS_S_ll:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i64_e64 s[8:9], v[1:2]
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_cmp_lt_i64_e64 s4, s[2:3], 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_lshl_b64 s[4:5], s[8:9], 3
s_mov_b64 s[8:9], 0
.p2align 6
.LBB0_3:
global_load_b64 v[7:8], v[5:6], off
s_load_b64 s[10:11], s[6:7], 0x0
s_add_u32 s8, s8, 1
s_addc_u32 s9, s9, 0
v_add_co_u32 v5, vcc_lo, v5, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[3:4], s[10:11], v[7:8], v[3:4]
v_cmp_ge_i64_e64 s10, s[8:9], s[2:3]
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s10
s_cbranch_vccz .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPdS_S_ll
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPdS_S_ll, .Lfunc_end0-_Z9matrixMulPdS_S_ll
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPdS_S_ll
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPdS_S_ll.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012c2cb_00000000-6_gpu_mul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z9Print_MatiiPd
.type _Z9Print_MatiiPd, @function
_Z9Print_MatiiPd:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, 8(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 16(%rsp)
testl %edi, %edi
jle .L3
movl $0, %r15d
movl $0, %r14d
movslq %esi, %rax
movq %rax, 24(%rsp)
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r13
jmp .L5
.L14:
call _ZSt16__throw_bad_castv@PLT
.L8:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L9:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r14d
movl 8(%rsp), %eax
addl %eax, %r15d
cmpl %r14d, %eax
je .L3
.L5:
cmpl $0, 12(%rsp)
jle .L11
movslq %r15d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,8), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,8), %r12
.L6:
movsd (%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L6
.L11:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L14
cmpb $0, 56(%rbx)
je .L8
movzbl 67(%rbx), %esi
jmp .L9
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z9Print_MatiiPd, .-_Z9Print_MatiiPd
.globl _Z17matMultiplyOnHostPfS_S_iiiiii
.type _Z17matMultiplyOnHostPfS_S_iiiiii, @function
_Z17matMultiplyOnHostPfS_S_iiiiii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -8(%rsp)
movl %ecx, -12(%rsp)
movl 72(%rsp), %ebx
testl %ecx, %ecx
jle .L15
movq %rdi, %rbp
movq %rdx, %r15
movl %r8d, %r11d
movslq 56(%rsp), %rdi
salq $2, %rdi
movl $0, %r13d
movl $0, %ecx
movl $0, %edx
movslq %ebx, %r14
movq %r15, %r8
movq %r14, %rsi
jmp .L17
.L21:
movslq %ecx, %rax
leaq (%r8,%rax,4), %r10
movq -8(%rsp), %r14
movslq %r13d, %rax
leaq 0(%rbp,%rax,4), %r15
addq %rsi, %rax
leaq 0(%rbp,%rax,4), %r9
movl $0, %r12d
movl %edx, -20(%rsp)
movl %ecx, -16(%rsp)
.L20:
movq %r10, %rcx
movl $0x00000000, (%r10)
testl %ebx, %ebx
jle .L18
movq %r14, %rdx
movq %r15, %rax
.L19:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addq $4, %rax
addq %rdi, %rdx
cmpq %r9, %rax
jne .L19
.L18:
addl $1, %r12d
addq $4, %r10
addq $4, %r14
cmpl %r12d, %r11d
jne .L20
movl -20(%rsp), %edx
movl -16(%rsp), %ecx
.L22:
addl $1, %edx
addl %ebx, %ecx
addl %r11d, %r13d
cmpl %edx, -12(%rsp)
je .L15
.L17:
testl %r11d, %r11d
jg .L21
jmp .L22
.L15:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z17matMultiplyOnHostPfS_S_iiiiii, .-_Z17matMultiplyOnHostPfS_S_iiiiii
.globl _Z34__device_stub__Z9matrixMulPdS_S_llPdS_S_ll
.type _Z34__device_stub__Z9matrixMulPdS_S_llPdS_S_ll, @function
_Z34__device_stub__Z9matrixMulPdS_S_llPdS_S_ll:
.LFB3696:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9matrixMulPdS_S_ll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z34__device_stub__Z9matrixMulPdS_S_llPdS_S_ll, .-_Z34__device_stub__Z9matrixMulPdS_S_llPdS_S_ll
.globl _Z9matrixMulPdS_S_ll
.type _Z9matrixMulPdS_S_ll, @function
_Z9matrixMulPdS_S_ll:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9matrixMulPdS_S_llPdS_S_ll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z9matrixMulPdS_S_ll, .-_Z9matrixMulPdS_S_ll
.section .rodata.str1.1
.LC2:
.string "GPU A"
.text
.globl _Z14generate_b_gpuPdS_S_ll
.type _Z14generate_b_gpuPdS_S_ll, @function
_Z14generate_b_gpuPdS_S_ll:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rcx, %rbp
movq %r8, %rbx
movl $1, 8(%rsp)
movq %r8, %rax
shrq $63, %rax
addq %r8, %rax
sarq %rax
addl $1, %eax
movl %eax, 12(%rsp)
movl $1, 16(%rsp)
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L35:
call cudaPeekAtLastError@PLT
call cudaDeviceSynchronize@PLT
movl $5, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r13
testq %r13, %r13
je .L41
cmpb $0, 56(%r13)
je .L37
movzbl 67(%r13), %esi
.L38:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r12, %rdx
movl %ebp, %esi
movl %ebx, %edi
call _Z9Print_MatiiPd
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movq %rbp, %r8
movq %rbx, %rcx
movl $0, %edx
movl $0, %esi
movl $0, %edi
call _Z34__device_stub__Z9matrixMulPdS_S_llPdS_S_ll
jmp .L35
.L41:
call _ZSt16__throw_bad_castv@PLT
.L37:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L38
.cfi_endproc
.LFE3671:
.size _Z14generate_b_gpuPdS_S_ll, .-_Z14generate_b_gpuPdS_S_ll
.section .rodata.str1.1
.LC3:
.string "_Z9matrixMulPdS_S_ll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPdS_S_ll(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_mul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__matrixMulPdS_S_ll # -- Begin function _Z24__device_stub__matrixMulPdS_S_ll
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPdS_S_ll,@function
_Z24__device_stub__matrixMulPdS_S_ll: # @_Z24__device_stub__matrixMulPdS_S_ll
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9matrixMulPdS_S_ll, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixMulPdS_S_ll, .Lfunc_end0-_Z24__device_stub__matrixMulPdS_S_ll
.cfi_endproc
# -- End function
.globl _Z9Print_MatiiPd # -- Begin function _Z9Print_MatiiPd
.p2align 4, 0x90
.type _Z9Print_MatiiPd,@function
_Z9Print_MatiiPd: # @_Z9Print_MatiiPd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 8(%rsp) # 8-byte Spill
movl %esi, 4(%rsp) # 4-byte Spill
testl %edi, %edi
jle .LBB1_10
# %bb.1: # %.preheader.lr.ph
movl %edi, %r14d
movl %edi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 4(%rsp), %r13d # 4-byte Reload
xorl %ebx, %ebx
xorl %r12d, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_2 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r12
addl %r14d, %ebx
cmpq 16(%rsp), %r12 # 8-byte Folded Reload
je .LBB1_10
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %ebx, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r15
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%rbp,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbp
cmpq %rbp, %r13
jne .LBB1_4
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r15)
je .LBB1_8
# %bb.7: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r15), %eax
jmp .LBB1_9
.LBB1_10: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z9Print_MatiiPd, .Lfunc_end1-_Z9Print_MatiiPd
.cfi_endproc
# -- End function
.globl _Z17matMultiplyOnHostPfS_S_iiiiii # -- Begin function _Z17matMultiplyOnHostPfS_S_iiiiii
.p2align 4, 0x90
.type _Z17matMultiplyOnHostPfS_S_iiiiii,@function
_Z17matMultiplyOnHostPfS_S_iiiiii: # @_Z17matMultiplyOnHostPfS_S_iiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB2_9
# %bb.1: # %.preheader.lr.ph
movl 72(%rsp), %eax
movslq 56(%rsp), %r9
movslq %eax, %r10
movslq %r8d, %r11
movl %ecx, %ecx
movl %r11d, %ebx
movl %r10d, %r14d
shlq $2, %r11
shlq $2, %r9
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_8: # %._crit_edge30
# in Loop: Header=BB2_2 Depth=1
incq %r15
addq %r11, %rdi
cmpq %rcx, %r15
je .LBB2_9
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_6 Depth 3
testl %r8d, %r8d
jle .LBB2_8
# %bb.3: # %.lr.ph29
# in Loop: Header=BB2_2 Depth=1
movq %r15, %rdx
imulq %r10, %rdx
movq -8(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %r12
movq -16(%rsp), %rsi # 8-byte Reload
xorl %ebp, %ebp
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
incq %rbp
addq $4, %rsi
cmpq %rbx, %rbp
je .LBB2_8
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_6 Depth 3
movl $0, (%r12,%rbp,4)
testl %eax, %eax
jle .LBB2_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB2_4 Depth=2
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rsi, %r13
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r13), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r12,%rbp,4)
incq %rdx
addq %r9, %r13
cmpq %rdx, %r14
jne .LBB2_6
jmp .LBB2_7
.LBB2_9: # %._crit_edge32
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z17matMultiplyOnHostPfS_S_iiiiii, .Lfunc_end2-_Z17matMultiplyOnHostPfS_S_iiiiii
.cfi_endproc
# -- End function
.globl _Z14generate_b_gpuPdS_S_ll # -- Begin function _Z14generate_b_gpuPdS_S_ll
.p2align 4, 0x90
.type _Z14generate_b_gpuPdS_S_ll,@function
_Z14generate_b_gpuPdS_S_ll: # @_Z14generate_b_gpuPdS_S_ll
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r8, %r15
movq %rcx, %r14
movq %rdi, %rbx
movq %r8, %rax
shrq $63, %rax
addq %r8, %rax
andq $-2, %rax
shlq $31, %rax
movabsq $4294967297, %rdi # imm = 0x100000001
addq %rax, %rdi
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %r15, 56(%rsp)
movq %r14, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 120(%rsp), %rax
movq %rax, 72(%rsp)
leaq 112(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9matrixMulPdS_S_ll, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipPeekAtLastError
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB3_5
# %bb.4:
movzbl 67(%r12), %eax
jmp .LBB3_6
.LBB3_5:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl %r15d, %edi
movl %r14d, %esi
movq %rbx, %rdx
callq _Z9Print_MatiiPd
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_7:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z14generate_b_gpuPdS_S_ll, .Lfunc_end3-_Z14generate_b_gpuPdS_S_ll
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPdS_S_ll, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixMulPdS_S_ll,@object # @_Z9matrixMulPdS_S_ll
.section .rodata,"a",@progbits
.globl _Z9matrixMulPdS_S_ll
.p2align 3, 0x0
_Z9matrixMulPdS_S_ll:
.quad _Z24__device_stub__matrixMulPdS_S_ll
.size _Z9matrixMulPdS_S_ll, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU A"
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixMulPdS_S_ll"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPdS_S_ll
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPdS_S_ll
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Single Author info:
hmajety Hari Krishna Majety
Group info:
hmajety Hari Krishna Majety
srout Sweta Rout
mreddy2 Harshavardhan Reddy Muppidi
*/
#include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <time.h>
#define __DEBUG
#define TSCALE 1.0
#define VSQR 0.1
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
extern int tpdt(double *t, double dt, double end_time);
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
cudaError_t err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
__global__ void evolve_GPU(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t, int nThreads){
int idx = blockIdx.x*blockDim.x+threadIdx.x;
int i, j;
i = idx % n;
j = idx /n;
if(idx<n*n){
if( i == 0 || i == n - 1 || j == 0 || j == n - 1)
{
un[idx] = 0.;
}
else{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] + 0.25*(uc[idx + n - 1] + uc[idx + n + 1] + uc[idx - n - 1] + uc[idx - n + 1]) -
5 * uc[idx])/(h * h) + (double)(-__expf(-TSCALE * (float)t) * pebbles[idx]));
//un[idx] = 5;
/*un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] - 4 * uc[idx])/(h * h) + (double)(-__expf(-TSCALE * (float)t) ));*/
}
}
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
cudaEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
double *uc, *uo, *nd, *cd, *od, *pebblesd;
double t, dt;
//un = (double*)malloc(sizeof(double) * n * n);
uc = (double*)malloc(sizeof(double) * n * n);
uo = (double*)malloc(sizeof(double) * n * n);
memcpy(uo, u0, sizeof(double) * n * n);
memcpy(uc, u1, sizeof(double) * n * n);
t = 0.0;
dt = h / 2.;
/*for (int i = 0; i < n*n; ++i)
{
printf("%d - %lf; ",i, pebbles[i]);
}*/
/* Set up device timers */
CUDA_CALL(cudaSetDevice(0));
CUDA_CALL(cudaEventCreate(&kstart));
CUDA_CALL(cudaEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
int threadsPerBlock = nthreads * nthreads;
int nBlocks = (n/nthreads)*(n/nthreads);
//dim3 blockdims(nthreads,nthreads,1);
//dim3 griddims(n/nthreads , n/nthreads , 1 );
/* Start GPU computation timer */
CUDA_CALL(cudaEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
//Allocate CUDA Variables
CUDA_CALL(cudaMalloc((void **)&od, n*n*sizeof(double)));
CUDA_CALL(cudaMalloc((void **)&cd, n*n*sizeof(double)));
CUDA_CALL(cudaMalloc((void **)&nd, n*n*sizeof(double)));
CUDA_CALL(cudaMalloc((void **)&pebblesd, n*n*sizeof(double)));
//Copy values from Host to Device
CUDA_CALL(cudaMemcpy(od,uo, n*n*sizeof(double), cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpy(cd,uc, n*n*sizeof(double), cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpy(pebblesd,pebbles, n*n*sizeof(double), cudaMemcpyHostToDevice));
double *temp;
//int count=0;
while(1){
evolve_GPU<<<nBlocks,threadsPerBlock>>>(nd,cd,od,pebblesd,n,h,dt,t,nthreads);
//Exchange the variables to pass them for next iteration
temp = od;
od = cd;
cd = nd;
//printf(" %lf\n", t);
if(!tpdt(&t,dt,end_time)) break;
nd = temp;
}
//printf("%lf,%lf",sizeof(u),u[1]);
cudaMemcpy(u,nd, n*n*sizeof(double), cudaMemcpyDeviceToHost);
/* Stop GPU computation timer */
/*for (int i = 0; i < n; ++i)
{
for (int j = 0; j < n; ++j)
{
printf("%lf\n", u[i*n+j]);
}
}*/
CUDA_CALL(cudaEventRecord(kstop, 0));
CUDA_CALL(cudaEventSynchronize(kstop));
CUDA_CALL(cudaEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
CUDA_CALL(cudaFree(od));
CUDA_CALL(cudaFree(cd));
CUDA_CALL(cudaFree(temp));
CUDA_CALL(cudaFree(pebblesd));
free(uc);
free(uo);
/* timer cleanup */
CUDA_CALL(cudaEventDestroy(kstart));
CUDA_CALL(cudaEventDestroy(kstop));
CUDA_CALL(cudaDeviceReset());
} | code for sm_80
Function : _Z10evolve_GPUPdS_S_S_idddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff057624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0050*/ IMAD R3, R5, c[0x0][0x180], RZ ; /* 0x0000600005037a24 */
/* 0x000fca00078e02ff */
/*0060*/ ISETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R7, c[0x0][0x180] ; /* 0x0000600000077a13 */
/* 0x000fe20000000000 */
/*0090*/ IMAD.MOV.U32 R21, RZ, RZ, 0x8 ; /* 0x00000008ff157424 */
/* 0x000fe200078e00ff */
/*00a0*/ LOP3.LUT R10, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff0a7a12 */
/* 0x000fe200078e33ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e220000209400 */
/*00d0*/ IMAD.WIDE R16, R0, R21, c[0x0][0x160] ; /* 0x0000580000107625 */
/* 0x000fce00078e0215 */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fe200078e02ff */
/*0140*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*0150*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fe200078e0002 */
/*0160*/ LOP3.LUT R2, R0, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x0000600000027a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*0180*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*01a0*/ IMAD R4, R7, R4, R6 ; /* 0x0000000407047224 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GT.U32.AND P1, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f24070 */
/*01c0*/ @!P1 IMAD.IADD R4, R4, 0x1, -R7 ; /* 0x0000000104049824 */
/* 0x000fe200078e0a07 */
/*01d0*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe40003f06070 */
/*01f0*/ IADD3 R4, R5, -0x1, RZ ; /* 0xffffffff05047810 */
/* 0x000fd60007ffe0ff */
/*0200*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fc60003f05270 */
/*0220*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fca00078e0a03 */
/*0230*/ SEL R3, R10, R3, !P0 ; /* 0x000000030a037207 */
/* 0x000fca0004000000 */
/*0240*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a03 */
/*0250*/ IMAD R2, R7, c[0x0][0x180], R0 ; /* 0x0000600007027a24 */
/* 0x000fca00078e0200 */
/*0260*/ ISETP.NE.AND P0, PT, R2, R4, PT ; /* 0x000000040200720c */
/* 0x000fc80003f05270 */
/*0270*/ ISETP.EQ.OR P0, PT, R2, RZ, !P0 ; /* 0x000000ff0200720c */
/* 0x000fc80004702670 */
/*0280*/ ISETP.EQ.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fc80000702670 */
/*0290*/ ISETP.EQ.OR P0, PT, R3, R4, P0 ; /* 0x000000040300720c */
/* 0x000fda0000702670 */
/*02a0*/ @P0 BRA 0x720 ; /* 0x0000047000000947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.SHL.U32 R2, R0, 0x8, RZ ; /* 0x0000000800027824 */
/* 0x000fe200078e00ff */
/*02c0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*02d0*/ SHF.L.U64.HI R3, R0, 0x3, R3 ; /* 0x0000000300037819 */
/* 0x000fe40000010203 */
/*02e0*/ IADD3 R24, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002187a10 */
/* 0x000fc80007f1e0ff */
/*02f0*/ IADD3.X R25, R3, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003197a10 */
/* 0x000fca00007fe4ff */
/*0300*/ LDG.E.64 R6, [R24.64+0x8] ; /* 0x0000080418067981 */
/* 0x0000a8000c1e1b00 */
/*0310*/ LDG.E.64 R8, [R24.64+-0x8] ; /* 0xfffff80418087981 */
/* 0x0000a2000c1e1b00 */
/*0320*/ IMAD.WIDE R4, R5, 0x8, R24 ; /* 0x0000000805047825 */
/* 0x000fc800078e0218 */
/*0330*/ IMAD.IADD R28, R0.reuse, 0x1, R10 ; /* 0x00000001001c7824 */
/* 0x040fe200078e020a */
/*0340*/ LDG.E.64 R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x0002e2000c1e1b00 */
/*0350*/ IADD3 R20, R0, -c[0x0][0x180], RZ ; /* 0x8000600000147a10 */
/* 0x000fc60007ffe0ff */
/*0360*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000322000c1e1b00 */
/*0370*/ IMAD.WIDE R28, R28, R21, c[0x0][0x168] ; /* 0x00005a001c1c7625 */
/* 0x000fc600078e0215 */
/*0380*/ LDG.E.64 R14, [R4.64+-0x8] ; /* 0xfffff804040e7981 */
/* 0x0002e2000c1e1b00 */
/*0390*/ IMAD.WIDE R20, R20, R21, c[0x0][0x168] ; /* 0x00005a0014147625 */
/* 0x000fc600078e0215 */
/*03a0*/ LDG.E.64 R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x000f68000c1e1b00 */
/*03b0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f68000c1e1b00 */
/*03c0*/ LDG.E.64 R22, [R28.64+0x10] ; /* 0x000010041c167981 */
/* 0x000f68000c1e1b00 */
/*03d0*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x001f62000c1e1b00 */
/*03e0*/ IADD3 R26, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c00021a7a10 */
/* 0x000fc80007f1e0ff */
/*03f0*/ IADD3.X R27, R3, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00031b7a10 */
/* 0x000fcc00007fe4ff */
/*0400*/ LDG.E.64 R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000f62000c1e1b00 */
/*0410*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff047624 */
/* 0x002fe400078e00ff */
/*0420*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff057624 */
/* 0x000fcc00078e00ff */
/*0430*/ DMUL R4, R4, c[0x0][0x188] ; /* 0x0000620004047a28 */
/* 0x000e220000000000 */
/*0440*/ BSSY B0, 0x640 ; /* 0x000001f000007945 */
/* 0x000fe60003800000 */
/*0450*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x0041240000000008 */
/*0460*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e220000001800 */
/*0470*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fc600078e00ff */
/*0480*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x010fc8000000000a */
/*0490*/ DADD R12, R12, R14 ; /* 0x000000000c0c7229 */
/* 0x008f48000000000e */
/*04a0*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e080000000106 */
/*04b0*/ DADD R12, R12, R18 ; /* 0x000000000c0c7229 */
/* 0x020fc80000000012 */
/*04c0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e080000000008 */
/*04d0*/ DADD R10, R10, R20 ; /* 0x000000000a0a7229 */
/* 0x000fc80000000014 */
/*04e0*/ DFMA R6, R6, R8, R6 ; /* 0x000000080606722b */
/* 0x001e080000000006 */
/*04f0*/ DADD R12, R12, R22 ; /* 0x000000000c0c7229 */
/* 0x000e480000000016 */
/*0500*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e080000000106 */
/*0510*/ DFMA R10, R12, 0.25, R10 ; /* 0x3fd000000c0a782b */
/* 0x002e48000000000a */
/*0520*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001fc80000000006 */
/*0530*/ DFMA R6, R24, -5, R10 ; /* 0xc01400001806782b */
/* 0x002e0c000000000a */
/*0540*/ DMUL R10, R6, R8 ; /* 0x00000008060a7228 */
/* 0x001e0c0000000000 */
/*0550*/ DFMA R12, -R4, R10, R6 ; /* 0x0000000a040c722b */
/* 0x001e0c0000000106 */
/*0560*/ DFMA R8, R8, R12, R10 ; /* 0x0000000c0808722b */
/* 0x001062000000000a */
/*0570*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fe20003f2e200 */
/*0580*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0c7624 */
/* 0x001fe400078e00ff */
/*0590*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0d7624 */
/* 0x000fcc00078e00ff */
/*05a0*/ FFMA R0, RZ, R5, R9 ; /* 0x00000005ff007223 */
/* 0x002fca0000000009 */
/*05b0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fe20003f04200 */
/*05c0*/ DADD R14, R24, R24 ; /* 0x00000000180e7229 */
/* 0x000e080000000018 */
/*05d0*/ DMUL R12, R12, c[0x0][0x190] ; /* 0x000064000c0c7a28 */
/* 0x000e480000000000 */
/*05e0*/ DADD R14, R14, -R26 ; /* 0x000000000e0e7229 */
/* 0x001088000000081a */
/*05f0*/ DMUL R12, R12, c[0x2][0x0] ; /* 0x008000000c0c7a28 */
/* 0x002e620000000000 */
/*0600*/ @P0 BRA P1, 0x630 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*0610*/ MOV R0, 0x630 ; /* 0x0000063000007802 */
/* 0x005fca0000000f00 */
/*0620*/ CALL.REL.NOINC 0x740 ; /* 0x0000011000007944 */
/* 0x002fea0003c00000 */
/*0630*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x005fea0003800000 */
/*0640*/ IADD3 R4, P0, R2, c[0x0][0x178], RZ ; /* 0x00005e0002047a10 */
/* 0x000fc80007f1e0ff */
/*0650*/ IADD3.X R5, R3, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0003057a10 */
/* 0x000fcc00007fe4ff */
/*0660*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0670*/ F2F.F32.F64 R0, c[0x0][0x198] ; /* 0x0000660000007b10 */
/* 0x000e240000301000 */
/*0680*/ FMUL R0, R0, -1.4426950216293334961 ; /* 0xbfb8aa3b00007820 */
/* 0x001fca0000400000 */
/*0690*/ FSETP.GEU.AND P0, PT, R0, -126, PT ; /* 0xc2fc00000000780b */
/* 0x000fda0003f0e000 */
/*06a0*/ @!P0 FMUL R0, R0, 0.5 ; /* 0x3f00000000008820 */
/* 0x000fc80000400000 */
/*06b0*/ MUFU.EX2 R6, R0 ; /* 0x0000000000067308 */
/* 0x000e240000000800 */
/*06c0*/ @!P0 FMUL R6, R6, R6 ; /* 0x0000000606068220 */
/* 0x001fcc0000400000 */
/*06d0*/ F2F.F64.F32 R2, R6 ; /* 0x0000000600027310 */
/* 0x000ea40000201800 */
/*06e0*/ DFMA R2, R2, -R4, R8 ; /* 0x800000040202722b */
/* 0x004e0c0000000008 */
/*06f0*/ DFMA R2, R12, R2, R14 ; /* 0x000000020c02722b */
/* 0x003e0e000000000e */
/*0700*/ STG.E.64 [R16.64], R2 ; /* 0x0000000210007986 */
/* 0x001fe2000c101b04 */
/*0710*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0720*/ STG.E.64 [R16.64], RZ ; /* 0x000000ff10007986 */
/* 0x000fe2000c101b04 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f0e200 */
/*0750*/ IMAD.MOV.U32 R8, RZ, RZ, R4.reuse ; /* 0x000000ffff087224 */
/* 0x100fe200078e0004 */
/*0760*/ LOP3.LUT R10, R5, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff050a7812 */
/* 0x000fe200078ec0ff */
/*0770*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0780*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0790*/ IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; /* 0x00000001ff167424 */
/* 0x000fe200078e00ff */
/*07a0*/ LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a0b7812 */
/* 0x000fe200078efcff */
/*07b0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*07c0*/ LOP3.LUT R4, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007047812 */
/* 0x000fe200078ec0ff */
/*07d0*/ BSSY B1, 0xcf0 ; /* 0x0000051000017945 */
/* 0x000fe20003800000 */
/*07e0*/ LOP3.LUT R27, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000051b7812 */
/* 0x000fe200078ec0ff */
/*07f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff057424 */
/* 0x000fc400078e00ff */
/*0800*/ @!P0 DMUL R10, R8, 8.98846567431157953865e+307 ; /* 0x7fe00000080a8828 */
/* 0x000e220000000000 */
/*0810*/ ISETP.GE.U32.AND P1, PT, R4, R27, PT ; /* 0x0000001b0400720c */
/* 0x000fc60003f26070 */
/*0820*/ @!P2 LOP3.LUT R21, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000915a812 */
/* 0x000fe200078ec0ff */
/*0830*/ @!P2 IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff18a224 */
/* 0x000fe200078e00ff */
/*0840*/ MUFU.RCP64H R23, R11 ; /* 0x0000000b00177308 */
/* 0x001e240000001800 */
/*0850*/ @!P2 ISETP.GE.U32.AND P3, PT, R4, R21, PT ; /* 0x000000150400a20c */
/* 0x000fe40003f66070 */
/*0860*/ SEL R21, R5.reuse, 0x63400000, !P1 ; /* 0x6340000005157807 */
/* 0x040fe40004800000 */
/*0870*/ @!P2 SEL R25, R5, 0x63400000, !P3 ; /* 0x634000000519a807 */
/* 0x000fe40005800000 */
/*0880*/ @!P0 LOP3.LUT R27, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b1b8812 */
/* 0x000fc400078ec0ff */
/*0890*/ @!P2 LOP3.LUT R25, R25, 0x80000000, R7, 0xf8, !PT ; /* 0x800000001919a812 */
/* 0x000fc800078ef807 */
/*08a0*/ @!P2 LOP3.LUT R25, R25, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001919a812 */
/* 0x000fe200078efcff */
/*08b0*/ DFMA R18, R22, -R10, 1 ; /* 0x3ff000001612742b */
/* 0x001e0c000000080a */
/*08c0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*08d0*/ DFMA R22, R22, R18, R22 ; /* 0x000000121616722b */
/* 0x0010640000000016 */
/*08e0*/ LOP3.LUT R19, R21, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff15137812 */
/* 0x001fe200078ef807 */
/*08f0*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fc600078e0006 */
/*0900*/ DFMA R20, R22, -R10, 1 ; /* 0x3ff000001614742b */
/* 0x002e08000000080a */
/*0910*/ @!P2 DFMA R18, R18, 2, -R24 ; /* 0x400000001212a82b */
/* 0x000fc80000000818 */
/*0920*/ DFMA R20, R22, R20, R22 ; /* 0x000000141614722b */
/* 0x001e0c0000000016 */
/*0930*/ DMUL R22, R20, R18 ; /* 0x0000001214167228 */
/* 0x001e0c0000000000 */
/*0940*/ DFMA R24, R22, -R10, R18 ; /* 0x8000000a1618722b */
/* 0x001e0c0000000012 */
/*0950*/ DFMA R24, R20, R24, R22 ; /* 0x000000181418722b */
/* 0x0010640000000016 */
/*0960*/ IMAD.MOV.U32 R20, RZ, RZ, R4 ; /* 0x000000ffff147224 */
/* 0x001fe200078e0004 */
/*0970*/ @!P2 LOP3.LUT R20, R19, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001314a812 */
/* 0x000fe400078ec0ff */
/*0980*/ IADD3 R22, R27, -0x1, RZ ; /* 0xffffffff1b167810 */
/* 0x000fe40007ffe0ff */
/*0990*/ IADD3 R21, R20, -0x1, RZ ; /* 0xffffffff14157810 */
/* 0x000fc80007ffe0ff */
/*09a0*/ ISETP.GT.U32.AND P0, PT, R21, 0x7feffffe, PT ; /* 0x7feffffe1500780c */
/* 0x000fc80003f04070 */
/*09b0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fda0000704470 */
/*09c0*/ @P0 BRA 0xb90 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*09d0*/ LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009077812 */
/* 0x002fe200078ec0ff */
/*09e0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fc600078e00ff */
/*09f0*/ ISETP.GE.U32.AND P0, PT, R4.reuse, R7, PT ; /* 0x000000070400720c */
/* 0x040fe20003f06070 */
/*0a00*/ IMAD.IADD R6, R4, 0x1, -R7 ; /* 0x0000000104067824 */
/* 0x000fc600078e0a07 */
/*0a10*/ SEL R5, R5, 0x63400000, !P0 ; /* 0x6340000005057807 */
/* 0x000fe40004000000 */
/*0a20*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0a30*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*0a40*/ IMAD.IADD R6, R6, 0x1, -R5 ; /* 0x0000000106067824 */
/* 0x000fca00078e0a05 */
/*0a50*/ IADD3 R21, R6, 0x7fe00000, RZ ; /* 0x7fe0000006157810 */
/* 0x000fcc0007ffe0ff */
/*0a60*/ DMUL R4, R24, R20 ; /* 0x0000001418047228 */
/* 0x000e140000000000 */
/*0a70*/ FSETP.GTU.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x001fda0003f0c200 */
/*0a80*/ @P0 BRA 0xce0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0a90*/ DFMA R10, R24, -R10, R18 ; /* 0x8000000a180a722b */
/* 0x000e220000000012 */
/*0aa0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fd200078e00ff */
/*0ab0*/ FSETP.NEU.AND P0, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x041fe40003f0d000 */
/*0ac0*/ LOP3.LUT R7, R11, 0x80000000, R9, 0x48, !PT ; /* 0x800000000b077812 */
/* 0x000fc800078e4809 */
/*0ad0*/ LOP3.LUT R21, R7, R21, RZ, 0xfc, !PT ; /* 0x0000001507157212 */
/* 0x000fce00078efcff */
/*0ae0*/ @!P0 BRA 0xce0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0af0*/ IMAD.MOV R9, RZ, RZ, -R6 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a06 */
/*0b00*/ DMUL.RP R20, R24, R20 ; /* 0x0000001418147228 */
/* 0x000e220000008000 */
/*0b10*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fcc00078e00ff */
/*0b20*/ DFMA R8, R4, -R8, R24 ; /* 0x800000080408722b */
/* 0x000e460000000018 */
/*0b30*/ LOP3.LUT R7, R21, R7, RZ, 0x3c, !PT ; /* 0x0000000715077212 */
/* 0x001fc600078e3cff */
/*0b40*/ IADD3 R8, -R6, -0x43300000, RZ ; /* 0xbcd0000006087810 */
/* 0x002fc80007ffe1ff */
/*0b50*/ FSETP.NEU.AND P0, PT, |R9|, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f0d200 */
/*0b60*/ FSEL R4, R20, R4, !P0 ; /* 0x0000000414047208 */
/* 0x000fe40004000000 */
/*0b70*/ FSEL R5, R7, R5, !P0 ; /* 0x0000000507057208 */
/* 0x000fe20004000000 */
/*0b80*/ BRA 0xce0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0b90*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x002e1c0003f08000 */
/*0ba0*/ @P0 BRA 0xcc0 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0bb0*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0bc0*/ @P0 BRA 0xc90 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0bd0*/ ISETP.NE.AND P0, PT, R20, R27, PT ; /* 0x0000001b1400720c */
/* 0x000fe20003f05270 */
/*0be0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*0bf0*/ IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff057424 */
/* 0x000fd400078e00ff */
/*0c00*/ @!P0 BRA 0xce0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0c10*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0c20*/ LOP3.LUT R5, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007057812 */
/* 0x000fe400078e4809 */
/*0c30*/ ISETP.EQ.OR P0, PT, R27, RZ, !P0 ; /* 0x000000ff1b00720c */
/* 0x000fda0004702670 */
/*0c40*/ @P0 LOP3.LUT R6, R5, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000005060812 */
/* 0x000fe200078efcff */
/*0c50*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe400078e00ff */
/*0c60*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*0c70*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0006 */
/*0c80*/ BRA 0xce0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c90*/ LOP3.LUT R5, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009057812 */
/* 0x000fe200078efcff */
/*0ca0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0cb0*/ BRA 0xce0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0cc0*/ LOP3.LUT R5, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007057812 */
/* 0x000fe200078efcff */
/*0cd0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*0ce0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0cf0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*0d00*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fc400078e0005 */
/*0d10*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0d20*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0d30*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff2c004007950 */
/* 0x000fea0003c3ffff */
/*0d40*/ BRA 0xd40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Single Author info:
hmajety Hari Krishna Majety
Group info:
hmajety Hari Krishna Majety
srout Sweta Rout
mreddy2 Harshavardhan Reddy Muppidi
*/
#include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <time.h>
#define __DEBUG
#define TSCALE 1.0
#define VSQR 0.1
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
extern int tpdt(double *t, double dt, double end_time);
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
cudaError_t err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
__global__ void evolve_GPU(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t, int nThreads){
int idx = blockIdx.x*blockDim.x+threadIdx.x;
int i, j;
i = idx % n;
j = idx /n;
if(idx<n*n){
if( i == 0 || i == n - 1 || j == 0 || j == n - 1)
{
un[idx] = 0.;
}
else{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] + 0.25*(uc[idx + n - 1] + uc[idx + n + 1] + uc[idx - n - 1] + uc[idx - n + 1]) -
5 * uc[idx])/(h * h) + (double)(-__expf(-TSCALE * (float)t) * pebbles[idx]));
//un[idx] = 5;
/*un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] - 4 * uc[idx])/(h * h) + (double)(-__expf(-TSCALE * (float)t) ));*/
}
}
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
cudaEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
double *uc, *uo, *nd, *cd, *od, *pebblesd;
double t, dt;
//un = (double*)malloc(sizeof(double) * n * n);
uc = (double*)malloc(sizeof(double) * n * n);
uo = (double*)malloc(sizeof(double) * n * n);
memcpy(uo, u0, sizeof(double) * n * n);
memcpy(uc, u1, sizeof(double) * n * n);
t = 0.0;
dt = h / 2.;
/*for (int i = 0; i < n*n; ++i)
{
printf("%d - %lf; ",i, pebbles[i]);
}*/
/* Set up device timers */
CUDA_CALL(cudaSetDevice(0));
CUDA_CALL(cudaEventCreate(&kstart));
CUDA_CALL(cudaEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
int threadsPerBlock = nthreads * nthreads;
int nBlocks = (n/nthreads)*(n/nthreads);
//dim3 blockdims(nthreads,nthreads,1);
//dim3 griddims(n/nthreads , n/nthreads , 1 );
/* Start GPU computation timer */
CUDA_CALL(cudaEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
//Allocate CUDA Variables
CUDA_CALL(cudaMalloc((void **)&od, n*n*sizeof(double)));
CUDA_CALL(cudaMalloc((void **)&cd, n*n*sizeof(double)));
CUDA_CALL(cudaMalloc((void **)&nd, n*n*sizeof(double)));
CUDA_CALL(cudaMalloc((void **)&pebblesd, n*n*sizeof(double)));
//Copy values from Host to Device
CUDA_CALL(cudaMemcpy(od,uo, n*n*sizeof(double), cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpy(cd,uc, n*n*sizeof(double), cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpy(pebblesd,pebbles, n*n*sizeof(double), cudaMemcpyHostToDevice));
double *temp;
//int count=0;
while(1){
evolve_GPU<<<nBlocks,threadsPerBlock>>>(nd,cd,od,pebblesd,n,h,dt,t,nthreads);
//Exchange the variables to pass them for next iteration
temp = od;
od = cd;
cd = nd;
//printf(" %lf\n", t);
if(!tpdt(&t,dt,end_time)) break;
nd = temp;
}
//printf("%lf,%lf",sizeof(u),u[1]);
cudaMemcpy(u,nd, n*n*sizeof(double), cudaMemcpyDeviceToHost);
/* Stop GPU computation timer */
/*for (int i = 0; i < n; ++i)
{
for (int j = 0; j < n; ++j)
{
printf("%lf\n", u[i*n+j]);
}
}*/
CUDA_CALL(cudaEventRecord(kstop, 0));
CUDA_CALL(cudaEventSynchronize(kstop));
CUDA_CALL(cudaEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
CUDA_CALL(cudaFree(od));
CUDA_CALL(cudaFree(cd));
CUDA_CALL(cudaFree(temp));
CUDA_CALL(cudaFree(pebblesd));
free(uc);
free(uo);
/* timer cleanup */
CUDA_CALL(cudaEventDestroy(kstart));
CUDA_CALL(cudaEventDestroy(kstop));
CUDA_CALL(cudaDeviceReset());
} | .file "tmpxft_00062ed2_00000000-6_lakegpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z10evolve_GPUPdS_S_S_idddiPdS_S_S_idddi
.type _Z41__device_stub__Z10evolve_GPUPdS_S_S_idddiPdS_S_S_idddi, @function
_Z41__device_stub__Z10evolve_GPUPdS_S_S_idddiPdS_S_S_idddi:
.LFB2084:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movsd %xmm2, (%rsp)
movl %r9d, 24(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z10evolve_GPUPdS_S_S_idddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z41__device_stub__Z10evolve_GPUPdS_S_S_idddiPdS_S_S_idddi, .-_Z41__device_stub__Z10evolve_GPUPdS_S_S_idddiPdS_S_S_idddi
.globl _Z10evolve_GPUPdS_S_S_idddi
.type _Z10evolve_GPUPdS_S_S_idddi, @function
_Z10evolve_GPUPdS_S_S_idddi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z10evolve_GPUPdS_S_S_idddiPdS_S_S_idddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10evolve_GPUPdS_S_S_idddi, .-_Z10evolve_GPUPdS_S_S_idddi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/majetyhk/ParallelProgramming/master/HW2/p3/V2/lakegpu.cu"
.align 8
.LC3:
.string "cudaSafeCall() failed at %s:%i : %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPU computation: %f msec\n"
.text
.globl _Z7run_gpuPdS_S_S_iddi
.type _Z7run_gpuPdS_S_S_iddi, @function
_Z7run_gpuPdS_S_S_iddi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, %rbp
movl %r8d, 28(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 16(%rsp)
movl %r9d, %r15d
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movslq %r8d, %rbx
imulq %rbx, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 40(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 48(%rsp)
movq %rbx, %rcx
movq %rbx, %rdx
movq %r13, %rsi
movq %rax, %rdi
call __memcpy_chk@PLT
movq %rbx, %rcx
movq %rbx, %rdx
movq %r12, %rsi
movq %r14, %rdi
call __memcpy_chk@PLT
movq $0x000000000, 120(%rsp)
movsd 32(%rsp), %xmm3
mulsd .LC1(%rip), %xmm3
movsd %xmm3, 8(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L39
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L40
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L41
movl %r15d, %r14d
imull %r15d, %r14d
movl 28(%rsp), %eax
cltd
idivl %r15d
movl %eax, %r12d
imull %eax, %r12d
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L42
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L43
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L44
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L45
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L46
movl $1, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L47
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L37
leaq 120(%rsp), %r13
jmp .L22
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $128, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $129, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $130, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $140, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $144, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $145, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $146, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L46:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $147, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $150, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $151, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $152, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L23:
movq 104(%rsp), %rbp
movq 96(%rsp), %rax
movq %rax, 104(%rsp)
movq 88(%rsp), %rax
movq %rax, 96(%rsp)
movsd 16(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movq %r13, %rdi
call _Z4tpdtPddd@PLT
testl %eax, %eax
je .L24
movq %rbp, 88(%rsp)
.L22:
movl %r14d, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl %r12d, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L23
movl %r15d, %r9d
movsd 120(%rsp), %xmm2
movsd 8(%rsp), %xmm1
movsd 32(%rsp), %xmm0
movl 28(%rsp), %r8d
movq 112(%rsp), %rcx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z41__device_stub__Z10evolve_GPUPdS_S_S_idddiPdS_S_S_idddi
jmp .L23
.L24:
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L49
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L50
leaq 140(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L51
pxor %xmm0, %xmm0
cvtss2sd 140(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L52
movq 96(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L53
movq %rbp, %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L54
movq 112(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L55
movq 40(%rsp), %rdi
call free@PLT
movq 48(%rsp), %rdi
call free@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L56
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L57
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L58
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $175, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $176, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $177, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $181, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $182, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $183, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $184, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $188, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $189, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $190, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z7run_gpuPdS_S_S_iddi, .-_Z7run_gpuPdS_S_S_iddi
.section .rodata.str1.1
.LC5:
.string "_Z10evolve_GPUPdS_S_S_idddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10evolve_GPUPdS_S_S_idddi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Single Author info:
hmajety Hari Krishna Majety
Group info:
hmajety Hari Krishna Majety
srout Sweta Rout
mreddy2 Harshavardhan Reddy Muppidi
*/
#include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
#include <time.h>
#define __DEBUG
#define TSCALE 1.0
#define VSQR 0.1
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
extern int tpdt(double *t, double dt, double end_time);
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
cudaError_t err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
__global__ void evolve_GPU(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t, int nThreads){
int idx = blockIdx.x*blockDim.x+threadIdx.x;
int i, j;
i = idx % n;
j = idx /n;
if(idx<n*n){
if( i == 0 || i == n - 1 || j == 0 || j == n - 1)
{
un[idx] = 0.;
}
else{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] + 0.25*(uc[idx + n - 1] + uc[idx + n + 1] + uc[idx - n - 1] + uc[idx - n + 1]) -
5 * uc[idx])/(h * h) + (double)(-__expf(-TSCALE * (float)t) * pebbles[idx]));
//un[idx] = 5;
/*un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] - 4 * uc[idx])/(h * h) + (double)(-__expf(-TSCALE * (float)t) ));*/
}
}
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
cudaEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
double *uc, *uo, *nd, *cd, *od, *pebblesd;
double t, dt;
//un = (double*)malloc(sizeof(double) * n * n);
uc = (double*)malloc(sizeof(double) * n * n);
uo = (double*)malloc(sizeof(double) * n * n);
memcpy(uo, u0, sizeof(double) * n * n);
memcpy(uc, u1, sizeof(double) * n * n);
t = 0.0;
dt = h / 2.;
/*for (int i = 0; i < n*n; ++i)
{
printf("%d - %lf; ",i, pebbles[i]);
}*/
/* Set up device timers */
CUDA_CALL(cudaSetDevice(0));
CUDA_CALL(cudaEventCreate(&kstart));
CUDA_CALL(cudaEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
int threadsPerBlock = nthreads * nthreads;
int nBlocks = (n/nthreads)*(n/nthreads);
//dim3 blockdims(nthreads,nthreads,1);
//dim3 griddims(n/nthreads , n/nthreads , 1 );
/* Start GPU computation timer */
CUDA_CALL(cudaEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
//Allocate CUDA Variables
CUDA_CALL(cudaMalloc((void **)&od, n*n*sizeof(double)));
CUDA_CALL(cudaMalloc((void **)&cd, n*n*sizeof(double)));
CUDA_CALL(cudaMalloc((void **)&nd, n*n*sizeof(double)));
CUDA_CALL(cudaMalloc((void **)&pebblesd, n*n*sizeof(double)));
//Copy values from Host to Device
CUDA_CALL(cudaMemcpy(od,uo, n*n*sizeof(double), cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpy(cd,uc, n*n*sizeof(double), cudaMemcpyHostToDevice));
CUDA_CALL(cudaMemcpy(pebblesd,pebbles, n*n*sizeof(double), cudaMemcpyHostToDevice));
double *temp;
//int count=0;
while(1){
evolve_GPU<<<nBlocks,threadsPerBlock>>>(nd,cd,od,pebblesd,n,h,dt,t,nthreads);
//Exchange the variables to pass them for next iteration
temp = od;
od = cd;
cd = nd;
//printf(" %lf\n", t);
if(!tpdt(&t,dt,end_time)) break;
nd = temp;
}
//printf("%lf,%lf",sizeof(u),u[1]);
cudaMemcpy(u,nd, n*n*sizeof(double), cudaMemcpyDeviceToHost);
/* Stop GPU computation timer */
/*for (int i = 0; i < n; ++i)
{
for (int j = 0; j < n; ++j)
{
printf("%lf\n", u[i*n+j]);
}
}*/
CUDA_CALL(cudaEventRecord(kstop, 0));
CUDA_CALL(cudaEventSynchronize(kstop));
CUDA_CALL(cudaEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
CUDA_CALL(cudaFree(od));
CUDA_CALL(cudaFree(cd));
CUDA_CALL(cudaFree(temp));
CUDA_CALL(cudaFree(pebblesd));
free(uc);
free(uo);
/* timer cleanup */
CUDA_CALL(cudaEventDestroy(kstart));
CUDA_CALL(cudaEventDestroy(kstop));
CUDA_CALL(cudaDeviceReset());
} | /*
Single Author info:
hmajety Hari Krishna Majety
Group info:
hmajety Hari Krishna Majety
srout Sweta Rout
mreddy2 Harshavardhan Reddy Muppidi
*/
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define __DEBUG
#define TSCALE 1.0
#define VSQR 0.1
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
extern int tpdt(double *t, double dt, double end_time);
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
__global__ void evolve_GPU(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t, int nThreads){
int idx = blockIdx.x*blockDim.x+threadIdx.x;
int i, j;
i = idx % n;
j = idx /n;
if(idx<n*n){
if( i == 0 || i == n - 1 || j == 0 || j == n - 1)
{
un[idx] = 0.;
}
else{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] + 0.25*(uc[idx + n - 1] + uc[idx + n + 1] + uc[idx - n - 1] + uc[idx - n + 1]) -
5 * uc[idx])/(h * h) + (double)(-__expf(-TSCALE * (float)t) * pebbles[idx]));
//un[idx] = 5;
/*un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] - 4 * uc[idx])/(h * h) + (double)(-__expf(-TSCALE * (float)t) ));*/
}
}
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
hipEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
double *uc, *uo, *nd, *cd, *od, *pebblesd;
double t, dt;
//un = (double*)malloc(sizeof(double) * n * n);
uc = (double*)malloc(sizeof(double) * n * n);
uo = (double*)malloc(sizeof(double) * n * n);
memcpy(uo, u0, sizeof(double) * n * n);
memcpy(uc, u1, sizeof(double) * n * n);
t = 0.0;
dt = h / 2.;
/*for (int i = 0; i < n*n; ++i)
{
printf("%d - %lf; ",i, pebbles[i]);
}*/
/* Set up device timers */
CUDA_CALL(hipSetDevice(0));
CUDA_CALL(hipEventCreate(&kstart));
CUDA_CALL(hipEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
int threadsPerBlock = nthreads * nthreads;
int nBlocks = (n/nthreads)*(n/nthreads);
//dim3 blockdims(nthreads,nthreads,1);
//dim3 griddims(n/nthreads , n/nthreads , 1 );
/* Start GPU computation timer */
CUDA_CALL(hipEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
//Allocate CUDA Variables
CUDA_CALL(hipMalloc((void **)&od, n*n*sizeof(double)));
CUDA_CALL(hipMalloc((void **)&cd, n*n*sizeof(double)));
CUDA_CALL(hipMalloc((void **)&nd, n*n*sizeof(double)));
CUDA_CALL(hipMalloc((void **)&pebblesd, n*n*sizeof(double)));
//Copy values from Host to Device
CUDA_CALL(hipMemcpy(od,uo, n*n*sizeof(double), hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpy(cd,uc, n*n*sizeof(double), hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpy(pebblesd,pebbles, n*n*sizeof(double), hipMemcpyHostToDevice));
double *temp;
//int count=0;
while(1){
evolve_GPU<<<nBlocks,threadsPerBlock>>>(nd,cd,od,pebblesd,n,h,dt,t,nthreads);
//Exchange the variables to pass them for next iteration
temp = od;
od = cd;
cd = nd;
//printf(" %lf\n", t);
if(!tpdt(&t,dt,end_time)) break;
nd = temp;
}
//printf("%lf,%lf",sizeof(u),u[1]);
hipMemcpy(u,nd, n*n*sizeof(double), hipMemcpyDeviceToHost);
/* Stop GPU computation timer */
/*for (int i = 0; i < n; ++i)
{
for (int j = 0; j < n; ++j)
{
printf("%lf\n", u[i*n+j]);
}
}*/
CUDA_CALL(hipEventRecord(kstop, 0));
CUDA_CALL(hipEventSynchronize(kstop));
CUDA_CALL(hipEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
CUDA_CALL(hipFree(od));
CUDA_CALL(hipFree(cd));
CUDA_CALL(hipFree(temp));
CUDA_CALL(hipFree(pebblesd));
free(uc);
free(uo);
/* timer cleanup */
CUDA_CALL(hipEventDestroy(kstart));
CUDA_CALL(hipEventDestroy(kstop));
CUDA_CALL(hipDeviceReset());
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Single Author info:
hmajety Hari Krishna Majety
Group info:
hmajety Hari Krishna Majety
srout Sweta Rout
mreddy2 Harshavardhan Reddy Muppidi
*/
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define __DEBUG
#define TSCALE 1.0
#define VSQR 0.1
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
extern int tpdt(double *t, double dt, double end_time);
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
__global__ void evolve_GPU(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t, int nThreads){
int idx = blockIdx.x*blockDim.x+threadIdx.x;
int i, j;
i = idx % n;
j = idx /n;
if(idx<n*n){
if( i == 0 || i == n - 1 || j == 0 || j == n - 1)
{
un[idx] = 0.;
}
else{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] + 0.25*(uc[idx + n - 1] + uc[idx + n + 1] + uc[idx - n - 1] + uc[idx - n + 1]) -
5 * uc[idx])/(h * h) + (double)(-__expf(-TSCALE * (float)t) * pebbles[idx]));
//un[idx] = 5;
/*un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] - 4 * uc[idx])/(h * h) + (double)(-__expf(-TSCALE * (float)t) ));*/
}
}
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
hipEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
double *uc, *uo, *nd, *cd, *od, *pebblesd;
double t, dt;
//un = (double*)malloc(sizeof(double) * n * n);
uc = (double*)malloc(sizeof(double) * n * n);
uo = (double*)malloc(sizeof(double) * n * n);
memcpy(uo, u0, sizeof(double) * n * n);
memcpy(uc, u1, sizeof(double) * n * n);
t = 0.0;
dt = h / 2.;
/*for (int i = 0; i < n*n; ++i)
{
printf("%d - %lf; ",i, pebbles[i]);
}*/
/* Set up device timers */
CUDA_CALL(hipSetDevice(0));
CUDA_CALL(hipEventCreate(&kstart));
CUDA_CALL(hipEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
int threadsPerBlock = nthreads * nthreads;
int nBlocks = (n/nthreads)*(n/nthreads);
//dim3 blockdims(nthreads,nthreads,1);
//dim3 griddims(n/nthreads , n/nthreads , 1 );
/* Start GPU computation timer */
CUDA_CALL(hipEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
//Allocate CUDA Variables
CUDA_CALL(hipMalloc((void **)&od, n*n*sizeof(double)));
CUDA_CALL(hipMalloc((void **)&cd, n*n*sizeof(double)));
CUDA_CALL(hipMalloc((void **)&nd, n*n*sizeof(double)));
CUDA_CALL(hipMalloc((void **)&pebblesd, n*n*sizeof(double)));
//Copy values from Host to Device
CUDA_CALL(hipMemcpy(od,uo, n*n*sizeof(double), hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpy(cd,uc, n*n*sizeof(double), hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpy(pebblesd,pebbles, n*n*sizeof(double), hipMemcpyHostToDevice));
double *temp;
//int count=0;
while(1){
evolve_GPU<<<nBlocks,threadsPerBlock>>>(nd,cd,od,pebblesd,n,h,dt,t,nthreads);
//Exchange the variables to pass them for next iteration
temp = od;
od = cd;
cd = nd;
//printf(" %lf\n", t);
if(!tpdt(&t,dt,end_time)) break;
nd = temp;
}
//printf("%lf,%lf",sizeof(u),u[1]);
hipMemcpy(u,nd, n*n*sizeof(double), hipMemcpyDeviceToHost);
/* Stop GPU computation timer */
/*for (int i = 0; i < n; ++i)
{
for (int j = 0; j < n; ++j)
{
printf("%lf\n", u[i*n+j]);
}
}*/
CUDA_CALL(hipEventRecord(kstop, 0));
CUDA_CALL(hipEventSynchronize(kstop));
CUDA_CALL(hipEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
CUDA_CALL(hipFree(od));
CUDA_CALL(hipFree(cd));
CUDA_CALL(hipFree(temp));
CUDA_CALL(hipFree(pebblesd));
free(uc);
free(uo);
/* timer cleanup */
CUDA_CALL(hipEventDestroy(kstart));
CUDA_CALL(hipEventDestroy(kstop));
CUDA_CALL(hipDeviceReset());
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10evolve_GPUPdS_S_S_idddi
.globl _Z10evolve_GPUPdS_S_S_idddi
.p2align 8
.type _Z10evolve_GPUPdS_S_S_idddi,@function
_Z10evolve_GPUPdS_S_S_idddi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b32 s10, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s10, s10
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_8
s_ashr_i32 s2, s10, 31
v_ashrrev_i32_e32 v4, 31, v1
s_add_i32 s3, s10, s2
s_mov_b32 s9, exec_lo
s_xor_b32 s3, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v1, v4
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s4, 0, s3
v_xor_b32_e32 v5, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v4, s2, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mad_u64_u32 v[2:3], null, v5, v0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v3, s3
v_add_nc_u32_e32 v2, 1, v3
v_sub_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v5, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v0, v0, v5 :: v_dual_add_nc_u32 v3, 1, v2
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v2, v3, vcc_lo
v_xor_b32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v4
v_mul_lo_u32 v2, v0, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v2
v_cmp_eq_u32_e64 s8, 0, v2
v_cmpx_ne_u32_e32 0, v2
s_cbranch_execz .LBB0_5
s_add_i32 s3, s10, -1
v_cmp_ne_u32_e64 s2, 0, v0
v_cmp_ne_u32_e32 vcc_lo, s3, v2
v_cmp_ne_u32_e64 s3, s3, v0
s_mov_b32 s4, -1
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[16:17], s[0:1], 0x18
v_add_nc_u32_e32 v3, s10, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[15:16], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v4, vcc_lo
s_clause 0x3
global_load_b128 v[3:6], v[7:8], off
global_load_b64 v[17:18], v[7:8], off offset:-8
global_load_b128 v[7:10], v[11:12], off
global_load_b64 v[19:20], v[11:12], off offset:-8
v_subrev_nc_u32_e32 v11, s10, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 3, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
s_clause 0x1
global_load_b64 v[21:22], v[11:12], off offset:-8
global_load_b128 v[11:14], v[11:12], off
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x28
s_load_b64 s[4:5], s[0:1], 0x38
s_waitcnt lgkmcnt(0)
v_cvt_f32_f64_e32 v0, s[4:5]
s_mov_b32 s5, 0x3fb99999
s_mov_b32 s4, 0x9999999a
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, 0xbfb8aa3b, v0
v_exp_f32_e32 v0, v0
s_waitcnt vmcnt(4)
v_add_f64 v[5:6], v[17:18], v[5:6]
s_waitcnt vmcnt(2)
v_add_f64 v[9:10], v[19:20], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[7:8]
s_waitcnt vmcnt(1)
v_add_f64 v[7:8], v[9:10], v[21:22]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[11:12]
v_add_f64 v[7:8], v[7:8], v[13:14]
v_add_co_u32 v13, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, s16, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s17, v16, vcc_lo
global_load_b64 v[13:14], v[13:14], off
global_load_b64 v[15:16], v[15:16], off
v_fma_f64 v[5:6], v[7:8], 0x3fd00000, v[5:6]
v_mul_f64 v[7:8], s[12:13], s[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[3:4], 0xc0140000, v[5:6]
v_div_scale_f64 v[9:10], null, v[7:8], v[7:8], v[5:6]
v_div_scale_f64 v[19:20], vcc_lo, v[5:6], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[11:12], v[9:10]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[17:18], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[17:18], v[11:12]
s_waitcnt vmcnt(1)
v_fma_f64 v[3:4], v[3:4], 2.0, -v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[19:20], v[11:12]
v_fma_f64 v[9:10], -v[9:10], v[17:18], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[17:18]
v_mul_f64 v[11:12], s[14:15], s[14:15]
v_div_fixup_f64 v[5:6], v[9:10], v[7:8], v[5:6]
v_cvt_f64_f32_e32 v[7:8], v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f64 v[9:10], v[11:12], s[4:5]
s_xor_b32 s4, exec_lo, -1
s_waitcnt vmcnt(0)
v_fma_f64 v[5:6], -v[15:16], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[3:4], v[9:10], v[5:6], v[3:4]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s8, exec_lo
s_and_b32 s3, s4, exec_lo
s_or_b32 s8, s2, s3
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s2, s8
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
v_ashrrev_i32_e32 v2, 31, v1
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10evolve_GPUPdS_S_S_idddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10evolve_GPUPdS_S_S_idddi, .Lfunc_end0-_Z10evolve_GPUPdS_S_S_idddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10evolve_GPUPdS_S_S_idddi
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10evolve_GPUPdS_S_S_idddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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