system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
55.5k
|
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b94f5_00000000-6_histo1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5histoPiPKiiPiPKii
.type _Z28__device_stub__Z5histoPiPKiiPiPKii, @function
_Z28__device_stub__Z5histoPiPKiiPiPKii:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5histoPiPKii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z5histoPiPKiiPiPKii, .-_Z28__device_stub__Z5histoPiPKiiPiPKii
.globl _Z5histoPiPKii
.type _Z5histoPiPKii, @function
_Z5histoPiPKii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5histoPiPKiiPiPKii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5histoPiPKii, .-_Z5histoPiPKii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "error: no devices supporting CUDA.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Using device %d:\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "%s; global mem: %dB; compute v%d.%d; clock: %d kHz\n"
.section .rodata.str1.1
.LC3:
.string "bin %d: count %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1624, %rsp
.cfi_def_cfa_offset 1648
movq %fs:40, %rax
movq %rax, 1608(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 4(%rsp)
je .L21
movl $0, %edi
call cudaSetDevice@PLT
leaq 576(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
je .L22
.L13:
movl $0, %eax
.L14:
movl %eax, 64(%rsp,%rax,4)
addq $1, %rax
cmpq $128, %rax
jne .L14
movl $0, 52(%rsp)
movl $0, 56(%rsp)
movl $0, 60(%rsp)
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $512, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 52(%rsp), %rsi
movl $1, %ecx
movl $12, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
leaq 52(%rsp), %rdi
movl $2, %ecx
movl $12, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC3(%rip), %rbp
.L16:
movl 52(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L16
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 1608(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $1624, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
movl $0, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 576(%rsp), %rdx
subq $8, %rsp
.cfi_def_cfa_offset 1656
movl 932(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1664
movl 956(%rsp), %r9d
movl 952(%rsp), %r8d
movl 880(%rsp), %ecx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1648
jmp .L13
.L23:
movl $3, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z28__device_stub__Z5histoPiPKiiPiPKii
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z36__device_stub__Z12simple_histoPiPKiiPiPKii
.type _Z36__device_stub__Z12simple_histoPiPKiiPiPKii, @function
_Z36__device_stub__Z12simple_histoPiPKiiPiPKii:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12simple_histoPiPKii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z12simple_histoPiPKiiPiPKii, .-_Z36__device_stub__Z12simple_histoPiPKiiPiPKii
.globl _Z12simple_histoPiPKii
.type _Z12simple_histoPiPKii, @function
_Z12simple_histoPiPKii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12simple_histoPiPKiiPiPKii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12simple_histoPiPKii, .-_Z12simple_histoPiPKii
.section .rodata.str1.1
.LC4:
.string "_Z12simple_histoPiPKii"
.LC5:
.string "_Z5histoPiPKii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12simple_histoPiPKii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z5histoPiPKii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "histo1.hip"
.globl _Z20__device_stub__histoPiPKii # -- Begin function _Z20__device_stub__histoPiPKii
.p2align 4, 0x90
.type _Z20__device_stub__histoPiPKii,@function
_Z20__device_stub__histoPiPKii: # @_Z20__device_stub__histoPiPKii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5histoPiPKii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z20__device_stub__histoPiPKii, .Lfunc_end0-_Z20__device_stub__histoPiPKii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__simple_histoPiPKii # -- Begin function _Z27__device_stub__simple_histoPiPKii
.p2align 4, 0x90
.type _Z27__device_stub__simple_histoPiPKii,@function
_Z27__device_stub__simple_histoPiPKii: # @_Z27__device_stub__simple_histoPiPKii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12simple_histoPiPKii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z27__device_stub__simple_histoPiPKii, .Lfunc_end1-_Z27__device_stub__simple_histoPiPKii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $2128, %rsp # imm = 0x850
.cfi_def_cfa_offset 2144
.cfi_offset %rbx, -16
leaq 24(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 24(%rsp)
je .LBB2_10
# %bb.1:
xorl %edi, %edi
callq hipSetDevice
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movl $.L.str.1, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
movl 504(%rsp), %ecx
movl 508(%rsp), %r8d
movl 432(%rsp), %edx
movl 492(%rsp), %r9d
leaq 144(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.LBB2_3:
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_4: # =>This Inner Loop Header: Depth=1
movl %eax, 1616(%rsp,%rax,4)
incq %rax
cmpq $128, %rax
jne .LBB2_4
# %bb.5:
movl $0, 40(%rsp)
movq $0, 32(%rsp)
leaq 16(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 8(%rsp), %rdi
movl $12, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 1616(%rsp), %rsi
movl $512, %edx # imm = 0x200
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $12, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $3, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5histoPiPKii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $12, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_8: # =>This Inner Loop Header: Depth=1
movl 32(%rsp,%rbx,4), %edx
movl $.L.str.3, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $3, %rbx
jne .LBB2_8
# %bb.9:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $2128, %rsp # imm = 0x850
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_10:
.cfi_def_cfa_offset 2144
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $35, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5histoPiPKii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12simple_histoPiPKii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5histoPiPKii,@object # @_Z5histoPiPKii
.section .rodata,"a",@progbits
.globl _Z5histoPiPKii
.p2align 3, 0x0
_Z5histoPiPKii:
.quad _Z20__device_stub__histoPiPKii
.size _Z5histoPiPKii, 8
.type _Z12simple_histoPiPKii,@object # @_Z12simple_histoPiPKii
.globl _Z12simple_histoPiPKii
.p2align 3, 0x0
_Z12simple_histoPiPKii:
.quad _Z27__device_stub__simple_histoPiPKii
.size _Z12simple_histoPiPKii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error: no devices supporting CUDA.\n"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Using device %d:\n"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s
.size .L.str.2, 52
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "bin %d: count %d\n"
.size .L.str.3, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5histoPiPKii"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12simple_histoPiPKii"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__histoPiPKii
.addrsig_sym _Z27__device_stub__simple_histoPiPKii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5histoPiPKii
.addrsig_sym _Z12simple_histoPiPKii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <string.h>
#include <cuda.h>
/*********************************/
/** constants/define statements **/
/*********************************/
#define THREADS_PER_BLOCK 1024
#define MAX_BLOCKS 65535
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
#define BUFFER_CHAR 'A'
#define PAD_AMT 5
/**********************/
/** function headers **/
/**********************/
void usage(void);
int init_data(char** data, unsigned int num_chars);
int init_data_pad(char** data, unsigned int num_chars);
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len, unsigned int vicinity);
void free_data(char* data, unsigned int num_genomes);
__global__ void readcmp(char* a, char* b, /*char* result,*/
unsigned long nthreads, unsigned int str_len,
unsigned int vicinity, unsigned int tstride,
char *reduce, unsigned int pop_thresh,
unsigned int threads_per_block,
unsigned int shift_amt);
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads,
unsigned int str_len, unsigned int pop_thresh,
unsigned int tstride);
void print_device_info(void);
unsigned int next_power_2(unsigned int v);
unsigned int log_2(unsigned int v);
/***************/
/** functions **/
/***************/
/*
* Function - gpuAssert
*
* Inputs:
* code - gpu error code
* file - current source file
* line - line within this file
* abort - if true, the prgram aborts
*
* Description:
* This function checks the cuda error code, and aborts if it is not a
* success.
*/
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n",cudaGetErrorString(code),file,line);
if (abort) exit(code);
}
}
/*
* Kernel - readcmp
*
* Inputs:
* a - a pointer to one read
* b - a pointer to the other read
* nthreads - the maximum number of threads used
* str_len - the length of the reads to be compared (this is a power of 2)
* vicinity - the bit-flip vicinity
* tstride - the read index stride distance for each thread
* pop_thresh - the pop count threshold
* thread_per_block - the number of threads per block
* shift_amt - the maximum shift amount between the reads
*
* Outputs:
* reduce - the array returned which contains 0 for "reads match" or 1 for
* "reads don't match"
*
* Description:
* This Kernel does two things: for each pair of reads, it compares the
* characters and stores the bit-op results. It then performas a sum
* reduction on each read comparison and checks if it is above the edit
* threshold.
*/
__global__ void readcmp(char *dev_test_array, char *a, char *b, /*char *result,*/ unsigned long nthreads, unsigned int str_len, unsigned int vicinity, unsigned int tstride, char *reduce, unsigned int pop_thresh, unsigned int threads_per_block, unsigned int shift_amt) {
// Set up shared memory
extern __shared__ char shared_data[];
char* sdata = (char *)shared_data;
char* result = (char *)&shared_data[threads_per_block];
// Find index of this thread
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long tid = x + y * blockDim.x * gridDim.x;
unsigned long i = threadIdx.x; //local block tid
int j, k;
while(tid < nthreads) {
//make the first xor comparison without shifting
result[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT];
__syncthreads();
//check the vicinity for 100...01
if (result[i]!=0) {
for (j=1; j<vicinity; j++) {
if(result[i+j]!=0)
break;
}
if (result[i+j]!=0) {
for (k=1; k<j; k++) {
result[i+k]=0xff;
}
}
}
//make the remaining xor comparisons with shifting up until the limit
for(unsigned int cur_shift = 1; cur_shift <= shift_amt; cur_shift++) {
__syncthreads();
sdata[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT-cur_shift]; //shift b left
__syncthreads();
//check vicinity
if (sdata[i] != 0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
//AND result
__syncthreads();
result[i] = result[i] && sdata[i];
sdata[i] = b[tid+PAD_AMT] ^ a[tid+PAD_AMT-cur_shift]; //shift a left
__syncthreads();
//check vicinity
if (sdata[i]!=0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
//AND result
__syncthreads();
result[i] = result[i] && sdata[i];
__syncthreads();
}
/////////////////////////////////////////////////////////////////////
// the code below is used for the sum reduce
/////////////////////////////////////////////////////////////////////
sdata[i] = result[i];
__syncthreads();
/*
* conservative reduction implemented by John Emmons Feb. 2014
* EX. if vicinity = 3 then 111100110111111 -> 100100110100101
*/
if(sdata[i] != 0 && (i == 0 || sdata[i-1] == 0)){
int m, n = i;
bool flag = true;
while(true){
for(m = 1; m < vicinity + 1; m++){
if(n + m < str_len) {
if(sdata[n + m] != 0){ continue; }
else if(m < 2){ flag = false; break; }
else{ break; }
}
else{
if(m < 2){ flag = false; break; }
else{ break; }
}
}
if(flag){
for(m -= 2; m > 0; m--)
sdata[n + m] = 0x00;
n += vicinity;
}
else{ break; }
}
}
__syncthreads();
// conservative reduction debugging
dev_test_array[i] = sdata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
if(i < s) {
sdata[i] += sdata[i + s];
}
__syncthreads();
}
__syncthreads();
// write result for this block to global mem
if(i%str_len == 0) {
reduce[tid/str_len] = (sdata[i]<=pop_thresh)?0:1;
}
///////////////////////////////////////////////////////////////////////
__syncthreads();
tid += tstride; //increase tid by thread stride amount
}
}
/*********************************/
/** THIS FUNCTION IS DEPRECATED **/
/*********************************/
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads, unsigned int str_len, unsigned int pop_thresh, unsigned int tstride) {
extern __shared__ char sdata[];
// each thread loads one element from global to shared mem
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long i = x + y * blockDim.x * gridDim.x; //global tid
unsigned int tid = threadIdx.x; //local block tid
while(i < nthreads) {
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
if (tid<s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid%str_len == 0) {
g_odata[i/str_len] = (sdata[tid]<=pop_thresh)?1:0;
g_odata[i/str_len] = sdata[tid];
}
i += tstride;
}
}
/*
* Function - main
*
* Arguments:
* argc - the number of command line arguments
* argv - an array of the command line arguments
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This is the main function. It initializes memory. It reads in the
* files which contain the reads. It, then, launches the kernel on
* the GPU.
*/
int main(int argc, char *argv[]) {
/* check the number of command line arguments */
if(argc != 8) {
usage();
return 1;
}
/* get arguments */
char* file_1;
char* file_2;
unsigned int num_genomes, genome_len, buffed_len,
buffer_len, vicinity, errors, pop_thresh, shift_amt;
FILE *pop_count_file;
file_1 = argv[1]; //contains reads
file_2 = argv[2]; //contains reads
num_genomes = atoi(argv[3]); //the number of reads in each file
genome_len = atoi(argv[4]); //the length of each read
errors = atoi(argv[5]); //the number of edits allowed between two reads
vicinity = atoi(argv[6]); //the vicinity for bit flips
shift_amt = atoi(argv[7]); //the maximum shift amount when comparing reads
/* calculate important values */
pop_thresh = /*(vicinity-1)*(errors-1) +*/ errors; //popcount threshold (is simply the num of allowed errors with conservative reduction)
buffed_len = next_power_2(genome_len); //genome length + buffer space
buffer_len = buffed_len - genome_len; //difference bw genome len and buf len
unsigned long num_chars = num_genomes*buffed_len; //the total number of chars in every buffed read
/* initialize and allocate strings to compare */
char* genome_1_data; //first genome data
char* genome_2_data; //second genome data
char* reduce_data; //sum of "errors" in each string
if(init_data_pad(&genome_1_data, num_chars)) return 1;
if(init_data_pad(&genome_2_data, num_chars)) return 1;
if(init_data(&reduce_data, num_genomes)) return 1;
// conservative reduction debugging
char* test_array;
if(init_data(&test_array, num_chars+PAD_AMT)) return 1;
/* read in the data */
if(read_data(genome_1_data, file_1, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
if(read_data(genome_2_data, file_2, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
/* create timing events */
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
/* initialize and allocate memoer for GPU input and output arrays */
char *dev_genome_1_data;
char *dev_genome_2_data;
char *dev_reduce_data;
gpuErrchk( cudaMalloc((void**)&dev_genome_1_data, (num_chars+PAD_AMT)*sizeof(char)));
gpuErrchk( cudaMalloc((void**)&dev_genome_2_data, (num_chars+PAD_AMT)*sizeof(char)));
gpuErrchk( cudaMalloc((void**)&dev_reduce_data, num_genomes*sizeof(char) ));
// conservative reduction debugging
char *dev_test_array;
gpuErrchk( cudaMalloc((void**)&dev_test_array, (num_chars+PAD_AMT)*sizeof(char) ));
/******************/
/** START TIMING **/
/******************/
/*========================================================================*/
/* set start time */
cudaEventRecord(start, 0);
/* copy data to GPU */
gpuErrchk(cudaMemcpy( dev_genome_1_data, genome_1_data,
(num_chars+PAD_AMT)*sizeof(char), cudaMemcpyHostToDevice ));
gpuErrchk(cudaMemcpy( dev_genome_2_data, genome_2_data,
(num_chars+PAD_AMT)*sizeof(char), cudaMemcpyHostToDevice ));
// conservative reduction debugging
gpuErrchk(cudaMemcpy( dev_test_array, test_array,
(num_chars+PAD_AMT)*sizeof(char), cudaMemcpyHostToDevice ));
/* figure out thread count and dimensions for GPU */
unsigned int num_blocks_x = 128;
unsigned int num_blocks_y = 128;
unsigned int threads_per_block = buffed_len;
unsigned int tstride = threads_per_block*num_blocks_x*num_blocks_y;
dim3 grid_size(num_blocks_x, num_blocks_y, 1);
unsigned int log_len = log_2(buffed_len); //TODO: ALL OF THIS SHOULD PROBABLY BE MOVED ABOVE THE BEGINNING OF TIMING
/* create and run GPU threads */
readcmp<<<grid_size,threads_per_block,2*threads_per_block>>>(dev_test_array, dev_genome_1_data,
dev_genome_2_data,/* dev_result_data,*/ num_chars, buffed_len, vicinity,
tstride, dev_reduce_data, pop_thresh, threads_per_block, shift_amt);
gpuErrchk(cudaThreadSynchronize());
/* write the results back */
gpuErrchk(cudaMemcpy( reduce_data, dev_reduce_data,
num_genomes*sizeof(char), cudaMemcpyDeviceToHost ));
// conservative reduction debugging
gpuErrchk(cudaMemcpy( test_array, dev_test_array,
(num_chars + PAD_AMT) *sizeof(char), cudaMemcpyDeviceToHost ));
/*========================================================================*/
/****************/
/** END TIMING **/
/****************/
/* set stop time */
cudaEventRecord(stop,0);
cudaEventSynchronize( stop );
/* calculate elapsed time for GPU computation */
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("Time to complete comparison %1.4f ms\n", elapsedTime);
// Writing output pop count to file
// for data collection purposes
unsigned int matches=0;
for (unsigned int q=0; q<num_genomes; q++) {
if (reduce_data[q]==0)
matches++;
}
// conservative reduction debugging
int j = 0;
int bad_strings[num_genomes];
for(int i=0; i < num_genomes; i++)
bad_strings[i] = 0;
// find the bad strings
for(int i=0; i < num_genomes; i++){
if (reduce_data[i]!=0){
bad_strings[j] = i;
j++;
}
}
for(int i=0; i < num_genomes; i++){
if(bad_strings[i] != 0){
printf("genome number %d is a false negative\n", bad_strings[i]);
//printf("Original genome:\n");
for(int k=0; k < genome_len; k++){
printf("%c", genome_1_data[k + bad_strings[i]]);
}
printf("\n");
//printf("Edited genome:\n");
for(int k=0; k < genome_len; k++){
printf("%c", genome_2_data[k + bad_strings[i]]);
}
printf("\n");
}
}
// for(unsigned int i=0; i < num_chars + PAD_AMT; i++){
// printf("the test_array: %i\n", test_array[i]);
// }
pop_count_file = fopen("pop_output.txt","w");
fprintf(pop_count_file, "%d %d\n", matches, num_genomes-matches);
fclose(pop_count_file);
/* free and destroy all allocated information */
cudaFree(dev_genome_1_data);
cudaFree(dev_genome_2_data);
cudaFree(dev_reduce_data);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFreeHost(genome_1_data);
cudaFreeHost(genome_2_data);
cudaFreeHost(reduce_data);
}
/*
* Function - usage
*
* Description:
* Just prints the usage invariant for this program.
*/
void usage(void) {
printf("\nUsage:\n");
printf("\t./a.out <file_1> <file_2> <num_genomes> <genome_len> <errors> <vicinity> <adj_errs>\n\n");
}
/*
* Function - init_data
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow.
*/
int init_data(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
cudaHostAlloc((void**)data,num_chars*sizeof(char),cudaHostAllocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - init_data_pad
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow. It's
* the same as the above function except that it adds the PAD_AMT to
* to it.
*/
int init_data_pad(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
cudaHostAlloc((void**)data,(num_chars+PAD_AMT)*sizeof(char),cudaHostAllocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - read_data
*
* Arguments:
* data - the char* to which the data will be written
* file - the filae that contains the genomes we care about
* num_genomes - the numebr of genomed to read
* genome_len - the length of the genomes
* buffer_len - the length of the buffer at the end of each genome
* buffed_len - length of genome + buffer
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function reads in all of the genome data from the given genome
* file. Each line contains a genome read, and this is read into each
* string.
*/
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len,unsigned int vicinity) {
/* basic info and variables */
FILE* ifp; //ifp: "in file pointer"
char* mode = "r";
/* open the file */
ifp = fopen(file, mode);
if(NULL == ifp) {
printf("Can't open input file %s!\n", file);
return 1;
}
/* create read in buffer */
char* buf = (char*)malloc((genome_len+2)*sizeof(char));
/* initialize the padding at beginning of array */
for(int i = 0; i < PAD_AMT; i++) {
*(data + i) = BUFFER_CHAR;
}
int limit_len;
/* calculate the limit to which we will read data */
if (buffer_len < vicinity)
limit_len = buffed_len - vicinity;
else
limit_len = genome_len;
/* read in the file */
for(int i = 0; i < num_genomes; i++) {
if(NULL != fgets(buf, genome_len + 2, ifp)) {
for(int j = 0; j < limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + j) = buf[j];
}
for(int j = 0; j < buffed_len-limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + limit_len + j) = BUFFER_CHAR;
}
}
else {
printf("Failed to read from the file\n");
return 1;
}
}
/* close the file */
fclose(ifp);
free(buf);
return 0; //SUCCESS
}
/*
* Function - print_device_info
*
* Description:
* Prints valuable information out regarding the CUDA-capable devices
* in this system.
*/
void print_device_info(void) {
cudaDeviceProp prop;
int count;
cudaGetDeviceCount( &count );
for (int i=0; i< count; i++) {
cudaGetDeviceProperties( &prop, i );
printf( " --- General Information for device %d ---\n", i );
printf( "Name: %s\n", prop.name );
printf( "Compute capability: %d.%d\n", prop.major, prop.minor );
printf( "Clock rate: %d\n", prop.clockRate );
printf( "Device copy overlap: " );
if (prop.deviceOverlap)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "Kernel execition timeout : " );
if (prop.kernelExecTimeoutEnabled)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( " --- Memory Information for device %d ---\n", i );
printf( "Total global mem: %ld\n", prop.totalGlobalMem );
printf( "Total constant Mem: %ld\n", prop.totalConstMem );
printf( "Max mem pitch: %ld\n", prop.memPitch );
printf( "Texture Alignment: %ld\n", prop.textureAlignment );
printf( " --- MP Information for device %d ---\n", i );
printf( "Multiprocessor count: %d\n", prop.multiProcessorCount );
printf( "Shared mem per mp: %ld\n", prop.sharedMemPerBlock );
printf( "Registers per mp: %d\n", prop.regsPerBlock );
printf( "Threads in warp: %d\n", prop.warpSize );
printf( "Max threads per block: %d\n", prop.maxThreadsPerBlock );
printf( "Max thread dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2] );
printf( "Max grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2] );
printf( "\n" );
}
}
/*
* Function - next_power_2
*
* Arguments:
* v - the value for which we want to find the next power of 2
*
* Outputs:
* unsigned int - the next power of 2 greater than v
*
* Description:
* This code basically rounds v up to the next highest power of 2. So if
* v was 2, this function would return 2. If v was 15, this function would
* return 16. Etcetera.
*
* Source:
* http://graphics.stanford.edu/~seander/bithacks.html
*/
unsigned int next_power_2(unsigned int v) {
v--;
v |= v >> 1;
v |= v >> 2;
v |= v >> 4;
v |= v >> 8;
v |= v >> 16;
v++;
return v;
}
unsigned int log_2(unsigned int v) {
unsigned int r=0;
while (v >>= 1) // unroll for more speed...
{
r++;
}
return r;
} | .file "tmpxft_0017bdcf_00000000-6_introCUDA_injection_taylor_shift.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPcib,comdat
.weak _Z9gpuAssert9cudaErrorPcib
.type _Z9gpuAssert9cudaErrorPcib, @function
_Z9gpuAssert9cudaErrorPcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPcib, .-_Z9gpuAssert9cudaErrorPcib
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nUsage:\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\t./a.out <file_1> <file_2> <num_genomes> <genome_len> <errors> <vicinity> <adj_errs>\n\n"
.text
.globl _Z5usagev
.type _Z5usagev, @function
_Z5usagev:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z5usagev, .-_Z5usagev
.section .rodata.str1.1
.LC3:
.string "init_data - malloc failed\n"
.text
.globl _Z9init_dataPPcj
.type _Z9init_dataPPcj, @function
_Z9init_dataPPcj:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl %esi, %esi
movl $0, %edx
call cudaHostAlloc@PLT
movl $0, %eax
cmpq $0, (%rbx)
je .L17
.L13:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
jmp .L13
.cfi_endproc
.LFE2060:
.size _Z9init_dataPPcj, .-_Z9init_dataPPcj
.globl _Z13init_data_padPPcj
.type _Z13init_data_padPPcj, @function
_Z13init_data_padPPcj:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leal 5(%rsi), %esi
movl $0, %edx
call cudaHostAlloc@PLT
movl $0, %eax
cmpq $0, (%rbx)
je .L22
.L18:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
jmp .L18
.cfi_endproc
.LFE2061:
.size _Z13init_data_padPPcj, .-_Z13init_data_padPPcj
.section .rodata.str1.1
.LC4:
.string "r"
.LC5:
.string "Can't open input file %s!\n"
.LC6:
.string "Failed to read from the file\n"
.text
.globl _Z9read_dataPcS_jjjjj
.type _Z9read_dataPcS_jjjjj, @function
_Z9read_dataPcS_jjjjj:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r15
movq %rsi, %rbx
movl %edx, 16(%rsp)
movl %ecx, %ebp
movl %r8d, %r14d
movl %r9d, %r12d
movl 96(%rsp), %r13d
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call fopen@PLT
movq %rax, 8(%rsp)
testq %rax, %rax
je .L39
leal 2(%rbp), %eax
movl %eax, 20(%rsp)
movl %eax, %eax
movq %rax, 24(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbx
movb $65, (%r15)
movb $65, 1(%r15)
movb $65, 2(%r15)
movb $65, 3(%r15)
movb $65, 4(%r15)
movl %r12d, %eax
subl %r13d, %eax
cmpl %r13d, %r14d
cmovb %eax, %ebp
movl %ebp, %r13d
cmpl $0, 16(%rsp)
je .L28
movl $0, 4(%rsp)
movl $0, %r14d
movslq %ebp, %rbp
jmp .L34
.L39:
movq %rbx, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
jmp .L23
.L29:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L23
.L32:
addl $1, %r14d
addl %r12d, 4(%rsp)
movl 16(%rsp), %eax
cmpl %eax, %r14d
je .L28
.L34:
movq 8(%rsp), %rcx
movl 20(%rsp), %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call __fgets_chk@PLT
testq %rax, %rax
je .L29
testl %r13d, %r13d
jle .L30
movl 4(%rsp), %ecx
movl $0, %eax
addq %r15, %rcx
.L31:
movzbl (%rbx,%rax), %edx
movb %dl, 5(%rcx,%rax)
addq $1, %rax
cmpq %rax, %rbp
jne .L31
.L30:
movl %r12d, %ecx
subl %r13d, %ecx
cmpl %r13d, %r12d
je .L32
movl 4(%rsp), %eax
leaq 5(%rax,%rbp), %rdx
movl $0, %eax
addq %r15, %rdx
.L33:
movb $65, (%rdx,%rax)
addq $1, %rax
cmpl %ecx, %eax
jb .L33
jmp .L32
.L28:
movq 8(%rsp), %rdi
call fclose@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
.L23:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z9read_dataPcS_jjjjj, .-_Z9read_dataPcS_jjjjj
.section .rodata.str1.8
.align 8
.LC7:
.string " --- General Information for device %d ---\n"
.section .rodata.str1.1
.LC8:
.string "Name: %s\n"
.LC9:
.string "Compute capability: %d.%d\n"
.LC10:
.string "Clock rate: %d\n"
.LC11:
.string "Device copy overlap: "
.LC12:
.string "Enabled\n"
.LC13:
.string "Disabled\n"
.LC14:
.string "Kernel execition timeout : "
.section .rodata.str1.8
.align 8
.LC15:
.string " --- Memory Information for device %d ---\n"
.section .rodata.str1.1
.LC16:
.string "Total global mem: %ld\n"
.LC17:
.string "Total constant Mem: %ld\n"
.LC18:
.string "Max mem pitch: %ld\n"
.LC19:
.string "Texture Alignment: %ld\n"
.section .rodata.str1.8
.align 8
.LC20:
.string " --- MP Information for device %d ---\n"
.section .rodata.str1.1
.LC21:
.string "Multiprocessor count: %d\n"
.LC22:
.string "Shared mem per mp: %ld\n"
.LC23:
.string "Registers per mp: %d\n"
.LC24:
.string "Threads in warp: %d\n"
.LC25:
.string "Max threads per block: %d\n"
.section .rodata.str1.8
.align 8
.LC26:
.string "Max thread dimensions: (%d, %d, %d)\n"
.align 8
.LC27:
.string "Max grid dimensions: (%d, %d, %d)\n"
.section .rodata.str1.1
.LC28:
.string "\n"
.text
.globl _Z17print_device_infov
.type _Z17print_device_infov, @function
_Z17print_device_infov:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L40
movl $0, %ebx
leaq .LC7(%rip), %r15
leaq .LC8(%rip), %r14
leaq .LC9(%rip), %r13
leaq .LC10(%rip), %r12
jmp .L46
.L42:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L43
.L44:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L45:
movl %ebx, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L40
.L46:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 400(%rsp)
je .L42
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L43:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 408(%rsp)
je .L44
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L45
.L40:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z17print_device_infov, .-_Z17print_device_infov
.globl _Z12next_power_2j
.type _Z12next_power_2j, @function
_Z12next_power_2j:
.LFB2064:
.cfi_startproc
endbr64
subl $1, %edi
movl %edi, %eax
shrl %eax
orl %edi, %eax
movl %eax, %edi
shrl $2, %edi
orl %eax, %edi
movl %edi, %eax
shrl $4, %eax
orl %edi, %eax
movl %eax, %edx
shrl $8, %edx
orl %eax, %edx
movl %edx, %eax
shrl $16, %eax
orl %edx, %eax
addl $1, %eax
ret
.cfi_endproc
.LFE2064:
.size _Z12next_power_2j, .-_Z12next_power_2j
.globl _Z5log_2j
.type _Z5log_2j, @function
_Z5log_2j:
.LFB2065:
.cfi_startproc
endbr64
movl %edi, %eax
shrl %eax
je .L52
movl %eax, %edx
.L54:
shrl %edx
jne .L54
bsrl %eax, %edx
xorl $31, %edx
movl $32, %eax
subl %edx, %eax
.L52:
ret
.cfi_endproc
.LFE2065:
.size _Z5log_2j, .-_Z5log_2j
.globl _Z39__device_stub__Z7readcmpPcS_S_mjjjS_jjjPcS_S_mjjjS_jjj
.type _Z39__device_stub__Z7readcmpPcS_S_mjjjS_jjjPcS_S_mjjjS_jjj, @function
_Z39__device_stub__Z7readcmpPcS_S_mjjjS_jjjPcS_S_mjjjS_jjj:
.LFB2090:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq 232(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7readcmpPcS_S_mjjjS_jjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z39__device_stub__Z7readcmpPcS_S_mjjjS_jjjPcS_S_mjjjS_jjj, .-_Z39__device_stub__Z7readcmpPcS_S_mjjjS_jjjPcS_S_mjjjS_jjj
.globl _Z7readcmpPcS_S_mjjjS_jjj
.type _Z7readcmpPcS_S_mjjjS_jjj, @function
_Z7readcmpPcS_S_mjjjS_jjj:
.LFB2091:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z39__device_stub__Z7readcmpPcS_S_mjjjS_jjjPcS_S_mjjjS_jjj
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z7readcmpPcS_S_mjjjS_jjj, .-_Z7readcmpPcS_S_mjjjS_jjj
.section .rodata.str1.8
.align 8
.LC29:
.string "/home/ubuntu/Datasets/stackv2/train-structured/xhongyi/toybrick/master/cuda/740_cuda_twomack_nnuemah/introCUDA_injection_taylor_shift.cu"
.align 8
.LC30:
.string "Time to complete comparison %1.4f ms\n"
.align 8
.LC31:
.string "genome number %d is a false negative\n"
.section .rodata.str1.1
.LC32:
.string "%c"
.LC33:
.string "w"
.LC34:
.string "pop_output.txt"
.LC35:
.string "%d %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $184, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $8, %edi
je .L65
call _Z5usagev
movl $1, -164(%rbp)
.L64:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L94
movl -164(%rbp), %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L65:
.cfi_restore_state
movq %rsi, %rbx
movq 8(%rsi), %r14
movq 16(%rsi), %rax
movq %rax, -200(%rbp)
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, -168(%rbp)
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, -184(%rbp)
movl %eax, %r13d
movq 40(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, -216(%rbp)
movq 48(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, -192(%rbp)
movq 56(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, -208(%rbp)
movl %r13d, -176(%rbp)
movl %r13d, %edi
call _Z12next_power_2j
movl %eax, %r13d
movl %eax, %r12d
imull %r15d, %r12d
leaq -160(%rbp), %rdi
movl %r12d, %esi
call _Z13init_data_padPPcj
movl $1, -164(%rbp)
testl %eax, %eax
jne .L64
leaq -152(%rbp), %rdi
movl %r12d, %esi
call _Z13init_data_padPPcj
movl $1, -164(%rbp)
testl %eax, %eax
jne .L64
leaq -144(%rbp), %rdi
movl -168(%rbp), %ebx
movl %ebx, %esi
call _Z9init_dataPPcj
movl $1, -164(%rbp)
testl %eax, %eax
jne .L64
leal 5(%r12), %esi
leaq -136(%rbp), %rdi
call _Z9init_dataPPcj
movl $1, -164(%rbp)
testl %eax, %eax
jne .L64
movl %r13d, %ecx
movl -184(%rbp), %edx
subl %edx, %ecx
movl -192(%rbp), %edx
addl $1, %edx
subq $8, %rsp
movl %edx, -220(%rbp)
pushq %rdx
movl %r13d, %r9d
movl %ecx, -224(%rbp)
movl %ecx, %r8d
movl -176(%rbp), %ecx
movl %ebx, %edx
movq %r14, %rsi
movq -160(%rbp), %rdi
call _Z9read_dataPcS_jjjjj
addq $16, %rsp
movl $1, -164(%rbp)
testl %eax, %eax
jne .L64
subq $8, %rsp
movl -220(%rbp), %edx
pushq %rdx
movl %r13d, %r9d
movl -224(%rbp), %r8d
movl -176(%rbp), %ecx
movl %ebx, %edx
movq -200(%rbp), %rsi
movq -152(%rbp), %rdi
call _Z9read_dataPcS_jjjjj
movl %eax, -164(%rbp)
addq $16, %rsp
testl %eax, %eax
je .L95
movl $1, -164(%rbp)
jmp .L64
.L95:
movl %r12d, %ebx
leaq -128(%rbp), %rdi
call cudaEventCreate@PLT
leaq -120(%rbp), %rdi
call cudaEventCreate@PLT
leaq 5(%rbx), %r14
leaq -112(%rbp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $347, %edx
leaq .LC29(%rip), %r12
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPcib
leaq -104(%rbp), %rdi
movq %r14, -176(%rbp)
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $348, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl %r15d, %r14d
leaq -96(%rbp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $349, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPcib
leaq -88(%rbp), %rdi
movq -176(%rbp), %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $353, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $0, %esi
movq -128(%rbp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq -176(%rbp), %rdx
movq -160(%rbp), %rsi
movq -112(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $365, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $1, %ecx
movq -176(%rbp), %rdx
movq -152(%rbp), %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $367, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $1, %ecx
movq -176(%rbp), %rdx
movq -136(%rbp), %rsi
movq -88(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $371, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $128, -80(%rbp)
movl $128, -76(%rbp)
movl $1, -72(%rbp)
movl %r13d, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
leal (%r13,%r13), %r8d
movl $0, %r9d
movl %r8d, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L96
.L67:
call cudaThreadSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $386, %edx
leaq .LC29(%rip), %r12
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $2, %ecx
movq %r14, %rdx
movq -96(%rbp), %rsi
movq -144(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $389, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $2, %ecx
movq -176(%rbp), %rdx
movq -88(%rbp), %rsi
movq -136(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $393, %edx
movq %r12, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $0, %esi
movq -120(%rbp), %rdi
call cudaEventRecord@PLT
movq -120(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -68(%rbp), %rdi
movq -120(%rbp), %rdx
movq -128(%rbp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd -68(%rbp), %xmm0
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -144(%rbp), %rdx
movl $0, %eax
movl $0, %r13d
movl -168(%rbp), %ecx
jmp .L68
.L96:
subq $8, %rsp
movl -208(%rbp), %eax
pushq %rax
pushq %r13
movl -216(%rbp), %eax
pushq %rax
pushq -96(%rbp)
movl %r13d, %eax
sall $14, %eax
pushq %rax
movl -192(%rbp), %r9d
movl %r13d, %r8d
movq %rbx, %rcx
movq -104(%rbp), %rdx
movq -112(%rbp), %rsi
movq -88(%rbp), %rdi
call _Z39__device_stub__Z7readcmpPcS_S_mjjjS_jjjPcS_S_mjjjS_jjj
addq $48, %rsp
jmp .L67
.L69:
addq $1, %rax
.L68:
cmpl %ecx, %eax
jnb .L97
cmpb $0, (%rdx,%rax)
jne .L69
addl $1, %r13d
jmp .L69
.L97:
leaq 15(,%r14,4), %rax
shrq $4, %rax
salq $4, %rax
movq %rax, %rsi
andq $-4096, %rsi
movq %rsp, %rcx
subq %rsi, %rcx
.L71:
cmpq %rcx, %rsp
je .L72
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L71
.L72:
movq %rax, %rcx
andl $4095, %ecx
subq %rcx, %rsp
testq %rcx, %rcx
je .L73
orq $0, -8(%rsp,%rcx)
.L73:
movq %rsp, %rsi
movq %rsi, -176(%rbp)
movl $0, %eax
movl -168(%rbp), %ecx
jmp .L74
.L75:
movl $0, (%rsi,%rax,4)
addq $1, %rax
.L74:
cmpl %ecx, %eax
jb .L75
movl -164(%rbp), %ecx
movl $0, %eax
movl -168(%rbp), %esi
movq -176(%rbp), %r8
jmp .L76
.L77:
addq $1, %rax
.L76:
cmpl %esi, %eax
jnb .L98
cmpb $0, (%rdx,%rax)
je .L77
movslq %ecx, %rdi
movl %eax, (%r8,%rdi,4)
addl $1, %ecx
jmp .L77
.L98:
movl $0, %r14d
movl %r13d, -192(%rbp)
movq %r15, -200(%rbp)
movl -168(%rbp), %r15d
jmp .L79
.L82:
movq -160(%rbp), %rax
movsbl (%rax,%r12), %edx
leaq .LC32(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r12
.L81:
cmpq %r13, %r12
jne .L82
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L83
.L84:
movq -152(%rbp), %rax
movsbl (%rax,%rbx), %edx
leaq .LC32(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
.L83:
cmpq %r12, %rbx
jne .L84
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L80:
addq $1, %r14
.L79:
cmpl %r15d, %r14d
jnb .L99
movq -176(%rbp), %rax
movl (%rax,%r14,4), %ebx
testl %ebx, %ebx
je .L80
movl %ebx, %edx
leaq .LC31(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rbx
movl -184(%rbp), %r13d
addq %rbx, %r13
movq %rbx, %r12
jmp .L81
.L99:
movl -192(%rbp), %r13d
movq -200(%rbp), %r15
leaq .LC33(%rip), %rsi
leaq .LC34(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movl %r15d, %r8d
subl %r13d, %r8d
movl %r13d, %ecx
leaq .LC35(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r12, %rdi
call fclose@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -128(%rbp), %rdi
call cudaEventDestroy@PLT
movq -120(%rbp), %rdi
call cudaEventDestroy@PLT
movq -160(%rbp), %rdi
call cudaFreeHost@PLT
movq -152(%rbp), %rdi
call cudaFreeHost@PLT
movq -144(%rbp), %rdi
call cudaFreeHost@PLT
jmp .L64
.L94:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.globl _Z31__device_stub__Z6reducePcS_mjjjPcS_mjjj
.type _Z31__device_stub__Z6reducePcS_mjjjPcS_mjjj, @function
_Z31__device_stub__Z6reducePcS_mjjjPcS_mjjj:
.LFB2092:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L104
.L100:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L105
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L104:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6reducePcS_mjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L100
.L105:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z31__device_stub__Z6reducePcS_mjjjPcS_mjjj, .-_Z31__device_stub__Z6reducePcS_mjjjPcS_mjjj
.globl _Z6reducePcS_mjjj
.type _Z6reducePcS_mjjj, @function
_Z6reducePcS_mjjj:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6reducePcS_mjjjPcS_mjjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z6reducePcS_mjjj, .-_Z6reducePcS_mjjj
.section .rodata.str1.1
.LC36:
.string "_Z6reducePcS_mjjj"
.LC37:
.string "_Z7readcmpPcS_S_mjjjS_jjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC36(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducePcS_mjjj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC37(%rip), %rdx
movq %rdx, %rcx
leaq _Z7readcmpPcS_S_mjjjS_jjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <string.h>
#include <cuda.h>
/*********************************/
/** constants/define statements **/
/*********************************/
#define THREADS_PER_BLOCK 1024
#define MAX_BLOCKS 65535
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
#define BUFFER_CHAR 'A'
#define PAD_AMT 5
/**********************/
/** function headers **/
/**********************/
void usage(void);
int init_data(char** data, unsigned int num_chars);
int init_data_pad(char** data, unsigned int num_chars);
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len, unsigned int vicinity);
void free_data(char* data, unsigned int num_genomes);
__global__ void readcmp(char* a, char* b, /*char* result,*/
unsigned long nthreads, unsigned int str_len,
unsigned int vicinity, unsigned int tstride,
char *reduce, unsigned int pop_thresh,
unsigned int threads_per_block,
unsigned int shift_amt);
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads,
unsigned int str_len, unsigned int pop_thresh,
unsigned int tstride);
void print_device_info(void);
unsigned int next_power_2(unsigned int v);
unsigned int log_2(unsigned int v);
/***************/
/** functions **/
/***************/
/*
* Function - gpuAssert
*
* Inputs:
* code - gpu error code
* file - current source file
* line - line within this file
* abort - if true, the prgram aborts
*
* Description:
* This function checks the cuda error code, and aborts if it is not a
* success.
*/
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n",cudaGetErrorString(code),file,line);
if (abort) exit(code);
}
}
/*
* Kernel - readcmp
*
* Inputs:
* a - a pointer to one read
* b - a pointer to the other read
* nthreads - the maximum number of threads used
* str_len - the length of the reads to be compared (this is a power of 2)
* vicinity - the bit-flip vicinity
* tstride - the read index stride distance for each thread
* pop_thresh - the pop count threshold
* thread_per_block - the number of threads per block
* shift_amt - the maximum shift amount between the reads
*
* Outputs:
* reduce - the array returned which contains 0 for "reads match" or 1 for
* "reads don't match"
*
* Description:
* This Kernel does two things: for each pair of reads, it compares the
* characters and stores the bit-op results. It then performas a sum
* reduction on each read comparison and checks if it is above the edit
* threshold.
*/
__global__ void readcmp(char *dev_test_array, char *a, char *b, /*char *result,*/ unsigned long nthreads, unsigned int str_len, unsigned int vicinity, unsigned int tstride, char *reduce, unsigned int pop_thresh, unsigned int threads_per_block, unsigned int shift_amt) {
// Set up shared memory
extern __shared__ char shared_data[];
char* sdata = (char *)shared_data;
char* result = (char *)&shared_data[threads_per_block];
// Find index of this thread
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long tid = x + y * blockDim.x * gridDim.x;
unsigned long i = threadIdx.x; //local block tid
int j, k;
while(tid < nthreads) {
//make the first xor comparison without shifting
result[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT];
__syncthreads();
//check the vicinity for 100...01
if (result[i]!=0) {
for (j=1; j<vicinity; j++) {
if(result[i+j]!=0)
break;
}
if (result[i+j]!=0) {
for (k=1; k<j; k++) {
result[i+k]=0xff;
}
}
}
//make the remaining xor comparisons with shifting up until the limit
for(unsigned int cur_shift = 1; cur_shift <= shift_amt; cur_shift++) {
__syncthreads();
sdata[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT-cur_shift]; //shift b left
__syncthreads();
//check vicinity
if (sdata[i] != 0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
//AND result
__syncthreads();
result[i] = result[i] && sdata[i];
sdata[i] = b[tid+PAD_AMT] ^ a[tid+PAD_AMT-cur_shift]; //shift a left
__syncthreads();
//check vicinity
if (sdata[i]!=0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
//AND result
__syncthreads();
result[i] = result[i] && sdata[i];
__syncthreads();
}
/////////////////////////////////////////////////////////////////////
// the code below is used for the sum reduce
/////////////////////////////////////////////////////////////////////
sdata[i] = result[i];
__syncthreads();
/*
* conservative reduction implemented by John Emmons Feb. 2014
* EX. if vicinity = 3 then 111100110111111 -> 100100110100101
*/
if(sdata[i] != 0 && (i == 0 || sdata[i-1] == 0)){
int m, n = i;
bool flag = true;
while(true){
for(m = 1; m < vicinity + 1; m++){
if(n + m < str_len) {
if(sdata[n + m] != 0){ continue; }
else if(m < 2){ flag = false; break; }
else{ break; }
}
else{
if(m < 2){ flag = false; break; }
else{ break; }
}
}
if(flag){
for(m -= 2; m > 0; m--)
sdata[n + m] = 0x00;
n += vicinity;
}
else{ break; }
}
}
__syncthreads();
// conservative reduction debugging
dev_test_array[i] = sdata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
if(i < s) {
sdata[i] += sdata[i + s];
}
__syncthreads();
}
__syncthreads();
// write result for this block to global mem
if(i%str_len == 0) {
reduce[tid/str_len] = (sdata[i]<=pop_thresh)?0:1;
}
///////////////////////////////////////////////////////////////////////
__syncthreads();
tid += tstride; //increase tid by thread stride amount
}
}
/*********************************/
/** THIS FUNCTION IS DEPRECATED **/
/*********************************/
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads, unsigned int str_len, unsigned int pop_thresh, unsigned int tstride) {
extern __shared__ char sdata[];
// each thread loads one element from global to shared mem
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long i = x + y * blockDim.x * gridDim.x; //global tid
unsigned int tid = threadIdx.x; //local block tid
while(i < nthreads) {
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
if (tid<s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid%str_len == 0) {
g_odata[i/str_len] = (sdata[tid]<=pop_thresh)?1:0;
g_odata[i/str_len] = sdata[tid];
}
i += tstride;
}
}
/*
* Function - main
*
* Arguments:
* argc - the number of command line arguments
* argv - an array of the command line arguments
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This is the main function. It initializes memory. It reads in the
* files which contain the reads. It, then, launches the kernel on
* the GPU.
*/
int main(int argc, char *argv[]) {
/* check the number of command line arguments */
if(argc != 8) {
usage();
return 1;
}
/* get arguments */
char* file_1;
char* file_2;
unsigned int num_genomes, genome_len, buffed_len,
buffer_len, vicinity, errors, pop_thresh, shift_amt;
FILE *pop_count_file;
file_1 = argv[1]; //contains reads
file_2 = argv[2]; //contains reads
num_genomes = atoi(argv[3]); //the number of reads in each file
genome_len = atoi(argv[4]); //the length of each read
errors = atoi(argv[5]); //the number of edits allowed between two reads
vicinity = atoi(argv[6]); //the vicinity for bit flips
shift_amt = atoi(argv[7]); //the maximum shift amount when comparing reads
/* calculate important values */
pop_thresh = /*(vicinity-1)*(errors-1) +*/ errors; //popcount threshold (is simply the num of allowed errors with conservative reduction)
buffed_len = next_power_2(genome_len); //genome length + buffer space
buffer_len = buffed_len - genome_len; //difference bw genome len and buf len
unsigned long num_chars = num_genomes*buffed_len; //the total number of chars in every buffed read
/* initialize and allocate strings to compare */
char* genome_1_data; //first genome data
char* genome_2_data; //second genome data
char* reduce_data; //sum of "errors" in each string
if(init_data_pad(&genome_1_data, num_chars)) return 1;
if(init_data_pad(&genome_2_data, num_chars)) return 1;
if(init_data(&reduce_data, num_genomes)) return 1;
// conservative reduction debugging
char* test_array;
if(init_data(&test_array, num_chars+PAD_AMT)) return 1;
/* read in the data */
if(read_data(genome_1_data, file_1, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
if(read_data(genome_2_data, file_2, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
/* create timing events */
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
/* initialize and allocate memoer for GPU input and output arrays */
char *dev_genome_1_data;
char *dev_genome_2_data;
char *dev_reduce_data;
gpuErrchk( cudaMalloc((void**)&dev_genome_1_data, (num_chars+PAD_AMT)*sizeof(char)));
gpuErrchk( cudaMalloc((void**)&dev_genome_2_data, (num_chars+PAD_AMT)*sizeof(char)));
gpuErrchk( cudaMalloc((void**)&dev_reduce_data, num_genomes*sizeof(char) ));
// conservative reduction debugging
char *dev_test_array;
gpuErrchk( cudaMalloc((void**)&dev_test_array, (num_chars+PAD_AMT)*sizeof(char) ));
/******************/
/** START TIMING **/
/******************/
/*========================================================================*/
/* set start time */
cudaEventRecord(start, 0);
/* copy data to GPU */
gpuErrchk(cudaMemcpy( dev_genome_1_data, genome_1_data,
(num_chars+PAD_AMT)*sizeof(char), cudaMemcpyHostToDevice ));
gpuErrchk(cudaMemcpy( dev_genome_2_data, genome_2_data,
(num_chars+PAD_AMT)*sizeof(char), cudaMemcpyHostToDevice ));
// conservative reduction debugging
gpuErrchk(cudaMemcpy( dev_test_array, test_array,
(num_chars+PAD_AMT)*sizeof(char), cudaMemcpyHostToDevice ));
/* figure out thread count and dimensions for GPU */
unsigned int num_blocks_x = 128;
unsigned int num_blocks_y = 128;
unsigned int threads_per_block = buffed_len;
unsigned int tstride = threads_per_block*num_blocks_x*num_blocks_y;
dim3 grid_size(num_blocks_x, num_blocks_y, 1);
unsigned int log_len = log_2(buffed_len); //TODO: ALL OF THIS SHOULD PROBABLY BE MOVED ABOVE THE BEGINNING OF TIMING
/* create and run GPU threads */
readcmp<<<grid_size,threads_per_block,2*threads_per_block>>>(dev_test_array, dev_genome_1_data,
dev_genome_2_data,/* dev_result_data,*/ num_chars, buffed_len, vicinity,
tstride, dev_reduce_data, pop_thresh, threads_per_block, shift_amt);
gpuErrchk(cudaThreadSynchronize());
/* write the results back */
gpuErrchk(cudaMemcpy( reduce_data, dev_reduce_data,
num_genomes*sizeof(char), cudaMemcpyDeviceToHost ));
// conservative reduction debugging
gpuErrchk(cudaMemcpy( test_array, dev_test_array,
(num_chars + PAD_AMT) *sizeof(char), cudaMemcpyDeviceToHost ));
/*========================================================================*/
/****************/
/** END TIMING **/
/****************/
/* set stop time */
cudaEventRecord(stop,0);
cudaEventSynchronize( stop );
/* calculate elapsed time for GPU computation */
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
printf("Time to complete comparison %1.4f ms\n", elapsedTime);
// Writing output pop count to file
// for data collection purposes
unsigned int matches=0;
for (unsigned int q=0; q<num_genomes; q++) {
if (reduce_data[q]==0)
matches++;
}
// conservative reduction debugging
int j = 0;
int bad_strings[num_genomes];
for(int i=0; i < num_genomes; i++)
bad_strings[i] = 0;
// find the bad strings
for(int i=0; i < num_genomes; i++){
if (reduce_data[i]!=0){
bad_strings[j] = i;
j++;
}
}
for(int i=0; i < num_genomes; i++){
if(bad_strings[i] != 0){
printf("genome number %d is a false negative\n", bad_strings[i]);
//printf("Original genome:\n");
for(int k=0; k < genome_len; k++){
printf("%c", genome_1_data[k + bad_strings[i]]);
}
printf("\n");
//printf("Edited genome:\n");
for(int k=0; k < genome_len; k++){
printf("%c", genome_2_data[k + bad_strings[i]]);
}
printf("\n");
}
}
// for(unsigned int i=0; i < num_chars + PAD_AMT; i++){
// printf("the test_array: %i\n", test_array[i]);
// }
pop_count_file = fopen("pop_output.txt","w");
fprintf(pop_count_file, "%d %d\n", matches, num_genomes-matches);
fclose(pop_count_file);
/* free and destroy all allocated information */
cudaFree(dev_genome_1_data);
cudaFree(dev_genome_2_data);
cudaFree(dev_reduce_data);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFreeHost(genome_1_data);
cudaFreeHost(genome_2_data);
cudaFreeHost(reduce_data);
}
/*
* Function - usage
*
* Description:
* Just prints the usage invariant for this program.
*/
void usage(void) {
printf("\nUsage:\n");
printf("\t./a.out <file_1> <file_2> <num_genomes> <genome_len> <errors> <vicinity> <adj_errs>\n\n");
}
/*
* Function - init_data
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow.
*/
int init_data(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
cudaHostAlloc((void**)data,num_chars*sizeof(char),cudaHostAllocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - init_data_pad
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow. It's
* the same as the above function except that it adds the PAD_AMT to
* to it.
*/
int init_data_pad(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
cudaHostAlloc((void**)data,(num_chars+PAD_AMT)*sizeof(char),cudaHostAllocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - read_data
*
* Arguments:
* data - the char* to which the data will be written
* file - the filae that contains the genomes we care about
* num_genomes - the numebr of genomed to read
* genome_len - the length of the genomes
* buffer_len - the length of the buffer at the end of each genome
* buffed_len - length of genome + buffer
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function reads in all of the genome data from the given genome
* file. Each line contains a genome read, and this is read into each
* string.
*/
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len,unsigned int vicinity) {
/* basic info and variables */
FILE* ifp; //ifp: "in file pointer"
char* mode = "r";
/* open the file */
ifp = fopen(file, mode);
if(NULL == ifp) {
printf("Can't open input file %s!\n", file);
return 1;
}
/* create read in buffer */
char* buf = (char*)malloc((genome_len+2)*sizeof(char));
/* initialize the padding at beginning of array */
for(int i = 0; i < PAD_AMT; i++) {
*(data + i) = BUFFER_CHAR;
}
int limit_len;
/* calculate the limit to which we will read data */
if (buffer_len < vicinity)
limit_len = buffed_len - vicinity;
else
limit_len = genome_len;
/* read in the file */
for(int i = 0; i < num_genomes; i++) {
if(NULL != fgets(buf, genome_len + 2, ifp)) {
for(int j = 0; j < limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + j) = buf[j];
}
for(int j = 0; j < buffed_len-limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + limit_len + j) = BUFFER_CHAR;
}
}
else {
printf("Failed to read from the file\n");
return 1;
}
}
/* close the file */
fclose(ifp);
free(buf);
return 0; //SUCCESS
}
/*
* Function - print_device_info
*
* Description:
* Prints valuable information out regarding the CUDA-capable devices
* in this system.
*/
void print_device_info(void) {
cudaDeviceProp prop;
int count;
cudaGetDeviceCount( &count );
for (int i=0; i< count; i++) {
cudaGetDeviceProperties( &prop, i );
printf( " --- General Information for device %d ---\n", i );
printf( "Name: %s\n", prop.name );
printf( "Compute capability: %d.%d\n", prop.major, prop.minor );
printf( "Clock rate: %d\n", prop.clockRate );
printf( "Device copy overlap: " );
if (prop.deviceOverlap)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "Kernel execition timeout : " );
if (prop.kernelExecTimeoutEnabled)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( " --- Memory Information for device %d ---\n", i );
printf( "Total global mem: %ld\n", prop.totalGlobalMem );
printf( "Total constant Mem: %ld\n", prop.totalConstMem );
printf( "Max mem pitch: %ld\n", prop.memPitch );
printf( "Texture Alignment: %ld\n", prop.textureAlignment );
printf( " --- MP Information for device %d ---\n", i );
printf( "Multiprocessor count: %d\n", prop.multiProcessorCount );
printf( "Shared mem per mp: %ld\n", prop.sharedMemPerBlock );
printf( "Registers per mp: %d\n", prop.regsPerBlock );
printf( "Threads in warp: %d\n", prop.warpSize );
printf( "Max threads per block: %d\n", prop.maxThreadsPerBlock );
printf( "Max thread dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2] );
printf( "Max grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2] );
printf( "\n" );
}
}
/*
* Function - next_power_2
*
* Arguments:
* v - the value for which we want to find the next power of 2
*
* Outputs:
* unsigned int - the next power of 2 greater than v
*
* Description:
* This code basically rounds v up to the next highest power of 2. So if
* v was 2, this function would return 2. If v was 15, this function would
* return 16. Etcetera.
*
* Source:
* http://graphics.stanford.edu/~seander/bithacks.html
*/
unsigned int next_power_2(unsigned int v) {
v--;
v |= v >> 1;
v |= v >> 2;
v |= v >> 4;
v |= v >> 8;
v |= v >> 16;
v++;
return v;
}
unsigned int log_2(unsigned int v) {
unsigned int r=0;
while (v >>= 1) // unroll for more speed...
{
r++;
}
return r;
} | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <string.h>
#include <hip/hip_runtime.h>
/*********************************/
/** constants/define statements **/
/*********************************/
#define THREADS_PER_BLOCK 1024
#define MAX_BLOCKS 65535
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
#define BUFFER_CHAR 'A'
#define PAD_AMT 5
/**********************/
/** function headers **/
/**********************/
void usage(void);
int init_data(char** data, unsigned int num_chars);
int init_data_pad(char** data, unsigned int num_chars);
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len, unsigned int vicinity);
void free_data(char* data, unsigned int num_genomes);
__global__ void readcmp(char* a, char* b, /*char* result,*/
unsigned long nthreads, unsigned int str_len,
unsigned int vicinity, unsigned int tstride,
char *reduce, unsigned int pop_thresh,
unsigned int threads_per_block,
unsigned int shift_amt);
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads,
unsigned int str_len, unsigned int pop_thresh,
unsigned int tstride);
void print_device_info(void);
unsigned int next_power_2(unsigned int v);
unsigned int log_2(unsigned int v);
/***************/
/** functions **/
/***************/
/*
* Function - gpuAssert
*
* Inputs:
* code - gpu error code
* file - current source file
* line - line within this file
* abort - if true, the prgram aborts
*
* Description:
* This function checks the cuda error code, and aborts if it is not a
* success.
*/
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n",hipGetErrorString(code),file,line);
if (abort) exit(code);
}
}
/*
* Kernel - readcmp
*
* Inputs:
* a - a pointer to one read
* b - a pointer to the other read
* nthreads - the maximum number of threads used
* str_len - the length of the reads to be compared (this is a power of 2)
* vicinity - the bit-flip vicinity
* tstride - the read index stride distance for each thread
* pop_thresh - the pop count threshold
* thread_per_block - the number of threads per block
* shift_amt - the maximum shift amount between the reads
*
* Outputs:
* reduce - the array returned which contains 0 for "reads match" or 1 for
* "reads don't match"
*
* Description:
* This Kernel does two things: for each pair of reads, it compares the
* characters and stores the bit-op results. It then performas a sum
* reduction on each read comparison and checks if it is above the edit
* threshold.
*/
__global__ void readcmp(char *dev_test_array, char *a, char *b, /*char *result,*/ unsigned long nthreads, unsigned int str_len, unsigned int vicinity, unsigned int tstride, char *reduce, unsigned int pop_thresh, unsigned int threads_per_block, unsigned int shift_amt) {
// Set up shared memory
extern __shared__ char shared_data[];
char* sdata = (char *)shared_data;
char* result = (char *)&shared_data[threads_per_block];
// Find index of this thread
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long tid = x + y * blockDim.x * gridDim.x;
unsigned long i = threadIdx.x; //local block tid
int j, k;
while(tid < nthreads) {
//make the first xor comparison without shifting
result[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT];
__syncthreads();
//check the vicinity for 100...01
if (result[i]!=0) {
for (j=1; j<vicinity; j++) {
if(result[i+j]!=0)
break;
}
if (result[i+j]!=0) {
for (k=1; k<j; k++) {
result[i+k]=0xff;
}
}
}
//make the remaining xor comparisons with shifting up until the limit
for(unsigned int cur_shift = 1; cur_shift <= shift_amt; cur_shift++) {
__syncthreads();
sdata[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT-cur_shift]; //shift b left
__syncthreads();
//check vicinity
if (sdata[i] != 0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
//AND result
__syncthreads();
result[i] = result[i] && sdata[i];
sdata[i] = b[tid+PAD_AMT] ^ a[tid+PAD_AMT-cur_shift]; //shift a left
__syncthreads();
//check vicinity
if (sdata[i]!=0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
//AND result
__syncthreads();
result[i] = result[i] && sdata[i];
__syncthreads();
}
/////////////////////////////////////////////////////////////////////
// the code below is used for the sum reduce
/////////////////////////////////////////////////////////////////////
sdata[i] = result[i];
__syncthreads();
/*
* conservative reduction implemented by John Emmons Feb. 2014
* EX. if vicinity = 3 then 111100110111111 -> 100100110100101
*/
if(sdata[i] != 0 && (i == 0 || sdata[i-1] == 0)){
int m, n = i;
bool flag = true;
while(true){
for(m = 1; m < vicinity + 1; m++){
if(n + m < str_len) {
if(sdata[n + m] != 0){ continue; }
else if(m < 2){ flag = false; break; }
else{ break; }
}
else{
if(m < 2){ flag = false; break; }
else{ break; }
}
}
if(flag){
for(m -= 2; m > 0; m--)
sdata[n + m] = 0x00;
n += vicinity;
}
else{ break; }
}
}
__syncthreads();
// conservative reduction debugging
dev_test_array[i] = sdata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
if(i < s) {
sdata[i] += sdata[i + s];
}
__syncthreads();
}
__syncthreads();
// write result for this block to global mem
if(i%str_len == 0) {
reduce[tid/str_len] = (sdata[i]<=pop_thresh)?0:1;
}
///////////////////////////////////////////////////////////////////////
__syncthreads();
tid += tstride; //increase tid by thread stride amount
}
}
/*********************************/
/** THIS FUNCTION IS DEPRECATED **/
/*********************************/
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads, unsigned int str_len, unsigned int pop_thresh, unsigned int tstride) {
extern __shared__ char sdata[];
// each thread loads one element from global to shared mem
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long i = x + y * blockDim.x * gridDim.x; //global tid
unsigned int tid = threadIdx.x; //local block tid
while(i < nthreads) {
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
if (tid<s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid%str_len == 0) {
g_odata[i/str_len] = (sdata[tid]<=pop_thresh)?1:0;
g_odata[i/str_len] = sdata[tid];
}
i += tstride;
}
}
/*
* Function - main
*
* Arguments:
* argc - the number of command line arguments
* argv - an array of the command line arguments
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This is the main function. It initializes memory. It reads in the
* files which contain the reads. It, then, launches the kernel on
* the GPU.
*/
int main(int argc, char *argv[]) {
/* check the number of command line arguments */
if(argc != 8) {
usage();
return 1;
}
/* get arguments */
char* file_1;
char* file_2;
unsigned int num_genomes, genome_len, buffed_len,
buffer_len, vicinity, errors, pop_thresh, shift_amt;
FILE *pop_count_file;
file_1 = argv[1]; //contains reads
file_2 = argv[2]; //contains reads
num_genomes = atoi(argv[3]); //the number of reads in each file
genome_len = atoi(argv[4]); //the length of each read
errors = atoi(argv[5]); //the number of edits allowed between two reads
vicinity = atoi(argv[6]); //the vicinity for bit flips
shift_amt = atoi(argv[7]); //the maximum shift amount when comparing reads
/* calculate important values */
pop_thresh = /*(vicinity-1)*(errors-1) +*/ errors; //popcount threshold (is simply the num of allowed errors with conservative reduction)
buffed_len = next_power_2(genome_len); //genome length + buffer space
buffer_len = buffed_len - genome_len; //difference bw genome len and buf len
unsigned long num_chars = num_genomes*buffed_len; //the total number of chars in every buffed read
/* initialize and allocate strings to compare */
char* genome_1_data; //first genome data
char* genome_2_data; //second genome data
char* reduce_data; //sum of "errors" in each string
if(init_data_pad(&genome_1_data, num_chars)) return 1;
if(init_data_pad(&genome_2_data, num_chars)) return 1;
if(init_data(&reduce_data, num_genomes)) return 1;
// conservative reduction debugging
char* test_array;
if(init_data(&test_array, num_chars+PAD_AMT)) return 1;
/* read in the data */
if(read_data(genome_1_data, file_1, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
if(read_data(genome_2_data, file_2, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
/* create timing events */
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
/* initialize and allocate memoer for GPU input and output arrays */
char *dev_genome_1_data;
char *dev_genome_2_data;
char *dev_reduce_data;
gpuErrchk( hipMalloc((void**)&dev_genome_1_data, (num_chars+PAD_AMT)*sizeof(char)));
gpuErrchk( hipMalloc((void**)&dev_genome_2_data, (num_chars+PAD_AMT)*sizeof(char)));
gpuErrchk( hipMalloc((void**)&dev_reduce_data, num_genomes*sizeof(char) ));
// conservative reduction debugging
char *dev_test_array;
gpuErrchk( hipMalloc((void**)&dev_test_array, (num_chars+PAD_AMT)*sizeof(char) ));
/******************/
/** START TIMING **/
/******************/
/*========================================================================*/
/* set start time */
hipEventRecord(start, 0);
/* copy data to GPU */
gpuErrchk(hipMemcpy( dev_genome_1_data, genome_1_data,
(num_chars+PAD_AMT)*sizeof(char), hipMemcpyHostToDevice ));
gpuErrchk(hipMemcpy( dev_genome_2_data, genome_2_data,
(num_chars+PAD_AMT)*sizeof(char), hipMemcpyHostToDevice ));
// conservative reduction debugging
gpuErrchk(hipMemcpy( dev_test_array, test_array,
(num_chars+PAD_AMT)*sizeof(char), hipMemcpyHostToDevice ));
/* figure out thread count and dimensions for GPU */
unsigned int num_blocks_x = 128;
unsigned int num_blocks_y = 128;
unsigned int threads_per_block = buffed_len;
unsigned int tstride = threads_per_block*num_blocks_x*num_blocks_y;
dim3 grid_size(num_blocks_x, num_blocks_y, 1);
unsigned int log_len = log_2(buffed_len); //TODO: ALL OF THIS SHOULD PROBABLY BE MOVED ABOVE THE BEGINNING OF TIMING
/* create and run GPU threads */
readcmp<<<grid_size,threads_per_block,2*threads_per_block>>>(dev_test_array, dev_genome_1_data,
dev_genome_2_data,/* dev_result_data,*/ num_chars, buffed_len, vicinity,
tstride, dev_reduce_data, pop_thresh, threads_per_block, shift_amt);
gpuErrchk(hipDeviceSynchronize());
/* write the results back */
gpuErrchk(hipMemcpy( reduce_data, dev_reduce_data,
num_genomes*sizeof(char), hipMemcpyDeviceToHost ));
// conservative reduction debugging
gpuErrchk(hipMemcpy( test_array, dev_test_array,
(num_chars + PAD_AMT) *sizeof(char), hipMemcpyDeviceToHost ));
/*========================================================================*/
/****************/
/** END TIMING **/
/****************/
/* set stop time */
hipEventRecord(stop,0);
hipEventSynchronize( stop );
/* calculate elapsed time for GPU computation */
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("Time to complete comparison %1.4f ms\n", elapsedTime);
// Writing output pop count to file
// for data collection purposes
unsigned int matches=0;
for (unsigned int q=0; q<num_genomes; q++) {
if (reduce_data[q]==0)
matches++;
}
// conservative reduction debugging
int j = 0;
int bad_strings[num_genomes];
for(int i=0; i < num_genomes; i++)
bad_strings[i] = 0;
// find the bad strings
for(int i=0; i < num_genomes; i++){
if (reduce_data[i]!=0){
bad_strings[j] = i;
j++;
}
}
for(int i=0; i < num_genomes; i++){
if(bad_strings[i] != 0){
printf("genome number %d is a false negative\n", bad_strings[i]);
//printf("Original genome:\n");
for(int k=0; k < genome_len; k++){
printf("%c", genome_1_data[k + bad_strings[i]]);
}
printf("\n");
//printf("Edited genome:\n");
for(int k=0; k < genome_len; k++){
printf("%c", genome_2_data[k + bad_strings[i]]);
}
printf("\n");
}
}
// for(unsigned int i=0; i < num_chars + PAD_AMT; i++){
// printf("the test_array: %i\n", test_array[i]);
// }
pop_count_file = fopen("pop_output.txt","w");
fprintf(pop_count_file, "%d %d\n", matches, num_genomes-matches);
fclose(pop_count_file);
/* free and destroy all allocated information */
hipFree(dev_genome_1_data);
hipFree(dev_genome_2_data);
hipFree(dev_reduce_data);
hipEventDestroy(start);
hipEventDestroy(stop);
hipHostFree(genome_1_data);
hipHostFree(genome_2_data);
hipHostFree(reduce_data);
}
/*
* Function - usage
*
* Description:
* Just prints the usage invariant for this program.
*/
void usage(void) {
printf("\nUsage:\n");
printf("\t./a.out <file_1> <file_2> <num_genomes> <genome_len> <errors> <vicinity> <adj_errs>\n\n");
}
/*
* Function - init_data
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow.
*/
int init_data(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
hipHostAlloc((void**)data,num_chars*sizeof(char),hipHostMallocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - init_data_pad
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow. It's
* the same as the above function except that it adds the PAD_AMT to
* to it.
*/
int init_data_pad(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
hipHostAlloc((void**)data,(num_chars+PAD_AMT)*sizeof(char),hipHostMallocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - read_data
*
* Arguments:
* data - the char* to which the data will be written
* file - the filae that contains the genomes we care about
* num_genomes - the numebr of genomed to read
* genome_len - the length of the genomes
* buffer_len - the length of the buffer at the end of each genome
* buffed_len - length of genome + buffer
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function reads in all of the genome data from the given genome
* file. Each line contains a genome read, and this is read into each
* string.
*/
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len,unsigned int vicinity) {
/* basic info and variables */
FILE* ifp; //ifp: "in file pointer"
char* mode = "r";
/* open the file */
ifp = fopen(file, mode);
if(NULL == ifp) {
printf("Can't open input file %s!\n", file);
return 1;
}
/* create read in buffer */
char* buf = (char*)malloc((genome_len+2)*sizeof(char));
/* initialize the padding at beginning of array */
for(int i = 0; i < PAD_AMT; i++) {
*(data + i) = BUFFER_CHAR;
}
int limit_len;
/* calculate the limit to which we will read data */
if (buffer_len < vicinity)
limit_len = buffed_len - vicinity;
else
limit_len = genome_len;
/* read in the file */
for(int i = 0; i < num_genomes; i++) {
if(NULL != fgets(buf, genome_len + 2, ifp)) {
for(int j = 0; j < limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + j) = buf[j];
}
for(int j = 0; j < buffed_len-limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + limit_len + j) = BUFFER_CHAR;
}
}
else {
printf("Failed to read from the file\n");
return 1;
}
}
/* close the file */
fclose(ifp);
free(buf);
return 0; //SUCCESS
}
/*
* Function - print_device_info
*
* Description:
* Prints valuable information out regarding the CUDA-capable devices
* in this system.
*/
void print_device_info(void) {
hipDeviceProp_t prop;
int count;
hipGetDeviceCount( &count );
for (int i=0; i< count; i++) {
hipGetDeviceProperties( &prop, i );
printf( " --- General Information for device %d ---\n", i );
printf( "Name: %s\n", prop.name );
printf( "Compute capability: %d.%d\n", prop.major, prop.minor );
printf( "Clock rate: %d\n", prop.clockRate );
printf( "Device copy overlap: " );
if (prop.deviceOverlap)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "Kernel execition timeout : " );
if (prop.kernelExecTimeoutEnabled)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( " --- Memory Information for device %d ---\n", i );
printf( "Total global mem: %ld\n", prop.totalGlobalMem );
printf( "Total constant Mem: %ld\n", prop.totalConstMem );
printf( "Max mem pitch: %ld\n", prop.memPitch );
printf( "Texture Alignment: %ld\n", prop.textureAlignment );
printf( " --- MP Information for device %d ---\n", i );
printf( "Multiprocessor count: %d\n", prop.multiProcessorCount );
printf( "Shared mem per mp: %ld\n", prop.sharedMemPerBlock );
printf( "Registers per mp: %d\n", prop.regsPerBlock );
printf( "Threads in warp: %d\n", prop.warpSize );
printf( "Max threads per block: %d\n", prop.maxThreadsPerBlock );
printf( "Max thread dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2] );
printf( "Max grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2] );
printf( "\n" );
}
}
/*
* Function - next_power_2
*
* Arguments:
* v - the value for which we want to find the next power of 2
*
* Outputs:
* unsigned int - the next power of 2 greater than v
*
* Description:
* This code basically rounds v up to the next highest power of 2. So if
* v was 2, this function would return 2. If v was 15, this function would
* return 16. Etcetera.
*
* Source:
* http://graphics.stanford.edu/~seander/bithacks.html
*/
unsigned int next_power_2(unsigned int v) {
v--;
v |= v >> 1;
v |= v >> 2;
v |= v >> 4;
v |= v >> 8;
v |= v >> 16;
v++;
return v;
}
unsigned int log_2(unsigned int v) {
unsigned int r=0;
while (v >>= 1) // unroll for more speed...
{
r++;
}
return r;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <string.h>
#include <hip/hip_runtime.h>
/*********************************/
/** constants/define statements **/
/*********************************/
#define THREADS_PER_BLOCK 1024
#define MAX_BLOCKS 65535
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
#define BUFFER_CHAR 'A'
#define PAD_AMT 5
/**********************/
/** function headers **/
/**********************/
void usage(void);
int init_data(char** data, unsigned int num_chars);
int init_data_pad(char** data, unsigned int num_chars);
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len, unsigned int vicinity);
void free_data(char* data, unsigned int num_genomes);
__global__ void readcmp(char* a, char* b, /*char* result,*/
unsigned long nthreads, unsigned int str_len,
unsigned int vicinity, unsigned int tstride,
char *reduce, unsigned int pop_thresh,
unsigned int threads_per_block,
unsigned int shift_amt);
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads,
unsigned int str_len, unsigned int pop_thresh,
unsigned int tstride);
void print_device_info(void);
unsigned int next_power_2(unsigned int v);
unsigned int log_2(unsigned int v);
/***************/
/** functions **/
/***************/
/*
* Function - gpuAssert
*
* Inputs:
* code - gpu error code
* file - current source file
* line - line within this file
* abort - if true, the prgram aborts
*
* Description:
* This function checks the cuda error code, and aborts if it is not a
* success.
*/
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n",hipGetErrorString(code),file,line);
if (abort) exit(code);
}
}
/*
* Kernel - readcmp
*
* Inputs:
* a - a pointer to one read
* b - a pointer to the other read
* nthreads - the maximum number of threads used
* str_len - the length of the reads to be compared (this is a power of 2)
* vicinity - the bit-flip vicinity
* tstride - the read index stride distance for each thread
* pop_thresh - the pop count threshold
* thread_per_block - the number of threads per block
* shift_amt - the maximum shift amount between the reads
*
* Outputs:
* reduce - the array returned which contains 0 for "reads match" or 1 for
* "reads don't match"
*
* Description:
* This Kernel does two things: for each pair of reads, it compares the
* characters and stores the bit-op results. It then performas a sum
* reduction on each read comparison and checks if it is above the edit
* threshold.
*/
__global__ void readcmp(char *dev_test_array, char *a, char *b, /*char *result,*/ unsigned long nthreads, unsigned int str_len, unsigned int vicinity, unsigned int tstride, char *reduce, unsigned int pop_thresh, unsigned int threads_per_block, unsigned int shift_amt) {
// Set up shared memory
extern __shared__ char shared_data[];
char* sdata = (char *)shared_data;
char* result = (char *)&shared_data[threads_per_block];
// Find index of this thread
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long tid = x + y * blockDim.x * gridDim.x;
unsigned long i = threadIdx.x; //local block tid
int j, k;
while(tid < nthreads) {
//make the first xor comparison without shifting
result[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT];
__syncthreads();
//check the vicinity for 100...01
if (result[i]!=0) {
for (j=1; j<vicinity; j++) {
if(result[i+j]!=0)
break;
}
if (result[i+j]!=0) {
for (k=1; k<j; k++) {
result[i+k]=0xff;
}
}
}
//make the remaining xor comparisons with shifting up until the limit
for(unsigned int cur_shift = 1; cur_shift <= shift_amt; cur_shift++) {
__syncthreads();
sdata[i] = a[tid+PAD_AMT] ^ b[tid+PAD_AMT-cur_shift]; //shift b left
__syncthreads();
//check vicinity
if (sdata[i] != 0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
//AND result
__syncthreads();
result[i] = result[i] && sdata[i];
sdata[i] = b[tid+PAD_AMT] ^ a[tid+PAD_AMT-cur_shift]; //shift a left
__syncthreads();
//check vicinity
if (sdata[i]!=0) {
for (j=1; j<vicinity; j++) {
if(sdata[i+j]!=0)
break;
}
if (sdata[i+j]!=0) {
for (k=1; k<j; k++) {
sdata[i+k]=0xff;
}
}
}
//AND result
__syncthreads();
result[i] = result[i] && sdata[i];
__syncthreads();
}
/////////////////////////////////////////////////////////////////////
// the code below is used for the sum reduce
/////////////////////////////////////////////////////////////////////
sdata[i] = result[i];
__syncthreads();
/*
* conservative reduction implemented by John Emmons Feb. 2014
* EX. if vicinity = 3 then 111100110111111 -> 100100110100101
*/
if(sdata[i] != 0 && (i == 0 || sdata[i-1] == 0)){
int m, n = i;
bool flag = true;
while(true){
for(m = 1; m < vicinity + 1; m++){
if(n + m < str_len) {
if(sdata[n + m] != 0){ continue; }
else if(m < 2){ flag = false; break; }
else{ break; }
}
else{
if(m < 2){ flag = false; break; }
else{ break; }
}
}
if(flag){
for(m -= 2; m > 0; m--)
sdata[n + m] = 0x00;
n += vicinity;
}
else{ break; }
}
}
__syncthreads();
// conservative reduction debugging
dev_test_array[i] = sdata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
if(i < s) {
sdata[i] += sdata[i + s];
}
__syncthreads();
}
__syncthreads();
// write result for this block to global mem
if(i%str_len == 0) {
reduce[tid/str_len] = (sdata[i]<=pop_thresh)?0:1;
}
///////////////////////////////////////////////////////////////////////
__syncthreads();
tid += tstride; //increase tid by thread stride amount
}
}
/*********************************/
/** THIS FUNCTION IS DEPRECATED **/
/*********************************/
__global__ void reduce(char *g_idata, char *g_odata, unsigned long nthreads, unsigned int str_len, unsigned int pop_thresh, unsigned int tstride) {
extern __shared__ char sdata[];
// each thread loads one element from global to shared mem
unsigned long x = threadIdx.x + blockIdx.x * blockDim.x;
unsigned long y = threadIdx.y + blockIdx.y * blockDim.y;
unsigned long i = x + y * blockDim.x * gridDim.x; //global tid
unsigned int tid = threadIdx.x; //local block tid
while(i < nthreads) {
sdata[tid] = g_idata[i];
__syncthreads();
// do reduction in shared mem
for(unsigned int s=str_len/2; s>0; s >>= 1){
if (tid<s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
// write result for this block to global mem
if (tid%str_len == 0) {
g_odata[i/str_len] = (sdata[tid]<=pop_thresh)?1:0;
g_odata[i/str_len] = sdata[tid];
}
i += tstride;
}
}
/*
* Function - main
*
* Arguments:
* argc - the number of command line arguments
* argv - an array of the command line arguments
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This is the main function. It initializes memory. It reads in the
* files which contain the reads. It, then, launches the kernel on
* the GPU.
*/
int main(int argc, char *argv[]) {
/* check the number of command line arguments */
if(argc != 8) {
usage();
return 1;
}
/* get arguments */
char* file_1;
char* file_2;
unsigned int num_genomes, genome_len, buffed_len,
buffer_len, vicinity, errors, pop_thresh, shift_amt;
FILE *pop_count_file;
file_1 = argv[1]; //contains reads
file_2 = argv[2]; //contains reads
num_genomes = atoi(argv[3]); //the number of reads in each file
genome_len = atoi(argv[4]); //the length of each read
errors = atoi(argv[5]); //the number of edits allowed between two reads
vicinity = atoi(argv[6]); //the vicinity for bit flips
shift_amt = atoi(argv[7]); //the maximum shift amount when comparing reads
/* calculate important values */
pop_thresh = /*(vicinity-1)*(errors-1) +*/ errors; //popcount threshold (is simply the num of allowed errors with conservative reduction)
buffed_len = next_power_2(genome_len); //genome length + buffer space
buffer_len = buffed_len - genome_len; //difference bw genome len and buf len
unsigned long num_chars = num_genomes*buffed_len; //the total number of chars in every buffed read
/* initialize and allocate strings to compare */
char* genome_1_data; //first genome data
char* genome_2_data; //second genome data
char* reduce_data; //sum of "errors" in each string
if(init_data_pad(&genome_1_data, num_chars)) return 1;
if(init_data_pad(&genome_2_data, num_chars)) return 1;
if(init_data(&reduce_data, num_genomes)) return 1;
// conservative reduction debugging
char* test_array;
if(init_data(&test_array, num_chars+PAD_AMT)) return 1;
/* read in the data */
if(read_data(genome_1_data, file_1, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
if(read_data(genome_2_data, file_2, num_genomes, genome_len, buffer_len, buffed_len, vicinity+1)) return 1;
/* create timing events */
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
/* initialize and allocate memoer for GPU input and output arrays */
char *dev_genome_1_data;
char *dev_genome_2_data;
char *dev_reduce_data;
gpuErrchk( hipMalloc((void**)&dev_genome_1_data, (num_chars+PAD_AMT)*sizeof(char)));
gpuErrchk( hipMalloc((void**)&dev_genome_2_data, (num_chars+PAD_AMT)*sizeof(char)));
gpuErrchk( hipMalloc((void**)&dev_reduce_data, num_genomes*sizeof(char) ));
// conservative reduction debugging
char *dev_test_array;
gpuErrchk( hipMalloc((void**)&dev_test_array, (num_chars+PAD_AMT)*sizeof(char) ));
/******************/
/** START TIMING **/
/******************/
/*========================================================================*/
/* set start time */
hipEventRecord(start, 0);
/* copy data to GPU */
gpuErrchk(hipMemcpy( dev_genome_1_data, genome_1_data,
(num_chars+PAD_AMT)*sizeof(char), hipMemcpyHostToDevice ));
gpuErrchk(hipMemcpy( dev_genome_2_data, genome_2_data,
(num_chars+PAD_AMT)*sizeof(char), hipMemcpyHostToDevice ));
// conservative reduction debugging
gpuErrchk(hipMemcpy( dev_test_array, test_array,
(num_chars+PAD_AMT)*sizeof(char), hipMemcpyHostToDevice ));
/* figure out thread count and dimensions for GPU */
unsigned int num_blocks_x = 128;
unsigned int num_blocks_y = 128;
unsigned int threads_per_block = buffed_len;
unsigned int tstride = threads_per_block*num_blocks_x*num_blocks_y;
dim3 grid_size(num_blocks_x, num_blocks_y, 1);
unsigned int log_len = log_2(buffed_len); //TODO: ALL OF THIS SHOULD PROBABLY BE MOVED ABOVE THE BEGINNING OF TIMING
/* create and run GPU threads */
readcmp<<<grid_size,threads_per_block,2*threads_per_block>>>(dev_test_array, dev_genome_1_data,
dev_genome_2_data,/* dev_result_data,*/ num_chars, buffed_len, vicinity,
tstride, dev_reduce_data, pop_thresh, threads_per_block, shift_amt);
gpuErrchk(hipDeviceSynchronize());
/* write the results back */
gpuErrchk(hipMemcpy( reduce_data, dev_reduce_data,
num_genomes*sizeof(char), hipMemcpyDeviceToHost ));
// conservative reduction debugging
gpuErrchk(hipMemcpy( test_array, dev_test_array,
(num_chars + PAD_AMT) *sizeof(char), hipMemcpyDeviceToHost ));
/*========================================================================*/
/****************/
/** END TIMING **/
/****************/
/* set stop time */
hipEventRecord(stop,0);
hipEventSynchronize( stop );
/* calculate elapsed time for GPU computation */
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
printf("Time to complete comparison %1.4f ms\n", elapsedTime);
// Writing output pop count to file
// for data collection purposes
unsigned int matches=0;
for (unsigned int q=0; q<num_genomes; q++) {
if (reduce_data[q]==0)
matches++;
}
// conservative reduction debugging
int j = 0;
int bad_strings[num_genomes];
for(int i=0; i < num_genomes; i++)
bad_strings[i] = 0;
// find the bad strings
for(int i=0; i < num_genomes; i++){
if (reduce_data[i]!=0){
bad_strings[j] = i;
j++;
}
}
for(int i=0; i < num_genomes; i++){
if(bad_strings[i] != 0){
printf("genome number %d is a false negative\n", bad_strings[i]);
//printf("Original genome:\n");
for(int k=0; k < genome_len; k++){
printf("%c", genome_1_data[k + bad_strings[i]]);
}
printf("\n");
//printf("Edited genome:\n");
for(int k=0; k < genome_len; k++){
printf("%c", genome_2_data[k + bad_strings[i]]);
}
printf("\n");
}
}
// for(unsigned int i=0; i < num_chars + PAD_AMT; i++){
// printf("the test_array: %i\n", test_array[i]);
// }
pop_count_file = fopen("pop_output.txt","w");
fprintf(pop_count_file, "%d %d\n", matches, num_genomes-matches);
fclose(pop_count_file);
/* free and destroy all allocated information */
hipFree(dev_genome_1_data);
hipFree(dev_genome_2_data);
hipFree(dev_reduce_data);
hipEventDestroy(start);
hipEventDestroy(stop);
hipHostFree(genome_1_data);
hipHostFree(genome_2_data);
hipHostFree(reduce_data);
}
/*
* Function - usage
*
* Description:
* Just prints the usage invariant for this program.
*/
void usage(void) {
printf("\nUsage:\n");
printf("\t./a.out <file_1> <file_2> <num_genomes> <genome_len> <errors> <vicinity> <adj_errs>\n\n");
}
/*
* Function - init_data
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow.
*/
int init_data(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
hipHostAlloc((void**)data,num_chars*sizeof(char),hipHostMallocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - init_data_pad
*
* Arguments:
* data - the array in which to place data
* num_chars - the number of chars to allocate
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function initializes a data array. Pretty simple to follow. It's
* the same as the above function except that it adds the PAD_AMT to
* to it.
*/
int init_data_pad(char** data, unsigned int num_chars) {
/* allocate pointers for the genome strings */
hipHostAlloc((void**)data,(num_chars+PAD_AMT)*sizeof(char),hipHostMallocDefault);
if(NULL == *data) {
printf("init_data - malloc failed\n");
return 1;
}
return 0; //SUCCESS
}
/*
* Function - read_data
*
* Arguments:
* data - the char* to which the data will be written
* file - the filae that contains the genomes we care about
* num_genomes - the numebr of genomed to read
* genome_len - the length of the genomes
* buffer_len - the length of the buffer at the end of each genome
* buffed_len - length of genome + buffer
*
* Outputs:
* int - 0 if success, 1 if failure
*
* Description:
* This function reads in all of the genome data from the given genome
* file. Each line contains a genome read, and this is read into each
* string.
*/
int read_data(char* data, char* file, unsigned int num_genomes,
unsigned int genome_len, unsigned int buffer_len,
unsigned int buffed_len,unsigned int vicinity) {
/* basic info and variables */
FILE* ifp; //ifp: "in file pointer"
char* mode = "r";
/* open the file */
ifp = fopen(file, mode);
if(NULL == ifp) {
printf("Can't open input file %s!\n", file);
return 1;
}
/* create read in buffer */
char* buf = (char*)malloc((genome_len+2)*sizeof(char));
/* initialize the padding at beginning of array */
for(int i = 0; i < PAD_AMT; i++) {
*(data + i) = BUFFER_CHAR;
}
int limit_len;
/* calculate the limit to which we will read data */
if (buffer_len < vicinity)
limit_len = buffed_len - vicinity;
else
limit_len = genome_len;
/* read in the file */
for(int i = 0; i < num_genomes; i++) {
if(NULL != fgets(buf, genome_len + 2, ifp)) {
for(int j = 0; j < limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + j) = buf[j];
}
for(int j = 0; j < buffed_len-limit_len; j++) {
*(data + PAD_AMT + i*buffed_len + limit_len + j) = BUFFER_CHAR;
}
}
else {
printf("Failed to read from the file\n");
return 1;
}
}
/* close the file */
fclose(ifp);
free(buf);
return 0; //SUCCESS
}
/*
* Function - print_device_info
*
* Description:
* Prints valuable information out regarding the CUDA-capable devices
* in this system.
*/
void print_device_info(void) {
hipDeviceProp_t prop;
int count;
hipGetDeviceCount( &count );
for (int i=0; i< count; i++) {
hipGetDeviceProperties( &prop, i );
printf( " --- General Information for device %d ---\n", i );
printf( "Name: %s\n", prop.name );
printf( "Compute capability: %d.%d\n", prop.major, prop.minor );
printf( "Clock rate: %d\n", prop.clockRate );
printf( "Device copy overlap: " );
if (prop.deviceOverlap)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( "Kernel execition timeout : " );
if (prop.kernelExecTimeoutEnabled)
printf( "Enabled\n" );
else
printf( "Disabled\n" );
printf( " --- Memory Information for device %d ---\n", i );
printf( "Total global mem: %ld\n", prop.totalGlobalMem );
printf( "Total constant Mem: %ld\n", prop.totalConstMem );
printf( "Max mem pitch: %ld\n", prop.memPitch );
printf( "Texture Alignment: %ld\n", prop.textureAlignment );
printf( " --- MP Information for device %d ---\n", i );
printf( "Multiprocessor count: %d\n", prop.multiProcessorCount );
printf( "Shared mem per mp: %ld\n", prop.sharedMemPerBlock );
printf( "Registers per mp: %d\n", prop.regsPerBlock );
printf( "Threads in warp: %d\n", prop.warpSize );
printf( "Max threads per block: %d\n", prop.maxThreadsPerBlock );
printf( "Max thread dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0], prop.maxThreadsDim[1],
prop.maxThreadsDim[2] );
printf( "Max grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0], prop.maxGridSize[1],
prop.maxGridSize[2] );
printf( "\n" );
}
}
/*
* Function - next_power_2
*
* Arguments:
* v - the value for which we want to find the next power of 2
*
* Outputs:
* unsigned int - the next power of 2 greater than v
*
* Description:
* This code basically rounds v up to the next highest power of 2. So if
* v was 2, this function would return 2. If v was 15, this function would
* return 16. Etcetera.
*
* Source:
* http://graphics.stanford.edu/~seander/bithacks.html
*/
unsigned int next_power_2(unsigned int v) {
v--;
v |= v >> 1;
v |= v >> 2;
v |= v >> 4;
v |= v >> 8;
v |= v >> 16;
v++;
return v;
}
unsigned int log_2(unsigned int v) {
unsigned int r=0;
while (v >>= 1) // unroll for more speed...
{
r++;
}
return r;
} | .text
.file "introCUDA_injection_taylor_shift.hip"
.globl _Z22__device_stub__readcmpPcS_S_mjjjS_jjj # -- Begin function _Z22__device_stub__readcmpPcS_S_mjjjS_jjj
.p2align 4, 0x90
.type _Z22__device_stub__readcmpPcS_S_mjjjS_jjj,@function
_Z22__device_stub__readcmpPcS_S_mjjjS_jjj: # @_Z22__device_stub__readcmpPcS_S_mjjjS_jjj
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7readcmpPcS_S_mjjjS_jjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z22__device_stub__readcmpPcS_S_mjjjS_jjj, .Lfunc_end0-_Z22__device_stub__readcmpPcS_S_mjjjS_jjj
.cfi_endproc
# -- End function
.globl _Z21__device_stub__reducePcS_mjjj # -- Begin function _Z21__device_stub__reducePcS_mjjj
.p2align 4, 0x90
.type _Z21__device_stub__reducePcS_mjjj,@function
_Z21__device_stub__reducePcS_mjjj: # @_Z21__device_stub__reducePcS_mjjj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6reducePcS_mjjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z21__device_stub__reducePcS_mjjj, .Lfunc_end1-_Z21__device_stub__reducePcS_mjjj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $168, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
cmpl $8, %edi
jne .LBB2_1
# %bb.2:
movq 8(%rsi), %rax
movq %rax, -88(%rbp) # 8-byte Spill
movq 16(%rsi), %rax
movq %rax, -120(%rbp) # 8-byte Spill
movq 24(%rsi), %rdi
movq %rsi, %r14
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 40(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, -112(%rbp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, -56(%rbp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, -200(%rbp) # 8-byte Spill
movq %rbx, -96(%rbp) # 8-byte Spill
leal -1(%rbx), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $8, %eax
orl %ecx, %eax
movl %eax, %r13d
shrl $16, %r13d
orl %eax, %r13d
incl %r13d
movl %r13d, %r12d
imull %r15d, %r12d
leal 5(%r12), %r14d
leaq -80(%rbp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostAlloc
cmpq $0, -80(%rbp)
je .LBB2_3
# %bb.5: # %.critedge
leaq -72(%rbp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostAlloc
cmpq $0, -72(%rbp)
je .LBB2_3
# %bb.6: # %.critedge136
movl %r15d, %ebx
leaq -64(%rbp), %rdi
movq %rbx, %rsi
xorl %edx, %edx
callq hipHostAlloc
cmpq $0, -64(%rbp)
je .LBB2_3
# %bb.7: # %.critedge137
leaq 5(%r12), %r14
movl %r14d, %esi
leaq -168(%rbp), %rdi
xorl %edx, %edx
callq hipHostAlloc
cmpq $0, -168(%rbp)
je .LBB2_3
# %bb.8: # %.critedge138
movq %r14, -184(%rbp) # 8-byte Spill
movq %rbx, -192(%rbp) # 8-byte Spill
movl %r13d, %r14d
movq -96(%rbp), %rbx # 8-byte Reload
subl %ebx, %r14d
movq -80(%rbp), %rdi
movq %r15, %rdx
movq -56(%rbp), %rax # 8-byte Reload
leal 1(%rax), %r15d
subq $8, %rsp
movq -88(%rbp), %rsi # 8-byte Reload
movq %rdx, -48(%rbp) # 8-byte Spill
# kill: def $edx killed $edx killed $rdx
movl %ebx, %ecx
movl %r14d, %r8d
movl %r13d, %r9d
pushq %r15
callq _Z9read_dataPcS_jjjjj
addq $16, %rsp
movl %eax, %ecx
movl $1, %eax
testl %ecx, %ecx
jne .LBB2_29
# %bb.9:
movq -72(%rbp), %rdi
subq $8, %rsp
movq -120(%rbp), %rsi # 8-byte Reload
movq -48(%rbp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movl %ebx, %ecx
movl %r14d, %r8d
movl %r13d, %r9d
pushq %r15
callq _Z9read_dataPcS_jjjjj
addq $16, %rsp
movl %eax, %ecx
movl $1, %eax
testl %ecx, %ecx
jne .LBB2_29
# %bb.10: # %_Z5log_2j.exit
leaq -160(%rbp), %rdi
callq hipEventCreate
leaq -104(%rbp), %rdi
callq hipEventCreate
leaq -152(%rbp), %rdi
movq -184(%rbp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
movl $.L.str, %esi
movl %eax, %edi
movl $347, %edx # imm = 0x15B
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
leaq -144(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $.L.str, %esi
movl %eax, %edi
movl $348, %edx # imm = 0x15C
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
leaq -136(%rbp), %rdi
movq -192(%rbp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
movl $.L.str, %esi
movl %eax, %edi
movl $349, %edx # imm = 0x15D
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
leaq -128(%rbp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $.L.str, %esi
movl %eax, %edi
movl $353, %edx # imm = 0x161
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq -160(%rbp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq -152(%rbp), %rdi
movq -80(%rbp), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str, %esi
movl %eax, %edi
movl $366, %edx # imm = 0x16E
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq -144(%rbp), %rdi
movq -72(%rbp), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str, %esi
movl %eax, %edi
movl $368, %edx # imm = 0x170
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq -128(%rbp), %rdi
movq -168(%rbp), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str, %esi
movl %eax, %edi
movl $372, %edx # imm = 0x174
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
leal (,%r13,2), %r8d
movl %r13d, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rax, %rdx
movabsq $549755814016, %rdi # imm = 0x8000000080
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movl %r13d, %eax
shll $14, %eax
movq -128(%rbp), %rdi
movq -152(%rbp), %rsi
movq -144(%rbp), %rdx
subq $8, %rsp
movq %r12, %rcx
movl %r13d, %r8d
movq -56(%rbp), %r9 # 8-byte Reload
# kill: def $r9d killed $r9d killed $r9
pushq -200(%rbp) # 8-byte Folded Reload
pushq %r13
pushq -112(%rbp) # 8-byte Folded Reload
pushq -136(%rbp)
pushq %rax
callq _Z22__device_stub__readcmpPcS_S_mjjjS_jjj
addq $48, %rsp
.LBB2_12:
callq hipDeviceSynchronize
movl $.L.str, %esi
movl %eax, %edi
movl $386, %edx # imm = 0x182
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq -64(%rbp), %rdi
movq -136(%rbp), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %esi
movl %eax, %edi
movl $390, %edx # imm = 0x186
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq -168(%rbp), %rdi
movq -128(%rbp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %esi
movl %eax, %edi
movl $394, %edx # imm = 0x18A
movl $1, %ecx
callq _Z9gpuAssert10hipError_tPcib
movq -104(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -104(%rbp), %rdi
callq hipEventSynchronize
movq -160(%rbp), %rsi
movq -104(%rbp), %rdx
leaq -172(%rbp), %rdi
callq hipEventElapsedTime
movss -172(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
cmpl $0, -48(%rbp) # 4-byte Folded Reload
je .LBB2_15
# %bb.13: # %.lr.ph
movq -64(%rbp), %rax
movl -48(%rbp), %ecx # 4-byte Reload
xorl %edx, %edx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_14: # =>This Inner Loop Header: Depth=1
cmpb $1, (%rax,%rdx)
adcl $0, %r15d
incq %rdx
cmpq %rdx, %rcx
jne .LBB2_14
.LBB2_15: # %._crit_edge
movq %rsp, -112(%rbp) # 8-byte Spill
movq %rsp, %rcx
leaq 15(,%rbx,4), %rax
andq $-16, %rax
subq %rax, %rcx
movq %rcx, -56(%rbp) # 8-byte Spill
movq %rcx, %rsp
cmpl $0, -48(%rbp) # 4-byte Folded Reload
je .LBB2_28
# %bb.16: # %.lr.ph144.preheader
movl -48(%rbp), %ebx # 4-byte Reload
leaq (,%rbx,4), %rdx
xorl %r14d, %r14d
movq -56(%rbp), %rdi # 8-byte Reload
xorl %esi, %esi
callq memset@PLT
movq -64(%rbp), %rax
xorl %ecx, %ecx
movq -96(%rbp), %rdx # 8-byte Reload
movq -56(%rbp), %rsi # 8-byte Reload
jmp .LBB2_17
.LBB2_1:
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
jmp .LBB2_4
.LBB2_3: # %_Z13init_data_padPPcj.exit
movl $.Lstr.3, %edi
.LBB2_4:
callq puts@PLT
movl $1, %eax
.LBB2_29:
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.p2align 4, 0x90
.LBB2_19: # in Loop: Header=BB2_17 Depth=1
.cfi_def_cfa %rbp, 16
incq %r14
cmpq %r14, %rbx
je .LBB2_20
.LBB2_17: # =>This Inner Loop Header: Depth=1
cmpb $0, (%rax,%r14)
je .LBB2_19
# %bb.18: # in Loop: Header=BB2_17 Depth=1
movslq %ecx, %rcx
movl %r14d, (%rsi,%rcx,4)
incl %ecx
jmp .LBB2_19
.LBB2_20: # %.lr.ph157
movl -48(%rbp), %eax # 4-byte Reload
movq %rax, -120(%rbp) # 8-byte Spill
movl %edx, %eax
movq %rax, -88(%rbp) # 8-byte Spill
xorl %r13d, %r13d
jmp .LBB2_21
.LBB2_26: # %._crit_edge155
# in Loop: Header=BB2_21 Depth=1
movl $10, %edi
callq putchar@PLT
.LBB2_27: # in Loop: Header=BB2_21 Depth=1
incq %r13
cmpq -120(%rbp), %r13 # 8-byte Folded Reload
je .LBB2_28
.LBB2_21: # =>This Loop Header: Depth=1
# Child Loop BB2_30 Depth 2
# Child Loop BB2_25 Depth 2
movq -56(%rbp), %rax # 8-byte Reload
movslq (%rax,%r13,4), %r12
testq %r12, %r12
je .LBB2_27
# %bb.22: # in Loop: Header=BB2_21 Depth=1
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movq -88(%rbp), %r14 # 8-byte Reload
movq %r12, %rbx
cmpl $0, -96(%rbp) # 4-byte Folded Reload
je .LBB2_23
.p2align 4, 0x90
.LBB2_30: # %.lr.ph150
# Parent Loop BB2_21 Depth=1
# => This Inner Loop Header: Depth=2
movq -80(%rbp), %rax
movsbl (%rax,%rbx), %edi
callq putchar@PLT
incq %rbx
decq %r14
jne .LBB2_30
.LBB2_23: # %._crit_edge151
# in Loop: Header=BB2_21 Depth=1
movl $10, %edi
callq putchar@PLT
cmpl $0, -96(%rbp) # 4-byte Folded Reload
je .LBB2_26
# %bb.24: # %.lr.ph154.preheader
# in Loop: Header=BB2_21 Depth=1
movq -88(%rbp), %rbx # 8-byte Reload
.p2align 4, 0x90
.LBB2_25: # %.lr.ph154
# Parent Loop BB2_21 Depth=1
# => This Inner Loop Header: Depth=2
movq -72(%rbp), %rax
movsbl (%rax,%r12), %edi
callq putchar@PLT
incq %r12
decq %rbx
jne .LBB2_25
jmp .LBB2_26
.LBB2_28: # %._crit_edge158
movl $.L.str.5, %edi
movl $.L.str.6, %esi
callq fopen
movq %rax, %rbx
movq -48(%rbp), %rcx # 8-byte Reload
subl %r15d, %ecx
movl $.L.str.7, %esi
movq %rax, %rdi
movl %r15d, %edx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq fprintf
movq %rbx, %rdi
callq fclose
movq -152(%rbp), %rdi
callq hipFree
movq -144(%rbp), %rdi
callq hipFree
movq -136(%rbp), %rdi
callq hipFree
movq -160(%rbp), %rdi
callq hipEventDestroy
movq -104(%rbp), %rdi
callq hipEventDestroy
movq -80(%rbp), %rdi
callq hipHostFree
movq -72(%rbp), %rdi
callq hipHostFree
movq -64(%rbp), %rdi
callq hipHostFree
xorl %eax, %eax
movq -112(%rbp), %rsp # 8-byte Reload
jmp .LBB2_29
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.globl _Z5usagev # -- Begin function _Z5usagev
.p2align 4, 0x90
.type _Z5usagev,@function
_Z5usagev: # @_Z5usagev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z5usagev, .Lfunc_end3-_Z5usagev
.cfi_endproc
# -- End function
.globl _Z12next_power_2j # -- Begin function _Z12next_power_2j
.p2align 4, 0x90
.type _Z12next_power_2j,@function
_Z12next_power_2j: # @_Z12next_power_2j
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
leal -1(%rdi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $4, %ecx
orl %eax, %ecx
movl %ecx, %edx
shrl $8, %edx
orl %ecx, %edx
movl %edx, %eax
shrl $16, %eax
orl %edx, %eax
incl %eax
retq
.Lfunc_end4:
.size _Z12next_power_2j, .Lfunc_end4-_Z12next_power_2j
.cfi_endproc
# -- End function
.globl _Z13init_data_padPPcj # -- Begin function _Z13init_data_padPPcj
.p2align 4, 0x90
.type _Z13init_data_padPPcj,@function
_Z13init_data_padPPcj: # @_Z13init_data_padPPcj
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
# kill: def $esi killed $esi def $rsi
movq %rdi, %r14
addl $5, %esi
xorl %ebx, %ebx
xorl %edx, %edx
callq hipHostAlloc
cmpq $0, (%r14)
jne .LBB5_2
# %bb.1:
movl $.Lstr.3, %edi
callq puts@PLT
movl $1, %ebx
.LBB5_2:
movl %ebx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z13init_data_padPPcj, .Lfunc_end5-_Z13init_data_padPPcj
.cfi_endproc
# -- End function
.globl _Z9init_dataPPcj # -- Begin function _Z9init_dataPPcj
.p2align 4, 0x90
.type _Z9init_dataPPcj,@function
_Z9init_dataPPcj: # @_Z9init_dataPPcj
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %r14
movl %esi, %esi
xorl %ebx, %ebx
xorl %edx, %edx
callq hipHostAlloc
cmpq $0, (%r14)
jne .LBB6_2
# %bb.1:
movl $.Lstr.3, %edi
callq puts@PLT
movl $1, %ebx
.LBB6_2:
movl %ebx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z9init_dataPPcj, .Lfunc_end6-_Z9init_dataPPcj
.cfi_endproc
# -- End function
.globl _Z9read_dataPcS_jjjjj # -- Begin function _Z9read_dataPcS_jjjjj
.p2align 4, 0x90
.type _Z9read_dataPcS_jjjjj,@function
_Z9read_dataPcS_jjjjj: # @_Z9read_dataPcS_jjjjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %r15d
movl %ecx, %r14d
movl %edx, %ebp
movq %rsi, %r13
movq %rdi, %r12
movl $.L.str.11, %esi
movq %r13, %rdi
callq fopen
movq %rax, (%rsp) # 8-byte Spill
testq %rax, %rax
je .LBB7_10
# %bb.1:
leal 2(%r14), %edi
movq %rdi, 32(%rsp) # 8-byte Spill
callq malloc
movq %rax, %r13
movl $1094795585, (%r12) # imm = 0x41414141
movb $65, 4(%r12)
testl %ebp, %ebp
je .LBB7_9
# %bb.2: # %.lr.ph58
movq %r12, %rdx
movl 96(%rsp), %eax
movl %ebx, %ecx
subl %eax, %ecx
cmpl %eax, %r15d
cmovbl %ecx, %r14d
movslq %r14d, %rax
leaq (%r12,%rax), %rcx
addq $5, %rcx
movq %rcx, 8(%rsp) # 8-byte Spill
addq $5, %rdx
movq %rdx, 24(%rsp) # 8-byte Spill
notl %eax
addl %ebx, %eax
incq %rax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebp, %ebp
xorl %r12d, %r12d
jmp .LBB7_4
.p2align 4, 0x90
.LBB7_3: # %._crit_edge
# in Loop: Header=BB7_4 Depth=1
addl %ebx, %r12d
decq %rbp
je .LBB7_9
.LBB7_4: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movq 32(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movq (%rsp), %rdx # 8-byte Reload
callq fgets
testq %rax, %rax
je .LBB7_11
# %bb.5: # %.preheader50
# in Loop: Header=BB7_4 Depth=1
movl %r12d, %r15d
testl %r14d, %r14d
jle .LBB7_7
# %bb.6: # %.lr.ph
# in Loop: Header=BB7_4 Depth=1
movq 24(%rsp), %rax # 8-byte Reload
leaq (%rax,%r15), %rdi
movq %r13, %rsi
movq %r14, %rdx
callq memcpy@PLT
.LBB7_7: # %.preheader
# in Loop: Header=BB7_4 Depth=1
cmpl %ebx, %r14d
je .LBB7_3
# %bb.8: # %.lr.ph54
# in Loop: Header=BB7_4 Depth=1
addq 8(%rsp), %r15 # 8-byte Folded Reload
movq %r15, %rdi
movl $65, %esi
movq 16(%rsp), %rdx # 8-byte Reload
callq memset@PLT
jmp .LBB7_3
.LBB7_9: # %.critedge
movq (%rsp), %rdi # 8-byte Reload
callq fclose
movq %r13, %rdi
callq free
xorl %eax, %eax
jmp .LBB7_13
.LBB7_10:
movl $.L.str.12, %edi
movq %r13, %rsi
xorl %eax, %eax
callq printf
jmp .LBB7_12
.LBB7_11:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB7_12:
movl $1, %eax
.LBB7_13:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z9read_dataPcS_jjjjj, .Lfunc_end7-_Z9read_dataPcS_jjjjj
.cfi_endproc
# -- End function
.section .text._Z9gpuAssert10hipError_tPcib,"axG",@progbits,_Z9gpuAssert10hipError_tPcib,comdat
.weak _Z9gpuAssert10hipError_tPcib # -- Begin function _Z9gpuAssert10hipError_tPcib
.p2align 4, 0x90
.type _Z9gpuAssert10hipError_tPcib,@function
_Z9gpuAssert10hipError_tPcib: # @_Z9gpuAssert10hipError_tPcib
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testl %edi, %edi
jne .LBB8_1
.LBB8_2:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB8_1:
.cfi_def_cfa_offset 48
movq stderr(%rip), %r14
movl %edi, %ebx
movl %ecx, %r12d
movl %edx, %ebp
movq %rsi, %r15
callq hipGetErrorString
movl $.L.str.35, %esi
movq %r14, %rdi
movq %rax, %rdx
movq %r15, %rcx
movl %ebp, %r8d
xorl %eax, %eax
callq fprintf
testb %r12b, %r12b
je .LBB8_2
# %bb.3:
movl %ebx, %edi
callq exit
.Lfunc_end8:
.size _Z9gpuAssert10hipError_tPcib, .Lfunc_end8-_Z9gpuAssert10hipError_tPcib
.cfi_endproc
# -- End function
.text
.globl _Z5log_2j # -- Begin function _Z5log_2j
.p2align 4, 0x90
.type _Z5log_2j,@function
_Z5log_2j: # @_Z5log_2j
.cfi_startproc
# %bb.0:
xorl %eax, %eax
cmpl $2, %edi
jb .LBB9_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
movl %edi, %ecx
.p2align 4, 0x90
.LBB9_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
shrl %ecx
incl %eax
cmpl $3, %edi
movl %ecx, %edi
ja .LBB9_2
.LBB9_3: # %._crit_edge
retq
.Lfunc_end9:
.size _Z5log_2j, .Lfunc_end9-_Z5log_2j
.cfi_endproc
# -- End function
.globl _Z17print_device_infov # -- Begin function _Z17print_device_infov
.p2align 4, 0x90
.type _Z17print_device_infov,@function
_Z17print_device_infov: # @_Z17print_device_infov
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB10_3
# %bb.1: # %.lr.ph
leaq 16(%rsp), %rbx
movl $.Lstr.7, %r14d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB10_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.14, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.15, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 376(%rsp), %esi
movl 380(%rsp), %edx
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
movl 364(%rsp), %esi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
movl $.L.str.18, %edi
xorl %eax, %eax
callq printf
cmpl $0, 400(%rsp)
movl $.Lstr.8, %edi
cmoveq %r14, %rdi
callq puts@PLT
movl $.L.str.21, %edi
xorl %eax, %eax
callq printf
cmpl $0, 408(%rsp)
movl $.Lstr.8, %edi
cmoveq %r14, %rdi
callq puts@PLT
movl $.L.str.22, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.23, %edi
xorl %eax, %eax
callq printf
movq 368(%rsp), %rsi
movl $.L.str.24, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.25, %edi
xorl %eax, %eax
callq printf
movq 384(%rsp), %rsi
movl $.L.str.26, %edi
xorl %eax, %eax
callq printf
movl $.L.str.27, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl 404(%rsp), %esi
movl $.L.str.28, %edi
xorl %eax, %eax
callq printf
movq 312(%rsp), %rsi
movl $.L.str.29, %edi
xorl %eax, %eax
callq printf
movl 320(%rsp), %esi
movl $.L.str.30, %edi
xorl %eax, %eax
callq printf
movl 324(%rsp), %esi
movl $.L.str.31, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.32, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl 344(%rsp), %edx
movl 348(%rsp), %ecx
movl $.L.str.33, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl 356(%rsp), %edx
movl 360(%rsp), %ecx
movl $.L.str.34, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB10_2
.LBB10_3: # %._crit_edge
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end10:
.size _Z17print_device_infov, .Lfunc_end10-_Z17print_device_infov
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7readcmpPcS_S_mjjjS_jjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducePcS_mjjj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7readcmpPcS_S_mjjjS_jjj,@object # @_Z7readcmpPcS_S_mjjjS_jjj
.section .rodata,"a",@progbits
.globl _Z7readcmpPcS_S_mjjjS_jjj
.p2align 3, 0x0
_Z7readcmpPcS_S_mjjjS_jjj:
.quad _Z22__device_stub__readcmpPcS_S_mjjjS_jjj
.size _Z7readcmpPcS_S_mjjjS_jjj, 8
.type _Z6reducePcS_mjjj,@object # @_Z6reducePcS_mjjj
.globl _Z6reducePcS_mjjj
.p2align 3, 0x0
_Z6reducePcS_mjjj:
.quad _Z21__device_stub__reducePcS_mjjj
.size _Z6reducePcS_mjjj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/xhongyi/toybrick/master/cuda/740_cuda_twomack_nnuemah/introCUDA_injection_taylor_shift.hip"
.size .L.str, 148
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time to complete comparison %1.4f ms\n"
.size .L.str.1, 38
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "genome number %d is a false negative\n"
.size .L.str.2, 38
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "pop_output.txt"
.size .L.str.5, 15
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "w"
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d %d\n"
.size .L.str.7, 7
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "r"
.size .L.str.11, 2
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Can't open input file %s!\n"
.size .L.str.12, 27
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " --- General Information for device %d ---\n"
.size .L.str.14, 44
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Name: %s\n"
.size .L.str.15, 10
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Compute capability: %d.%d\n"
.size .L.str.16, 27
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Clock rate: %d\n"
.size .L.str.17, 16
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Device copy overlap: "
.size .L.str.18, 22
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Kernel execition timeout : "
.size .L.str.21, 28
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz " --- Memory Information for device %d ---\n"
.size .L.str.22, 45
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Total global mem: %ld\n"
.size .L.str.23, 24
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "Total constant Mem: %ld\n"
.size .L.str.24, 26
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "Max mem pitch: %ld\n"
.size .L.str.25, 21
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "Texture Alignment: %ld\n"
.size .L.str.26, 25
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz " --- MP Information for device %d ---\n"
.size .L.str.27, 41
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "Multiprocessor count: %d\n"
.size .L.str.28, 27
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "Shared mem per mp: %ld\n"
.size .L.str.29, 25
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz "Registers per mp: %d\n"
.size .L.str.30, 23
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz "Threads in warp: %d\n"
.size .L.str.31, 22
.type .L.str.32,@object # @.str.32
.L.str.32:
.asciz "Max threads per block: %d\n"
.size .L.str.32, 28
.type .L.str.33,@object # @.str.33
.L.str.33:
.asciz "Max thread dimensions: (%d, %d, %d)\n"
.size .L.str.33, 38
.type .L.str.34,@object # @.str.34
.L.str.34:
.asciz "Max grid dimensions: (%d, %d, %d)\n"
.size .L.str.34, 36
.type .L.str.35,@object # @.str.35
.L.str.35:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.35, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7readcmpPcS_S_mjjjS_jjj"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6reducePcS_mjjj"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nUsage:"
.size .Lstr, 8
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\t./a.out <file_1> <file_2> <num_genomes> <genome_len> <errors> <vicinity> <adj_errs>\n"
.size .Lstr.1, 86
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "init_data - malloc failed"
.size .Lstr.3, 26
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Failed to read from the file"
.size .Lstr.4, 29
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "Disabled"
.size .Lstr.7, 9
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "Enabled"
.size .Lstr.8, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__readcmpPcS_S_mjjjS_jjj
.addrsig_sym _Z21__device_stub__reducePcS_mjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7readcmpPcS_S_mjjjS_jjj
.addrsig_sym _Z6reducePcS_mjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <thrust/random.h>
#include <thrust/inner_product.h>
#include <thrust/binary_search.h>
#include <thrust/adjacent_difference.h>
#include <thrust/iterator/constant_iterator.h>
#include <thrust/iterator/counting_iterator.h>
#include <iostream>
#include <iomanip>
#include <iterator>
// simple routine to print contents of a vector
template <typename Vector>
void print_vector(const std::string& name, const Vector& v)
{
typedef typename Vector::value_type T;
std::cout << " " << std::setw(20) << name << " ";
thrust::copy(v.begin(), v.end(), std::ostream_iterator<T>(std::cout, " "));
std::cout << std::endl;
}
// dense histogram using binary search
template <typename Vector1,
typename Vector2>
void dense_histogram(const Vector1& input,
Vector2& histogram)
{
typedef typename Vector1::value_type ValueType; // input value type
typedef typename Vector2::value_type IndexType; // histogram index type
// copy input data (could be skipped if input is allowed to be modified)
thrust::device_vector<ValueType> data(input);
// print the initial data
print_vector("initial data", data);
// sort data to bring equal elements together
thrust::sort(data.begin(), data.end());
// print the sorted data
print_vector("sorted data", data);
// number of histogram bins is equal to the maximum value plus one
IndexType num_bins = data.back() + 1;
// resize histogram storage
histogram.resize(num_bins);
// find the end of each bin of values
thrust::counting_iterator<IndexType> search_begin(0);
thrust::upper_bound(data.begin(), data.end(),
search_begin, search_begin + num_bins,
histogram.begin());
// print the cumulative histogram
print_vector("cumulative histogram", histogram);
// compute the histogram by taking differences of the cumulative histogram
thrust::adjacent_difference(histogram.begin(), histogram.end(),
histogram.begin());
// print the histogram
print_vector("histogram", histogram);
}
// sparse histogram using reduce_by_key
template <typename Vector1,
typename Vector2,
typename Vector3>
void sparse_histogram(const Vector1& input,
Vector2& histogram_values,
Vector3& histogram_counts)
{
typedef typename Vector1::value_type ValueType; // input value type
typedef typename Vector3::value_type IndexType; // histogram index type
// copy input data (could be skipped if input is allowed to be modified)
thrust::device_vector<ValueType> data(input);
// print the initial data
print_vector("initial data", data);
// sort data to bring equal elements together
thrust::sort(data.begin(), data.end());
// print the sorted data
print_vector("sorted data", data);
// number of histogram bins is equal to number of unique values (assumes data.size() > 0)
IndexType num_bins = thrust::inner_product(data.begin(), data.end() - 1,
data.begin() + 1,
IndexType(1),
thrust::plus<IndexType>(),
thrust::not_equal_to<ValueType>());
// resize histogram storage
histogram_values.resize(num_bins);
histogram_counts.resize(num_bins);
// compact find the end of each bin of values
thrust::reduce_by_key(data.begin(), data.end(),
thrust::constant_iterator<IndexType>(1),
histogram_values.begin(),
histogram_counts.begin());
// print the sparse histogram
print_vector("histogram values", histogram_values);
print_vector("histogram counts", histogram_counts);
}
int main(void)
{
thrust::default_random_engine rng;
thrust::uniform_int_distribution<int> dist(0, 9);
const int N = 40;
const int S = 4;
// generate random data on the host
thrust::host_vector<int> input(N);
for(int i = 0; i < N; i++)
{
int sum = 0;
for (int j = 0; j < S; j++)
sum += dist(rng);
input[i] = sum / S;
}
// demonstrate dense histogram method
{
std::cout << "Dense Histogram" << std::endl;
thrust::device_vector<int> histogram;
dense_histogram(input, histogram);
}
// demonstrate sparse histogram method
{
std::cout << "Sparse Histogram" << std::endl;
thrust::device_vector<int> histogram_values;
thrust::device_vector<int> histogram_counts;
sparse_histogram(input, histogram_values, histogram_counts);
}
// Note:
// A dense histogram can be converted to a sparse histogram
// using stream compaction (i.e. thrust::copy_if).
// A sparse histogram can be expanded into a dense histogram
// by initializing the dense histogram to zero (with thrust::fill)
// and then scattering the histogram counts (with thrust::scatter).
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/sort.h>
#include <thrust/copy.h>
#include <thrust/random.h>
#include <thrust/inner_product.h>
#include <thrust/binary_search.h>
#include <thrust/adjacent_difference.h>
#include <thrust/iterator/constant_iterator.h>
#include <thrust/iterator/counting_iterator.h>
#include <iostream>
#include <iomanip>
#include <iterator>
// simple routine to print contents of a vector
template <typename Vector>
void print_vector(const std::string& name, const Vector& v)
{
typedef typename Vector::value_type T;
std::cout << " " << std::setw(20) << name << " ";
thrust::copy(v.begin(), v.end(), std::ostream_iterator<T>(std::cout, " "));
std::cout << std::endl;
}
// dense histogram using binary search
template <typename Vector1,
typename Vector2>
void dense_histogram(const Vector1& input,
Vector2& histogram)
{
typedef typename Vector1::value_type ValueType; // input value type
typedef typename Vector2::value_type IndexType; // histogram index type
// copy input data (could be skipped if input is allowed to be modified)
thrust::device_vector<ValueType> data(input);
// print the initial data
print_vector("initial data", data);
// sort data to bring equal elements together
thrust::sort(data.begin(), data.end());
// print the sorted data
print_vector("sorted data", data);
// number of histogram bins is equal to the maximum value plus one
IndexType num_bins = data.back() + 1;
// resize histogram storage
histogram.resize(num_bins);
// find the end of each bin of values
thrust::counting_iterator<IndexType> search_begin(0);
thrust::upper_bound(data.begin(), data.end(),
search_begin, search_begin + num_bins,
histogram.begin());
// print the cumulative histogram
print_vector("cumulative histogram", histogram);
// compute the histogram by taking differences of the cumulative histogram
thrust::adjacent_difference(histogram.begin(), histogram.end(),
histogram.begin());
// print the histogram
print_vector("histogram", histogram);
}
// sparse histogram using reduce_by_key
template <typename Vector1,
typename Vector2,
typename Vector3>
void sparse_histogram(const Vector1& input,
Vector2& histogram_values,
Vector3& histogram_counts)
{
typedef typename Vector1::value_type ValueType; // input value type
typedef typename Vector3::value_type IndexType; // histogram index type
// copy input data (could be skipped if input is allowed to be modified)
thrust::device_vector<ValueType> data(input);
// print the initial data
print_vector("initial data", data);
// sort data to bring equal elements together
thrust::sort(data.begin(), data.end());
// print the sorted data
print_vector("sorted data", data);
// number of histogram bins is equal to number of unique values (assumes data.size() > 0)
IndexType num_bins = thrust::inner_product(data.begin(), data.end() - 1,
data.begin() + 1,
IndexType(1),
thrust::plus<IndexType>(),
thrust::not_equal_to<ValueType>());
// resize histogram storage
histogram_values.resize(num_bins);
histogram_counts.resize(num_bins);
// compact find the end of each bin of values
thrust::reduce_by_key(data.begin(), data.end(),
thrust::constant_iterator<IndexType>(1),
histogram_values.begin(),
histogram_counts.begin());
// print the sparse histogram
print_vector("histogram values", histogram_values);
print_vector("histogram counts", histogram_counts);
}
int main(void)
{
thrust::default_random_engine rng;
thrust::uniform_int_distribution<int> dist(0, 9);
const int N = 40;
const int S = 4;
// generate random data on the host
thrust::host_vector<int> input(N);
for(int i = 0; i < N; i++)
{
int sum = 0;
for (int j = 0; j < S; j++)
sum += dist(rng);
input[i] = sum / S;
}
// demonstrate dense histogram method
{
std::cout << "Dense Histogram" << std::endl;
thrust::device_vector<int> histogram;
dense_histogram(input, histogram);
}
// demonstrate sparse histogram method
{
std::cout << "Sparse Histogram" << std::endl;
thrust::device_vector<int> histogram_values;
thrust::device_vector<int> histogram_counts;
sparse_histogram(input, histogram_values, histogram_counts);
}
// Note:
// A dense histogram can be converted to a sparse histogram
// using stream compaction (i.e. thrust::copy_if).
// A sparse histogram can be expanded into a dense histogram
// by initializing the dense histogram to zero (with thrust::fill)
// and then scattering the histogram counts (with thrust::scatter).
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ac_kernel1 ( int *d_state_transition, unsigned int *d_state_supply, unsigned int *d_state_final, unsigned char *d_text, unsigned int *d_out, size_t pitch, int m, int n, int p_size, int alphabet, int numBlocks ) {
//int idx = blockIdx.x * blockDim.x + threadIdx.x;
int effective_pitch = pitch / sizeof ( int );
int charactersPerBlock = n / numBlocks;
int startBlock = blockIdx.x * charactersPerBlock;
int stopBlock = startBlock + charactersPerBlock;
int charactersPerThread = ( stopBlock - startBlock ) / blockDim.x;
int startThread = startBlock + charactersPerThread * threadIdx.x;
int stopThread;
if( blockIdx.x == numBlocks -1 && threadIdx.x==blockDim.x-1)
stopThread = n - 1;
else stopThread = startThread + charactersPerThread + m-1;
int r = 0, s;
int column;
//cuPrintf("Working from %i to %i chars %i\n", startThread, stopThread, charactersPerThread);
for ( column = startThread; ( column < stopThread && column < n ); column++ ) {
while ( ( s = d_state_transition[r * effective_pitch + (d_text[column]-(unsigned char)'A')] ) == -1 )
r = d_state_supply[r];
r = s;
d_out[column] = d_state_final[r];
}
} | code for sm_80
Function : _Z10ac_kernel1PiPjS0_PhS0_miiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R5, c[0x0][0x1a0] ; /* 0x0000680000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC UR4, c[0x0][0x194] ; /* 0x0000650000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IABS R6, c[0x0][0x194] ; /* 0x0000650000067a13 */
/* 0x000fe20000000000 */
/*0040*/ ULDC UR5, c[0x0][0x1a0] ; /* 0x0000680000057ab9 */
/* 0x000fe20000000800 */
/*0050*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e220000209400 */
/*0060*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fcc000f8e3c3f */
/*0070*/ ISETP.LE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fca000bf23270 */
/*0080*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e620000002500 */
/*0090*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00a0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0000a4000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x004fc800078e0a03 */
/*00e0*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe400078e02ff */
/*00f0*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e240000209000 */
/*0100*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0110*/ IMAD.HI.U32 R0, R3, R6, RZ ; /* 0x0000000603007227 */
/* 0x000fc800078e00ff */
/*0120*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a00 */
/*0130*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e260000001000 */
/*0140*/ IMAD R2, R5, R3, R6 ; /* 0x0000000305027224 */
/* 0x000fca00078e0206 */
/*0150*/ ISETP.GT.U32.AND P2, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fe40003f44070 */
/*0160*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fd60007ffe0ff */
/*0170*/ @!P2 IMAD.IADD R2, R2, 0x1, -R5 ; /* 0x000000010202a824 */
/* 0x000fe200078e0a05 */
/*0180*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe20007ffe0ff */
/*0190*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e22000021f000 */
/*01a0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x1a0], PT ; /* 0x00006800ff007a0c */
/* 0x000fe40003f45270 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe20003f06070 */
/*01c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x001fd400078e0a03 */
/*01e0*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x000fc800078e02ff */
/*0200*/ @!P1 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff009224 */
/* 0x000fe200078e0a00 */
/*0210*/ @!P2 LOP3.LUT R0, RZ, c[0x0][0x1a0], RZ, 0x33, !PT ; /* 0x00006800ff00aa12 */
/* 0x000fe200078e33ff */
/*0220*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe200078e0002 */
/*0230*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fca0003f45070 */
/*0240*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0250*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0260*/ IMAD R2, R5, c[0x0][0x0], R0 ; /* 0x0000000005027a24 */
/* 0x000fe400078e0200 */
/*0270*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0280*/ IMAD R0, R0, UR4, RZ ; /* 0x0000000400007c24 */
/* 0x002fe4000f8e02ff */
/*0290*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x0], PT ; /* 0x0000000002007a0c */
/* 0x000fda0003f06070 */
/*02a0*/ @P0 IADD3 R2, R2, -c[0x0][0x0], RZ ; /* 0x8000000002020a10 */
/* 0x000fe40007ffe0ff */
/*02b0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x0], PT ; /* 0x0000000002007a0c */
/* 0x000fe20003f26070 */
/*02d0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fca00078e00ff */
/*02e0*/ IADD3 R4, -R2.reuse, c[0x0][0x1a0], RZ ; /* 0x0000680002047a10 */
/* 0x040fe40007ffe1ff */
/*02f0*/ IADD3 R2, -R2, c[0x0][0x0], RZ ; /* 0x0000000002027a10 */
/* 0x000fe40007ffe1ff */
/*0300*/ ISETP.NE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fc6000bf05270 */
/*0310*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0320*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fe400078e33ff */
/*0330*/ ISETP.EQ.AND P0, PT, R5, R2, !P0 ; /* 0x000000020500720c */
/* 0x001fc60004702270 */
/*0340*/ IMAD R0, R3, R5, R0 ; /* 0x0000000503007224 */
/* 0x000fca00078e0200 */
/*0350*/ IADD3 R3, R0, c[0x0][0x190], R3 ; /* 0x0000640000037a10 */
/* 0x000fc80007ffe003 */
/*0360*/ SEL R3, R3, c[0x0][0x194], !P0 ; /* 0x0000650003037a07 */
/* 0x000fe40004000000 */
/*0370*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x194], PT ; /* 0x0000650000007a0c */
/* 0x000fe40003f06270 */
/*0380*/ IADD3 R11, R3, -0x1, RZ ; /* 0xffffffff030b7810 */
/* 0x000fc80007ffe0ff */
/*0390*/ ISETP.GE.OR P0, PT, R0, R11, P0 ; /* 0x0000000b0000720c */
/* 0x000fda0000706670 */
/*03a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*03c0*/ ULDC.64 UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */
/* 0x000fe40000000a00 */
/*03d0*/ USHF.R.U64 UR4, UR4, 0x2, UR5 ; /* 0x0000000204047899 */
/* 0x000fe40008001205 */
/*03e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*03f0*/ SHF.R.S32.HI R13, RZ, 0x1f, R0 ; /* 0x0000001fff0d7819 */
/* 0x000fe40000011400 */
/*0400*/ IADD3 R4, P0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x001fc80007f1e0ff */
/*0410*/ IADD3.X R5, R13, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000d057a10 */
/* 0x000fca00007fe4ff */
/*0420*/ LDG.E.U8 R15, [R4.64] ; /* 0x00000006040f7981 */
/* 0x000ea2000c1e1100 */
/*0430*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe400078e00ff */
/*0440*/ IMAD R2, R6, UR4, R15 ; /* 0x0000000406027c24 */
/* 0x004fca000f8e020f */
/*0450*/ IADD3 R2, R2, -0x41, RZ ; /* 0xffffffbf02027810 */
/* 0x000fca0007ffe0ff */
/*0460*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0209 */
/*0470*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea2000c1e1900 */
/*0480*/ BSSY B0, 0x560 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0490*/ ISETP.NE.AND P0, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x004fda0003f05270 */
/*04a0*/ @P0 BRA 0x550 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*04b0*/ BSSY B1, 0x550 ; /* 0x0000009000017945 */
/* 0x000fe40003800000 */
/*04c0*/ IMAD.WIDE R2, R6, R9, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0209 */
/*04d0*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ IMAD R4, R6, UR4, R15 ; /* 0x0000000406047c24 */
/* 0x004fca000f8e020f */
/*04f0*/ IADD3 R4, R4, -0x41, RZ ; /* 0xffffffbf04047810 */
/* 0x000fca0007ffe0ff */
/*0500*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0209 */
/*0510*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000ea4000c1e1900 */
/*0520*/ ISETP.NE.AND P0, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x004fda0003f05270 */
/*0530*/ @!P0 BRA 0x4c0 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0540*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0550*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0560*/ IMAD.WIDE R2, R7, R9, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fcc00078e0209 */
/*0570*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0580*/ LEA R4, P0, R0, c[0x0][0x180], 0x2 ; /* 0x0000600000047a11 */
/* 0x000fe200078010ff */
/*0590*/ IMAD.MOV.U32 R6, RZ, RZ, R7 ; /* 0x000000ffff067224 */
/* 0x000fc600078e0007 */
/*05a0*/ LEA.HI.X R5, R0.reuse, c[0x0][0x184], R13, 0x2, P0 ; /* 0x0000610000057a11 */
/* 0x040fe400000f140d */
/*05b0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GE.AND P0, PT, R0.reuse, R11, PT ; /* 0x0000000b0000720c */
/* 0x040fe40003f06270 */
/*05d0*/ ISETP.LT.AND P1, PT, R0, c[0x0][0x194], PT ; /* 0x0000650000007a0c */
/* 0x000fe20003f21270 */
/*05e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041d8000c101906 */
/*05f0*/ @!P0 BRA P1, 0x3f0 ; /* 0xfffffdf000008947 */
/* 0x000fea000083ffff */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ac_kernel1 ( int *d_state_transition, unsigned int *d_state_supply, unsigned int *d_state_final, unsigned char *d_text, unsigned int *d_out, size_t pitch, int m, int n, int p_size, int alphabet, int numBlocks ) {
//int idx = blockIdx.x * blockDim.x + threadIdx.x;
int effective_pitch = pitch / sizeof ( int );
int charactersPerBlock = n / numBlocks;
int startBlock = blockIdx.x * charactersPerBlock;
int stopBlock = startBlock + charactersPerBlock;
int charactersPerThread = ( stopBlock - startBlock ) / blockDim.x;
int startThread = startBlock + charactersPerThread * threadIdx.x;
int stopThread;
if( blockIdx.x == numBlocks -1 && threadIdx.x==blockDim.x-1)
stopThread = n - 1;
else stopThread = startThread + charactersPerThread + m-1;
int r = 0, s;
int column;
//cuPrintf("Working from %i to %i chars %i\n", startThread, stopThread, charactersPerThread);
for ( column = startThread; ( column < stopThread && column < n ); column++ ) {
while ( ( s = d_state_transition[r * effective_pitch + (d_text[column]-(unsigned char)'A')] ) == -1 )
r = d_state_supply[r];
r = s;
d_out[column] = d_state_final[r];
}
} | .file "tmpxft_0016862c_00000000-6_ac_kernel1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z10ac_kernel1PiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii
.type _Z46__device_stub__Z10ac_kernel1PiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii, @function
_Z46__device_stub__Z10ac_kernel1PiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10ac_kernel1PiPjS0_PhS0_miiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z10ac_kernel1PiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii, .-_Z46__device_stub__Z10ac_kernel1PiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii
.globl _Z10ac_kernel1PiPjS0_PhS0_miiiii
.type _Z10ac_kernel1PiPjS0_PhS0_miiiii, @function
_Z10ac_kernel1PiPjS0_PhS0_miiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z46__device_stub__Z10ac_kernel1PiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10ac_kernel1PiPjS0_PhS0_miiiii, .-_Z10ac_kernel1PiPjS0_PhS0_miiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10ac_kernel1PiPjS0_PhS0_miiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10ac_kernel1PiPjS0_PhS0_miiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ac_kernel1 ( int *d_state_transition, unsigned int *d_state_supply, unsigned int *d_state_final, unsigned char *d_text, unsigned int *d_out, size_t pitch, int m, int n, int p_size, int alphabet, int numBlocks ) {
//int idx = blockIdx.x * blockDim.x + threadIdx.x;
int effective_pitch = pitch / sizeof ( int );
int charactersPerBlock = n / numBlocks;
int startBlock = blockIdx.x * charactersPerBlock;
int stopBlock = startBlock + charactersPerBlock;
int charactersPerThread = ( stopBlock - startBlock ) / blockDim.x;
int startThread = startBlock + charactersPerThread * threadIdx.x;
int stopThread;
if( blockIdx.x == numBlocks -1 && threadIdx.x==blockDim.x-1)
stopThread = n - 1;
else stopThread = startThread + charactersPerThread + m-1;
int r = 0, s;
int column;
//cuPrintf("Working from %i to %i chars %i\n", startThread, stopThread, charactersPerThread);
for ( column = startThread; ( column < stopThread && column < n ); column++ ) {
while ( ( s = d_state_transition[r * effective_pitch + (d_text[column]-(unsigned char)'A')] ) == -1 )
r = d_state_supply[r];
r = s;
d_out[column] = d_state_final[r];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ac_kernel1 ( int *d_state_transition, unsigned int *d_state_supply, unsigned int *d_state_final, unsigned char *d_text, unsigned int *d_out, size_t pitch, int m, int n, int p_size, int alphabet, int numBlocks ) {
//int idx = blockIdx.x * blockDim.x + threadIdx.x;
int effective_pitch = pitch / sizeof ( int );
int charactersPerBlock = n / numBlocks;
int startBlock = blockIdx.x * charactersPerBlock;
int stopBlock = startBlock + charactersPerBlock;
int charactersPerThread = ( stopBlock - startBlock ) / blockDim.x;
int startThread = startBlock + charactersPerThread * threadIdx.x;
int stopThread;
if( blockIdx.x == numBlocks -1 && threadIdx.x==blockDim.x-1)
stopThread = n - 1;
else stopThread = startThread + charactersPerThread + m-1;
int r = 0, s;
int column;
//cuPrintf("Working from %i to %i chars %i\n", startThread, stopThread, charactersPerThread);
for ( column = startThread; ( column < stopThread && column < n ); column++ ) {
while ( ( s = d_state_transition[r * effective_pitch + (d_text[column]-(unsigned char)'A')] ) == -1 )
r = d_state_supply[r];
r = s;
d_out[column] = d_state_final[r];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ac_kernel1 ( int *d_state_transition, unsigned int *d_state_supply, unsigned int *d_state_final, unsigned char *d_text, unsigned int *d_out, size_t pitch, int m, int n, int p_size, int alphabet, int numBlocks ) {
//int idx = blockIdx.x * blockDim.x + threadIdx.x;
int effective_pitch = pitch / sizeof ( int );
int charactersPerBlock = n / numBlocks;
int startBlock = blockIdx.x * charactersPerBlock;
int stopBlock = startBlock + charactersPerBlock;
int charactersPerThread = ( stopBlock - startBlock ) / blockDim.x;
int startThread = startBlock + charactersPerThread * threadIdx.x;
int stopThread;
if( blockIdx.x == numBlocks -1 && threadIdx.x==blockDim.x-1)
stopThread = n - 1;
else stopThread = startThread + charactersPerThread + m-1;
int r = 0, s;
int column;
//cuPrintf("Working from %i to %i chars %i\n", startThread, stopThread, charactersPerThread);
for ( column = startThread; ( column < stopThread && column < n ); column++ ) {
while ( ( s = d_state_transition[r * effective_pitch + (d_text[column]-(unsigned char)'A')] ) == -1 )
r = d_state_supply[r];
r = s;
d_out[column] = d_state_final[r];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10ac_kernel1PiPjS0_PhS0_miiiii
.globl _Z10ac_kernel1PiPjS0_PhS0_miiiii
.p2align 8
.type _Z10ac_kernel1PiPjS0_PhS0_miiiii,@function
_Z10ac_kernel1PiPjS0_PhS0_miiiii:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x40
s_load_b32 s4, s[0:1], 0x54
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s5, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s5, s6
s_xor_b32 s7, s2, s6
s_load_b64 s[2:3], s[0:1], 0x30
v_cvt_f32_u32_e32 v1, s7
s_sub_i32 s9, 0, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s10, s3, 31
v_cvt_u32_f32_e32 v1, v1
s_add_i32 s11, s3, s10
s_xor_b32 s6, s10, s6
s_xor_b32 s11, s11, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s8, v1
s_mul_i32 s9, s9, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s9, s8, s9
s_add_i32 s8, s8, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s8, s11, s8
s_mul_i32 s9, s8, s7
s_add_i32 s10, s8, 1
s_sub_i32 s9, s11, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s11, s9, s7
s_cmp_ge_u32 s9, s7
s_cselect_b32 s8, s10, s8
s_cselect_b32 s9, s11, s9
s_add_i32 s10, s8, 1
s_cmp_ge_u32 s9, s7
s_cselect_b32 s7, s10, s8
s_and_b32 s8, s4, 0xffff
s_xor_b32 s7, s7, s6
v_cvt_f32_u32_e32 v1, s8
s_sub_i32 s9, 0, s8
s_sub_i32 s6, s7, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s4, v1
s_mul_i32 s9, s9, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s9, s4, s9
s_add_i32 s4, s4, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s6, s4
s_mul_i32 s7, s4, s8
s_add_i32 s9, s4, 1
s_sub_i32 s7, s6, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s10, s7, s8
s_cmp_ge_u32 s7, s8
s_cselect_b32 s9, s9, s4
s_cselect_b32 s4, s10, s7
s_add_i32 s7, s9, 1
s_cmp_ge_u32 s4, s8
s_mul_i32 s4, s6, s15
s_cselect_b32 s6, s7, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s6, v0, s[4:5]
s_add_i32 s5, s5, -1
s_cmp_eq_u32 s15, s5
s_cselect_b32 s4, -1, 0
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, s8, v0
v_add3_u32 v0, s6, s2, v1
s_and_b32 s2, s4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v0, v0, s3, s2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, -1, v0
v_min_i32_e32 v0, s3, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v1, v0
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x20
s_load_b256 s[4:11], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_alignbit_b32 v6, s15, s14, 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_co_u32 v7, vcc_lo, s8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, v1, v0
global_load_b32 v5, v[7:8], off
v_add_co_u32 v7, s0, s12, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, s13, v3, s0
v_mov_b32_e32 v3, v4
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
global_store_b32 v[7:8], v5, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v4, vcc_lo, s10, v1
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v2, vcc_lo
global_load_u8 v5, v[4:5], off
v_mul_lo_u32 v4, v3, v6
s_waitcnt vmcnt(0)
v_add3_u32 v7, v4, v5, 0xffffffbf
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v4, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 -1, v4
s_cbranch_execz .LBB0_2
s_mov_b32 s1, 0
.p2align 6
.LBB0_5:
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, v3, v6
v_add3_u32 v7, v4, v5, 0xffffffbf
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v4, v[7:8], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s1
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10ac_kernel1PiPjS0_PhS0_miiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10ac_kernel1PiPjS0_PhS0_miiiii, .Lfunc_end0-_Z10ac_kernel1PiPjS0_PhS0_miiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10ac_kernel1PiPjS0_PhS0_miiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10ac_kernel1PiPjS0_PhS0_miiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ac_kernel1 ( int *d_state_transition, unsigned int *d_state_supply, unsigned int *d_state_final, unsigned char *d_text, unsigned int *d_out, size_t pitch, int m, int n, int p_size, int alphabet, int numBlocks ) {
//int idx = blockIdx.x * blockDim.x + threadIdx.x;
int effective_pitch = pitch / sizeof ( int );
int charactersPerBlock = n / numBlocks;
int startBlock = blockIdx.x * charactersPerBlock;
int stopBlock = startBlock + charactersPerBlock;
int charactersPerThread = ( stopBlock - startBlock ) / blockDim.x;
int startThread = startBlock + charactersPerThread * threadIdx.x;
int stopThread;
if( blockIdx.x == numBlocks -1 && threadIdx.x==blockDim.x-1)
stopThread = n - 1;
else stopThread = startThread + charactersPerThread + m-1;
int r = 0, s;
int column;
//cuPrintf("Working from %i to %i chars %i\n", startThread, stopThread, charactersPerThread);
for ( column = startThread; ( column < stopThread && column < n ); column++ ) {
while ( ( s = d_state_transition[r * effective_pitch + (d_text[column]-(unsigned char)'A')] ) == -1 )
r = d_state_supply[r];
r = s;
d_out[column] = d_state_final[r];
}
} | .text
.file "ac_kernel1.hip"
.globl _Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii # -- Begin function _Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii
.p2align 4, 0x90
.type _Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii,@function
_Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii: # @_Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10ac_kernel1PiPjS0_PhS0_miiiii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii, .Lfunc_end0-_Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10ac_kernel1PiPjS0_PhS0_miiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10ac_kernel1PiPjS0_PhS0_miiiii,@object # @_Z10ac_kernel1PiPjS0_PhS0_miiiii
.section .rodata,"a",@progbits
.globl _Z10ac_kernel1PiPjS0_PhS0_miiiii
.p2align 3, 0x0
_Z10ac_kernel1PiPjS0_PhS0_miiiii:
.quad _Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii
.size _Z10ac_kernel1PiPjS0_PhS0_miiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10ac_kernel1PiPjS0_PhS0_miiiii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10ac_kernel1PiPjS0_PhS0_miiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10ac_kernel1PiPjS0_PhS0_miiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R5, c[0x0][0x1a0] ; /* 0x0000680000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC UR4, c[0x0][0x194] ; /* 0x0000650000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IABS R6, c[0x0][0x194] ; /* 0x0000650000067a13 */
/* 0x000fe20000000000 */
/*0040*/ ULDC UR5, c[0x0][0x1a0] ; /* 0x0000680000057ab9 */
/* 0x000fe20000000800 */
/*0050*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e220000209400 */
/*0060*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fcc000f8e3c3f */
/*0070*/ ISETP.LE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fca000bf23270 */
/*0080*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e620000002500 */
/*0090*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00a0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0000a4000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x004fc800078e0a03 */
/*00e0*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe400078e02ff */
/*00f0*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e240000209000 */
/*0100*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0110*/ IMAD.HI.U32 R0, R3, R6, RZ ; /* 0x0000000603007227 */
/* 0x000fc800078e00ff */
/*0120*/ IMAD.MOV R3, RZ, RZ, -R0 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a00 */
/*0130*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e260000001000 */
/*0140*/ IMAD R2, R5, R3, R6 ; /* 0x0000000305027224 */
/* 0x000fca00078e0206 */
/*0150*/ ISETP.GT.U32.AND P2, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fe40003f44070 */
/*0160*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fd60007ffe0ff */
/*0170*/ @!P2 IMAD.IADD R2, R2, 0x1, -R5 ; /* 0x000000010202a824 */
/* 0x000fe200078e0a05 */
/*0180*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe20007ffe0ff */
/*0190*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e22000021f000 */
/*01a0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x1a0], PT ; /* 0x00006800ff007a0c */
/* 0x000fe40003f45270 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe20003f06070 */
/*01c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x001fd400078e0a03 */
/*01e0*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ IMAD R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a24 */
/* 0x000fc800078e02ff */
/*0200*/ @!P1 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff009224 */
/* 0x000fe200078e0a00 */
/*0210*/ @!P2 LOP3.LUT R0, RZ, c[0x0][0x1a0], RZ, 0x33, !PT ; /* 0x00006800ff00aa12 */
/* 0x000fe200078e33ff */
/*0220*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe200078e0002 */
/*0230*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fca0003f45070 */
/*0240*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0250*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0260*/ IMAD R2, R5, c[0x0][0x0], R0 ; /* 0x0000000005027a24 */
/* 0x000fe400078e0200 */
/*0270*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0280*/ IMAD R0, R0, UR4, RZ ; /* 0x0000000400007c24 */
/* 0x002fe4000f8e02ff */
/*0290*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x0], PT ; /* 0x0000000002007a0c */
/* 0x000fda0003f06070 */
/*02a0*/ @P0 IADD3 R2, R2, -c[0x0][0x0], RZ ; /* 0x8000000002020a10 */
/* 0x000fe40007ffe0ff */
/*02b0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x0], PT ; /* 0x0000000002007a0c */
/* 0x000fe20003f26070 */
/*02d0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fca00078e00ff */
/*02e0*/ IADD3 R4, -R2.reuse, c[0x0][0x1a0], RZ ; /* 0x0000680002047a10 */
/* 0x040fe40007ffe1ff */
/*02f0*/ IADD3 R2, -R2, c[0x0][0x0], RZ ; /* 0x0000000002027a10 */
/* 0x000fe40007ffe1ff */
/*0300*/ ISETP.NE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fc6000bf05270 */
/*0310*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0320*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fe400078e33ff */
/*0330*/ ISETP.EQ.AND P0, PT, R5, R2, !P0 ; /* 0x000000020500720c */
/* 0x001fc60004702270 */
/*0340*/ IMAD R0, R3, R5, R0 ; /* 0x0000000503007224 */
/* 0x000fca00078e0200 */
/*0350*/ IADD3 R3, R0, c[0x0][0x190], R3 ; /* 0x0000640000037a10 */
/* 0x000fc80007ffe003 */
/*0360*/ SEL R3, R3, c[0x0][0x194], !P0 ; /* 0x0000650003037a07 */
/* 0x000fe40004000000 */
/*0370*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x194], PT ; /* 0x0000650000007a0c */
/* 0x000fe40003f06270 */
/*0380*/ IADD3 R11, R3, -0x1, RZ ; /* 0xffffffff030b7810 */
/* 0x000fc80007ffe0ff */
/*0390*/ ISETP.GE.OR P0, PT, R0, R11, P0 ; /* 0x0000000b0000720c */
/* 0x000fda0000706670 */
/*03a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*03c0*/ ULDC.64 UR4, c[0x0][0x188] ; /* 0x0000620000047ab9 */
/* 0x000fe40000000a00 */
/*03d0*/ USHF.R.U64 UR4, UR4, 0x2, UR5 ; /* 0x0000000204047899 */
/* 0x000fe40008001205 */
/*03e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*03f0*/ SHF.R.S32.HI R13, RZ, 0x1f, R0 ; /* 0x0000001fff0d7819 */
/* 0x000fe40000011400 */
/*0400*/ IADD3 R4, P0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x001fc80007f1e0ff */
/*0410*/ IADD3.X R5, R13, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000d057a10 */
/* 0x000fca00007fe4ff */
/*0420*/ LDG.E.U8 R15, [R4.64] ; /* 0x00000006040f7981 */
/* 0x000ea2000c1e1100 */
/*0430*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe400078e00ff */
/*0440*/ IMAD R2, R6, UR4, R15 ; /* 0x0000000406027c24 */
/* 0x004fca000f8e020f */
/*0450*/ IADD3 R2, R2, -0x41, RZ ; /* 0xffffffbf02027810 */
/* 0x000fca0007ffe0ff */
/*0460*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0209 */
/*0470*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea2000c1e1900 */
/*0480*/ BSSY B0, 0x560 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0490*/ ISETP.NE.AND P0, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x004fda0003f05270 */
/*04a0*/ @P0 BRA 0x550 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*04b0*/ BSSY B1, 0x550 ; /* 0x0000009000017945 */
/* 0x000fe40003800000 */
/*04c0*/ IMAD.WIDE R2, R6, R9, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0209 */
/*04d0*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ IMAD R4, R6, UR4, R15 ; /* 0x0000000406047c24 */
/* 0x004fca000f8e020f */
/*04f0*/ IADD3 R4, R4, -0x41, RZ ; /* 0xffffffbf04047810 */
/* 0x000fca0007ffe0ff */
/*0500*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0209 */
/*0510*/ LDG.E R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x000ea4000c1e1900 */
/*0520*/ ISETP.NE.AND P0, PT, R7, -0x1, PT ; /* 0xffffffff0700780c */
/* 0x004fda0003f05270 */
/*0530*/ @!P0 BRA 0x4c0 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0540*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0550*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0560*/ IMAD.WIDE R2, R7, R9, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x000fcc00078e0209 */
/*0570*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0580*/ LEA R4, P0, R0, c[0x0][0x180], 0x2 ; /* 0x0000600000047a11 */
/* 0x000fe200078010ff */
/*0590*/ IMAD.MOV.U32 R6, RZ, RZ, R7 ; /* 0x000000ffff067224 */
/* 0x000fc600078e0007 */
/*05a0*/ LEA.HI.X R5, R0.reuse, c[0x0][0x184], R13, 0x2, P0 ; /* 0x0000610000057a11 */
/* 0x040fe400000f140d */
/*05b0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GE.AND P0, PT, R0.reuse, R11, PT ; /* 0x0000000b0000720c */
/* 0x040fe40003f06270 */
/*05d0*/ ISETP.LT.AND P1, PT, R0, c[0x0][0x194], PT ; /* 0x0000650000007a0c */
/* 0x000fe20003f21270 */
/*05e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041d8000c101906 */
/*05f0*/ @!P0 BRA P1, 0x3f0 ; /* 0xfffffdf000008947 */
/* 0x000fea000083ffff */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10ac_kernel1PiPjS0_PhS0_miiiii
.globl _Z10ac_kernel1PiPjS0_PhS0_miiiii
.p2align 8
.type _Z10ac_kernel1PiPjS0_PhS0_miiiii,@function
_Z10ac_kernel1PiPjS0_PhS0_miiiii:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x40
s_load_b32 s4, s[0:1], 0x54
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s5, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s5, s6
s_xor_b32 s7, s2, s6
s_load_b64 s[2:3], s[0:1], 0x30
v_cvt_f32_u32_e32 v1, s7
s_sub_i32 s9, 0, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s10, s3, 31
v_cvt_u32_f32_e32 v1, v1
s_add_i32 s11, s3, s10
s_xor_b32 s6, s10, s6
s_xor_b32 s11, s11, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s8, v1
s_mul_i32 s9, s9, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s9, s8, s9
s_add_i32 s8, s8, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s8, s11, s8
s_mul_i32 s9, s8, s7
s_add_i32 s10, s8, 1
s_sub_i32 s9, s11, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s11, s9, s7
s_cmp_ge_u32 s9, s7
s_cselect_b32 s8, s10, s8
s_cselect_b32 s9, s11, s9
s_add_i32 s10, s8, 1
s_cmp_ge_u32 s9, s7
s_cselect_b32 s7, s10, s8
s_and_b32 s8, s4, 0xffff
s_xor_b32 s7, s7, s6
v_cvt_f32_u32_e32 v1, s8
s_sub_i32 s9, 0, s8
s_sub_i32 s6, s7, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s4, v1
s_mul_i32 s9, s9, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s9, s4, s9
s_add_i32 s4, s4, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s4, s6, s4
s_mul_i32 s7, s4, s8
s_add_i32 s9, s4, 1
s_sub_i32 s7, s6, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s10, s7, s8
s_cmp_ge_u32 s7, s8
s_cselect_b32 s9, s9, s4
s_cselect_b32 s4, s10, s7
s_add_i32 s7, s9, 1
s_cmp_ge_u32 s4, s8
s_mul_i32 s4, s6, s15
s_cselect_b32 s6, s7, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s6, v0, s[4:5]
s_add_i32 s5, s5, -1
s_cmp_eq_u32 s15, s5
s_cselect_b32 s4, -1, 0
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, s8, v0
v_add3_u32 v0, s6, s2, v1
s_and_b32 s2, s4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v0, v0, s3, s2
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, -1, v0
v_min_i32_e32 v0, s3, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v1, v0
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x20
s_load_b256 s[4:11], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_alignbit_b32 v6, s15, s14, 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_co_u32 v7, vcc_lo, s8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, v1, v0
global_load_b32 v5, v[7:8], off
v_add_co_u32 v7, s0, s12, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, s13, v3, s0
v_mov_b32_e32 v3, v4
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
global_store_b32 v[7:8], v5, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v4, vcc_lo, s10, v1
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v2, vcc_lo
global_load_u8 v5, v[4:5], off
v_mul_lo_u32 v4, v3, v6
s_waitcnt vmcnt(0)
v_add3_u32 v7, v4, v5, 0xffffffbf
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v4, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 -1, v4
s_cbranch_execz .LBB0_2
s_mov_b32 s1, 0
.p2align 6
.LBB0_5:
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, v3, v6
v_add3_u32 v7, v4, v5, 0xffffffbf
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v4, v[7:8], off
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, -1, v4
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s1
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10ac_kernel1PiPjS0_PhS0_miiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10ac_kernel1PiPjS0_PhS0_miiiii, .Lfunc_end0-_Z10ac_kernel1PiPjS0_PhS0_miiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10ac_kernel1PiPjS0_PhS0_miiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10ac_kernel1PiPjS0_PhS0_miiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016862c_00000000-6_ac_kernel1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z10ac_kernel1PiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii
.type _Z46__device_stub__Z10ac_kernel1PiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii, @function
_Z46__device_stub__Z10ac_kernel1PiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10ac_kernel1PiPjS0_PhS0_miiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z10ac_kernel1PiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii, .-_Z46__device_stub__Z10ac_kernel1PiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii
.globl _Z10ac_kernel1PiPjS0_PhS0_miiiii
.type _Z10ac_kernel1PiPjS0_PhS0_miiiii, @function
_Z10ac_kernel1PiPjS0_PhS0_miiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z46__device_stub__Z10ac_kernel1PiPjS0_PhS0_miiiiiPiPjS0_PhS0_miiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10ac_kernel1PiPjS0_PhS0_miiiii, .-_Z10ac_kernel1PiPjS0_PhS0_miiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10ac_kernel1PiPjS0_PhS0_miiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10ac_kernel1PiPjS0_PhS0_miiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ac_kernel1.hip"
.globl _Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii # -- Begin function _Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii
.p2align 4, 0x90
.type _Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii,@function
_Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii: # @_Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10ac_kernel1PiPjS0_PhS0_miiiii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii, .Lfunc_end0-_Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10ac_kernel1PiPjS0_PhS0_miiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10ac_kernel1PiPjS0_PhS0_miiiii,@object # @_Z10ac_kernel1PiPjS0_PhS0_miiiii
.section .rodata,"a",@progbits
.globl _Z10ac_kernel1PiPjS0_PhS0_miiiii
.p2align 3, 0x0
_Z10ac_kernel1PiPjS0_PhS0_miiiii:
.quad _Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii
.size _Z10ac_kernel1PiPjS0_PhS0_miiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10ac_kernel1PiPjS0_PhS0_miiiii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__ac_kernel1PiPjS0_PhS0_miiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10ac_kernel1PiPjS0_PhS0_miiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
int main() {
cudaError_t error_code = cudaDeviceReset();
printf("returned error code:%d \n", error_code); // a cudaError_t variable can be regarded as a integer
printf("cudaSuccess:%d, error_code==cudaSuccess:%d \n", cudaSuccess, cudaSuccess==error_code);
if(error_code==cudaSuccess)
{
printf("CUDA API successed!\n");
}
else
{
printf("Error needs to be handled! code:%d \n", error_code);
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
int main() {
cudaError_t error_code = cudaDeviceReset();
printf("returned error code:%d \n", error_code); // a cudaError_t variable can be regarded as a integer
printf("cudaSuccess:%d, error_code==cudaSuccess:%d \n", cudaSuccess, cudaSuccess==error_code);
if(error_code==cudaSuccess)
{
printf("CUDA API successed!\n");
}
else
{
printf("Error needs to be handled! code:%d \n", error_code);
}
return 0;
} | .file "tmpxft_000de0d9_00000000-6_error_check01.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "returned error code:%d \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cudaSuccess:%d, error_code==cudaSuccess:%d \n"
.section .rodata.str1.1
.LC2:
.string "CUDA API successed!\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "Error needs to be handled! code:%d \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
call cudaDeviceReset@PLT
movl %eax, %ebx
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
sete %cl
movzbl %cl, %ecx
movl $0, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jne .L4
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L5:
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
int main() {
cudaError_t error_code = cudaDeviceReset();
printf("returned error code:%d \n", error_code); // a cudaError_t variable can be regarded as a integer
printf("cudaSuccess:%d, error_code==cudaSuccess:%d \n", cudaSuccess, cudaSuccess==error_code);
if(error_code==cudaSuccess)
{
printf("CUDA API successed!\n");
}
else
{
printf("Error needs to be handled! code:%d \n", error_code);
}
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
int main() {
hipError_t error_code = hipDeviceReset();
printf("returned error code:%d \n", error_code); // a cudaError_t variable can be regarded as a integer
printf("cudaSuccess:%d, error_code==cudaSuccess:%d \n", hipSuccess, hipSuccess==error_code);
if(error_code==hipSuccess)
{
printf("CUDA API successed!\n");
}
else
{
printf("Error needs to be handled! code:%d \n", error_code);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
int main() {
hipError_t error_code = hipDeviceReset();
printf("returned error code:%d \n", error_code); // a cudaError_t variable can be regarded as a integer
printf("cudaSuccess:%d, error_code==cudaSuccess:%d \n", hipSuccess, hipSuccess==error_code);
if(error_code==hipSuccess)
{
printf("CUDA API successed!\n");
}
else
{
printf("Error needs to be handled! code:%d \n", error_code);
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
int main() {
hipError_t error_code = hipDeviceReset();
printf("returned error code:%d \n", error_code); // a cudaError_t variable can be regarded as a integer
printf("cudaSuccess:%d, error_code==cudaSuccess:%d \n", hipSuccess, hipSuccess==error_code);
if(error_code==hipSuccess)
{
printf("CUDA API successed!\n");
}
else
{
printf("Error needs to be handled! code:%d \n", error_code);
}
return 0;
} | .text
.file "error_check01.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
callq hipDeviceReset
movl %eax, %ebx
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
xorl %edx, %edx
testl %ebx, %ebx
sete %dl
movl $.L.str.1, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
testl %ebx, %ebx
je .LBB0_1
# %bb.2:
movl $.L.str.3, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
jmp .LBB0_3
.LBB0_1:
movl $.Lstr, %edi
callq puts@PLT
.LBB0_3:
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "returned error code:%d \n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "cudaSuccess:%d, error_code==cudaSuccess:%d \n"
.size .L.str.1, 45
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error needs to be handled! code:%d \n"
.size .L.str.3, 37
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CUDA API successed!"
.size .Lstr, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000de0d9_00000000-6_error_check01.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "returned error code:%d \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cudaSuccess:%d, error_code==cudaSuccess:%d \n"
.section .rodata.str1.1
.LC2:
.string "CUDA API successed!\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "Error needs to be handled! code:%d \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
call cudaDeviceReset@PLT
movl %eax, %ebx
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
sete %cl
movzbl %cl, %ecx
movl $0, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jne .L4
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L5:
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "error_check01.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
callq hipDeviceReset
movl %eax, %ebx
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
xorl %edx, %edx
testl %ebx, %ebx
sete %dl
movl $.L.str.1, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
testl %ebx, %ebx
je .LBB0_1
# %bb.2:
movl $.L.str.3, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
jmp .LBB0_3
.LBB0_1:
movl $.Lstr, %edi
callq puts@PLT
.LBB0_3:
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "returned error code:%d \n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "cudaSuccess:%d, error_code==cudaSuccess:%d \n"
.size .L.str.1, 45
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error needs to be handled! code:%d \n"
.size .L.str.3, 37
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CUDA API successed!"
.size .Lstr, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
void inline check(cudaError_t err, const char* filename, int line)
{
if (err != cudaSuccess)
{
printf("%s-l%i: %s\n", filename, line, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(int argc, char** argv)
{
cudaError_t err; // variable for error codes
int count; // variable for number of devices
int device; // variable for active device id
err = cudaGetDeviceCount(&count);
check(err, __FILE__, __LINE__);
printf("\nFound %i devices\n\n", count);
for (device = 0; device < count; device++)
{
err = cudaSetDevice(device);
check(err, __FILE__, __LINE__);
struct cudaDeviceProp p;
err = cudaGetDeviceProperties(&p, device);
check(err, __FILE__, __LINE__);
printf("Device %i : ", device);
printf("%s ", p.name);
printf("with %i SMs\n", p.multiProcessorCount);
}
printf("\n");
return EXIT_SUCCESS;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
void inline check(cudaError_t err, const char* filename, int line)
{
if (err != cudaSuccess)
{
printf("%s-l%i: %s\n", filename, line, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(int argc, char** argv)
{
cudaError_t err; // variable for error codes
int count; // variable for number of devices
int device; // variable for active device id
err = cudaGetDeviceCount(&count);
check(err, __FILE__, __LINE__);
printf("\nFound %i devices\n\n", count);
for (device = 0; device < count; device++)
{
err = cudaSetDevice(device);
check(err, __FILE__, __LINE__);
struct cudaDeviceProp p;
err = cudaGetDeviceProperties(&p, device);
check(err, __FILE__, __LINE__);
printf("Device %i : ", device);
printf("%s ", p.name);
printf("with %i SMs\n", p.multiProcessorCount);
}
printf("\n");
return EXIT_SUCCESS;
} | .file "tmpxft_00005e62_00000000-6_query.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/PawseySC/Develop-with-CUDA/master/query/query.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s-l%i: %s\n"
.LC2:
.string "\nFound %i devices\n\n"
.LC3:
.string "Device %i : "
.LC4:
.string "%s "
.LC5:
.string "with %i SMs\n"
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L12
movl 12(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L5
movl $0, %ebx
leaq 16(%rsp), %rbp
leaq .LC3(%rip), %r14
leaq .LC4(%rip), %r13
leaq .LC5(%rip), %r12
.L8:
movl %ebx, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L13
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L14
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L8
.L5:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $22, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L13:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $29, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L14:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $33, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <cuda_runtime.h>
void inline check(cudaError_t err, const char* filename, int line)
{
if (err != cudaSuccess)
{
printf("%s-l%i: %s\n", filename, line, cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(int argc, char** argv)
{
cudaError_t err; // variable for error codes
int count; // variable for number of devices
int device; // variable for active device id
err = cudaGetDeviceCount(&count);
check(err, __FILE__, __LINE__);
printf("\nFound %i devices\n\n", count);
for (device = 0; device < count; device++)
{
err = cudaSetDevice(device);
check(err, __FILE__, __LINE__);
struct cudaDeviceProp p;
err = cudaGetDeviceProperties(&p, device);
check(err, __FILE__, __LINE__);
printf("Device %i : ", device);
printf("%s ", p.name);
printf("with %i SMs\n", p.multiProcessorCount);
}
printf("\n");
return EXIT_SUCCESS;
} | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
void inline check(hipError_t err, const char* filename, int line)
{
if (err != hipSuccess)
{
printf("%s-l%i: %s\n", filename, line, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(int argc, char** argv)
{
hipError_t err; // variable for error codes
int count; // variable for number of devices
int device; // variable for active device id
err = hipGetDeviceCount(&count);
check(err, __FILE__, __LINE__);
printf("\nFound %i devices\n\n", count);
for (device = 0; device < count; device++)
{
err = hipSetDevice(device);
check(err, __FILE__, __LINE__);
struct hipDeviceProp_t p;
err = hipGetDeviceProperties(&p, device);
check(err, __FILE__, __LINE__);
printf("Device %i : ", device);
printf("%s ", p.name);
printf("with %i SMs\n", p.multiProcessorCount);
}
printf("\n");
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
void inline check(hipError_t err, const char* filename, int line)
{
if (err != hipSuccess)
{
printf("%s-l%i: %s\n", filename, line, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(int argc, char** argv)
{
hipError_t err; // variable for error codes
int count; // variable for number of devices
int device; // variable for active device id
err = hipGetDeviceCount(&count);
check(err, __FILE__, __LINE__);
printf("\nFound %i devices\n\n", count);
for (device = 0; device < count; device++)
{
err = hipSetDevice(device);
check(err, __FILE__, __LINE__);
struct hipDeviceProp_t p;
err = hipGetDeviceProperties(&p, device);
check(err, __FILE__, __LINE__);
printf("Device %i : ", device);
printf("%s ", p.name);
printf("with %i SMs\n", p.multiProcessorCount);
}
printf("\n");
return EXIT_SUCCESS;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
void inline check(hipError_t err, const char* filename, int line)
{
if (err != hipSuccess)
{
printf("%s-l%i: %s\n", filename, line, hipGetErrorString(err));
exit(EXIT_FAILURE);
}
}
int main(int argc, char** argv)
{
hipError_t err; // variable for error codes
int count; // variable for number of devices
int device; // variable for active device id
err = hipGetDeviceCount(&count);
check(err, __FILE__, __LINE__);
printf("\nFound %i devices\n\n", count);
for (device = 0; device < count; device++)
{
err = hipSetDevice(device);
check(err, __FILE__, __LINE__);
struct hipDeviceProp_t p;
err = hipGetDeviceProperties(&p, device);
check(err, __FILE__, __LINE__);
printf("Device %i : ", device);
printf("%s ", p.name);
printf("with %i SMs\n", p.multiProcessorCount);
}
printf("\n");
return EXIT_SUCCESS;
} | .text
.file "query.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_Z5check10hipError_tPKci.exit
movl 4(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB0_10
# %bb.4: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movl %ebp, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_6
# %bb.7: # %_Z5check10hipError_tPKci.exit9
# in Loop: Header=BB0_5 Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_8
# %bb.9: # %_Z5check10hipError_tPKci.exit11
# in Loop: Header=BB0_5 Depth=1
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_5
.LBB0_10: # %._crit_edge
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_8:
.cfi_def_cfa_offset 1504
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movl $.L.str, %esi
movl $33, %edx
jmp .LBB0_2
.LBB0_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movl $.L.str, %esi
movl $29, %edx
.LBB0_2:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB0_1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movl $.L.str, %esi
movl $22, %edx
jmp .LBB0_2
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/PawseySC/Develop-with-CUDA/master/query/query.hip"
.size .L.str, 107
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nFound %i devices\n\n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device %i : "
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%s "
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "with %i SMs\n"
.size .L.str.4, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%s-l%i: %s\n"
.size .L.str.6, 12
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00005e62_00000000-6_query.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/PawseySC/Develop-with-CUDA/master/query/query.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s-l%i: %s\n"
.LC2:
.string "\nFound %i devices\n\n"
.LC3:
.string "Device %i : "
.LC4:
.string "%s "
.LC5:
.string "with %i SMs\n"
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L12
movl 12(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L5
movl $0, %ebx
leaq 16(%rsp), %rbp
leaq .LC3(%rip), %r14
leaq .LC4(%rip), %r13
leaq .LC5(%rip), %r12
.L8:
movl %ebx, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L13
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L14
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L8
.L5:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $22, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L13:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $29, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L14:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $33, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "query.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_Z5check10hipError_tPKci.exit
movl 4(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB0_10
# %bb.4: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movl %ebp, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_6
# %bb.7: # %_Z5check10hipError_tPKci.exit9
# in Loop: Header=BB0_5 Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_8
# %bb.9: # %_Z5check10hipError_tPKci.exit11
# in Loop: Header=BB0_5 Depth=1
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_5
.LBB0_10: # %._crit_edge
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_8:
.cfi_def_cfa_offset 1504
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movl $.L.str, %esi
movl $33, %edx
jmp .LBB0_2
.LBB0_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movl $.L.str, %esi
movl $29, %edx
.LBB0_2:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB0_1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movl $.L.str, %esi
movl $22, %edx
jmp .LBB0_2
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/PawseySC/Develop-with-CUDA/master/query/query.hip"
.size .L.str, 107
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\nFound %i devices\n\n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device %i : "
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%s "
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "with %i SMs\n"
.size .L.str.4, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%s-l%i: %s\n"
.size .L.str.6, 12
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __device__
void compute(double *x) {
x[0] = 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__
void compute(double *x) {
x[0] = 0;
} | .file "tmpxft_0001b6e2_00000000-6_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7computePd
.type _Z7computePd, @function
_Z7computePd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z7computePd, .-_Z7computePd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__
void compute(double *x) {
x[0] = 0;
} | #include <hip/hip_runtime.h>
__device__
void compute(double *x) {
x[0] = 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__device__
void compute(double *x) {
x[0] = 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__
void compute(double *x) {
x[0] = 0;
} | .text
.file "simple.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001b6e2_00000000-6_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7computePd
.type _Z7computePd, @function
_Z7computePd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z7computePd, .-_Z7computePd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void zeros(double *field, int n){
int xid = blockDim.x*blockIdx.x + threadIdx.x;
if (xid < n){
field[xid] = 0;
}
} | code for sm_80
Function : _Z5zerosPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void zeros(double *field, int n){
int xid = blockDim.x*blockIdx.x + threadIdx.x;
if (xid < n){
field[xid] = 0;
}
} | .file "tmpxft_00168f63_00000000-6_zeros.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z5zerosPdiPdi
.type _Z25__device_stub__Z5zerosPdiPdi, @function
_Z25__device_stub__Z5zerosPdiPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5zerosPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z5zerosPdiPdi, .-_Z25__device_stub__Z5zerosPdiPdi
.globl _Z5zerosPdi
.type _Z5zerosPdi, @function
_Z5zerosPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z5zerosPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5zerosPdi, .-_Z5zerosPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5zerosPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5zerosPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void zeros(double *field, int n){
int xid = blockDim.x*blockIdx.x + threadIdx.x;
if (xid < n){
field[xid] = 0;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void zeros(double *field, int n){
int xid = blockDim.x*blockIdx.x + threadIdx.x;
if (xid < n){
field[xid] = 0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void zeros(double *field, int n){
int xid = blockDim.x*blockIdx.x + threadIdx.x;
if (xid < n){
field[xid] = 0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5zerosPdi
.globl _Z5zerosPdi
.p2align 8
.type _Z5zerosPdi,@function
_Z5zerosPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5zerosPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5zerosPdi, .Lfunc_end0-_Z5zerosPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5zerosPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5zerosPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void zeros(double *field, int n){
int xid = blockDim.x*blockIdx.x + threadIdx.x;
if (xid < n){
field[xid] = 0;
}
} | .text
.file "zeros.hip"
.globl _Z20__device_stub__zerosPdi # -- Begin function _Z20__device_stub__zerosPdi
.p2align 4, 0x90
.type _Z20__device_stub__zerosPdi,@function
_Z20__device_stub__zerosPdi: # @_Z20__device_stub__zerosPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5zerosPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__zerosPdi, .Lfunc_end0-_Z20__device_stub__zerosPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5zerosPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5zerosPdi,@object # @_Z5zerosPdi
.section .rodata,"a",@progbits
.globl _Z5zerosPdi
.p2align 3, 0x0
_Z5zerosPdi:
.quad _Z20__device_stub__zerosPdi
.size _Z5zerosPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5zerosPdi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__zerosPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5zerosPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5zerosPdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5zerosPdi
.globl _Z5zerosPdi
.p2align 8
.type _Z5zerosPdi,@function
_Z5zerosPdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5zerosPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5zerosPdi, .Lfunc_end0-_Z5zerosPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5zerosPdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5zerosPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00168f63_00000000-6_zeros.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z5zerosPdiPdi
.type _Z25__device_stub__Z5zerosPdiPdi, @function
_Z25__device_stub__Z5zerosPdiPdi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5zerosPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z5zerosPdiPdi, .-_Z25__device_stub__Z5zerosPdiPdi
.globl _Z5zerosPdi
.type _Z5zerosPdi, @function
_Z5zerosPdi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z5zerosPdiPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5zerosPdi, .-_Z5zerosPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5zerosPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5zerosPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "zeros.hip"
.globl _Z20__device_stub__zerosPdi # -- Begin function _Z20__device_stub__zerosPdi
.p2align 4, 0x90
.type _Z20__device_stub__zerosPdi,@function
_Z20__device_stub__zerosPdi: # @_Z20__device_stub__zerosPdi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5zerosPdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__zerosPdi, .Lfunc_end0-_Z20__device_stub__zerosPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5zerosPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5zerosPdi,@object # @_Z5zerosPdi
.section .rodata,"a",@progbits
.globl _Z5zerosPdi
.p2align 3, 0x0
_Z5zerosPdi:
.quad _Z20__device_stub__zerosPdi
.size _Z5zerosPdi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5zerosPdi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__zerosPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5zerosPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void test()
{
do
{
}while(1);
} | code for sm_80
Function : _Z4testv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ BRA 0x10 ; /* 0xfffffff000007947 */
/* 0x000fea000383ffff */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void test()
{
do
{
}while(1);
} | .file "tmpxft_00076e17_00000000-6_tt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4testvv
.type _Z22__device_stub__Z4testvv, @function
_Z22__device_stub__Z4testvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4testv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z22__device_stub__Z4testvv, .-_Z22__device_stub__Z4testvv
.globl _Z4testv
.type _Z4testv, @function
_Z4testv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4testvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4testv, .-_Z4testv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4testv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void test()
{
do
{
}while(1);
} | #include <hip/hip_runtime.h>
__global__ void test()
{
do
{
}while(1);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void test()
{
do
{
}while(1);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testv
.globl _Z4testv
.p2align 8
.type _Z4testv,@function
_Z4testv:
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testv, .Lfunc_end0-_Z4testv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z4testv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void test()
{
do
{
}while(1);
} | .text
.file "tt.hip"
.globl _Z19__device_stub__testv # -- Begin function _Z19__device_stub__testv
.p2align 4, 0x90
.type _Z19__device_stub__testv,@function
_Z19__device_stub__testv: # @_Z19__device_stub__testv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__testv, .Lfunc_end0-_Z19__device_stub__testv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testv,@object # @_Z4testv
.section .rodata,"a",@progbits
.globl _Z4testv
.p2align 3, 0x0
_Z4testv:
.quad _Z19__device_stub__testv
.size _Z4testv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4testv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4testv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ BRA 0x10 ; /* 0xfffffff000007947 */
/* 0x000fea000383ffff */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testv
.globl _Z4testv
.p2align 8
.type _Z4testv,@function
_Z4testv:
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testv, .Lfunc_end0-_Z4testv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z4testv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00076e17_00000000-6_tt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4testvv
.type _Z22__device_stub__Z4testvv, @function
_Z22__device_stub__Z4testvv:
.LFB2051:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4testv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z22__device_stub__Z4testvv, .-_Z22__device_stub__Z4testvv
.globl _Z4testv
.type _Z4testv, @function
_Z4testv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4testvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4testv, .-_Z4testv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4testv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tt.hip"
.globl _Z19__device_stub__testv # -- Begin function _Z19__device_stub__testv
.p2align 4, 0x90
.type _Z19__device_stub__testv,@function
_Z19__device_stub__testv: # @_Z19__device_stub__testv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__testv, .Lfunc_end0-_Z19__device_stub__testv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testv,@object # @_Z4testv
.section .rodata,"a",@progbits
.globl _Z4testv
.p2align 3, 0x0
_Z4testv:
.quad _Z19__device_stub__testv
.size _Z4testv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4testv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
#define SIMPLE
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
#ifdef SIMPLE
__shared__ float in_s[2*BLOCK_SIZE];
int idx = 2 * blockIdx.x * blockDim.x + threadIdx.x;
in_s[threadIdx.x] = ((idx < size)? in[idx]: 0.0f);
in_s[threadIdx.x+BLOCK_SIZE] = ((idx + BLOCK_SIZE < size)? in[idx+BLOCK_SIZE]: 0.0f);
for(int stride = 1; stride < BLOCK_SIZE<<1; stride <<= 1) {
__syncthreads();
if(threadIdx.x % stride == 0)
in_s[2*threadIdx.x] += in_s[2*threadIdx.x + stride];
}
#else
// INSERT KERNEL CODE HERE
#endif
if(threadIdx.x == 0)
out[blockIdx.x] = in_s[0];
} | code for sm_80
Function : _Z9reductionPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0060*/ SHF.L.U32 R3, R0, 0x1, RZ ; /* 0x0000000100037819 */
/* 0x001fca00000006ff */
/*0070*/ IMAD R4, R3, c[0x0][0x0], R2 ; /* 0x0000000003047a24 */
/* 0x002fca00078e0202 */
/*0080*/ IADD3 R3, R4.reuse, 0x200, RZ ; /* 0x0000020004037810 */
/* 0x040fe40007ffe0ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f06070 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f26070 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00c0*/ IMAD.WIDE R4, R4, R3, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0203 */
/*00d0*/ @!P0 LDG.E R9, [R4.64] ; /* 0x0000000404098981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ @!P1 LDG.E R7, [R4.64+0x800] ; /* 0x0008000404079981 */
/* 0x000ee2000c1e1900 */
/*00f0*/ LOP3.LUT R6, R2.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000102067812 */
/* 0x040fe400078ec0ff */
/*0100*/ LOP3.LUT P1, RZ, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302ff7812 */
/* 0x000fe4000782c0ff */
/*0110*/ ISETP.NE.U32.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f05070 */
/*0120*/ STS [R2.X4], R9 ; /* 0x0000000902007388 */
/* 0x004fe80000004800 */
/*0130*/ STS [R2.X4+0x800], R7 ; /* 0x0008000702007388 */
/* 0x008fe80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDS.64 R10, [R2.X8] ; /* 0x00000000020a7984 */
/* 0x000e240000008a00 */
/*0160*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x001fca0000000000 */
/*0170*/ STS [R2.X8], R11 ; /* 0x0000000b02007388 */
/* 0x000fe80000008800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ @P0 LDS R6, [R2.X8] ; /* 0x0000000002060984 */
/* 0x000fe80000008800 */
/*01a0*/ @P0 LDS R5, [R2.X8+0x8] ; /* 0x0000080002050984 */
/* 0x000e240000008800 */
/*01b0*/ @P0 FADD R5, R6, R5 ; /* 0x0000000506050221 */
/* 0x001fca0000000000 */
/*01c0*/ @P0 STS [R2.X8], R5 ; /* 0x0000000502000388 */
/* 0x000fe80000008800 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01e0*/ LOP3.LUT P0, RZ, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702ff7812 */
/* 0x000fca000780c0ff */
/*01f0*/ @!P1 LDS R4, [R2.X8] ; /* 0x0000000002049984 */
/* 0x000fe80000008800 */
/*0200*/ @!P1 LDS R7, [R2.X8+0x10] ; /* 0x0000100002079984 */
/* 0x000e240000008800 */
/*0210*/ @!P1 FADD R7, R4, R7 ; /* 0x0000000704079221 */
/* 0x001fca0000000000 */
/*0220*/ @!P1 STS [R2.X8], R7 ; /* 0x0000000702009388 */
/* 0x000fe80000008800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0240*/ LOP3.LUT P1, RZ, R2, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f02ff7812 */
/* 0x000fca000782c0ff */
/*0250*/ @!P0 LDS R4, [R2.X8] ; /* 0x0000000002048984 */
/* 0x000fe80000008800 */
/*0260*/ @!P0 LDS R9, [R2.X8+0x20] ; /* 0x0000200002098984 */
/* 0x000e240000008800 */
/*0270*/ @!P0 FADD R9, R4, R9 ; /* 0x0000000904098221 */
/* 0x001fca0000000000 */
/*0280*/ @!P0 STS [R2.X8], R9 ; /* 0x0000000902008388 */
/* 0x000fe80000008800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ LOP3.LUT P0, RZ, R2, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f02ff7812 */
/* 0x000fca000780c0ff */
/*02b0*/ @!P1 LDS R4, [R2.X8] ; /* 0x0000000002049984 */
/* 0x000fe80000008800 */
/*02c0*/ @!P1 LDS R5, [R2.X8+0x40] ; /* 0x0000400002059984 */
/* 0x000e240000008800 */
/*02d0*/ @!P1 FADD R5, R4, R5 ; /* 0x0000000504059221 */
/* 0x001fca0000000000 */
/*02e0*/ @!P1 STS [R2.X8], R5 ; /* 0x0000000502009388 */
/* 0x000fe80000008800 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0300*/ LOP3.LUT P1, RZ, R2, 0x3f, RZ, 0xc0, !PT ; /* 0x0000003f02ff7812 */
/* 0x000fca000782c0ff */
/*0310*/ @!P0 LDS R4, [R2.X8] ; /* 0x0000000002048984 */
/* 0x000fe80000008800 */
/*0320*/ @!P0 LDS R7, [R2.X8+0x80] ; /* 0x0000800002078984 */
/* 0x000e240000008800 */
/*0330*/ @!P0 FADD R7, R4, R7 ; /* 0x0000000704078221 */
/* 0x001fca0000000000 */
/*0340*/ @!P0 STS [R2.X8], R7 ; /* 0x0000000702008388 */
/* 0x000fe80000008800 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0360*/ LOP3.LUT P0, RZ, R2, 0x7f, RZ, 0xc0, !PT ; /* 0x0000007f02ff7812 */
/* 0x000fca000780c0ff */
/*0370*/ @!P1 LDS R4, [R2.X8] ; /* 0x0000000002049984 */
/* 0x000fe80000008800 */
/*0380*/ @!P1 LDS R9, [R2.X8+0x100] ; /* 0x0001000002099984 */
/* 0x000e240000008800 */
/*0390*/ @!P1 FADD R9, R4, R9 ; /* 0x0000000904099221 */
/* 0x001fca0000000000 */
/*03a0*/ @!P1 STS [R2.X8], R9 ; /* 0x0000000902009388 */
/* 0x000fe80000008800 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03c0*/ LOP3.LUT P1, RZ, R2, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff02ff7812 */
/* 0x000fca000782c0ff */
/*03d0*/ @!P0 LDS R4, [R2.X8] ; /* 0x0000000002048984 */
/* 0x000fe80000008800 */
/*03e0*/ @!P0 LDS R5, [R2.X8+0x200] ; /* 0x0002000002058984 */
/* 0x000e240000008800 */
/*03f0*/ @!P0 FADD R5, R4, R5 ; /* 0x0000000504058221 */
/* 0x001fca0000000000 */
/*0400*/ @!P0 STS [R2.X8], R5 ; /* 0x0000000502008388 */
/* 0x000fe80000008800 */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0420*/ LOP3.LUT P0, RZ, R2, 0x1ff, RZ, 0xc0, !PT ; /* 0x000001ff02ff7812 */
/* 0x000fca000780c0ff */
/*0430*/ @!P1 LDS R4, [R2.X8] ; /* 0x0000000002049984 */
/* 0x000fe80000008800 */
/*0440*/ @!P1 LDS R7, [R2.X8+0x400] ; /* 0x0004000002079984 */
/* 0x000e240000008800 */
/*0450*/ @!P1 FADD R7, R4, R7 ; /* 0x0000000704079221 */
/* 0x001fca0000000000 */
/*0460*/ @!P1 STS [R2.X8], R7 ; /* 0x0000000702009388 */
/* 0x000fe80000008800 */
/*0470*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0480*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fca0003f25270 */
/*0490*/ @!P0 LDS R4, [R2.X8] ; /* 0x0000000002048984 */
/* 0x000fe80000008800 */
/*04a0*/ @!P0 LDS R9, [R2.X8+0x800] ; /* 0x0008000002098984 */
/* 0x000e240000008800 */
/*04b0*/ @!P0 FADD R9, R4, R9 ; /* 0x0000000904098221 */
/* 0x001fca0000000000 */
/*04c0*/ @!P0 STS [R2.X8], R9 ; /* 0x0000000902008388 */
/* 0x0001e20000008800 */
/*04d0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*04e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*04f0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0003 */
/*0500*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
#define SIMPLE
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
#ifdef SIMPLE
__shared__ float in_s[2*BLOCK_SIZE];
int idx = 2 * blockIdx.x * blockDim.x + threadIdx.x;
in_s[threadIdx.x] = ((idx < size)? in[idx]: 0.0f);
in_s[threadIdx.x+BLOCK_SIZE] = ((idx + BLOCK_SIZE < size)? in[idx+BLOCK_SIZE]: 0.0f);
for(int stride = 1; stride < BLOCK_SIZE<<1; stride <<= 1) {
__syncthreads();
if(threadIdx.x % stride == 0)
in_s[2*threadIdx.x] += in_s[2*threadIdx.x + stride];
}
#else
// INSERT KERNEL CODE HERE
#endif
if(threadIdx.x == 0)
out[blockIdx.x] = in_s[0];
} | .file "tmpxft_00040c9b_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9reductionPfS_jPfS_j
.type _Z31__device_stub__Z9reductionPfS_jPfS_j, @function
_Z31__device_stub__Z9reductionPfS_jPfS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reductionPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9reductionPfS_jPfS_j, .-_Z31__device_stub__Z9reductionPfS_jPfS_j
.globl _Z9reductionPfS_j
.type _Z9reductionPfS_j, @function
_Z9reductionPfS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9reductionPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9reductionPfS_j, .-_Z9reductionPfS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9reductionPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
#define SIMPLE
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
#ifdef SIMPLE
__shared__ float in_s[2*BLOCK_SIZE];
int idx = 2 * blockIdx.x * blockDim.x + threadIdx.x;
in_s[threadIdx.x] = ((idx < size)? in[idx]: 0.0f);
in_s[threadIdx.x+BLOCK_SIZE] = ((idx + BLOCK_SIZE < size)? in[idx+BLOCK_SIZE]: 0.0f);
for(int stride = 1; stride < BLOCK_SIZE<<1; stride <<= 1) {
__syncthreads();
if(threadIdx.x % stride == 0)
in_s[2*threadIdx.x] += in_s[2*threadIdx.x + stride];
}
#else
// INSERT KERNEL CODE HERE
#endif
if(threadIdx.x == 0)
out[blockIdx.x] = in_s[0];
} | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
#define SIMPLE
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
#ifdef SIMPLE
__shared__ float in_s[2*BLOCK_SIZE];
int idx = 2 * blockIdx.x * blockDim.x + threadIdx.x;
in_s[threadIdx.x] = ((idx < size)? in[idx]: 0.0f);
in_s[threadIdx.x+BLOCK_SIZE] = ((idx + BLOCK_SIZE < size)? in[idx+BLOCK_SIZE]: 0.0f);
for(int stride = 1; stride < BLOCK_SIZE<<1; stride <<= 1) {
__syncthreads();
if(threadIdx.x % stride == 0)
in_s[2*threadIdx.x] += in_s[2*threadIdx.x + stride];
}
#else
// INSERT KERNEL CODE HERE
#endif
if(threadIdx.x == 0)
out[blockIdx.x] = in_s[0];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
#define SIMPLE
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
#ifdef SIMPLE
__shared__ float in_s[2*BLOCK_SIZE];
int idx = 2 * blockIdx.x * blockDim.x + threadIdx.x;
in_s[threadIdx.x] = ((idx < size)? in[idx]: 0.0f);
in_s[threadIdx.x+BLOCK_SIZE] = ((idx + BLOCK_SIZE < size)? in[idx+BLOCK_SIZE]: 0.0f);
for(int stride = 1; stride < BLOCK_SIZE<<1; stride <<= 1) {
__syncthreads();
if(threadIdx.x % stride == 0)
in_s[2*threadIdx.x] += in_s[2*threadIdx.x + stride];
}
#else
// INSERT KERNEL CODE HERE
#endif
if(threadIdx.x == 0)
out[blockIdx.x] = in_s[0];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPfS_j
.globl _Z9reductionPfS_j
.p2align 8
.type _Z9reductionPfS_j,@function
_Z9reductionPfS_j:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s6
v_lshl_add_u32 v1, s6, 1, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v1, 0x200, v1
v_lshlrev_b32_e32 v4, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_waitcnt vmcnt(0)
ds_store_b32 v4, v2
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[1:2], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v1, 1, v0
v_lshlrev_b32_e32 v2, 3, v0
s_mov_b32 s3, 1
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3 offset:2048
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_gt_i32 s3, 0x3ff
s_cbranch_scc1 .LBB0_8
.LBB0_6:
s_add_i32 s4, s3, -1
s_waitcnt lgkmcnt(0)
v_and_b32_e32 v3, s4, v0
s_mov_b32 s4, exec_lo
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v3, s3, v1, 2
ds_load_b32 v3, v3
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
ds_store_b32 v2, v3
s_branch .LBB0_5
.LBB0_8:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPfS_j
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPfS_j, .Lfunc_end0-_Z9reductionPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/******************************************************************************
*cr
*cr (C) Copyright 2010 The Board of Trustees of the
*cr University of Illinois
*cr All Rights Reserved
*cr
******************************************************************************/
#define BLOCK_SIZE 512
#define SIMPLE
__global__ void reduction(float *out, float *in, unsigned size)
{
/********************************************************************
Load a segment of the input vector into shared memory
Traverse the reduction tree
Write the computed sum to the output vector at the correct index
********************************************************************/
#ifdef SIMPLE
__shared__ float in_s[2*BLOCK_SIZE];
int idx = 2 * blockIdx.x * blockDim.x + threadIdx.x;
in_s[threadIdx.x] = ((idx < size)? in[idx]: 0.0f);
in_s[threadIdx.x+BLOCK_SIZE] = ((idx + BLOCK_SIZE < size)? in[idx+BLOCK_SIZE]: 0.0f);
for(int stride = 1; stride < BLOCK_SIZE<<1; stride <<= 1) {
__syncthreads();
if(threadIdx.x % stride == 0)
in_s[2*threadIdx.x] += in_s[2*threadIdx.x + stride];
}
#else
// INSERT KERNEL CODE HERE
#endif
if(threadIdx.x == 0)
out[blockIdx.x] = in_s[0];
} | .text
.file "kernel.hip"
.globl _Z24__device_stub__reductionPfS_j # -- Begin function _Z24__device_stub__reductionPfS_j
.p2align 4, 0x90
.type _Z24__device_stub__reductionPfS_j,@function
_Z24__device_stub__reductionPfS_j: # @_Z24__device_stub__reductionPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reductionPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPfS_j, .Lfunc_end0-_Z24__device_stub__reductionPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPfS_j,@object # @_Z9reductionPfS_j
.section .rodata,"a",@progbits
.globl _Z9reductionPfS_j
.p2align 3, 0x0
_Z9reductionPfS_j:
.quad _Z24__device_stub__reductionPfS_j
.size _Z9reductionPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9reductionPfS_j"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9reductionPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0060*/ SHF.L.U32 R3, R0, 0x1, RZ ; /* 0x0000000100037819 */
/* 0x001fca00000006ff */
/*0070*/ IMAD R4, R3, c[0x0][0x0], R2 ; /* 0x0000000003047a24 */
/* 0x002fca00078e0202 */
/*0080*/ IADD3 R3, R4.reuse, 0x200, RZ ; /* 0x0000020004037810 */
/* 0x040fe40007ffe0ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f06070 */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f26070 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00c0*/ IMAD.WIDE R4, R4, R3, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0203 */
/*00d0*/ @!P0 LDG.E R9, [R4.64] ; /* 0x0000000404098981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ @!P1 LDG.E R7, [R4.64+0x800] ; /* 0x0008000404079981 */
/* 0x000ee2000c1e1900 */
/*00f0*/ LOP3.LUT R6, R2.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000102067812 */
/* 0x040fe400078ec0ff */
/*0100*/ LOP3.LUT P1, RZ, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302ff7812 */
/* 0x000fe4000782c0ff */
/*0110*/ ISETP.NE.U32.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f05070 */
/*0120*/ STS [R2.X4], R9 ; /* 0x0000000902007388 */
/* 0x004fe80000004800 */
/*0130*/ STS [R2.X4+0x800], R7 ; /* 0x0008000702007388 */
/* 0x008fe80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0150*/ LDS.64 R10, [R2.X8] ; /* 0x00000000020a7984 */
/* 0x000e240000008a00 */
/*0160*/ FADD R11, R11, R10 ; /* 0x0000000a0b0b7221 */
/* 0x001fca0000000000 */
/*0170*/ STS [R2.X8], R11 ; /* 0x0000000b02007388 */
/* 0x000fe80000008800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ @P0 LDS R6, [R2.X8] ; /* 0x0000000002060984 */
/* 0x000fe80000008800 */
/*01a0*/ @P0 LDS R5, [R2.X8+0x8] ; /* 0x0000080002050984 */
/* 0x000e240000008800 */
/*01b0*/ @P0 FADD R5, R6, R5 ; /* 0x0000000506050221 */
/* 0x001fca0000000000 */
/*01c0*/ @P0 STS [R2.X8], R5 ; /* 0x0000000502000388 */
/* 0x000fe80000008800 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01e0*/ LOP3.LUT P0, RZ, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702ff7812 */
/* 0x000fca000780c0ff */
/*01f0*/ @!P1 LDS R4, [R2.X8] ; /* 0x0000000002049984 */
/* 0x000fe80000008800 */
/*0200*/ @!P1 LDS R7, [R2.X8+0x10] ; /* 0x0000100002079984 */
/* 0x000e240000008800 */
/*0210*/ @!P1 FADD R7, R4, R7 ; /* 0x0000000704079221 */
/* 0x001fca0000000000 */
/*0220*/ @!P1 STS [R2.X8], R7 ; /* 0x0000000702009388 */
/* 0x000fe80000008800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0240*/ LOP3.LUT P1, RZ, R2, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f02ff7812 */
/* 0x000fca000782c0ff */
/*0250*/ @!P0 LDS R4, [R2.X8] ; /* 0x0000000002048984 */
/* 0x000fe80000008800 */
/*0260*/ @!P0 LDS R9, [R2.X8+0x20] ; /* 0x0000200002098984 */
/* 0x000e240000008800 */
/*0270*/ @!P0 FADD R9, R4, R9 ; /* 0x0000000904098221 */
/* 0x001fca0000000000 */
/*0280*/ @!P0 STS [R2.X8], R9 ; /* 0x0000000902008388 */
/* 0x000fe80000008800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02a0*/ LOP3.LUT P0, RZ, R2, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f02ff7812 */
/* 0x000fca000780c0ff */
/*02b0*/ @!P1 LDS R4, [R2.X8] ; /* 0x0000000002049984 */
/* 0x000fe80000008800 */
/*02c0*/ @!P1 LDS R5, [R2.X8+0x40] ; /* 0x0000400002059984 */
/* 0x000e240000008800 */
/*02d0*/ @!P1 FADD R5, R4, R5 ; /* 0x0000000504059221 */
/* 0x001fca0000000000 */
/*02e0*/ @!P1 STS [R2.X8], R5 ; /* 0x0000000502009388 */
/* 0x000fe80000008800 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0300*/ LOP3.LUT P1, RZ, R2, 0x3f, RZ, 0xc0, !PT ; /* 0x0000003f02ff7812 */
/* 0x000fca000782c0ff */
/*0310*/ @!P0 LDS R4, [R2.X8] ; /* 0x0000000002048984 */
/* 0x000fe80000008800 */
/*0320*/ @!P0 LDS R7, [R2.X8+0x80] ; /* 0x0000800002078984 */
/* 0x000e240000008800 */
/*0330*/ @!P0 FADD R7, R4, R7 ; /* 0x0000000704078221 */
/* 0x001fca0000000000 */
/*0340*/ @!P0 STS [R2.X8], R7 ; /* 0x0000000702008388 */
/* 0x000fe80000008800 */
/*0350*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0360*/ LOP3.LUT P0, RZ, R2, 0x7f, RZ, 0xc0, !PT ; /* 0x0000007f02ff7812 */
/* 0x000fca000780c0ff */
/*0370*/ @!P1 LDS R4, [R2.X8] ; /* 0x0000000002049984 */
/* 0x000fe80000008800 */
/*0380*/ @!P1 LDS R9, [R2.X8+0x100] ; /* 0x0001000002099984 */
/* 0x000e240000008800 */
/*0390*/ @!P1 FADD R9, R4, R9 ; /* 0x0000000904099221 */
/* 0x001fca0000000000 */
/*03a0*/ @!P1 STS [R2.X8], R9 ; /* 0x0000000902009388 */
/* 0x000fe80000008800 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03c0*/ LOP3.LUT P1, RZ, R2, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff02ff7812 */
/* 0x000fca000782c0ff */
/*03d0*/ @!P0 LDS R4, [R2.X8] ; /* 0x0000000002048984 */
/* 0x000fe80000008800 */
/*03e0*/ @!P0 LDS R5, [R2.X8+0x200] ; /* 0x0002000002058984 */
/* 0x000e240000008800 */
/*03f0*/ @!P0 FADD R5, R4, R5 ; /* 0x0000000504058221 */
/* 0x001fca0000000000 */
/*0400*/ @!P0 STS [R2.X8], R5 ; /* 0x0000000502008388 */
/* 0x000fe80000008800 */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0420*/ LOP3.LUT P0, RZ, R2, 0x1ff, RZ, 0xc0, !PT ; /* 0x000001ff02ff7812 */
/* 0x000fca000780c0ff */
/*0430*/ @!P1 LDS R4, [R2.X8] ; /* 0x0000000002049984 */
/* 0x000fe80000008800 */
/*0440*/ @!P1 LDS R7, [R2.X8+0x400] ; /* 0x0004000002079984 */
/* 0x000e240000008800 */
/*0450*/ @!P1 FADD R7, R4, R7 ; /* 0x0000000704079221 */
/* 0x001fca0000000000 */
/*0460*/ @!P1 STS [R2.X8], R7 ; /* 0x0000000702009388 */
/* 0x000fe80000008800 */
/*0470*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0480*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fca0003f25270 */
/*0490*/ @!P0 LDS R4, [R2.X8] ; /* 0x0000000002048984 */
/* 0x000fe80000008800 */
/*04a0*/ @!P0 LDS R9, [R2.X8+0x800] ; /* 0x0008000002098984 */
/* 0x000e240000008800 */
/*04b0*/ @!P0 FADD R9, R4, R9 ; /* 0x0000000904098221 */
/* 0x001fca0000000000 */
/*04c0*/ @!P0 STS [R2.X8], R9 ; /* 0x0000000902008388 */
/* 0x0001e20000008800 */
/*04d0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*04e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*04f0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0003 */
/*0500*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPfS_j
.globl _Z9reductionPfS_j
.p2align 8
.type _Z9reductionPfS_j,@function
_Z9reductionPfS_j:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, 0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s6
v_lshl_add_u32 v1, s6, 1, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v2, v[4:5], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v1, 0x200, v1
v_lshlrev_b32_e32 v4, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_waitcnt vmcnt(0)
ds_store_b32 v4, v2
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[1:2], off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v1, 1, v0
v_lshlrev_b32_e32 v2, 3, v0
s_mov_b32 s3, 1
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3 offset:2048
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_gt_i32 s3, 0x3ff
s_cbranch_scc1 .LBB0_8
.LBB0_6:
s_add_i32 s4, s3, -1
s_waitcnt lgkmcnt(0)
v_and_b32_e32 v3, s4, v0
s_mov_b32 s4, exec_lo
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_5
v_add_lshl_u32 v3, s3, v1, 2
ds_load_b32 v3, v3
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v3, v3, v4
ds_store_b32 v2, v3
s_branch .LBB0_5
.LBB0_8:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPfS_j
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPfS_j, .Lfunc_end0-_Z9reductionPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00040c9b_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9reductionPfS_jPfS_j
.type _Z31__device_stub__Z9reductionPfS_jPfS_j, @function
_Z31__device_stub__Z9reductionPfS_jPfS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reductionPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9reductionPfS_jPfS_j, .-_Z31__device_stub__Z9reductionPfS_jPfS_j
.globl _Z9reductionPfS_j
.type _Z9reductionPfS_j, @function
_Z9reductionPfS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9reductionPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9reductionPfS_j, .-_Z9reductionPfS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9reductionPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z24__device_stub__reductionPfS_j # -- Begin function _Z24__device_stub__reductionPfS_j
.p2align 4, 0x90
.type _Z24__device_stub__reductionPfS_j,@function
_Z24__device_stub__reductionPfS_j: # @_Z24__device_stub__reductionPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reductionPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPfS_j, .Lfunc_end0-_Z24__device_stub__reductionPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPfS_j,@object # @_Z9reductionPfS_j
.section .rodata,"a",@progbits
.globl _Z9reductionPfS_j
.p2align 3, 0x0
_Z9reductionPfS_j:
.quad _Z24__device_stub__reductionPfS_j
.size _Z9reductionPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9reductionPfS_j"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
**Author: Mark Williams
** Simple matrix multiplication using device code (NVIDIA GPU).
** Matrix size is 16*16, values are all 32 and the output is 256.
*/
#include <stdio.h>
#include <stdlib.h>
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int Width){
//2D Thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
//Pvalue stores the Pd element that is computed by the thread
float Pvalue = 0;
for(int k = 0; k < Width; ++k){
float Mdelement = Md[ty * Width + k];
float Ndelement = Nd[k * Width + tx];
Pvalue += Mdelement * Ndelement;
}
//Write the matrix to device memory each thread writes one element
Pd[ty * Width + tx] = Pvalue;
}
void MatrixMultiplication(float* M, float* N, float* P, int Width){
//Pointers for each matrix (separate matrices for device computation)
float *Md, *Nd, *Pd;
//Size to be used for memory allocation
int size = Width * Width * sizeof(float);
//Transfer matrix M and N to device memory
cudaMalloc((void**) &Md, size);
cudaMemcpy(Md, M, size, cudaMemcpyHostToDevice);
cudaMalloc((void**) &Nd, size);
cudaMemcpy(Nd, N, size, cudaMemcpyHostToDevice);
//Allocate matrix P on the device
cudaMalloc((void**) &Pd, size);
//Setup the execution configuration
dim3 dimBlock(Width, Width);
dim3 dimGrid(1,1);
//Launch the device computation threads
MatrixMulKernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, Width);
//Transfer P from device to host
cudaMemcpy(P, Pd, size, cudaMemcpyDeviceToHost);
//Free device matrices
cudaFree(Md);
cudaFree(Nd);
cudaFree(Pd);
}
int main (){
//Pointers for each matrix
float *M, *N, *P;
//Use matrix width of 16, calculate size of memory for this width
int Width = 16;
int size = Width * Width * sizeof(float);
int count = 0;
//Allocate the memory
M = (float*)malloc(size);
N = (float*)malloc(size);
P = (float*)malloc(size);
//Populate M and N with 1's and 2's, repsectively
for(int i = 0; i < (Width * Width); i++){
M[i] = 1.0;
N[i] = 2.0;
}
//Pass the matrices and width size to multiplication function
MatrixMultiplication(M, N, P, Width);
//Print out the results
for(int i = 0; i < (Width * Width); i++){
count++;
printf("%.0f ", P[i]);
if(count % 16 == 0)
printf("\n");
}
printf("Count is %d\n", count);
//Deallocate memory
free(M);
free(N);
free(P);
return 0;
} | code for sm_80
Function : _Z15MatrixMulKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002200 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x001fd800078e02ff */
/*0080*/ @!P0 BRA 0xbb0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*00c0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*00e0*/ @!P0 BRA 0xa90 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0100*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0110*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0130*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0150*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x002fcc00078e0219 */
/*0160*/ @!P0 BRA 0x900 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x640 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01c0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*01d0*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*01e0*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*01f0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0210*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0220*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0230*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0240*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0250*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*0260*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*0270*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*0280*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*02c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*02d0*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0300*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0310*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0320*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0330*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0340*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0350*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0360*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*0370*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*0380*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0390*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03a0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03b0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*03c0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*03d0*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*03e0*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*03f0*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0420*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0430*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0440*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0450*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*0460*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*0470*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*0480*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0490*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04a0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04b0*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*04c0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*04d0*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*04e0*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*04f0*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0510*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0520*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0530*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*0540*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0570*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*0580*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0590*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05a0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05b0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05c0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*05e0*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*05f0*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0600*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0610*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0620*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0630*/ @P1 BRA 0x1b0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0640*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0650*/ @!P1 BRA 0x8e0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*0670*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0680*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0690*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06a0*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x000fe200078e0210 */
/*06b0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06c0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*06d0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*06e0*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*06f0*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0710*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0720*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0730*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*0740*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0750*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0760*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*0770*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0790*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*07a0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07b0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07c0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*07d0*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*07e0*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0800*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0810*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0820*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0830*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0840*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0850*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*0860*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*0870*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*0880*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0890*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08a0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08b0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*08c0*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*08d0*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*08e0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08f0*/ @!P0 BRA 0xa90 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0900*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0910*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0920*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0930*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0940*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0950*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*0960*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*0980*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0990*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09c0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*09d0*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*09e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*09f0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a00*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a10*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a20*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a30*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a40*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a50*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0a60*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0a70*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0a80*/ @P0 BRA 0x900 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0aa0*/ @!P0 BRA 0xbb0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0ac0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0ad0*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x002fd000078e0200 */
/*0ae0*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0af0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b00*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b10*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b20*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b30*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b40*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b70*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0b80*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0b90*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0ba0*/ @P0 BRA 0xb10 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bb0*/ IADD3 R2, R4, R0, RZ ; /* 0x0000000004027210 */
/* 0x002fe40007ffe0ff */
/*0bc0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0bd0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0be0*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0bf0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
**Author: Mark Williams
** Simple matrix multiplication using device code (NVIDIA GPU).
** Matrix size is 16*16, values are all 32 and the output is 256.
*/
#include <stdio.h>
#include <stdlib.h>
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int Width){
//2D Thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
//Pvalue stores the Pd element that is computed by the thread
float Pvalue = 0;
for(int k = 0; k < Width; ++k){
float Mdelement = Md[ty * Width + k];
float Ndelement = Nd[k * Width + tx];
Pvalue += Mdelement * Ndelement;
}
//Write the matrix to device memory each thread writes one element
Pd[ty * Width + tx] = Pvalue;
}
void MatrixMultiplication(float* M, float* N, float* P, int Width){
//Pointers for each matrix (separate matrices for device computation)
float *Md, *Nd, *Pd;
//Size to be used for memory allocation
int size = Width * Width * sizeof(float);
//Transfer matrix M and N to device memory
cudaMalloc((void**) &Md, size);
cudaMemcpy(Md, M, size, cudaMemcpyHostToDevice);
cudaMalloc((void**) &Nd, size);
cudaMemcpy(Nd, N, size, cudaMemcpyHostToDevice);
//Allocate matrix P on the device
cudaMalloc((void**) &Pd, size);
//Setup the execution configuration
dim3 dimBlock(Width, Width);
dim3 dimGrid(1,1);
//Launch the device computation threads
MatrixMulKernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, Width);
//Transfer P from device to host
cudaMemcpy(P, Pd, size, cudaMemcpyDeviceToHost);
//Free device matrices
cudaFree(Md);
cudaFree(Nd);
cudaFree(Pd);
}
int main (){
//Pointers for each matrix
float *M, *N, *P;
//Use matrix width of 16, calculate size of memory for this width
int Width = 16;
int size = Width * Width * sizeof(float);
int count = 0;
//Allocate the memory
M = (float*)malloc(size);
N = (float*)malloc(size);
P = (float*)malloc(size);
//Populate M and N with 1's and 2's, repsectively
for(int i = 0; i < (Width * Width); i++){
M[i] = 1.0;
N[i] = 2.0;
}
//Pass the matrices and width size to multiplication function
MatrixMultiplication(M, N, P, Width);
//Print out the results
for(int i = 0; i < (Width * Width); i++){
count++;
printf("%.0f ", P[i]);
if(count % 16 == 0)
printf("\n");
}
printf("Count is %d\n", count);
//Deallocate memory
free(M);
free(N);
free(P);
return 0;
} | .file "tmpxft_000a493c_00000000-6_multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.type _Z15MatrixMulKernelPfS_S_i, @function
_Z15MatrixMulKernelPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15MatrixMulKernelPfS_S_i, .-_Z15MatrixMulKernelPfS_S_i
.globl _Z20MatrixMultiplicationPfS_S_i
.type _Z20MatrixMultiplicationPfS_S_i, @function
_Z20MatrixMultiplicationPfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %ecx, %ebx
imull %ecx, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %ebp, 32(%rsp)
movl %ebp, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z20MatrixMultiplicationPfS_S_i, .-_Z20MatrixMultiplicationPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%.0f "
.LC3:
.string "\n"
.LC4:
.string "Count is %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl $1024, %edi
call malloc@PLT
movq %rax, %r13
movl $1024, %edi
call malloc@PLT
movq %rax, %r12
movl $1024, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L18:
movss %xmm1, 0(%r13,%rax)
movss %xmm0, (%r12,%rax)
addq $4, %rax
cmpq $1024, %rax
jne .L18
movl $16, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z20MatrixMultiplicationPfS_S_i
movl $1, %ebx
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r15
jmp .L20
.L19:
addq $1, %rbx
cmpq $257, %rbx
je .L24
.L20:
pxor %xmm0, %xmm0
cvtss2sd -4(%rbp,%rbx,4), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testb $15, %bl
jne .L19
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L24:
movl $256, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z15MatrixMulKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
**Author: Mark Williams
** Simple matrix multiplication using device code (NVIDIA GPU).
** Matrix size is 16*16, values are all 32 and the output is 256.
*/
#include <stdio.h>
#include <stdlib.h>
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int Width){
//2D Thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
//Pvalue stores the Pd element that is computed by the thread
float Pvalue = 0;
for(int k = 0; k < Width; ++k){
float Mdelement = Md[ty * Width + k];
float Ndelement = Nd[k * Width + tx];
Pvalue += Mdelement * Ndelement;
}
//Write the matrix to device memory each thread writes one element
Pd[ty * Width + tx] = Pvalue;
}
void MatrixMultiplication(float* M, float* N, float* P, int Width){
//Pointers for each matrix (separate matrices for device computation)
float *Md, *Nd, *Pd;
//Size to be used for memory allocation
int size = Width * Width * sizeof(float);
//Transfer matrix M and N to device memory
cudaMalloc((void**) &Md, size);
cudaMemcpy(Md, M, size, cudaMemcpyHostToDevice);
cudaMalloc((void**) &Nd, size);
cudaMemcpy(Nd, N, size, cudaMemcpyHostToDevice);
//Allocate matrix P on the device
cudaMalloc((void**) &Pd, size);
//Setup the execution configuration
dim3 dimBlock(Width, Width);
dim3 dimGrid(1,1);
//Launch the device computation threads
MatrixMulKernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, Width);
//Transfer P from device to host
cudaMemcpy(P, Pd, size, cudaMemcpyDeviceToHost);
//Free device matrices
cudaFree(Md);
cudaFree(Nd);
cudaFree(Pd);
}
int main (){
//Pointers for each matrix
float *M, *N, *P;
//Use matrix width of 16, calculate size of memory for this width
int Width = 16;
int size = Width * Width * sizeof(float);
int count = 0;
//Allocate the memory
M = (float*)malloc(size);
N = (float*)malloc(size);
P = (float*)malloc(size);
//Populate M and N with 1's and 2's, repsectively
for(int i = 0; i < (Width * Width); i++){
M[i] = 1.0;
N[i] = 2.0;
}
//Pass the matrices and width size to multiplication function
MatrixMultiplication(M, N, P, Width);
//Print out the results
for(int i = 0; i < (Width * Width); i++){
count++;
printf("%.0f ", P[i]);
if(count % 16 == 0)
printf("\n");
}
printf("Count is %d\n", count);
//Deallocate memory
free(M);
free(N);
free(P);
return 0;
} | /*
**Author: Mark Williams
** Simple matrix multiplication using device code (NVIDIA GPU).
** Matrix size is 16*16, values are all 32 and the output is 256.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int Width){
//2D Thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
//Pvalue stores the Pd element that is computed by the thread
float Pvalue = 0;
for(int k = 0; k < Width; ++k){
float Mdelement = Md[ty * Width + k];
float Ndelement = Nd[k * Width + tx];
Pvalue += Mdelement * Ndelement;
}
//Write the matrix to device memory each thread writes one element
Pd[ty * Width + tx] = Pvalue;
}
void MatrixMultiplication(float* M, float* N, float* P, int Width){
//Pointers for each matrix (separate matrices for device computation)
float *Md, *Nd, *Pd;
//Size to be used for memory allocation
int size = Width * Width * sizeof(float);
//Transfer matrix M and N to device memory
hipMalloc((void**) &Md, size);
hipMemcpy(Md, M, size, hipMemcpyHostToDevice);
hipMalloc((void**) &Nd, size);
hipMemcpy(Nd, N, size, hipMemcpyHostToDevice);
//Allocate matrix P on the device
hipMalloc((void**) &Pd, size);
//Setup the execution configuration
dim3 dimBlock(Width, Width);
dim3 dimGrid(1,1);
//Launch the device computation threads
MatrixMulKernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, Width);
//Transfer P from device to host
hipMemcpy(P, Pd, size, hipMemcpyDeviceToHost);
//Free device matrices
hipFree(Md);
hipFree(Nd);
hipFree(Pd);
}
int main (){
//Pointers for each matrix
float *M, *N, *P;
//Use matrix width of 16, calculate size of memory for this width
int Width = 16;
int size = Width * Width * sizeof(float);
int count = 0;
//Allocate the memory
M = (float*)malloc(size);
N = (float*)malloc(size);
P = (float*)malloc(size);
//Populate M and N with 1's and 2's, repsectively
for(int i = 0; i < (Width * Width); i++){
M[i] = 1.0;
N[i] = 2.0;
}
//Pass the matrices and width size to multiplication function
MatrixMultiplication(M, N, P, Width);
//Print out the results
for(int i = 0; i < (Width * Width); i++){
count++;
printf("%.0f ", P[i]);
if(count % 16 == 0)
printf("\n");
}
printf("Count is %d\n", count);
//Deallocate memory
free(M);
free(N);
free(P);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
**Author: Mark Williams
** Simple matrix multiplication using device code (NVIDIA GPU).
** Matrix size is 16*16, values are all 32 and the output is 256.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int Width){
//2D Thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
//Pvalue stores the Pd element that is computed by the thread
float Pvalue = 0;
for(int k = 0; k < Width; ++k){
float Mdelement = Md[ty * Width + k];
float Ndelement = Nd[k * Width + tx];
Pvalue += Mdelement * Ndelement;
}
//Write the matrix to device memory each thread writes one element
Pd[ty * Width + tx] = Pvalue;
}
void MatrixMultiplication(float* M, float* N, float* P, int Width){
//Pointers for each matrix (separate matrices for device computation)
float *Md, *Nd, *Pd;
//Size to be used for memory allocation
int size = Width * Width * sizeof(float);
//Transfer matrix M and N to device memory
hipMalloc((void**) &Md, size);
hipMemcpy(Md, M, size, hipMemcpyHostToDevice);
hipMalloc((void**) &Nd, size);
hipMemcpy(Nd, N, size, hipMemcpyHostToDevice);
//Allocate matrix P on the device
hipMalloc((void**) &Pd, size);
//Setup the execution configuration
dim3 dimBlock(Width, Width);
dim3 dimGrid(1,1);
//Launch the device computation threads
MatrixMulKernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, Width);
//Transfer P from device to host
hipMemcpy(P, Pd, size, hipMemcpyDeviceToHost);
//Free device matrices
hipFree(Md);
hipFree(Nd);
hipFree(Pd);
}
int main (){
//Pointers for each matrix
float *M, *N, *P;
//Use matrix width of 16, calculate size of memory for this width
int Width = 16;
int size = Width * Width * sizeof(float);
int count = 0;
//Allocate the memory
M = (float*)malloc(size);
N = (float*)malloc(size);
P = (float*)malloc(size);
//Populate M and N with 1's and 2's, repsectively
for(int i = 0; i < (Width * Width); i++){
M[i] = 1.0;
N[i] = 2.0;
}
//Pass the matrices and width size to multiplication function
MatrixMultiplication(M, N, P, Width);
//Print out the results
for(int i = 0; i < (Width * Width); i++){
count++;
printf("%.0f ", P[i]);
if(count % 16 == 0)
printf("\n");
}
printf("Count is %d\n", count);
//Deallocate memory
free(M);
free(N);
free(P);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 8
.type _Z15MatrixMulKernelPfS_S_i,@function
_Z15MatrixMulKernelPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v3, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v6, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v9, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z15MatrixMulKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
**Author: Mark Williams
** Simple matrix multiplication using device code (NVIDIA GPU).
** Matrix size is 16*16, values are all 32 and the output is 256.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void MatrixMulKernel(float *Md, float *Nd, float *Pd, int Width){
//2D Thread ID
int tx = threadIdx.x;
int ty = threadIdx.y;
//Pvalue stores the Pd element that is computed by the thread
float Pvalue = 0;
for(int k = 0; k < Width; ++k){
float Mdelement = Md[ty * Width + k];
float Ndelement = Nd[k * Width + tx];
Pvalue += Mdelement * Ndelement;
}
//Write the matrix to device memory each thread writes one element
Pd[ty * Width + tx] = Pvalue;
}
void MatrixMultiplication(float* M, float* N, float* P, int Width){
//Pointers for each matrix (separate matrices for device computation)
float *Md, *Nd, *Pd;
//Size to be used for memory allocation
int size = Width * Width * sizeof(float);
//Transfer matrix M and N to device memory
hipMalloc((void**) &Md, size);
hipMemcpy(Md, M, size, hipMemcpyHostToDevice);
hipMalloc((void**) &Nd, size);
hipMemcpy(Nd, N, size, hipMemcpyHostToDevice);
//Allocate matrix P on the device
hipMalloc((void**) &Pd, size);
//Setup the execution configuration
dim3 dimBlock(Width, Width);
dim3 dimGrid(1,1);
//Launch the device computation threads
MatrixMulKernel<<<dimGrid, dimBlock>>>(Md, Nd, Pd, Width);
//Transfer P from device to host
hipMemcpy(P, Pd, size, hipMemcpyDeviceToHost);
//Free device matrices
hipFree(Md);
hipFree(Nd);
hipFree(Pd);
}
int main (){
//Pointers for each matrix
float *M, *N, *P;
//Use matrix width of 16, calculate size of memory for this width
int Width = 16;
int size = Width * Width * sizeof(float);
int count = 0;
//Allocate the memory
M = (float*)malloc(size);
N = (float*)malloc(size);
P = (float*)malloc(size);
//Populate M and N with 1's and 2's, repsectively
for(int i = 0; i < (Width * Width); i++){
M[i] = 1.0;
N[i] = 2.0;
}
//Pass the matrices and width size to multiplication function
MatrixMultiplication(M, N, P, Width);
//Print out the results
for(int i = 0; i < (Width * Width); i++){
count++;
printf("%.0f ", P[i]);
if(count % 16 == 0)
printf("\n");
}
printf("Count is %d\n", count);
//Deallocate memory
free(M);
free(N);
free(P);
return 0;
} | .text
.file "multiply.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_i,@function
_Z30__device_stub__MatrixMulKernelPfS_S_i: # @_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z20MatrixMultiplicationPfS_S_i # -- Begin function _Z20MatrixMultiplicationPfS_S_i
.p2align 4, 0x90
.type _Z20MatrixMultiplicationPfS_S_i,@function
_Z20MatrixMultiplicationPfS_S_i: # @_Z20MatrixMultiplicationPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r12
movl %ecx, %eax
imull %ecx, %eax
shll $2, %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %ebp, %eax
movq %rax, %rdx
shlq $32, %rdx
orq %rax, %rdx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z20MatrixMultiplicationPfS_S_i, .Lfunc_end1-_Z20MatrixMultiplicationPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB2_1
# %bb.2:
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $16, %ecx
callq _Z20MatrixMultiplicationPfS_S_i
movl $1, %r12d
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
incq %r12
cmpq $257, %r12 # imm = 0x101
je .LBB2_6
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss -4(%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
testb $15, %r12b
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_5
.LBB2_6:
movl $.L.str.2, %edi
movl $256, %esi # imm = 0x100
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPfS_S_i,@object # @_Z15MatrixMulKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_S_i:
.quad _Z30__device_stub__MatrixMulKernelPfS_S_i
.size _Z15MatrixMulKernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.0f "
.size .L.str, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Count is %d\n"
.size .L.str.2, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15MatrixMulKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002200 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x001fd800078e02ff */
/*0080*/ @!P0 BRA 0xbb0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*00c0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*00e0*/ @!P0 BRA 0xa90 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0100*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0110*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0130*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0150*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x002fcc00078e0219 */
/*0160*/ @!P0 BRA 0x900 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x640 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01c0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*01d0*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*01e0*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*01f0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0210*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0220*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0230*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0240*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0250*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*0260*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*0270*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*0280*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*02c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*02d0*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0300*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0310*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0320*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0330*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0340*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0350*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0360*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*0370*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*0380*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0390*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03a0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03b0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*03c0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*03d0*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*03e0*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*03f0*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0420*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0430*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0440*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0450*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*0460*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*0470*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*0480*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0490*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04a0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04b0*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*04c0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*04d0*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*04e0*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*04f0*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0510*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0520*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0530*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*0540*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0570*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*0580*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0590*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05a0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05b0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05c0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*05e0*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*05f0*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0600*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0610*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0620*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0630*/ @P1 BRA 0x1b0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0640*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0650*/ @!P1 BRA 0x8e0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*0670*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0680*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0690*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06a0*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x000fe200078e0210 */
/*06b0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06c0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*06d0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*06e0*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*06f0*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0710*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0720*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0730*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*0740*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0750*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0760*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*0770*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0790*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*07a0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07b0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07c0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*07d0*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*07e0*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0800*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0810*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0820*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0830*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0840*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0850*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*0860*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*0870*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*0880*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0890*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08a0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08b0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*08c0*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*08d0*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*08e0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08f0*/ @!P0 BRA 0xa90 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0900*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0910*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0920*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0930*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0940*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0950*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*0960*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*0980*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0990*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09c0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*09d0*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*09e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*09f0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a00*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a10*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a20*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a30*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a40*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a50*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0a60*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0a70*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0a80*/ @P0 BRA 0x900 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0aa0*/ @!P0 BRA 0xbb0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0ac0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0ad0*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x002fd000078e0200 */
/*0ae0*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0af0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b00*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b10*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b20*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b30*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b40*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b70*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0b80*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0b90*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0ba0*/ @P0 BRA 0xb10 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bb0*/ IADD3 R2, R4, R0, RZ ; /* 0x0000000004027210 */
/* 0x002fe40007ffe0ff */
/*0bc0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0bd0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0be0*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0bf0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 8
.type _Z15MatrixMulKernelPfS_S_i,@function
_Z15MatrixMulKernelPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v3, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v6, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v9, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z15MatrixMulKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a493c_00000000-6_multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.type _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
.globl _Z15MatrixMulKernelPfS_S_i
.type _Z15MatrixMulKernelPfS_S_i, @function
_Z15MatrixMulKernelPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15MatrixMulKernelPfS_S_i, .-_Z15MatrixMulKernelPfS_S_i
.globl _Z20MatrixMultiplicationPfS_S_i
.type _Z20MatrixMultiplicationPfS_S_i, @function
_Z20MatrixMultiplicationPfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %ecx, %ebx
imull %ecx, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %ebp, 32(%rsp)
movl %ebp, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z15MatrixMulKernelPfS_S_iPfS_S_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z20MatrixMultiplicationPfS_S_i, .-_Z20MatrixMultiplicationPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%.0f "
.LC3:
.string "\n"
.LC4:
.string "Count is %d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl $1024, %edi
call malloc@PLT
movq %rax, %r13
movl $1024, %edi
call malloc@PLT
movq %rax, %r12
movl $1024, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L18:
movss %xmm1, 0(%r13,%rax)
movss %xmm0, (%r12,%rax)
addq $4, %rax
cmpq $1024, %rax
jne .L18
movl $16, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z20MatrixMultiplicationPfS_S_i
movl $1, %ebx
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r15
jmp .L20
.L19:
addq $1, %rbx
cmpq $257, %rbx
je .L24
.L20:
pxor %xmm0, %xmm0
cvtss2sd -4(%rbp,%rbx,4), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testb $15, %bl
jne .L19
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L24:
movl $256, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z15MatrixMulKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multiply.hip"
.globl _Z30__device_stub__MatrixMulKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPfS_S_i,@function
_Z30__device_stub__MatrixMulKernelPfS_S_i: # @_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z20MatrixMultiplicationPfS_S_i # -- Begin function _Z20MatrixMultiplicationPfS_S_i
.p2align 4, 0x90
.type _Z20MatrixMultiplicationPfS_S_i,@function
_Z20MatrixMultiplicationPfS_S_i: # @_Z20MatrixMultiplicationPfS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r12
movl %ecx, %eax
imull %ecx, %eax
shll $2, %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %ebp, %eax
movq %rax, %rdx
shlq $32, %rdx
orq %rax, %rdx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15MatrixMulKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z20MatrixMultiplicationPfS_S_i, .Lfunc_end1-_Z20MatrixMultiplicationPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB2_1
# %bb.2:
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $16, %ecx
callq _Z20MatrixMultiplicationPfS_S_i
movl $1, %r12d
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
incq %r12
cmpq $257, %r12 # imm = 0x101
je .LBB2_6
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss -4(%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
testb $15, %r12b
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_5
.LBB2_6:
movl $.L.str.2, %edi
movl $256, %esi # imm = 0x100
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPfS_S_i,@object # @_Z15MatrixMulKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPfS_S_i
.p2align 3, 0x0
_Z15MatrixMulKernelPfS_S_i:
.quad _Z30__device_stub__MatrixMulKernelPfS_S_i
.size _Z15MatrixMulKernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.0f "
.size .L.str, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Count is %d\n"
.size .L.str.2, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPfS_S_i"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void bitflip_kernel(float* M, int height, int row, int n) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int off = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < n; i += off){
M[i * height + row] = 1 - M[i * height + row];
}
} | code for sm_80
Function : _Z14bitflip_kernelPfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fe200000001ff */
/*0080*/ MOV R3, c[0x0][0x168] ; /* 0x00005a0000037a02 */
/* 0x000fca0000000f00 */
/*0090*/ IMAD R2, R0, R3, c[0x0][0x16c] ; /* 0x00005b0000027624 */
/* 0x000fc800078e0203 */
/*00a0*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*00b0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fca0000000f00 */
/*00d0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*00f0*/ FADD R5, -R4, 1 ; /* 0x3f80000004057421 */
/* 0x004fca0000000100 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ee000c101904 */
/*0110*/ @!P0 BRA 0x70 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void bitflip_kernel(float* M, int height, int row, int n) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int off = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < n; i += off){
M[i * height + row] = 1 - M[i * height + row];
}
} | .file "tmpxft_0010853c_00000000-6_bitflip_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14bitflip_kernelPfiiiPfiii
.type _Z37__device_stub__Z14bitflip_kernelPfiiiPfiii, @function
_Z37__device_stub__Z14bitflip_kernelPfiiiPfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14bitflip_kernelPfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z14bitflip_kernelPfiiiPfiii, .-_Z37__device_stub__Z14bitflip_kernelPfiiiPfiii
.globl _Z14bitflip_kernelPfiii
.type _Z14bitflip_kernelPfiii, @function
_Z14bitflip_kernelPfiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14bitflip_kernelPfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14bitflip_kernelPfiii, .-_Z14bitflip_kernelPfiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14bitflip_kernelPfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14bitflip_kernelPfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void bitflip_kernel(float* M, int height, int row, int n) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int off = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < n; i += off){
M[i * height + row] = 1 - M[i * height + row];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void bitflip_kernel(float* M, int height, int row, int n) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int off = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < n; i += off){
M[i * height + row] = 1 - M[i * height + row];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void bitflip_kernel(float* M, int height, int row, int n) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int off = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < n; i += off){
M[i * height + row] = 1 - M[i * height + row];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14bitflip_kernelPfiii
.globl _Z14bitflip_kernelPfiii
.p2align 8
.type _Z14bitflip_kernelPfiii,@function
_Z14bitflip_kernelPfiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
s_load_b32 s5, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_mov_b32 s4, s3
s_mul_i32 s3, s5, s7
v_mad_u64_u32 v[2:3], null, s2, v1, s[4:5]
v_mov_b32_e32 v3, 0
s_mul_i32 s2, s3, s2
s_mov_b32 s4, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_dual_sub_f32 v0, 1.0, v0 :: v_dual_add_nc_u32 v1, s3, v1
v_cmp_le_u32_e32 vcc_lo, s6, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14bitflip_kernelPfiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14bitflip_kernelPfiii, .Lfunc_end0-_Z14bitflip_kernelPfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14bitflip_kernelPfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14bitflip_kernelPfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void bitflip_kernel(float* M, int height, int row, int n) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
int off = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < n; i += off){
M[i * height + row] = 1 - M[i * height + row];
}
} | .text
.file "bitflip_kernel.hip"
.globl _Z29__device_stub__bitflip_kernelPfiii # -- Begin function _Z29__device_stub__bitflip_kernelPfiii
.p2align 4, 0x90
.type _Z29__device_stub__bitflip_kernelPfiii,@function
_Z29__device_stub__bitflip_kernelPfiii: # @_Z29__device_stub__bitflip_kernelPfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14bitflip_kernelPfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__bitflip_kernelPfiii, .Lfunc_end0-_Z29__device_stub__bitflip_kernelPfiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14bitflip_kernelPfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14bitflip_kernelPfiii,@object # @_Z14bitflip_kernelPfiii
.section .rodata,"a",@progbits
.globl _Z14bitflip_kernelPfiii
.p2align 3, 0x0
_Z14bitflip_kernelPfiii:
.quad _Z29__device_stub__bitflip_kernelPfiii
.size _Z14bitflip_kernelPfiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14bitflip_kernelPfiii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__bitflip_kernelPfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14bitflip_kernelPfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14bitflip_kernelPfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x001fe200000001ff */
/*0080*/ MOV R3, c[0x0][0x168] ; /* 0x00005a0000037a02 */
/* 0x000fca0000000f00 */
/*0090*/ IMAD R2, R0, R3, c[0x0][0x16c] ; /* 0x00005b0000027624 */
/* 0x000fc800078e0203 */
/*00a0*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*00b0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fca0000000f00 */
/*00d0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*00f0*/ FADD R5, -R4, 1 ; /* 0x3f80000004057421 */
/* 0x004fca0000000100 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001ee000c101904 */
/*0110*/ @!P0 BRA 0x70 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14bitflip_kernelPfiii
.globl _Z14bitflip_kernelPfiii
.p2align 8
.type _Z14bitflip_kernelPfiii,@function
_Z14bitflip_kernelPfiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s6, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
s_load_b32 s5, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_mov_b32 s4, s3
s_mul_i32 s3, s5, s7
v_mad_u64_u32 v[2:3], null, s2, v1, s[4:5]
v_mov_b32_e32 v3, 0
s_mul_i32 s2, s3, s2
s_mov_b32 s4, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_dual_sub_f32 v0, 1.0, v0 :: v_dual_add_nc_u32 v1, s3, v1
v_cmp_le_u32_e32 vcc_lo, s6, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14bitflip_kernelPfiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14bitflip_kernelPfiii, .Lfunc_end0-_Z14bitflip_kernelPfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14bitflip_kernelPfiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14bitflip_kernelPfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010853c_00000000-6_bitflip_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14bitflip_kernelPfiiiPfiii
.type _Z37__device_stub__Z14bitflip_kernelPfiiiPfiii, @function
_Z37__device_stub__Z14bitflip_kernelPfiiiPfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14bitflip_kernelPfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z14bitflip_kernelPfiiiPfiii, .-_Z37__device_stub__Z14bitflip_kernelPfiiiPfiii
.globl _Z14bitflip_kernelPfiii
.type _Z14bitflip_kernelPfiii, @function
_Z14bitflip_kernelPfiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14bitflip_kernelPfiiiPfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14bitflip_kernelPfiii, .-_Z14bitflip_kernelPfiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14bitflip_kernelPfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14bitflip_kernelPfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bitflip_kernel.hip"
.globl _Z29__device_stub__bitflip_kernelPfiii # -- Begin function _Z29__device_stub__bitflip_kernelPfiii
.p2align 4, 0x90
.type _Z29__device_stub__bitflip_kernelPfiii,@function
_Z29__device_stub__bitflip_kernelPfiii: # @_Z29__device_stub__bitflip_kernelPfiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14bitflip_kernelPfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__bitflip_kernelPfiii, .Lfunc_end0-_Z29__device_stub__bitflip_kernelPfiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14bitflip_kernelPfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14bitflip_kernelPfiii,@object # @_Z14bitflip_kernelPfiii
.section .rodata,"a",@progbits
.globl _Z14bitflip_kernelPfiii
.p2align 3, 0x0
_Z14bitflip_kernelPfiii:
.quad _Z29__device_stub__bitflip_kernelPfiii
.size _Z14bitflip_kernelPfiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14bitflip_kernelPfiii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__bitflip_kernelPfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14bitflip_kernelPfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <math.h>
#include <stdio.h>
#define N 2048*2048 // Number of elements in each vector
#define rowcol2idx(num, r, c) ((r)*(num)+(c))
/*
* Optimize this already-accelerated codebase. Work iteratively,
* and use nvprof to support your work.
*
* Aim to profile `saxpy` (without modifying `N`) running under
* 20us.
*
* Some bugs have been placed in this codebase for your edification.
*/
__global__ void saxpy(int *a, int *b, int *c, int base)
{
/*
int tid = threadIdx.x + blockIdx.x * blockDim.x;
for (; tid < N; tid += stride)
c[tid] = (a[tid]<<1) + b[tid];
*/
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
int tid = rowcol2idx(gridDim.x*blockDim.x, row, col)+base;
if (tid < N)
c[tid] = (a[tid]<<1) + b[tid];
}
/*
__global__ void init_array(int *a, int *b, int *c)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (; tid < N; tid += stride) {
a[tid] = 2;
b[tid] = 1;
c[tid] = 0;
}
}
*/
__global__ void init_array(int *a, int target, int stride)
{
for (int tid = threadIdx.x + blockIdx.x * blockDim.x; tid < N; tid += stride)
a[tid] = target;
}
int main()
{
int *a, *b, *c;
int size = N*sizeof(int); // The total number of bytes per vector
cudaMallocManaged(&a, size);
cudaMallocManaged(&b, size);
cudaMallocManaged(&c, size);
int deviceId;
cudaDeviceProp props;
cudaGetDevice(&deviceId);
cudaGetDeviceProperties(&props, deviceId);
int multiProcessorCount = props.multiProcessorCount;
size_t threadsPerBlock = 1024;
size_t numberOfBlocks = ((N>>10)/multiProcessorCount+1)*multiProcessorCount;
// i first prefetch pages...
cudaMemPrefetchAsync(a, size, deviceId);
cudaMemPrefetchAsync(b, size, deviceId);
init_array<<<numberOfBlocks, threadsPerBlock>>>(a,2,threadsPerBlock*numberOfBlocks);
init_array<<<numberOfBlocks, threadsPerBlock>>>(b,1,threadsPerBlock*numberOfBlocks);
// we have no need to initialize array c, because of default value is 0.
//init_array<<<numberOfBlocks, threadsPerBlock>>>(c,0,threadsPerBlock*numberOfBlocks);
cudaDeviceSynchronize();
//printf("sm numer = %d\n", multiProcessorCount);
cudaMemPrefetchAsync(c, size, deviceId);
//saxpy <<<numberOfBlocks, threadsPerBlock>>>(a,b,c,threadsPerBlock*numberOfBlocks);
int len = 40;
dim3 threads_per_block(32, 32, 1);
dim3 number_of_blocks(len, len, 1);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 0);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 1600*1024);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 3200*1024);
cudaDeviceSynchronize();
cudaMemPrefetchAsync(c, size, cudaCpuDeviceId);
// Print out the first and last 5 values of c for a quality check
for( int i = 0; i < 5; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
for( int i = N-5; i < N; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
cudaFree(a);
cudaFree(b);
cudaFree(c);
} | code for sm_80
Function : _Z10init_arrayPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x3fffff, PT ; /* 0x003fffff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ I2F.U32.RP R4, c[0x0][0x16c] ; /* 0x00005b0000047b06 */
/* 0x000e220000209000 */
/*0070*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0080*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fe20003f45070 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ BSSY B0, 0x2a0 ; /* 0x000001f000007945 */
/* 0x000fe80003800000 */
/*00b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00c0*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*00e0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x001fc800078e0a03 */
/*00f0*/ IMAD R5, R5, c[0x0][0x16c], RZ ; /* 0x00005b0005057a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R5, R3, R5, R2 ; /* 0x0000000503057227 */
/* 0x000fe200078e0002 */
/*0110*/ IADD3 R2, -R0, 0x3fffff, RZ ; /* 0x003fffff00027810 */
/* 0x000fca0007ffe1ff */
/*0120*/ IMAD.HI.U32 R5, R5, R2, RZ ; /* 0x0000000205057227 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a05 */
/*0140*/ IMAD R2, R7, c[0x0][0x16c], R2 ; /* 0x00005b0007027a24 */
/* 0x000fca00078e0202 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06070 */
/*0160*/ @P0 IADD3 R2, R2, -c[0x0][0x16c], RZ ; /* 0x80005b0002020a10 */
/* 0x000fe40007ffe0ff */
/*0170*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fda0003f26070 */
/*0190*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff05aa12 */
/* 0x000fc800078e33ff */
/*01b0*/ IADD3 R2, R5.reuse, 0x1, RZ ; /* 0x0000000105027810 */
/* 0x040fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f26070 */
/*01d0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*01e0*/ @!P0 BRA 0x290 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0200*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff077624 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*0230*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0240*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101904 */
/*0250*/ IADD3 R0, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a10 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0270*/ IMAD.WIDE R2, R5, c[0x0][0x16c], R2 ; /* 0x00005b0005027a25 */
/* 0x001fd800078e0202 */
/*0280*/ @P0 BRA 0x230 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*02c0*/ MOV R13, c[0x0][0x168] ; /* 0x00005a00000d7a02 */
/* 0x000fc60000000f00 */
/*02d0*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fe200078e020b */
/*02e0*/ MOV R17, c[0x0][0x16c] ; /* 0x00005b0000117a02 */
/* 0x000fc60000000f00 */
/*02f0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0f7624 */
/* 0x000fe200078e00ff */
/*0300*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e2000c101904 */
/*0310*/ IMAD.WIDE R4, R11, c[0x0][0x16c], R2 ; /* 0x00005b000b047a25 */
/* 0x000fc800078e0202 */
/*0320*/ IMAD R0, R15, 0x2, R0 ; /* 0x000000020f007824 */
/* 0x000fe200078e0200 */
/*0330*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0001e2000c101904 */
/*0340*/ IMAD.WIDE R6, R11, c[0x0][0x16c], R4 ; /* 0x00005b000b067a25 */
/* 0x000fc600078e0204 */
/*0350*/ LEA R0, R17, R0, 0x1 ; /* 0x0000000011007211 */
/* 0x000fe400078e08ff */
/*0360*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e2000c101904 */
/*0370*/ IMAD.WIDE R8, R11, c[0x0][0x16c], R6 ; /* 0x00005b000b087a25 */
/* 0x000fe200078e0206 */
/*0380*/ ISETP.GE.AND P0, PT, R0, 0x400000, PT ; /* 0x004000000000780c */
/* 0x000fc80003f06270 */
/*0390*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x0001f2000c101904 */
/*03a0*/ @!P0 BRA 0x2d0 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ BRA 0x3c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5saxpyPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000ea20000002500 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe200078e0203 */
/*0060*/ IADD3 R3, R2, c[0x0][0x178], RZ ; /* 0x00005e0002037a10 */
/* 0x002fc60007ffe0ff */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x004fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x000fca00078e0203 */
/*0090*/ ISETP.GT.AND P0, PT, R0, 0x3fffff, PT ; /* 0x003fffff0000780c */
/* 0x000fda0003f04270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0120*/ LEA R9, R2, R5, 0x1 ; /* 0x0000000502097211 */
/* 0x004fca00078e08ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math.h>
#include <stdio.h>
#define N 2048*2048 // Number of elements in each vector
#define rowcol2idx(num, r, c) ((r)*(num)+(c))
/*
* Optimize this already-accelerated codebase. Work iteratively,
* and use nvprof to support your work.
*
* Aim to profile `saxpy` (without modifying `N`) running under
* 20us.
*
* Some bugs have been placed in this codebase for your edification.
*/
__global__ void saxpy(int *a, int *b, int *c, int base)
{
/*
int tid = threadIdx.x + blockIdx.x * blockDim.x;
for (; tid < N; tid += stride)
c[tid] = (a[tid]<<1) + b[tid];
*/
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
int tid = rowcol2idx(gridDim.x*blockDim.x, row, col)+base;
if (tid < N)
c[tid] = (a[tid]<<1) + b[tid];
}
/*
__global__ void init_array(int *a, int *b, int *c)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (; tid < N; tid += stride) {
a[tid] = 2;
b[tid] = 1;
c[tid] = 0;
}
}
*/
__global__ void init_array(int *a, int target, int stride)
{
for (int tid = threadIdx.x + blockIdx.x * blockDim.x; tid < N; tid += stride)
a[tid] = target;
}
int main()
{
int *a, *b, *c;
int size = N*sizeof(int); // The total number of bytes per vector
cudaMallocManaged(&a, size);
cudaMallocManaged(&b, size);
cudaMallocManaged(&c, size);
int deviceId;
cudaDeviceProp props;
cudaGetDevice(&deviceId);
cudaGetDeviceProperties(&props, deviceId);
int multiProcessorCount = props.multiProcessorCount;
size_t threadsPerBlock = 1024;
size_t numberOfBlocks = ((N>>10)/multiProcessorCount+1)*multiProcessorCount;
// i first prefetch pages...
cudaMemPrefetchAsync(a, size, deviceId);
cudaMemPrefetchAsync(b, size, deviceId);
init_array<<<numberOfBlocks, threadsPerBlock>>>(a,2,threadsPerBlock*numberOfBlocks);
init_array<<<numberOfBlocks, threadsPerBlock>>>(b,1,threadsPerBlock*numberOfBlocks);
// we have no need to initialize array c, because of default value is 0.
//init_array<<<numberOfBlocks, threadsPerBlock>>>(c,0,threadsPerBlock*numberOfBlocks);
cudaDeviceSynchronize();
//printf("sm numer = %d\n", multiProcessorCount);
cudaMemPrefetchAsync(c, size, deviceId);
//saxpy <<<numberOfBlocks, threadsPerBlock>>>(a,b,c,threadsPerBlock*numberOfBlocks);
int len = 40;
dim3 threads_per_block(32, 32, 1);
dim3 number_of_blocks(len, len, 1);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 0);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 1600*1024);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 3200*1024);
cudaDeviceSynchronize();
cudaMemPrefetchAsync(c, size, cudaCpuDeviceId);
// Print out the first and last 5 values of c for a quality check
for( int i = 0; i < 5; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
for( int i = N-5; i < N; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
cudaFree(a);
cudaFree(b);
cudaFree(c);
} | .file "tmpxft_00017d84_00000000-6_01-saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i
.type _Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i, @function
_Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i, .-_Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i
.globl _Z5saxpyPiS_S_i
.type _Z5saxpyPiS_S_i, @function
_Z5saxpyPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5saxpyPiS_S_i, .-_Z5saxpyPiS_S_i
.globl _Z32__device_stub__Z10init_arrayPiiiPiii
.type _Z32__device_stub__Z10init_arrayPiiiPiii, @function
_Z32__device_stub__Z10init_arrayPiiiPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10init_arrayPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z10init_arrayPiiiPiii, .-_Z32__device_stub__Z10init_arrayPiiiPiii
.globl _Z10init_arrayPiii
.type _Z10init_arrayPiii, @function
_Z10init_arrayPiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10init_arrayPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10init_arrayPiii, .-_Z10init_arrayPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "c[%d] = %d, "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1104, %rsp
.cfi_def_cfa_offset 1136
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 64(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl 452(%rsp), %ebp
movl $0, %ecx
movl 12(%rsp), %edx
movl $16777216, %esi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl 12(%rsp), %edx
movl $16777216, %esi
movq 24(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $1024, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $4096, %eax
movl $0, %edx
idivl %ebp
leal 1(%rax), %ebx
imull %ebp, %ebx
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L20:
movl $1024, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L21:
call cudaDeviceSynchronize@PLT
movl $0, %ecx
movl 12(%rsp), %edx
movl $16777216, %esi
movq 32(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $32, 40(%rsp)
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $40, 52(%rsp)
movl $40, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L22:
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L23:
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L24:
call cudaDeviceSynchronize@PLT
movl $0, %ecx
movl $-1, %edx
movl $16777216, %esi
movq 32(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L25:
movq 32(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L25
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16777196, %ebp
movl $4194299, %ebx
leaq .LC0(%rip), %r12
.L26:
movq 32(%rsp), %rax
movl (%rax,%rbp), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
addq $4, %rbp
cmpl $4194304, %ebx
jne .L26
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $1104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl %ebx, %edx
sall $10, %edx
movl $2, %esi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z10init_arrayPiiiPiii
jmp .L20
.L32:
movl %ebx, %edx
sall $10, %edx
movl $1, %esi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z10init_arrayPiiiPiii
jmp .L21
.L33:
movl $0, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i
jmp .L22
.L34:
movl $1638400, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i
jmp .L23
.L35:
movl $3276800, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i
jmp .L24
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10init_arrayPiii"
.LC3:
.string "_Z5saxpyPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10init_arrayPiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#include <stdio.h>
#define N 2048*2048 // Number of elements in each vector
#define rowcol2idx(num, r, c) ((r)*(num)+(c))
/*
* Optimize this already-accelerated codebase. Work iteratively,
* and use nvprof to support your work.
*
* Aim to profile `saxpy` (without modifying `N`) running under
* 20us.
*
* Some bugs have been placed in this codebase for your edification.
*/
__global__ void saxpy(int *a, int *b, int *c, int base)
{
/*
int tid = threadIdx.x + blockIdx.x * blockDim.x;
for (; tid < N; tid += stride)
c[tid] = (a[tid]<<1) + b[tid];
*/
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
int tid = rowcol2idx(gridDim.x*blockDim.x, row, col)+base;
if (tid < N)
c[tid] = (a[tid]<<1) + b[tid];
}
/*
__global__ void init_array(int *a, int *b, int *c)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (; tid < N; tid += stride) {
a[tid] = 2;
b[tid] = 1;
c[tid] = 0;
}
}
*/
__global__ void init_array(int *a, int target, int stride)
{
for (int tid = threadIdx.x + blockIdx.x * blockDim.x; tid < N; tid += stride)
a[tid] = target;
}
int main()
{
int *a, *b, *c;
int size = N*sizeof(int); // The total number of bytes per vector
cudaMallocManaged(&a, size);
cudaMallocManaged(&b, size);
cudaMallocManaged(&c, size);
int deviceId;
cudaDeviceProp props;
cudaGetDevice(&deviceId);
cudaGetDeviceProperties(&props, deviceId);
int multiProcessorCount = props.multiProcessorCount;
size_t threadsPerBlock = 1024;
size_t numberOfBlocks = ((N>>10)/multiProcessorCount+1)*multiProcessorCount;
// i first prefetch pages...
cudaMemPrefetchAsync(a, size, deviceId);
cudaMemPrefetchAsync(b, size, deviceId);
init_array<<<numberOfBlocks, threadsPerBlock>>>(a,2,threadsPerBlock*numberOfBlocks);
init_array<<<numberOfBlocks, threadsPerBlock>>>(b,1,threadsPerBlock*numberOfBlocks);
// we have no need to initialize array c, because of default value is 0.
//init_array<<<numberOfBlocks, threadsPerBlock>>>(c,0,threadsPerBlock*numberOfBlocks);
cudaDeviceSynchronize();
//printf("sm numer = %d\n", multiProcessorCount);
cudaMemPrefetchAsync(c, size, deviceId);
//saxpy <<<numberOfBlocks, threadsPerBlock>>>(a,b,c,threadsPerBlock*numberOfBlocks);
int len = 40;
dim3 threads_per_block(32, 32, 1);
dim3 number_of_blocks(len, len, 1);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 0);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 1600*1024);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 3200*1024);
cudaDeviceSynchronize();
cudaMemPrefetchAsync(c, size, cudaCpuDeviceId);
// Print out the first and last 5 values of c for a quality check
for( int i = 0; i < 5; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
for( int i = N-5; i < N; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
cudaFree(a);
cudaFree(b);
cudaFree(c);
} | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#define N 2048*2048 // Number of elements in each vector
#define rowcol2idx(num, r, c) ((r)*(num)+(c))
/*
* Optimize this already-accelerated codebase. Work iteratively,
* and use nvprof to support your work.
*
* Aim to profile `saxpy` (without modifying `N`) running under
* 20us.
*
* Some bugs have been placed in this codebase for your edification.
*/
__global__ void saxpy(int *a, int *b, int *c, int base)
{
/*
int tid = threadIdx.x + blockIdx.x * blockDim.x;
for (; tid < N; tid += stride)
c[tid] = (a[tid]<<1) + b[tid];
*/
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
int tid = rowcol2idx(gridDim.x*blockDim.x, row, col)+base;
if (tid < N)
c[tid] = (a[tid]<<1) + b[tid];
}
/*
__global__ void init_array(int *a, int *b, int *c)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (; tid < N; tid += stride) {
a[tid] = 2;
b[tid] = 1;
c[tid] = 0;
}
}
*/
__global__ void init_array(int *a, int target, int stride)
{
for (int tid = threadIdx.x + blockIdx.x * blockDim.x; tid < N; tid += stride)
a[tid] = target;
}
int main()
{
int *a, *b, *c;
int size = N*sizeof(int); // The total number of bytes per vector
hipMallocManaged(&a, size);
hipMallocManaged(&b, size);
hipMallocManaged(&c, size);
int deviceId;
hipDeviceProp_t props;
hipGetDevice(&deviceId);
hipGetDeviceProperties(&props, deviceId);
int multiProcessorCount = props.multiProcessorCount;
size_t threadsPerBlock = 1024;
size_t numberOfBlocks = ((N>>10)/multiProcessorCount+1)*multiProcessorCount;
// i first prefetch pages...
hipMemPrefetchAsync(a, size, deviceId);
hipMemPrefetchAsync(b, size, deviceId);
init_array<<<numberOfBlocks, threadsPerBlock>>>(a,2,threadsPerBlock*numberOfBlocks);
init_array<<<numberOfBlocks, threadsPerBlock>>>(b,1,threadsPerBlock*numberOfBlocks);
// we have no need to initialize array c, because of default value is 0.
//init_array<<<numberOfBlocks, threadsPerBlock>>>(c,0,threadsPerBlock*numberOfBlocks);
hipDeviceSynchronize();
//printf("sm numer = %d\n", multiProcessorCount);
hipMemPrefetchAsync(c, size, deviceId);
//saxpy <<<numberOfBlocks, threadsPerBlock>>>(a,b,c,threadsPerBlock*numberOfBlocks);
int len = 40;
dim3 threads_per_block(32, 32, 1);
dim3 number_of_blocks(len, len, 1);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 0);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 1600*1024);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 3200*1024);
hipDeviceSynchronize();
hipMemPrefetchAsync(c, size, hipCpuDeviceId);
// Print out the first and last 5 values of c for a quality check
for( int i = 0; i < 5; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
for( int i = N-5; i < N; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
hipFree(a);
hipFree(b);
hipFree(c);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#define N 2048*2048 // Number of elements in each vector
#define rowcol2idx(num, r, c) ((r)*(num)+(c))
/*
* Optimize this already-accelerated codebase. Work iteratively,
* and use nvprof to support your work.
*
* Aim to profile `saxpy` (without modifying `N`) running under
* 20us.
*
* Some bugs have been placed in this codebase for your edification.
*/
__global__ void saxpy(int *a, int *b, int *c, int base)
{
/*
int tid = threadIdx.x + blockIdx.x * blockDim.x;
for (; tid < N; tid += stride)
c[tid] = (a[tid]<<1) + b[tid];
*/
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
int tid = rowcol2idx(gridDim.x*blockDim.x, row, col)+base;
if (tid < N)
c[tid] = (a[tid]<<1) + b[tid];
}
/*
__global__ void init_array(int *a, int *b, int *c)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (; tid < N; tid += stride) {
a[tid] = 2;
b[tid] = 1;
c[tid] = 0;
}
}
*/
__global__ void init_array(int *a, int target, int stride)
{
for (int tid = threadIdx.x + blockIdx.x * blockDim.x; tid < N; tid += stride)
a[tid] = target;
}
int main()
{
int *a, *b, *c;
int size = N*sizeof(int); // The total number of bytes per vector
hipMallocManaged(&a, size);
hipMallocManaged(&b, size);
hipMallocManaged(&c, size);
int deviceId;
hipDeviceProp_t props;
hipGetDevice(&deviceId);
hipGetDeviceProperties(&props, deviceId);
int multiProcessorCount = props.multiProcessorCount;
size_t threadsPerBlock = 1024;
size_t numberOfBlocks = ((N>>10)/multiProcessorCount+1)*multiProcessorCount;
// i first prefetch pages...
hipMemPrefetchAsync(a, size, deviceId);
hipMemPrefetchAsync(b, size, deviceId);
init_array<<<numberOfBlocks, threadsPerBlock>>>(a,2,threadsPerBlock*numberOfBlocks);
init_array<<<numberOfBlocks, threadsPerBlock>>>(b,1,threadsPerBlock*numberOfBlocks);
// we have no need to initialize array c, because of default value is 0.
//init_array<<<numberOfBlocks, threadsPerBlock>>>(c,0,threadsPerBlock*numberOfBlocks);
hipDeviceSynchronize();
//printf("sm numer = %d\n", multiProcessorCount);
hipMemPrefetchAsync(c, size, deviceId);
//saxpy <<<numberOfBlocks, threadsPerBlock>>>(a,b,c,threadsPerBlock*numberOfBlocks);
int len = 40;
dim3 threads_per_block(32, 32, 1);
dim3 number_of_blocks(len, len, 1);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 0);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 1600*1024);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 3200*1024);
hipDeviceSynchronize();
hipMemPrefetchAsync(c, size, hipCpuDeviceId);
// Print out the first and last 5 values of c for a quality check
for( int i = 0; i < 5; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
for( int i = N-5; i < N; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
hipFree(a);
hipFree(b);
hipFree(c);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyPiS_S_i
.globl _Z5saxpyPiS_S_i
.p2align 8
.type _Z5saxpyPiS_S_i,@function
_Z5saxpyPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b32 s4, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mul_lo_u32 v1, v3, s2
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v0, s4, v1
v_cmpx_gt_i32_e32 0x400000, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_lshl_add_u32 v2, v2, 1, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyPiS_S_i, .Lfunc_end0-_Z5saxpyPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10init_arrayPiii
.globl _Z10init_arrayPiii
.p2align 8
.type _Z10init_arrayPiii,@function
_Z10init_arrayPiii:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x400000, v1
s_cbranch_execz .LBB1_3
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_mov_b32_e32 v0, s2
s_ashr_i32 s5, s3, 31
s_mov_b32 s4, s3
s_mov_b32 s1, 0
s_lshl_b64 s[4:5], s[4:5], 2
.LBB1_2:
v_add_nc_u32_e32 v1, s3, v1
global_store_b32 v[2:3], v0, off
v_add_co_u32 v2, s0, v2, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
v_cmp_lt_i32_e32 vcc_lo, 0x3fffff, v1
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10init_arrayPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10init_arrayPiii, .Lfunc_end1-_Z10init_arrayPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10init_arrayPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10init_arrayPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#define N 2048*2048 // Number of elements in each vector
#define rowcol2idx(num, r, c) ((r)*(num)+(c))
/*
* Optimize this already-accelerated codebase. Work iteratively,
* and use nvprof to support your work.
*
* Aim to profile `saxpy` (without modifying `N`) running under
* 20us.
*
* Some bugs have been placed in this codebase for your edification.
*/
__global__ void saxpy(int *a, int *b, int *c, int base)
{
/*
int tid = threadIdx.x + blockIdx.x * blockDim.x;
for (; tid < N; tid += stride)
c[tid] = (a[tid]<<1) + b[tid];
*/
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
int tid = rowcol2idx(gridDim.x*blockDim.x, row, col)+base;
if (tid < N)
c[tid] = (a[tid]<<1) + b[tid];
}
/*
__global__ void init_array(int *a, int *b, int *c)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int stride = blockDim.x * gridDim.x;
for (; tid < N; tid += stride) {
a[tid] = 2;
b[tid] = 1;
c[tid] = 0;
}
}
*/
__global__ void init_array(int *a, int target, int stride)
{
for (int tid = threadIdx.x + blockIdx.x * blockDim.x; tid < N; tid += stride)
a[tid] = target;
}
int main()
{
int *a, *b, *c;
int size = N*sizeof(int); // The total number of bytes per vector
hipMallocManaged(&a, size);
hipMallocManaged(&b, size);
hipMallocManaged(&c, size);
int deviceId;
hipDeviceProp_t props;
hipGetDevice(&deviceId);
hipGetDeviceProperties(&props, deviceId);
int multiProcessorCount = props.multiProcessorCount;
size_t threadsPerBlock = 1024;
size_t numberOfBlocks = ((N>>10)/multiProcessorCount+1)*multiProcessorCount;
// i first prefetch pages...
hipMemPrefetchAsync(a, size, deviceId);
hipMemPrefetchAsync(b, size, deviceId);
init_array<<<numberOfBlocks, threadsPerBlock>>>(a,2,threadsPerBlock*numberOfBlocks);
init_array<<<numberOfBlocks, threadsPerBlock>>>(b,1,threadsPerBlock*numberOfBlocks);
// we have no need to initialize array c, because of default value is 0.
//init_array<<<numberOfBlocks, threadsPerBlock>>>(c,0,threadsPerBlock*numberOfBlocks);
hipDeviceSynchronize();
//printf("sm numer = %d\n", multiProcessorCount);
hipMemPrefetchAsync(c, size, deviceId);
//saxpy <<<numberOfBlocks, threadsPerBlock>>>(a,b,c,threadsPerBlock*numberOfBlocks);
int len = 40;
dim3 threads_per_block(32, 32, 1);
dim3 number_of_blocks(len, len, 1);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 0);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 1600*1024);
saxpy<<<number_of_blocks, threads_per_block>>>(a, b, c, 3200*1024);
hipDeviceSynchronize();
hipMemPrefetchAsync(c, size, hipCpuDeviceId);
// Print out the first and last 5 values of c for a quality check
for( int i = 0; i < 5; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
for( int i = N-5; i < N; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
hipFree(a);
hipFree(b);
hipFree(c);
} | .text
.file "01-saxpy.hip"
.globl _Z20__device_stub__saxpyPiS_S_i # -- Begin function _Z20__device_stub__saxpyPiS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPiS_S_i,@function
_Z20__device_stub__saxpyPiS_S_i: # @_Z20__device_stub__saxpyPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyPiS_S_i, .Lfunc_end0-_Z20__device_stub__saxpyPiS_S_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__init_arrayPiii # -- Begin function _Z25__device_stub__init_arrayPiii
.p2align 4, 0x90
.type _Z25__device_stub__init_arrayPiii,@function
_Z25__device_stub__init_arrayPiii: # @_Z25__device_stub__init_arrayPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10init_arrayPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__init_arrayPiii, .Lfunc_end1-_Z25__device_stub__init_arrayPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1616, %rsp # imm = 0x650
.cfi_def_cfa_offset 1648
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294968320, %rbx # imm = 0x100000400
leaq 104(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
leaq 96(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
leaq 88(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
leaq 84(%rsp), %rdi
callq hipGetDevice
movl 84(%rsp), %esi
leaq 144(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl 532(%rsp), %ecx
movl $4096, %eax # imm = 0x1000
xorl %edx, %edx
idivl %ecx
movl %eax, %r14d
incl %r14d
imull %ecx, %r14d
movq 104(%rsp), %rdi
movl 84(%rsp), %edx
movl $16777216, %esi # imm = 0x1000000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 96(%rsp), %rdi
movl 84(%rsp), %edx
movl $16777216, %esi # imm = 0x1000000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
leaq (%r14,%rbx), %r15
addq $-1024, %r15 # imm = 0xFC00
movq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 104(%rsp), %rax
movl %r14d, %ecx
shll $10, %ecx
movq %rax, 72(%rsp)
movl $2, 16(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10init_arrayPiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 96(%rsp), %rax
shll $10, %r14d
movq %rax, 72(%rsp)
movl $1, 16(%rsp)
movl %r14d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10init_arrayPiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movabsq $171798691880, %r14 # imm = 0x2800000028
movabsq $137438953504, %rbx # imm = 0x2000000020
callq hipDeviceSynchronize
movq 88(%rsp), %rdi
movl 84(%rsp), %edx
movl $16777216, %esi # imm = 0x1000000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5saxpyPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $1638400, 4(%rsp) # imm = 0x190000
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5saxpyPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $3276800, 4(%rsp) # imm = 0x320000
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5saxpyPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
callq hipDeviceSynchronize
movq 88(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $-1, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movq 88(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB2_11
# %bb.12:
movl $10, %edi
callq putchar@PLT
movl $4194299, %ebx # imm = 0x3FFFFB
.p2align 4, 0x90
.LBB2_13: # =>This Inner Loop Header: Depth=1
movq 88(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4194304, %rbx # imm = 0x400000
jne .LBB2_13
# %bb.14:
movl $10, %edi
callq putchar@PLT
movq 104(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1616, %rsp # imm = 0x650
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10init_arrayPiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyPiS_S_i,@object # @_Z5saxpyPiS_S_i
.section .rodata,"a",@progbits
.globl _Z5saxpyPiS_S_i
.p2align 3, 0x0
_Z5saxpyPiS_S_i:
.quad _Z20__device_stub__saxpyPiS_S_i
.size _Z5saxpyPiS_S_i, 8
.type _Z10init_arrayPiii,@object # @_Z10init_arrayPiii
.globl _Z10init_arrayPiii
.p2align 3, 0x0
_Z10init_arrayPiii:
.quad _Z25__device_stub__init_arrayPiii
.size _Z10init_arrayPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c[%d] = %d, "
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyPiS_S_i"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10init_arrayPiii"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyPiS_S_i
.addrsig_sym _Z25__device_stub__init_arrayPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyPiS_S_i
.addrsig_sym _Z10init_arrayPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10init_arrayPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x3fffff, PT ; /* 0x003fffff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ I2F.U32.RP R4, c[0x0][0x16c] ; /* 0x00005b0000047b06 */
/* 0x000e220000209000 */
/*0070*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0080*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fe20003f45070 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ BSSY B0, 0x2a0 ; /* 0x000001f000007945 */
/* 0x000fe80003800000 */
/*00b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00c0*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*00e0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x001fc800078e0a03 */
/*00f0*/ IMAD R5, R5, c[0x0][0x16c], RZ ; /* 0x00005b0005057a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R5, R3, R5, R2 ; /* 0x0000000503057227 */
/* 0x000fe200078e0002 */
/*0110*/ IADD3 R2, -R0, 0x3fffff, RZ ; /* 0x003fffff00027810 */
/* 0x000fca0007ffe1ff */
/*0120*/ IMAD.HI.U32 R5, R5, R2, RZ ; /* 0x0000000205057227 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a05 */
/*0140*/ IMAD R2, R7, c[0x0][0x16c], R2 ; /* 0x00005b0007027a24 */
/* 0x000fca00078e0202 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06070 */
/*0160*/ @P0 IADD3 R2, R2, -c[0x0][0x16c], RZ ; /* 0x80005b0002020a10 */
/* 0x000fe40007ffe0ff */
/*0170*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x16c], PT ; /* 0x00005b0002007a0c */
/* 0x000fda0003f26070 */
/*0190*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff05aa12 */
/* 0x000fc800078e33ff */
/*01b0*/ IADD3 R2, R5.reuse, 0x1, RZ ; /* 0x0000000105027810 */
/* 0x040fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f26070 */
/*01d0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*01e0*/ @!P0 BRA 0x290 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0200*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff077624 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*0230*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0240*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101904 */
/*0250*/ IADD3 R0, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a10 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0270*/ IMAD.WIDE R2, R5, c[0x0][0x16c], R2 ; /* 0x00005b0005027a25 */
/* 0x001fd800078e0202 */
/*0280*/ @P0 BRA 0x230 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*02c0*/ MOV R13, c[0x0][0x168] ; /* 0x00005a00000d7a02 */
/* 0x000fc60000000f00 */
/*02d0*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fe200078e020b */
/*02e0*/ MOV R17, c[0x0][0x16c] ; /* 0x00005b0000117a02 */
/* 0x000fc60000000f00 */
/*02f0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0f7624 */
/* 0x000fe200078e00ff */
/*0300*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e2000c101904 */
/*0310*/ IMAD.WIDE R4, R11, c[0x0][0x16c], R2 ; /* 0x00005b000b047a25 */
/* 0x000fc800078e0202 */
/*0320*/ IMAD R0, R15, 0x2, R0 ; /* 0x000000020f007824 */
/* 0x000fe200078e0200 */
/*0330*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0001e2000c101904 */
/*0340*/ IMAD.WIDE R6, R11, c[0x0][0x16c], R4 ; /* 0x00005b000b067a25 */
/* 0x000fc600078e0204 */
/*0350*/ LEA R0, R17, R0, 0x1 ; /* 0x0000000011007211 */
/* 0x000fe400078e08ff */
/*0360*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e2000c101904 */
/*0370*/ IMAD.WIDE R8, R11, c[0x0][0x16c], R6 ; /* 0x00005b000b087a25 */
/* 0x000fe200078e0206 */
/*0380*/ ISETP.GE.AND P0, PT, R0, 0x400000, PT ; /* 0x004000000000780c */
/* 0x000fc80003f06270 */
/*0390*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x0001f2000c101904 */
/*03a0*/ @!P0 BRA 0x2d0 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ BRA 0x3c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5saxpyPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000ea20000002500 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe200078e0203 */
/*0060*/ IADD3 R3, R2, c[0x0][0x178], RZ ; /* 0x00005e0002037a10 */
/* 0x002fc60007ffe0ff */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x004fc800078e0205 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x000fca00078e0203 */
/*0090*/ ISETP.GT.AND P0, PT, R0, 0x3fffff, PT ; /* 0x003fffff0000780c */
/* 0x000fda0003f04270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*0120*/ LEA R9, R2, R5, 0x1 ; /* 0x0000000502097211 */
/* 0x004fca00078e08ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyPiS_S_i
.globl _Z5saxpyPiS_S_i
.p2align 8
.type _Z5saxpyPiS_S_i,@function
_Z5saxpyPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b32 s4, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_mul_lo_u32 v1, v3, s2
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v0, s4, v1
v_cmpx_gt_i32_e32 0x400000, v0
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_lshl_add_u32 v2, v2, 1, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyPiS_S_i, .Lfunc_end0-_Z5saxpyPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10init_arrayPiii
.globl _Z10init_arrayPiii
.p2align 8
.type _Z10init_arrayPiii,@function
_Z10init_arrayPiii:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x400000, v1
s_cbranch_execz .LBB1_3
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_mov_b32_e32 v0, s2
s_ashr_i32 s5, s3, 31
s_mov_b32 s4, s3
s_mov_b32 s1, 0
s_lshl_b64 s[4:5], s[4:5], 2
.LBB1_2:
v_add_nc_u32_e32 v1, s3, v1
global_store_b32 v[2:3], v0, off
v_add_co_u32 v2, s0, v2, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
v_cmp_lt_i32_e32 vcc_lo, 0x3fffff, v1
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10init_arrayPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10init_arrayPiii, .Lfunc_end1-_Z10init_arrayPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10init_arrayPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10init_arrayPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00017d84_00000000-6_01-saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i
.type _Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i, @function
_Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i, .-_Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i
.globl _Z5saxpyPiS_S_i
.type _Z5saxpyPiS_S_i, @function
_Z5saxpyPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5saxpyPiS_S_i, .-_Z5saxpyPiS_S_i
.globl _Z32__device_stub__Z10init_arrayPiiiPiii
.type _Z32__device_stub__Z10init_arrayPiiiPiii, @function
_Z32__device_stub__Z10init_arrayPiiiPiii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10init_arrayPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z32__device_stub__Z10init_arrayPiiiPiii, .-_Z32__device_stub__Z10init_arrayPiiiPiii
.globl _Z10init_arrayPiii
.type _Z10init_arrayPiii, @function
_Z10init_arrayPiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10init_arrayPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10init_arrayPiii, .-_Z10init_arrayPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "c[%d] = %d, "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1104, %rsp
.cfi_def_cfa_offset 1136
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 64(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
movl 452(%rsp), %ebp
movl $0, %ecx
movl 12(%rsp), %edx
movl $16777216, %esi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ecx
movl 12(%rsp), %edx
movl $16777216, %esi
movq 24(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $1024, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $4096, %eax
movl $0, %edx
idivl %ebp
leal 1(%rax), %ebx
imull %ebp, %ebx
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L20:
movl $1024, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L21:
call cudaDeviceSynchronize@PLT
movl $0, %ecx
movl 12(%rsp), %edx
movl $16777216, %esi
movq 32(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $32, 40(%rsp)
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $40, 52(%rsp)
movl $40, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L22:
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L23:
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L24:
call cudaDeviceSynchronize@PLT
movl $0, %ecx
movl $-1, %edx
movl $16777216, %esi
movq 32(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L25:
movq 32(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L25
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16777196, %ebp
movl $4194299, %ebx
leaq .LC0(%rip), %r12
.L26:
movq 32(%rsp), %rax
movl (%rax,%rbp), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
addq $4, %rbp
cmpl $4194304, %ebx
jne .L26
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $1104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl %ebx, %edx
sall $10, %edx
movl $2, %esi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z10init_arrayPiiiPiii
jmp .L20
.L32:
movl %ebx, %edx
sall $10, %edx
movl $1, %esi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z10init_arrayPiiiPiii
jmp .L21
.L33:
movl $0, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i
jmp .L22
.L34:
movl $1638400, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i
jmp .L23
.L35:
movl $3276800, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z5saxpyPiS_S_iPiS_S_i
jmp .L24
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10init_arrayPiii"
.LC3:
.string "_Z5saxpyPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10init_arrayPiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "01-saxpy.hip"
.globl _Z20__device_stub__saxpyPiS_S_i # -- Begin function _Z20__device_stub__saxpyPiS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPiS_S_i,@function
_Z20__device_stub__saxpyPiS_S_i: # @_Z20__device_stub__saxpyPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyPiS_S_i, .Lfunc_end0-_Z20__device_stub__saxpyPiS_S_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__init_arrayPiii # -- Begin function _Z25__device_stub__init_arrayPiii
.p2align 4, 0x90
.type _Z25__device_stub__init_arrayPiii,@function
_Z25__device_stub__init_arrayPiii: # @_Z25__device_stub__init_arrayPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10init_arrayPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__init_arrayPiii, .Lfunc_end1-_Z25__device_stub__init_arrayPiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1616, %rsp # imm = 0x650
.cfi_def_cfa_offset 1648
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294968320, %rbx # imm = 0x100000400
leaq 104(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
leaq 96(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
leaq 88(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
leaq 84(%rsp), %rdi
callq hipGetDevice
movl 84(%rsp), %esi
leaq 144(%rsp), %rdi
callq hipGetDevicePropertiesR0600
movl 532(%rsp), %ecx
movl $4096, %eax # imm = 0x1000
xorl %edx, %edx
idivl %ecx
movl %eax, %r14d
incl %r14d
imull %ecx, %r14d
movq 104(%rsp), %rdi
movl 84(%rsp), %edx
movl $16777216, %esi # imm = 0x1000000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq 96(%rsp), %rdi
movl 84(%rsp), %edx
movl $16777216, %esi # imm = 0x1000000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
leaq (%r14,%rbx), %r15
addq $-1024, %r15 # imm = 0xFC00
movq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 104(%rsp), %rax
movl %r14d, %ecx
shll $10, %ecx
movq %rax, 72(%rsp)
movl $2, 16(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10init_arrayPiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 96(%rsp), %rax
shll $10, %r14d
movq %rax, 72(%rsp)
movl $1, 16(%rsp)
movl %r14d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10init_arrayPiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movabsq $171798691880, %r14 # imm = 0x2800000028
movabsq $137438953504, %rbx # imm = 0x2000000020
callq hipDeviceSynchronize
movq 88(%rsp), %rdi
movl 84(%rsp), %edx
movl $16777216, %esi # imm = 0x1000000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5saxpyPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $1638400, 4(%rsp) # imm = 0x190000
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5saxpyPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl $3276800, 4(%rsp) # imm = 0x320000
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5saxpyPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
callq hipDeviceSynchronize
movq 88(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $-1, %edx
xorl %ecx, %ecx
callq hipMemPrefetchAsync
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movq 88(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB2_11
# %bb.12:
movl $10, %edi
callq putchar@PLT
movl $4194299, %ebx # imm = 0x3FFFFB
.p2align 4, 0x90
.LBB2_13: # =>This Inner Loop Header: Depth=1
movq 88(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4194304, %rbx # imm = 0x400000
jne .LBB2_13
# %bb.14:
movl $10, %edi
callq putchar@PLT
movq 104(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1616, %rsp # imm = 0x650
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10init_arrayPiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyPiS_S_i,@object # @_Z5saxpyPiS_S_i
.section .rodata,"a",@progbits
.globl _Z5saxpyPiS_S_i
.p2align 3, 0x0
_Z5saxpyPiS_S_i:
.quad _Z20__device_stub__saxpyPiS_S_i
.size _Z5saxpyPiS_S_i, 8
.type _Z10init_arrayPiii,@object # @_Z10init_arrayPiii
.globl _Z10init_arrayPiii
.p2align 3, 0x0
_Z10init_arrayPiii:
.quad _Z25__device_stub__init_arrayPiii
.size _Z10init_arrayPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c[%d] = %d, "
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyPiS_S_i"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10init_arrayPiii"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyPiS_S_i
.addrsig_sym _Z25__device_stub__init_arrayPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyPiS_S_i
.addrsig_sym _Z10init_arrayPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* This program uses the host CURAND API.
* I copied most of it from cuRAND
* documentation.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand.h>
#include <math.h>
#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CURAND_CALL(x) do { if((x)!=CURAND_STATUS_SUCCESS) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void float_to_int(int * devInts, float * devData)
{
int x_glob;
int y_glob;
int x_total_dim = blockDim.x * gridDim.x;
//int y_total_dim = blockDim.y * gridDim.y;
int location;
x_glob = blockDim.x * blockIdx.x + threadIdx.x;
y_glob = blockDim.y * blockIdx.y + threadIdx.y;
location = y_glob * x_total_dim + x_glob;
devInts[location] = (int) floor(devData[location] * 10);
}
__global__ void simple_histo(int * devInts, int * devHistogram)
{
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int myItem = devInts[myId];
int myBin = myItem;
atomicAdd(&(devHistogram[myBin]), 1);
}
int main(int argc, char *argv[])
{
int nx = 1024;
int ny = 1024;
//int n_threads = 10;
int n = nx * ny;
int i;
curandGenerator_t gen;
float *devData;
//float *hostData;
int *histogram;
int *devInts;
//int *hostInts;
int *devHistogram;
/* Allocate n floats on host */
// hostData = (float *)calloc(n, sizeof(float));
//hostInts = (int *)calloc(n, sizeof(int));
histogram = (int *)calloc(10, sizeof(int));
/* Allocate n floats on device */
CUDA_CALL(cudaMalloc((void **)&devData, n*sizeof(float)));
CUDA_CALL(cudaMalloc((void **)&devInts, n*sizeof(int)));
CUDA_CALL(cudaMalloc((void **)&devHistogram, 10*sizeof(int)));
/* Create pseudo-random number generator */
CURAND_CALL(curandCreateGenerator(&gen,
CURAND_RNG_PSEUDO_DEFAULT));
/* Set seed */
CURAND_CALL(curandSetPseudoRandomGeneratorSeed(gen,
1234ULL));
/* Generate n floats on device */
CURAND_CALL(curandGenerateUniform(gen, devData, n));
/* Turn them into random integers */
float_to_int<<<dim3(32,32), dim3(nx/32,ny/32)>>>(devInts, devData);
/* Make a simple histogram */
simple_histo<<<dim3(1024), dim3(n / 1024)>>>(devInts, devHistogram);
/* Copy device memory to host */
// CUDA_CALL(cudaMemcpy(hostData, devData, n * sizeof(float),
// cudaMemcpyDeviceToHost));
// CUDA_CALL(cudaMemcpy(hostInts, devInts, n * sizeof(int),
// cudaMemcpyDeviceToHost));
CUDA_CALL(cudaMemcpy(histogram, devHistogram, 10 * sizeof(int),
cudaMemcpyDeviceToHost));
/* Show result */
// for(i = 0; i < n; i++) {
// printf("%1.4f ", hostData[i]);
// }
// printf("\n");
//
// for(i = 0; i < n; i++) {
// printf("%d ", hostInts[i]);
// }
// printf("\n");
for(i = 0; i<10; i++)
{
printf("%d ", histogram[i]);
}
printf("\n");
/* Cleanup */
CURAND_CALL(curandDestroyGenerator(gen));
CUDA_CALL(cudaFree(devData));
CUDA_CALL(cudaFree(devInts));
CUDA_CALL(cudaFree(devHistogram));
free(histogram);
//free(hostData);
//free(hostInts);
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z12simple_histoPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*0090*/ IMAD.WIDE R4, R2, R5, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x004fcc00078e0205 */
/*00a0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x000fe2000c10e184 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12float_to_intPiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002200 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000ea20000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R7 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0207 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0203 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0205 */
/*00a0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0209 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0209 */
/*00d0*/ FMUL R6, R2, 10 ; /* 0x4120000002067820 */
/* 0x004fc80000400000 */
/*00e0*/ F2I.FLOOR.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000e240000207100 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* This program uses the host CURAND API.
* I copied most of it from cuRAND
* documentation.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand.h>
#include <math.h>
#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CURAND_CALL(x) do { if((x)!=CURAND_STATUS_SUCCESS) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void float_to_int(int * devInts, float * devData)
{
int x_glob;
int y_glob;
int x_total_dim = blockDim.x * gridDim.x;
//int y_total_dim = blockDim.y * gridDim.y;
int location;
x_glob = blockDim.x * blockIdx.x + threadIdx.x;
y_glob = blockDim.y * blockIdx.y + threadIdx.y;
location = y_glob * x_total_dim + x_glob;
devInts[location] = (int) floor(devData[location] * 10);
}
__global__ void simple_histo(int * devInts, int * devHistogram)
{
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int myItem = devInts[myId];
int myBin = myItem;
atomicAdd(&(devHistogram[myBin]), 1);
}
int main(int argc, char *argv[])
{
int nx = 1024;
int ny = 1024;
//int n_threads = 10;
int n = nx * ny;
int i;
curandGenerator_t gen;
float *devData;
//float *hostData;
int *histogram;
int *devInts;
//int *hostInts;
int *devHistogram;
/* Allocate n floats on host */
// hostData = (float *)calloc(n, sizeof(float));
//hostInts = (int *)calloc(n, sizeof(int));
histogram = (int *)calloc(10, sizeof(int));
/* Allocate n floats on device */
CUDA_CALL(cudaMalloc((void **)&devData, n*sizeof(float)));
CUDA_CALL(cudaMalloc((void **)&devInts, n*sizeof(int)));
CUDA_CALL(cudaMalloc((void **)&devHistogram, 10*sizeof(int)));
/* Create pseudo-random number generator */
CURAND_CALL(curandCreateGenerator(&gen,
CURAND_RNG_PSEUDO_DEFAULT));
/* Set seed */
CURAND_CALL(curandSetPseudoRandomGeneratorSeed(gen,
1234ULL));
/* Generate n floats on device */
CURAND_CALL(curandGenerateUniform(gen, devData, n));
/* Turn them into random integers */
float_to_int<<<dim3(32,32), dim3(nx/32,ny/32)>>>(devInts, devData);
/* Make a simple histogram */
simple_histo<<<dim3(1024), dim3(n / 1024)>>>(devInts, devHistogram);
/* Copy device memory to host */
// CUDA_CALL(cudaMemcpy(hostData, devData, n * sizeof(float),
// cudaMemcpyDeviceToHost));
// CUDA_CALL(cudaMemcpy(hostInts, devInts, n * sizeof(int),
// cudaMemcpyDeviceToHost));
CUDA_CALL(cudaMemcpy(histogram, devHistogram, 10 * sizeof(int),
cudaMemcpyDeviceToHost));
/* Show result */
// for(i = 0; i < n; i++) {
// printf("%1.4f ", hostData[i]);
// }
// printf("\n");
//
// for(i = 0; i < n; i++) {
// printf("%d ", hostInts[i]);
// }
// printf("\n");
for(i = 0; i<10; i++)
{
printf("%d ", histogram[i]);
}
printf("\n");
/* Cleanup */
CURAND_CALL(curandDestroyGenerator(gen));
CUDA_CALL(cudaFree(devData));
CUDA_CALL(cudaFree(devInts));
CUDA_CALL(cudaFree(devHistogram));
free(histogram);
//free(hostData);
//free(hostInts);
return EXIT_SUCCESS;
} | .file "tmpxft_000e771e_00000000-6_histogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12float_to_intPiPfPiPf
.type _Z34__device_stub__Z12float_to_intPiPfPiPf, @function
_Z34__device_stub__Z12float_to_intPiPfPiPf:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12float_to_intPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z12float_to_intPiPfPiPf, .-_Z34__device_stub__Z12float_to_intPiPfPiPf
.globl _Z12float_to_intPiPf
.type _Z12float_to_intPiPf, @function
_Z12float_to_intPiPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12float_to_intPiPfPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12float_to_intPiPf, .-_Z12float_to_intPiPf
.globl _Z34__device_stub__Z12simple_histoPiS_PiS_
.type _Z34__device_stub__Z12simple_histoPiS_PiS_, @function
_Z34__device_stub__Z12simple_histoPiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12simple_histoPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z12simple_histoPiS_PiS_, .-_Z34__device_stub__Z12simple_histoPiS_PiS_
.globl _Z12simple_histoPiS_
.type _Z12simple_histoPiS_, @function
_Z12simple_histoPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12simple_histoPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12simple_histoPiS_, .-_Z12simple_histoPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/aleksey-uvarov/hpc-2019/master/histogram.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Error at %s:%d\n"
.LC2:
.string "%d "
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $10, %edi
call calloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L39
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L40
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
movq %rsp, %rdi
movl $100, %esi
call curandCreateGenerator@PLT
testl %eax, %eax
jne .L42
movl $1234, %esi
movq (%rsp), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
testl %eax, %eax
jne .L43
movl $1048576, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call curandGenerateUniform@PLT
testl %eax, %eax
jne .L44
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $1, 52(%rsp)
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L27:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L28:
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %r12
testl %eax, %eax
jne .L47
.L29:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L29
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call curandDestroyGenerator@PLT
testl %eax, %eax
jne .L48
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L49
movq 16(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L50
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L51
movq %rbp, %rdi
call free@PLT
movl $0, %eax
jmp .L19
.L39:
movl $67, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L19:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L52
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movl $69, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L41:
movl $70, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L42:
movl $75, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L43:
movl $79, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L44:
movl $83, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L45:
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z12float_to_intPiPfPiPf
jmp .L27
.L46:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z12simple_histoPiS_PiS_
jmp .L28
.L47:
movl $101, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L48:
movl $123, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L49:
movl $124, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L50:
movl $125, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L51:
movl $126, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z12simple_histoPiS_"
.LC5:
.string "_Z12float_to_intPiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12simple_histoPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12float_to_intPiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* This program uses the host CURAND API.
* I copied most of it from cuRAND
* documentation.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand.h>
#include <math.h>
#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CURAND_CALL(x) do { if((x)!=CURAND_STATUS_SUCCESS) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void float_to_int(int * devInts, float * devData)
{
int x_glob;
int y_glob;
int x_total_dim = blockDim.x * gridDim.x;
//int y_total_dim = blockDim.y * gridDim.y;
int location;
x_glob = blockDim.x * blockIdx.x + threadIdx.x;
y_glob = blockDim.y * blockIdx.y + threadIdx.y;
location = y_glob * x_total_dim + x_glob;
devInts[location] = (int) floor(devData[location] * 10);
}
__global__ void simple_histo(int * devInts, int * devHistogram)
{
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int myItem = devInts[myId];
int myBin = myItem;
atomicAdd(&(devHistogram[myBin]), 1);
}
int main(int argc, char *argv[])
{
int nx = 1024;
int ny = 1024;
//int n_threads = 10;
int n = nx * ny;
int i;
curandGenerator_t gen;
float *devData;
//float *hostData;
int *histogram;
int *devInts;
//int *hostInts;
int *devHistogram;
/* Allocate n floats on host */
// hostData = (float *)calloc(n, sizeof(float));
//hostInts = (int *)calloc(n, sizeof(int));
histogram = (int *)calloc(10, sizeof(int));
/* Allocate n floats on device */
CUDA_CALL(cudaMalloc((void **)&devData, n*sizeof(float)));
CUDA_CALL(cudaMalloc((void **)&devInts, n*sizeof(int)));
CUDA_CALL(cudaMalloc((void **)&devHistogram, 10*sizeof(int)));
/* Create pseudo-random number generator */
CURAND_CALL(curandCreateGenerator(&gen,
CURAND_RNG_PSEUDO_DEFAULT));
/* Set seed */
CURAND_CALL(curandSetPseudoRandomGeneratorSeed(gen,
1234ULL));
/* Generate n floats on device */
CURAND_CALL(curandGenerateUniform(gen, devData, n));
/* Turn them into random integers */
float_to_int<<<dim3(32,32), dim3(nx/32,ny/32)>>>(devInts, devData);
/* Make a simple histogram */
simple_histo<<<dim3(1024), dim3(n / 1024)>>>(devInts, devHistogram);
/* Copy device memory to host */
// CUDA_CALL(cudaMemcpy(hostData, devData, n * sizeof(float),
// cudaMemcpyDeviceToHost));
// CUDA_CALL(cudaMemcpy(hostInts, devInts, n * sizeof(int),
// cudaMemcpyDeviceToHost));
CUDA_CALL(cudaMemcpy(histogram, devHistogram, 10 * sizeof(int),
cudaMemcpyDeviceToHost));
/* Show result */
// for(i = 0; i < n; i++) {
// printf("%1.4f ", hostData[i]);
// }
// printf("\n");
//
// for(i = 0; i < n; i++) {
// printf("%d ", hostInts[i]);
// }
// printf("\n");
for(i = 0; i<10; i++)
{
printf("%d ", histogram[i]);
}
printf("\n");
/* Cleanup */
CURAND_CALL(curandDestroyGenerator(gen));
CUDA_CALL(cudaFree(devData));
CUDA_CALL(cudaFree(devInts));
CUDA_CALL(cudaFree(devHistogram));
free(histogram);
//free(hostData);
//free(hostInts);
return EXIT_SUCCESS;
} | /*
* This program uses the host CURAND API.
* I copied most of it from cuRAND
* documentation.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <math.h>
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CURAND_CALL(x) do { if((x)!=HIPRAND_STATUS_SUCCESS) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void float_to_int(int * devInts, float * devData)
{
int x_glob;
int y_glob;
int x_total_dim = blockDim.x * gridDim.x;
//int y_total_dim = blockDim.y * gridDim.y;
int location;
x_glob = blockDim.x * blockIdx.x + threadIdx.x;
y_glob = blockDim.y * blockIdx.y + threadIdx.y;
location = y_glob * x_total_dim + x_glob;
devInts[location] = (int) floor(devData[location] * 10);
}
__global__ void simple_histo(int * devInts, int * devHistogram)
{
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int myItem = devInts[myId];
int myBin = myItem;
atomicAdd(&(devHistogram[myBin]), 1);
}
int main(int argc, char *argv[])
{
int nx = 1024;
int ny = 1024;
//int n_threads = 10;
int n = nx * ny;
int i;
hiprandGenerator_t gen;
float *devData;
//float *hostData;
int *histogram;
int *devInts;
//int *hostInts;
int *devHistogram;
/* Allocate n floats on host */
// hostData = (float *)calloc(n, sizeof(float));
//hostInts = (int *)calloc(n, sizeof(int));
histogram = (int *)calloc(10, sizeof(int));
/* Allocate n floats on device */
CUDA_CALL(hipMalloc((void **)&devData, n*sizeof(float)));
CUDA_CALL(hipMalloc((void **)&devInts, n*sizeof(int)));
CUDA_CALL(hipMalloc((void **)&devHistogram, 10*sizeof(int)));
/* Create pseudo-random number generator */
CURAND_CALL(hiprandCreateGenerator(&gen,
HIPRAND_RNG_PSEUDO_DEFAULT));
/* Set seed */
CURAND_CALL(hiprandSetPseudoRandomGeneratorSeed(gen,
1234ULL));
/* Generate n floats on device */
CURAND_CALL(hiprandGenerateUniform(gen, devData, n));
/* Turn them into random integers */
float_to_int<<<dim3(32,32), dim3(nx/32,ny/32)>>>(devInts, devData);
/* Make a simple histogram */
simple_histo<<<dim3(1024), dim3(n / 1024)>>>(devInts, devHistogram);
/* Copy device memory to host */
// CUDA_CALL(cudaMemcpy(hostData, devData, n * sizeof(float),
// cudaMemcpyDeviceToHost));
// CUDA_CALL(cudaMemcpy(hostInts, devInts, n * sizeof(int),
// cudaMemcpyDeviceToHost));
CUDA_CALL(hipMemcpy(histogram, devHistogram, 10 * sizeof(int),
hipMemcpyDeviceToHost));
/* Show result */
// for(i = 0; i < n; i++) {
// printf("%1.4f ", hostData[i]);
// }
// printf("\n");
//
// for(i = 0; i < n; i++) {
// printf("%d ", hostInts[i]);
// }
// printf("\n");
for(i = 0; i<10; i++)
{
printf("%d ", histogram[i]);
}
printf("\n");
/* Cleanup */
CURAND_CALL(hiprandDestroyGenerator(gen));
CUDA_CALL(hipFree(devData));
CUDA_CALL(hipFree(devInts));
CUDA_CALL(hipFree(devHistogram));
free(histogram);
//free(hostData);
//free(hostInts);
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* This program uses the host CURAND API.
* I copied most of it from cuRAND
* documentation.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <math.h>
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CURAND_CALL(x) do { if((x)!=HIPRAND_STATUS_SUCCESS) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void float_to_int(int * devInts, float * devData)
{
int x_glob;
int y_glob;
int x_total_dim = blockDim.x * gridDim.x;
//int y_total_dim = blockDim.y * gridDim.y;
int location;
x_glob = blockDim.x * blockIdx.x + threadIdx.x;
y_glob = blockDim.y * blockIdx.y + threadIdx.y;
location = y_glob * x_total_dim + x_glob;
devInts[location] = (int) floor(devData[location] * 10);
}
__global__ void simple_histo(int * devInts, int * devHistogram)
{
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int myItem = devInts[myId];
int myBin = myItem;
atomicAdd(&(devHistogram[myBin]), 1);
}
int main(int argc, char *argv[])
{
int nx = 1024;
int ny = 1024;
//int n_threads = 10;
int n = nx * ny;
int i;
hiprandGenerator_t gen;
float *devData;
//float *hostData;
int *histogram;
int *devInts;
//int *hostInts;
int *devHistogram;
/* Allocate n floats on host */
// hostData = (float *)calloc(n, sizeof(float));
//hostInts = (int *)calloc(n, sizeof(int));
histogram = (int *)calloc(10, sizeof(int));
/* Allocate n floats on device */
CUDA_CALL(hipMalloc((void **)&devData, n*sizeof(float)));
CUDA_CALL(hipMalloc((void **)&devInts, n*sizeof(int)));
CUDA_CALL(hipMalloc((void **)&devHistogram, 10*sizeof(int)));
/* Create pseudo-random number generator */
CURAND_CALL(hiprandCreateGenerator(&gen,
HIPRAND_RNG_PSEUDO_DEFAULT));
/* Set seed */
CURAND_CALL(hiprandSetPseudoRandomGeneratorSeed(gen,
1234ULL));
/* Generate n floats on device */
CURAND_CALL(hiprandGenerateUniform(gen, devData, n));
/* Turn them into random integers */
float_to_int<<<dim3(32,32), dim3(nx/32,ny/32)>>>(devInts, devData);
/* Make a simple histogram */
simple_histo<<<dim3(1024), dim3(n / 1024)>>>(devInts, devHistogram);
/* Copy device memory to host */
// CUDA_CALL(cudaMemcpy(hostData, devData, n * sizeof(float),
// cudaMemcpyDeviceToHost));
// CUDA_CALL(cudaMemcpy(hostInts, devInts, n * sizeof(int),
// cudaMemcpyDeviceToHost));
CUDA_CALL(hipMemcpy(histogram, devHistogram, 10 * sizeof(int),
hipMemcpyDeviceToHost));
/* Show result */
// for(i = 0; i < n; i++) {
// printf("%1.4f ", hostData[i]);
// }
// printf("\n");
//
// for(i = 0; i < n; i++) {
// printf("%d ", hostInts[i]);
// }
// printf("\n");
for(i = 0; i<10; i++)
{
printf("%d ", histogram[i]);
}
printf("\n");
/* Cleanup */
CURAND_CALL(hiprandDestroyGenerator(gen));
CUDA_CALL(hipFree(devData));
CUDA_CALL(hipFree(devInts));
CUDA_CALL(hipFree(devHistogram));
free(histogram);
//free(hostData);
//free(hostInts);
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12float_to_intPiPf
.globl _Z12float_to_intPiPf
.p2align 8
.type _Z12float_to_intPiPf,@function
_Z12float_to_intPiPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s2, s[14:15]
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, v3, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, 0x41200000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v2, v2
v_cvt_i32_f32_e32 v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12float_to_intPiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12float_to_intPiPf, .Lfunc_end0-_Z12float_to_intPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12simple_histoPiS_
.globl _Z12simple_histoPiS_
.p2align 8
.type _Z12simple_histoPiS_,@function
_Z12simple_histoPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12simple_histoPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12simple_histoPiS_, .Lfunc_end1-_Z12simple_histoPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12float_to_intPiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12float_to_intPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12simple_histoPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12simple_histoPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* This program uses the host CURAND API.
* I copied most of it from cuRAND
* documentation.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <math.h>
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CURAND_CALL(x) do { if((x)!=HIPRAND_STATUS_SUCCESS) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void float_to_int(int * devInts, float * devData)
{
int x_glob;
int y_glob;
int x_total_dim = blockDim.x * gridDim.x;
//int y_total_dim = blockDim.y * gridDim.y;
int location;
x_glob = blockDim.x * blockIdx.x + threadIdx.x;
y_glob = blockDim.y * blockIdx.y + threadIdx.y;
location = y_glob * x_total_dim + x_glob;
devInts[location] = (int) floor(devData[location] * 10);
}
__global__ void simple_histo(int * devInts, int * devHistogram)
{
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int myItem = devInts[myId];
int myBin = myItem;
atomicAdd(&(devHistogram[myBin]), 1);
}
int main(int argc, char *argv[])
{
int nx = 1024;
int ny = 1024;
//int n_threads = 10;
int n = nx * ny;
int i;
hiprandGenerator_t gen;
float *devData;
//float *hostData;
int *histogram;
int *devInts;
//int *hostInts;
int *devHistogram;
/* Allocate n floats on host */
// hostData = (float *)calloc(n, sizeof(float));
//hostInts = (int *)calloc(n, sizeof(int));
histogram = (int *)calloc(10, sizeof(int));
/* Allocate n floats on device */
CUDA_CALL(hipMalloc((void **)&devData, n*sizeof(float)));
CUDA_CALL(hipMalloc((void **)&devInts, n*sizeof(int)));
CUDA_CALL(hipMalloc((void **)&devHistogram, 10*sizeof(int)));
/* Create pseudo-random number generator */
CURAND_CALL(hiprandCreateGenerator(&gen,
HIPRAND_RNG_PSEUDO_DEFAULT));
/* Set seed */
CURAND_CALL(hiprandSetPseudoRandomGeneratorSeed(gen,
1234ULL));
/* Generate n floats on device */
CURAND_CALL(hiprandGenerateUniform(gen, devData, n));
/* Turn them into random integers */
float_to_int<<<dim3(32,32), dim3(nx/32,ny/32)>>>(devInts, devData);
/* Make a simple histogram */
simple_histo<<<dim3(1024), dim3(n / 1024)>>>(devInts, devHistogram);
/* Copy device memory to host */
// CUDA_CALL(cudaMemcpy(hostData, devData, n * sizeof(float),
// cudaMemcpyDeviceToHost));
// CUDA_CALL(cudaMemcpy(hostInts, devInts, n * sizeof(int),
// cudaMemcpyDeviceToHost));
CUDA_CALL(hipMemcpy(histogram, devHistogram, 10 * sizeof(int),
hipMemcpyDeviceToHost));
/* Show result */
// for(i = 0; i < n; i++) {
// printf("%1.4f ", hostData[i]);
// }
// printf("\n");
//
// for(i = 0; i < n; i++) {
// printf("%d ", hostInts[i]);
// }
// printf("\n");
for(i = 0; i<10; i++)
{
printf("%d ", histogram[i]);
}
printf("\n");
/* Cleanup */
CURAND_CALL(hiprandDestroyGenerator(gen));
CUDA_CALL(hipFree(devData));
CUDA_CALL(hipFree(devInts));
CUDA_CALL(hipFree(devHistogram));
free(histogram);
//free(hostData);
//free(hostInts);
return EXIT_SUCCESS;
} | .text
.file "histogram.hip"
.globl _Z27__device_stub__float_to_intPiPf # -- Begin function _Z27__device_stub__float_to_intPiPf
.p2align 4, 0x90
.type _Z27__device_stub__float_to_intPiPf,@function
_Z27__device_stub__float_to_intPiPf: # @_Z27__device_stub__float_to_intPiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12float_to_intPiPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__float_to_intPiPf, .Lfunc_end0-_Z27__device_stub__float_to_intPiPf
.cfi_endproc
# -- End function
.globl _Z27__device_stub__simple_histoPiS_ # -- Begin function _Z27__device_stub__simple_histoPiS_
.p2align 4, 0x90
.type _Z27__device_stub__simple_histoPiS_,@function
_Z27__device_stub__simple_histoPiS_: # @_Z27__device_stub__simple_histoPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12simple_histoPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__simple_histoPiS_, .Lfunc_end1-_Z27__device_stub__simple_histoPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $40, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $10, %edi
movl $4, %esi
callq calloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
je .LBB2_3
# %bb.1:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $67, %edx
jmp .LBB2_2
.LBB2_3:
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
je .LBB2_5
# %bb.4:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $69, %edx
jmp .LBB2_2
.LBB2_5:
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
testl %eax, %eax
je .LBB2_7
# %bb.6:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $70, %edx
jmp .LBB2_2
.LBB2_7:
leaq 32(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
testl %eax, %eax
je .LBB2_9
# %bb.8:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $76, %edx
jmp .LBB2_2
.LBB2_9:
movq 32(%rsp), %rdi
movl $1234, %esi # imm = 0x4D2
callq hiprandSetPseudoRandomGeneratorSeed
testl %eax, %eax
je .LBB2_11
# %bb.10:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $80, %edx
jmp .LBB2_2
.LBB2_11:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movl $1048576, %edx # imm = 0x100000
callq hiprandGenerateUniform
testl %eax, %eax
je .LBB2_13
# %bb.12:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $83, %edx
jmp .LBB2_2
.LBB2_13:
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 16(%rsp), %rdi
movq 24(%rsp), %rsi
callq _Z27__device_stub__float_to_intPiPf
.LBB2_15:
movabsq $4294968320, %rdi # imm = 0x100000400
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_17
# %bb.16:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
callq _Z27__device_stub__simple_histoPiS_
.LBB2_17:
movq 8(%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_18
# %bb.30:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $102, %edx
jmp .LBB2_2
.LBB2_18: # %.preheader.preheader
xorl %r14d, %r14d
.LBB2_19: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB2_19
# %bb.20:
movl $10, %edi
callq putchar@PLT
movq 32(%rsp), %rdi
callq hiprandDestroyGenerator
testl %eax, %eax
je .LBB2_22
# %bb.21:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $123, %edx
jmp .LBB2_2
.LBB2_22:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_24
# %bb.23:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $124, %edx
jmp .LBB2_2
.LBB2_24:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_26
# %bb.25:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $125, %edx
jmp .LBB2_2
.LBB2_26:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_28
# %bb.27:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $126, %edx
.LBB2_2:
xorl %eax, %eax
callq printf
movl $1, %eax
.LBB2_29:
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_28:
.cfi_def_cfa_offset 64
movq %rbx, %rdi
callq free
xorl %eax, %eax
jmp .LBB2_29
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12float_to_intPiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12simple_histoPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12float_to_intPiPf,@object # @_Z12float_to_intPiPf
.section .rodata,"a",@progbits
.globl _Z12float_to_intPiPf
.p2align 3, 0x0
_Z12float_to_intPiPf:
.quad _Z27__device_stub__float_to_intPiPf
.size _Z12float_to_intPiPf, 8
.type _Z12simple_histoPiS_,@object # @_Z12simple_histoPiS_
.globl _Z12simple_histoPiS_
.p2align 3, 0x0
_Z12simple_histoPiS_:
.quad _Z27__device_stub__simple_histoPiS_
.size _Z12simple_histoPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error at %s:%d\n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/aleksey-uvarov/hpc-2019/master/histogram.hip"
.size .L.str.1, 102
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12float_to_intPiPf"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12simple_histoPiS_"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__float_to_intPiPf
.addrsig_sym _Z27__device_stub__simple_histoPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12float_to_intPiPf
.addrsig_sym _Z12simple_histoPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12simple_histoPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*0090*/ IMAD.WIDE R4, R2, R5, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x004fcc00078e0205 */
/*00a0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x000fe2000c10e184 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12float_to_intPiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002200 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000ea20000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R7 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0207 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0203 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x004fc800078e0205 */
/*00a0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0209 */
/*00b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0209 */
/*00d0*/ FMUL R6, R2, 10 ; /* 0x4120000002067820 */
/* 0x004fc80000400000 */
/*00e0*/ F2I.FLOOR.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000e240000207100 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12float_to_intPiPf
.globl _Z12float_to_intPiPf
.p2align 8
.type _Z12float_to_intPiPf,@function
_Z12float_to_intPiPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s2, s[14:15]
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, v3, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, 0x41200000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v2, v2
v_cvt_i32_f32_e32 v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12float_to_intPiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12float_to_intPiPf, .Lfunc_end0-_Z12float_to_intPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12simple_histoPiS_
.globl _Z12simple_histoPiS_
.p2align 8
.type _Z12simple_histoPiS_,@function
_Z12simple_histoPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12simple_histoPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12simple_histoPiS_, .Lfunc_end1-_Z12simple_histoPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12float_to_intPiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12float_to_intPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12simple_histoPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12simple_histoPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e771e_00000000-6_histogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12float_to_intPiPfPiPf
.type _Z34__device_stub__Z12float_to_intPiPfPiPf, @function
_Z34__device_stub__Z12float_to_intPiPfPiPf:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12float_to_intPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z12float_to_intPiPfPiPf, .-_Z34__device_stub__Z12float_to_intPiPfPiPf
.globl _Z12float_to_intPiPf
.type _Z12float_to_intPiPf, @function
_Z12float_to_intPiPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12float_to_intPiPfPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12float_to_intPiPf, .-_Z12float_to_intPiPf
.globl _Z34__device_stub__Z12simple_histoPiS_PiS_
.type _Z34__device_stub__Z12simple_histoPiS_PiS_, @function
_Z34__device_stub__Z12simple_histoPiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12simple_histoPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z12simple_histoPiS_PiS_, .-_Z34__device_stub__Z12simple_histoPiS_PiS_
.globl _Z12simple_histoPiS_
.type _Z12simple_histoPiS_, @function
_Z12simple_histoPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12simple_histoPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12simple_histoPiS_, .-_Z12simple_histoPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/aleksey-uvarov/hpc-2019/master/histogram.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Error at %s:%d\n"
.LC2:
.string "%d "
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4, %esi
movl $10, %edi
call calloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L39
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L40
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
movq %rsp, %rdi
movl $100, %esi
call curandCreateGenerator@PLT
testl %eax, %eax
jne .L42
movl $1234, %esi
movq (%rsp), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
testl %eax, %eax
jne .L43
movl $1048576, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call curandGenerateUniform@PLT
testl %eax, %eax
jne .L44
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $1, 52(%rsp)
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L27:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L28:
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %r12
testl %eax, %eax
jne .L47
.L29:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L29
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call curandDestroyGenerator@PLT
testl %eax, %eax
jne .L48
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L49
movq 16(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L50
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L51
movq %rbp, %rdi
call free@PLT
movl $0, %eax
jmp .L19
.L39:
movl $67, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L19:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L52
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movl $69, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L41:
movl $70, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L42:
movl $75, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L43:
movl $79, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L44:
movl $83, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L45:
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z12float_to_intPiPfPiPf
jmp .L27
.L46:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z34__device_stub__Z12simple_histoPiS_PiS_
jmp .L28
.L47:
movl $101, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L48:
movl $123, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L49:
movl $124, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L50:
movl $125, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L51:
movl $126, %ecx
leaq .LC0(%rip), %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L19
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z12simple_histoPiS_"
.LC5:
.string "_Z12float_to_intPiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12simple_histoPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12float_to_intPiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "histogram.hip"
.globl _Z27__device_stub__float_to_intPiPf # -- Begin function _Z27__device_stub__float_to_intPiPf
.p2align 4, 0x90
.type _Z27__device_stub__float_to_intPiPf,@function
_Z27__device_stub__float_to_intPiPf: # @_Z27__device_stub__float_to_intPiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12float_to_intPiPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__float_to_intPiPf, .Lfunc_end0-_Z27__device_stub__float_to_intPiPf
.cfi_endproc
# -- End function
.globl _Z27__device_stub__simple_histoPiS_ # -- Begin function _Z27__device_stub__simple_histoPiS_
.p2align 4, 0x90
.type _Z27__device_stub__simple_histoPiS_,@function
_Z27__device_stub__simple_histoPiS_: # @_Z27__device_stub__simple_histoPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12simple_histoPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__simple_histoPiS_, .Lfunc_end1-_Z27__device_stub__simple_histoPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $40, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $10, %edi
movl $4, %esi
callq calloc
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
je .LBB2_3
# %bb.1:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $67, %edx
jmp .LBB2_2
.LBB2_3:
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
testl %eax, %eax
je .LBB2_5
# %bb.4:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $69, %edx
jmp .LBB2_2
.LBB2_5:
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
testl %eax, %eax
je .LBB2_7
# %bb.6:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $70, %edx
jmp .LBB2_2
.LBB2_7:
leaq 32(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
testl %eax, %eax
je .LBB2_9
# %bb.8:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $76, %edx
jmp .LBB2_2
.LBB2_9:
movq 32(%rsp), %rdi
movl $1234, %esi # imm = 0x4D2
callq hiprandSetPseudoRandomGeneratorSeed
testl %eax, %eax
je .LBB2_11
# %bb.10:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $80, %edx
jmp .LBB2_2
.LBB2_11:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movl $1048576, %edx # imm = 0x100000
callq hiprandGenerateUniform
testl %eax, %eax
je .LBB2_13
# %bb.12:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $83, %edx
jmp .LBB2_2
.LBB2_13:
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 16(%rsp), %rdi
movq 24(%rsp), %rsi
callq _Z27__device_stub__float_to_intPiPf
.LBB2_15:
movabsq $4294968320, %rdi # imm = 0x100000400
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_17
# %bb.16:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
callq _Z27__device_stub__simple_histoPiS_
.LBB2_17:
movq 8(%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_18
# %bb.30:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $102, %edx
jmp .LBB2_2
.LBB2_18: # %.preheader.preheader
xorl %r14d, %r14d
.LBB2_19: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB2_19
# %bb.20:
movl $10, %edi
callq putchar@PLT
movq 32(%rsp), %rdi
callq hiprandDestroyGenerator
testl %eax, %eax
je .LBB2_22
# %bb.21:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $123, %edx
jmp .LBB2_2
.LBB2_22:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_24
# %bb.23:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $124, %edx
jmp .LBB2_2
.LBB2_24:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_26
# %bb.25:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $125, %edx
jmp .LBB2_2
.LBB2_26:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
je .LBB2_28
# %bb.27:
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $126, %edx
.LBB2_2:
xorl %eax, %eax
callq printf
movl $1, %eax
.LBB2_29:
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_28:
.cfi_def_cfa_offset 64
movq %rbx, %rdi
callq free
xorl %eax, %eax
jmp .LBB2_29
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12float_to_intPiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12simple_histoPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12float_to_intPiPf,@object # @_Z12float_to_intPiPf
.section .rodata,"a",@progbits
.globl _Z12float_to_intPiPf
.p2align 3, 0x0
_Z12float_to_intPiPf:
.quad _Z27__device_stub__float_to_intPiPf
.size _Z12float_to_intPiPf, 8
.type _Z12simple_histoPiS_,@object # @_Z12simple_histoPiS_
.globl _Z12simple_histoPiS_
.p2align 3, 0x0
_Z12simple_histoPiS_:
.quad _Z27__device_stub__simple_histoPiS_
.size _Z12simple_histoPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error at %s:%d\n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/aleksey-uvarov/hpc-2019/master/histogram.hip"
.size .L.str.1, 102
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12float_to_intPiPf"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12simple_histoPiS_"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__float_to_intPiPf
.addrsig_sym _Z27__device_stub__simple_histoPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12float_to_intPiPf
.addrsig_sym _Z12simple_histoPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
void question1() {
/*
latency of arithmetic instruction = ~10+ ns
GK110 SM (Kepler) has:
2 warp schedulers
4 warp dispatchers
2 * 4 * 10 = 80 arithmetic instructions required
*/
}
void question2() {
/*
block shape = (32, 32, 1)
a)
int idx = threadIdx.y + blockSize.y * threadIdx.x;
if (idx % 32 < 16) {
foo();
}
else {
bar();
}
The code will not diverge because the idx will always be in iterations of 32; The block
size is 32x32x1 meaning every iteration of threadIdx.x will increment idx by a scale of
32. threadIdx.y will stay consistant for every thread inside the warp meaning the warp
will not diverge
b)
const float pi = 3.14;
float result = 1.0;
for (int i = 0; i < threadIdx.x; i++) {
result *= pi;
}
The code will diverge because each thread in the warp has a different threadIdx.x meaning
threads with smaller thread indices will have to stall and wait for the threads with
larger thread indices
*/
}
void question3() {
/*
block shape = (32, 32, 1)
a)
data[threadIdx.x + blockSize.x * threadIdx.y] = 1.0;
b)
data[threadIdx.y + blockSize.y * threadIdx.x] = 1.0;
c)
data[1 + threadIdx.x + blockSize.x * threadIdx.y] = 1.0;
*/
}
int main(void) {
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
void question1() {
/*
latency of arithmetic instruction = ~10+ ns
GK110 SM (Kepler) has:
2 warp schedulers
4 warp dispatchers
2 * 4 * 10 = 80 arithmetic instructions required
*/
}
void question2() {
/*
block shape = (32, 32, 1)
a)
int idx = threadIdx.y + blockSize.y * threadIdx.x;
if (idx % 32 < 16) {
foo();
}
else {
bar();
}
The code will not diverge because the idx will always be in iterations of 32; The block
size is 32x32x1 meaning every iteration of threadIdx.x will increment idx by a scale of
32. threadIdx.y will stay consistant for every thread inside the warp meaning the warp
will not diverge
b)
const float pi = 3.14;
float result = 1.0;
for (int i = 0; i < threadIdx.x; i++) {
result *= pi;
}
The code will diverge because each thread in the warp has a different threadIdx.x meaning
threads with smaller thread indices will have to stall and wait for the threads with
larger thread indices
*/
}
void question3() {
/*
block shape = (32, 32, 1)
a)
data[threadIdx.x + blockSize.x * threadIdx.y] = 1.0;
b)
data[threadIdx.y + blockSize.y * threadIdx.x] = 1.0;
c)
data[1 + threadIdx.x + blockSize.x * threadIdx.y] = 1.0;
*/
}
int main(void) {
} | .file "tmpxft_0007c973_00000000-6_questions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9question1v
.type _Z9question1v, @function
_Z9question1v:
.LFB2057:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2057:
.size _Z9question1v, .-_Z9question1v
.globl _Z9question2v
.type _Z9question2v, @function
_Z9question2v:
.LFB2058:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2058:
.size _Z9question2v, .-_Z9question2v
.globl _Z9question3v
.type _Z9question3v, @function
_Z9question3v:
.LFB2059:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2059:
.size _Z9question3v, .-_Z9question3v
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
void question1() {
/*
latency of arithmetic instruction = ~10+ ns
GK110 SM (Kepler) has:
2 warp schedulers
4 warp dispatchers
2 * 4 * 10 = 80 arithmetic instructions required
*/
}
void question2() {
/*
block shape = (32, 32, 1)
a)
int idx = threadIdx.y + blockSize.y * threadIdx.x;
if (idx % 32 < 16) {
foo();
}
else {
bar();
}
The code will not diverge because the idx will always be in iterations of 32; The block
size is 32x32x1 meaning every iteration of threadIdx.x will increment idx by a scale of
32. threadIdx.y will stay consistant for every thread inside the warp meaning the warp
will not diverge
b)
const float pi = 3.14;
float result = 1.0;
for (int i = 0; i < threadIdx.x; i++) {
result *= pi;
}
The code will diverge because each thread in the warp has a different threadIdx.x meaning
threads with smaller thread indices will have to stall and wait for the threads with
larger thread indices
*/
}
void question3() {
/*
block shape = (32, 32, 1)
a)
data[threadIdx.x + blockSize.x * threadIdx.y] = 1.0;
b)
data[threadIdx.y + blockSize.y * threadIdx.x] = 1.0;
c)
data[1 + threadIdx.x + blockSize.x * threadIdx.y] = 1.0;
*/
}
int main(void) {
} | #include <hip/hip_runtime.h>
#include <stdio.h>
void question1() {
/*
latency of arithmetic instruction = ~10+ ns
GK110 SM (Kepler) has:
2 warp schedulers
4 warp dispatchers
2 * 4 * 10 = 80 arithmetic instructions required
*/
}
void question2() {
/*
block shape = (32, 32, 1)
a)
int idx = threadIdx.y + blockSize.y * threadIdx.x;
if (idx % 32 < 16) {
foo();
}
else {
bar();
}
The code will not diverge because the idx will always be in iterations of 32; The block
size is 32x32x1 meaning every iteration of threadIdx.x will increment idx by a scale of
32. threadIdx.y will stay consistant for every thread inside the warp meaning the warp
will not diverge
b)
const float pi = 3.14;
float result = 1.0;
for (int i = 0; i < threadIdx.x; i++) {
result *= pi;
}
The code will diverge because each thread in the warp has a different threadIdx.x meaning
threads with smaller thread indices will have to stall and wait for the threads with
larger thread indices
*/
}
void question3() {
/*
block shape = (32, 32, 1)
a)
data[threadIdx.x + blockSize.x * threadIdx.y] = 1.0;
b)
data[threadIdx.y + blockSize.y * threadIdx.x] = 1.0;
c)
data[1 + threadIdx.x + blockSize.x * threadIdx.y] = 1.0;
*/
}
int main(void) {
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
void question1() {
/*
latency of arithmetic instruction = ~10+ ns
GK110 SM (Kepler) has:
2 warp schedulers
4 warp dispatchers
2 * 4 * 10 = 80 arithmetic instructions required
*/
}
void question2() {
/*
block shape = (32, 32, 1)
a)
int idx = threadIdx.y + blockSize.y * threadIdx.x;
if (idx % 32 < 16) {
foo();
}
else {
bar();
}
The code will not diverge because the idx will always be in iterations of 32; The block
size is 32x32x1 meaning every iteration of threadIdx.x will increment idx by a scale of
32. threadIdx.y will stay consistant for every thread inside the warp meaning the warp
will not diverge
b)
const float pi = 3.14;
float result = 1.0;
for (int i = 0; i < threadIdx.x; i++) {
result *= pi;
}
The code will diverge because each thread in the warp has a different threadIdx.x meaning
threads with smaller thread indices will have to stall and wait for the threads with
larger thread indices
*/
}
void question3() {
/*
block shape = (32, 32, 1)
a)
data[threadIdx.x + blockSize.x * threadIdx.y] = 1.0;
b)
data[threadIdx.y + blockSize.y * threadIdx.x] = 1.0;
c)
data[1 + threadIdx.x + blockSize.x * threadIdx.y] = 1.0;
*/
}
int main(void) {
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
void question1() {
/*
latency of arithmetic instruction = ~10+ ns
GK110 SM (Kepler) has:
2 warp schedulers
4 warp dispatchers
2 * 4 * 10 = 80 arithmetic instructions required
*/
}
void question2() {
/*
block shape = (32, 32, 1)
a)
int idx = threadIdx.y + blockSize.y * threadIdx.x;
if (idx % 32 < 16) {
foo();
}
else {
bar();
}
The code will not diverge because the idx will always be in iterations of 32; The block
size is 32x32x1 meaning every iteration of threadIdx.x will increment idx by a scale of
32. threadIdx.y will stay consistant for every thread inside the warp meaning the warp
will not diverge
b)
const float pi = 3.14;
float result = 1.0;
for (int i = 0; i < threadIdx.x; i++) {
result *= pi;
}
The code will diverge because each thread in the warp has a different threadIdx.x meaning
threads with smaller thread indices will have to stall and wait for the threads with
larger thread indices
*/
}
void question3() {
/*
block shape = (32, 32, 1)
a)
data[threadIdx.x + blockSize.x * threadIdx.y] = 1.0;
b)
data[threadIdx.y + blockSize.y * threadIdx.x] = 1.0;
c)
data[1 + threadIdx.x + blockSize.x * threadIdx.y] = 1.0;
*/
}
int main(void) {
} | .text
.file "questions.hip"
.globl _Z9question1v # -- Begin function _Z9question1v
.p2align 4, 0x90
.type _Z9question1v,@function
_Z9question1v: # @_Z9question1v
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z9question1v, .Lfunc_end0-_Z9question1v
.cfi_endproc
# -- End function
.globl _Z9question2v # -- Begin function _Z9question2v
.p2align 4, 0x90
.type _Z9question2v,@function
_Z9question2v: # @_Z9question2v
.cfi_startproc
# %bb.0:
retq
.Lfunc_end1:
.size _Z9question2v, .Lfunc_end1-_Z9question2v
.cfi_endproc
# -- End function
.globl _Z9question3v # -- Begin function _Z9question3v
.p2align 4, 0x90
.type _Z9question3v,@function
_Z9question3v: # @_Z9question3v
.cfi_startproc
# %bb.0:
retq
.Lfunc_end2:
.size _Z9question3v, .Lfunc_end2-_Z9question3v
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007c973_00000000-6_questions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9question1v
.type _Z9question1v, @function
_Z9question1v:
.LFB2057:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2057:
.size _Z9question1v, .-_Z9question1v
.globl _Z9question2v
.type _Z9question2v, @function
_Z9question2v:
.LFB2058:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2058:
.size _Z9question2v, .-_Z9question2v
.globl _Z9question3v
.type _Z9question3v, @function
_Z9question3v:
.LFB2059:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2059:
.size _Z9question3v, .-_Z9question3v
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "questions.hip"
.globl _Z9question1v # -- Begin function _Z9question1v
.p2align 4, 0x90
.type _Z9question1v,@function
_Z9question1v: # @_Z9question1v
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z9question1v, .Lfunc_end0-_Z9question1v
.cfi_endproc
# -- End function
.globl _Z9question2v # -- Begin function _Z9question2v
.p2align 4, 0x90
.type _Z9question2v,@function
_Z9question2v: # @_Z9question2v
.cfi_startproc
# %bb.0:
retq
.Lfunc_end1:
.size _Z9question2v, .Lfunc_end1-_Z9question2v
.cfi_endproc
# -- End function
.globl _Z9question3v # -- Begin function _Z9question3v
.p2align 4, 0x90
.type _Z9question3v,@function
_Z9question3v: # @_Z9question3v
.cfi_startproc
# %bb.0:
retq
.Lfunc_end2:
.size _Z9question3v, .Lfunc_end2-_Z9question3v
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //pass
//--gridDim=64 --blockDim=256
template<class TData> __global__ void testKernel(TData *d_odata, TData *d_idata, int numElements);
template __global__ void testKernel<int>(int *d_odata, int *d_idata, int numElements);
template<class TData> __global__ void testKernel(
TData *d_odata,
TData *d_idata,
int numElements
)
{
const int tid = blockDim.x * blockIdx.x + threadIdx.x;
const int numThreads = blockDim.x * gridDim.x;
for (int pos = tid; pos < numElements; pos += numThreads)
{
d_odata[pos] = d_idata[pos];
}
} | code for sm_80
Function : _Z10testKernelIiEvPT_S1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x300 ; /* 0x0000027000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x170], R0 ; /* 0x00005c0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x2f0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fd200078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fca00078e0206 */
/*0270*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0000a2000c1e1900 */
/*0280*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0290*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02b0*/ IMAD.WIDE R6, R0.reuse, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x041fe200078e0206 */
/*02c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0041e6000c101904 */
/*02d0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fd000078e0204 */
/*02e0*/ @P0 BRA 0x270 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0310*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x001fc800078e00ff */
/*0320*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fca00078e0206 */
/*0330*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x000ea2000c1e1900 */
/*0340*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R8, R0.reuse, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x040fe200078e0204 */
/*0360*/ STG.E [R6.64], R19 ; /* 0x0000001306007986 */
/* 0x0041e8000c101904 */
/*0370*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0390*/ IMAD.WIDE R12, R0.reuse, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x040fe200078e0208 */
/*03a0*/ STG.E [R10.64], R21 ; /* 0x000000150a007986 */
/* 0x0041e8000c101904 */
/*03b0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*03d0*/ IMAD.WIDE R16, R0.reuse, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x040fe200078e020c */
/*03e0*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0041ea000c101904 */
/*03f0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IMAD.WIDE R4, R0.reuse, 0x4, R14 ; /* 0x0000000400047825 */
/* 0x040fe200078e020e */
/*0410*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0420*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0430*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*0440*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x0041d8000c101904 */
/*0450*/ @!P0 BRA 0x310 ; /* 0xfffffeb000008947 */
/* 0x000fea000383ffff */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ BRA 0x470; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //pass
//--gridDim=64 --blockDim=256
template<class TData> __global__ void testKernel(TData *d_odata, TData *d_idata, int numElements);
template __global__ void testKernel<int>(int *d_odata, int *d_idata, int numElements);
template<class TData> __global__ void testKernel(
TData *d_odata,
TData *d_idata,
int numElements
)
{
const int tid = blockDim.x * blockIdx.x + threadIdx.x;
const int numThreads = blockDim.x * gridDim.x;
for (int pos = tid; pos < numElements; pos += numThreads)
{
d_odata[pos] = d_idata[pos];
}
} | .file "tmpxft_00169ffa_00000000-6_alignedTypes.cudafe1.cpp"
.text
#APP
#NO_APP
.section .text._Z10testKernelIiEvPT_S1_i,"axG",@progbits,_Z10testKernelIiEvPT_S1_i,comdat
.weak _Z10testKernelIiEvPT_S1_i
.type _Z10testKernelIiEvPT_S1_i, @function
_Z10testKernelIiEvPT_S1_i:
.LFB2102:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10testKernelIiEvPT_S1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2102:
.size _Z10testKernelIiEvPT_S1_i, .-_Z10testKernelIiEvPT_S1_i
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10testKernelIiEvPT_S1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10testKernelIiEvPT_S1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //pass
//--gridDim=64 --blockDim=256
template<class TData> __global__ void testKernel(TData *d_odata, TData *d_idata, int numElements);
template __global__ void testKernel<int>(int *d_odata, int *d_idata, int numElements);
template<class TData> __global__ void testKernel(
TData *d_odata,
TData *d_idata,
int numElements
)
{
const int tid = blockDim.x * blockIdx.x + threadIdx.x;
const int numThreads = blockDim.x * gridDim.x;
for (int pos = tid; pos < numElements; pos += numThreads)
{
d_odata[pos] = d_idata[pos];
}
} | #include <hip/hip_runtime.h>
//pass
//--gridDim=64 --blockDim=256
template<class TData> __global__ void testKernel(TData *d_odata, TData *d_idata, int numElements);
template __global__ void testKernel<int>(int *d_odata, int *d_idata, int numElements);
template<class TData> __global__ void testKernel(
TData *d_odata,
TData *d_idata,
int numElements
)
{
const int tid = blockDim.x * blockIdx.x + threadIdx.x;
const int numThreads = blockDim.x * gridDim.x;
for (int pos = tid; pos < numElements; pos += numThreads)
{
d_odata[pos] = d_idata[pos];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//pass
//--gridDim=64 --blockDim=256
template<class TData> __global__ void testKernel(TData *d_odata, TData *d_idata, int numElements);
template __global__ void testKernel<int>(int *d_odata, int *d_idata, int numElements);
template<class TData> __global__ void testKernel(
TData *d_odata,
TData *d_idata,
int numElements
)
{
const int tid = blockDim.x * blockIdx.x + threadIdx.x;
const int numThreads = blockDim.x * gridDim.x;
for (int pos = tid; pos < numElements; pos += numThreads)
{
d_odata[pos] = d_idata[pos];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z10testKernelIiEvPT_S1_i,"axG",@progbits,_Z10testKernelIiEvPT_S1_i,comdat
.protected _Z10testKernelIiEvPT_S1_i
.globl _Z10testKernelIiEvPT_S1_i
.p2align 8
.type _Z10testKernelIiEvPT_S1_i,@function
_Z10testKernelIiEvPT_S1_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s2, v1
global_load_b32 v0, v[4:5], off
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s10, v1
v_add_co_u32 v2, s0, v2, s8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10testKernelIiEvPT_S1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z10testKernelIiEvPT_S1_i,"axG",@progbits,_Z10testKernelIiEvPT_S1_i,comdat
.Lfunc_end0:
.size _Z10testKernelIiEvPT_S1_i, .Lfunc_end0-_Z10testKernelIiEvPT_S1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10testKernelIiEvPT_S1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10testKernelIiEvPT_S1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//pass
//--gridDim=64 --blockDim=256
template<class TData> __global__ void testKernel(TData *d_odata, TData *d_idata, int numElements);
template __global__ void testKernel<int>(int *d_odata, int *d_idata, int numElements);
template<class TData> __global__ void testKernel(
TData *d_odata,
TData *d_idata,
int numElements
)
{
const int tid = blockDim.x * blockIdx.x + threadIdx.x;
const int numThreads = blockDim.x * gridDim.x;
for (int pos = tid; pos < numElements; pos += numThreads)
{
d_odata[pos] = d_idata[pos];
}
} | .text
.file "alignedTypes.hip"
.section .text._Z25__device_stub__testKernelIiEvPT_S1_i,"axG",@progbits,_Z25__device_stub__testKernelIiEvPT_S1_i,comdat
.weak _Z25__device_stub__testKernelIiEvPT_S1_i # -- Begin function _Z25__device_stub__testKernelIiEvPT_S1_i
.p2align 4, 0x90
.type _Z25__device_stub__testKernelIiEvPT_S1_i,@function
_Z25__device_stub__testKernelIiEvPT_S1_i: # @_Z25__device_stub__testKernelIiEvPT_S1_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10testKernelIiEvPT_S1_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__testKernelIiEvPT_S1_i, .Lfunc_end0-_Z25__device_stub__testKernelIiEvPT_S1_i
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10testKernelIiEvPT_S1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10testKernelIiEvPT_S1_i,@object # @_Z10testKernelIiEvPT_S1_i
.section .rodata,"a",@progbits
.weak _Z10testKernelIiEvPT_S1_i
.p2align 3, 0x0
_Z10testKernelIiEvPT_S1_i:
.quad _Z25__device_stub__testKernelIiEvPT_S1_i
.size _Z10testKernelIiEvPT_S1_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10testKernelIiEvPT_S1_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__testKernelIiEvPT_S1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10testKernelIiEvPT_S1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10testKernelIiEvPT_S1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x300 ; /* 0x0000027000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x170], R0 ; /* 0x00005c0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x2f0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fd200078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fca00078e0206 */
/*0270*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0000a2000c1e1900 */
/*0280*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0290*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02b0*/ IMAD.WIDE R6, R0.reuse, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x041fe200078e0206 */
/*02c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0041e6000c101904 */
/*02d0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fd000078e0204 */
/*02e0*/ @P0 BRA 0x270 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*02f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0300*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0310*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x001fc800078e00ff */
/*0320*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fca00078e0206 */
/*0330*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x000ea2000c1e1900 */
/*0340*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R8, R0.reuse, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x040fe200078e0204 */
/*0360*/ STG.E [R6.64], R19 ; /* 0x0000001306007986 */
/* 0x0041e8000c101904 */
/*0370*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0390*/ IMAD.WIDE R12, R0.reuse, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x040fe200078e0208 */
/*03a0*/ STG.E [R10.64], R21 ; /* 0x000000150a007986 */
/* 0x0041e8000c101904 */
/*03b0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*03d0*/ IMAD.WIDE R16, R0.reuse, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x040fe200078e020c */
/*03e0*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0041ea000c101904 */
/*03f0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IMAD.WIDE R4, R0.reuse, 0x4, R14 ; /* 0x0000000400047825 */
/* 0x040fe200078e020e */
/*0410*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0420*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0430*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*0440*/ STG.E [R4.64], R17 ; /* 0x0000001104007986 */
/* 0x0041d8000c101904 */
/*0450*/ @!P0 BRA 0x310 ; /* 0xfffffeb000008947 */
/* 0x000fea000383ffff */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ BRA 0x470; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z10testKernelIiEvPT_S1_i,"axG",@progbits,_Z10testKernelIiEvPT_S1_i,comdat
.protected _Z10testKernelIiEvPT_S1_i
.globl _Z10testKernelIiEvPT_S1_i
.p2align 8
.type _Z10testKernelIiEvPT_S1_i,@function
_Z10testKernelIiEvPT_S1_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s2, v1
global_load_b32 v0, v[4:5], off
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s10, v1
v_add_co_u32 v2, s0, v2, s8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10testKernelIiEvPT_S1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z10testKernelIiEvPT_S1_i,"axG",@progbits,_Z10testKernelIiEvPT_S1_i,comdat
.Lfunc_end0:
.size _Z10testKernelIiEvPT_S1_i, .Lfunc_end0-_Z10testKernelIiEvPT_S1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10testKernelIiEvPT_S1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10testKernelIiEvPT_S1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00169ffa_00000000-6_alignedTypes.cudafe1.cpp"
.text
#APP
#NO_APP
.section .text._Z10testKernelIiEvPT_S1_i,"axG",@progbits,_Z10testKernelIiEvPT_S1_i,comdat
.weak _Z10testKernelIiEvPT_S1_i
.type _Z10testKernelIiEvPT_S1_i, @function
_Z10testKernelIiEvPT_S1_i:
.LFB2102:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10testKernelIiEvPT_S1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2102:
.size _Z10testKernelIiEvPT_S1_i, .-_Z10testKernelIiEvPT_S1_i
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10testKernelIiEvPT_S1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10testKernelIiEvPT_S1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "alignedTypes.hip"
.section .text._Z25__device_stub__testKernelIiEvPT_S1_i,"axG",@progbits,_Z25__device_stub__testKernelIiEvPT_S1_i,comdat
.weak _Z25__device_stub__testKernelIiEvPT_S1_i # -- Begin function _Z25__device_stub__testKernelIiEvPT_S1_i
.p2align 4, 0x90
.type _Z25__device_stub__testKernelIiEvPT_S1_i,@function
_Z25__device_stub__testKernelIiEvPT_S1_i: # @_Z25__device_stub__testKernelIiEvPT_S1_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10testKernelIiEvPT_S1_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__testKernelIiEvPT_S1_i, .Lfunc_end0-_Z25__device_stub__testKernelIiEvPT_S1_i
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10testKernelIiEvPT_S1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10testKernelIiEvPT_S1_i,@object # @_Z10testKernelIiEvPT_S1_i
.section .rodata,"a",@progbits
.weak _Z10testKernelIiEvPT_S1_i
.p2align 3, 0x0
_Z10testKernelIiEvPT_S1_i:
.quad _Z25__device_stub__testKernelIiEvPT_S1_i
.size _Z10testKernelIiEvPT_S1_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10testKernelIiEvPT_S1_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__testKernelIiEvPT_S1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10testKernelIiEvPT_S1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ __forceinline__ float sigmoid(float a) {
return 1.0 / (1.0 + exp (-a));
}
__global__ void sigmoid_kernel(float *vec, int len) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < len) {
vec[index] = sigmoid(vec[index]);
}
} | code for sm_80
Function : _Z14sigmoid_kernelPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ; /* 0x3bbb989dff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x437c0000 ; /* 0x437c0000ff077424 */
/* 0x000fe200078e00ff */
/*00c0*/ BSSY B0, 0x250 ; /* 0x0000018000007945 */
/* 0x000ff00003800000 */
/*00d0*/ FFMA.SAT R4, -R0, R5, 0.5 ; /* 0x3f00000000047423 */
/* 0x004fc80000002105 */
/*00e0*/ FFMA.RM R4, R4, R7, 12582913 ; /* 0x4b40000104047423 */
/* 0x000fc80000004007 */
/*00f0*/ FADD R5, R4.reuse, -12583039 ; /* 0xcb40007f04057421 */
/* 0x040fe40000000000 */
/*0100*/ IMAD.SHL.U32 R4, R4, 0x800000, RZ ; /* 0x0080000004047824 */
/* 0x000fe400078e00ff */
/*0110*/ FFMA R5, -R0, 1.4426950216293334961, -R5 ; /* 0x3fb8aa3b00057823 */
/* 0x000fc80000000905 */
/*0120*/ FFMA R0, -R0, 1.925963033500011079e-08, R5 ; /* 0x32a5706000007823 */
/* 0x000fc80000000105 */
/*0130*/ MUFU.EX2 R5, R0 ; /* 0x0000000000057308 */
/* 0x000e240000000800 */
/*0140*/ FMUL R12, R4, R5 ; /* 0x00000005040c7220 */
/* 0x001fcc0000400000 */
/*0150*/ F2F.F64.F32 R4, R12 ; /* 0x0000000c00047310 */
/* 0x000e240000201800 */
/*0160*/ DADD R4, R4, 1 ; /* 0x3ff0000004047429 */
/* 0x001e0c0000000000 */
/*0170*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e280000001800 */
/*0180*/ IADD3 R6, R5, 0x300402, RZ ; /* 0x0030040205067810 */
/* 0x000fc80007ffe0ff */
/*0190*/ FSETP.GEU.AND P0, PT, |R6|, 5.8789094863358348022e-39, PT ; /* 0x004004020600780b */
/* 0x000fe40003f0e200 */
/*01a0*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000106 */
/*01b0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*01c0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*01d0*/ DFMA R10, -R4, R8, 1 ; /* 0x3ff00000040a742b */
/* 0x001e0c0000000108 */
/*01e0*/ DFMA R8, R8, R10, R8 ; /* 0x0000000a0808722b */
/* 0x0010620000000008 */
/*01f0*/ @P0 BRA 0x240 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0200*/ LOP3.LUT R0, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05007812 */
/* 0x000fc800078ec0ff */
/*0210*/ IADD3 R8, R0, -0x100000, RZ ; /* 0xfff0000000087810 */
/* 0x002fe40007ffe0ff */
/*0220*/ MOV R0, 0x240 ; /* 0x0000024000007802 */
/* 0x000fe40000000f00 */
/*0230*/ CALL.REL.NOINC 0x280 ; /* 0x0000004000007944 */
/* 0x001fea0003c00000 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x002e640000301000 */
/*0260*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x002fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ DSETP.GTU.AND P0, PT, |R4|, +INF , PT ; /* 0x7ff000000400742a */
/* 0x000e220003f0c200 */
/*0290*/ BSSY B1, 0x4d0 ; /* 0x0000023000017945 */
/* 0x000fda0003800000 */
/*02a0*/ @P0 BRA 0x4a0 ; /* 0x000001f000000947 */
/* 0x001fea0003800000 */
/*02b0*/ LOP3.LUT R9, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05097812 */
/* 0x000fc800078ec0ff */
/*02c0*/ IADD3 R6, R9, -0x1, RZ ; /* 0xffffffff09067810 */
/* 0x000fc80007ffe0ff */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R6, 0x7fefffff, PT ; /* 0x7fefffff0600780c */
/* 0x000fda0003f06070 */
/*02e0*/ @P0 LOP3.LUT R7, R5, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff0000005070812 */
/* 0x000fe400078e3cff */
/*02f0*/ @P0 MOV R6, RZ ; /* 0x000000ff00060202 */
/* 0x000fe20000000f00 */
/*0300*/ @P0 BRA 0x4c0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GE.U32.AND P0, PT, R9, 0x1000001, PT ; /* 0x010000010900780c */
/* 0x000fda0003f06070 */
/*0320*/ @!P0 BRA 0x400 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0330*/ IADD3 R7, R5, -0x3fe00000, RZ ; /* 0xc020000005077810 */
/* 0x000fe20007ffe0ff */
/*0340*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fc600078e0004 */
/*0350*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x000e260000001800 */
/*0360*/ DFMA R10, -R6, R8, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c0000000108 */
/*0370*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0380*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*0390*/ DFMA R8, -R6, R10, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c000000010a */
/*03a0*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*03b0*/ DMUL R8, R8, 2.2250738585072013831e-308 ; /* 0x0010000008087828 */
/* 0x001e0c0000000000 */
/*03c0*/ DFMA R4, -R4, R8, 1 ; /* 0x3ff000000404742b */
/* 0x001e0c0000000108 */
/*03d0*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*03e0*/ DFMA R6, R8, R4, R8 ; /* 0x000000040806722b */
/* 0x0010620000000008 */
/*03f0*/ BRA 0x4c0 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0400*/ DMUL R4, R4, 8.11296384146066816958e+31 ; /* 0x4690000004047828 */
/* 0x000e220000000000 */
/*0410*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fca00078e0008 */
/*0420*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e240000001800 */
/*0430*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000106 */
/*0440*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0450*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0460*/ DFMA R6, -R4, R8, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000108 */
/*0470*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x001e0c0000000008 */
/*0480*/ DMUL R6, R6, 8.11296384146066816958e+31 ; /* 0x4690000006067828 */
/* 0x001e220000000000 */
/*0490*/ BRA 0x4c0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*04a0*/ LOP3.LUT R7, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000005077812 */
/* 0x000fe400078efcff */
/*04b0*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fe40000000f00 */
/*04c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04d0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x001fe200000001ff */
/*04e0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0000 */
/*04f0*/ MOV R9, R7 ; /* 0x0000000700097202 */
/* 0x002fe20000000f00 */
/*0500*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0006 */
/*0510*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffae004007950 */
/* 0x000fea0003c3ffff */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ __forceinline__ float sigmoid(float a) {
return 1.0 / (1.0 + exp (-a));
}
__global__ void sigmoid_kernel(float *vec, int len) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < len) {
vec[index] = sigmoid(vec[index]);
}
} | .file "tmpxft_001aeb11_00000000-6_sigmoid_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z14sigmoid_kernelPfiPfi
.type _Z35__device_stub__Z14sigmoid_kernelPfiPfi, @function
_Z35__device_stub__Z14sigmoid_kernelPfiPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14sigmoid_kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z35__device_stub__Z14sigmoid_kernelPfiPfi, .-_Z35__device_stub__Z14sigmoid_kernelPfiPfi
.globl _Z14sigmoid_kernelPfi
.type _Z14sigmoid_kernelPfi, @function
_Z14sigmoid_kernelPfi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14sigmoid_kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14sigmoid_kernelPfi, .-_Z14sigmoid_kernelPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14sigmoid_kernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sigmoid_kernelPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ __forceinline__ float sigmoid(float a) {
return 1.0 / (1.0 + exp (-a));
}
__global__ void sigmoid_kernel(float *vec, int len) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < len) {
vec[index] = sigmoid(vec[index]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ __forceinline__ float sigmoid(float a) {
return 1.0 / (1.0 + exp (-a));
}
__global__ void sigmoid_kernel(float *vec, int len) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < len) {
vec[index] = sigmoid(vec[index]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ __forceinline__ float sigmoid(float a) {
return 1.0 / (1.0 + exp (-a));
}
__global__ void sigmoid_kernel(float *vec, int len) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < len) {
vec[index] = sigmoid(vec[index]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sigmoid_kernelPfi
.globl _Z14sigmoid_kernelPfi
.p2align 8
.type _Z14sigmoid_kernelPfi,@function
_Z14sigmoid_kernelPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0xbfb8aa3b, v2
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v2
v_fma_f32 v4, v2, 0xbfb8aa3b, -v3
v_rndne_f32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v4, v2, 0xb2a5705f, v4 :: v_dual_sub_f32 v3, v3, v5
v_add_f32_e32 v3, v3, v4
v_cvt_i32_f32_e32 v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v3, v4
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], 1.0
v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, 1.0, v[2:3], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[8:9], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sigmoid_kernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sigmoid_kernelPfi, .Lfunc_end0-_Z14sigmoid_kernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sigmoid_kernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14sigmoid_kernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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