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stringlengths 10
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You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Single Author info:
hmajety Hari Krishna Majety
Group info:
hmajety Hari Krishna Majety
srout Sweta Rout
mreddy2 Harshavardhan Reddy Muppidi
*/
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <time.h>
#define __DEBUG
#define TSCALE 1.0
#define VSQR 0.1
#define CUDA_CALL( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CUDA_CHK_ERR() __cudaCheckError(__FILE__,__LINE__)
extern int tpdt(double *t, double dt, double end_time);
/**************************************
* void __cudaSafeCall(cudaError err, const char *file, const int line)
* void __cudaCheckError(const char *file, const int line)
*
* These routines were taken from the GPU Computing SDK
* (http://developer.nvidia.com/gpu-computing-sdk) include file "cutil.h"
**************************************/
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef __DEBUG
#pragma warning( push )
#pragma warning( disable: 4127 ) // Prevent warning on do-while(0);
do
{
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s.\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment if not needed.
/*err = cudaThreadSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s.\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}*/
} while ( 0 );
#pragma warning( pop )
#endif // __DEBUG
return;
}
__global__ void evolve_GPU(double *un, double *uc, double *uo, double *pebbles, int n, double h, double dt, double t, int nThreads){
int idx = blockIdx.x*blockDim.x+threadIdx.x;
int i, j;
i = idx % n;
j = idx /n;
if(idx<n*n){
if( i == 0 || i == n - 1 || j == 0 || j == n - 1)
{
un[idx] = 0.;
}
else{
un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] + 0.25*(uc[idx + n - 1] + uc[idx + n + 1] + uc[idx - n - 1] + uc[idx - n + 1]) -
5 * uc[idx])/(h * h) + (double)(-__expf(-TSCALE * (float)t) * pebbles[idx]));
//un[idx] = 5;
/*un[idx] = 2*uc[idx] - uo[idx] + VSQR *(dt * dt) *((uc[idx-1] + uc[idx+1] +
uc[idx + n] + uc[idx - n] - 4 * uc[idx])/(h * h) + (double)(-__expf(-TSCALE * (float)t) ));*/
}
}
}
void run_gpu(double *u, double *u0, double *u1, double *pebbles, int n, double h, double end_time, int nthreads)
{
hipEvent_t kstart, kstop;
float ktime;
/* HW2: Define your local variables here */
double *uc, *uo, *nd, *cd, *od, *pebblesd;
double t, dt;
//un = (double*)malloc(sizeof(double) * n * n);
uc = (double*)malloc(sizeof(double) * n * n);
uo = (double*)malloc(sizeof(double) * n * n);
memcpy(uo, u0, sizeof(double) * n * n);
memcpy(uc, u1, sizeof(double) * n * n);
t = 0.0;
dt = h / 2.;
/*for (int i = 0; i < n*n; ++i)
{
printf("%d - %lf; ",i, pebbles[i]);
}*/
/* Set up device timers */
CUDA_CALL(hipSetDevice(0));
CUDA_CALL(hipEventCreate(&kstart));
CUDA_CALL(hipEventCreate(&kstop));
/* HW2: Add CUDA kernel call preperation code here */
int threadsPerBlock = nthreads * nthreads;
int nBlocks = (n/nthreads)*(n/nthreads);
//dim3 blockdims(nthreads,nthreads,1);
//dim3 griddims(n/nthreads , n/nthreads , 1 );
/* Start GPU computation timer */
CUDA_CALL(hipEventRecord(kstart, 0));
/* HW2: Add main lake simulation loop here */
//Allocate CUDA Variables
CUDA_CALL(hipMalloc((void **)&od, n*n*sizeof(double)));
CUDA_CALL(hipMalloc((void **)&cd, n*n*sizeof(double)));
CUDA_CALL(hipMalloc((void **)&nd, n*n*sizeof(double)));
CUDA_CALL(hipMalloc((void **)&pebblesd, n*n*sizeof(double)));
//Copy values from Host to Device
CUDA_CALL(hipMemcpy(od,uo, n*n*sizeof(double), hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpy(cd,uc, n*n*sizeof(double), hipMemcpyHostToDevice));
CUDA_CALL(hipMemcpy(pebblesd,pebbles, n*n*sizeof(double), hipMemcpyHostToDevice));
double *temp;
//int count=0;
while(1){
evolve_GPU<<<nBlocks,threadsPerBlock>>>(nd,cd,od,pebblesd,n,h,dt,t,nthreads);
//Exchange the variables to pass them for next iteration
temp = od;
od = cd;
cd = nd;
//printf(" %lf\n", t);
if(!tpdt(&t,dt,end_time)) break;
nd = temp;
}
//printf("%lf,%lf",sizeof(u),u[1]);
hipMemcpy(u,nd, n*n*sizeof(double), hipMemcpyDeviceToHost);
/* Stop GPU computation timer */
/*for (int i = 0; i < n; ++i)
{
for (int j = 0; j < n; ++j)
{
printf("%lf\n", u[i*n+j]);
}
}*/
CUDA_CALL(hipEventRecord(kstop, 0));
CUDA_CALL(hipEventSynchronize(kstop));
CUDA_CALL(hipEventElapsedTime(&ktime, kstart, kstop));
printf("GPU computation: %f msec\n", ktime);
/* HW2: Add post CUDA kernel call processing and cleanup here */
CUDA_CALL(hipFree(od));
CUDA_CALL(hipFree(cd));
CUDA_CALL(hipFree(temp));
CUDA_CALL(hipFree(pebblesd));
free(uc);
free(uo);
/* timer cleanup */
CUDA_CALL(hipEventDestroy(kstart));
CUDA_CALL(hipEventDestroy(kstop));
CUDA_CALL(hipDeviceReset());
} | .text
.file "lakegpu.hip"
.globl _Z25__device_stub__evolve_GPUPdS_S_S_idddi # -- Begin function _Z25__device_stub__evolve_GPUPdS_S_S_idddi
.p2align 4, 0x90
.type _Z25__device_stub__evolve_GPUPdS_S_S_idddi,@function
_Z25__device_stub__evolve_GPUPdS_S_S_idddi: # @_Z25__device_stub__evolve_GPUPdS_S_S_idddi
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 4(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
movl %r9d, (%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
movq %rsp, %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10evolve_GPUPdS_S_S_idddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z25__device_stub__evolve_GPUPdS_S_S_idddi, .Lfunc_end0-_Z25__device_stub__evolve_GPUPdS_S_S_idddi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7run_gpuPdS_S_S_iddi
.LCPI1_0:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z7run_gpuPdS_S_S_iddi
.p2align 4, 0x90
.type _Z7run_gpuPdS_S_S_iddi,@function
_Z7run_gpuPdS_S_S_iddi: # @_Z7run_gpuPdS_S_S_iddi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, 4(%rsp) # 4-byte Spill
movsd %xmm1, 128(%rsp) # 8-byte Spill
movsd %xmm0, 72(%rsp) # 8-byte Spill
movq %rcx, %r12
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, 120(%rsp) # 8-byte Spill
movl %r8d, 28(%rsp) # 4-byte Spill
movslq %r8d, %r15
imulq %r15, %r15
shlq $3, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r13
movq %r15, %rdi
callq malloc
movq %rax, %rbp
movq %rax, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
movq %r13, %rdi
movq %rbx, %rsi
movq %r15, %rdx
callq memcpy@PLT
movq $0, 88(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z14__cudaSafeCall10hipError_tPKci.exit
leaq 56(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z14__cudaSafeCall10hipError_tPKci.exit54
leaq 40(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
movl 28(%rsp), %r14d # 4-byte Reload
jne .LBB1_6
# %bb.7: # %_Z14__cudaSafeCall10hipError_tPKci.exit56
movl %r14d, %eax
cltd
idivl 4(%rsp) # 4-byte Folded Reload
movl %eax, %ebx
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z14__cudaSafeCall10hipError_tPKci.exit58
# kill: def $r14d killed $r14d def $r14
imull %r14d, %r14d
shlq $3, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z14__cudaSafeCall10hipError_tPKci.exit60
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_Z14__cudaSafeCall10hipError_tPKci.exit62
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_Z14__cudaSafeCall10hipError_tPKci.exit64
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z14__cudaSafeCall10hipError_tPKci.exit66
movq 8(%rsp), %rdi
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z14__cudaSafeCall10hipError_tPKci.exit68
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_Z14__cudaSafeCall10hipError_tPKci.exit70
movq %rbp, 96(%rsp) # 8-byte Spill
movq %r13, 104(%rsp) # 8-byte Spill
movq 48(%rsp), %rdi
movq %r12, %rsi
movq %r14, 112(%rsp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_48
# %bb.22: # %_Z14__cudaSafeCall10hipError_tPKci.exit72.preheader
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd 72(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 80(%rsp) # 8-byte Spill
movl 4(%rsp), %eax # 4-byte Reload
imull %eax, %eax
imull %ebx, %ebx
movl %ebx, %ebx
movabsq $4294967296, %rcx # imm = 0x100000000
orq %rcx, %rbx
movl %eax, %r12d
orq %rcx, %r12
leaq 136(%rsp), %rbp
leaq 240(%rsp), %r15
leaq 88(%rsp), %r13
.p2align 4, 0x90
.LBB1_23: # %_Z14__cudaSafeCall10hipError_tPKci.exit72
# =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_25
# %bb.24: # in Loop: Header=BB1_23 Depth=1
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq 48(%rsp), %rsi
movsd 88(%rsp), %xmm0 # xmm0 = mem[0],zero
movq %rax, 232(%rsp)
movq %rcx, 224(%rsp)
movq %rdx, 216(%rsp)
movq %rsi, 208(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 68(%rsp)
movsd 72(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movsd %xmm1, 200(%rsp)
movsd 80(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movsd %xmm1, 192(%rsp)
movsd %xmm0, 184(%rsp)
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, 64(%rsp)
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 208(%rsp), %rax
movq %rax, 264(%rsp)
leaq 68(%rsp), %rax
movq %rax, 272(%rsp)
leaq 200(%rsp), %rax
movq %rax, 280(%rsp)
leaq 192(%rsp), %rax
movq %rax, 288(%rsp)
leaq 184(%rsp), %rax
movq %rax, 296(%rsp)
leaq 64(%rsp), %rax
movq %rax, 304(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
movl $_Z10evolve_GPUPdS_S_S_idddi, %edi
movq %r15, %r9
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_25: # in Loop: Header=BB1_23 Depth=1
movq 8(%rsp), %r14
movq 16(%rsp), %rax
movq %rax, 8(%rsp)
movq 32(%rsp), %rax
movq %rax, 16(%rsp)
movq %r13, %rdi
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 128(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
callq _Z4tpdtPddd
testl %eax, %eax
je .LBB1_27
# %bb.26: # in Loop: Header=BB1_23 Depth=1
movq %r14, 32(%rsp)
jmp .LBB1_23
.LBB1_27:
movq 32(%rsp), %rsi
movq 120(%rsp), %rdi # 8-byte Reload
movq 112(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_28
# %bb.29: # %_Z14__cudaSafeCall10hipError_tPKci.exit74
movq 40(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
movq 104(%rsp), %rbx # 8-byte Reload
movq 96(%rsp), %r15 # 8-byte Reload
jne .LBB1_30
# %bb.31: # %_Z14__cudaSafeCall10hipError_tPKci.exit76
movq 56(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 240(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_32
# %bb.33: # %_Z14__cudaSafeCall10hipError_tPKci.exit78
movss 240(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_34
# %bb.35: # %_Z14__cudaSafeCall10hipError_tPKci.exit80
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_36
# %bb.37: # %_Z14__cudaSafeCall10hipError_tPKci.exit82
movq %r14, %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_38
# %bb.39: # %_Z14__cudaSafeCall10hipError_tPKci.exit84
movq 48(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_40
# %bb.41: # %_Z14__cudaSafeCall10hipError_tPKci.exit86
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq 56(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_42
# %bb.43: # %_Z14__cudaSafeCall10hipError_tPKci.exit88
movq 40(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_44
# %bb.45: # %_Z14__cudaSafeCall10hipError_tPKci.exit90
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_46
# %bb.47: # %_Z14__cudaSafeCall10hipError_tPKci.exit92
addq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 368
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $128, %ecx
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $129, %ecx
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $130, %ecx
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $140, %ecx
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $144, %ecx
jmp .LBB1_2
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $145, %ecx
jmp .LBB1_2
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $146, %ecx
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $147, %ecx
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $150, %ecx
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $151, %ecx
jmp .LBB1_2
.LBB1_48:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $152, %ecx
jmp .LBB1_2
.LBB1_28:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $175, %ecx
jmp .LBB1_2
.LBB1_30:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $176, %ecx
jmp .LBB1_2
.LBB1_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $177, %ecx
jmp .LBB1_2
.LBB1_34:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $181, %ecx
jmp .LBB1_2
.LBB1_36:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $182, %ecx
jmp .LBB1_2
.LBB1_38:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $183, %ecx
jmp .LBB1_2
.LBB1_40:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $184, %ecx
jmp .LBB1_2
.LBB1_42:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $188, %ecx
jmp .LBB1_2
.LBB1_44:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $189, %ecx
jmp .LBB1_2
.LBB1_46:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $190, %ecx
.LBB1_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z7run_gpuPdS_S_S_iddi, .Lfunc_end1-_Z7run_gpuPdS_S_S_iddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10evolve_GPUPdS_S_S_idddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10evolve_GPUPdS_S_S_idddi,@object # @_Z10evolve_GPUPdS_S_S_idddi
.section .rodata,"a",@progbits
.globl _Z10evolve_GPUPdS_S_S_idddi
.p2align 3, 0x0
_Z10evolve_GPUPdS_S_S_idddi:
.quad _Z25__device_stub__evolve_GPUPdS_S_S_idddi
.size _Z10evolve_GPUPdS_S_S_idddi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/majetyhk/ParallelProgramming/master/HW2/p3/V2/lakegpu.hip"
.size .L.str, 115
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU computation: %f msec\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudaSafeCall() failed at %s:%i : %s\n"
.size .L.str.2, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10evolve_GPUPdS_S_S_idddi"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__evolve_GPUPdS_S_S_idddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10evolve_GPUPdS_S_S_idddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10evolve_GPUPdS_S_S_idddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff057624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0050*/ IMAD R3, R5, c[0x0][0x180], RZ ; /* 0x0000600005037a24 */
/* 0x000fca00078e02ff */
/*0060*/ ISETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R7, c[0x0][0x180] ; /* 0x0000600000077a13 */
/* 0x000fe20000000000 */
/*0090*/ IMAD.MOV.U32 R21, RZ, RZ, 0x8 ; /* 0x00000008ff157424 */
/* 0x000fe200078e00ff */
/*00a0*/ LOP3.LUT R10, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff0a7a12 */
/* 0x000fe200078e33ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e220000209400 */
/*00d0*/ IMAD.WIDE R16, R0, R21, c[0x0][0x160] ; /* 0x0000580000107625 */
/* 0x000fce00078e0215 */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fe200078e02ff */
/*0140*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*0150*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fe200078e0002 */
/*0160*/ LOP3.LUT R2, R0, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x0000600000027a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*0180*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*01a0*/ IMAD R4, R7, R4, R6 ; /* 0x0000000407047224 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GT.U32.AND P1, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f24070 */
/*01c0*/ @!P1 IMAD.IADD R4, R4, 0x1, -R7 ; /* 0x0000000104049824 */
/* 0x000fe200078e0a07 */
/*01d0*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe40003f06070 */
/*01f0*/ IADD3 R4, R5, -0x1, RZ ; /* 0xffffffff05047810 */
/* 0x000fd60007ffe0ff */
/*0200*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fc60003f05270 */
/*0220*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fca00078e0a03 */
/*0230*/ SEL R3, R10, R3, !P0 ; /* 0x000000030a037207 */
/* 0x000fca0004000000 */
/*0240*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a03 */
/*0250*/ IMAD R2, R7, c[0x0][0x180], R0 ; /* 0x0000600007027a24 */
/* 0x000fca00078e0200 */
/*0260*/ ISETP.NE.AND P0, PT, R2, R4, PT ; /* 0x000000040200720c */
/* 0x000fc80003f05270 */
/*0270*/ ISETP.EQ.OR P0, PT, R2, RZ, !P0 ; /* 0x000000ff0200720c */
/* 0x000fc80004702670 */
/*0280*/ ISETP.EQ.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fc80000702670 */
/*0290*/ ISETP.EQ.OR P0, PT, R3, R4, P0 ; /* 0x000000040300720c */
/* 0x000fda0000702670 */
/*02a0*/ @P0 BRA 0x720 ; /* 0x0000047000000947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.SHL.U32 R2, R0, 0x8, RZ ; /* 0x0000000800027824 */
/* 0x000fe200078e00ff */
/*02c0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*02d0*/ SHF.L.U64.HI R3, R0, 0x3, R3 ; /* 0x0000000300037819 */
/* 0x000fe40000010203 */
/*02e0*/ IADD3 R24, P0, R2, c[0x0][0x168], RZ ; /* 0x00005a0002187a10 */
/* 0x000fc80007f1e0ff */
/*02f0*/ IADD3.X R25, R3, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003197a10 */
/* 0x000fca00007fe4ff */
/*0300*/ LDG.E.64 R6, [R24.64+0x8] ; /* 0x0000080418067981 */
/* 0x0000a8000c1e1b00 */
/*0310*/ LDG.E.64 R8, [R24.64+-0x8] ; /* 0xfffff80418087981 */
/* 0x0000a2000c1e1b00 */
/*0320*/ IMAD.WIDE R4, R5, 0x8, R24 ; /* 0x0000000805047825 */
/* 0x000fc800078e0218 */
/*0330*/ IMAD.IADD R28, R0.reuse, 0x1, R10 ; /* 0x00000001001c7824 */
/* 0x040fe200078e020a */
/*0340*/ LDG.E.64 R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x0002e2000c1e1b00 */
/*0350*/ IADD3 R20, R0, -c[0x0][0x180], RZ ; /* 0x8000600000147a10 */
/* 0x000fc60007ffe0ff */
/*0360*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000322000c1e1b00 */
/*0370*/ IMAD.WIDE R28, R28, R21, c[0x0][0x168] ; /* 0x00005a001c1c7625 */
/* 0x000fc600078e0215 */
/*0380*/ LDG.E.64 R14, [R4.64+-0x8] ; /* 0xfffff804040e7981 */
/* 0x0002e2000c1e1b00 */
/*0390*/ IMAD.WIDE R20, R20, R21, c[0x0][0x168] ; /* 0x00005a0014147625 */
/* 0x000fc600078e0215 */
/*03a0*/ LDG.E.64 R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x000f68000c1e1b00 */
/*03b0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f68000c1e1b00 */
/*03c0*/ LDG.E.64 R22, [R28.64+0x10] ; /* 0x000010041c167981 */
/* 0x000f68000c1e1b00 */
/*03d0*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x001f62000c1e1b00 */
/*03e0*/ IADD3 R26, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c00021a7a10 */
/* 0x000fc80007f1e0ff */
/*03f0*/ IADD3.X R27, R3, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00031b7a10 */
/* 0x000fcc00007fe4ff */
/*0400*/ LDG.E.64 R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000f62000c1e1b00 */
/*0410*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff047624 */
/* 0x002fe400078e00ff */
/*0420*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff057624 */
/* 0x000fcc00078e00ff */
/*0430*/ DMUL R4, R4, c[0x0][0x188] ; /* 0x0000620004047a28 */
/* 0x000e220000000000 */
/*0440*/ BSSY B0, 0x640 ; /* 0x000001f000007945 */
/* 0x000fe60003800000 */
/*0450*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x0041240000000008 */
/*0460*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e220000001800 */
/*0470*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fc600078e00ff */
/*0480*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x010fc8000000000a */
/*0490*/ DADD R12, R12, R14 ; /* 0x000000000c0c7229 */
/* 0x008f48000000000e */
/*04a0*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e080000000106 */
/*04b0*/ DADD R12, R12, R18 ; /* 0x000000000c0c7229 */
/* 0x020fc80000000012 */
/*04c0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e080000000008 */
/*04d0*/ DADD R10, R10, R20 ; /* 0x000000000a0a7229 */
/* 0x000fc80000000014 */
/*04e0*/ DFMA R6, R6, R8, R6 ; /* 0x000000080606722b */
/* 0x001e080000000006 */
/*04f0*/ DADD R12, R12, R22 ; /* 0x000000000c0c7229 */
/* 0x000e480000000016 */
/*0500*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e080000000106 */
/*0510*/ DFMA R10, R12, 0.25, R10 ; /* 0x3fd000000c0a782b */
/* 0x002e48000000000a */
/*0520*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001fc80000000006 */
/*0530*/ DFMA R6, R24, -5, R10 ; /* 0xc01400001806782b */
/* 0x002e0c000000000a */
/*0540*/ DMUL R10, R6, R8 ; /* 0x00000008060a7228 */
/* 0x001e0c0000000000 */
/*0550*/ DFMA R12, -R4, R10, R6 ; /* 0x0000000a040c722b */
/* 0x001e0c0000000106 */
/*0560*/ DFMA R8, R8, R12, R10 ; /* 0x0000000c0808722b */
/* 0x001062000000000a */
/*0570*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fe20003f2e200 */
/*0580*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0c7624 */
/* 0x001fe400078e00ff */
/*0590*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0d7624 */
/* 0x000fcc00078e00ff */
/*05a0*/ FFMA R0, RZ, R5, R9 ; /* 0x00000005ff007223 */
/* 0x002fca0000000009 */
/*05b0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fe20003f04200 */
/*05c0*/ DADD R14, R24, R24 ; /* 0x00000000180e7229 */
/* 0x000e080000000018 */
/*05d0*/ DMUL R12, R12, c[0x0][0x190] ; /* 0x000064000c0c7a28 */
/* 0x000e480000000000 */
/*05e0*/ DADD R14, R14, -R26 ; /* 0x000000000e0e7229 */
/* 0x001088000000081a */
/*05f0*/ DMUL R12, R12, c[0x2][0x0] ; /* 0x008000000c0c7a28 */
/* 0x002e620000000000 */
/*0600*/ @P0 BRA P1, 0x630 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*0610*/ MOV R0, 0x630 ; /* 0x0000063000007802 */
/* 0x005fca0000000f00 */
/*0620*/ CALL.REL.NOINC 0x740 ; /* 0x0000011000007944 */
/* 0x002fea0003c00000 */
/*0630*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x005fea0003800000 */
/*0640*/ IADD3 R4, P0, R2, c[0x0][0x178], RZ ; /* 0x00005e0002047a10 */
/* 0x000fc80007f1e0ff */
/*0650*/ IADD3.X R5, R3, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0003057a10 */
/* 0x000fcc00007fe4ff */
/*0660*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0670*/ F2F.F32.F64 R0, c[0x0][0x198] ; /* 0x0000660000007b10 */
/* 0x000e240000301000 */
/*0680*/ FMUL R0, R0, -1.4426950216293334961 ; /* 0xbfb8aa3b00007820 */
/* 0x001fca0000400000 */
/*0690*/ FSETP.GEU.AND P0, PT, R0, -126, PT ; /* 0xc2fc00000000780b */
/* 0x000fda0003f0e000 */
/*06a0*/ @!P0 FMUL R0, R0, 0.5 ; /* 0x3f00000000008820 */
/* 0x000fc80000400000 */
/*06b0*/ MUFU.EX2 R6, R0 ; /* 0x0000000000067308 */
/* 0x000e240000000800 */
/*06c0*/ @!P0 FMUL R6, R6, R6 ; /* 0x0000000606068220 */
/* 0x001fcc0000400000 */
/*06d0*/ F2F.F64.F32 R2, R6 ; /* 0x0000000600027310 */
/* 0x000ea40000201800 */
/*06e0*/ DFMA R2, R2, -R4, R8 ; /* 0x800000040202722b */
/* 0x004e0c0000000008 */
/*06f0*/ DFMA R2, R12, R2, R14 ; /* 0x000000020c02722b */
/* 0x003e0e000000000e */
/*0700*/ STG.E.64 [R16.64], R2 ; /* 0x0000000210007986 */
/* 0x001fe2000c101b04 */
/*0710*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0720*/ STG.E.64 [R16.64], RZ ; /* 0x000000ff10007986 */
/* 0x000fe2000c101b04 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ FSETP.GEU.AND P0, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f0e200 */
/*0750*/ IMAD.MOV.U32 R8, RZ, RZ, R4.reuse ; /* 0x000000ffff087224 */
/* 0x100fe200078e0004 */
/*0760*/ LOP3.LUT R10, R5, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff050a7812 */
/* 0x000fe200078ec0ff */
/*0770*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0780*/ FSETP.GEU.AND P2, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f4e200 */
/*0790*/ IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; /* 0x00000001ff167424 */
/* 0x000fe200078e00ff */
/*07a0*/ LOP3.LUT R11, R10, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000a0b7812 */
/* 0x000fe200078efcff */
/*07b0*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0004 */
/*07c0*/ LOP3.LUT R4, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007047812 */
/* 0x000fe200078ec0ff */
/*07d0*/ BSSY B1, 0xcf0 ; /* 0x0000051000017945 */
/* 0x000fe20003800000 */
/*07e0*/ LOP3.LUT R27, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000051b7812 */
/* 0x000fe200078ec0ff */
/*07f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff057424 */
/* 0x000fc400078e00ff */
/*0800*/ @!P0 DMUL R10, R8, 8.98846567431157953865e+307 ; /* 0x7fe00000080a8828 */
/* 0x000e220000000000 */
/*0810*/ ISETP.GE.U32.AND P1, PT, R4, R27, PT ; /* 0x0000001b0400720c */
/* 0x000fc60003f26070 */
/*0820*/ @!P2 LOP3.LUT R21, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000915a812 */
/* 0x000fe200078ec0ff */
/*0830*/ @!P2 IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff18a224 */
/* 0x000fe200078e00ff */
/*0840*/ MUFU.RCP64H R23, R11 ; /* 0x0000000b00177308 */
/* 0x001e240000001800 */
/*0850*/ @!P2 ISETP.GE.U32.AND P3, PT, R4, R21, PT ; /* 0x000000150400a20c */
/* 0x000fe40003f66070 */
/*0860*/ SEL R21, R5.reuse, 0x63400000, !P1 ; /* 0x6340000005157807 */
/* 0x040fe40004800000 */
/*0870*/ @!P2 SEL R25, R5, 0x63400000, !P3 ; /* 0x634000000519a807 */
/* 0x000fe40005800000 */
/*0880*/ @!P0 LOP3.LUT R27, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b1b8812 */
/* 0x000fc400078ec0ff */
/*0890*/ @!P2 LOP3.LUT R25, R25, 0x80000000, R7, 0xf8, !PT ; /* 0x800000001919a812 */
/* 0x000fc800078ef807 */
/*08a0*/ @!P2 LOP3.LUT R25, R25, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001919a812 */
/* 0x000fe200078efcff */
/*08b0*/ DFMA R18, R22, -R10, 1 ; /* 0x3ff000001612742b */
/* 0x001e0c000000080a */
/*08c0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*08d0*/ DFMA R22, R22, R18, R22 ; /* 0x000000121616722b */
/* 0x0010640000000016 */
/*08e0*/ LOP3.LUT R19, R21, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff15137812 */
/* 0x001fe200078ef807 */
/*08f0*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fc600078e0006 */
/*0900*/ DFMA R20, R22, -R10, 1 ; /* 0x3ff000001614742b */
/* 0x002e08000000080a */
/*0910*/ @!P2 DFMA R18, R18, 2, -R24 ; /* 0x400000001212a82b */
/* 0x000fc80000000818 */
/*0920*/ DFMA R20, R22, R20, R22 ; /* 0x000000141614722b */
/* 0x001e0c0000000016 */
/*0930*/ DMUL R22, R20, R18 ; /* 0x0000001214167228 */
/* 0x001e0c0000000000 */
/*0940*/ DFMA R24, R22, -R10, R18 ; /* 0x8000000a1618722b */
/* 0x001e0c0000000012 */
/*0950*/ DFMA R24, R20, R24, R22 ; /* 0x000000181418722b */
/* 0x0010640000000016 */
/*0960*/ IMAD.MOV.U32 R20, RZ, RZ, R4 ; /* 0x000000ffff147224 */
/* 0x001fe200078e0004 */
/*0970*/ @!P2 LOP3.LUT R20, R19, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001314a812 */
/* 0x000fe400078ec0ff */
/*0980*/ IADD3 R22, R27, -0x1, RZ ; /* 0xffffffff1b167810 */
/* 0x000fe40007ffe0ff */
/*0990*/ IADD3 R21, R20, -0x1, RZ ; /* 0xffffffff14157810 */
/* 0x000fc80007ffe0ff */
/*09a0*/ ISETP.GT.U32.AND P0, PT, R21, 0x7feffffe, PT ; /* 0x7feffffe1500780c */
/* 0x000fc80003f04070 */
/*09b0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fda0000704470 */
/*09c0*/ @P0 BRA 0xb90 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*09d0*/ LOP3.LUT R7, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009077812 */
/* 0x002fe200078ec0ff */
/*09e0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fc600078e00ff */
/*09f0*/ ISETP.GE.U32.AND P0, PT, R4.reuse, R7, PT ; /* 0x000000070400720c */
/* 0x040fe20003f06070 */
/*0a00*/ IMAD.IADD R6, R4, 0x1, -R7 ; /* 0x0000000104067824 */
/* 0x000fc600078e0a07 */
/*0a10*/ SEL R5, R5, 0x63400000, !P0 ; /* 0x6340000005057807 */
/* 0x000fe40004000000 */
/*0a20*/ IMNMX R6, R6, -0x46a00000, !PT ; /* 0xb960000006067817 */
/* 0x000fc80007800200 */
/*0a30*/ IMNMX R6, R6, 0x46a00000, PT ; /* 0x46a0000006067817 */
/* 0x000fca0003800200 */
/*0a40*/ IMAD.IADD R6, R6, 0x1, -R5 ; /* 0x0000000106067824 */
/* 0x000fca00078e0a05 */
/*0a50*/ IADD3 R21, R6, 0x7fe00000, RZ ; /* 0x7fe0000006157810 */
/* 0x000fcc0007ffe0ff */
/*0a60*/ DMUL R4, R24, R20 ; /* 0x0000001418047228 */
/* 0x000e140000000000 */
/*0a70*/ FSETP.GTU.AND P0, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x001fda0003f0c200 */
/*0a80*/ @P0 BRA 0xce0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0a90*/ DFMA R10, R24, -R10, R18 ; /* 0x8000000a180a722b */
/* 0x000e220000000012 */
/*0aa0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fd200078e00ff */
/*0ab0*/ FSETP.NEU.AND P0, PT, R11.reuse, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x041fe40003f0d000 */
/*0ac0*/ LOP3.LUT R7, R11, 0x80000000, R9, 0x48, !PT ; /* 0x800000000b077812 */
/* 0x000fc800078e4809 */
/*0ad0*/ LOP3.LUT R21, R7, R21, RZ, 0xfc, !PT ; /* 0x0000001507157212 */
/* 0x000fce00078efcff */
/*0ae0*/ @!P0 BRA 0xce0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0af0*/ IMAD.MOV R9, RZ, RZ, -R6 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a06 */
/*0b00*/ DMUL.RP R20, R24, R20 ; /* 0x0000001418147228 */
/* 0x000e220000008000 */
/*0b10*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fcc00078e00ff */
/*0b20*/ DFMA R8, R4, -R8, R24 ; /* 0x800000080408722b */
/* 0x000e460000000018 */
/*0b30*/ LOP3.LUT R7, R21, R7, RZ, 0x3c, !PT ; /* 0x0000000715077212 */
/* 0x001fc600078e3cff */
/*0b40*/ IADD3 R8, -R6, -0x43300000, RZ ; /* 0xbcd0000006087810 */
/* 0x002fc80007ffe1ff */
/*0b50*/ FSETP.NEU.AND P0, PT, |R9|, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f0d200 */
/*0b60*/ FSEL R4, R20, R4, !P0 ; /* 0x0000000414047208 */
/* 0x000fe40004000000 */
/*0b70*/ FSEL R5, R7, R5, !P0 ; /* 0x0000000507057208 */
/* 0x000fe20004000000 */
/*0b80*/ BRA 0xce0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0b90*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x002e1c0003f08000 */
/*0ba0*/ @P0 BRA 0xcc0 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0bb0*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0bc0*/ @P0 BRA 0xc90 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0bd0*/ ISETP.NE.AND P0, PT, R20, R27, PT ; /* 0x0000001b1400720c */
/* 0x000fe20003f05270 */
/*0be0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*0bf0*/ IMAD.MOV.U32 R5, RZ, RZ, -0x80000 ; /* 0xfff80000ff057424 */
/* 0x000fd400078e00ff */
/*0c00*/ @!P0 BRA 0xce0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0c10*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0c20*/ LOP3.LUT R5, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007057812 */
/* 0x000fe400078e4809 */
/*0c30*/ ISETP.EQ.OR P0, PT, R27, RZ, !P0 ; /* 0x000000ff1b00720c */
/* 0x000fda0004702670 */
/*0c40*/ @P0 LOP3.LUT R6, R5, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000005060812 */
/* 0x000fe200078efcff */
/*0c50*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x000fe400078e00ff */
/*0c60*/ @P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff040224 */
/* 0x000fe400078e00ff */
/*0c70*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0006 */
/*0c80*/ BRA 0xce0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c90*/ LOP3.LUT R5, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009057812 */
/* 0x000fe200078efcff */
/*0ca0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0cb0*/ BRA 0xce0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0cc0*/ LOP3.LUT R5, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007057812 */
/* 0x000fe200078efcff */
/*0cd0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0006 */
/*0ce0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0cf0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*0d00*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fc400078e0005 */
/*0d10*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0d20*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0d30*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff2c004007950 */
/* 0x000fea0003c3ffff */
/*0d40*/ BRA 0xd40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10evolve_GPUPdS_S_S_idddi
.globl _Z10evolve_GPUPdS_S_S_idddi
.p2align 8
.type _Z10evolve_GPUPdS_S_S_idddi,@function
_Z10evolve_GPUPdS_S_S_idddi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x54
s_load_b32 s10, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s10, s10
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_8
s_ashr_i32 s2, s10, 31
v_ashrrev_i32_e32 v4, 31, v1
s_add_i32 s3, s10, s2
s_mov_b32 s9, exec_lo
s_xor_b32 s3, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v1, v4
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s4, 0, s3
v_xor_b32_e32 v5, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v4, s2, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mad_u64_u32 v[2:3], null, v5, v0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v3, s3
v_add_nc_u32_e32 v2, 1, v3
v_sub_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v5, s3, v0
v_cmp_le_u32_e32 vcc_lo, s3, v0
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v0, v0, v5 :: v_dual_add_nc_u32 v3, 1, v2
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v2, v3, vcc_lo
v_xor_b32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v4
v_mul_lo_u32 v2, v0, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v2
v_cmp_eq_u32_e64 s8, 0, v2
v_cmpx_ne_u32_e32 0, v2
s_cbranch_execz .LBB0_5
s_add_i32 s3, s10, -1
v_cmp_ne_u32_e64 s2, 0, v0
v_cmp_ne_u32_e32 vcc_lo, s3, v2
v_cmp_ne_u32_e64 s3, s3, v0
s_mov_b32 s4, -1
s_delay_alu instid0(VALU_DEP_3)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[16:17], s[0:1], 0x18
v_add_nc_u32_e32 v3, s10, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[15:16], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v4, vcc_lo
s_clause 0x3
global_load_b128 v[3:6], v[7:8], off
global_load_b64 v[17:18], v[7:8], off offset:-8
global_load_b128 v[7:10], v[11:12], off
global_load_b64 v[19:20], v[11:12], off offset:-8
v_subrev_nc_u32_e32 v11, s10, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 3, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
s_clause 0x1
global_load_b64 v[21:22], v[11:12], off offset:-8
global_load_b128 v[11:14], v[11:12], off
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x28
s_load_b64 s[4:5], s[0:1], 0x38
s_waitcnt lgkmcnt(0)
v_cvt_f32_f64_e32 v0, s[4:5]
s_mov_b32 s5, 0x3fb99999
s_mov_b32 s4, 0x9999999a
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, 0xbfb8aa3b, v0
v_exp_f32_e32 v0, v0
s_waitcnt vmcnt(4)
v_add_f64 v[5:6], v[17:18], v[5:6]
s_waitcnt vmcnt(2)
v_add_f64 v[9:10], v[19:20], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[7:8]
s_waitcnt vmcnt(1)
v_add_f64 v[7:8], v[9:10], v[21:22]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[11:12]
v_add_f64 v[7:8], v[7:8], v[13:14]
v_add_co_u32 v13, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, s16, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s17, v16, vcc_lo
global_load_b64 v[13:14], v[13:14], off
global_load_b64 v[15:16], v[15:16], off
v_fma_f64 v[5:6], v[7:8], 0x3fd00000, v[5:6]
v_mul_f64 v[7:8], s[12:13], s[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[3:4], 0xc0140000, v[5:6]
v_div_scale_f64 v[9:10], null, v[7:8], v[7:8], v[5:6]
v_div_scale_f64 v[19:20], vcc_lo, v[5:6], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[11:12], v[9:10]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[17:18], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[9:10], v[11:12], 1.0
v_fma_f64 v[11:12], v[11:12], v[17:18], v[11:12]
s_waitcnt vmcnt(1)
v_fma_f64 v[3:4], v[3:4], 2.0, -v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[19:20], v[11:12]
v_fma_f64 v[9:10], -v[9:10], v[17:18], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[17:18]
v_mul_f64 v[11:12], s[14:15], s[14:15]
v_div_fixup_f64 v[5:6], v[9:10], v[7:8], v[5:6]
v_cvt_f64_f32_e32 v[7:8], v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f64 v[9:10], v[11:12], s[4:5]
s_xor_b32 s4, exec_lo, -1
s_waitcnt vmcnt(0)
v_fma_f64 v[5:6], -v[15:16], v[7:8], v[5:6]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[3:4], v[9:10], v[5:6], v[3:4]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s8, exec_lo
s_and_b32 s3, s4, exec_lo
s_or_b32 s8, s2, s3
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s2, s8
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
v_ashrrev_i32_e32 v2, 31, v1
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10evolve_GPUPdS_S_S_idddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 328
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10evolve_GPUPdS_S_S_idddi, .Lfunc_end0-_Z10evolve_GPUPdS_S_S_idddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: hidden_block_count_x
- .offset: 76
.size: 4
.value_kind: hidden_block_count_y
- .offset: 80
.size: 4
.value_kind: hidden_block_count_z
- .offset: 84
.size: 2
.value_kind: hidden_group_size_x
- .offset: 86
.size: 2
.value_kind: hidden_group_size_y
- .offset: 88
.size: 2
.value_kind: hidden_group_size_z
- .offset: 90
.size: 2
.value_kind: hidden_remainder_x
- .offset: 92
.size: 2
.value_kind: hidden_remainder_y
- .offset: 94
.size: 2
.value_kind: hidden_remainder_z
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 136
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 328
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10evolve_GPUPdS_S_S_idddi
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10evolve_GPUPdS_S_S_idddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00062ed2_00000000-6_lakegpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z10evolve_GPUPdS_S_S_idddiPdS_S_S_idddi
.type _Z41__device_stub__Z10evolve_GPUPdS_S_S_idddiPdS_S_S_idddi, @function
_Z41__device_stub__Z10evolve_GPUPdS_S_S_idddiPdS_S_S_idddi:
.LFB2084:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movsd %xmm2, (%rsp)
movl %r9d, 24(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z10evolve_GPUPdS_S_S_idddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z41__device_stub__Z10evolve_GPUPdS_S_S_idddiPdS_S_S_idddi, .-_Z41__device_stub__Z10evolve_GPUPdS_S_S_idddiPdS_S_S_idddi
.globl _Z10evolve_GPUPdS_S_S_idddi
.type _Z10evolve_GPUPdS_S_S_idddi, @function
_Z10evolve_GPUPdS_S_S_idddi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z10evolve_GPUPdS_S_S_idddiPdS_S_S_idddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10evolve_GPUPdS_S_S_idddi, .-_Z10evolve_GPUPdS_S_S_idddi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/majetyhk/ParallelProgramming/master/HW2/p3/V2/lakegpu.cu"
.align 8
.LC3:
.string "cudaSafeCall() failed at %s:%i : %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPU computation: %f msec\n"
.text
.globl _Z7run_gpuPdS_S_S_iddi
.type _Z7run_gpuPdS_S_S_iddi, @function
_Z7run_gpuPdS_S_S_iddi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, %rbp
movl %r8d, 28(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 16(%rsp)
movl %r9d, %r15d
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movslq %r8d, %rbx
imulq %rbx, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, 40(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 48(%rsp)
movq %rbx, %rcx
movq %rbx, %rdx
movq %r13, %rsi
movq %rax, %rdi
call __memcpy_chk@PLT
movq %rbx, %rcx
movq %rbx, %rdx
movq %r12, %rsi
movq %r14, %rdi
call __memcpy_chk@PLT
movq $0x000000000, 120(%rsp)
movsd 32(%rsp), %xmm3
mulsd .LC1(%rip), %xmm3
movsd %xmm3, 8(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L39
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L40
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L41
movl %r15d, %r14d
imull %r15d, %r14d
movl 28(%rsp), %eax
cltd
idivl %r15d
movl %eax, %r12d
imull %eax, %r12d
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L42
leaq 104(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L43
leaq 96(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L44
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L45
leaq 112(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L46
movl $1, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L47
movl $1, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L37
leaq 120(%rsp), %r13
jmp .L22
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $128, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $129, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $130, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $140, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $144, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $145, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $146, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L46:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $147, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $150, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $151, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $152, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L23:
movq 104(%rsp), %rbp
movq 96(%rsp), %rax
movq %rax, 104(%rsp)
movq 88(%rsp), %rax
movq %rax, 96(%rsp)
movsd 16(%rsp), %xmm1
movsd 8(%rsp), %xmm0
movq %r13, %rdi
call _Z4tpdtPddd@PLT
testl %eax, %eax
je .L24
movq %rbp, 88(%rsp)
.L22:
movl %r14d, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl %r12d, 128(%rsp)
movl $1, 132(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L23
movl %r15d, %r9d
movsd 120(%rsp), %xmm2
movsd 8(%rsp), %xmm1
movsd 32(%rsp), %xmm0
movl 28(%rsp), %r8d
movq 112(%rsp), %rcx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z41__device_stub__Z10evolve_GPUPdS_S_S_idddiPdS_S_S_idddi
jmp .L23
.L24:
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L49
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L50
leaq 140(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L51
pxor %xmm0, %xmm0
cvtss2sd 140(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L52
movq 96(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L53
movq %rbp, %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L54
movq 112(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L55
movq 40(%rsp), %rdi
call free@PLT
movq 48(%rsp), %rdi
call free@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L56
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L57
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L58
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $175, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $176, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $177, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $181, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $182, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $183, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $184, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $188, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $189, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $190, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z7run_gpuPdS_S_S_iddi, .-_Z7run_gpuPdS_S_S_iddi
.section .rodata.str1.1
.LC5:
.string "_Z10evolve_GPUPdS_S_S_idddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10evolve_GPUPdS_S_S_idddi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lakegpu.hip"
.globl _Z25__device_stub__evolve_GPUPdS_S_S_idddi # -- Begin function _Z25__device_stub__evolve_GPUPdS_S_S_idddi
.p2align 4, 0x90
.type _Z25__device_stub__evolve_GPUPdS_S_S_idddi,@function
_Z25__device_stub__evolve_GPUPdS_S_S_idddi: # @_Z25__device_stub__evolve_GPUPdS_S_S_idddi
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r8d, 4(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
movl %r9d, (%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rax
movq %rax, 168(%rsp)
movq %rsp, %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10evolve_GPUPdS_S_S_idddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z25__device_stub__evolve_GPUPdS_S_S_idddi, .Lfunc_end0-_Z25__device_stub__evolve_GPUPdS_S_S_idddi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7run_gpuPdS_S_S_iddi
.LCPI1_0:
.quad 0x3fe0000000000000 # double 0.5
.text
.globl _Z7run_gpuPdS_S_S_iddi
.p2align 4, 0x90
.type _Z7run_gpuPdS_S_S_iddi,@function
_Z7run_gpuPdS_S_S_iddi: # @_Z7run_gpuPdS_S_S_iddi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, 4(%rsp) # 4-byte Spill
movsd %xmm1, 128(%rsp) # 8-byte Spill
movsd %xmm0, 72(%rsp) # 8-byte Spill
movq %rcx, %r12
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, 120(%rsp) # 8-byte Spill
movl %r8d, 28(%rsp) # 4-byte Spill
movslq %r8d, %r15
imulq %r15, %r15
shlq $3, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r13
movq %r15, %rdi
callq malloc
movq %rax, %rbp
movq %rax, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
movq %r13, %rdi
movq %rbx, %rsi
movq %r15, %rdx
callq memcpy@PLT
movq $0, 88(%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_1
# %bb.3: # %_Z14__cudaSafeCall10hipError_tPKci.exit
leaq 56(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_4
# %bb.5: # %_Z14__cudaSafeCall10hipError_tPKci.exit54
leaq 40(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
movl 28(%rsp), %r14d # 4-byte Reload
jne .LBB1_6
# %bb.7: # %_Z14__cudaSafeCall10hipError_tPKci.exit56
movl %r14d, %eax
cltd
idivl 4(%rsp) # 4-byte Folded Reload
movl %eax, %ebx
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z14__cudaSafeCall10hipError_tPKci.exit58
# kill: def $r14d killed $r14d def $r14
imull %r14d, %r14d
shlq $3, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z14__cudaSafeCall10hipError_tPKci.exit60
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_Z14__cudaSafeCall10hipError_tPKci.exit62
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_14
# %bb.15: # %_Z14__cudaSafeCall10hipError_tPKci.exit64
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z14__cudaSafeCall10hipError_tPKci.exit66
movq 8(%rsp), %rdi
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_18
# %bb.19: # %_Z14__cudaSafeCall10hipError_tPKci.exit68
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_20
# %bb.21: # %_Z14__cudaSafeCall10hipError_tPKci.exit70
movq %rbp, 96(%rsp) # 8-byte Spill
movq %r13, 104(%rsp) # 8-byte Spill
movq 48(%rsp), %rdi
movq %r12, %rsi
movq %r14, 112(%rsp) # 8-byte Spill
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_48
# %bb.22: # %_Z14__cudaSafeCall10hipError_tPKci.exit72.preheader
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
mulsd 72(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 80(%rsp) # 8-byte Spill
movl 4(%rsp), %eax # 4-byte Reload
imull %eax, %eax
imull %ebx, %ebx
movl %ebx, %ebx
movabsq $4294967296, %rcx # imm = 0x100000000
orq %rcx, %rbx
movl %eax, %r12d
orq %rcx, %r12
leaq 136(%rsp), %rbp
leaq 240(%rsp), %r15
leaq 88(%rsp), %r13
.p2align 4, 0x90
.LBB1_23: # %_Z14__cudaSafeCall10hipError_tPKci.exit72
# =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_25
# %bb.24: # in Loop: Header=BB1_23 Depth=1
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq 48(%rsp), %rsi
movsd 88(%rsp), %xmm0 # xmm0 = mem[0],zero
movq %rax, 232(%rsp)
movq %rcx, 224(%rsp)
movq %rdx, 216(%rsp)
movq %rsi, 208(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 68(%rsp)
movsd 72(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movsd %xmm1, 200(%rsp)
movsd 80(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movsd %xmm1, 192(%rsp)
movsd %xmm0, 184(%rsp)
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, 64(%rsp)
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 208(%rsp), %rax
movq %rax, 264(%rsp)
leaq 68(%rsp), %rax
movq %rax, 272(%rsp)
leaq 200(%rsp), %rax
movq %rax, 280(%rsp)
leaq 192(%rsp), %rax
movq %rax, 288(%rsp)
leaq 184(%rsp), %rax
movq %rax, 296(%rsp)
leaq 64(%rsp), %rax
movq %rax, 304(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
movl $_Z10evolve_GPUPdS_S_S_idddi, %edi
movq %r15, %r9
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_25: # in Loop: Header=BB1_23 Depth=1
movq 8(%rsp), %r14
movq 16(%rsp), %rax
movq %rax, 8(%rsp)
movq 32(%rsp), %rax
movq %rax, 16(%rsp)
movq %r13, %rdi
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 128(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
callq _Z4tpdtPddd
testl %eax, %eax
je .LBB1_27
# %bb.26: # in Loop: Header=BB1_23 Depth=1
movq %r14, 32(%rsp)
jmp .LBB1_23
.LBB1_27:
movq 32(%rsp), %rsi
movq 120(%rsp), %rdi # 8-byte Reload
movq 112(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_28
# %bb.29: # %_Z14__cudaSafeCall10hipError_tPKci.exit74
movq 40(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
movq 104(%rsp), %rbx # 8-byte Reload
movq 96(%rsp), %r15 # 8-byte Reload
jne .LBB1_30
# %bb.31: # %_Z14__cudaSafeCall10hipError_tPKci.exit76
movq 56(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 240(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_32
# %bb.33: # %_Z14__cudaSafeCall10hipError_tPKci.exit78
movss 240(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_34
# %bb.35: # %_Z14__cudaSafeCall10hipError_tPKci.exit80
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_36
# %bb.37: # %_Z14__cudaSafeCall10hipError_tPKci.exit82
movq %r14, %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_38
# %bb.39: # %_Z14__cudaSafeCall10hipError_tPKci.exit84
movq 48(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_40
# %bb.41: # %_Z14__cudaSafeCall10hipError_tPKci.exit86
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq 56(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_42
# %bb.43: # %_Z14__cudaSafeCall10hipError_tPKci.exit88
movq 40(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_44
# %bb.45: # %_Z14__cudaSafeCall10hipError_tPKci.exit90
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_46
# %bb.47: # %_Z14__cudaSafeCall10hipError_tPKci.exit92
addq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 368
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $128, %ecx
jmp .LBB1_2
.LBB1_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $129, %ecx
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $130, %ecx
jmp .LBB1_2
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $140, %ecx
jmp .LBB1_2
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $144, %ecx
jmp .LBB1_2
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $145, %ecx
jmp .LBB1_2
.LBB1_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $146, %ecx
jmp .LBB1_2
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $147, %ecx
jmp .LBB1_2
.LBB1_18:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $150, %ecx
jmp .LBB1_2
.LBB1_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $151, %ecx
jmp .LBB1_2
.LBB1_48:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $152, %ecx
jmp .LBB1_2
.LBB1_28:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $175, %ecx
jmp .LBB1_2
.LBB1_30:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $176, %ecx
jmp .LBB1_2
.LBB1_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $177, %ecx
jmp .LBB1_2
.LBB1_34:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $181, %ecx
jmp .LBB1_2
.LBB1_36:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $182, %ecx
jmp .LBB1_2
.LBB1_38:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $183, %ecx
jmp .LBB1_2
.LBB1_40:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $184, %ecx
jmp .LBB1_2
.LBB1_42:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $188, %ecx
jmp .LBB1_2
.LBB1_44:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $189, %ecx
jmp .LBB1_2
.LBB1_46:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movl $.L.str, %edx
movq %rbx, %rdi
movl $190, %ecx
.LBB1_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size _Z7run_gpuPdS_S_S_iddi, .Lfunc_end1-_Z7run_gpuPdS_S_S_iddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10evolve_GPUPdS_S_S_idddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10evolve_GPUPdS_S_S_idddi,@object # @_Z10evolve_GPUPdS_S_S_idddi
.section .rodata,"a",@progbits
.globl _Z10evolve_GPUPdS_S_S_idddi
.p2align 3, 0x0
_Z10evolve_GPUPdS_S_S_idddi:
.quad _Z25__device_stub__evolve_GPUPdS_S_S_idddi
.size _Z10evolve_GPUPdS_S_S_idddi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/majetyhk/ParallelProgramming/master/HW2/p3/V2/lakegpu.hip"
.size .L.str, 115
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU computation: %f msec\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "cudaSafeCall() failed at %s:%i : %s\n"
.size .L.str.2, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10evolve_GPUPdS_S_S_idddi"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__evolve_GPUPdS_S_S_idddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10evolve_GPUPdS_S_S_idddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int i = blockIdx.x*64 + tx;
int j = blockIdx.y*2;
__shared__ float cb0[32], cb1[32];
float sum0 = 0.0, sum1 = 0., sum2 = 0.0, sum3 = 0.0;
for( int ks = 0; ks < p; ks += 32 ){
cb0[tx] = c[ks+tx+pitch_c*j];
cb1[tx] = c[ks+tx+pitch_c*(j+1)];
__syncthreads();
for( int k = ks; k < ks+32; ++k ){
float rb0 = b[i+pitch_b*k];
float rb1 = b[i+32+pitch_b*k];
sum0 += rb0 * cb0[k - ks];
sum1 += rb0 * cb1[k - ks];
sum2 += rb1*cb0[k - ks];
sum3 += rb1*cb1[k - ks];
}
__syncthreads();
}
a[i+pitch_a*j] = sum0;
a[i+pitch_a*(j+1)] = sum1;
a[i+32+pitch_a*j] = sum2;
a[i+32+pitch_a*(j+1)] = sum3;
} | .file "tmpxft_00179a46_00000000-6_k5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
.type _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq mmkernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii, .-_Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
.globl mmkernel
.type mmkernel, @function
mmkernel:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size mmkernel, .-mmkernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "mmkernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq mmkernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int i = blockIdx.x*64 + tx;
int j = blockIdx.y*2;
__shared__ float cb0[32], cb1[32];
float sum0 = 0.0, sum1 = 0., sum2 = 0.0, sum3 = 0.0;
for( int ks = 0; ks < p; ks += 32 ){
cb0[tx] = c[ks+tx+pitch_c*j];
cb1[tx] = c[ks+tx+pitch_c*(j+1)];
__syncthreads();
for( int k = ks; k < ks+32; ++k ){
float rb0 = b[i+pitch_b*k];
float rb1 = b[i+32+pitch_b*k];
sum0 += rb0 * cb0[k - ks];
sum1 += rb0 * cb1[k - ks];
sum2 += rb1*cb0[k - ks];
sum3 += rb1*cb1[k - ks];
}
__syncthreads();
}
a[i+pitch_a*j] = sum0;
a[i+pitch_a*(j+1)] = sum1;
a[i+32+pitch_a*j] = sum2;
a[i+32+pitch_a*(j+1)] = sum3;
} | #include <hip/hip_runtime.h>
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int i = blockIdx.x*64 + tx;
int j = blockIdx.y*2;
__shared__ float cb0[32], cb1[32];
float sum0 = 0.0, sum1 = 0., sum2 = 0.0, sum3 = 0.0;
for( int ks = 0; ks < p; ks += 32 ){
cb0[tx] = c[ks+tx+pitch_c*j];
cb1[tx] = c[ks+tx+pitch_c*(j+1)];
__syncthreads();
for( int k = ks; k < ks+32; ++k ){
float rb0 = b[i+pitch_b*k];
float rb1 = b[i+32+pitch_b*k];
sum0 += rb0 * cb0[k - ks];
sum1 += rb0 * cb1[k - ks];
sum2 += rb1*cb0[k - ks];
sum3 += rb1*cb1[k - ks];
}
__syncthreads();
}
a[i+pitch_a*j] = sum0;
a[i+pitch_a*(j+1)] = sum1;
a[i+32+pitch_a*j] = sum2;
a[i+32+pitch_a*(j+1)] = sum3;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int i = blockIdx.x*64 + tx;
int j = blockIdx.y*2;
__shared__ float cb0[32], cb1[32];
float sum0 = 0.0, sum1 = 0., sum2 = 0.0, sum3 = 0.0;
for( int ks = 0; ks < p; ks += 32 ){
cb0[tx] = c[ks+tx+pitch_c*j];
cb1[tx] = c[ks+tx+pitch_c*(j+1)];
__syncthreads();
for( int k = ks; k < ks+32; ++k ){
float rb0 = b[i+pitch_b*k];
float rb1 = b[i+32+pitch_b*k];
sum0 += rb0 * cb0[k - ks];
sum1 += rb0 * cb1[k - ks];
sum2 += rb1*cb0[k - ks];
sum3 += rb1*cb1[k - ks];
}
__syncthreads();
}
a[i+pitch_a*j] = sum0;
a[i+pitch_a*(j+1)] = sum1;
a[i+32+pitch_a*j] = sum2;
a[i+32+pitch_a*(j+1)] = sum3;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected mmkernel
.globl mmkernel
.p2align 8
.type mmkernel,@function
mmkernel:
s_load_b32 s9, s[0:1], 0x2c
v_lshl_add_u32 v6, s14, 6, v0
s_lshl_b32 s8, s15, 1
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x8
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v8, 2, v0
v_dual_mov_b32 v9, v6 :: v_dual_mov_b32 v4, 0
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v10, 0x80, v8
v_mov_b32_e32 v7, 0
s_or_b32 s12, s8, 1
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s8, s3
s_mul_i32 s3, s12, s3
s_lshl_b32 s12, s2, 5
.LBB0_2:
v_add_nc_u32_e32 v2, s10, v0
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, s11, v2
v_add_nc_u32_e32 v11, s3, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
s_clause 0x1
global_load_b32 v2, v[1:2], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v1, v9
s_waitcnt vmcnt(1)
ds_store_b32 v8, v2
s_waitcnt vmcnt(0)
ds_store_b32 v10, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.p2align 6
.LBB0_3:
v_add_nc_u32_e32 v11, 32, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[13:14], 2, v[1:2]
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v13, vcc_lo, s4, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
s_clause 0x1
global_load_b32 v2, v[13:14], off
global_load_b32 v13, v[11:12], off
v_mov_b32_e32 v11, s13
s_add_i32 s13, s13, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s13, 0x80
ds_load_2addr_b32 v[11:12], v11 offset1:32
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_fmac_f32 v3, v2, v11 :: v_dual_fmac_f32 v4, v13, v12
v_fmac_f32_e32 v5, v2, v12
v_fmac_f32_e32 v7, v13, v11
s_cbranch_scc0 .LBB0_3
v_add_nc_u32_e32 v9, s12, v9
s_add_i32 s10, s10, 32
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s10, s9
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_6
.LBB0_5:
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v7, 0
.LBB0_6:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x0
s_or_b32 s3, s8, 1
v_add_nc_u32_e32 v1, 32, v6
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s8, s2
s_mul_i32 s3, s3, s2
v_add_nc_u32_e32 v0, s8, v6
v_add_nc_u32_e32 v8, s3, v6
v_add_nc_u32_e32 v10, s8, v1
v_add_nc_u32_e32 v12, s3, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v11, 31, v10
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s1, v13, vcc_lo
s_clause 0x3
global_store_b32 v[0:1], v3, off
global_store_b32 v[8:9], v5, off
global_store_b32 v[10:11], v7, off
global_store_b32 v[12:13], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel mmkernel
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size mmkernel, .Lfunc_end0-mmkernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: mmkernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: mmkernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __global__ void
mmkernel( float* a, float* b, float* c,
int pitch_a, int pitch_b, int pitch_c,
int n, int m, int p )
{
int tx = threadIdx.x;
int i = blockIdx.x*64 + tx;
int j = blockIdx.y*2;
__shared__ float cb0[32], cb1[32];
float sum0 = 0.0, sum1 = 0., sum2 = 0.0, sum3 = 0.0;
for( int ks = 0; ks < p; ks += 32 ){
cb0[tx] = c[ks+tx+pitch_c*j];
cb1[tx] = c[ks+tx+pitch_c*(j+1)];
__syncthreads();
for( int k = ks; k < ks+32; ++k ){
float rb0 = b[i+pitch_b*k];
float rb1 = b[i+32+pitch_b*k];
sum0 += rb0 * cb0[k - ks];
sum1 += rb0 * cb1[k - ks];
sum2 += rb1*cb0[k - ks];
sum3 += rb1*cb1[k - ks];
}
__syncthreads();
}
a[i+pitch_a*j] = sum0;
a[i+pitch_a*(j+1)] = sum1;
a[i+32+pitch_a*j] = sum2;
a[i+32+pitch_a*(j+1)] = sum3;
} | .text
.file "k5.hip"
.globl __device_stub__mmkernel # -- Begin function __device_stub__mmkernel
.p2align 4, 0x90
.type __device_stub__mmkernel,@function
__device_stub__mmkernel: # @__device_stub__mmkernel
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $mmkernel, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__mmkernel, .Lfunc_end0-__device_stub__mmkernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mmkernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type mmkernel,@object # @mmkernel
.section .rodata,"a",@progbits
.globl mmkernel
.p2align 3, 0x0
mmkernel:
.quad __device_stub__mmkernel
.size mmkernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "mmkernel"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__mmkernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mmkernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00179a46_00000000-6_k5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
.type _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii, @function
_Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq mmkernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii, .-_Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
.globl mmkernel
.type mmkernel, @function
mmkernel:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z37__device_stub__Z8mmkernelPfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size mmkernel, .-mmkernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "mmkernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq mmkernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "k5.hip"
.globl __device_stub__mmkernel # -- Begin function __device_stub__mmkernel
.p2align 4, 0x90
.type __device_stub__mmkernel,@function
__device_stub__mmkernel: # @__device_stub__mmkernel
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $mmkernel, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__mmkernel, .Lfunc_end0-__device_stub__mmkernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mmkernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type mmkernel,@object # @mmkernel
.section .rodata,"a",@progbits
.globl mmkernel
.p2align 3, 0x0
mmkernel:
.quad __device_stub__mmkernel
.size mmkernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "mmkernel"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__mmkernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mmkernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void square_i32 (int* vector, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = vector[idx] * vector[idx];
}
} | code for sm_80
Function : _Z10square_i32PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD R7, R2, R2, RZ ; /* 0x0000000202077224 */
/* 0x004fca00078e02ff */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void square_i32 (int* vector, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = vector[idx] * vector[idx];
}
} | .file "tmpxft_000fc9c7_00000000-6_square_i32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10square_i32PiS_iPiS_i
.type _Z33__device_stub__Z10square_i32PiS_iPiS_i, @function
_Z33__device_stub__Z10square_i32PiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10square_i32PiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10square_i32PiS_iPiS_i, .-_Z33__device_stub__Z10square_i32PiS_iPiS_i
.globl _Z10square_i32PiS_i
.type _Z10square_i32PiS_i, @function
_Z10square_i32PiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10square_i32PiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10square_i32PiS_i, .-_Z10square_i32PiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10square_i32PiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10square_i32PiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void square_i32 (int* vector, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = vector[idx] * vector[idx];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square_i32 (int* vector, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = vector[idx] * vector[idx];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square_i32 (int* vector, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = vector[idx] * vector[idx];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10square_i32PiS_i
.globl _Z10square_i32PiS_i
.p2align 8
.type _Z10square_i32PiS_i,@function
_Z10square_i32PiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10square_i32PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10square_i32PiS_i, .Lfunc_end0-_Z10square_i32PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10square_i32PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10square_i32PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void square_i32 (int* vector, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = vector[idx] * vector[idx];
}
} | .text
.file "square_i32.hip"
.globl _Z25__device_stub__square_i32PiS_i # -- Begin function _Z25__device_stub__square_i32PiS_i
.p2align 4, 0x90
.type _Z25__device_stub__square_i32PiS_i,@function
_Z25__device_stub__square_i32PiS_i: # @_Z25__device_stub__square_i32PiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10square_i32PiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__square_i32PiS_i, .Lfunc_end0-_Z25__device_stub__square_i32PiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10square_i32PiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10square_i32PiS_i,@object # @_Z10square_i32PiS_i
.section .rodata,"a",@progbits
.globl _Z10square_i32PiS_i
.p2align 3, 0x0
_Z10square_i32PiS_i:
.quad _Z25__device_stub__square_i32PiS_i
.size _Z10square_i32PiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10square_i32PiS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__square_i32PiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10square_i32PiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10square_i32PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD R7, R2, R2, RZ ; /* 0x0000000202077224 */
/* 0x004fca00078e02ff */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10square_i32PiS_i
.globl _Z10square_i32PiS_i
.p2align 8
.type _Z10square_i32PiS_i,@function
_Z10square_i32PiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10square_i32PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10square_i32PiS_i, .Lfunc_end0-_Z10square_i32PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10square_i32PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10square_i32PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fc9c7_00000000-6_square_i32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10square_i32PiS_iPiS_i
.type _Z33__device_stub__Z10square_i32PiS_iPiS_i, @function
_Z33__device_stub__Z10square_i32PiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10square_i32PiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10square_i32PiS_iPiS_i, .-_Z33__device_stub__Z10square_i32PiS_iPiS_i
.globl _Z10square_i32PiS_i
.type _Z10square_i32PiS_i, @function
_Z10square_i32PiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10square_i32PiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10square_i32PiS_i, .-_Z10square_i32PiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10square_i32PiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10square_i32PiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "square_i32.hip"
.globl _Z25__device_stub__square_i32PiS_i # -- Begin function _Z25__device_stub__square_i32PiS_i
.p2align 4, 0x90
.type _Z25__device_stub__square_i32PiS_i,@function
_Z25__device_stub__square_i32PiS_i: # @_Z25__device_stub__square_i32PiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10square_i32PiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__square_i32PiS_i, .Lfunc_end0-_Z25__device_stub__square_i32PiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10square_i32PiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10square_i32PiS_i,@object # @_Z10square_i32PiS_i
.section .rodata,"a",@progbits
.globl _Z10square_i32PiS_i
.p2align 3, 0x0
_Z10square_i32PiS_i:
.quad _Z25__device_stub__square_i32PiS_i
.size _Z10square_i32PiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10square_i32PiS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__square_i32PiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10square_i32PiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void calcCDFnormalized(const unsigned int *histo, float *cdf, size_t width, size_t height) {
for (int i = 0; i <= threadIdx.x; i++) {
cdf[threadIdx.x] += (float) histo[i];
}
cdf[threadIdx.x] *= 1.0f / float((width * height));
} | code for sm_80
Function : _Z17calcCDFnormalizedPKjPfmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x420 ; /* 0x000003d000007945 */
/* 0x000fe20003800000 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R15.reuse, 0x3, PT ; /* 0x000000030f00780c */
/* 0x041fe20003f06070 */
/*0060*/ IMAD.WIDE.U32 R2, R15.reuse, R4, c[0x0][0x168] ; /* 0x00005a000f027625 */
/* 0x040fe200078e0004 */
/*0070*/ IADD3 R0, R15, 0x1, RZ ; /* 0x000000010f007810 */
/* 0x000fc80007ffe0ff */
/*0080*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fce00078ec0ff */
/*0090*/ @!P0 BRA 0x3f0 ; /* 0x0000035000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ LDG.E R5, [R2.64] ; /* 0x0000000c02057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fca00078e00ff */
/*00d0*/ LDG.E R8, [R6.64] ; /* 0x0000000c06087981 */
/* 0x000ee4000c1e1900 */
/*00e0*/ I2F.U32 R8, R8 ; /* 0x0000000800087306 */
/* 0x008ea40000201000 */
/*00f0*/ FADD R5, R5, R8 ; /* 0x0000000805057221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c10190c */
/*0110*/ LDG.E R9, [R6.64+0x4] ; /* 0x0000040c06097981 */
/* 0x000ea4000c1e1900 */
/*0120*/ I2F.U32 R10, R9 ; /* 0x00000009000a7306 */
/* 0x004e240000201000 */
/*0130*/ FADD R11, R5, R10 ; /* 0x0000000a050b7221 */
/* 0x001fca0000000000 */
/*0140*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c10190c */
/*0150*/ LDG.E R10, [R6.64+0x8] ; /* 0x0000080c060a7981 */
/* 0x000ea4000c1e1900 */
/*0160*/ I2F.U32 R10, R10 ; /* 0x0000000a000a7306 */
/* 0x004e640000201000 */
/*0170*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x002fca0000000000 */
/*0180*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c10190c */
/*0190*/ LDG.E R8, [R6.64+0xc] ; /* 0x00000c0c06087981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff097624 */
/* 0x000fe200078e00ff */
/*01b0*/ BSSY B1, 0x3e0 ; /* 0x0000022000017945 */
/* 0x000fe80003800000 */
/*01c0*/ IADD3 R11, P1, R9, 0x10, RZ ; /* 0x00000010090b7810 */
/* 0x001fe20007f3e0ff */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.X R10, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0a7624 */
/* 0x000fe200008e06ff */
/*01f0*/ I2F.U32 R8, R8 ; /* 0x0000000800087306 */
/* 0x004e240000201000 */
/*0200*/ FADD R5, R13, R8 ; /* 0x000000080d057221 */
/* 0x001fe20000000000 */
/*0210*/ IADD3 R8, R15, -0x4, -R0 ; /* 0xfffffffc0f087810 */
/* 0x000fc80007ffe800 */
/*0220*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0003e2000c10190c */
/*0230*/ ISETP.NE.AND P0, PT, R8, -0x1, PT ; /* 0xffffffff0800780c */
/* 0x000fda0003f05270 */
/*0240*/ @!P0 BRA 0x3d0 ; /* 0x0000018000008947 */
/* 0x002fea0003800000 */
/*0250*/ MOV R6, R11 ; /* 0x0000000b00067202 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fca00078e000a */
/*0270*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*0280*/ I2F.U32 R10, R10 ; /* 0x0000000a000a7306 */
/* 0x004e240000201000 */
/*0290*/ FADD R5, R10, R5 ; /* 0x000000050a057221 */
/* 0x003fca0000000000 */
/*02a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e8000c10190c */
/*02b0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ I2F.U32 R12, R11 ; /* 0x0000000b000c7306 */
/* 0x004e640000201000 */
/*02d0*/ FADD R13, R5, R12 ; /* 0x0000000c050d7221 */
/* 0x002fca0000000000 */
/*02e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c10190c */
/*02f0*/ LDG.E R12, [R6.64+0x8] ; /* 0x0000080c060c7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ I2F.U32 R12, R12 ; /* 0x0000000c000c7306 */
/* 0x004ea40000201000 */
/*0310*/ FADD R15, R13, R12 ; /* 0x0000000c0d0f7221 */
/* 0x004fca0000000000 */
/*0320*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c10190c */
/*0330*/ LDG.E R10, [R6.64+0xc] ; /* 0x00000c0c060a7981 */
/* 0x000ea2000c1e1900 */
/*0340*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R11, P1, R6, 0x10, RZ ; /* 0x00000010060b7810 */
/* 0x000fe40007f3e0ff */
/*0360*/ ISETP.NE.AND P0, PT, R8, -0x1, PT ; /* 0xffffffff0800780c */
/* 0x000fe40003f05270 */
/*0370*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007ffe0ff */
/*0380*/ I2F.U32 R10, R10 ; /* 0x0000000a000a7306 */
/* 0x004e240000201000 */
/*0390*/ FADD R5, R15, R10 ; /* 0x0000000a0f057221 */
/* 0x001fc40000000000 */
/*03a0*/ IMAD.X R10, RZ, RZ, R7, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fc600008e0607 */
/*03b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0003e6000c10190c */
/*03c0*/ @P0 BRA 0x250 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*03d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x410 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*03f0*/ LDG.E R5, [R2.64] ; /* 0x0000000c02057981 */
/* 0x000162000c1e1900 */
/*0400*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc600078e00ff */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0430*/ BSSY B0, 0x500 ; /* 0x000000c000007945 */
/* 0x000fd80003800000 */
/*0440*/ @!P0 BRA 0x4f0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0450*/ IMAD.WIDE R6, R9, R4, c[0x0][0x160] ; /* 0x0000580009067625 */
/* 0x000fca00078e0204 */
/*0460*/ LDG.E R4, [R6.64] ; /* 0x0000000c06047981 */
/* 0x0004e2000c1e1900 */
/*0470*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0480*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0490*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x004fca0007f3e0ff */
/*04a0*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*04b0*/ I2F.U32 R4, R4 ; /* 0x0000000400047306 */
/* 0x008ea40000201000 */
/*04c0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x026fca0000000000 */
/*04d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0003e2000c10190c */
/*04e0*/ @P0 BRA 0x460 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe40000000a00 */
/*0510*/ ULDC.64 UR10, c[0x0][0x178] ; /* 0x00005e00000a7ab9 */
/* 0x000fe40000000a00 */
/*0520*/ UIMAD UR6, UR8, UR11, URZ ; /* 0x0000000b080672a4 */
/* 0x000fe4000f8e023f */
/*0530*/ UIMAD.WIDE.U32 UR4, UR8, UR10, URZ ; /* 0x0000000a080472a5 */
/* 0x000fe4000f8e003f */
/*0540*/ UIMAD UR6, UR10, UR9, UR6 ; /* 0x000000090a0672a4 */
/* 0x000fc8000f8e0206 */
/*0550*/ UIADD3 UR5, UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fd2000fffe03f */
/*0560*/ I2F.U64 R4, UR4 ; /* 0x0000000400047d12 */
/* 0x000ea40008301000 */
/*0570*/ IADD3 R0, R4, 0x1800000, RZ ; /* 0x0180000004007810 */
/* 0x004fc80007ffe0ff */
/*0580*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*0590*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fda0003f04070 */
/*05a0*/ @P0 BRA 0x5f0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*05b0*/ MOV R0, 0x5d0 ; /* 0x000005d000007802 */
/* 0x000fe40000000f00 */
/*05c0*/ CALL.REL.NOINC 0x660 ; /* 0x0000009000007944 */
/* 0x023fea0003c00000 */
/*05d0*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0004 */
/*05e0*/ BRA 0x630 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*05f0*/ MUFU.RCP R7, R4 ; /* 0x0000000400077308 */
/* 0x000ea40000001000 */
/*0600*/ FFMA R0, R4, R7, -1 ; /* 0xbf80000004007423 */
/* 0x004fc80000000007 */
/*0610*/ FADD.FTZ R0, -R0, -RZ ; /* 0x800000ff00007221 */
/* 0x000fc80000010100 */
/*0620*/ FFMA R0, R7, R0, R7 ; /* 0x0000000007007223 */
/* 0x000fc80000000007 */
/*0630*/ FMUL R5, R0, R5 ; /* 0x0000000500057220 */
/* 0x022fca0000400000 */
/*0640*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c10190c */
/*0650*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0660*/ SHF.L.U32 R6, R4, 0x1, RZ ; /* 0x0000000104067819 */
/* 0x000fc800000006ff */
/*0670*/ SHF.R.U32.HI R6, RZ, 0x18, R6 ; /* 0x00000018ff067819 */
/* 0x000fc80000011606 */
/*0680*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05070 */
/*0690*/ @P0 BRA 0x750 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.SHL.U32 R6, R4, 0x2, RZ ; /* 0x0000000204067824 */
/* 0x000fca00078e00ff */
/*06b0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*06c0*/ @!P0 MUFU.RCP R6, R4 ; /* 0x0000000400068308 */
/* 0x0000620000001000 */
/*06d0*/ @!P0 BRA 0x970 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*06e0*/ FFMA R4, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004047823 */
/* 0x001fc800000000ff */
/*06f0*/ MUFU.RCP R7, R4 ; /* 0x0000000400077308 */
/* 0x000e240000001000 */
/*0700*/ FFMA R6, R4, R7, -1 ; /* 0xbf80000004067423 */
/* 0x003fc80000000007 */
/*0710*/ FADD.FTZ R6, -R6, -RZ ; /* 0x800000ff06067221 */
/* 0x000fc80000010100 */
/*0720*/ FFMA R6, R7, R6, R7 ; /* 0x0000000607067223 */
/* 0x000fc80000000007 */
/*0730*/ FFMA R6, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006067823 */
/* 0x000fe200000000ff */
/*0740*/ BRA 0x970 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0750*/ IADD3 R7, R6, -0xfd, RZ ; /* 0xffffff0306077810 */
/* 0x000fc80007ffe0ff */
/*0760*/ ISETP.GT.U32.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f04070 */
/*0770*/ @P0 BRA 0x960 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0780*/ LOP3.LUT R8, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04087812 */
/* 0x000fe200078ec0ff */
/*0790*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3 ; /* 0x00000003ff0c7424 */
/* 0x000fc600078e00ff */
/*07a0*/ LOP3.LUT R8, R8, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000008087812 */
/* 0x000fe400078efcff */
/*07b0*/ SHF.L.U32 R13, R12, R7, RZ ; /* 0x000000070c0d7219 */
/* 0x000fe400000006ff */
/*07c0*/ MUFU.RCP R9, R8 ; /* 0x0000000800097308 */
/* 0x000e240000001000 */
/*07d0*/ FFMA R10, R8, R9, -1 ; /* 0xbf800000080a7423 */
/* 0x001fc80000000009 */
/*07e0*/ FADD.FTZ R10, -R10, -RZ ; /* 0x800000ff0a0a7221 */
/* 0x000fc80000010100 */
/*07f0*/ FFMA.RM R11, R9.reuse, R10.reuse, R9.reuse ; /* 0x0000000a090b7223 */
/* 0x1c0fe40000004009 */
/*0800*/ FFMA.RP R10, R9, R10, R9 ; /* 0x0000000a090a7223 */
/* 0x000fc60000008009 */
/*0810*/ LOP3.LUT R9, R11.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0b097812 */
/* 0x040fe400078ec0ff */
/*0820*/ FSETP.NEU.FTZ.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720b */
/* 0x000fe40003f1d000 */
/*0830*/ LOP3.LUT R10, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x00800000090a7812 */
/* 0x000fe400078efcff */
/*0840*/ SEL R9, RZ, 0xffffffff, !P0 ; /* 0xffffffffff097807 */
/* 0x000fe40004000000 */
/*0850*/ LOP3.LUT R8, R13, R10, RZ, 0xc0, !PT ; /* 0x0000000a0d087212 */
/* 0x000fc600078ec0ff */
/*0860*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0870*/ SHF.R.U32.HI R8, RZ, R7, R8 ; /* 0x00000007ff087219 */
/* 0x000fc80000011608 */
/*0880*/ LOP3.LUT P1, RZ, R9, R7, R10, 0xf8, !PT ; /* 0x0000000709ff7212 */
/* 0x000fe4000782f80a */
/*0890*/ LOP3.LUT P0, RZ, R8.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000108ff7812 */
/* 0x040fe4000780c0ff */
/*08a0*/ LOP3.LUT P2, RZ, R8, 0x2, RZ, 0xc0, !PT ; /* 0x0000000208ff7812 */
/* 0x000fc8000784c0ff */
/*08b0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*08c0*/ LOP3.LUT P1, RZ, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04ff7812 */
/* 0x000fe4000782c0ff */
/*08d0*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fca0004000000 */
/*08e0*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a07 */
/*08f0*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f06270 */
/*0900*/ IADD3 R7, R6, -0xfc, RZ ; /* 0xffffff0406077810 */
/* 0x000fc80007ffe0ff */
/*0910*/ SHF.R.U32.HI R7, RZ, R7, R10 ; /* 0x00000007ff077219 */
/* 0x000fce000001160a */
/*0920*/ @!P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107078810 */
/* 0x000fc80007ffe0ff */
/*0930*/ @!P1 SHF.L.U32 R7, R7, 0x1, RZ ; /* 0x0000000107079819 */
/* 0x000fc800000006ff */
/*0940*/ LOP3.LUT R6, R7, 0x80000000, R4, 0xf8, !PT ; /* 0x8000000007067812 */
/* 0x000fe200078ef804 */
/*0950*/ BRA 0x970 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0960*/ MUFU.RCP R6, R4 ; /* 0x0000000400067308 */
/* 0x0000640000001000 */
/*0970*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x003fe400078e0006 */
/*0980*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0990*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*09a0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff65006007950 */
/* 0x000fea0003c3ffff */
/*09b0*/ BRA 0x9b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void calcCDFnormalized(const unsigned int *histo, float *cdf, size_t width, size_t height) {
for (int i = 0; i <= threadIdx.x; i++) {
cdf[threadIdx.x] += (float) histo[i];
}
cdf[threadIdx.x] *= 1.0f / float((width * height));
} | .file "tmpxft_0009c3d6_00000000-6_calcCDFnormalized.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17calcCDFnormalizedPKjPfmmPKjPfmm
.type _Z42__device_stub__Z17calcCDFnormalizedPKjPfmmPKjPfmm, @function
_Z42__device_stub__Z17calcCDFnormalizedPKjPfmmPKjPfmm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17calcCDFnormalizedPKjPfmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17calcCDFnormalizedPKjPfmmPKjPfmm, .-_Z42__device_stub__Z17calcCDFnormalizedPKjPfmmPKjPfmm
.globl _Z17calcCDFnormalizedPKjPfmm
.type _Z17calcCDFnormalizedPKjPfmm, @function
_Z17calcCDFnormalizedPKjPfmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17calcCDFnormalizedPKjPfmmPKjPfmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17calcCDFnormalizedPKjPfmm, .-_Z17calcCDFnormalizedPKjPfmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17calcCDFnormalizedPKjPfmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17calcCDFnormalizedPKjPfmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void calcCDFnormalized(const unsigned int *histo, float *cdf, size_t width, size_t height) {
for (int i = 0; i <= threadIdx.x; i++) {
cdf[threadIdx.x] += (float) histo[i];
}
cdf[threadIdx.x] *= 1.0f / float((width * height));
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcCDFnormalized(const unsigned int *histo, float *cdf, size_t width, size_t height) {
for (int i = 0; i <= threadIdx.x; i++) {
cdf[threadIdx.x] += (float) histo[i];
}
cdf[threadIdx.x] *= 1.0f / float((width * height));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcCDFnormalized(const unsigned int *histo, float *cdf, size_t width, size_t height) {
for (int i = 0; i <= threadIdx.x; i++) {
cdf[threadIdx.x] += (float) histo[i];
}
cdf[threadIdx.x] *= 1.0f / float((width * height));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17calcCDFnormalizedPKjPfmm
.globl _Z17calcCDFnormalizedPKjPfmm
.p2align 8
.type _Z17calcCDFnormalizedPKjPfmm,@function
_Z17calcCDFnormalizedPKjPfmm:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
v_add_nc_u32_e32 v4, 1, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v3, v1, s[6:7]
v_add_co_u32 v1, s2, s6, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s7, 0, s2
s_mov_b32 s2, 0
.LBB0_1:
s_load_b32 s3, s[4:5], 0x0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v5, s3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v3, v5 :: v_dual_add_nc_u32 v4, -1, v4
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[0:3], s[0:1], 0x10
global_store_b32 v[1:2], v3, off
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s1
s_mul_hi_u32 s4, s2, s0
s_mul_i32 s3, s3, s0
s_add_i32 s1, s4, s1
s_mul_i32 s0, s2, s0
s_add_i32 s1, s1, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_clz_i32_u32 s3, s1
s_min_u32 s2, s3, 32
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], s2
s_min_u32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s1, s0
v_cvt_f32_u32_e32 v2, s0
s_sub_i32 s0, 32, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_ldexp_f32 v2, v2, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v3, null, v2, v2, 1.0
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, 1.0, v2, 1.0
v_mul_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v6, v5
v_fmac_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v6, v5
v_div_fmas_f32 v3, v3, v4, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v3, v2, 1.0
v_lshlrev_b32_e32 v0, 2, v0
global_load_b32 v1, v0, s[6:7]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v2, v1
global_store_b32 v0, v1, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17calcCDFnormalizedPKjPfmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17calcCDFnormalizedPKjPfmm, .Lfunc_end0-_Z17calcCDFnormalizedPKjPfmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17calcCDFnormalizedPKjPfmm
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z17calcCDFnormalizedPKjPfmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcCDFnormalized(const unsigned int *histo, float *cdf, size_t width, size_t height) {
for (int i = 0; i <= threadIdx.x; i++) {
cdf[threadIdx.x] += (float) histo[i];
}
cdf[threadIdx.x] *= 1.0f / float((width * height));
} | .text
.file "calcCDFnormalized.hip"
.globl _Z32__device_stub__calcCDFnormalizedPKjPfmm # -- Begin function _Z32__device_stub__calcCDFnormalizedPKjPfmm
.p2align 4, 0x90
.type _Z32__device_stub__calcCDFnormalizedPKjPfmm,@function
_Z32__device_stub__calcCDFnormalizedPKjPfmm: # @_Z32__device_stub__calcCDFnormalizedPKjPfmm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17calcCDFnormalizedPKjPfmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__calcCDFnormalizedPKjPfmm, .Lfunc_end0-_Z32__device_stub__calcCDFnormalizedPKjPfmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17calcCDFnormalizedPKjPfmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17calcCDFnormalizedPKjPfmm,@object # @_Z17calcCDFnormalizedPKjPfmm
.section .rodata,"a",@progbits
.globl _Z17calcCDFnormalizedPKjPfmm
.p2align 3, 0x0
_Z17calcCDFnormalizedPKjPfmm:
.quad _Z32__device_stub__calcCDFnormalizedPKjPfmm
.size _Z17calcCDFnormalizedPKjPfmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17calcCDFnormalizedPKjPfmm"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__calcCDFnormalizedPKjPfmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17calcCDFnormalizedPKjPfmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17calcCDFnormalizedPKjPfmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x420 ; /* 0x000003d000007945 */
/* 0x000fe20003800000 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R15.reuse, 0x3, PT ; /* 0x000000030f00780c */
/* 0x041fe20003f06070 */
/*0060*/ IMAD.WIDE.U32 R2, R15.reuse, R4, c[0x0][0x168] ; /* 0x00005a000f027625 */
/* 0x040fe200078e0004 */
/*0070*/ IADD3 R0, R15, 0x1, RZ ; /* 0x000000010f007810 */
/* 0x000fc80007ffe0ff */
/*0080*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fce00078ec0ff */
/*0090*/ @!P0 BRA 0x3f0 ; /* 0x0000035000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe200078e00ff */
/*00b0*/ LDG.E R5, [R2.64] ; /* 0x0000000c02057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff077624 */
/* 0x000fca00078e00ff */
/*00d0*/ LDG.E R8, [R6.64] ; /* 0x0000000c06087981 */
/* 0x000ee4000c1e1900 */
/*00e0*/ I2F.U32 R8, R8 ; /* 0x0000000800087306 */
/* 0x008ea40000201000 */
/*00f0*/ FADD R5, R5, R8 ; /* 0x0000000805057221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c10190c */
/*0110*/ LDG.E R9, [R6.64+0x4] ; /* 0x0000040c06097981 */
/* 0x000ea4000c1e1900 */
/*0120*/ I2F.U32 R10, R9 ; /* 0x00000009000a7306 */
/* 0x004e240000201000 */
/*0130*/ FADD R11, R5, R10 ; /* 0x0000000a050b7221 */
/* 0x001fca0000000000 */
/*0140*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c10190c */
/*0150*/ LDG.E R10, [R6.64+0x8] ; /* 0x0000080c060a7981 */
/* 0x000ea4000c1e1900 */
/*0160*/ I2F.U32 R10, R10 ; /* 0x0000000a000a7306 */
/* 0x004e640000201000 */
/*0170*/ FADD R13, R11, R10 ; /* 0x0000000a0b0d7221 */
/* 0x002fca0000000000 */
/*0180*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c10190c */
/*0190*/ LDG.E R8, [R6.64+0xc] ; /* 0x00000c0c06087981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff097624 */
/* 0x000fe200078e00ff */
/*01b0*/ BSSY B1, 0x3e0 ; /* 0x0000022000017945 */
/* 0x000fe80003800000 */
/*01c0*/ IADD3 R11, P1, R9, 0x10, RZ ; /* 0x00000010090b7810 */
/* 0x001fe20007f3e0ff */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.X R10, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff0a7624 */
/* 0x000fe200008e06ff */
/*01f0*/ I2F.U32 R8, R8 ; /* 0x0000000800087306 */
/* 0x004e240000201000 */
/*0200*/ FADD R5, R13, R8 ; /* 0x000000080d057221 */
/* 0x001fe20000000000 */
/*0210*/ IADD3 R8, R15, -0x4, -R0 ; /* 0xfffffffc0f087810 */
/* 0x000fc80007ffe800 */
/*0220*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0003e2000c10190c */
/*0230*/ ISETP.NE.AND P0, PT, R8, -0x1, PT ; /* 0xffffffff0800780c */
/* 0x000fda0003f05270 */
/*0240*/ @!P0 BRA 0x3d0 ; /* 0x0000018000008947 */
/* 0x002fea0003800000 */
/*0250*/ MOV R6, R11 ; /* 0x0000000b00067202 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fca00078e000a */
/*0270*/ LDG.E R10, [R6.64] ; /* 0x0000000c060a7981 */
/* 0x000ea4000c1e1900 */
/*0280*/ I2F.U32 R10, R10 ; /* 0x0000000a000a7306 */
/* 0x004e240000201000 */
/*0290*/ FADD R5, R10, R5 ; /* 0x000000050a057221 */
/* 0x003fca0000000000 */
/*02a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e8000c10190c */
/*02b0*/ LDG.E R11, [R6.64+0x4] ; /* 0x0000040c060b7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ I2F.U32 R12, R11 ; /* 0x0000000b000c7306 */
/* 0x004e640000201000 */
/*02d0*/ FADD R13, R5, R12 ; /* 0x0000000c050d7221 */
/* 0x002fca0000000000 */
/*02e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c10190c */
/*02f0*/ LDG.E R12, [R6.64+0x8] ; /* 0x0000080c060c7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ I2F.U32 R12, R12 ; /* 0x0000000c000c7306 */
/* 0x004ea40000201000 */
/*0310*/ FADD R15, R13, R12 ; /* 0x0000000c0d0f7221 */
/* 0x004fca0000000000 */
/*0320*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c10190c */
/*0330*/ LDG.E R10, [R6.64+0xc] ; /* 0x00000c0c060a7981 */
/* 0x000ea2000c1e1900 */
/*0340*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R11, P1, R6, 0x10, RZ ; /* 0x00000010060b7810 */
/* 0x000fe40007f3e0ff */
/*0360*/ ISETP.NE.AND P0, PT, R8, -0x1, PT ; /* 0xffffffff0800780c */
/* 0x000fe40003f05270 */
/*0370*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007ffe0ff */
/*0380*/ I2F.U32 R10, R10 ; /* 0x0000000a000a7306 */
/* 0x004e240000201000 */
/*0390*/ FADD R5, R15, R10 ; /* 0x0000000a0f057221 */
/* 0x001fc40000000000 */
/*03a0*/ IMAD.X R10, RZ, RZ, R7, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fc600008e0607 */
/*03b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0003e6000c10190c */
/*03c0*/ @P0 BRA 0x250 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*03d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x410 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*03f0*/ LDG.E R5, [R2.64] ; /* 0x0000000c02057981 */
/* 0x000162000c1e1900 */
/*0400*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc600078e00ff */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0430*/ BSSY B0, 0x500 ; /* 0x000000c000007945 */
/* 0x000fd80003800000 */
/*0440*/ @!P0 BRA 0x4f0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0450*/ IMAD.WIDE R6, R9, R4, c[0x0][0x160] ; /* 0x0000580009067625 */
/* 0x000fca00078e0204 */
/*0460*/ LDG.E R4, [R6.64] ; /* 0x0000000c06047981 */
/* 0x0004e2000c1e1900 */
/*0470*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0480*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0490*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x004fca0007f3e0ff */
/*04a0*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*04b0*/ I2F.U32 R4, R4 ; /* 0x0000000400047306 */
/* 0x008ea40000201000 */
/*04c0*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x026fca0000000000 */
/*04d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0003e2000c10190c */
/*04e0*/ @P0 BRA 0x460 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe40000000a00 */
/*0510*/ ULDC.64 UR10, c[0x0][0x178] ; /* 0x00005e00000a7ab9 */
/* 0x000fe40000000a00 */
/*0520*/ UIMAD UR6, UR8, UR11, URZ ; /* 0x0000000b080672a4 */
/* 0x000fe4000f8e023f */
/*0530*/ UIMAD.WIDE.U32 UR4, UR8, UR10, URZ ; /* 0x0000000a080472a5 */
/* 0x000fe4000f8e003f */
/*0540*/ UIMAD UR6, UR10, UR9, UR6 ; /* 0x000000090a0672a4 */
/* 0x000fc8000f8e0206 */
/*0550*/ UIADD3 UR5, UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fd2000fffe03f */
/*0560*/ I2F.U64 R4, UR4 ; /* 0x0000000400047d12 */
/* 0x000ea40008301000 */
/*0570*/ IADD3 R0, R4, 0x1800000, RZ ; /* 0x0180000004007810 */
/* 0x004fc80007ffe0ff */
/*0580*/ LOP3.LUT R0, R0, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000000007812 */
/* 0x000fc800078ec0ff */
/*0590*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ffffff, PT ; /* 0x01ffffff0000780c */
/* 0x000fda0003f04070 */
/*05a0*/ @P0 BRA 0x5f0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*05b0*/ MOV R0, 0x5d0 ; /* 0x000005d000007802 */
/* 0x000fe40000000f00 */
/*05c0*/ CALL.REL.NOINC 0x660 ; /* 0x0000009000007944 */
/* 0x023fea0003c00000 */
/*05d0*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0004 */
/*05e0*/ BRA 0x630 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*05f0*/ MUFU.RCP R7, R4 ; /* 0x0000000400077308 */
/* 0x000ea40000001000 */
/*0600*/ FFMA R0, R4, R7, -1 ; /* 0xbf80000004007423 */
/* 0x004fc80000000007 */
/*0610*/ FADD.FTZ R0, -R0, -RZ ; /* 0x800000ff00007221 */
/* 0x000fc80000010100 */
/*0620*/ FFMA R0, R7, R0, R7 ; /* 0x0000000007007223 */
/* 0x000fc80000000007 */
/*0630*/ FMUL R5, R0, R5 ; /* 0x0000000500057220 */
/* 0x022fca0000400000 */
/*0640*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c10190c */
/*0650*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0660*/ SHF.L.U32 R6, R4, 0x1, RZ ; /* 0x0000000104067819 */
/* 0x000fc800000006ff */
/*0670*/ SHF.R.U32.HI R6, RZ, 0x18, R6 ; /* 0x00000018ff067819 */
/* 0x000fc80000011606 */
/*0680*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05070 */
/*0690*/ @P0 BRA 0x750 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.SHL.U32 R6, R4, 0x2, RZ ; /* 0x0000000204067824 */
/* 0x000fca00078e00ff */
/*06b0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*06c0*/ @!P0 MUFU.RCP R6, R4 ; /* 0x0000000400068308 */
/* 0x0000620000001000 */
/*06d0*/ @!P0 BRA 0x970 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*06e0*/ FFMA R4, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004047823 */
/* 0x001fc800000000ff */
/*06f0*/ MUFU.RCP R7, R4 ; /* 0x0000000400077308 */
/* 0x000e240000001000 */
/*0700*/ FFMA R6, R4, R7, -1 ; /* 0xbf80000004067423 */
/* 0x003fc80000000007 */
/*0710*/ FADD.FTZ R6, -R6, -RZ ; /* 0x800000ff06067221 */
/* 0x000fc80000010100 */
/*0720*/ FFMA R6, R7, R6, R7 ; /* 0x0000000607067223 */
/* 0x000fc80000000007 */
/*0730*/ FFMA R6, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006067823 */
/* 0x000fe200000000ff */
/*0740*/ BRA 0x970 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0750*/ IADD3 R7, R6, -0xfd, RZ ; /* 0xffffff0306077810 */
/* 0x000fc80007ffe0ff */
/*0760*/ ISETP.GT.U32.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f04070 */
/*0770*/ @P0 BRA 0x960 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0780*/ LOP3.LUT R8, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04087812 */
/* 0x000fe200078ec0ff */
/*0790*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3 ; /* 0x00000003ff0c7424 */
/* 0x000fc600078e00ff */
/*07a0*/ LOP3.LUT R8, R8, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000008087812 */
/* 0x000fe400078efcff */
/*07b0*/ SHF.L.U32 R13, R12, R7, RZ ; /* 0x000000070c0d7219 */
/* 0x000fe400000006ff */
/*07c0*/ MUFU.RCP R9, R8 ; /* 0x0000000800097308 */
/* 0x000e240000001000 */
/*07d0*/ FFMA R10, R8, R9, -1 ; /* 0xbf800000080a7423 */
/* 0x001fc80000000009 */
/*07e0*/ FADD.FTZ R10, -R10, -RZ ; /* 0x800000ff0a0a7221 */
/* 0x000fc80000010100 */
/*07f0*/ FFMA.RM R11, R9.reuse, R10.reuse, R9.reuse ; /* 0x0000000a090b7223 */
/* 0x1c0fe40000004009 */
/*0800*/ FFMA.RP R10, R9, R10, R9 ; /* 0x0000000a090a7223 */
/* 0x000fc60000008009 */
/*0810*/ LOP3.LUT R9, R11.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0b097812 */
/* 0x040fe400078ec0ff */
/*0820*/ FSETP.NEU.FTZ.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720b */
/* 0x000fe40003f1d000 */
/*0830*/ LOP3.LUT R10, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x00800000090a7812 */
/* 0x000fe400078efcff */
/*0840*/ SEL R9, RZ, 0xffffffff, !P0 ; /* 0xffffffffff097807 */
/* 0x000fe40004000000 */
/*0850*/ LOP3.LUT R8, R13, R10, RZ, 0xc0, !PT ; /* 0x0000000a0d087212 */
/* 0x000fc600078ec0ff */
/*0860*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0870*/ SHF.R.U32.HI R8, RZ, R7, R8 ; /* 0x00000007ff087219 */
/* 0x000fc80000011608 */
/*0880*/ LOP3.LUT P1, RZ, R9, R7, R10, 0xf8, !PT ; /* 0x0000000709ff7212 */
/* 0x000fe4000782f80a */
/*0890*/ LOP3.LUT P0, RZ, R8.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000108ff7812 */
/* 0x040fe4000780c0ff */
/*08a0*/ LOP3.LUT P2, RZ, R8, 0x2, RZ, 0xc0, !PT ; /* 0x0000000208ff7812 */
/* 0x000fc8000784c0ff */
/*08b0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*08c0*/ LOP3.LUT P1, RZ, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04ff7812 */
/* 0x000fe4000782c0ff */
/*08d0*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fca0004000000 */
/*08e0*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a07 */
/*08f0*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f06270 */
/*0900*/ IADD3 R7, R6, -0xfc, RZ ; /* 0xffffff0406077810 */
/* 0x000fc80007ffe0ff */
/*0910*/ SHF.R.U32.HI R7, RZ, R7, R10 ; /* 0x00000007ff077219 */
/* 0x000fce000001160a */
/*0920*/ @!P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107078810 */
/* 0x000fc80007ffe0ff */
/*0930*/ @!P1 SHF.L.U32 R7, R7, 0x1, RZ ; /* 0x0000000107079819 */
/* 0x000fc800000006ff */
/*0940*/ LOP3.LUT R6, R7, 0x80000000, R4, 0xf8, !PT ; /* 0x8000000007067812 */
/* 0x000fe200078ef804 */
/*0950*/ BRA 0x970 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0960*/ MUFU.RCP R6, R4 ; /* 0x0000000400067308 */
/* 0x0000640000001000 */
/*0970*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x003fe400078e0006 */
/*0980*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0990*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*09a0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff65006007950 */
/* 0x000fea0003c3ffff */
/*09b0*/ BRA 0x9b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17calcCDFnormalizedPKjPfmm
.globl _Z17calcCDFnormalizedPKjPfmm
.p2align 8
.type _Z17calcCDFnormalizedPKjPfmm,@function
_Z17calcCDFnormalizedPKjPfmm:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
v_add_nc_u32_e32 v4, 1, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v3, v1, s[6:7]
v_add_co_u32 v1, s2, s6, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s7, 0, s2
s_mov_b32 s2, 0
.LBB0_1:
s_load_b32 s3, s[4:5], 0x0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v5, s3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v3, v5 :: v_dual_add_nc_u32 v4, -1, v4
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[0:3], s[0:1], 0x10
global_store_b32 v[1:2], v3, off
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s1
s_mul_hi_u32 s4, s2, s0
s_mul_i32 s3, s3, s0
s_add_i32 s1, s4, s1
s_mul_i32 s0, s2, s0
s_add_i32 s1, s1, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_clz_i32_u32 s3, s1
s_min_u32 s2, s3, 32
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], s2
s_min_u32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s1, s0
v_cvt_f32_u32_e32 v2, s0
s_sub_i32 s0, 32, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_ldexp_f32 v2, v2, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v3, null, v2, v2, 1.0
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, 1.0, v2, 1.0
v_mul_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v6, v5
v_fmac_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v6, v5
v_div_fmas_f32 v3, v3, v4, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v3, v2, 1.0
v_lshlrev_b32_e32 v0, 2, v0
global_load_b32 v1, v0, s[6:7]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v2, v1
global_store_b32 v0, v1, s[6:7]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17calcCDFnormalizedPKjPfmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17calcCDFnormalizedPKjPfmm, .Lfunc_end0-_Z17calcCDFnormalizedPKjPfmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17calcCDFnormalizedPKjPfmm
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z17calcCDFnormalizedPKjPfmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009c3d6_00000000-6_calcCDFnormalized.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17calcCDFnormalizedPKjPfmmPKjPfmm
.type _Z42__device_stub__Z17calcCDFnormalizedPKjPfmmPKjPfmm, @function
_Z42__device_stub__Z17calcCDFnormalizedPKjPfmmPKjPfmm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17calcCDFnormalizedPKjPfmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17calcCDFnormalizedPKjPfmmPKjPfmm, .-_Z42__device_stub__Z17calcCDFnormalizedPKjPfmmPKjPfmm
.globl _Z17calcCDFnormalizedPKjPfmm
.type _Z17calcCDFnormalizedPKjPfmm, @function
_Z17calcCDFnormalizedPKjPfmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17calcCDFnormalizedPKjPfmmPKjPfmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17calcCDFnormalizedPKjPfmm, .-_Z17calcCDFnormalizedPKjPfmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17calcCDFnormalizedPKjPfmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17calcCDFnormalizedPKjPfmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "calcCDFnormalized.hip"
.globl _Z32__device_stub__calcCDFnormalizedPKjPfmm # -- Begin function _Z32__device_stub__calcCDFnormalizedPKjPfmm
.p2align 4, 0x90
.type _Z32__device_stub__calcCDFnormalizedPKjPfmm,@function
_Z32__device_stub__calcCDFnormalizedPKjPfmm: # @_Z32__device_stub__calcCDFnormalizedPKjPfmm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17calcCDFnormalizedPKjPfmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__calcCDFnormalizedPKjPfmm, .Lfunc_end0-_Z32__device_stub__calcCDFnormalizedPKjPfmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17calcCDFnormalizedPKjPfmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17calcCDFnormalizedPKjPfmm,@object # @_Z17calcCDFnormalizedPKjPfmm
.section .rodata,"a",@progbits
.globl _Z17calcCDFnormalizedPKjPfmm
.p2align 3, 0x0
_Z17calcCDFnormalizedPKjPfmm:
.quad _Z32__device_stub__calcCDFnormalizedPKjPfmm
.size _Z17calcCDFnormalizedPKjPfmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17calcCDFnormalizedPKjPfmm"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__calcCDFnormalizedPKjPfmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17calcCDFnormalizedPKjPfmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Tiled Matrix Multiplication
* (MP2, Fall 2014, GPU Programming/Auburn University)
*
* Compile with -DTILE_WIDTH=16 (for example) to change the tile size.
* Compile with -DSEED=12 (for example) to seed the random number generator.
*/
#include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <math.h>
/* Usage message displayed when invalid command line arguments are supplied */
#define USAGE \
"MP2 generates a random (m x k) matrix M and (k x n) matrix N\n" \
"and multiplies M by N using tiled matrix multiplication.\n" \
"The values of m, k, and n must be >= 1.\n" \
"\n" \
"Usage: mp2 m k n\n"
/* Tile size -- define here if not defined using the -D compiler flag */
#ifndef TILE_WIDTH
# define TILE_WIDTH 16
#endif
/* Seed for the random number generator -- define here if not using -D */
#ifndef SEED
# define SEED 1
#endif
/* Maximum difference allowed between the GPU and CPU result matrices */
#define EPSILON 1e-2
/* If a CUDA call fails, display an error message and exit */
#define CUDA_CHECK(e) { \
cudaError_t err = (e); \
if (err != cudaSuccess) \
{ \
fprintf(stderr, "CUDA error: %s, line %d, %s: %s\n", \
__FILE__, __LINE__, #e, cudaGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
/* assert() is only supported on devices of compute capability >= 2.0 */
#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ < 200)
# undef assert
# define assert(arg)
#endif
/* Tiled matrix multiplication kernel */
__global__ static void matMul(float *d_M, float *d_N, float *d_P,
int m, int k, int n)
{
assert(blockDim.x == TILE_WIDTH && blockDim.y == TILE_WIDTH);
/*
*
*
* TODO: IMPLEMENT TILED MATRIX MULTIPLICATION
*
* Multiply matrix d_M by d_N, storing product in d_P.
* Use tiled matrix multiplication with shared memory.
*
*
*/
//__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
//__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x, ty = threadIdx.y;
int row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int col= blockIdx.x * TILE_WIDTH + threadIdx.x;
float sum = 0;
//double numberoftiles =ceil(m/TILE_WIDTH);
if (m == k== n) {
for (int l=0;l<m/TILE_WIDTH ; ++l) { //iterate through tiles
for (int j=0; j< TILE_WIDTH ; ++j) { //iterate through elements in the tile
sum = sum + d_M[(row*m) + ( l*TILE_WIDTH+j)] * d_N[(l*TILE_WIDTH+j)*m + col ];
}
__syncthreads();
}
d_P[row*m +col] = sum;
} else {
for (int l=0;l<ceil((float) k/TILE_WIDTH) ; ++l) { //iterate through tiles
if (row < m && l * TILE_WIDTH + tx < k)
ds_A[ty][tx] = d_M[row *k + l * TILE_WIDTH + tx];
else
ds_A[ty][tx] = 0.0;
if (l * TILE_WIDTH + ty < k && col < n)
ds_B[ty][tx] = d_N[(l * TILE_WIDTH + ty) *n + col];
else
ds_B[ty][tx] = 0.0;
__syncthreads();
for (int j=0; j< TILE_WIDTH && j < k ; ++j) { //iterate through elements in the tile
sum = sum + ds_A[ty][j] * ds_B[j][tx];
}
__syncthreads();
}
if (row < m && col < n)
d_P[row*n+col] =sum;
}
}
/* Displays one row of the given matrix */
static void printRow(int row, float *matrix, int cols)
{
printf("[");
if (cols >= 1) printf(" %3.3f", matrix[row*cols+0]);
if (cols >= 2) printf(" %3.3f", matrix[row*cols+1]);
if (cols >= 3) printf(" %3.3f", matrix[row*cols+2]);
if (cols >= 6) printf(" ...");
if (cols >= 5) printf(" %3.3f", matrix[row*cols+(cols-2)]);
if (cols >= 4) printf(" %3.3f", matrix[row*cols+(cols-1)]);
printf(" ]\n");
}
/* Displays the given matrix */
static void printMatrix(float *matrix, int rows, int cols)
{
if (rows >= 1) printRow(0, matrix, cols);
if (rows >= 2) printRow(1, matrix, cols);
if (rows >= 3) printRow(2, matrix, cols);
if (rows >= 6) printf(" ...\n");
if (rows >= 5) printRow(rows-2, matrix, cols);
if (rows >= 4) printRow(rows-1, matrix, cols);
}
/* Program entrypoint. Invoke with three command line arguments: m k n */
int main(int argc, char **argv)
{
/* Get command line arguments; save as m, k, and n */
if (argc != 4)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Expected 3 arguments; received %d.\n", argc-1);
return EXIT_FAILURE;
}
int m = atoi(argv[1]);
int k = atoi(argv[2]);
int n = atoi(argv[3]);
if (m < 1 || k < 1 || n < 1)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Invalid value for m, k, or n (%d, %d, %d)\n",
m, k, n);
return EXIT_FAILURE;
}
printf("Multiplying MN = P. M is (%d x %d); N is (%d x %d); ",
m, k, k, n);
printf("using (%d x %d) tiles.\n", TILE_WIDTH, TILE_WIDTH);
/********************************************/
/* M is (m x k), N is (k x n), P is (m x n) */
/********************************************/
/* Compute number of bytes needed to stores matrices M, N, and P */
size_t bytesForM = m * k * sizeof(float);
size_t bytesForN = k * n * sizeof(float);
size_t bytesForP = m * n * sizeof(float);
/* Allocate host memory for matrices */
float *h_M, *h_N, *h_P;
h_M = (float *)malloc(bytesForM);
h_N = (float *)malloc(bytesForN);
h_P = (float *)malloc(bytesForP);
if (h_M == NULL || h_N == NULL || h_P == NULL)
{
fprintf(stderr, "Unable to allocate host memory\n");
return EXIT_FAILURE;
}
/* Allocate device memory for matrices */
float *d_M, *d_N, *d_P;
CUDA_CHECK(cudaMalloc((void **)&d_M, bytesForM));
CUDA_CHECK(cudaMalloc((void **)&d_N, bytesForN));
CUDA_CHECK(cudaMalloc((void **)&d_P, bytesForP));
/* Fill M and N with random numbers (on host) */
srand(SEED);
for (int i = 0; i < m*k; ++i)
h_M[i] = rand()/(float)RAND_MAX*10.0;
for (int i = 0; i < k*n; ++i)
h_N[i] = rand()/(float)RAND_MAX*10.0;
if (m <= 5 && k <= 5 && n <= 5)
{
printf("M =\n"); printMatrix(h_M, m, k);
printf("N =\n"); printMatrix(h_N, k, n);
}
/* Copy M and N to device global memory */
CUDA_CHECK(cudaMemcpy(d_M, h_M, bytesForM, cudaMemcpyHostToDevice));
CUDA_CHECK(cudaMemcpy(d_N, h_N, bytesForN, cudaMemcpyHostToDevice));
/* Launch the CUDA kernel */
dim3 dimGrid((n+TILE_WIDTH-1)/TILE_WIDTH, (m+TILE_WIDTH-1)/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
printf("matMul called from host");
matMul<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, m, k, n);
CUDA_CHECK(cudaDeviceSynchronize());
/* Copy result matrix from device global memory back to host memory */
CUDA_CHECK(cudaMemcpy(h_P, d_P, bytesForP, cudaMemcpyDeviceToHost));
printf(" product received from host");
if (m <= 5 && k <= 5 && n <= 5)
{
printf("P =\n"); printMatrix(h_P, m, n);
}
/* Verify that the result matrix is correct */
for (int row = 0; row < m; row++)
{
for (int col = 0; col < n; col++)
{
float expected = 0.0;
for (int i = 0; i < k; i++)
{
expected += h_M[row*k+i] * h_N[i*n+col];
}
float actual = h_P[row*n+col];
if (fabs(expected - actual) > EPSILON)
{
fprintf(stderr, "d_P[%d, %d] is incorrect\n",
row, col);
fprintf(stderr, " Expected: %f\n", expected);
fprintf(stderr, " Computed: %f\n", actual);
return EXIT_FAILURE;
}
}
}
/* Free device global memory */
CUDA_CHECK(cudaFree(d_M));
CUDA_CHECK(cudaFree(d_N));
CUDA_CHECK(cudaFree(d_P));
/* Free host memory */
free(h_M);
free(h_N);
free(h_P);
/* Reset the device (unnecessary if not profiling, but good practice) */
CUDA_CHECK(cudaDeviceReset());
printf("Done\n");
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z6matMulPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R9, c[0x0][0x178] ; /* 0x00005e0000097a02 */
/* 0x000fe20000000f00 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ ISETP.NE.AND P0, PT, R9, c[0x0][0x17c], PT ; /* 0x00005f0009007a0c */
/* 0x000fe20003f05270 */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0060*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe40000000a00 */
/*0070*/ SEL R4, RZ, 0x1, P0 ; /* 0x00000001ff047807 */
/* 0x000fe20000000000 */
/*0080*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e660000002500 */
/*0090*/ ISETP.NE.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fe20003f05270 */
/*00a0*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*00b0*/ LEA R18, R3, R0, 0x4 ; /* 0x0000000003127211 */
/* 0x001fc400078e20ff */
/*00c0*/ LEA R17, R17, R2, 0x4 ; /* 0x0000000211117211 */
/* 0x002fd200078e20ff */
/*00d0*/ @!P0 BRA 0xbb0 ; /* 0x00000ad000008947 */
/* 0x000fea0003800000 */
/*00e0*/ I2F R3, c[0x0][0x17c] ; /* 0x00005f0000037b06 */
/* 0x000e220000201400 */
/*00f0*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe200000001ff */
/*0100*/ FMUL R3, R3, 0.0625 ; /* 0x3d80000003037820 */
/* 0x001fcc0000400000 */
/*0110*/ FRND.CEIL R3, R3 ; /* 0x0000000300037307 */
/* 0x000e240000209000 */
/*0120*/ FSETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x001fda0003f04000 */
/*0130*/ @!P0 BRA 0xb30 ; /* 0x000009f000008947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R4, RZ, -c[0x0][0x17c], RZ ; /* 0x80005f00ff047a10 */
/* 0x000fe40007ffe0ff */
/*0150*/ SHF.L.U32 R7, R0, 0x6, RZ ; /* 0x0000000600077819 */
/* 0x000fe400000006ff */
/*0160*/ IMNMX.U32 R4, R4, -0x10, !PT ; /* 0xfffffff004047817 */
/* 0x000fe40007800000 */
/*0170*/ LEA R6, R2, 0x480, 0x2 ; /* 0x0000048002067811 */
/* 0x000fe400078e10ff */
/*0180*/ IADD3 R5, -R4, RZ, RZ ; /* 0x000000ff04057210 */
/* 0x000fe40007ffe1ff */
/*0190*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fc40000000f00 */
/*01a0*/ LOP3.LUT R5, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305057812 */
/* 0x000fe400078ec0ff */
/*01b0*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe40000000f00 */
/*01c0*/ IADD3 R12, R4, R5, RZ ; /* 0x00000005040c7210 */
/* 0x000fe40007ffe0ff */
/*01d0*/ LEA R14, R2, R7, 0x2 ; /* 0x00000007020e7211 */
/* 0x000fe400078e10ff */
/*01e0*/ IADD3 R15, R7, 0x8, RZ ; /* 0x00000008070f7810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ IADD3 R16, -R12, RZ, RZ ; /* 0x000000ff0c107210 */
/* 0x000fc40007ffe1ff */
/*0200*/ LEA R9, R13.reuse, R2, 0x4 ; /* 0x000000020d097211 */
/* 0x040fe200078e20ff */
/*0210*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*0220*/ LEA R8, R13, R0, 0x4 ; /* 0x000000000d087211 */
/* 0x000fc400078e20ff */
/*0230*/ ISETP.GE.AND P1, PT, R9, c[0x0][0x17c], PT ; /* 0x00005f0009007a0c */
/* 0x000fe40003f26270 */
/*0240*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x17c], PT ; /* 0x00005f0008007a0c */
/* 0x000fe40003f06270 */
/*0250*/ ISETP.GE.OR P1, PT, R18, c[0x0][0x178], P1 ; /* 0x00005e0012007a0c */
/* 0x000fe40000f26670 */
/*0260*/ ISETP.GE.OR P0, PT, R17, c[0x0][0x180], P0 ; /* 0x0000600011007a0c */
/* 0x000fe40000706670 */
/*0270*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fd20000000f00 */
/*0280*/ @!P1 IMAD R10, R18, c[0x0][0x17c], R9 ; /* 0x00005f00120a9a24 */
/* 0x000fe200078e0209 */
/*0290*/ @!P1 MOV R11, 0x4 ; /* 0x00000004000b9802 */
/* 0x000fe20000000f00 */
/*02a0*/ @!P0 IMAD R8, R8, c[0x0][0x180], R17 ; /* 0x0000600008088a24 */
/* 0x000fe200078e0211 */
/*02b0*/ @!P0 MOV R9, 0x4 ; /* 0x0000000400098802 */
/* 0x000fc60000000f00 */
/*02c0*/ @!P1 IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a9625 */
/* 0x000fc800078e020b */
/*02d0*/ @!P0 IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008088625 */
/* 0x000fe200078e0209 */
/*02e0*/ @!P1 LDG.E R19, [R10.64] ; /* 0x000000060a139981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ @!P0 LDG.E R21, [R8.64] ; /* 0x0000000608158981 */
/* 0x000ee2000c1e1900 */
/*0300*/ MOV R20, c[0x0][0x17c] ; /* 0x00005f0000147a02 */
/* 0x000fc80000000f00 */
/*0310*/ ISETP.GE.AND P0, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fe20003f06270 */
/*0320*/ STS [R14], R19 ; /* 0x000000130e007388 */
/* 0x0041e80000000800 */
/*0330*/ STS [R14+0x400], R21 ; /* 0x000400150e007388 */
/* 0x0081e80000000800 */
/*0340*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0350*/ @!P0 BRA 0xae0 ; /* 0x0000078000008947 */
/* 0x000fea0003800000 */
/*0360*/ ISETP.GT.U32.AND P0, PT, R4, -0x4, PT ; /* 0xfffffffc0400780c */
/* 0x001fe20003f04070 */
/*0370*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fd80008000000 */
/*0380*/ @P0 BRA 0x9f0 ; /* 0x0000066000000947 */
/* 0x000fea0003800000 */
/*0390*/ IADD3 R8, -R12, RZ, RZ ; /* 0x000000ff0c087210 */
/* 0x000fe20007ffe1ff */
/*03a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*03b0*/ MOV R21, R15 ; /* 0x0000000f00157202 */
/* 0x000fe40000000f00 */
/*03c0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f04270 */
/*03d0*/ MOV R20, R6 ; /* 0x0000000600147202 */
/* 0x000fe40000000f00 */
/*03e0*/ MOV R19, R16 ; /* 0x0000001000137202 */
/* 0x000fd20000000f00 */
/*03f0*/ @!P0 BRA 0x8f0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0400*/ ISETP.GT.AND P1, PT, R19, 0xc, PT ; /* 0x0000000c1300780c */
/* 0x000fe40003f24270 */
/*0410*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0420*/ @!P1 BRA 0x720 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*0430*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0440*/ LDS R24, [R20+-0x80] ; /* 0xffff800014187984 */
/* 0x000fe20000000800 */
/*0450*/ IADD3 R19, R19, -0x10, RZ ; /* 0xfffffff013137810 */
/* 0x000fe20007ffe0ff */
/*0460*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*0470*/ LDS.64 R10, [R21+-0x8] ; /* 0xfffff800150a7984 */
/* 0x000e220000000a00 */
/*0480*/ ISETP.GT.AND P1, PT, R19, 0xc, PT ; /* 0x0000000c1300780c */
/* 0x000fc60003f24270 */
/*0490*/ LDS R26, [R20+-0x40] ; /* 0xffffc000141a7984 */
/* 0x000e680000000800 */
/*04a0*/ LDS R25, [R20] ; /* 0x0000000014197984 */
/* 0x000fe80000000800 */
/*04b0*/ LDS.64 R8, [R21] ; /* 0x0000000015087984 */
/* 0x000ea80000000a00 */
/*04c0*/ LDS R22, [R20+0x40] ; /* 0x0000400014167984 */
/* 0x000ee20000000800 */
/*04d0*/ FFMA R10, R24, R10, R23 ; /* 0x0000000a180a7223 */
/* 0x001fc60000000017 */
/*04e0*/ LDS R23, [R20+0x80] ; /* 0x0000800014177984 */
/* 0x000fe20000000800 */
/*04f0*/ FFMA R26, R26, R11, R10 ; /* 0x0000000b1a1a7223 */
/* 0x002fc6000000000a */
/*0500*/ LDS.64 R10, [R21+0x8] ; /* 0x00000800150a7984 */
/* 0x000e280000000a00 */
/*0510*/ LDS R24, [R20+0xc0] ; /* 0x0000c00014187984 */
/* 0x000e620000000800 */
/*0520*/ FFMA R8, R25, R8, R26 ; /* 0x0000000819087223 */
/* 0x004fc6000000001a */
/*0530*/ LDS R25, [R20+0x100] ; /* 0x0001000014197984 */
/* 0x000fe20000000800 */
/*0540*/ FFMA R26, R22, R9, R8 ; /* 0x00000009161a7223 */
/* 0x008fc60000000008 */
/*0550*/ LDS.64 R8, [R21+0x10] ; /* 0x0000100015087984 */
/* 0x000ea80000000a00 */
/*0560*/ LDS R22, [R20+0x140] ; /* 0x0001400014167984 */
/* 0x000ee20000000800 */
/*0570*/ FFMA R10, R23, R10, R26 ; /* 0x0000000a170a7223 */
/* 0x001fc6000000001a */
/*0580*/ LDS R23, [R20+0x180] ; /* 0x0001800014177984 */
/* 0x000fe20000000800 */
/*0590*/ FFMA R24, R24, R11, R10 ; /* 0x0000000b18187223 */
/* 0x002fc6000000000a */
/*05a0*/ LDS.64 R10, [R21+0x18] ; /* 0x00001800150a7984 */
/* 0x000e220000000a00 */
/*05b0*/ FFMA R8, R25, R8, R24 ; /* 0x0000000819087223 */
/* 0x004fc60000000018 */
/*05c0*/ LDS R24, [R20+0x1c0] ; /* 0x0001c00014187984 */
/* 0x000e620000000800 */
/*05d0*/ FFMA R26, R22, R9, R8 ; /* 0x00000009161a7223 */
/* 0x008fc60000000008 */
/*05e0*/ LDS R25, [R20+0x200] ; /* 0x0002000014197984 */
/* 0x000fe80000000800 */
/*05f0*/ LDS.64 R8, [R21+0x20] ; /* 0x0000200015087984 */
/* 0x000ea80000000a00 */
/*0600*/ LDS R22, [R20+0x240] ; /* 0x0002400014167984 */
/* 0x000ee20000000800 */
/*0610*/ FFMA R10, R23, R10, R26 ; /* 0x0000000a170a7223 */
/* 0x001fc6000000001a */
/*0620*/ LDS R23, [R20+0x280] ; /* 0x0002800014177984 */
/* 0x000fe80000000800 */
/*0630*/ LDS R26, [R20+0x340] ; /* 0x00034000141a7984 */
/* 0x000fe20000000800 */
/*0640*/ FFMA R24, R24, R11, R10 ; /* 0x0000000b18187223 */
/* 0x002fc6000000000a */
/*0650*/ LDS.64 R10, [R21+0x28] ; /* 0x00002800150a7984 */
/* 0x000e220000000a00 */
/*0660*/ FFMA R8, R25, R8, R24 ; /* 0x0000000819087223 */
/* 0x004fc60000000018 */
/*0670*/ LDS R24, [R20+0x2c0] ; /* 0x0002c00014187984 */
/* 0x000e620000000800 */
/*0680*/ FFMA R22, R22, R9, R8 ; /* 0x0000000916167223 */
/* 0x008fc60000000008 */
/*0690*/ LDS R25, [R20+0x300] ; /* 0x0003000014197984 */
/* 0x0005e80000000800 */
/*06a0*/ LDS.64 R8, [R21+0x30] ; /* 0x0000300015087984 */
/* 0x0007220000000a00 */
/*06b0*/ IADD3 R20, R20, 0x400, RZ ; /* 0x0000040014147810 */
/* 0x004fe40007ffe0ff */
/*06c0*/ IADD3 R21, R21, 0x40, RZ ; /* 0x0000004015157810 */
/* 0x008fe20007ffe0ff */
/*06d0*/ FFMA R10, R23, R10, R22 ; /* 0x0000000a170a7223 */
/* 0x001fc80000000016 */
/*06e0*/ FFMA R11, R24, R11, R10 ; /* 0x0000000b180b7223 */
/* 0x002fc8000000000a */
/*06f0*/ FFMA R8, R25, R8, R11 ; /* 0x0000000819087223 */
/* 0x010fc8000000000b */
/*0700*/ FFMA R23, R26, R9, R8 ; /* 0x000000091a177223 */
/* 0x000fe20000000008 */
/*0710*/ @P1 BRA 0x440 ; /* 0xfffffd2000001947 */
/* 0x000fea000383ffff */
/*0720*/ ISETP.GT.AND P1, PT, R19, 0x4, PT ; /* 0x000000041300780c */
/* 0x000fda0003f24270 */
/*0730*/ @!P1 BRA 0x8d0 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0740*/ LDS R24, [R20+-0x80] ; /* 0xffff800014187984 */
/* 0x000fe20000000800 */
/*0750*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0760*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0770*/ IADD3 R19, R19, -0x8, RZ ; /* 0xfffffff813137810 */
/* 0x000fe20007ffe0ff */
/*0780*/ LDS.64 R10, [R21+-0x8] ; /* 0xfffff800150a7984 */
/* 0x000e280000000a00 */
/*0790*/ LDS R26, [R20+-0x40] ; /* 0xffffc000141a7984 */
/* 0x000e680000000800 */
/*07a0*/ LDS R25, [R20] ; /* 0x0000000014197984 */
/* 0x000fe80000000800 */
/*07b0*/ LDS.64 R8, [R21] ; /* 0x0000000015087984 */
/* 0x000ea80000000a00 */
/*07c0*/ LDS R22, [R20+0x40] ; /* 0x0000400014167984 */
/* 0x000ee20000000800 */
/*07d0*/ FFMA R10, R24, R10, R23 ; /* 0x0000000a180a7223 */
/* 0x001fc60000000017 */
/*07e0*/ LDS R23, [R20+0x80] ; /* 0x0000800014177984 */
/* 0x000fe20000000800 */
/*07f0*/ FFMA R26, R26, R11, R10 ; /* 0x0000000b1a1a7223 */
/* 0x002fc6000000000a */
/*0800*/ LDS.64 R10, [R21+0x8] ; /* 0x00000800150a7984 */
/* 0x000e280000000a00 */
/*0810*/ LDS R24, [R20+0xc0] ; /* 0x0000c00014187984 */
/* 0x000e620000000800 */
/*0820*/ FFMA R8, R25, R8, R26 ; /* 0x0000000819087223 */
/* 0x004fc6000000001a */
/*0830*/ LDS R25, [R20+0x100] ; /* 0x0001000014197984 */
/* 0x000fe20000000800 */
/*0840*/ FFMA R22, R22, R9, R8 ; /* 0x0000000916167223 */
/* 0x008fc60000000008 */
/*0850*/ LDS.64 R8, [R21+0x10] ; /* 0x0000100015087984 */
/* 0x0004e80000000a00 */
/*0860*/ LDS R26, [R20+0x140] ; /* 0x00014000141a7984 */
/* 0x0009620000000800 */
/*0870*/ IADD3 R21, R21, 0x20, RZ ; /* 0x0000002015157810 */
/* 0x004fe40007ffe0ff */
/*0880*/ IADD3 R20, R20, 0x200, RZ ; /* 0x0000020014147810 */
/* 0x010fe20007ffe0ff */
/*0890*/ FFMA R10, R23, R10, R22 ; /* 0x0000000a170a7223 */
/* 0x001fc80000000016 */
/*08a0*/ FFMA R11, R24, R11, R10 ; /* 0x0000000b180b7223 */
/* 0x002fc8000000000a */
/*08b0*/ FFMA R8, R25, R8, R11 ; /* 0x0000000819087223 */
/* 0x008fc8000000000b */
/*08c0*/ FFMA R23, R26, R9, R8 ; /* 0x000000091a177223 */
/* 0x020fe40000000008 */
/*08d0*/ ISETP.NE.OR P0, PT, R19, RZ, P0 ; /* 0x000000ff1300720c */
/* 0x000fda0000705670 */
/*08e0*/ @!P0 BRA 0x9f0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*08f0*/ LDS R22, [R20+-0x80] ; /* 0xffff800014167984 */
/* 0x000fe20000000800 */
/*0900*/ IADD3 R19, R19, -0x4, RZ ; /* 0xfffffffc13137810 */
/* 0x000fe20007ffe0ff */
/*0910*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0920*/ LDS.64 R8, [R21+-0x8] ; /* 0xfffff80015087984 */
/* 0x000e220000000a00 */
/*0930*/ ISETP.NE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fc60003f05270 */
/*0940*/ LDS R24, [R20+-0x40] ; /* 0xffffc00014187984 */
/* 0x000e680000000800 */
/*0950*/ LDS R25, [R20] ; /* 0x0000000014197984 */
/* 0x000fe80000000800 */
/*0960*/ LDS.64 R10, [R21] ; /* 0x00000000150a7984 */
/* 0x0004e80000000a00 */
/*0970*/ LDS R26, [R20+0x40] ; /* 0x00004000141a7984 */
/* 0x0009620000000800 */
/*0980*/ IADD3 R21, R21, 0x10, RZ ; /* 0x0000001015157810 */
/* 0x004fc40007ffe0ff */
/*0990*/ IADD3 R20, R20, 0x100, RZ ; /* 0x0000010014147810 */
/* 0x010fe20007ffe0ff */
/*09a0*/ FFMA R8, R22, R8, R23 ; /* 0x0000000816087223 */
/* 0x001fc80000000017 */
/*09b0*/ FFMA R9, R24, R9, R8 ; /* 0x0000000918097223 */
/* 0x002fc80000000008 */
/*09c0*/ FFMA R10, R25, R10, R9 ; /* 0x0000000a190a7223 */
/* 0x008fc80000000009 */
/*09d0*/ FFMA R23, R26, R11, R10 ; /* 0x0000000b1a177223 */
/* 0x020fe2000000000a */
/*09e0*/ @P0 BRA 0x8f0 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*09f0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0a00*/ @!P0 BRA 0xae0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0a10*/ MOV R8, UR4 ; /* 0x0000000400087c02 */
/* 0x000fe20008000f00 */
/*0a20*/ ULEA UR5, UR4, 0x400, 0x6 ; /* 0x0000040004057891 */
/* 0x000fe2000f8e303f */
/*0a30*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f05270 */
/*0a40*/ LEA R8, R8, R7, 0x2 ; /* 0x0000000708087211 */
/* 0x000fcc00078e10ff */
/*0a50*/ LDS R19, [R2.X4+UR5] ; /* 0x0000000502137984 */
/* 0x000fe80008004800 */
/*0a60*/ LDS.128 R8, [R8] ; /* 0x0000000008087984 */
/* 0x000e240000000c00 */
/*0a70*/ FFMA R23, R19, R8, R23 ; /* 0x0000000813177223 */
/* 0x001fe20000000017 */
/*0a80*/ @!P0 BRA 0xae0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0a90*/ ISETP.NE.AND P0, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe20003f05270 */
/*0aa0*/ LDS R8, [R2.X4+UR5+0x40] ; /* 0x0000400502087984 */
/* 0x000e180008004800 */
/*0ab0*/ @P0 LDS R11, [R2.X4+UR5+0x80] ; /* 0x00008005020b0984 */
/* 0x000e620008004800 */
/*0ac0*/ FFMA R23, R8, R9, R23 ; /* 0x0000000908177223 */
/* 0x001fc80000000017 */
/*0ad0*/ @P0 FFMA R23, R11, R10, R23 ; /* 0x0000000a0b170223 */
/* 0x002fe40000000017 */
/*0ae0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x001fe20007ffe0ff */
/*0af0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b00*/ I2F R8, R13 ; /* 0x0000000d00087306 */
/* 0x000e240000201400 */
/*0b10*/ FSETP.GT.AND P0, PT, R3, R8, PT ; /* 0x000000080300720b */
/* 0x001fda0003f04000 */
/*0b20*/ @P0 BRA 0x200 ; /* 0xfffff6d000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x180], PT ; /* 0x0000600011007a0c */
/* 0x000fc80003f06270 */
/*0b40*/ ISETP.GE.OR P0, PT, R18, c[0x0][0x178], P0 ; /* 0x00005e0012007a0c */
/* 0x000fda0000706670 */
/*0b50*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0b60*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0b70*/ IMAD R2, R18, c[0x0][0x180], R17 ; /* 0x0000600012027a24 */
/* 0x000fd200078e0211 */
/*0b80*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0b90*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe2000c101906 */
/*0ba0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bb0*/ ISETP.GT.AND P0, PT, R9, 0xf, PT ; /* 0x0000000f0900780c */
/* 0x000fe20003f04270 */
/*0bc0*/ IMAD R2, R18, c[0x0][0x178], R17 ; /* 0x00005e0012027a24 */
/* 0x000fe200078e0211 */
/*0bd0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0be0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fcc00078e0203 */
/*0bf0*/ @!P0 MOV R11, RZ ; /* 0x000000ff000b8202 */
/* 0x000fe20000000f00 */
/*0c00*/ @!P0 BRA 0x1120 ; /* 0x0000051000008947 */
/* 0x000fea0003800000 */
/*0c10*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0c20*/ SHF.R.S32.HI R0, RZ, 0x1f, R9 ; /* 0x0000001fff007819 */
/* 0x000fe20000011409 */
/*0c30*/ IMAD R8, R18, c[0x0][0x178], RZ ; /* 0x00005e0012087a24 */
/* 0x000fe200078e02ff */
/*0c40*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe20000000f00 */
/*0c50*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0c60*/ LEA.HI R0, R0, c[0x0][0x178], RZ, 0x4 ; /* 0x00005e0000007a11 */
/* 0x000fc800078f20ff */
/*0c70*/ SHF.R.S32.HI R21, RZ, 0x4, R0 ; /* 0x00000004ff157819 */
/* 0x000fe20000011400 */
/*0c80*/ IMAD.WIDE R6, R17, R6, c[0x0][0x168] ; /* 0x00005a0011067625 */
/* 0x000fc800078e0206 */
/*0c90*/ MOV R4, UR8 ; /* 0x0000000800047c02 */
/* 0x000fe20008000f00 */
/*0ca0*/ LDG.E R10, [R6.64] ; /* 0x00000006060a7981 */
/* 0x0000a2000c1e1900 */
/*0cb0*/ MOV R5, UR9 ; /* 0x0000000900057c02 */
/* 0x000fca0008000f00 */
/*0cc0*/ IMAD.WIDE R4, R8, 0x4, R4 ; /* 0x0000000408047825 */
/* 0x000fc800078e0204 */
/*0cd0*/ IMAD.WIDE R18, R9.reuse, 0x4, R6 ; /* 0x0000000409127825 */
/* 0x040fe200078e0206 */
/*0ce0*/ LDG.E R0, [R4.64] ; /* 0x0000000604007981 */
/* 0x000ea8000c1e1900 */
/*0cf0*/ LDG.E R12, [R18.64] ; /* 0x00000006120c7981 */
/* 0x0002e2000c1e1900 */
/*0d00*/ IMAD.WIDE R28, R9, 0x4, R18 ; /* 0x00000004091c7825 */
/* 0x000fc600078e0212 */
/*0d10*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000406040d7981 */
/* 0x000ee6000c1e1900 */
/*0d20*/ IMAD.WIDE R6, R9.reuse, 0x4, R28 ; /* 0x0000000409067825 */
/* 0x041fe200078e021c */
/*0d30*/ LDG.E R14, [R28.64] ; /* 0x000000061c0e7981 */
/* 0x000128000c1e1900 */
/*0d40*/ LDG.E R15, [R4.64+0x8] ; /* 0x00000806040f7981 */
/* 0x000f22000c1e1900 */
/*0d50*/ IMAD.WIDE R16, R9, 0x4, R6 ; /* 0x0000000409107825 */
/* 0x000fc600078e0206 */
/*0d60*/ LDG.E R23, [R6.64] ; /* 0x0000000606177981 */
/* 0x000b28000c1e1900 */
/*0d70*/ LDG.E R20, [R4.64+0xc] ; /* 0x00000c0604147981 */
/* 0x000f28000c1e1900 */
/*0d80*/ LDG.E R25, [R4.64+0x10] ; /* 0x0000100604197981 */
/* 0x000f28000c1e1900 */
/*0d90*/ LDG.E R22, [R16.64] ; /* 0x0000000610167981 */
/* 0x000128000c1e1900 */
/*0da0*/ LDG.E R27, [R4.64+0x14] ; /* 0x00001406041b7981 */
/* 0x000f28000c1e1900 */
/*0db0*/ LDG.E R26, [R4.64+0x18] ; /* 0x00001806041a7981 */
/* 0x000f22000c1e1900 */
/*0dc0*/ IMAD.WIDE R16, R9, 0x4, R16 ; /* 0x0000000409107825 */
/* 0x001fca00078e0210 */
/*0dd0*/ LDG.E R24, [R16.64] ; /* 0x0000000610187981 */
/* 0x000122000c1e1900 */
/*0de0*/ IMAD.WIDE R18, R9, 0x4, R16 ; /* 0x0000000409127825 */
/* 0x002fca00078e0210 */
/*0df0*/ LDG.E R29, [R18.64] ; /* 0x00000006121d7981 */
/* 0x000322000c1e1900 */
/*0e00*/ IMAD.WIDE R6, R9, 0x4, R18 ; /* 0x0000000409067825 */
/* 0x020fc800078e0212 */
/*0e10*/ FFMA R0, R10, R0, R11 ; /* 0x000000000a007223 */
/* 0x004fe4000000000b */
/*0e20*/ IMAD.WIDE R10, R9.reuse, 0x4, R6 ; /* 0x00000004090a7825 */
/* 0x040fe400078e0206 */
/*0e30*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000564000c1e1900 */
/*0e40*/ FFMA R0, R12, R13, R0 ; /* 0x0000000d0c007223 */
/* 0x008fe40000000000 */
/*0e50*/ IMAD.WIDE R12, R9, 0x4, R10 ; /* 0x00000004090c7825 */
/* 0x000fe400078e020a */
/*0e60*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000764000c1e1900 */
/*0e70*/ FFMA R28, R14, R15, R0 ; /* 0x0000000f0e1c7223 */
/* 0x010fc40000000000 */
/*0e80*/ LDG.E R7, [R4.64+0x28] ; /* 0x0000280604077981 */
/* 0x004ea2000c1e1900 */
/*0e90*/ IMAD.WIDE R14, R9, 0x4, R12 ; /* 0x00000004090e7825 */
/* 0x000fc600078e020c */
/*0ea0*/ LDG.E R0, [R4.64+0x1c] ; /* 0x00001c0604007981 */
/* 0x000f62000c1e1900 */
/*0eb0*/ FFMA R23, R23, R20, R28 ; /* 0x0000001417177223 */
/* 0x000fc6000000001c */
/*0ec0*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x0008a2000c1e1900 */
/*0ed0*/ IMAD.WIDE R16, R9, 0x4, R14 ; /* 0x0000000409107825 */
/* 0x001fc600078e020e */
/*0ee0*/ LDG.E R20, [R4.64+0x20] ; /* 0x0000200604147981 */
/* 0x000ea2000c1e1900 */
/*0ef0*/ FFMA R22, R22, R25, R23 ; /* 0x0000001916167223 */
/* 0x000fc60000000017 */
/*0f00*/ LDG.E R28, [R14.64] ; /* 0x000000060e1c7981 */
/* 0x0000a2000c1e1900 */
/*0f10*/ IMAD.WIDE R18, R9, 0x4, R16 ; /* 0x0000000409127825 */
/* 0x002fc600078e0210 */
/*0f20*/ LDG.E R25, [R4.64+0x24] ; /* 0x0000240604197981 */
/* 0x000ea8000c1e1900 */
/*0f30*/ LDG.E R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x0002a8000c1e1900 */
/*0f40*/ LDG.E R11, [R4.64+0x2c] ; /* 0x00002c06040b7981 */
/* 0x008ee2000c1e1900 */
/*0f50*/ FFMA R24, R24, R27, R22 ; /* 0x0000001b18187223 */
/* 0x000fe40000000016 */
/*0f60*/ IMAD.WIDE R22, R9, 0x4, R18 ; /* 0x0000000409167825 */
/* 0x000fe200078e0212 */
/*0f70*/ LDG.E R13, [R4.64+0x30] ; /* 0x00003006040d7981 */
/* 0x010f26000c1e1900 */
/*0f80*/ FFMA R29, R29, R26, R24 ; /* 0x0000001a1d1d7223 */
/* 0x000fe20000000018 */
/*0f90*/ LDG.E R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000122000c1e1900 */
/*0fa0*/ IMAD.WIDE R26, R9, 0x4, R22 ; /* 0x00000004091a7825 */
/* 0x000fc600078e0216 */
/*0fb0*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x000128000c1e1900 */
/*0fc0*/ LDG.E R17, [R4.64+0x34] ; /* 0x0000340604117981 */
/* 0x002f22000c1e1900 */
/*0fd0*/ IMAD.WIDE R14, R9, 0x4, R26 ; /* 0x00000004090e7825 */
/* 0x001fc600078e021a */
/*0fe0*/ LDG.E R24, [R26.64] ; /* 0x000000061a187981 */
/* 0x000128000c1e1900 */
/*0ff0*/ LDG.E R19, [R4.64+0x38] ; /* 0x0000380604137981 */
/* 0x000f28000c1e1900 */
/*1000*/ LDG.E R23, [R14.64] ; /* 0x000000060e177981 */
/* 0x000f28000c1e1900 */
/*1010*/ LDG.E R26, [R4.64+0x3c] ; /* 0x00003c06041a7981 */
/* 0x001f22000c1e1900 */
/*1020*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fc6000fffe03f */
/*1030*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*1040*/ ISETP.LE.AND P0, PT, R21, UR4, PT ; /* 0x0000000415007c0c */
/* 0x000fe2000bf03270 */
/*1050*/ UIADD3 UR8, UP0, UR8, 0x40, URZ ; /* 0x0000004008087890 */
/* 0x000fc8000ff1e03f */
/*1060*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*1070*/ FFMA R29, R6, R0, R29 ; /* 0x00000000061d7223 */
/* 0x020fc8000000001d */
/*1080*/ FFMA R10, R10, R20, R29 ; /* 0x000000140a0a7223 */
/* 0x004fc8000000001d */
/*1090*/ FFMA R10, R12, R25, R10 ; /* 0x000000190c0a7223 */
/* 0x000fc8000000000a */
/*10a0*/ FFMA R7, R28, R7, R10 ; /* 0x000000071c077223 */
/* 0x000fc8000000000a */
/*10b0*/ FFMA R7, R16, R11, R7 ; /* 0x0000000b10077223 */
/* 0x008fc80000000007 */
/*10c0*/ FFMA R7, R18, R13, R7 ; /* 0x0000000d12077223 */
/* 0x010fc80000000007 */
/*10d0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x000fc80000000007 */
/*10e0*/ FFMA R7, R24, R19, R7 ; /* 0x0000001318077223 */
/* 0x000fc80000000007 */
/*10f0*/ FFMA R11, R23, R26, R7 ; /* 0x0000001a170b7223 */
/* 0x000fe40000000007 */
/*1100*/ IMAD.WIDE R6, R9, 0x4, R14 ; /* 0x0000000409067825 */
/* 0x000fe200078e020e */
/*1110*/ @!P0 BRA 0xc90 ; /* 0xfffffb7000008947 */
/* 0x000fea000383ffff */
/*1120*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101906 */
/*1130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1140*/ BRA 0x1140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Tiled Matrix Multiplication
* (MP2, Fall 2014, GPU Programming/Auburn University)
*
* Compile with -DTILE_WIDTH=16 (for example) to change the tile size.
* Compile with -DSEED=12 (for example) to seed the random number generator.
*/
#include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <math.h>
/* Usage message displayed when invalid command line arguments are supplied */
#define USAGE \
"MP2 generates a random (m x k) matrix M and (k x n) matrix N\n" \
"and multiplies M by N using tiled matrix multiplication.\n" \
"The values of m, k, and n must be >= 1.\n" \
"\n" \
"Usage: mp2 m k n\n"
/* Tile size -- define here if not defined using the -D compiler flag */
#ifndef TILE_WIDTH
# define TILE_WIDTH 16
#endif
/* Seed for the random number generator -- define here if not using -D */
#ifndef SEED
# define SEED 1
#endif
/* Maximum difference allowed between the GPU and CPU result matrices */
#define EPSILON 1e-2
/* If a CUDA call fails, display an error message and exit */
#define CUDA_CHECK(e) { \
cudaError_t err = (e); \
if (err != cudaSuccess) \
{ \
fprintf(stderr, "CUDA error: %s, line %d, %s: %s\n", \
__FILE__, __LINE__, #e, cudaGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
/* assert() is only supported on devices of compute capability >= 2.0 */
#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ < 200)
# undef assert
# define assert(arg)
#endif
/* Tiled matrix multiplication kernel */
__global__ static void matMul(float *d_M, float *d_N, float *d_P,
int m, int k, int n)
{
assert(blockDim.x == TILE_WIDTH && blockDim.y == TILE_WIDTH);
/*
*
*
* TODO: IMPLEMENT TILED MATRIX MULTIPLICATION
*
* Multiply matrix d_M by d_N, storing product in d_P.
* Use tiled matrix multiplication with shared memory.
*
*
*/
//__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
//__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x, ty = threadIdx.y;
int row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int col= blockIdx.x * TILE_WIDTH + threadIdx.x;
float sum = 0;
//double numberoftiles =ceil(m/TILE_WIDTH);
if (m == k== n) {
for (int l=0;l<m/TILE_WIDTH ; ++l) { //iterate through tiles
for (int j=0; j< TILE_WIDTH ; ++j) { //iterate through elements in the tile
sum = sum + d_M[(row*m) + ( l*TILE_WIDTH+j)] * d_N[(l*TILE_WIDTH+j)*m + col ];
}
__syncthreads();
}
d_P[row*m +col] = sum;
} else {
for (int l=0;l<ceil((float) k/TILE_WIDTH) ; ++l) { //iterate through tiles
if (row < m && l * TILE_WIDTH + tx < k)
ds_A[ty][tx] = d_M[row *k + l * TILE_WIDTH + tx];
else
ds_A[ty][tx] = 0.0;
if (l * TILE_WIDTH + ty < k && col < n)
ds_B[ty][tx] = d_N[(l * TILE_WIDTH + ty) *n + col];
else
ds_B[ty][tx] = 0.0;
__syncthreads();
for (int j=0; j< TILE_WIDTH && j < k ; ++j) { //iterate through elements in the tile
sum = sum + ds_A[ty][j] * ds_B[j][tx];
}
__syncthreads();
}
if (row < m && col < n)
d_P[row*n+col] =sum;
}
}
/* Displays one row of the given matrix */
static void printRow(int row, float *matrix, int cols)
{
printf("[");
if (cols >= 1) printf(" %3.3f", matrix[row*cols+0]);
if (cols >= 2) printf(" %3.3f", matrix[row*cols+1]);
if (cols >= 3) printf(" %3.3f", matrix[row*cols+2]);
if (cols >= 6) printf(" ...");
if (cols >= 5) printf(" %3.3f", matrix[row*cols+(cols-2)]);
if (cols >= 4) printf(" %3.3f", matrix[row*cols+(cols-1)]);
printf(" ]\n");
}
/* Displays the given matrix */
static void printMatrix(float *matrix, int rows, int cols)
{
if (rows >= 1) printRow(0, matrix, cols);
if (rows >= 2) printRow(1, matrix, cols);
if (rows >= 3) printRow(2, matrix, cols);
if (rows >= 6) printf(" ...\n");
if (rows >= 5) printRow(rows-2, matrix, cols);
if (rows >= 4) printRow(rows-1, matrix, cols);
}
/* Program entrypoint. Invoke with three command line arguments: m k n */
int main(int argc, char **argv)
{
/* Get command line arguments; save as m, k, and n */
if (argc != 4)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Expected 3 arguments; received %d.\n", argc-1);
return EXIT_FAILURE;
}
int m = atoi(argv[1]);
int k = atoi(argv[2]);
int n = atoi(argv[3]);
if (m < 1 || k < 1 || n < 1)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Invalid value for m, k, or n (%d, %d, %d)\n",
m, k, n);
return EXIT_FAILURE;
}
printf("Multiplying MN = P. M is (%d x %d); N is (%d x %d); ",
m, k, k, n);
printf("using (%d x %d) tiles.\n", TILE_WIDTH, TILE_WIDTH);
/********************************************/
/* M is (m x k), N is (k x n), P is (m x n) */
/********************************************/
/* Compute number of bytes needed to stores matrices M, N, and P */
size_t bytesForM = m * k * sizeof(float);
size_t bytesForN = k * n * sizeof(float);
size_t bytesForP = m * n * sizeof(float);
/* Allocate host memory for matrices */
float *h_M, *h_N, *h_P;
h_M = (float *)malloc(bytesForM);
h_N = (float *)malloc(bytesForN);
h_P = (float *)malloc(bytesForP);
if (h_M == NULL || h_N == NULL || h_P == NULL)
{
fprintf(stderr, "Unable to allocate host memory\n");
return EXIT_FAILURE;
}
/* Allocate device memory for matrices */
float *d_M, *d_N, *d_P;
CUDA_CHECK(cudaMalloc((void **)&d_M, bytesForM));
CUDA_CHECK(cudaMalloc((void **)&d_N, bytesForN));
CUDA_CHECK(cudaMalloc((void **)&d_P, bytesForP));
/* Fill M and N with random numbers (on host) */
srand(SEED);
for (int i = 0; i < m*k; ++i)
h_M[i] = rand()/(float)RAND_MAX*10.0;
for (int i = 0; i < k*n; ++i)
h_N[i] = rand()/(float)RAND_MAX*10.0;
if (m <= 5 && k <= 5 && n <= 5)
{
printf("M =\n"); printMatrix(h_M, m, k);
printf("N =\n"); printMatrix(h_N, k, n);
}
/* Copy M and N to device global memory */
CUDA_CHECK(cudaMemcpy(d_M, h_M, bytesForM, cudaMemcpyHostToDevice));
CUDA_CHECK(cudaMemcpy(d_N, h_N, bytesForN, cudaMemcpyHostToDevice));
/* Launch the CUDA kernel */
dim3 dimGrid((n+TILE_WIDTH-1)/TILE_WIDTH, (m+TILE_WIDTH-1)/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
printf("matMul called from host");
matMul<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, m, k, n);
CUDA_CHECK(cudaDeviceSynchronize());
/* Copy result matrix from device global memory back to host memory */
CUDA_CHECK(cudaMemcpy(h_P, d_P, bytesForP, cudaMemcpyDeviceToHost));
printf(" product received from host");
if (m <= 5 && k <= 5 && n <= 5)
{
printf("P =\n"); printMatrix(h_P, m, n);
}
/* Verify that the result matrix is correct */
for (int row = 0; row < m; row++)
{
for (int col = 0; col < n; col++)
{
float expected = 0.0;
for (int i = 0; i < k; i++)
{
expected += h_M[row*k+i] * h_N[i*n+col];
}
float actual = h_P[row*n+col];
if (fabs(expected - actual) > EPSILON)
{
fprintf(stderr, "d_P[%d, %d] is incorrect\n",
row, col);
fprintf(stderr, " Expected: %f\n", expected);
fprintf(stderr, " Computed: %f\n", actual);
return EXIT_FAILURE;
}
}
}
/* Free device global memory */
CUDA_CHECK(cudaFree(d_M));
CUDA_CHECK(cudaFree(d_N));
CUDA_CHECK(cudaFree(d_P));
/* Free host memory */
free(h_M);
free(h_N);
free(h_P);
/* Reset the device (unnecessary if not profiling, but good practice) */
CUDA_CHECK(cudaDeviceReset());
printf("Done\n");
return EXIT_SUCCESS;
} | .file "tmpxft_0006d7ad_00000000-6_mp2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL6matMulPfS_S_iii, @function
_ZL6matMulPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 40(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 20(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZL6matMulPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _ZL6matMulPfS_S_iii, .-_ZL6matMulPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "["
.LC1:
.string " %3.3f"
.LC2:
.string " ..."
.LC3:
.string " ]\n"
.text
.type _ZL8printRowiPfi, @function
_ZL8printRowiPfi:
.LFB2057:
.cfi_startproc
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %edi, %r12d
movq %rsi, %rbp
movl %edx, %ebx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jg .L15
.L13:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebx, %r14d
imull %r12d, %r14d
movslq %r14d, %r13
leaq 0(,%r13,4), %r15
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r13,4), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $1, %ebx
jle .L13
pxor %xmm0, %xmm0
cvtss2sd 4(%rbp,%r15), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $2, %ebx
jle .L13
pxor %xmm0, %xmm0
cvtss2sd 8(%rbp,%r13,4), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $5, %ebx
jg .L16
jne .L11
.L10:
leal -2(%r14,%rbx), %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rax,4), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L12:
movl %r12d, %eax
imull %ebx, %eax
leal -1(%rbx,%rax), %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rax,4), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L13
.L16:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L10
.L11:
cmpl $3, %ebx
jle .L13
jmp .L12
.cfi_endproc
.LFE2057:
.size _ZL8printRowiPfi, .-_ZL8printRowiPfi
.section .rodata.str1.1
.LC4:
.string " ...\n"
.text
.type _ZL11printMatrixPfii, @function
_ZL11printMatrixPfii:
.LFB2058:
.cfi_startproc
testl %esi, %esi
jg .L28
ret
.L28:
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %ebx
movl %edx, %r12d
movq %rdi, %rsi
movl $0, %edi
call _ZL8printRowiPfi
cmpl $1, %ebx
jle .L17
movl %r12d, %edx
movq %rbp, %rsi
movl $1, %edi
call _ZL8printRowiPfi
cmpl $2, %ebx
jle .L17
movl %r12d, %edx
movq %rbp, %rsi
movl $2, %edi
call _ZL8printRowiPfi
cmpl $5, %ebx
jg .L29
jne .L21
.L20:
leal -2(%rbx), %edi
movl %r12d, %edx
movq %rbp, %rsi
call _ZL8printRowiPfi
.L22:
leal -1(%rbx), %edi
movl %r12d, %edx
movq %rbp, %rsi
call _ZL8printRowiPfi
.L17:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L21:
cmpl $3, %ebx
jle .L17
jmp .L22
.cfi_endproc
.LFE2058:
.size _ZL11printMatrixPfii, .-_ZL11printMatrixPfii
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "MP2 generates a random (m x k) matrix M and (k x n) matrix N\nand multiplies M by N using tiled matrix multiplication.\nThe values of m, k, and n must be >= 1.\n\nUsage: mp2 m k n\n"
.align 8
.LC7:
.string "Expected 3 arguments; received %d.\n"
.align 8
.LC8:
.string "Invalid value for m, k, or n (%d, %d, %d)\n"
.align 8
.LC9:
.string "Multiplying MN = P. M is (%d x %d); N is (%d x %d); "
.section .rodata.str1.1
.LC10:
.string "using (%d x %d) tiles.\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Unable to allocate host memory\n"
.align 8
.LC12:
.string "cudaMalloc((void **)&d_M, bytesForM)"
.align 8
.LC13:
.string "/home/ubuntu/Datasets/stackv2/train-structured/venkateshreddy74/Tiled-Matrix-Multiplication-for-Square-and-Non-Square-Matrices/master/mp2.cu"
.align 8
.LC14:
.string "CUDA error: %s, line %d, %s: %s\n"
.align 8
.LC15:
.string "cudaMalloc((void **)&d_N, bytesForN)"
.align 8
.LC16:
.string "cudaMalloc((void **)&d_P, bytesForP)"
.section .rodata.str1.1
.LC19:
.string "M =\n"
.LC20:
.string "N =\n"
.section .rodata.str1.8
.align 8
.LC21:
.string "cudaMemcpy(d_M, h_M, bytesForM, cudaMemcpyHostToDevice)"
.align 8
.LC22:
.string "cudaMemcpy(d_N, h_N, bytesForN, cudaMemcpyHostToDevice)"
.section .rodata.str1.1
.LC23:
.string "matMul called from host"
.LC24:
.string "cudaDeviceSynchronize()"
.section .rodata.str1.8
.align 8
.LC25:
.string "cudaMemcpy(h_P, d_P, bytesForP, cudaMemcpyDeviceToHost)"
.section .rodata.str1.1
.LC26:
.string " product received from host"
.LC27:
.string "P =\n"
.LC30:
.string "d_P[%d, %d] is incorrect\n"
.LC31:
.string " Expected: %f\n"
.LC32:
.string " Computed: %f\n"
.LC33:
.string "cudaFree(d_M)"
.LC34:
.string "cudaFree(d_N)"
.LC35:
.string "cudaFree(d_P)"
.LC36:
.string "cudaDeviceReset()"
.LC37:
.string "Done\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cmpl $4, %edi
je .L33
movl %edi, %ebx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
leal -1(%rbx), %ecx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
.L32:
movq 136(%rsp), %rdx
subq %fs:40, %rdx
jne .L71
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq %rax, 32(%rsp)
movl %eax, 20(%rsp)
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq %rax, 8(%rsp)
movl %eax, %ebp
movq 24(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r14d
testl %r13d, %r13d
setle %al
testl %r15d, %r15d
setle %dl
orb %dl, %al
jne .L63
testl %ebx, %ebx
jle .L63
movl %ebx, %r9d
movq 8(%rsp), %r15
movl %r15d, %r8d
movl %ebp, %ecx
movl 20(%rsp), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %ecx
movl $16, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
movl %edi, %eax
imull %r15d, %eax
cltq
leaq 0(,%rax,4), %rcx
movq %rcx, 40(%rsp)
movl %r15d, %eax
imull %ebx, %eax
cltq
leaq 0(,%rax,4), %r15
movq %r15, 48(%rsp)
movl %edi, %eax
imull %ebx, %eax
cltq
leaq 0(,%rax,4), %r13
movq %r13, 72(%rsp)
movq %rcx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rax, 56(%rsp)
movq %r15, %rdi
call malloc@PLT
movq %rax, %r15
movq %rax, 24(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, %rsi
movq %rax, 64(%rsp)
testq %r12, %r12
sete %al
testq %r15, %r15
sete %dl
orb %dl, %al
jne .L64
testq %rsi, %rsi
je .L64
leaq 88(%rsp), %rdi
movq 40(%rsp), %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L72
leaq 96(%rsp), %rdi
movq 48(%rsp), %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L73
leaq 104(%rsp), %rdi
movq 72(%rsp), %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L74
movl $1, %edi
call srand@PLT
movq 56(%rsp), %r13
movq %r13, %r12
movq 40(%rsp), %rax
leaq (%rax,%r13), %r15
.L42:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC17(%rip), %xmm0
mulss .LC18(%rip), %xmm0
movss %xmm0, 0(%r13)
addq $4, %r13
cmpq %r15, %r13
jne .L42
movq 48(%rsp), %rax
movq 24(%rsp), %r13
leaq (%rax,%r13), %r15
.L43:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC17(%rip), %xmm0
mulss .LC18(%rip), %xmm0
movss %xmm0, 0(%r13)
addq $4, %r13
cmpq %r15, %r13
jne .L43
cmpl $5, 32(%rsp)
setle %al
cmpl $5, 8(%rsp)
setle %dl
andl %edx, %eax
cmpl $5, %ebx
setle %dl
andb %dl, %al
movl %eax, %r13d
jne .L75
.L44:
movl $1, %ecx
movq 40(%rsp), %rdx
movq 56(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L76
movl $1, %ecx
movq 48(%rsp), %rdx
movq 24(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L77
leal 15(%rbx), %eax
movl $16, %ecx
cltd
idivl %ecx
movl %eax, 112(%rsp)
movl 32(%rsp), %eax
addl $15, %eax
cltd
idivl %ecx
movl %eax, 116(%rsp)
movl $1, 120(%rsp)
movl $16, 124(%rsp)
movl $16, 128(%rsp)
movl $1, 132(%rsp)
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 132(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movq 112(%rsp), %rdi
movl 120(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L78
.L47:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L79
movl $2, %ecx
movq 72(%rsp), %rdx
movq 104(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L80
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb %r13b, %r13b
jne .L81
.L50:
movslq %ebx, %rcx
salq $2, %rcx
movq 64(%rsp), %rdi
movslq 8(%rsp), %r10
salq $2, %r10
movl $0, %r9d
movss .LC28(%rip), %xmm2
movsd .LC29(%rip), %xmm1
.L51:
movq 24(%rsp), %rsi
movl $0, %r8d
jmp .L57
.L63:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %r9d
movl 8(%rsp), %r8d
movl 20(%rsp), %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L32
.L64:
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L32
.L72:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 216
pushq %rax
.cfi_def_cfa_offset 224
leaq .LC12(%rip), %r9
movl $216, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L73:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 216
pushq %rax
.cfi_def_cfa_offset 224
leaq .LC15(%rip), %r9
movl $217, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L74:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 216
pushq %rax
.cfi_def_cfa_offset 224
leaq .LC16(%rip), %r9
movl $218, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L75:
.cfi_restore_state
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
movl 20(%rsp), %esi
movq 56(%rsp), %rdi
call _ZL11printMatrixPfii
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %edx
movl %ebp, %esi
movq 24(%rsp), %rdi
call _ZL11printMatrixPfii
jmp .L44
.L76:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 216
pushq %rax
.cfi_def_cfa_offset 224
leaq .LC21(%rip), %r9
movl $234, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L77:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 216
pushq %rax
.cfi_def_cfa_offset 224
leaq .LC22(%rip), %r9
movl $235, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L78:
.cfi_restore_state
movl %ebx, %r9d
movl 8(%rsp), %r8d
movl 20(%rsp), %ecx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _ZL6matMulPfS_S_iii
jmp .L47
.L79:
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 216
pushq %rax
.cfi_def_cfa_offset 224
leaq .LC24(%rip), %r9
movl $244, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L80:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 216
pushq %rax
.cfi_def_cfa_offset 224
leaq .LC25(%rip), %r9
movl $247, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L81:
.cfi_restore_state
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %edx
movl 20(%rsp), %esi
movq 64(%rsp), %rdi
call _ZL11printMatrixPfii
jmp .L50
.L83:
movss (%rdi,%r8,4), %xmm3
subss %xmm3, %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L82
addq $1, %r8
addq $4, %rsi
cmpl %r8d, %r14d
jle .L55
.L57:
movq %rsi, %rdx
movl $0, %eax
movl $0x00000000, 8(%rsp)
.L52:
movss (%r12,%rax,4), %xmm0
mulss (%rdx), %xmm0
addss 8(%rsp), %xmm0
movss %xmm0, 8(%rsp)
addq $1, %rax
addq %rcx, %rdx
cmpl %eax, %ebp
jg .L52
jmp .L83
.L82:
movd %xmm3, %ebx
movl %r9d, %ecx
leaq .LC30(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC31(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movd %ebx, %xmm5
pxor %xmm0, %xmm0
cvtss2sd %xmm5, %xmm0
leaq .LC32(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L32
.L55:
addl $1, %r9d
addq %rcx, %rdi
addq %r10, %r12
movl 20(%rsp), %eax
cmpl %eax, %r9d
jl .L51
movq 88(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
jne .L84
movq 96(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
jne .L85
movq 104(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
testl %eax, %eax
jne .L86
movq 56(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 64(%rsp), %rdi
call free@PLT
call cudaDeviceReset@PLT
movl %eax, %edi
testl %eax, %eax
jne .L87
leaq .LC37(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L32
.L84:
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 216
pushq %rax
.cfi_def_cfa_offset 224
leaq .LC33(%rip), %r9
movl $281, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L85:
.cfi_restore_state
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 216
pushq %rax
.cfi_def_cfa_offset 224
leaq .LC34(%rip), %r9
movl $282, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L86:
.cfi_restore_state
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 216
pushq %rax
.cfi_def_cfa_offset 224
leaq .LC35(%rip), %r9
movl $283, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L87:
.cfi_restore_state
call cudaGetErrorString@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 216
pushq %rax
.cfi_def_cfa_offset 224
leaq .LC36(%rip), %r9
movl $291, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L71:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC38:
.string "_Z6matMulPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC38(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6matMulPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC17:
.long 805306368
.align 4
.LC18:
.long 1092616192
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC28:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC29:
.long 1202590843
.long 1065646817
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Tiled Matrix Multiplication
* (MP2, Fall 2014, GPU Programming/Auburn University)
*
* Compile with -DTILE_WIDTH=16 (for example) to change the tile size.
* Compile with -DSEED=12 (for example) to seed the random number generator.
*/
#include <assert.h>
#include <cuda.h>
#include <stdio.h>
#include <math.h>
/* Usage message displayed when invalid command line arguments are supplied */
#define USAGE \
"MP2 generates a random (m x k) matrix M and (k x n) matrix N\n" \
"and multiplies M by N using tiled matrix multiplication.\n" \
"The values of m, k, and n must be >= 1.\n" \
"\n" \
"Usage: mp2 m k n\n"
/* Tile size -- define here if not defined using the -D compiler flag */
#ifndef TILE_WIDTH
# define TILE_WIDTH 16
#endif
/* Seed for the random number generator -- define here if not using -D */
#ifndef SEED
# define SEED 1
#endif
/* Maximum difference allowed between the GPU and CPU result matrices */
#define EPSILON 1e-2
/* If a CUDA call fails, display an error message and exit */
#define CUDA_CHECK(e) { \
cudaError_t err = (e); \
if (err != cudaSuccess) \
{ \
fprintf(stderr, "CUDA error: %s, line %d, %s: %s\n", \
__FILE__, __LINE__, #e, cudaGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
/* assert() is only supported on devices of compute capability >= 2.0 */
#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ < 200)
# undef assert
# define assert(arg)
#endif
/* Tiled matrix multiplication kernel */
__global__ static void matMul(float *d_M, float *d_N, float *d_P,
int m, int k, int n)
{
assert(blockDim.x == TILE_WIDTH && blockDim.y == TILE_WIDTH);
/*
*
*
* TODO: IMPLEMENT TILED MATRIX MULTIPLICATION
*
* Multiply matrix d_M by d_N, storing product in d_P.
* Use tiled matrix multiplication with shared memory.
*
*
*/
//__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
//__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x, ty = threadIdx.y;
int row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int col= blockIdx.x * TILE_WIDTH + threadIdx.x;
float sum = 0;
//double numberoftiles =ceil(m/TILE_WIDTH);
if (m == k== n) {
for (int l=0;l<m/TILE_WIDTH ; ++l) { //iterate through tiles
for (int j=0; j< TILE_WIDTH ; ++j) { //iterate through elements in the tile
sum = sum + d_M[(row*m) + ( l*TILE_WIDTH+j)] * d_N[(l*TILE_WIDTH+j)*m + col ];
}
__syncthreads();
}
d_P[row*m +col] = sum;
} else {
for (int l=0;l<ceil((float) k/TILE_WIDTH) ; ++l) { //iterate through tiles
if (row < m && l * TILE_WIDTH + tx < k)
ds_A[ty][tx] = d_M[row *k + l * TILE_WIDTH + tx];
else
ds_A[ty][tx] = 0.0;
if (l * TILE_WIDTH + ty < k && col < n)
ds_B[ty][tx] = d_N[(l * TILE_WIDTH + ty) *n + col];
else
ds_B[ty][tx] = 0.0;
__syncthreads();
for (int j=0; j< TILE_WIDTH && j < k ; ++j) { //iterate through elements in the tile
sum = sum + ds_A[ty][j] * ds_B[j][tx];
}
__syncthreads();
}
if (row < m && col < n)
d_P[row*n+col] =sum;
}
}
/* Displays one row of the given matrix */
static void printRow(int row, float *matrix, int cols)
{
printf("[");
if (cols >= 1) printf(" %3.3f", matrix[row*cols+0]);
if (cols >= 2) printf(" %3.3f", matrix[row*cols+1]);
if (cols >= 3) printf(" %3.3f", matrix[row*cols+2]);
if (cols >= 6) printf(" ...");
if (cols >= 5) printf(" %3.3f", matrix[row*cols+(cols-2)]);
if (cols >= 4) printf(" %3.3f", matrix[row*cols+(cols-1)]);
printf(" ]\n");
}
/* Displays the given matrix */
static void printMatrix(float *matrix, int rows, int cols)
{
if (rows >= 1) printRow(0, matrix, cols);
if (rows >= 2) printRow(1, matrix, cols);
if (rows >= 3) printRow(2, matrix, cols);
if (rows >= 6) printf(" ...\n");
if (rows >= 5) printRow(rows-2, matrix, cols);
if (rows >= 4) printRow(rows-1, matrix, cols);
}
/* Program entrypoint. Invoke with three command line arguments: m k n */
int main(int argc, char **argv)
{
/* Get command line arguments; save as m, k, and n */
if (argc != 4)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Expected 3 arguments; received %d.\n", argc-1);
return EXIT_FAILURE;
}
int m = atoi(argv[1]);
int k = atoi(argv[2]);
int n = atoi(argv[3]);
if (m < 1 || k < 1 || n < 1)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Invalid value for m, k, or n (%d, %d, %d)\n",
m, k, n);
return EXIT_FAILURE;
}
printf("Multiplying MN = P. M is (%d x %d); N is (%d x %d); ",
m, k, k, n);
printf("using (%d x %d) tiles.\n", TILE_WIDTH, TILE_WIDTH);
/********************************************/
/* M is (m x k), N is (k x n), P is (m x n) */
/********************************************/
/* Compute number of bytes needed to stores matrices M, N, and P */
size_t bytesForM = m * k * sizeof(float);
size_t bytesForN = k * n * sizeof(float);
size_t bytesForP = m * n * sizeof(float);
/* Allocate host memory for matrices */
float *h_M, *h_N, *h_P;
h_M = (float *)malloc(bytesForM);
h_N = (float *)malloc(bytesForN);
h_P = (float *)malloc(bytesForP);
if (h_M == NULL || h_N == NULL || h_P == NULL)
{
fprintf(stderr, "Unable to allocate host memory\n");
return EXIT_FAILURE;
}
/* Allocate device memory for matrices */
float *d_M, *d_N, *d_P;
CUDA_CHECK(cudaMalloc((void **)&d_M, bytesForM));
CUDA_CHECK(cudaMalloc((void **)&d_N, bytesForN));
CUDA_CHECK(cudaMalloc((void **)&d_P, bytesForP));
/* Fill M and N with random numbers (on host) */
srand(SEED);
for (int i = 0; i < m*k; ++i)
h_M[i] = rand()/(float)RAND_MAX*10.0;
for (int i = 0; i < k*n; ++i)
h_N[i] = rand()/(float)RAND_MAX*10.0;
if (m <= 5 && k <= 5 && n <= 5)
{
printf("M =\n"); printMatrix(h_M, m, k);
printf("N =\n"); printMatrix(h_N, k, n);
}
/* Copy M and N to device global memory */
CUDA_CHECK(cudaMemcpy(d_M, h_M, bytesForM, cudaMemcpyHostToDevice));
CUDA_CHECK(cudaMemcpy(d_N, h_N, bytesForN, cudaMemcpyHostToDevice));
/* Launch the CUDA kernel */
dim3 dimGrid((n+TILE_WIDTH-1)/TILE_WIDTH, (m+TILE_WIDTH-1)/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
printf("matMul called from host");
matMul<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, m, k, n);
CUDA_CHECK(cudaDeviceSynchronize());
/* Copy result matrix from device global memory back to host memory */
CUDA_CHECK(cudaMemcpy(h_P, d_P, bytesForP, cudaMemcpyDeviceToHost));
printf(" product received from host");
if (m <= 5 && k <= 5 && n <= 5)
{
printf("P =\n"); printMatrix(h_P, m, n);
}
/* Verify that the result matrix is correct */
for (int row = 0; row < m; row++)
{
for (int col = 0; col < n; col++)
{
float expected = 0.0;
for (int i = 0; i < k; i++)
{
expected += h_M[row*k+i] * h_N[i*n+col];
}
float actual = h_P[row*n+col];
if (fabs(expected - actual) > EPSILON)
{
fprintf(stderr, "d_P[%d, %d] is incorrect\n",
row, col);
fprintf(stderr, " Expected: %f\n", expected);
fprintf(stderr, " Computed: %f\n", actual);
return EXIT_FAILURE;
}
}
}
/* Free device global memory */
CUDA_CHECK(cudaFree(d_M));
CUDA_CHECK(cudaFree(d_N));
CUDA_CHECK(cudaFree(d_P));
/* Free host memory */
free(h_M);
free(h_N);
free(h_P);
/* Reset the device (unnecessary if not profiling, but good practice) */
CUDA_CHECK(cudaDeviceReset());
printf("Done\n");
return EXIT_SUCCESS;
} | /*
* Tiled Matrix Multiplication
* (MP2, Fall 2014, GPU Programming/Auburn University)
*
* Compile with -DTILE_WIDTH=16 (for example) to change the tile size.
* Compile with -DSEED=12 (for example) to seed the random number generator.
*/
#include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
/* Usage message displayed when invalid command line arguments are supplied */
#define USAGE \
"MP2 generates a random (m x k) matrix M and (k x n) matrix N\n" \
"and multiplies M by N using tiled matrix multiplication.\n" \
"The values of m, k, and n must be >= 1.\n" \
"\n" \
"Usage: mp2 m k n\n"
/* Tile size -- define here if not defined using the -D compiler flag */
#ifndef TILE_WIDTH
# define TILE_WIDTH 16
#endif
/* Seed for the random number generator -- define here if not using -D */
#ifndef SEED
# define SEED 1
#endif
/* Maximum difference allowed between the GPU and CPU result matrices */
#define EPSILON 1e-2
/* If a CUDA call fails, display an error message and exit */
#define CUDA_CHECK(e) { \
hipError_t err = (e); \
if (err != hipSuccess) \
{ \
fprintf(stderr, "CUDA error: %s, line %d, %s: %s\n", \
__FILE__, __LINE__, #e, hipGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
/* assert() is only supported on devices of compute capability >= 2.0 */
#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ < 200)
# undef assert
# define assert(arg)
#endif
/* Tiled matrix multiplication kernel */
__global__ static void matMul(float *d_M, float *d_N, float *d_P,
int m, int k, int n)
{
assert(blockDim.x == TILE_WIDTH && blockDim.y == TILE_WIDTH);
/*
*
*
* TODO: IMPLEMENT TILED MATRIX MULTIPLICATION
*
* Multiply matrix d_M by d_N, storing product in d_P.
* Use tiled matrix multiplication with shared memory.
*
*
*/
//__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
//__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x, ty = threadIdx.y;
int row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int col= blockIdx.x * TILE_WIDTH + threadIdx.x;
float sum = 0;
//double numberoftiles =ceil(m/TILE_WIDTH);
if (m == k== n) {
for (int l=0;l<m/TILE_WIDTH ; ++l) { //iterate through tiles
for (int j=0; j< TILE_WIDTH ; ++j) { //iterate through elements in the tile
sum = sum + d_M[(row*m) + ( l*TILE_WIDTH+j)] * d_N[(l*TILE_WIDTH+j)*m + col ];
}
__syncthreads();
}
d_P[row*m +col] = sum;
} else {
for (int l=0;l<ceil((float) k/TILE_WIDTH) ; ++l) { //iterate through tiles
if (row < m && l * TILE_WIDTH + tx < k)
ds_A[ty][tx] = d_M[row *k + l * TILE_WIDTH + tx];
else
ds_A[ty][tx] = 0.0;
if (l * TILE_WIDTH + ty < k && col < n)
ds_B[ty][tx] = d_N[(l * TILE_WIDTH + ty) *n + col];
else
ds_B[ty][tx] = 0.0;
__syncthreads();
for (int j=0; j< TILE_WIDTH && j < k ; ++j) { //iterate through elements in the tile
sum = sum + ds_A[ty][j] * ds_B[j][tx];
}
__syncthreads();
}
if (row < m && col < n)
d_P[row*n+col] =sum;
}
}
/* Displays one row of the given matrix */
static void printRow(int row, float *matrix, int cols)
{
printf("[");
if (cols >= 1) printf(" %3.3f", matrix[row*cols+0]);
if (cols >= 2) printf(" %3.3f", matrix[row*cols+1]);
if (cols >= 3) printf(" %3.3f", matrix[row*cols+2]);
if (cols >= 6) printf(" ...");
if (cols >= 5) printf(" %3.3f", matrix[row*cols+(cols-2)]);
if (cols >= 4) printf(" %3.3f", matrix[row*cols+(cols-1)]);
printf(" ]\n");
}
/* Displays the given matrix */
static void printMatrix(float *matrix, int rows, int cols)
{
if (rows >= 1) printRow(0, matrix, cols);
if (rows >= 2) printRow(1, matrix, cols);
if (rows >= 3) printRow(2, matrix, cols);
if (rows >= 6) printf(" ...\n");
if (rows >= 5) printRow(rows-2, matrix, cols);
if (rows >= 4) printRow(rows-1, matrix, cols);
}
/* Program entrypoint. Invoke with three command line arguments: m k n */
int main(int argc, char **argv)
{
/* Get command line arguments; save as m, k, and n */
if (argc != 4)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Expected 3 arguments; received %d.\n", argc-1);
return EXIT_FAILURE;
}
int m = atoi(argv[1]);
int k = atoi(argv[2]);
int n = atoi(argv[3]);
if (m < 1 || k < 1 || n < 1)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Invalid value for m, k, or n (%d, %d, %d)\n",
m, k, n);
return EXIT_FAILURE;
}
printf("Multiplying MN = P. M is (%d x %d); N is (%d x %d); ",
m, k, k, n);
printf("using (%d x %d) tiles.\n", TILE_WIDTH, TILE_WIDTH);
/********************************************/
/* M is (m x k), N is (k x n), P is (m x n) */
/********************************************/
/* Compute number of bytes needed to stores matrices M, N, and P */
size_t bytesForM = m * k * sizeof(float);
size_t bytesForN = k * n * sizeof(float);
size_t bytesForP = m * n * sizeof(float);
/* Allocate host memory for matrices */
float *h_M, *h_N, *h_P;
h_M = (float *)malloc(bytesForM);
h_N = (float *)malloc(bytesForN);
h_P = (float *)malloc(bytesForP);
if (h_M == NULL || h_N == NULL || h_P == NULL)
{
fprintf(stderr, "Unable to allocate host memory\n");
return EXIT_FAILURE;
}
/* Allocate device memory for matrices */
float *d_M, *d_N, *d_P;
CUDA_CHECK(hipMalloc((void **)&d_M, bytesForM));
CUDA_CHECK(hipMalloc((void **)&d_N, bytesForN));
CUDA_CHECK(hipMalloc((void **)&d_P, bytesForP));
/* Fill M and N with random numbers (on host) */
srand(SEED);
for (int i = 0; i < m*k; ++i)
h_M[i] = rand()/(float)RAND_MAX*10.0;
for (int i = 0; i < k*n; ++i)
h_N[i] = rand()/(float)RAND_MAX*10.0;
if (m <= 5 && k <= 5 && n <= 5)
{
printf("M =\n"); printMatrix(h_M, m, k);
printf("N =\n"); printMatrix(h_N, k, n);
}
/* Copy M and N to device global memory */
CUDA_CHECK(hipMemcpy(d_M, h_M, bytesForM, hipMemcpyHostToDevice));
CUDA_CHECK(hipMemcpy(d_N, h_N, bytesForN, hipMemcpyHostToDevice));
/* Launch the CUDA kernel */
dim3 dimGrid((n+TILE_WIDTH-1)/TILE_WIDTH, (m+TILE_WIDTH-1)/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
printf("matMul called from host");
matMul<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, m, k, n);
CUDA_CHECK(hipDeviceSynchronize());
/* Copy result matrix from device global memory back to host memory */
CUDA_CHECK(hipMemcpy(h_P, d_P, bytesForP, hipMemcpyDeviceToHost));
printf(" product received from host");
if (m <= 5 && k <= 5 && n <= 5)
{
printf("P =\n"); printMatrix(h_P, m, n);
}
/* Verify that the result matrix is correct */
for (int row = 0; row < m; row++)
{
for (int col = 0; col < n; col++)
{
float expected = 0.0;
for (int i = 0; i < k; i++)
{
expected += h_M[row*k+i] * h_N[i*n+col];
}
float actual = h_P[row*n+col];
if (fabs(expected - actual) > EPSILON)
{
fprintf(stderr, "d_P[%d, %d] is incorrect\n",
row, col);
fprintf(stderr, " Expected: %f\n", expected);
fprintf(stderr, " Computed: %f\n", actual);
return EXIT_FAILURE;
}
}
}
/* Free device global memory */
CUDA_CHECK(hipFree(d_M));
CUDA_CHECK(hipFree(d_N));
CUDA_CHECK(hipFree(d_P));
/* Free host memory */
free(h_M);
free(h_N);
free(h_P);
/* Reset the device (unnecessary if not profiling, but good practice) */
CUDA_CHECK(hipDeviceReset());
printf("Done\n");
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Tiled Matrix Multiplication
* (MP2, Fall 2014, GPU Programming/Auburn University)
*
* Compile with -DTILE_WIDTH=16 (for example) to change the tile size.
* Compile with -DSEED=12 (for example) to seed the random number generator.
*/
#include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
/* Usage message displayed when invalid command line arguments are supplied */
#define USAGE \
"MP2 generates a random (m x k) matrix M and (k x n) matrix N\n" \
"and multiplies M by N using tiled matrix multiplication.\n" \
"The values of m, k, and n must be >= 1.\n" \
"\n" \
"Usage: mp2 m k n\n"
/* Tile size -- define here if not defined using the -D compiler flag */
#ifndef TILE_WIDTH
# define TILE_WIDTH 16
#endif
/* Seed for the random number generator -- define here if not using -D */
#ifndef SEED
# define SEED 1
#endif
/* Maximum difference allowed between the GPU and CPU result matrices */
#define EPSILON 1e-2
/* If a CUDA call fails, display an error message and exit */
#define CUDA_CHECK(e) { \
hipError_t err = (e); \
if (err != hipSuccess) \
{ \
fprintf(stderr, "CUDA error: %s, line %d, %s: %s\n", \
__FILE__, __LINE__, #e, hipGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
/* assert() is only supported on devices of compute capability >= 2.0 */
#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ < 200)
# undef assert
# define assert(arg)
#endif
/* Tiled matrix multiplication kernel */
__global__ static void matMul(float *d_M, float *d_N, float *d_P,
int m, int k, int n)
{
assert(blockDim.x == TILE_WIDTH && blockDim.y == TILE_WIDTH);
/*
*
*
* TODO: IMPLEMENT TILED MATRIX MULTIPLICATION
*
* Multiply matrix d_M by d_N, storing product in d_P.
* Use tiled matrix multiplication with shared memory.
*
*
*/
//__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
//__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x, ty = threadIdx.y;
int row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int col= blockIdx.x * TILE_WIDTH + threadIdx.x;
float sum = 0;
//double numberoftiles =ceil(m/TILE_WIDTH);
if (m == k== n) {
for (int l=0;l<m/TILE_WIDTH ; ++l) { //iterate through tiles
for (int j=0; j< TILE_WIDTH ; ++j) { //iterate through elements in the tile
sum = sum + d_M[(row*m) + ( l*TILE_WIDTH+j)] * d_N[(l*TILE_WIDTH+j)*m + col ];
}
__syncthreads();
}
d_P[row*m +col] = sum;
} else {
for (int l=0;l<ceil((float) k/TILE_WIDTH) ; ++l) { //iterate through tiles
if (row < m && l * TILE_WIDTH + tx < k)
ds_A[ty][tx] = d_M[row *k + l * TILE_WIDTH + tx];
else
ds_A[ty][tx] = 0.0;
if (l * TILE_WIDTH + ty < k && col < n)
ds_B[ty][tx] = d_N[(l * TILE_WIDTH + ty) *n + col];
else
ds_B[ty][tx] = 0.0;
__syncthreads();
for (int j=0; j< TILE_WIDTH && j < k ; ++j) { //iterate through elements in the tile
sum = sum + ds_A[ty][j] * ds_B[j][tx];
}
__syncthreads();
}
if (row < m && col < n)
d_P[row*n+col] =sum;
}
}
/* Displays one row of the given matrix */
static void printRow(int row, float *matrix, int cols)
{
printf("[");
if (cols >= 1) printf(" %3.3f", matrix[row*cols+0]);
if (cols >= 2) printf(" %3.3f", matrix[row*cols+1]);
if (cols >= 3) printf(" %3.3f", matrix[row*cols+2]);
if (cols >= 6) printf(" ...");
if (cols >= 5) printf(" %3.3f", matrix[row*cols+(cols-2)]);
if (cols >= 4) printf(" %3.3f", matrix[row*cols+(cols-1)]);
printf(" ]\n");
}
/* Displays the given matrix */
static void printMatrix(float *matrix, int rows, int cols)
{
if (rows >= 1) printRow(0, matrix, cols);
if (rows >= 2) printRow(1, matrix, cols);
if (rows >= 3) printRow(2, matrix, cols);
if (rows >= 6) printf(" ...\n");
if (rows >= 5) printRow(rows-2, matrix, cols);
if (rows >= 4) printRow(rows-1, matrix, cols);
}
/* Program entrypoint. Invoke with three command line arguments: m k n */
int main(int argc, char **argv)
{
/* Get command line arguments; save as m, k, and n */
if (argc != 4)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Expected 3 arguments; received %d.\n", argc-1);
return EXIT_FAILURE;
}
int m = atoi(argv[1]);
int k = atoi(argv[2]);
int n = atoi(argv[3]);
if (m < 1 || k < 1 || n < 1)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Invalid value for m, k, or n (%d, %d, %d)\n",
m, k, n);
return EXIT_FAILURE;
}
printf("Multiplying MN = P. M is (%d x %d); N is (%d x %d); ",
m, k, k, n);
printf("using (%d x %d) tiles.\n", TILE_WIDTH, TILE_WIDTH);
/********************************************/
/* M is (m x k), N is (k x n), P is (m x n) */
/********************************************/
/* Compute number of bytes needed to stores matrices M, N, and P */
size_t bytesForM = m * k * sizeof(float);
size_t bytesForN = k * n * sizeof(float);
size_t bytesForP = m * n * sizeof(float);
/* Allocate host memory for matrices */
float *h_M, *h_N, *h_P;
h_M = (float *)malloc(bytesForM);
h_N = (float *)malloc(bytesForN);
h_P = (float *)malloc(bytesForP);
if (h_M == NULL || h_N == NULL || h_P == NULL)
{
fprintf(stderr, "Unable to allocate host memory\n");
return EXIT_FAILURE;
}
/* Allocate device memory for matrices */
float *d_M, *d_N, *d_P;
CUDA_CHECK(hipMalloc((void **)&d_M, bytesForM));
CUDA_CHECK(hipMalloc((void **)&d_N, bytesForN));
CUDA_CHECK(hipMalloc((void **)&d_P, bytesForP));
/* Fill M and N with random numbers (on host) */
srand(SEED);
for (int i = 0; i < m*k; ++i)
h_M[i] = rand()/(float)RAND_MAX*10.0;
for (int i = 0; i < k*n; ++i)
h_N[i] = rand()/(float)RAND_MAX*10.0;
if (m <= 5 && k <= 5 && n <= 5)
{
printf("M =\n"); printMatrix(h_M, m, k);
printf("N =\n"); printMatrix(h_N, k, n);
}
/* Copy M and N to device global memory */
CUDA_CHECK(hipMemcpy(d_M, h_M, bytesForM, hipMemcpyHostToDevice));
CUDA_CHECK(hipMemcpy(d_N, h_N, bytesForN, hipMemcpyHostToDevice));
/* Launch the CUDA kernel */
dim3 dimGrid((n+TILE_WIDTH-1)/TILE_WIDTH, (m+TILE_WIDTH-1)/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
printf("matMul called from host");
matMul<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, m, k, n);
CUDA_CHECK(hipDeviceSynchronize());
/* Copy result matrix from device global memory back to host memory */
CUDA_CHECK(hipMemcpy(h_P, d_P, bytesForP, hipMemcpyDeviceToHost));
printf(" product received from host");
if (m <= 5 && k <= 5 && n <= 5)
{
printf("P =\n"); printMatrix(h_P, m, n);
}
/* Verify that the result matrix is correct */
for (int row = 0; row < m; row++)
{
for (int col = 0; col < n; col++)
{
float expected = 0.0;
for (int i = 0; i < k; i++)
{
expected += h_M[row*k+i] * h_N[i*n+col];
}
float actual = h_P[row*n+col];
if (fabs(expected - actual) > EPSILON)
{
fprintf(stderr, "d_P[%d, %d] is incorrect\n",
row, col);
fprintf(stderr, " Expected: %f\n", expected);
fprintf(stderr, " Computed: %f\n", actual);
return EXIT_FAILURE;
}
}
}
/* Free device global memory */
CUDA_CHECK(hipFree(d_M));
CUDA_CHECK(hipFree(d_N));
CUDA_CHECK(hipFree(d_P));
/* Free host memory */
free(h_M);
free(h_N);
free(h_P);
/* Reset the device (unnecessary if not profiling, but good practice) */
CUDA_CHECK(hipDeviceReset());
printf("Done\n");
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL6matMulPfS_S_iii,"axG",@progbits,_ZL6matMulPfS_S_iii,comdat
.globl _ZL6matMulPfS_S_iii
.p2align 8
.type _ZL6matMulPfS_S_iii,@function
_ZL6matMulPfS_S_iii:
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v5, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 4, v5
v_lshl_add_u32 v0, s14, 4, v1
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s8, s9
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, 0, 1, s2
v_cmp_eq_u32_e32 vcc_lo, s10, v2
s_cbranch_vccnz .LBB0_16
v_cvt_f32_i32_e32 v2, s9
v_cmp_gt_i32_e64 s2, s8, v4
v_cmp_gt_i32_e64 s3, s10, v0
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_mul_f32 v2, 0x3d800000, v2
v_ceil_f32_e32 v6, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nlt_f32_e32 vcc_lo, 0, v6
s_cbranch_vccnz .LBB0_17
v_lshlrev_b32_e32 v9, 2, v1
v_lshlrev_b32_e32 v7, 6, v5
s_cmp_gt_i32 s9, 0
v_mad_u64_u32 v[2:3], null, v4, s9, v[1:2]
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v8, 0x400, v9
s_cselect_b32 s13, -1, 0
s_add_i32 s14, s9, -1
v_cmp_le_i32_e64 s12, s8, v4
v_add_nc_u32_e32 v9, v7, v9
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v10, v8, v7
s_min_u32 s14, s14, 15
s_xor_b32 s3, s3, -1
s_add_i32 s14, s14, 1
s_branch .LBB0_4
.LBB0_3:
s_add_i32 s11, s11, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v13, s11
s_barrier
buffer_gl0_inv
v_cmp_ngt_f32_e32 vcc_lo, v6, v13
s_cbranch_vccnz .LBB0_17
.LBB0_4:
s_mov_b32 s15, 0
s_mov_b32 s17, s12
s_and_saveexec_b32 s16, s2
s_lshl_b32 s17, s11, 4
s_mov_b32 s15, exec_lo
v_add_nc_u32_e32 v12, s17, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s9, v12
v_mov_b32_e32 v12, s17
s_and_not1_b32 s17, s12, exec_lo
s_and_b32 s18, vcc_lo, exec_lo
s_or_b32 s17, s17, s18
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s16, exec_lo, s16
s_cbranch_execz .LBB0_8
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v9, v11
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_10
v_add_nc_u32_e32 v13, v2, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v13
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s16
v_lshl_add_u32 v13, s11, 4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s9, v13
s_or_b32 s15, s3, vcc_lo
s_and_saveexec_b32 s16, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s15, exec_lo, s16
s_cbranch_execz .LBB0_12
ds_store_b32 v10, v11
.LBB0_12:
s_and_not1_saveexec_b32 s15, s15
s_cbranch_execz .LBB0_14
v_mad_u64_u32 v[14:15], null, v13, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[13:14], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, s6, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v13
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s15
v_dual_mov_b32 v13, v8 :: v_dual_mov_b32 v14, v7
s_and_not1_b32 vcc_lo, exec_lo, s13
s_mov_b32 s15, s14
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_3
.LBB0_15:
ds_load_b32 v15, v14
ds_load_b32 v16, v13
v_add_nc_u32_e32 v14, 4, v14
v_add_nc_u32_e32 v13, 64, v13
s_add_i32 s15, s15, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s15, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, v15, v16
s_cbranch_scc0 .LBB0_15
s_branch .LBB0_3
.LBB0_16:
s_mov_b32 s2, 0
s_cbranch_execnz .LBB0_18
s_branch .LBB0_24
.LBB0_17:
v_cmp_gt_i32_e32 vcc_lo, s8, v4
v_cmp_gt_i32_e64 s2, s10, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s2, vcc_lo, s2
s_branch .LBB0_24
.LBB0_18:
v_mov_b32_e32 v3, 0
s_cmp_lt_i32 s8, 16
s_cbranch_scc1 .LBB0_23
v_mul_lo_u32 v1, v4, s8
s_ashr_i32 s2, s8, 31
v_mov_b32_e32 v3, 0
s_lshr_b32 s2, s2, 28
v_mov_b32_e32 v7, v0
s_add_i32 s2, s8, s2
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
s_ashr_i32 s4, s2, 4
s_lshl_b32 s5, s8, 4
.p2align 6
.LBB0_20:
v_mov_b32_e32 v1, v7
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_21:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_add_co_u32 v8, vcc_lo, v5, s2
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[10:11], 2, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 64
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b32 v2, v[8:9], off
global_load_b32 v8, v[10:11], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v2, v8
s_cbranch_scc0 .LBB0_21
v_add_co_u32 v5, vcc_lo, v5, 64
v_add_nc_u32_e32 v7, s5, v7
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_20
.LBB0_23:
s_mov_b32 s2, -1
s_mov_b32 s10, s8
.LBB0_24:
s_and_saveexec_b32 s3, s2
s_cbranch_execnz .LBB0_26
s_endpgm
.LBB0_26:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v4, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL6matMulPfS_S_iii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL6matMulPfS_S_iii,"axG",@progbits,_ZL6matMulPfS_S_iii,comdat
.Lfunc_end0:
.size _ZL6matMulPfS_S_iii, .Lfunc_end0-_ZL6matMulPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL6matMulPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _ZL6matMulPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Tiled Matrix Multiplication
* (MP2, Fall 2014, GPU Programming/Auburn University)
*
* Compile with -DTILE_WIDTH=16 (for example) to change the tile size.
* Compile with -DSEED=12 (for example) to seed the random number generator.
*/
#include <assert.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
/* Usage message displayed when invalid command line arguments are supplied */
#define USAGE \
"MP2 generates a random (m x k) matrix M and (k x n) matrix N\n" \
"and multiplies M by N using tiled matrix multiplication.\n" \
"The values of m, k, and n must be >= 1.\n" \
"\n" \
"Usage: mp2 m k n\n"
/* Tile size -- define here if not defined using the -D compiler flag */
#ifndef TILE_WIDTH
# define TILE_WIDTH 16
#endif
/* Seed for the random number generator -- define here if not using -D */
#ifndef SEED
# define SEED 1
#endif
/* Maximum difference allowed between the GPU and CPU result matrices */
#define EPSILON 1e-2
/* If a CUDA call fails, display an error message and exit */
#define CUDA_CHECK(e) { \
hipError_t err = (e); \
if (err != hipSuccess) \
{ \
fprintf(stderr, "CUDA error: %s, line %d, %s: %s\n", \
__FILE__, __LINE__, #e, hipGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
/* assert() is only supported on devices of compute capability >= 2.0 */
#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ < 200)
# undef assert
# define assert(arg)
#endif
/* Tiled matrix multiplication kernel */
__global__ static void matMul(float *d_M, float *d_N, float *d_P,
int m, int k, int n)
{
assert(blockDim.x == TILE_WIDTH && blockDim.y == TILE_WIDTH);
/*
*
*
* TODO: IMPLEMENT TILED MATRIX MULTIPLICATION
*
* Multiply matrix d_M by d_N, storing product in d_P.
* Use tiled matrix multiplication with shared memory.
*
*
*/
//__shared__ float Mds[TILE_WIDTH][TILE_WIDTH];
//__shared__ float Nds[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int tx = threadIdx.x, ty = threadIdx.y;
int row = blockIdx.y * TILE_WIDTH + threadIdx.y;
int col= blockIdx.x * TILE_WIDTH + threadIdx.x;
float sum = 0;
//double numberoftiles =ceil(m/TILE_WIDTH);
if (m == k== n) {
for (int l=0;l<m/TILE_WIDTH ; ++l) { //iterate through tiles
for (int j=0; j< TILE_WIDTH ; ++j) { //iterate through elements in the tile
sum = sum + d_M[(row*m) + ( l*TILE_WIDTH+j)] * d_N[(l*TILE_WIDTH+j)*m + col ];
}
__syncthreads();
}
d_P[row*m +col] = sum;
} else {
for (int l=0;l<ceil((float) k/TILE_WIDTH) ; ++l) { //iterate through tiles
if (row < m && l * TILE_WIDTH + tx < k)
ds_A[ty][tx] = d_M[row *k + l * TILE_WIDTH + tx];
else
ds_A[ty][tx] = 0.0;
if (l * TILE_WIDTH + ty < k && col < n)
ds_B[ty][tx] = d_N[(l * TILE_WIDTH + ty) *n + col];
else
ds_B[ty][tx] = 0.0;
__syncthreads();
for (int j=0; j< TILE_WIDTH && j < k ; ++j) { //iterate through elements in the tile
sum = sum + ds_A[ty][j] * ds_B[j][tx];
}
__syncthreads();
}
if (row < m && col < n)
d_P[row*n+col] =sum;
}
}
/* Displays one row of the given matrix */
static void printRow(int row, float *matrix, int cols)
{
printf("[");
if (cols >= 1) printf(" %3.3f", matrix[row*cols+0]);
if (cols >= 2) printf(" %3.3f", matrix[row*cols+1]);
if (cols >= 3) printf(" %3.3f", matrix[row*cols+2]);
if (cols >= 6) printf(" ...");
if (cols >= 5) printf(" %3.3f", matrix[row*cols+(cols-2)]);
if (cols >= 4) printf(" %3.3f", matrix[row*cols+(cols-1)]);
printf(" ]\n");
}
/* Displays the given matrix */
static void printMatrix(float *matrix, int rows, int cols)
{
if (rows >= 1) printRow(0, matrix, cols);
if (rows >= 2) printRow(1, matrix, cols);
if (rows >= 3) printRow(2, matrix, cols);
if (rows >= 6) printf(" ...\n");
if (rows >= 5) printRow(rows-2, matrix, cols);
if (rows >= 4) printRow(rows-1, matrix, cols);
}
/* Program entrypoint. Invoke with three command line arguments: m k n */
int main(int argc, char **argv)
{
/* Get command line arguments; save as m, k, and n */
if (argc != 4)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Expected 3 arguments; received %d.\n", argc-1);
return EXIT_FAILURE;
}
int m = atoi(argv[1]);
int k = atoi(argv[2]);
int n = atoi(argv[3]);
if (m < 1 || k < 1 || n < 1)
{
fprintf(stderr, USAGE);
fprintf(stderr, "Invalid value for m, k, or n (%d, %d, %d)\n",
m, k, n);
return EXIT_FAILURE;
}
printf("Multiplying MN = P. M is (%d x %d); N is (%d x %d); ",
m, k, k, n);
printf("using (%d x %d) tiles.\n", TILE_WIDTH, TILE_WIDTH);
/********************************************/
/* M is (m x k), N is (k x n), P is (m x n) */
/********************************************/
/* Compute number of bytes needed to stores matrices M, N, and P */
size_t bytesForM = m * k * sizeof(float);
size_t bytesForN = k * n * sizeof(float);
size_t bytesForP = m * n * sizeof(float);
/* Allocate host memory for matrices */
float *h_M, *h_N, *h_P;
h_M = (float *)malloc(bytesForM);
h_N = (float *)malloc(bytesForN);
h_P = (float *)malloc(bytesForP);
if (h_M == NULL || h_N == NULL || h_P == NULL)
{
fprintf(stderr, "Unable to allocate host memory\n");
return EXIT_FAILURE;
}
/* Allocate device memory for matrices */
float *d_M, *d_N, *d_P;
CUDA_CHECK(hipMalloc((void **)&d_M, bytesForM));
CUDA_CHECK(hipMalloc((void **)&d_N, bytesForN));
CUDA_CHECK(hipMalloc((void **)&d_P, bytesForP));
/* Fill M and N with random numbers (on host) */
srand(SEED);
for (int i = 0; i < m*k; ++i)
h_M[i] = rand()/(float)RAND_MAX*10.0;
for (int i = 0; i < k*n; ++i)
h_N[i] = rand()/(float)RAND_MAX*10.0;
if (m <= 5 && k <= 5 && n <= 5)
{
printf("M =\n"); printMatrix(h_M, m, k);
printf("N =\n"); printMatrix(h_N, k, n);
}
/* Copy M and N to device global memory */
CUDA_CHECK(hipMemcpy(d_M, h_M, bytesForM, hipMemcpyHostToDevice));
CUDA_CHECK(hipMemcpy(d_N, h_N, bytesForN, hipMemcpyHostToDevice));
/* Launch the CUDA kernel */
dim3 dimGrid((n+TILE_WIDTH-1)/TILE_WIDTH, (m+TILE_WIDTH-1)/TILE_WIDTH);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH);
printf("matMul called from host");
matMul<<<dimGrid, dimBlock>>>(d_M, d_N, d_P, m, k, n);
CUDA_CHECK(hipDeviceSynchronize());
/* Copy result matrix from device global memory back to host memory */
CUDA_CHECK(hipMemcpy(h_P, d_P, bytesForP, hipMemcpyDeviceToHost));
printf(" product received from host");
if (m <= 5 && k <= 5 && n <= 5)
{
printf("P =\n"); printMatrix(h_P, m, n);
}
/* Verify that the result matrix is correct */
for (int row = 0; row < m; row++)
{
for (int col = 0; col < n; col++)
{
float expected = 0.0;
for (int i = 0; i < k; i++)
{
expected += h_M[row*k+i] * h_N[i*n+col];
}
float actual = h_P[row*n+col];
if (fabs(expected - actual) > EPSILON)
{
fprintf(stderr, "d_P[%d, %d] is incorrect\n",
row, col);
fprintf(stderr, " Expected: %f\n", expected);
fprintf(stderr, " Computed: %f\n", actual);
return EXIT_FAILURE;
}
}
}
/* Free device global memory */
CUDA_CHECK(hipFree(d_M));
CUDA_CHECK(hipFree(d_N));
CUDA_CHECK(hipFree(d_P));
/* Free host memory */
free(h_M);
free(h_N);
free(h_P);
/* Reset the device (unnecessary if not profiling, but good practice) */
CUDA_CHECK(hipDeviceReset());
printf("Done\n");
return EXIT_SUCCESS;
} | .text
.file "mp2.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x41200000 # float 10
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_3:
.quad 0x3f847ae147ae147b # double 0.01
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $4, %edi
jne .LBB0_1
# %bb.2:
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
movq %r15, 16(%rsp) # 8-byte Spill
testl %r15d, %r15d
jle .LBB0_5
# %bb.3:
testl %ebx, %ebx
jle .LBB0_5
# %bb.4:
cmpl $0, 8(%rsp) # 4-byte Folded Reload
jle .LBB0_5
# %bb.6:
movl $.L.str.3, %edi
movq 16(%rsp), %r13 # 8-byte Reload
movl %r13d, %esi
movq %rbx, %r15
movl %r15d, %edx
movl %r15d, %ecx
movq 8(%rsp), %r12 # 8-byte Reload
movl %r12d, %r8d
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl $16, %esi
movl $16, %edx
xorl %eax, %eax
callq printf
movl %r15d, %r14d
imull %r13d, %r14d
movslq %r14d, %rbp
shlq $2, %rbp
movl %r12d, %ebx
movq %r15, 24(%rsp) # 8-byte Spill
imull %r15d, %ebx
movslq %ebx, %r15
shlq $2, %r15
movl %r13d, %eax
imull %r12d, %eax
movslq %eax, %r13
shlq $2, %r13
movq %rbp, %rdi
callq malloc
movq %rax, %r12
movq %r15, 48(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r15
movq %r13, %rdi
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
testq %r12, %r12
je .LBB0_9
# %bb.7:
testq %r15, %r15
je .LBB0_9
# %bb.8:
cmpq $0, 40(%rsp) # 8-byte Folded Reload
je .LBB0_9
# %bb.10:
leaq 72(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_11
# %bb.13:
leaq 64(%rsp), %rdi
movq 48(%rsp), %rsi # 8-byte Reload
callq hipMalloc
testl %eax, %eax
jne .LBB0_14
# %bb.15:
movq %r15, 32(%rsp) # 8-byte Spill
leaq 56(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_16
# %bb.17:
movl $1, %edi
callq srand
testl %r14d, %r14d
jle .LBB0_20
# %bb.18: # %.lr.ph.preheader
movl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_19: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
mulss .LCPI0_1(%rip), %xmm0
movss %xmm0, (%r12,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_19
.LBB0_20: # %.preheader194
testl %ebx, %ebx
movq 32(%rsp), %r15 # 8-byte Reload
jle .LBB0_23
# %bb.21: # %.lr.ph197.preheader
movl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_22: # %.lr.ph197
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
mulss .LCPI0_1(%rip), %xmm0
movss %xmm0, (%r15,%r14,4)
incq %r14
cmpq %r14, %rbx
jne .LBB0_22
.LBB0_23: # %._crit_edge
movq 16(%rsp), %rbx # 8-byte Reload
cmpl $6, %ebx
setl %al
cmpl $6, 24(%rsp) # 4-byte Folded Reload
setl %cl
andb %al, %cl
cmpl $6, 8(%rsp) # 4-byte Folded Reload
setl %r15b
andb %cl, %r15b
je .LBB0_25
# %bb.24:
movl $.Lstr, %edi
callq puts@PLT
movq %r12, %rdi
movl %ebx, %esi
movq 24(%rsp), %rbx # 8-byte Reload
movl %ebx, %edx
callq _ZL11printMatrixPfii
movl $.Lstr.1, %edi
callq puts@PLT
movq 32(%rsp), %rdi # 8-byte Reload
movl %ebx, %esi
movq 16(%rsp), %rbx # 8-byte Reload
movq 8(%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
callq _ZL11printMatrixPfii
.LBB0_25:
movq 72(%rsp), %rdi
movq %r12, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_26
# %bb.27:
movq 64(%rsp), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
movq 48(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_28
# %bb.29:
movq 8(%rsp), %rcx # 8-byte Reload
leal 15(%rcx), %eax
addl $30, %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $4, %ecx
leal 15(%rbx), %eax
leal 30(%rbx), %r14d
testl %eax, %eax
cmovnsl %eax, %r14d
sarl $4, %r14d
shlq $32, %r14
orq %rcx, %r14
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_31
# %bb.30:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movq %rax, 216(%rsp)
movq %rcx, 208(%rsp)
movq %rdx, 200(%rsp)
movl %ebx, 100(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movl %eax, 96(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 92(%rsp)
leaq 216(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rax
movq %rax, 232(%rsp)
leaq 200(%rsp), %rax
movq %rax, 240(%rsp)
leaq 100(%rsp), %rax
movq %rax, 248(%rsp)
leaq 96(%rsp), %rax
movq %rax, 256(%rsp)
leaq 92(%rsp), %rax
movq %rax, 264(%rsp)
leaq 184(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 184(%rsp), %rsi
movl 192(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_ZL6matMulPfS_S_iii, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_31:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_32
# %bb.33:
movq 56(%rsp), %rsi
movq 40(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_34
# %bb.35:
movl $.L.str.18, %edi
xorl %eax, %eax
callq printf
testb %r15b, %r15b
je .LBB0_37
# %bb.36:
movl $.Lstr.2, %edi
callq puts@PLT
movq 40(%rsp), %rdi # 8-byte Reload
movl %ebx, %esi
movq 8(%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
callq _ZL11printMatrixPfii
.LBB0_37:
testl %ebx, %ebx
setg 7(%rsp) # 1-byte Folded Spill
jle .LBB0_38
# %bb.42: # %.preheader193.lr.ph
movq 8(%rsp), %rax # 8-byte Reload
testl %eax, %eax
setg 6(%rsp) # 1-byte Folded Spill
movslq %eax, %rsi
movq 24(%rsp), %r9 # 8-byte Reload
movslq %r9d, %rax
movl %ebx, %ecx
movq %rcx, 128(%rsp) # 8-byte Spill
movl %esi, %r8d
movl %eax, %r15d
shlq $2, %rax
movq %rax, 136(%rsp) # 8-byte Spill
leaq (,%rsi,4), %rbx
movaps .LCPI0_2(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movsd .LCPI0_3(%rip), %xmm2 # xmm2 = mem[0],zero
movq %r12, %rbp
xorl %edx, %edx
xorl %edi, %edi
movq %r12, 104(%rsp) # 8-byte Spill
movq %rsi, 120(%rsp) # 8-byte Spill
movq %r8, 112(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB0_44: # %.preheader193
# =>This Loop Header: Depth=1
# Child Loop BB0_50 Depth 2
# Child Loop BB0_55 Depth 3
cmpl $0, 8(%rsp) # 4-byte Folded Reload
jle .LBB0_45
# %bb.48: # %.preheader.lr.ph
# in Loop: Header=BB0_44 Depth=1
movq %rdx, %rax
imulq %rsi, %rax
movq 40(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r10
movq 32(%rsp), %r13 # 8-byte Reload
xorl %r14d, %r14d
movzbl 6(%rsp), %r12d # 1-byte Folded Reload
.p2align 4, 0x90
.LBB0_50: # %.preheader
# Parent Loop BB0_44 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_55 Depth 3
xorps %xmm3, %xmm3
testl %r9d, %r9d
jle .LBB0_51
# %bb.54: # %.lr.ph200.preheader
# in Loop: Header=BB0_50 Depth=2
movq %r13, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_55: # %.lr.ph200
# Parent Loop BB0_44 Depth=1
# Parent Loop BB0_50 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rbp,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rax), %xmm0
addss %xmm0, %xmm3
incq %rcx
addq %rbx, %rax
cmpq %rcx, %r15
jne .LBB0_55
.LBB0_51: # %._crit_edge201
# in Loop: Header=BB0_50 Depth=2
movss (%r10,%r14,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
movaps %xmm3, %xmm0
subss %xmm4, %xmm0
andps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm2, %xmm0
ja .LBB0_52
.LBB0_53: # in Loop: Header=BB0_50 Depth=2
ucomisd %xmm2, %xmm0
ja .LBB0_46
# %bb.49: # in Loop: Header=BB0_50 Depth=2
incq %r14
cmpq %rsi, %r14
setl %r12b
addq $4, %r13
cmpq %r8, %r14
jne .LBB0_50
jmp .LBB0_46
.LBB0_52: # in Loop: Header=BB0_50 Depth=2
movq stderr(%rip), %rdi
movl $.L.str.20, %esi
movl %r14d, %ecx
xorl %eax, %eax
movq %rdx, 16(%rsp) # 8-byte Spill
movq %r10, 48(%rsp) # 8-byte Spill
movss %xmm3, 84(%rsp) # 4-byte Spill
movsd %xmm0, 144(%rsp) # 8-byte Spill
movss %xmm4, 88(%rsp) # 4-byte Spill
callq fprintf
movq stderr(%rip), %rdi
movss 84(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.21, %esi
movb $1, %al
callq fprintf
movq stderr(%rip), %rdi
movss 88(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.22, %esi
movb $1, %al
callq fprintf
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movq 48(%rsp), %r10 # 8-byte Reload
movq 16(%rsp), %rdx # 8-byte Reload
movsd .LCPI0_3(%rip), %xmm2 # xmm2 = mem[0],zero
movaps .LCPI0_2(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movq 112(%rsp), %r8 # 8-byte Reload
movq 120(%rsp), %rsi # 8-byte Reload
movq 24(%rsp), %r9 # 8-byte Reload
movl $1, %edi
jmp .LBB0_53
.p2align 4, 0x90
.LBB0_45: # in Loop: Header=BB0_44 Depth=1
movzbl 6(%rsp), %r12d # 1-byte Folded Reload
.LBB0_46: # %._crit_edge206
# in Loop: Header=BB0_44 Depth=1
testb $1, %r12b
jne .LBB0_47
# %bb.43: # in Loop: Header=BB0_44 Depth=1
incq %rdx
movq 128(%rsp), %rax # 8-byte Reload
cmpq %rax, %rdx
setb 7(%rsp) # 1-byte Folded Spill
addq 136(%rsp), %rbp # 8-byte Folded Reload
cmpq %rax, %rdx
movq 104(%rsp), %r12 # 8-byte Reload
jne .LBB0_44
jmp .LBB0_39
.LBB0_38:
xorl %edi, %edi
.LBB0_39: # %._crit_edge216
testb $1, 7(%rsp) # 1-byte Folded Reload
je .LBB0_40
jmp .LBB0_63
.LBB0_47:
movq 104(%rsp), %r12 # 8-byte Reload
testb $1, 7(%rsp) # 1-byte Folded Reload
jne .LBB0_63
.LBB0_40:
movq 72(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_41
# %bb.56:
movq 64(%rsp), %rdi
callq hipFree
testl %eax, %eax
movq 32(%rsp), %rbx # 8-byte Reload
jne .LBB0_57
# %bb.58:
movq 56(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_59
# %bb.60:
movq %r12, %rdi
callq free
movq %rbx, %rdi
callq free
movq 40(%rsp), %rdi # 8-byte Reload
callq free
callq hipDeviceReset
testl %eax, %eax
jne .LBB0_61
# %bb.62:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %edi, %edi
.LBB0_63:
movl %edi, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 336
movq stderr(%rip), %rcx
movl %edi, %ebx
movl $.L.str, %edi
movl $176, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rdi
decl %ebx
movl $.L.str.1, %esi
movl %ebx, %edx
xorl %eax, %eax
callq fprintf
movl $1, %edi
jmp .LBB0_63
.LBB0_5:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $176, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rdi
movl $.L.str.2, %esi
movq 16(%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movl %ebx, %ecx
movq 8(%rsp), %r8 # 8-byte Reload
# kill: def $r8d killed $r8d killed $r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
jmp .LBB0_63
.LBB0_9:
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $31, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
jmp .LBB0_63
.LBB0_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movl $.L.str.8, %r8d
movq %rbx, %rdi
movl $216, %ecx
jmp .LBB0_12
.LBB0_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movl $.L.str.9, %r8d
movq %rbx, %rdi
movl $217, %ecx
jmp .LBB0_12
.LBB0_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movl $.L.str.10, %r8d
movq %rbx, %rdi
movl $218, %ecx
jmp .LBB0_12
.LBB0_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movl $.L.str.13, %r8d
movq %rbx, %rdi
movl $234, %ecx
jmp .LBB0_12
.LBB0_28:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movl $.L.str.14, %r8d
movq %rbx, %rdi
movl $235, %ecx
jmp .LBB0_12
.LBB0_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movl $.L.str.16, %r8d
movq %rbx, %rdi
movl $244, %ecx
jmp .LBB0_12
.LBB0_34:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movl $.L.str.17, %r8d
movq %rbx, %rdi
movl $247, %ecx
jmp .LBB0_12
.LBB0_41:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movl $.L.str.23, %r8d
movq %rbx, %rdi
movl $281, %ecx # imm = 0x119
jmp .LBB0_12
.LBB0_57:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movl $.L.str.24, %r8d
movq %rbx, %rdi
movl $282, %ecx # imm = 0x11A
jmp .LBB0_12
.LBB0_59:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movl $.L.str.25, %r8d
movq %rbx, %rdi
movl $283, %ecx # imm = 0x11B
jmp .LBB0_12
.LBB0_61:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
movl $.L.str.7, %edx
movl $.L.str.26, %r8d
movq %rbx, %rdi
movl $291, %ecx # imm = 0x123
.LBB0_12:
movq %rax, %r9
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL11printMatrixPfii
.type _ZL11printMatrixPfii,@function
_ZL11printMatrixPfii: # @_ZL11printMatrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
xorl %edi, %edi
movq %r14, %rsi
callq _ZL8printRowiPfi
cmpl $2, %ebp
jge .LBB1_1
# %bb.2:
cmpl $3, %ebp
jge .LBB1_3
.LBB1_4:
cmpl $5, %ebp
jge .LBB1_5
.LBB1_6:
cmpl $4, %ebp
jl .LBB1_7
.LBB1_8:
decl %ebp
movl %ebp, %edi
movq %r14, %rsi
movl %ebx, %edx
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZL8printRowiPfi # TAILCALL
.LBB1_1:
.cfi_def_cfa_offset 32
movl $1, %edi
movq %r14, %rsi
movl %ebx, %edx
callq _ZL8printRowiPfi
cmpl $3, %ebp
jl .LBB1_4
.LBB1_3:
movl $2, %edi
movq %r14, %rsi
movl %ebx, %edx
callq _ZL8printRowiPfi
cmpl $5, %ebp
jl .LBB1_6
.LBB1_5:
movl $3, %edi
movq %r14, %rsi
movl %ebx, %edx
callq _ZL8printRowiPfi
cmpl $4, %ebp
jge .LBB1_8
.LBB1_7:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _ZL11printMatrixPfii, .Lfunc_end1-_ZL11printMatrixPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL21__device_stub__matMulPfS_S_iii
.type _ZL21__device_stub__matMulPfS_S_iii,@function
_ZL21__device_stub__matMulPfS_S_iii: # @_ZL21__device_stub__matMulPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZL6matMulPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _ZL21__device_stub__matMulPfS_S_iii, .Lfunc_end2-_ZL21__device_stub__matMulPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL8printRowiPfi
.type _ZL8printRowiPfi,@function
_ZL8printRowiPfi: # @_ZL8printRowiPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %r14d
movq %rsi, %rbx
movl %edi, %r15d
movl $91, %edi
callq putchar@PLT
movl %r14d, %r12d
imull %r15d, %r12d
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.30, %edi
movb $1, %al
callq printf
movslq %r12d, %r13
cmpl $2, %r14d
jge .LBB3_1
# %bb.2:
cmpl $3, %r14d
jge .LBB3_3
.LBB3_4:
cmpl $5, %r14d
jge .LBB3_5
.LBB3_6:
cmpl $4, %r14d
jl .LBB3_8
.LBB3_7:
leal (%r14,%r12), %eax
decl %eax
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.30, %edi
movb $1, %al
callq printf
.LBB3_8:
movl $.Lstr.4, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB3_1:
.cfi_def_cfa_offset 48
movss 4(%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.30, %edi
movb $1, %al
callq printf
cmpl $3, %r14d
jl .LBB3_4
.LBB3_3:
movss 8(%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.30, %edi
movb $1, %al
callq printf
cmpl $5, %r14d
jl .LBB3_6
.LBB3_5:
leal (%r15,%r15,4), %eax
cltq
movss 12(%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.30, %edi
movb $1, %al
callq printf
cmpl $4, %r14d
jge .LBB3_7
jmp .LBB3_8
.Lfunc_end3:
.size _ZL8printRowiPfi, .Lfunc_end3-_ZL8printRowiPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL6matMulPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "MP2 generates a random (m x k) matrix M and (k x n) matrix N\nand multiplies M by N using tiled matrix multiplication.\nThe values of m, k, and n must be >= 1.\n\nUsage: mp2 m k n\n"
.size .L.str, 177
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Expected 3 arguments
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Invalid value for m, k, or n (%d, %d, %d)\n"
.size .L.str.2, 43
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Multiplying MN = P. M is (%d x %d)
.size .L.str.3, 54
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "using (%d x %d) tiles.\n"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Unable to allocate host memory\n"
.size .L.str.5, 32
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CUDA error: %s, line %d, %s: %s\n"
.size .L.str.6, 33
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/venkateshreddy74/Tiled-Matrix-Multiplication-for-Square-and-Non-Square-Matrices/master/mp2.hip"
.size .L.str.7, 152
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMalloc((void **)&d_M, bytesForM)"
.size .L.str.8, 36
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipMalloc((void **)&d_N, bytesForN)"
.size .L.str.9, 36
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipMalloc((void **)&d_P, bytesForP)"
.size .L.str.10, 36
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hipMemcpy(d_M, h_M, bytesForM, hipMemcpyHostToDevice)"
.size .L.str.13, 54
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "hipMemcpy(d_N, h_N, bytesForN, hipMemcpyHostToDevice)"
.size .L.str.14, 54
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "matMul called from host"
.size .L.str.15, 24
.type _ZL6matMulPfS_S_iii,@object # @_ZL6matMulPfS_S_iii
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL6matMulPfS_S_iii:
.quad _ZL21__device_stub__matMulPfS_S_iii
.size _ZL6matMulPfS_S_iii, 8
.type .L.str.16,@object # @.str.16
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.16:
.asciz "hipDeviceSynchronize()"
.size .L.str.16, 23
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "hipMemcpy(h_P, d_P, bytesForP, hipMemcpyDeviceToHost)"
.size .L.str.17, 54
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " product received from host"
.size .L.str.18, 28
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "d_P[%d, %d] is incorrect\n"
.size .L.str.20, 26
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz " Expected: %f\n"
.size .L.str.21, 18
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz " Computed: %f\n"
.size .L.str.22, 18
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "hipFree(d_M)"
.size .L.str.23, 13
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "hipFree(d_N)"
.size .L.str.24, 13
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "hipFree(d_P)"
.size .L.str.25, 13
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "hipDeviceReset()"
.size .L.str.26, 17
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz " %3.3f"
.size .L.str.30, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL6matMulPfS_S_iii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "M ="
.size .Lstr, 4
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "N ="
.size .Lstr.1, 4
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "P ="
.size .Lstr.2, 4
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Done"
.size .Lstr.3, 5
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz " ]"
.size .Lstr.4, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL21__device_stub__matMulPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL6matMulPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <cuda.h>
#include <stdio.h>
#include <malloc.h>
__host__
void fill_vector(float *V, int len){
float aux = 5.0;
for (int i = 0; i < len; i++) {
V[i] = ((float)rand() / (float)(RAND_MAX)) * aux ;
}
}
__host__
void print(float *V, int len){
for (int i = 0; i < len; i++) {
printf("%.2f ", V[i]);
}
printf("\n");
}
__global__
void AddVector(float* d_A, float* d_B, float* d_R, int n){
//calculate row index of element
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n) d_R[i] = d_A[i] + d_B[i];
return;
}
int main(){
int n = 100;
float size = n * sizeof(float);
//Manejo de errores en cuda
cudaError_t error = cudaSuccess;
//CPU
float *h_A, *h_B, *h_R;
h_A = (float*)malloc(size);
h_B = (float*)malloc(size);
h_R = (float*)malloc(size);
//GPU
float *d_A, *d_B, *d_R;
error = cudaMalloc((void**)&d_A, size);
if (error != cudaSuccess){
printf("Error solicitando memoria en la GPU para d_A\n");
exit(-1);
}
error = cudaMalloc((void**)&d_B, size);
if (error != cudaSuccess){
printf("Error solicitando memoria en la GPU para d_B\n");
exit(-1);
}
error = cudaMalloc((void**)&d_R, size);
if (error != cudaSuccess){
printf("Error solicitando memoria en la GPU para d_R\n");
exit(-1);
}
//Fill Matrix
fill_vector(h_A, n);
fill_vector(h_B, n);
print(h_A, n);
printf("---------------------------------\n");
print(h_B, n);
printf("---------------------------------\n");
//Copy from CPU to GPU
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//Dimension kernel
dim3 dimGrid(ceil(n/10.0), 1, 1);
dim3 dimBlock(10,1,1);
AddVector<<<dimGrid, dimBlock>>>(d_A, d_B, d_R, n);
cudaMemcpy(h_R, d_R, size, cudaMemcpyDeviceToHost);
print(h_R, n);
free(h_A); free(h_B); free(h_R);
cudaFree(d_A); cudaFree(d_B); cudaFree(d_R);
return 0;
} | code for sm_80
Function : _Z9AddVectorPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <cuda.h>
#include <stdio.h>
#include <malloc.h>
__host__
void fill_vector(float *V, int len){
float aux = 5.0;
for (int i = 0; i < len; i++) {
V[i] = ((float)rand() / (float)(RAND_MAX)) * aux ;
}
}
__host__
void print(float *V, int len){
for (int i = 0; i < len; i++) {
printf("%.2f ", V[i]);
}
printf("\n");
}
__global__
void AddVector(float* d_A, float* d_B, float* d_R, int n){
//calculate row index of element
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n) d_R[i] = d_A[i] + d_B[i];
return;
}
int main(){
int n = 100;
float size = n * sizeof(float);
//Manejo de errores en cuda
cudaError_t error = cudaSuccess;
//CPU
float *h_A, *h_B, *h_R;
h_A = (float*)malloc(size);
h_B = (float*)malloc(size);
h_R = (float*)malloc(size);
//GPU
float *d_A, *d_B, *d_R;
error = cudaMalloc((void**)&d_A, size);
if (error != cudaSuccess){
printf("Error solicitando memoria en la GPU para d_A\n");
exit(-1);
}
error = cudaMalloc((void**)&d_B, size);
if (error != cudaSuccess){
printf("Error solicitando memoria en la GPU para d_B\n");
exit(-1);
}
error = cudaMalloc((void**)&d_R, size);
if (error != cudaSuccess){
printf("Error solicitando memoria en la GPU para d_R\n");
exit(-1);
}
//Fill Matrix
fill_vector(h_A, n);
fill_vector(h_B, n);
print(h_A, n);
printf("---------------------------------\n");
print(h_B, n);
printf("---------------------------------\n");
//Copy from CPU to GPU
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//Dimension kernel
dim3 dimGrid(ceil(n/10.0), 1, 1);
dim3 dimBlock(10,1,1);
AddVector<<<dimGrid, dimBlock>>>(d_A, d_B, d_R, n);
cudaMemcpy(h_R, d_R, size, cudaMemcpyDeviceToHost);
print(h_R, n);
free(h_A); free(h_B); free(h_R);
cudaFree(d_A); cudaFree(d_B); cudaFree(d_R);
return 0;
} | .file "tmpxft_000b1bf5_00000000-6_add_vector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11fill_vectorPfi
.type _Z11fill_vectorPfi, @function
_Z11fill_vectorPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11fill_vectorPfi, .-_Z11fill_vectorPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%.2f "
.LC3:
.string "\n"
.text
.globl _Z5printPfi
.type _Z5printPfi, @function
_Z5printPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L12
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC2(%rip), %rbp
.L13:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
.L12:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z5printPfi, .-_Z5printPfi
.globl _Z33__device_stub__Z9AddVectorPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9AddVectorPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9AddVectorPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9AddVectorPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z9AddVectorPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9AddVectorPfS_S_iPfS_S_i
.globl _Z9AddVectorPfS_S_i
.type _Z9AddVectorPfS_S_i, @function
_Z9AddVectorPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9AddVectorPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9AddVectorPfS_S_i, .-_Z9AddVectorPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Error solicitando memoria en la GPU para d_A\n"
.align 8
.LC5:
.string "Error solicitando memoria en la GPU para d_B\n"
.align 8
.LC6:
.string "Error solicitando memoria en la GPU para d_R\n"
.align 8
.LC7:
.string "---------------------------------\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %rbp
movl $400, %edi
call malloc@PLT
movq %rax, %rbx
movl $400, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
leaq 16(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
leaq 24(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
movl $100, %esi
movq %rbp, %rdi
call _Z11fill_vectorPfi
movl $100, %esi
movq %rbx, %rdi
call _Z11fill_vectorPfi
movl $100, %esi
movq %rbp, %rdi
call _Z5printPfi
leaq .LC7(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, %esi
movq %rbx, %rdi
call _Z5printPfi
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $400, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L28:
movl $2, %ecx
movl $400, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $100, %esi
movq %r12, %rdi
call _Z5printPfi
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L32:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L33:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L34:
movl $100, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9AddVectorPfS_S_iPfS_S_i
jmp .L28
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9AddVectorPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9AddVectorPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1084227584
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <cuda.h>
#include <stdio.h>
#include <malloc.h>
__host__
void fill_vector(float *V, int len){
float aux = 5.0;
for (int i = 0; i < len; i++) {
V[i] = ((float)rand() / (float)(RAND_MAX)) * aux ;
}
}
__host__
void print(float *V, int len){
for (int i = 0; i < len; i++) {
printf("%.2f ", V[i]);
}
printf("\n");
}
__global__
void AddVector(float* d_A, float* d_B, float* d_R, int n){
//calculate row index of element
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n) d_R[i] = d_A[i] + d_B[i];
return;
}
int main(){
int n = 100;
float size = n * sizeof(float);
//Manejo de errores en cuda
cudaError_t error = cudaSuccess;
//CPU
float *h_A, *h_B, *h_R;
h_A = (float*)malloc(size);
h_B = (float*)malloc(size);
h_R = (float*)malloc(size);
//GPU
float *d_A, *d_B, *d_R;
error = cudaMalloc((void**)&d_A, size);
if (error != cudaSuccess){
printf("Error solicitando memoria en la GPU para d_A\n");
exit(-1);
}
error = cudaMalloc((void**)&d_B, size);
if (error != cudaSuccess){
printf("Error solicitando memoria en la GPU para d_B\n");
exit(-1);
}
error = cudaMalloc((void**)&d_R, size);
if (error != cudaSuccess){
printf("Error solicitando memoria en la GPU para d_R\n");
exit(-1);
}
//Fill Matrix
fill_vector(h_A, n);
fill_vector(h_B, n);
print(h_A, n);
printf("---------------------------------\n");
print(h_B, n);
printf("---------------------------------\n");
//Copy from CPU to GPU
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//Dimension kernel
dim3 dimGrid(ceil(n/10.0), 1, 1);
dim3 dimBlock(10,1,1);
AddVector<<<dimGrid, dimBlock>>>(d_A, d_B, d_R, n);
cudaMemcpy(h_R, d_R, size, cudaMemcpyDeviceToHost);
print(h_R, n);
free(h_A); free(h_B); free(h_R);
cudaFree(d_A); cudaFree(d_B); cudaFree(d_R);
return 0;
} | #include <stdlib.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <malloc.h>
__host__
void fill_vector(float *V, int len){
float aux = 5.0;
for (int i = 0; i < len; i++) {
V[i] = ((float)rand() / (float)(RAND_MAX)) * aux ;
}
}
__host__
void print(float *V, int len){
for (int i = 0; i < len; i++) {
printf("%.2f ", V[i]);
}
printf("\n");
}
__global__
void AddVector(float* d_A, float* d_B, float* d_R, int n){
//calculate row index of element
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n) d_R[i] = d_A[i] + d_B[i];
return;
}
int main(){
int n = 100;
float size = n * sizeof(float);
//Manejo de errores en cuda
hipError_t error = hipSuccess;
//CPU
float *h_A, *h_B, *h_R;
h_A = (float*)malloc(size);
h_B = (float*)malloc(size);
h_R = (float*)malloc(size);
//GPU
float *d_A, *d_B, *d_R;
error = hipMalloc((void**)&d_A, size);
if (error != hipSuccess){
printf("Error solicitando memoria en la GPU para d_A\n");
exit(-1);
}
error = hipMalloc((void**)&d_B, size);
if (error != hipSuccess){
printf("Error solicitando memoria en la GPU para d_B\n");
exit(-1);
}
error = hipMalloc((void**)&d_R, size);
if (error != hipSuccess){
printf("Error solicitando memoria en la GPU para d_R\n");
exit(-1);
}
//Fill Matrix
fill_vector(h_A, n);
fill_vector(h_B, n);
print(h_A, n);
printf("---------------------------------\n");
print(h_B, n);
printf("---------------------------------\n");
//Copy from CPU to GPU
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
//Dimension kernel
dim3 dimGrid(ceil(n/10.0), 1, 1);
dim3 dimBlock(10,1,1);
AddVector<<<dimGrid, dimBlock>>>(d_A, d_B, d_R, n);
hipMemcpy(h_R, d_R, size, hipMemcpyDeviceToHost);
print(h_R, n);
free(h_A); free(h_B); free(h_R);
hipFree(d_A); hipFree(d_B); hipFree(d_R);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <malloc.h>
__host__
void fill_vector(float *V, int len){
float aux = 5.0;
for (int i = 0; i < len; i++) {
V[i] = ((float)rand() / (float)(RAND_MAX)) * aux ;
}
}
__host__
void print(float *V, int len){
for (int i = 0; i < len; i++) {
printf("%.2f ", V[i]);
}
printf("\n");
}
__global__
void AddVector(float* d_A, float* d_B, float* d_R, int n){
//calculate row index of element
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n) d_R[i] = d_A[i] + d_B[i];
return;
}
int main(){
int n = 100;
float size = n * sizeof(float);
//Manejo de errores en cuda
hipError_t error = hipSuccess;
//CPU
float *h_A, *h_B, *h_R;
h_A = (float*)malloc(size);
h_B = (float*)malloc(size);
h_R = (float*)malloc(size);
//GPU
float *d_A, *d_B, *d_R;
error = hipMalloc((void**)&d_A, size);
if (error != hipSuccess){
printf("Error solicitando memoria en la GPU para d_A\n");
exit(-1);
}
error = hipMalloc((void**)&d_B, size);
if (error != hipSuccess){
printf("Error solicitando memoria en la GPU para d_B\n");
exit(-1);
}
error = hipMalloc((void**)&d_R, size);
if (error != hipSuccess){
printf("Error solicitando memoria en la GPU para d_R\n");
exit(-1);
}
//Fill Matrix
fill_vector(h_A, n);
fill_vector(h_B, n);
print(h_A, n);
printf("---------------------------------\n");
print(h_B, n);
printf("---------------------------------\n");
//Copy from CPU to GPU
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
//Dimension kernel
dim3 dimGrid(ceil(n/10.0), 1, 1);
dim3 dimBlock(10,1,1);
AddVector<<<dimGrid, dimBlock>>>(d_A, d_B, d_R, n);
hipMemcpy(h_R, d_R, size, hipMemcpyDeviceToHost);
print(h_R, n);
free(h_A); free(h_B); free(h_R);
hipFree(d_A); hipFree(d_B); hipFree(d_R);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9AddVectorPfS_S_i
.globl _Z9AddVectorPfS_S_i
.p2align 8
.type _Z9AddVectorPfS_S_i,@function
_Z9AddVectorPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9AddVectorPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9AddVectorPfS_S_i, .Lfunc_end0-_Z9AddVectorPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9AddVectorPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9AddVectorPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <malloc.h>
__host__
void fill_vector(float *V, int len){
float aux = 5.0;
for (int i = 0; i < len; i++) {
V[i] = ((float)rand() / (float)(RAND_MAX)) * aux ;
}
}
__host__
void print(float *V, int len){
for (int i = 0; i < len; i++) {
printf("%.2f ", V[i]);
}
printf("\n");
}
__global__
void AddVector(float* d_A, float* d_B, float* d_R, int n){
//calculate row index of element
int i = threadIdx.x + blockDim.x * blockIdx.x;
if (i < n) d_R[i] = d_A[i] + d_B[i];
return;
}
int main(){
int n = 100;
float size = n * sizeof(float);
//Manejo de errores en cuda
hipError_t error = hipSuccess;
//CPU
float *h_A, *h_B, *h_R;
h_A = (float*)malloc(size);
h_B = (float*)malloc(size);
h_R = (float*)malloc(size);
//GPU
float *d_A, *d_B, *d_R;
error = hipMalloc((void**)&d_A, size);
if (error != hipSuccess){
printf("Error solicitando memoria en la GPU para d_A\n");
exit(-1);
}
error = hipMalloc((void**)&d_B, size);
if (error != hipSuccess){
printf("Error solicitando memoria en la GPU para d_B\n");
exit(-1);
}
error = hipMalloc((void**)&d_R, size);
if (error != hipSuccess){
printf("Error solicitando memoria en la GPU para d_R\n");
exit(-1);
}
//Fill Matrix
fill_vector(h_A, n);
fill_vector(h_B, n);
print(h_A, n);
printf("---------------------------------\n");
print(h_B, n);
printf("---------------------------------\n");
//Copy from CPU to GPU
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
//Dimension kernel
dim3 dimGrid(ceil(n/10.0), 1, 1);
dim3 dimBlock(10,1,1);
AddVector<<<dimGrid, dimBlock>>>(d_A, d_B, d_R, n);
hipMemcpy(h_R, d_R, size, hipMemcpyDeviceToHost);
print(h_R, n);
free(h_A); free(h_B); free(h_R);
hipFree(d_A); hipFree(d_B); hipFree(d_R);
return 0;
} | .text
.file "add_vector.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11fill_vectorPfi
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x40a00000 # float 5
.text
.globl _Z11fill_vectorPfi
.p2align 4, 0x90
.type _Z11fill_vectorPfi,@function
_Z11fill_vectorPfi: # @_Z11fill_vectorPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
mulss .LCPI0_1(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z11fill_vectorPfi, .Lfunc_end0-_Z11fill_vectorPfi
.cfi_endproc
# -- End function
.globl _Z5printPfi # -- Begin function _Z5printPfi
.p2align 4, 0x90
.type _Z5printPfi,@function
_Z5printPfi: # @_Z5printPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z5printPfi, .Lfunc_end1-_Z5printPfi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__AddVectorPfS_S_i # -- Begin function _Z24__device_stub__AddVectorPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__AddVectorPfS_S_i,@function
_Z24__device_stub__AddVectorPfS_S_i: # @_Z24__device_stub__AddVectorPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9AddVectorPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z24__device_stub__AddVectorPfS_S_i, .Lfunc_end2-_Z24__device_stub__AddVectorPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI3_1:
.long 0x40a00000 # float 5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r14
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
testl %eax, %eax
jne .LBB3_1
# %bb.3:
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
testl %eax, %eax
jne .LBB3_4
# %bb.5:
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
testl %eax, %eax
jne .LBB3_19
# %bb.6: # %.lr.ph.i.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $100, %r12
jne .LBB3_7
# %bb.8: # %.lr.ph.i43.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_9: # %.lr.ph.i43
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
mulss .LCPI3_1(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $100, %r12
jne .LBB3_9
# %bb.10: # %.lr.ph.i48.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_11: # %.lr.ph.i48
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $100, %r12
jne .LBB3_11
# %bb.12: # %_Z5printPfi.exit
movl $10, %edi
callq putchar@PLT
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_13: # %.lr.ph.i52
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $100, %r12
jne .LBB3_13
# %bb.14: # %_Z5printPfi.exit57
movl $10, %edi
callq putchar@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movq 24(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_16
# %bb.15:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $100, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9AddVectorPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_16:
movq 8(%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_17: # %.lr.ph.i58
# =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $100, %r12
jne .LBB3_17
# %bb.18: # %_Z5printPfi.exit63
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 192
movl $.Lstr.4, %edi
jmp .LBB3_2
.LBB3_4:
movl $.Lstr.3, %edi
jmp .LBB3_2
.LBB3_19:
movl $.Lstr.2, %edi
.LBB3_2:
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9AddVectorPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f "
.size .L.str, 6
.type _Z9AddVectorPfS_S_i,@object # @_Z9AddVectorPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9AddVectorPfS_S_i
.p2align 3, 0x0
_Z9AddVectorPfS_S_i:
.quad _Z24__device_stub__AddVectorPfS_S_i
.size _Z9AddVectorPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9AddVectorPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "---------------------------------"
.size .Lstr.1, 34
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Error solicitando memoria en la GPU para d_R"
.size .Lstr.2, 45
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Error solicitando memoria en la GPU para d_B"
.size .Lstr.3, 45
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Error solicitando memoria en la GPU para d_A"
.size .Lstr.4, 45
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__AddVectorPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9AddVectorPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9AddVectorPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9AddVectorPfS_S_i
.globl _Z9AddVectorPfS_S_i
.p2align 8
.type _Z9AddVectorPfS_S_i,@function
_Z9AddVectorPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9AddVectorPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9AddVectorPfS_S_i, .Lfunc_end0-_Z9AddVectorPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9AddVectorPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9AddVectorPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b1bf5_00000000-6_add_vector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11fill_vectorPfi
.type _Z11fill_vectorPfi, @function
_Z11fill_vectorPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
mulss .LC1(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11fill_vectorPfi, .-_Z11fill_vectorPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%.2f "
.LC3:
.string "\n"
.text
.globl _Z5printPfi
.type _Z5printPfi, @function
_Z5printPfi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %esi, %esi
jle .L12
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC2(%rip), %rbp
.L13:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
.L12:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z5printPfi, .-_Z5printPfi
.globl _Z33__device_stub__Z9AddVectorPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9AddVectorPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9AddVectorPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9AddVectorPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z9AddVectorPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9AddVectorPfS_S_iPfS_S_i
.globl _Z9AddVectorPfS_S_i
.type _Z9AddVectorPfS_S_i, @function
_Z9AddVectorPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9AddVectorPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9AddVectorPfS_S_i, .-_Z9AddVectorPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Error solicitando memoria en la GPU para d_A\n"
.align 8
.LC5:
.string "Error solicitando memoria en la GPU para d_B\n"
.align 8
.LC6:
.string "Error solicitando memoria en la GPU para d_R\n"
.align 8
.LC7:
.string "---------------------------------\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %rbp
movl $400, %edi
call malloc@PLT
movq %rax, %rbx
movl $400, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
leaq 16(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L32
leaq 24(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L33
movl $100, %esi
movq %rbp, %rdi
call _Z11fill_vectorPfi
movl $100, %esi
movq %rbx, %rdi
call _Z11fill_vectorPfi
movl $100, %esi
movq %rbp, %rdi
call _Z5printPfi
leaq .LC7(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, %esi
movq %rbx, %rdi
call _Z5printPfi
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $400, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 32(%rsp)
movl $1, 36(%rsp)
movl $10, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L28:
movl $2, %ecx
movl $400, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $100, %esi
movq %r12, %rdi
call _Z5printPfi
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L32:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L33:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L34:
movl $100, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9AddVectorPfS_S_iPfS_S_i
jmp .L28
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9AddVectorPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9AddVectorPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC1:
.long 1084227584
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_vector.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11fill_vectorPfi
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI0_1:
.long 0x40a00000 # float 5
.text
.globl _Z11fill_vectorPfi
.p2align 4, 0x90
.type _Z11fill_vectorPfi,@function
_Z11fill_vectorPfi: # @_Z11fill_vectorPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI0_0(%rip), %xmm0
mulss .LCPI0_1(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z11fill_vectorPfi, .Lfunc_end0-_Z11fill_vectorPfi
.cfi_endproc
# -- End function
.globl _Z5printPfi # -- Begin function _Z5printPfi
.p2align 4, 0x90
.type _Z5printPfi,@function
_Z5printPfi: # @_Z5printPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z5printPfi, .Lfunc_end1-_Z5printPfi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__AddVectorPfS_S_i # -- Begin function _Z24__device_stub__AddVectorPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__AddVectorPfS_S_i,@function
_Z24__device_stub__AddVectorPfS_S_i: # @_Z24__device_stub__AddVectorPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9AddVectorPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z24__device_stub__AddVectorPfS_S_i, .Lfunc_end2-_Z24__device_stub__AddVectorPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI3_1:
.long 0x40a00000 # float 5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r14
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
testl %eax, %eax
jne .LBB3_1
# %bb.3:
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
testl %eax, %eax
jne .LBB3_4
# %bb.5:
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
testl %eax, %eax
jne .LBB3_19
# %bb.6: # %.lr.ph.i.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $100, %r12
jne .LBB3_7
# %bb.8: # %.lr.ph.i43.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_9: # %.lr.ph.i43
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
mulss .LCPI3_1(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $100, %r12
jne .LBB3_9
# %bb.10: # %.lr.ph.i48.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_11: # %.lr.ph.i48
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $100, %r12
jne .LBB3_11
# %bb.12: # %_Z5printPfi.exit
movl $10, %edi
callq putchar@PLT
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_13: # %.lr.ph.i52
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $100, %r12
jne .LBB3_13
# %bb.14: # %_Z5printPfi.exit57
movl $10, %edi
callq putchar@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movq 24(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967306, %rdi # imm = 0x10000000A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_16
# %bb.15:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $100, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9AddVectorPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_16:
movq 8(%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_17: # %.lr.ph.i58
# =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $100, %r12
jne .LBB3_17
# %bb.18: # %_Z5printPfi.exit63
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 192
movl $.Lstr.4, %edi
jmp .LBB3_2
.LBB3_4:
movl $.Lstr.3, %edi
jmp .LBB3_2
.LBB3_19:
movl $.Lstr.2, %edi
.LBB3_2:
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9AddVectorPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f "
.size .L.str, 6
.type _Z9AddVectorPfS_S_i,@object # @_Z9AddVectorPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9AddVectorPfS_S_i
.p2align 3, 0x0
_Z9AddVectorPfS_S_i:
.quad _Z24__device_stub__AddVectorPfS_S_i
.size _Z9AddVectorPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9AddVectorPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "---------------------------------"
.size .Lstr.1, 34
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Error solicitando memoria en la GPU para d_R"
.size .Lstr.2, 45
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Error solicitando memoria en la GPU para d_B"
.size .Lstr.3, 45
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Error solicitando memoria en la GPU para d_A"
.size .Lstr.4, 45
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__AddVectorPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9AddVectorPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define SIZ 20
#define num_inp 4
using namespace std;
typedef struct edge {
int first, second;
} edges;
__global__ void grads_w1_kernel(double * grads_W1,double * W1,double reg, int size)
{
int i = blockIdx.x;
int j = threadIdx.x;
grads_W1[i*size + j] += W1[i*size + j] * reg;
} | code for sm_80
Function : _Z15grads_w1_kernelPdS_di
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x178], R3 ; /* 0x00005e0004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*00a0*/ DFMA R6, R2, c[0x0][0x170], R6 ; /* 0x00005c0002067a2b */
/* 0x004e0e0000000006 */
/*00b0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define SIZ 20
#define num_inp 4
using namespace std;
typedef struct edge {
int first, second;
} edges;
__global__ void grads_w1_kernel(double * grads_W1,double * W1,double reg, int size)
{
int i = blockIdx.x;
int j = threadIdx.x;
grads_W1[i*size + j] += W1[i*size + j] * reg;
} | .file "tmpxft_00135141_00000000-6_grads_w1_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15grads_w1_kernelPdS_diPdS_di
.type _Z39__device_stub__Z15grads_w1_kernelPdS_diPdS_di, @function
_Z39__device_stub__Z15grads_w1_kernelPdS_diPdS_di:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15grads_w1_kernelPdS_di(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15grads_w1_kernelPdS_diPdS_di, .-_Z39__device_stub__Z15grads_w1_kernelPdS_diPdS_di
.globl _Z15grads_w1_kernelPdS_di
.type _Z15grads_w1_kernelPdS_di, @function
_Z15grads_w1_kernelPdS_di:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15grads_w1_kernelPdS_diPdS_di
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15grads_w1_kernelPdS_di, .-_Z15grads_w1_kernelPdS_di
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15grads_w1_kernelPdS_di"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15grads_w1_kernelPdS_di(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define SIZ 20
#define num_inp 4
using namespace std;
typedef struct edge {
int first, second;
} edges;
__global__ void grads_w1_kernel(double * grads_W1,double * W1,double reg, int size)
{
int i = blockIdx.x;
int j = threadIdx.x;
grads_W1[i*size + j] += W1[i*size + j] * reg;
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define SIZ 20
#define num_inp 4
using namespace std;
typedef struct edge {
int first, second;
} edges;
__global__ void grads_w1_kernel(double * grads_W1,double * W1,double reg, int size)
{
int i = blockIdx.x;
int j = threadIdx.x;
grads_W1[i*size + j] += W1[i*size + j] * reg;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define SIZ 20
#define num_inp 4
using namespace std;
typedef struct edge {
int first, second;
} edges;
__global__ void grads_w1_kernel(double * grads_W1,double * W1,double reg, int size)
{
int i = blockIdx.x;
int j = threadIdx.x;
grads_W1[i*size + j] += W1[i*size + j] * reg;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15grads_w1_kernelPdS_di
.globl _Z15grads_w1_kernelPdS_di
.p2align 8
.type _Z15grads_w1_kernelPdS_di,@function
_Z15grads_w1_kernelPdS_di:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[2:3], s[0:1], v[4:5]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15grads_w1_kernelPdS_di
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15grads_w1_kernelPdS_di, .Lfunc_end0-_Z15grads_w1_kernelPdS_di
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15grads_w1_kernelPdS_di
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15grads_w1_kernelPdS_di.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define SIZ 20
#define num_inp 4
using namespace std;
typedef struct edge {
int first, second;
} edges;
__global__ void grads_w1_kernel(double * grads_W1,double * W1,double reg, int size)
{
int i = blockIdx.x;
int j = threadIdx.x;
grads_W1[i*size + j] += W1[i*size + j] * reg;
} | .text
.file "grads_w1_kernel.hip"
.globl _Z30__device_stub__grads_w1_kernelPdS_di # -- Begin function _Z30__device_stub__grads_w1_kernelPdS_di
.p2align 4, 0x90
.type _Z30__device_stub__grads_w1_kernelPdS_di,@function
_Z30__device_stub__grads_w1_kernelPdS_di: # @_Z30__device_stub__grads_w1_kernelPdS_di
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15grads_w1_kernelPdS_di, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__grads_w1_kernelPdS_di, .Lfunc_end0-_Z30__device_stub__grads_w1_kernelPdS_di
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15grads_w1_kernelPdS_di, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15grads_w1_kernelPdS_di,@object # @_Z15grads_w1_kernelPdS_di
.section .rodata,"a",@progbits
.globl _Z15grads_w1_kernelPdS_di
.p2align 3, 0x0
_Z15grads_w1_kernelPdS_di:
.quad _Z30__device_stub__grads_w1_kernelPdS_di
.size _Z15grads_w1_kernelPdS_di, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15grads_w1_kernelPdS_di"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__grads_w1_kernelPdS_di
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15grads_w1_kernelPdS_di
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15grads_w1_kernelPdS_di
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x178], R3 ; /* 0x00005e0004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1b00 */
/*00a0*/ DFMA R6, R2, c[0x0][0x170], R6 ; /* 0x00005c0002067a2b */
/* 0x004e0e0000000006 */
/*00b0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15grads_w1_kernelPdS_di
.globl _Z15grads_w1_kernelPdS_di
.p2align 8
.type _Z15grads_w1_kernelPdS_di,@function
_Z15grads_w1_kernelPdS_di:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[2:3], s[0:1], v[4:5]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15grads_w1_kernelPdS_di
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15grads_w1_kernelPdS_di, .Lfunc_end0-_Z15grads_w1_kernelPdS_di
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15grads_w1_kernelPdS_di
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15grads_w1_kernelPdS_di.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00135141_00000000-6_grads_w1_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15grads_w1_kernelPdS_diPdS_di
.type _Z39__device_stub__Z15grads_w1_kernelPdS_diPdS_di, @function
_Z39__device_stub__Z15grads_w1_kernelPdS_diPdS_di:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15grads_w1_kernelPdS_di(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z15grads_w1_kernelPdS_diPdS_di, .-_Z39__device_stub__Z15grads_w1_kernelPdS_diPdS_di
.globl _Z15grads_w1_kernelPdS_di
.type _Z15grads_w1_kernelPdS_di, @function
_Z15grads_w1_kernelPdS_di:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15grads_w1_kernelPdS_diPdS_di
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15grads_w1_kernelPdS_di, .-_Z15grads_w1_kernelPdS_di
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15grads_w1_kernelPdS_di"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15grads_w1_kernelPdS_di(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "grads_w1_kernel.hip"
.globl _Z30__device_stub__grads_w1_kernelPdS_di # -- Begin function _Z30__device_stub__grads_w1_kernelPdS_di
.p2align 4, 0x90
.type _Z30__device_stub__grads_w1_kernelPdS_di,@function
_Z30__device_stub__grads_w1_kernelPdS_di: # @_Z30__device_stub__grads_w1_kernelPdS_di
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15grads_w1_kernelPdS_di, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__grads_w1_kernelPdS_di, .Lfunc_end0-_Z30__device_stub__grads_w1_kernelPdS_di
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15grads_w1_kernelPdS_di, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15grads_w1_kernelPdS_di,@object # @_Z15grads_w1_kernelPdS_di
.section .rodata,"a",@progbits
.globl _Z15grads_w1_kernelPdS_di
.p2align 3, 0x0
_Z15grads_w1_kernelPdS_di:
.quad _Z30__device_stub__grads_w1_kernelPdS_di
.size _Z15grads_w1_kernelPdS_di, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15grads_w1_kernelPdS_di"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__grads_w1_kernelPdS_di
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15grads_w1_kernelPdS_di
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ApplyMat3(float* input, float* output, float* matrix){
int id = threadIdx.x + blockDim.x * blockIdx.x;
//for (int i = 0; i < 148 * 148; ++i){
// if(input[i] > 0.1f) printf("Input above 0, %i", i);
//}
for (int i = 0; i < 146; ++i){
float total = 0.0f;
//if (input[id * 148 + i] > 0.1f) printf("Input above 0, %i", id * 148 + i);
total += input[id * 148 + i] * matrix[0];
total += input[id * 148 + i + 1] * matrix[1];
total += input[id * 148 + i + 2] * matrix[2];
total += input[id * 148 + i + 148 * 1] * matrix[3];
total += input[id * 148 + i + 148 * 1 + 1] * matrix[4];
total += input[id * 148 + i + 148 * 1 + 2] * matrix[5];
total += input[id * 148 + i + 148 * 2] * matrix[6];
total += input[id * 148 + i + 148 * 2 + 1] * matrix[7];
total += input[id * 148 + i + 148 * 2 + 2] * matrix[8];
//if (total < -0.1f || total > 0.1f) printf("Total: %f", total);
total = fmax(0.0f, total);
output[i + id * 146] = total;
}
} | code for sm_80
Function : _Z9ApplyMat3PfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0203 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0070*/ IMAD R6, R0.reuse, 0x92, RZ ; /* 0x0000009200067824 */
/* 0x040fe400078e02ff */
/*0080*/ IMAD R4, R0, 0x94, RZ ; /* 0x0000009400047824 */
/* 0x000fc600078e02ff */
/*0090*/ IADD3 R2, R6, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x000fe40007ffe0ff */
/*00a0*/ IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R6, R6, R3.reuse, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x080fe200078e0203 */
/*00c0*/ IADD3 R12, P0, R4, 0x258, RZ ; /* 0x00000258040c7810 */
/* 0x000fe40007f1e0ff */
/*00d0*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0203 */
/*00f0*/ MOV R9, R7 ; /* 0x0000000700097202 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3.X R15, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff0f7210 */
/* 0x000fe400007fe4ff */
/*0110*/ MOV R0, R2 ; /* 0x0000000200007202 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R7, R3 ; /* 0x0000000300077202 */
/* 0x000fc40000000f00 */
/*0130*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fc80000000f00 */
/*0140*/ MOV R2, R12 ; /* 0x0000000c00027202 */
/* 0x000fe20000000f00 */
/*0150*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea2000c1e1900 */
/*0160*/ MOV R3, R15 ; /* 0x0000000f00037202 */
/* 0x000fc60000000f00 */
/*0170*/ LDG.E R23, [R4.64+0x4] ; /* 0x0000040404177981 */
/* 0x000ee8000c1e1900 */
/*0180*/ LDG.E R21, [R2.64+-0x258] ; /* 0xfffda80402157981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R24, [R2.64+-0x254] ; /* 0xfffdac0402187981 */
/* 0x000ee8000c1e1900 */
/*01a0*/ LDG.E R25, [R4.64+0x8] ; /* 0x0000080404197981 */
/* 0x000f28000c1e1900 */
/*01b0*/ LDG.E R26, [R2.64+-0x250] ; /* 0xfffdb004021a7981 */
/* 0x000f28000c1e1900 */
/*01c0*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R19, [R2.64+-0x8] ; /* 0xfffff80402137981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R17, [R2.64+-0x4] ; /* 0xfffffc0402117981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R13, [R2.64+0x248] ; /* 0x00024804020d7981 */
/* 0x001f68000c1e1900 */
/*0240*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000f68000c1e1900 */
/*0250*/ LDG.E R11, [R2.64+0x24c] ; /* 0x00024c04020b7981 */
/* 0x000f62000c1e1900 */
/*0260*/ FFMA R22, R20, R21, RZ ; /* 0x0000001514167223 */
/* 0x004fc600000000ff */
/*0270*/ LDG.E R20, [R4.64+0x20] ; /* 0x0000200404147981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R21, [R2.64+0x250] ; /* 0x0002500402157981 */
/* 0x000ea2000c1e1900 */
/*0290*/ FFMA R22, R23, R24, R22 ; /* 0x0000001817167223 */
/* 0x008fc80000000016 */
/*02a0*/ FFMA R22, R25, R26, R22 ; /* 0x0000001a19167223 */
/* 0x010fc80000000016 */
/*02b0*/ FFMA R18, R18, R19, R22 ; /* 0x0000001312127223 */
/* 0x020fc80000000016 */
/*02c0*/ FFMA R16, R16, R17, R18 ; /* 0x0000001110107223 */
/* 0x000fc80000000012 */
/*02d0*/ FFMA R14, R14, R15, R16 ; /* 0x0000000f0e0e7223 */
/* 0x000fc80000000010 */
/*02e0*/ FFMA R12, R12, R13, R14 ; /* 0x0000000d0c0c7223 */
/* 0x000fc8000000000e */
/*02f0*/ FFMA R10, R10, R11, R12 ; /* 0x0000000b0a0a7223 */
/* 0x000fe2000000000c */
/*0300*/ MOV R11, R9 ; /* 0x00000009000b7202 */
/* 0x000fc60000000f00 */
/*0310*/ FFMA R10, R20, R21, R10 ; /* 0x00000015140a7223 */
/* 0x004fca000000000a */
/*0320*/ FMNMX R13, RZ, R10, !PT ; /* 0x0000000aff0d7209 */
/* 0x000fe40007800000 */
/*0330*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fca0000000f00 */
/*0340*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0001e8000c101904 */
/*0350*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R21, [R2.64+-0x254] ; /* 0xfffdac0402157981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R23, [R4.64+0x4] ; /* 0x0000040404177981 */
/* 0x000ee8000c1e1900 */
/*0380*/ LDG.E R24, [R2.64+-0x250] ; /* 0xfffdb00402187981 */
/* 0x000ee8000c1e1900 */
/*0390*/ LDG.E R25, [R4.64+0x8] ; /* 0x0000080404197981 */
/* 0x000f28000c1e1900 */
/*03a0*/ LDG.E R26, [R2.64+-0x24c] ; /* 0xfffdb404021a7981 */
/* 0x000f28000c1e1900 */
/*03b0*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f68000c1e1900 */
/*03c0*/ LDG.E R19, [R2.64+-0x4] ; /* 0xfffffc0402137981 */
/* 0x000f68000c1e1900 */
/*03d0*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000f68000c1e1900 */
/*03e0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000f68000c1e1900 */
/*03f0*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000f68000c1e1900 */
/*0410*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000f68000c1e1900 */
/*0420*/ LDG.E R13, [R2.64+0x24c] ; /* 0x00024c04020d7981 */
/* 0x001f68000c1e1900 */
/*0430*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000f68000c1e1900 */
/*0440*/ LDG.E R11, [R2.64+0x250] ; /* 0x00025004020b7981 */
/* 0x000f62000c1e1900 */
/*0450*/ FFMA R22, R20, R21, RZ ; /* 0x0000001514167223 */
/* 0x004fc600000000ff */
/*0460*/ LDG.E R20, [R4.64+0x20] ; /* 0x0000200404147981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R21, [R2.64+0x254] ; /* 0x0002540402157981 */
/* 0x000ea2000c1e1900 */
/*0480*/ FFMA R22, R23, R24, R22 ; /* 0x0000001817167223 */
/* 0x008fc80000000016 */
/*0490*/ FFMA R22, R25, R26, R22 ; /* 0x0000001a19167223 */
/* 0x010fc80000000016 */
/*04a0*/ FFMA R18, R18, R19, R22 ; /* 0x0000001312127223 */
/* 0x020fc80000000016 */
/*04b0*/ FFMA R16, R16, R17, R18 ; /* 0x0000001110107223 */
/* 0x000fe20000000012 */
/*04c0*/ IADD3 R8, R8, 0x2, RZ ; /* 0x0000000208087810 */
/* 0x000fc60007ffe0ff */
/*04d0*/ FFMA R14, R14, R15, R16 ; /* 0x0000000f0e0e7223 */
/* 0x000fe20000000010 */
/*04e0*/ ISETP.NE.AND P0, PT, R8, 0x92, PT ; /* 0x000000920800780c */
/* 0x000fc60003f05270 */
/*04f0*/ FFMA R12, R12, R13, R14 ; /* 0x0000000d0c0c7223 */
/* 0x000fc8000000000e */
/*0500*/ FFMA R10, R10, R11, R12 ; /* 0x0000000b0a0a7223 */
/* 0x000fe2000000000c */
/*0510*/ MOV R11, R7 ; /* 0x00000007000b7202 */
/* 0x000fe40000000f00 */
/*0520*/ IADD3 R6, P2, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007f5e0ff */
/*0530*/ IADD3 R12, P3, R2, 0x8, RZ ; /* 0x00000008020c7810 */
/* 0x000fe40007f7e0ff */
/*0540*/ IADD3.X R9, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff097210 */
/* 0x000fe400017fe4ff */
/*0550*/ IADD3.X R15, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff0f7210 */
/* 0x000fe20001ffe4ff */
/*0560*/ FFMA R10, R20, R21, R10 ; /* 0x00000015140a7223 */
/* 0x004fca000000000a */
/*0570*/ FMNMX R13, RZ, R10, !PT ; /* 0x0000000aff0d7209 */
/* 0x000fe40007800000 */
/*0580*/ MOV R10, R0 ; /* 0x00000000000a7202 */
/* 0x000fe40000000f00 */
/*0590*/ IADD3 R0, P1, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fc60007f3e0ff */
/*05a0*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0001e2000c101904 */
/*05b0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*05c0*/ @P0 BRA 0x140 ; /* 0xfffffb7000000947 */
/* 0x000fea000383ffff */
/*05d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05e0*/ BRA 0x5e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ApplyMat3(float* input, float* output, float* matrix){
int id = threadIdx.x + blockDim.x * blockIdx.x;
//for (int i = 0; i < 148 * 148; ++i){
// if(input[i] > 0.1f) printf("Input above 0, %i", i);
//}
for (int i = 0; i < 146; ++i){
float total = 0.0f;
//if (input[id * 148 + i] > 0.1f) printf("Input above 0, %i", id * 148 + i);
total += input[id * 148 + i] * matrix[0];
total += input[id * 148 + i + 1] * matrix[1];
total += input[id * 148 + i + 2] * matrix[2];
total += input[id * 148 + i + 148 * 1] * matrix[3];
total += input[id * 148 + i + 148 * 1 + 1] * matrix[4];
total += input[id * 148 + i + 148 * 1 + 2] * matrix[5];
total += input[id * 148 + i + 148 * 2] * matrix[6];
total += input[id * 148 + i + 148 * 2 + 1] * matrix[7];
total += input[id * 148 + i + 148 * 2 + 2] * matrix[8];
//if (total < -0.1f || total > 0.1f) printf("Total: %f", total);
total = fmax(0.0f, total);
output[i + id * 146] = total;
}
} | .file "tmpxft_0007bd96_00000000-6_ApplyMat3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9ApplyMat3PfS_S_PfS_S_
.type _Z32__device_stub__Z9ApplyMat3PfS_S_PfS_S_, @function
_Z32__device_stub__Z9ApplyMat3PfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9ApplyMat3PfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z9ApplyMat3PfS_S_PfS_S_, .-_Z32__device_stub__Z9ApplyMat3PfS_S_PfS_S_
.globl _Z9ApplyMat3PfS_S_
.type _Z9ApplyMat3PfS_S_, @function
_Z9ApplyMat3PfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9ApplyMat3PfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9ApplyMat3PfS_S_, .-_Z9ApplyMat3PfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9ApplyMat3PfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9ApplyMat3PfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ApplyMat3(float* input, float* output, float* matrix){
int id = threadIdx.x + blockDim.x * blockIdx.x;
//for (int i = 0; i < 148 * 148; ++i){
// if(input[i] > 0.1f) printf("Input above 0, %i", i);
//}
for (int i = 0; i < 146; ++i){
float total = 0.0f;
//if (input[id * 148 + i] > 0.1f) printf("Input above 0, %i", id * 148 + i);
total += input[id * 148 + i] * matrix[0];
total += input[id * 148 + i + 1] * matrix[1];
total += input[id * 148 + i + 2] * matrix[2];
total += input[id * 148 + i + 148 * 1] * matrix[3];
total += input[id * 148 + i + 148 * 1 + 1] * matrix[4];
total += input[id * 148 + i + 148 * 1 + 2] * matrix[5];
total += input[id * 148 + i + 148 * 2] * matrix[6];
total += input[id * 148 + i + 148 * 2 + 1] * matrix[7];
total += input[id * 148 + i + 148 * 2 + 2] * matrix[8];
//if (total < -0.1f || total > 0.1f) printf("Total: %f", total);
total = fmax(0.0f, total);
output[i + id * 146] = total;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ApplyMat3(float* input, float* output, float* matrix){
int id = threadIdx.x + blockDim.x * blockIdx.x;
//for (int i = 0; i < 148 * 148; ++i){
// if(input[i] > 0.1f) printf("Input above 0, %i", i);
//}
for (int i = 0; i < 146; ++i){
float total = 0.0f;
//if (input[id * 148 + i] > 0.1f) printf("Input above 0, %i", id * 148 + i);
total += input[id * 148 + i] * matrix[0];
total += input[id * 148 + i + 1] * matrix[1];
total += input[id * 148 + i + 2] * matrix[2];
total += input[id * 148 + i + 148 * 1] * matrix[3];
total += input[id * 148 + i + 148 * 1 + 1] * matrix[4];
total += input[id * 148 + i + 148 * 1 + 2] * matrix[5];
total += input[id * 148 + i + 148 * 2] * matrix[6];
total += input[id * 148 + i + 148 * 2 + 1] * matrix[7];
total += input[id * 148 + i + 148 * 2 + 2] * matrix[8];
//if (total < -0.1f || total > 0.1f) printf("Total: %f", total);
total = fmax(0.0f, total);
output[i + id * 146] = total;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ApplyMat3(float* input, float* output, float* matrix){
int id = threadIdx.x + blockDim.x * blockIdx.x;
//for (int i = 0; i < 148 * 148; ++i){
// if(input[i] > 0.1f) printf("Input above 0, %i", i);
//}
for (int i = 0; i < 146; ++i){
float total = 0.0f;
//if (input[id * 148 + i] > 0.1f) printf("Input above 0, %i", id * 148 + i);
total += input[id * 148 + i] * matrix[0];
total += input[id * 148 + i + 1] * matrix[1];
total += input[id * 148 + i + 2] * matrix[2];
total += input[id * 148 + i + 148 * 1] * matrix[3];
total += input[id * 148 + i + 148 * 1 + 1] * matrix[4];
total += input[id * 148 + i + 148 * 1 + 2] * matrix[5];
total += input[id * 148 + i + 148 * 2] * matrix[6];
total += input[id * 148 + i + 148 * 2 + 1] * matrix[7];
total += input[id * 148 + i + 148 * 2 + 2] * matrix[8];
//if (total < -0.1f || total > 0.1f) printf("Total: %f", total);
total = fmax(0.0f, total);
output[i + id * 146] = total;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9ApplyMat3PfS_S_
.globl _Z9ApplyMat3PfS_S_
.p2align 8
.type _Z9ApplyMat3PfS_S_,@function
_Z9ApplyMat3PfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b64 s[2:3], 0
v_mul_lo_u32 v2, v1, 0x94
v_mul_lo_u32 v0, v1, 0x92
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v19, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v20, vcc_lo, s3, v3, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
s_add_u32 s2, s2, 4
global_load_b128 v[5:8], v4, s[0:1]
s_clause 0x1
global_load_b96 v[13:15], v[19:20], off
global_load_b96 v[16:18], v[19:20], off offset:592
global_load_b128 v[9:12], v4, s[0:1] offset:16
global_load_b96 v[19:21], v[19:20], off offset:1184
global_load_b32 v22, v4, s[0:1] offset:32
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x248
s_waitcnt vmcnt(4)
v_fma_f32 v13, v13, v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v13, v14, v6
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_dual_fmac_f32 v13, v15, v7 :: v_dual_add_nc_u32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v16, v8
s_waitcnt vmcnt(2)
v_fmac_f32_e32 v13, v17, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v18, v10
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v13, v19, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v20, v12
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v13, v21, v22
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v1, 0, v13
global_store_b32 v[5:6], v1, off
s_cbranch_scc0 .LBB0_1
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9ApplyMat3PfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9ApplyMat3PfS_S_, .Lfunc_end0-_Z9ApplyMat3PfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9ApplyMat3PfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9ApplyMat3PfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ApplyMat3(float* input, float* output, float* matrix){
int id = threadIdx.x + blockDim.x * blockIdx.x;
//for (int i = 0; i < 148 * 148; ++i){
// if(input[i] > 0.1f) printf("Input above 0, %i", i);
//}
for (int i = 0; i < 146; ++i){
float total = 0.0f;
//if (input[id * 148 + i] > 0.1f) printf("Input above 0, %i", id * 148 + i);
total += input[id * 148 + i] * matrix[0];
total += input[id * 148 + i + 1] * matrix[1];
total += input[id * 148 + i + 2] * matrix[2];
total += input[id * 148 + i + 148 * 1] * matrix[3];
total += input[id * 148 + i + 148 * 1 + 1] * matrix[4];
total += input[id * 148 + i + 148 * 1 + 2] * matrix[5];
total += input[id * 148 + i + 148 * 2] * matrix[6];
total += input[id * 148 + i + 148 * 2 + 1] * matrix[7];
total += input[id * 148 + i + 148 * 2 + 2] * matrix[8];
//if (total < -0.1f || total > 0.1f) printf("Total: %f", total);
total = fmax(0.0f, total);
output[i + id * 146] = total;
}
} | .text
.file "ApplyMat3.hip"
.globl _Z24__device_stub__ApplyMat3PfS_S_ # -- Begin function _Z24__device_stub__ApplyMat3PfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__ApplyMat3PfS_S_,@function
_Z24__device_stub__ApplyMat3PfS_S_: # @_Z24__device_stub__ApplyMat3PfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9ApplyMat3PfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__ApplyMat3PfS_S_, .Lfunc_end0-_Z24__device_stub__ApplyMat3PfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9ApplyMat3PfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9ApplyMat3PfS_S_,@object # @_Z9ApplyMat3PfS_S_
.section .rodata,"a",@progbits
.globl _Z9ApplyMat3PfS_S_
.p2align 3, 0x0
_Z9ApplyMat3PfS_S_:
.quad _Z24__device_stub__ApplyMat3PfS_S_
.size _Z9ApplyMat3PfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9ApplyMat3PfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__ApplyMat3PfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9ApplyMat3PfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9ApplyMat3PfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0203 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0070*/ IMAD R6, R0.reuse, 0x92, RZ ; /* 0x0000009200067824 */
/* 0x040fe400078e02ff */
/*0080*/ IMAD R4, R0, 0x94, RZ ; /* 0x0000009400047824 */
/* 0x000fc600078e02ff */
/*0090*/ IADD3 R2, R6, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x000fe40007ffe0ff */
/*00a0*/ IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R6, R6, R3.reuse, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x080fe200078e0203 */
/*00c0*/ IADD3 R12, P0, R4, 0x258, RZ ; /* 0x00000258040c7810 */
/* 0x000fe40007f1e0ff */
/*00d0*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe200078e0203 */
/*00f0*/ MOV R9, R7 ; /* 0x0000000700097202 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3.X R15, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff0f7210 */
/* 0x000fe400007fe4ff */
/*0110*/ MOV R0, R2 ; /* 0x0000000200007202 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R7, R3 ; /* 0x0000000300077202 */
/* 0x000fc40000000f00 */
/*0130*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fc80000000f00 */
/*0140*/ MOV R2, R12 ; /* 0x0000000c00027202 */
/* 0x000fe20000000f00 */
/*0150*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea2000c1e1900 */
/*0160*/ MOV R3, R15 ; /* 0x0000000f00037202 */
/* 0x000fc60000000f00 */
/*0170*/ LDG.E R23, [R4.64+0x4] ; /* 0x0000040404177981 */
/* 0x000ee8000c1e1900 */
/*0180*/ LDG.E R21, [R2.64+-0x258] ; /* 0xfffda80402157981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R24, [R2.64+-0x254] ; /* 0xfffdac0402187981 */
/* 0x000ee8000c1e1900 */
/*01a0*/ LDG.E R25, [R4.64+0x8] ; /* 0x0000080404197981 */
/* 0x000f28000c1e1900 */
/*01b0*/ LDG.E R26, [R2.64+-0x250] ; /* 0xfffdb004021a7981 */
/* 0x000f28000c1e1900 */
/*01c0*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R19, [R2.64+-0x8] ; /* 0xfffff80402137981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R17, [R2.64+-0x4] ; /* 0xfffffc0402117981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R13, [R2.64+0x248] ; /* 0x00024804020d7981 */
/* 0x001f68000c1e1900 */
/*0240*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000f68000c1e1900 */
/*0250*/ LDG.E R11, [R2.64+0x24c] ; /* 0x00024c04020b7981 */
/* 0x000f62000c1e1900 */
/*0260*/ FFMA R22, R20, R21, RZ ; /* 0x0000001514167223 */
/* 0x004fc600000000ff */
/*0270*/ LDG.E R20, [R4.64+0x20] ; /* 0x0000200404147981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R21, [R2.64+0x250] ; /* 0x0002500402157981 */
/* 0x000ea2000c1e1900 */
/*0290*/ FFMA R22, R23, R24, R22 ; /* 0x0000001817167223 */
/* 0x008fc80000000016 */
/*02a0*/ FFMA R22, R25, R26, R22 ; /* 0x0000001a19167223 */
/* 0x010fc80000000016 */
/*02b0*/ FFMA R18, R18, R19, R22 ; /* 0x0000001312127223 */
/* 0x020fc80000000016 */
/*02c0*/ FFMA R16, R16, R17, R18 ; /* 0x0000001110107223 */
/* 0x000fc80000000012 */
/*02d0*/ FFMA R14, R14, R15, R16 ; /* 0x0000000f0e0e7223 */
/* 0x000fc80000000010 */
/*02e0*/ FFMA R12, R12, R13, R14 ; /* 0x0000000d0c0c7223 */
/* 0x000fc8000000000e */
/*02f0*/ FFMA R10, R10, R11, R12 ; /* 0x0000000b0a0a7223 */
/* 0x000fe2000000000c */
/*0300*/ MOV R11, R9 ; /* 0x00000009000b7202 */
/* 0x000fc60000000f00 */
/*0310*/ FFMA R10, R20, R21, R10 ; /* 0x00000015140a7223 */
/* 0x004fca000000000a */
/*0320*/ FMNMX R13, RZ, R10, !PT ; /* 0x0000000aff0d7209 */
/* 0x000fe40007800000 */
/*0330*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fca0000000f00 */
/*0340*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0001e8000c101904 */
/*0350*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R21, [R2.64+-0x254] ; /* 0xfffdac0402157981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R23, [R4.64+0x4] ; /* 0x0000040404177981 */
/* 0x000ee8000c1e1900 */
/*0380*/ LDG.E R24, [R2.64+-0x250] ; /* 0xfffdb00402187981 */
/* 0x000ee8000c1e1900 */
/*0390*/ LDG.E R25, [R4.64+0x8] ; /* 0x0000080404197981 */
/* 0x000f28000c1e1900 */
/*03a0*/ LDG.E R26, [R2.64+-0x24c] ; /* 0xfffdb404021a7981 */
/* 0x000f28000c1e1900 */
/*03b0*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f68000c1e1900 */
/*03c0*/ LDG.E R19, [R2.64+-0x4] ; /* 0xfffffc0402137981 */
/* 0x000f68000c1e1900 */
/*03d0*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000f68000c1e1900 */
/*03e0*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000f68000c1e1900 */
/*03f0*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000f68000c1e1900 */
/*0410*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000f68000c1e1900 */
/*0420*/ LDG.E R13, [R2.64+0x24c] ; /* 0x00024c04020d7981 */
/* 0x001f68000c1e1900 */
/*0430*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000f68000c1e1900 */
/*0440*/ LDG.E R11, [R2.64+0x250] ; /* 0x00025004020b7981 */
/* 0x000f62000c1e1900 */
/*0450*/ FFMA R22, R20, R21, RZ ; /* 0x0000001514167223 */
/* 0x004fc600000000ff */
/*0460*/ LDG.E R20, [R4.64+0x20] ; /* 0x0000200404147981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R21, [R2.64+0x254] ; /* 0x0002540402157981 */
/* 0x000ea2000c1e1900 */
/*0480*/ FFMA R22, R23, R24, R22 ; /* 0x0000001817167223 */
/* 0x008fc80000000016 */
/*0490*/ FFMA R22, R25, R26, R22 ; /* 0x0000001a19167223 */
/* 0x010fc80000000016 */
/*04a0*/ FFMA R18, R18, R19, R22 ; /* 0x0000001312127223 */
/* 0x020fc80000000016 */
/*04b0*/ FFMA R16, R16, R17, R18 ; /* 0x0000001110107223 */
/* 0x000fe20000000012 */
/*04c0*/ IADD3 R8, R8, 0x2, RZ ; /* 0x0000000208087810 */
/* 0x000fc60007ffe0ff */
/*04d0*/ FFMA R14, R14, R15, R16 ; /* 0x0000000f0e0e7223 */
/* 0x000fe20000000010 */
/*04e0*/ ISETP.NE.AND P0, PT, R8, 0x92, PT ; /* 0x000000920800780c */
/* 0x000fc60003f05270 */
/*04f0*/ FFMA R12, R12, R13, R14 ; /* 0x0000000d0c0c7223 */
/* 0x000fc8000000000e */
/*0500*/ FFMA R10, R10, R11, R12 ; /* 0x0000000b0a0a7223 */
/* 0x000fe2000000000c */
/*0510*/ MOV R11, R7 ; /* 0x00000007000b7202 */
/* 0x000fe40000000f00 */
/*0520*/ IADD3 R6, P2, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007f5e0ff */
/*0530*/ IADD3 R12, P3, R2, 0x8, RZ ; /* 0x00000008020c7810 */
/* 0x000fe40007f7e0ff */
/*0540*/ IADD3.X R9, RZ, R9, RZ, P2, !PT ; /* 0x00000009ff097210 */
/* 0x000fe400017fe4ff */
/*0550*/ IADD3.X R15, RZ, R3, RZ, P3, !PT ; /* 0x00000003ff0f7210 */
/* 0x000fe20001ffe4ff */
/*0560*/ FFMA R10, R20, R21, R10 ; /* 0x00000015140a7223 */
/* 0x004fca000000000a */
/*0570*/ FMNMX R13, RZ, R10, !PT ; /* 0x0000000aff0d7209 */
/* 0x000fe40007800000 */
/*0580*/ MOV R10, R0 ; /* 0x00000000000a7202 */
/* 0x000fe40000000f00 */
/*0590*/ IADD3 R0, P1, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fc60007f3e0ff */
/*05a0*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0001e2000c101904 */
/*05b0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*05c0*/ @P0 BRA 0x140 ; /* 0xfffffb7000000947 */
/* 0x000fea000383ffff */
/*05d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05e0*/ BRA 0x5e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9ApplyMat3PfS_S_
.globl _Z9ApplyMat3PfS_S_
.p2align 8
.type _Z9ApplyMat3PfS_S_,@function
_Z9ApplyMat3PfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b64 s[2:3], 0
v_mul_lo_u32 v2, v1, 0x94
v_mul_lo_u32 v0, v1, 0x92
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v19, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v20, vcc_lo, s3, v3, vcc_lo
v_ashrrev_i32_e32 v1, 31, v0
s_add_u32 s2, s2, 4
global_load_b128 v[5:8], v4, s[0:1]
s_clause 0x1
global_load_b96 v[13:15], v[19:20], off
global_load_b96 v[16:18], v[19:20], off offset:592
global_load_b128 v[9:12], v4, s[0:1] offset:16
global_load_b96 v[19:21], v[19:20], off offset:1184
global_load_b32 v22, v4, s[0:1] offset:32
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x248
s_waitcnt vmcnt(4)
v_fma_f32 v13, v13, v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v13, v14, v6
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_dual_fmac_f32 v13, v15, v7 :: v_dual_add_nc_u32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v16, v8
s_waitcnt vmcnt(2)
v_fmac_f32_e32 v13, v17, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v18, v10
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v13, v19, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v20, v12
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v13, v21, v22
s_delay_alu instid0(VALU_DEP_1)
v_max_f32_e32 v1, 0, v13
global_store_b32 v[5:6], v1, off
s_cbranch_scc0 .LBB0_1
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9ApplyMat3PfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9ApplyMat3PfS_S_, .Lfunc_end0-_Z9ApplyMat3PfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9ApplyMat3PfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9ApplyMat3PfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007bd96_00000000-6_ApplyMat3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9ApplyMat3PfS_S_PfS_S_
.type _Z32__device_stub__Z9ApplyMat3PfS_S_PfS_S_, @function
_Z32__device_stub__Z9ApplyMat3PfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9ApplyMat3PfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z9ApplyMat3PfS_S_PfS_S_, .-_Z32__device_stub__Z9ApplyMat3PfS_S_PfS_S_
.globl _Z9ApplyMat3PfS_S_
.type _Z9ApplyMat3PfS_S_, @function
_Z9ApplyMat3PfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9ApplyMat3PfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9ApplyMat3PfS_S_, .-_Z9ApplyMat3PfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9ApplyMat3PfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9ApplyMat3PfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ApplyMat3.hip"
.globl _Z24__device_stub__ApplyMat3PfS_S_ # -- Begin function _Z24__device_stub__ApplyMat3PfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__ApplyMat3PfS_S_,@function
_Z24__device_stub__ApplyMat3PfS_S_: # @_Z24__device_stub__ApplyMat3PfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9ApplyMat3PfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__ApplyMat3PfS_S_, .Lfunc_end0-_Z24__device_stub__ApplyMat3PfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9ApplyMat3PfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9ApplyMat3PfS_S_,@object # @_Z9ApplyMat3PfS_S_
.section .rodata,"a",@progbits
.globl _Z9ApplyMat3PfS_S_
.p2align 3, 0x0
_Z9ApplyMat3PfS_S_:
.quad _Z24__device_stub__ApplyMat3PfS_S_
.size _Z9ApplyMat3PfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9ApplyMat3PfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__ApplyMat3PfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9ApplyMat3PfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <fstream>
#include <vector>
#include <string>
#include <sstream>
using namespace std;
#define gpuErrchk(ans){gpuAssert((ans), __FILE__, __LINE__);}
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
if(code != cudaSuccess)
{
fprintf(stderr, "GPUassert : %s %s %d\n", cudaGetErrorString(code), file, line);
if(abort) exit(code);
}
}
__global__ void dipoleCorrelation(double *px, double *py, double *pz, double *corr, int N)
{
int tau = threadIdx.x + blockDim.x * blockIdx.x;
double local_corr = 0;
if(tau < N)
{
for(int index = 0; index < N - tau; ++index)
{
local_corr += px[index] * px[index + tau]
+ py[index] * py[index + tau]
+ pz[index] * pz[index + tau];
}
local_corr = local_corr/(N-tau);
corr[tau] = local_corr;
}
__syncthreads();
}
int main()
{
string data, line, word;
int pos(8);
vector< double > dipole_x, dipole_y, dipole_z;
vector< double > t;
const string fileName = "Platinum_nanosphere_run2.stat";
const string fileOut = "CorrfuncCuda.wcorr";
ifstream file;
//open file
file.open(fileName,ios::in);
if(!file)
{
cout<<"Error in opening file"<<endl;
return -1;
}
while(!file.eof())
{
getline(file, line);
int i = 0;
stringstream is(line);
while( is >> word )
{
if (word.compare("#") == 0 || word.compare("##") == 0 ) break;
if(i == 0) t.push_back(stod(word));
if(i == pos)
{
dipole_x.push_back(stod(word));
}
if(i == pos + 1)
{
dipole_y.push_back(stod(word));
}
if(i == pos + 2)
{
dipole_z.push_back(stod(word));
}
i++;
}
}
cout<<"Dipole vector list created"<<endl;
//vector<double> dipole_corr, corr_time;
// calculation of co-orelation function
ofstream outfile;
outfile.open(fileOut);
int N = dipole_x.size();
double *xcomp_dipole = &dipole_x[0]; //convert dipole_x vector to array
double *ycomp_dipole = &dipole_y[0];
double *zcomp_dipole = &dipole_z[0];
double *xcomp_dipole_d, *ycomp_dipole_d, *zcomp_dipole_d;
double *corr_h, *corr_d;
corr_h = (double*)malloc(N*sizeof(double));
double dt = t[1]-t[0];
cout<<"Finding the correlation funciton"<<endl;
gpuErrchk(cudaMalloc((void**)&xcomp_dipole_d, N * sizeof(double)));
gpuErrchk(cudaMalloc((void**)&ycomp_dipole_d, N * sizeof(double)));
gpuErrchk(cudaMalloc((void**)&zcomp_dipole_d, N * sizeof(double)));
gpuErrchk(cudaMalloc((void**)&corr_d, N * sizeof(double)));
/*
for(int index =0; index < N ; ++index)
{
printf("Index: %d Px: %e, Py: %e, Pz: %e\n",index,xcomp_dipole[index],ycomp_dipole[index],zcomp_dipole[index]);
printf("Index: %d Px: %e, Py: %e, Pz: %e\n",index,dipole_x[index],dipole_y[index],dipole_z[index]);
}
*/
gpuErrchk(cudaMemcpy(xcomp_dipole_d, xcomp_dipole, N * sizeof(double), cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(ycomp_dipole_d, ycomp_dipole, N * sizeof(double), cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(zcomp_dipole_d, zcomp_dipole, N * sizeof(double), cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(corr_d, corr_h, N * sizeof(double), cudaMemcpyHostToDevice));
int number_of_blocks;
number_of_blocks = ( N/1024 ) + 1;
dipoleCorrelation<<<number_of_blocks,1024>>> (xcomp_dipole_d, ycomp_dipole_d, zcomp_dipole_d, corr_d, N);
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(corr_h, corr_d, N * sizeof(double), cudaMemcpyDeviceToHost));
outfile<<"## charge velocity autocorrelation function"<<endl;
outfile<<"# time(tau)\t wcorr"<<endl;
for(int count= 0; count < N ; ++count )
{
outfile << t[count] << "\t" << corr_h[count]<<endl;
// cout << t[count] << "\t" << corr_h[count]<<endl;
//dipole_corr.push_back(local_corr/(length - tau));
//corr_time.push_back(tau * dt);
}
outfile.close();
delete [] corr_h;
corr_h = NULL;
gpuErrchk(cudaFree(corr_d));
} | code for sm_80
Function : _Z17dipoleCorrelationPdS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ BSSY B0, 0xaa0 ; /* 0x00000a7000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R7, R2, c[0x0][0x0], R3 ; /* 0x0000000002077a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x180], PT ; /* 0x0000600007007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 BRA 0xa90 ; /* 0x00000a2000000947 */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R6, -R7, c[0x0][0x180], RZ ; /* 0x0000600007067a10 */
/* 0x000fe20007ffe1ff */
/*0080*/ BSSY B1, 0x8e0 ; /* 0x0000085000017945 */
/* 0x000fe20003800000 */
/*0090*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe4000001ff00 */
/*00a0*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f06270 */
/*00b0*/ @!P0 BRA 0x8d0 ; /* 0x0000081000008947 */
/* 0x000fea0003800000 */
/*00c0*/ LOP3.LUT R0, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff007212 */
/* 0x000fe200078e33ff */
/*00d0*/ BSSY B2, 0x710 ; /* 0x0000063000027945 */
/* 0x000fe20003800000 */
/*00e0*/ LOP3.LUT R5, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306057812 */
/* 0x000fe200078ec0ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a10 */
/* 0x000fe20007ffe0ff */
/*0110*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*0120*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0130*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f26070 */
/*0140*/ @!P1 BRA 0x700 ; /* 0x000005b000009947 */
/* 0x000fea0003800000 */
/*0150*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe20000000a00 */
/*0160*/ IMAD.MOV R0, RZ, RZ, -R2 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0a02 */
/*0170*/ UIADD3 UR8, UP0, UR8, 0x10, URZ ; /* 0x0000001008087890 */
/* 0x000fe2000ff1e03f */
/*0180*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*0190*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*01a0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x8 ; /* 0x00000008ff087424 */
/* 0x000fe200078e00ff */
/*01b0*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*01c0*/ IMAD R0, R0, R9, c[0x0][0x180] ; /* 0x0000600000007624 */
/* 0x000fe200078e0209 */
/*01d0*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*01e0*/ IMAD.WIDE R8, R7, R8, c[0x2][0x0] ; /* 0x0080000007087625 */
/* 0x000fe200078e0208 */
/*01f0*/ UIADD3 UR6, UP1, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff3e03f */
/*0200*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*0210*/ UIADD3 UR4, UP0, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000ff1e03f */
/*0220*/ IADD3 R3, -R3, R0, -R5 ; /* 0x0000000003037210 */
/* 0x000fe20007ffe905 */
/*0230*/ UIADD3.X UR7, URZ, UR7, URZ, UP1, !UPT ; /* 0x000000073f077290 */
/* 0x000fe20008ffe43f */
/*0240*/ IADD3 R2, P1, R8.reuse, c[0x0][0x160], RZ ; /* 0x0000580008027a10 */
/* 0x040fe20007f3e0ff */
/*0250*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0260*/ IADD3 R10, P2, R8.reuse, c[0x0][0x168], RZ ; /* 0x00005a00080a7a10 */
/* 0x040fe20007f5e0ff */
/*0270*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0280*/ IADD3 R0, P3, R8, c[0x0][0x170], RZ ; /* 0x00005c0008007a10 */
/* 0x000fe20007f7e0ff */
/*0290*/ IMAD.U32 R12, RZ, RZ, UR8 ; /* 0x00000008ff0c7e24 */
/* 0x000fe2000f8e00ff */
/*02a0*/ IADD3.X R15, R9.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x00005900090f7a10 */
/* 0x040fe20000ffe4ff */
/*02b0*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*02c0*/ IADD3.X R11, R9.reuse, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b00090b7a10 */
/* 0x040fe200017fe4ff */
/*02d0*/ IMAD.U32 R24, RZ, RZ, UR4 ; /* 0x00000004ff187e24 */
/* 0x000fe2000f8e00ff */
/*02e0*/ IADD3.X R23, R9, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0009177a10 */
/* 0x000fe20001ffe4ff */
/*02f0*/ IMAD.U32 R13, RZ, RZ, UR9 ; /* 0x00000009ff0d7e24 */
/* 0x000fc4000f8e00ff */
/*0300*/ IMAD.U32 R9, RZ, RZ, UR7 ; /* 0x00000007ff097e24 */
/* 0x000fe4000f8e00ff */
/*0310*/ IMAD.U32 R25, RZ, RZ, UR5 ; /* 0x00000005ff197e24 */
/* 0x000fe4000f8e00ff */
/*0320*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0330*/ IMAD.MOV.U32 R14, RZ, RZ, R2 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0002 */
/*0340*/ LDG.E.64 R18, [R10.64+-0x10] ; /* 0xfffff0040a127981 */
/* 0x000ea8000c1e1b00 */
/*0350*/ LDG.E.64 R16, [R8.64+-0x10] ; /* 0xfffff00408107981 */
/* 0x000ea8000c1e1b00 */
/*0360*/ LDG.E.64 R28, [R14.64+-0x10] ; /* 0xfffff0040e1c7981 */
/* 0x000ee8000c1e1b00 */
/*0370*/ LDG.E.64 R26, [R12.64+-0x10] ; /* 0xfffff0040c1a7981 */
/* 0x000ee2000c1e1b00 */
/*0380*/ DMUL R16, R18, R16 ; /* 0x0000001012107228 */
/* 0x0040c40000000000 */
/*0390*/ IMAD.MOV.U32 R18, RZ, RZ, R0 ; /* 0x000000ffff127224 */
/* 0x001fe400078e0000 */
/*03a0*/ IMAD.MOV.U32 R19, RZ, RZ, R23 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0017 */
/*03b0*/ LDG.E.64 R22, [R8.64+-0x8] ; /* 0xfffff80408167981 */
/* 0x000ea2000c1e1b00 */
/*03c0*/ DFMA R26, R28, R26, R16 ; /* 0x0000001a1c1a722b */
/* 0x0080640000000010 */
/*03d0*/ IMAD.MOV.U32 R16, RZ, RZ, R24 ; /* 0x000000ffff107224 */
/* 0x001fe200078e0018 */
/*03e0*/ LDG.E.64 R30, [R18.64+-0x10] ; /* 0xfffff004121e7981 */
/* 0x000e62000c1e1b00 */
/*03f0*/ IMAD.MOV.U32 R17, RZ, RZ, R25 ; /* 0x000000ffff117224 */
/* 0x000fc600078e0019 */
/*0400*/ LDG.E.64 R24, [R10.64+-0x8] ; /* 0xfffff8040a187981 */
/* 0x000ea8000c1e1b00 */
/*0410*/ LDG.E.64 R28, [R16.64+-0x10] ; /* 0xfffff004101c7981 */
/* 0x000e64000c1e1b00 */
/*0420*/ DFMA R30, R30, R28, R26 ; /* 0x0000001c1e1e722b */
/* 0x002064000000001a */
/*0430*/ LDG.E.64 R28, [R14.64+-0x8] ; /* 0xfffff8040e1c7981 */
/* 0x001ee8000c1e1b00 */
/*0440*/ LDG.E.64 R26, [R12.64+-0x8] ; /* 0xfffff8040c1a7981 */
/* 0x000ee2000c1e1b00 */
/*0450*/ DMUL R22, R24, R22 ; /* 0x0000001618167228 */
/* 0x0040c60000000000 */
/*0460*/ LDG.E.64 R24, [R16.64+-0x8] ; /* 0xfffff80410187981 */
/* 0x001ea2000c1e1b00 */
/*0470*/ DADD R30, R30, R20 ; /* 0x000000001e1e7229 */
/* 0x0021c60000000014 */
/*0480*/ LDG.E.64 R20, [R18.64+-0x8] ; /* 0xfffff80412147981 */
/* 0x001ea2000c1e1b00 */
/*0490*/ DFMA R22, R28, R26, R22 ; /* 0x0000001a1c16722b */
/* 0x0080860000000016 */
/*04a0*/ LDG.E.64 R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x001ee8000c1e1b00 */
/*04b0*/ LDG.E.64 R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000f22000c1e1b00 */
/*04c0*/ DFMA R20, R20, R24, R22 ; /* 0x000000181414722b */
/* 0x0040460000000016 */
/*04d0*/ LDG.E.64 R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x001ea8000c1e1b00 */
/*04e0*/ LDG.E.64 R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ea2000c1e1b00 */
/*04f0*/ DADD R20, R30, R20 ; /* 0x000000001e147229 */
/* 0x0021c60000000014 */
/*0500*/ LDG.E.64 R30, [R12.64] ; /* 0x000000040c1e7981 */
/* 0x001ee2000c1e1b00 */
/*0510*/ DMUL R22, R24, R22 ; /* 0x0000001618167228 */
/* 0x0040c60000000000 */
/*0520*/ LDG.E.64 R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x001f26000c1e1b00 */
/*0530*/ DFMA R30, R26, R30, R22 ; /* 0x0000001e1a1e722b */
/* 0x0081240000000016 */
/*0540*/ LDG.E.64 R26, [R10.64+0x8] ; /* 0x000008040a1a7981 */
/* 0x001ea8000c1e1b00 */
/*0550*/ LDG.E.64 R22, [R8.64+0x8] ; /* 0x0000080408167981 */
/* 0x000ea2000c1e1b00 */
/*0560*/ DFMA R24, R28, R24, R30 ; /* 0x000000181c18722b */
/* 0x010046000000001e */
/*0570*/ LDG.E.64 R30, [R14.64+0x8] ; /* 0x000008040e1e7981 */
/* 0x0010e8000c1e1b00 */
/*0580*/ LDG.E.64 R28, [R12.64+0x8] ; /* 0x000008040c1c7981 */
/* 0x0008e2000c1e1b00 */
/*0590*/ DADD R20, R20, R24 ; /* 0x0000000014147229 */
/* 0x0023c60000000018 */
/*05a0*/ LDG.E.64 R24, [R16.64+0x8] ; /* 0x0000080410187981 */
/* 0x002f62000c1e1b00 */
/*05b0*/ DMUL R26, R26, R22 ; /* 0x000000161a1a7228 */
/* 0x0042c60000000000 */
/*05c0*/ LDG.E.64 R22, [R18.64+0x8] ; /* 0x0000080412167981 */
/* 0x002f62000c1e1b00 */
/*05d0*/ IADD3 R12, P1, R12, 0x20, RZ ; /* 0x000000200c0c7810 */
/* 0x010fe40007f3e0ff */
/*05e0*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fc60007ffe0ff */
/*05f0*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e060d */
/*0600*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f25270 */
/*0610*/ IADD3 R2, P2, R14, 0x20, RZ ; /* 0x000000200e027810 */
/* 0x000fe40007f5e0ff */
/*0620*/ IADD3 R10, P3, R10, 0x20, RZ ; /* 0x000000200a0a7810 */
/* 0x000fe40007f7e0ff */
/*0630*/ IADD3 R0, P5, R18, 0x20, RZ ; /* 0x0000002012007810 */
/* 0x000fe20007fbe0ff */
/*0640*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x001fe200010e060f */
/*0650*/ IADD3 R8, P2, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x000fe20007f5e0ff */
/*0660*/ IMAD.X R11, RZ, RZ, R11, P3 ; /* 0x000000ffff0b7224 */
/* 0x000fe200018e060b */
/*0670*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0680*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*0690*/ DFMA R26, R30, R28, R26 ; /* 0x0000001c1e1a722b */
/* 0x008f4c000000001a */
/*06a0*/ DFMA R22, R22, R24, R26 ; /* 0x000000181616722b */
/* 0x020064000000001a */
/*06b0*/ IADD3 R24, P4, R16, 0x20, RZ ; /* 0x0000002010187810 */
/* 0x001fc80007f9e0ff */
/*06c0*/ DADD R20, R20, R22 ; /* 0x0000000014147229 */
/* 0x0020620000000016 */
/*06d0*/ IMAD.X R25, RZ, RZ, R17, P4 ; /* 0x000000ffff197224 */
/* 0x000fe400020e0611 */
/*06e0*/ IMAD.X R23, RZ, RZ, R19, P5 ; /* 0x000000ffff177224 */
/* 0x001fe200028e0613 */
/*06f0*/ @P1 BRA 0x320 ; /* 0xfffffc2000001947 */
/* 0x002fea000383ffff */
/*0700*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0710*/ @!P0 BRA 0x8d0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0720*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fc800078e00ff */
/*0730*/ IMAD.WIDE R14, R4, R9, c[0x0][0x170] ; /* 0x00005c00040e7625 */
/* 0x000fc800078e0209 */
/*0740*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0209 */
/*0750*/ IMAD.WIDE R8, R4, R9, c[0x0][0x160] ; /* 0x0000580004087625 */
/* 0x000fc800078e0209 */
/*0760*/ IMAD.WIDE R12, R7.reuse, 0x8, R2 ; /* 0x00000008070c7825 */
/* 0x040fe200078e0202 */
/*0770*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0780*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x0010a2000c1e1b00 */
/*0790*/ IMAD.WIDE R24, R7, 0x8, R8 ; /* 0x0000000807187825 */
/* 0x000fc600078e0208 */
/*07a0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*07b0*/ IMAD.WIDE R18, R7, 0x8, R14 ; /* 0x0000000807127825 */
/* 0x000fc600078e020e */
/*07c0*/ LDG.E.64 R16, [R8.64] ; /* 0x0000000408107981 */
/* 0x0022e8000c1e1b00 */
/*07d0*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ee8000c1e1b00 */
/*07e0*/ LDG.E.64 R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000968000c1e1b00 */
/*07f0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1b00 */
/*0800*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0810*/ IADD3 R2, P2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x001fe40007f5e0ff */
/*0820*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0830*/ IADD3 R14, P1, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x010fe20007f3e0ff */
/*0840*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0850*/ IADD3 R8, P3, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x002fc60007f7e0ff */
/*0860*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe400008e060f */
/*0870*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe200018e0609 */
/*0880*/ DMUL R10, R12, R10 ; /* 0x0000000a0c0a7228 */
/* 0x004ecc0000000000 */
/*0890*/ DFMA R10, R24, R16, R10 ; /* 0x00000010180a722b */
/* 0x008f4c000000000a */
/*08a0*/ DFMA R10, R18, R22, R10 ; /* 0x00000016120a722b */
/* 0x020e0c000000000a */
/*08b0*/ DADD R20, R10, R20 ; /* 0x000000000a147229 */
/* 0x0010620000000014 */
/*08c0*/ @P0 BRA 0x760 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*08d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08e0*/ I2F.F64 R8, R6 ; /* 0x0000000600087312 */
/* 0x000ea20000201c00 */
/*08f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0900*/ FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; /* 0x036000001500780b */
/* 0x002fe20003f2e200 */
/*0910*/ BSSY B1, 0xa50 ; /* 0x0000013000017945 */
/* 0x000fea0003800000 */
/*0920*/ MUFU.RCP64H R3, R9 ; /* 0x0000000900037308 */
/* 0x004e640000001800 */
/*0930*/ DFMA R4, -R8, R2, 1 ; /* 0x3ff000000804742b */
/* 0x002e4c0000000102 */
/*0940*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x002e4c0000000004 */
/*0950*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x002e4c0000000002 */
/*0960*/ DFMA R2, -R8, R4, 1 ; /* 0x3ff000000802742b */
/* 0x002e4c0000000104 */
/*0970*/ DFMA R2, R4, R2, R4 ; /* 0x000000020402722b */
/* 0x002e4c0000000004 */
/*0980*/ DMUL R4, R2, R20 ; /* 0x0000001402047228 */
/* 0x002e4c0000000000 */
/*0990*/ DFMA R10, -R8, R4, R20 ; /* 0x00000004080a722b */
/* 0x003e0c0000000114 */
/*09a0*/ DFMA R2, R2, R10, R4 ; /* 0x0000000a0202722b */
/* 0x001e140000000004 */
/*09b0*/ FFMA R0, RZ, R9, R3 ; /* 0x00000009ff007223 */
/* 0x001fca0000000003 */
/*09c0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*09d0*/ @P0 BRA P1, 0xa40 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*09e0*/ IMAD.MOV.U32 R2, RZ, RZ, R20 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0014 */
/*09f0*/ MOV R0, 0xa20 ; /* 0x00000a2000007802 */
/* 0x000fe20000000f00 */
/*0a00*/ IMAD.MOV.U32 R3, RZ, RZ, R21 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0015 */
/*0a10*/ CALL.REL.NOINC 0xac0 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0a20*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000c */
/*0a30*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0a40*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a50*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fe200078e00ff */
/*0a60*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0a70*/ IMAD.WIDE R4, R7, R4, c[0x0][0x178] ; /* 0x00005e0007047625 */
/* 0x000fca00078e0204 */
/*0a80*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x0005e4000c101b04 */
/*0a90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0aa0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ab0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ac0*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0ad0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0c7424 */
/* 0x000fe200078e00ff */
/*0ae0*/ LOP3.LUT R4, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09047812 */
/* 0x000fe200078ec0ff */
/*0af0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0b00*/ FSETP.GEU.AND P2, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f4e200 */
/*0b10*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*0b20*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0b30*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0b40*/ LOP3.LUT R6, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003067812 */
/* 0x000fe200078ec0ff */
/*0b50*/ BSSY B2, 0x1060 ; /* 0x0000050000027945 */
/* 0x000fe20003800000 */
/*0b60*/ LOP3.LUT R13, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090d7812 */
/* 0x000fc600078ec0ff */
/*0b70*/ @!P0 DMUL R4, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008048828 */
/* 0x000e220000000000 */
/*0b80*/ ISETP.GE.U32.AND P1, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fc60003f26070 */
/*0b90*/ @!P2 LOP3.LUT R11, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090ba812 */
/* 0x000fe200078ec0ff */
/*0ba0*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12a224 */
/* 0x000fe200078e00ff */
/*0bb0*/ MUFU.RCP64H R15, R5 ; /* 0x00000005000f7308 */
/* 0x001e240000001800 */
/*0bc0*/ @!P2 ISETP.GE.U32.AND P3, PT, R6, R11, PT ; /* 0x0000000b0600a20c */
/* 0x000fe40003f66070 */
/*0bd0*/ SEL R11, R12.reuse, 0x63400000, !P1 ; /* 0x634000000c0b7807 */
/* 0x040fe40004800000 */
/*0be0*/ @!P2 SEL R19, R12, 0x63400000, !P3 ; /* 0x634000000c13a807 */
/* 0x000fe40005800000 */
/*0bf0*/ LOP3.LUT R11, R11, 0x800fffff, R3, 0xf8, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fc400078ef803 */
/*0c00*/ @!P2 LOP3.LUT R19, R19, 0x80000000, R3, 0xf8, !PT ; /* 0x800000001313a812 */
/* 0x000fc800078ef803 */
/*0c10*/ @!P2 LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001313a812 */
/* 0x000fe200078efcff */
/*0c20*/ DFMA R16, R14, -R4, 1 ; /* 0x3ff000000e10742b */
/* 0x001e0a0000000804 */
/*0c30*/ @!P2 DFMA R10, R10, 2, -R18 ; /* 0x400000000a0aa82b */
/* 0x000fc80000000812 */
/*0c40*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0c50*/ DFMA R14, R14, R16, R14 ; /* 0x000000100e0e722b */
/* 0x001064000000000e */
/*0c60*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x001fe200078e0006 */
/*0c70*/ @!P2 LOP3.LUT R16, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b10a812 */
/* 0x000fe200078ec0ff */
/*0c80*/ IMAD.MOV.U32 R17, RZ, RZ, R13 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000d */
/*0c90*/ @!P0 LOP3.LUT R17, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005118812 */
/* 0x000fe200078ec0ff */
/*0ca0*/ DFMA R18, R14.reuse, -R4, 1 ; /* 0x3ff000000e12742b */
/* 0x042e220000000804 */
/*0cb0*/ IADD3 R13, R16, -0x1, RZ ; /* 0xffffffff100d7810 */
/* 0x000fe40007ffe0ff */
/*0cc0*/ IADD3 R22, R17, -0x1, RZ ; /* 0xffffffff11167810 */
/* 0x000fe40007ffe0ff */
/*0cd0*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fe20003f04070 */
/*0ce0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e06000000000e */
/*0cf0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fc60000704470 */
/*0d00*/ DMUL R18, R14, R10 ; /* 0x0000000a0e127228 */
/* 0x001e0c0000000000 */
/*0d10*/ DFMA R20, R18, -R4, R10 ; /* 0x800000041214722b */
/* 0x001e0c000000000a */
/*0d20*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*0d30*/ @P0 BRA 0xf00 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0d40*/ LOP3.LUT R3, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009037812 */
/* 0x000fc800078ec0ff */
/*0d50*/ ISETP.GE.U32.AND P0, PT, R6.reuse, R3, PT ; /* 0x000000030600720c */
/* 0x040fe20003f06070 */
/*0d60*/ IMAD.IADD R2, R6, 0x1, -R3 ; /* 0x0000000106027824 */
/* 0x000fc600078e0a03 */
/*0d70*/ SEL R3, R12, 0x63400000, !P0 ; /* 0x634000000c037807 */
/* 0x000fe40004000000 */
/*0d80*/ IMNMX R2, R2, -0x46a00000, !PT ; /* 0xb960000002027817 */
/* 0x000fc80007800200 */
/*0d90*/ IMNMX R2, R2, 0x46a00000, PT ; /* 0x46a0000002027817 */
/* 0x000fca0003800200 */
/*0da0*/ IMAD.IADD R6, R2, 0x1, -R3 ; /* 0x0000000102067824 */
/* 0x000fe400078e0a03 */
/*0db0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0dc0*/ IADD3 R3, R6, 0x7fe00000, RZ ; /* 0x7fe0000006037810 */
/* 0x000fcc0007ffe0ff */
/*0dd0*/ DMUL R12, R14, R2 ; /* 0x000000020e0c7228 */
/* 0x002e540000000000 */
/*0de0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*0df0*/ @P0 BRA 0x1050 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0e00*/ DFMA R4, R14, -R4, R10 ; /* 0x800000040e04722b */
/* 0x000e62000000000a */
/*0e10*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fd200078e00ff */
/*0e20*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x042fe40003f0d000 */
/*0e30*/ LOP3.LUT R9, R5, 0x80000000, R9, 0x48, !PT ; /* 0x8000000005097812 */
/* 0x000fc800078e4809 */
/*0e40*/ LOP3.LUT R3, R9, R3, RZ, 0xfc, !PT ; /* 0x0000000309037212 */
/* 0x000fce00078efcff */
/*0e50*/ @!P0 BRA 0x1050 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0e60*/ IMAD.MOV R5, RZ, RZ, -R6 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a06 */
/*0e70*/ DMUL.RP R2, R14, R2 ; /* 0x000000020e027228 */
/* 0x000e620000008000 */
/*0e80*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0e90*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e86000000000e */
/*0ea0*/ LOP3.LUT R9, R3, R9, RZ, 0x3c, !PT ; /* 0x0000000903097212 */
/* 0x002fc600078e3cff */
/*0eb0*/ IADD3 R4, -R6, -0x43300000, RZ ; /* 0xbcd0000006047810 */
/* 0x004fc80007ffe1ff */
/*0ec0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0ed0*/ FSEL R12, R2, R12, !P0 ; /* 0x0000000c020c7208 */
/* 0x000fe40004000000 */
/*0ee0*/ FSEL R13, R9, R13, !P0 ; /* 0x0000000d090d7208 */
/* 0x000fe20004000000 */
/*0ef0*/ BRA 0x1050 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0f00*/ DSETP.NAN.AND P0, PT, R2, R2, PT ; /* 0x000000020200722a */
/* 0x000e9c0003f08000 */
/*0f10*/ @P0 BRA 0x1030 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0f20*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f08000 */
/*0f30*/ @P0 BRA 0x1000 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0f40*/ ISETP.NE.AND P0, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fe20003f05270 */
/*0f50*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0f60*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0f70*/ @!P0 BRA 0x1050 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0f80*/ ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; /* 0x7ff000001000780c */
/* 0x000fe40003f05270 */
/*0f90*/ LOP3.LUT R13, R3, 0x80000000, R9, 0x48, !PT ; /* 0x80000000030d7812 */
/* 0x000fe400078e4809 */
/*0fa0*/ ISETP.EQ.OR P0, PT, R17, RZ, !P0 ; /* 0x000000ff1100720c */
/* 0x000fda0004702670 */
/*0fb0*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0fc0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0fd0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0fe0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*0ff0*/ BRA 0x1050 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1000*/ LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090d7812 */
/* 0x000fe200078efcff */
/*1010*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*1020*/ BRA 0x1050 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*1030*/ LOP3.LUT R13, R3, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000030d7812 */
/* 0x000fe200078efcff */
/*1040*/ IMAD.MOV.U32 R12, RZ, RZ, R2 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0002 */
/*1050*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1060*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*1070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*1080*/ RET.REL.NODEC R2 0x0 ; /* 0xffffef7002007950 */
/* 0x000fea0003c3ffff */
/*1090*/ BRA 0x1090; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <fstream>
#include <vector>
#include <string>
#include <sstream>
using namespace std;
#define gpuErrchk(ans){gpuAssert((ans), __FILE__, __LINE__);}
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
if(code != cudaSuccess)
{
fprintf(stderr, "GPUassert : %s %s %d\n", cudaGetErrorString(code), file, line);
if(abort) exit(code);
}
}
__global__ void dipoleCorrelation(double *px, double *py, double *pz, double *corr, int N)
{
int tau = threadIdx.x + blockDim.x * blockIdx.x;
double local_corr = 0;
if(tau < N)
{
for(int index = 0; index < N - tau; ++index)
{
local_corr += px[index] * px[index + tau]
+ py[index] * py[index + tau]
+ pz[index] * pz[index + tau];
}
local_corr = local_corr/(N-tau);
corr[tau] = local_corr;
}
__syncthreads();
}
int main()
{
string data, line, word;
int pos(8);
vector< double > dipole_x, dipole_y, dipole_z;
vector< double > t;
const string fileName = "Platinum_nanosphere_run2.stat";
const string fileOut = "CorrfuncCuda.wcorr";
ifstream file;
//open file
file.open(fileName,ios::in);
if(!file)
{
cout<<"Error in opening file"<<endl;
return -1;
}
while(!file.eof())
{
getline(file, line);
int i = 0;
stringstream is(line);
while( is >> word )
{
if (word.compare("#") == 0 || word.compare("##") == 0 ) break;
if(i == 0) t.push_back(stod(word));
if(i == pos)
{
dipole_x.push_back(stod(word));
}
if(i == pos + 1)
{
dipole_y.push_back(stod(word));
}
if(i == pos + 2)
{
dipole_z.push_back(stod(word));
}
i++;
}
}
cout<<"Dipole vector list created"<<endl;
//vector<double> dipole_corr, corr_time;
// calculation of co-orelation function
ofstream outfile;
outfile.open(fileOut);
int N = dipole_x.size();
double *xcomp_dipole = &dipole_x[0]; //convert dipole_x vector to array
double *ycomp_dipole = &dipole_y[0];
double *zcomp_dipole = &dipole_z[0];
double *xcomp_dipole_d, *ycomp_dipole_d, *zcomp_dipole_d;
double *corr_h, *corr_d;
corr_h = (double*)malloc(N*sizeof(double));
double dt = t[1]-t[0];
cout<<"Finding the correlation funciton"<<endl;
gpuErrchk(cudaMalloc((void**)&xcomp_dipole_d, N * sizeof(double)));
gpuErrchk(cudaMalloc((void**)&ycomp_dipole_d, N * sizeof(double)));
gpuErrchk(cudaMalloc((void**)&zcomp_dipole_d, N * sizeof(double)));
gpuErrchk(cudaMalloc((void**)&corr_d, N * sizeof(double)));
/*
for(int index =0; index < N ; ++index)
{
printf("Index: %d Px: %e, Py: %e, Pz: %e\n",index,xcomp_dipole[index],ycomp_dipole[index],zcomp_dipole[index]);
printf("Index: %d Px: %e, Py: %e, Pz: %e\n",index,dipole_x[index],dipole_y[index],dipole_z[index]);
}
*/
gpuErrchk(cudaMemcpy(xcomp_dipole_d, xcomp_dipole, N * sizeof(double), cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(ycomp_dipole_d, ycomp_dipole, N * sizeof(double), cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(zcomp_dipole_d, zcomp_dipole, N * sizeof(double), cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(corr_d, corr_h, N * sizeof(double), cudaMemcpyHostToDevice));
int number_of_blocks;
number_of_blocks = ( N/1024 ) + 1;
dipoleCorrelation<<<number_of_blocks,1024>>> (xcomp_dipole_d, ycomp_dipole_d, zcomp_dipole_d, corr_d, N);
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(corr_h, corr_d, N * sizeof(double), cudaMemcpyDeviceToHost));
outfile<<"## charge velocity autocorrelation function"<<endl;
outfile<<"# time(tau)\t wcorr"<<endl;
for(int count= 0; count < N ; ++count )
{
outfile << t[count] << "\t" << corr_h[count]<<endl;
// cout << t[count] << "\t" << corr_h[count]<<endl;
//dipole_corr.push_back(local_corr/(length - tau));
//corr_time.push_back(tau * dt);
}
outfile.close();
delete [] corr_h;
corr_h = NULL;
gpuErrchk(cudaFree(corr_d));
} | .file "tmpxft_00196827_00000000-6_stat2dipole.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4235:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4235:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert : %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB4220:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE4220:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z44__device_stub__Z17dipoleCorrelationPdS_S_S_iPdS_S_S_i
.type _Z44__device_stub__Z17dipoleCorrelationPdS_S_S_iPdS_S_S_i, @function
_Z44__device_stub__Z17dipoleCorrelationPdS_S_S_iPdS_S_S_i:
.LFB4257:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17dipoleCorrelationPdS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4257:
.size _Z44__device_stub__Z17dipoleCorrelationPdS_S_S_iPdS_S_S_i, .-_Z44__device_stub__Z17dipoleCorrelationPdS_S_S_iPdS_S_S_i
.globl _Z17dipoleCorrelationPdS_S_S_i
.type _Z17dipoleCorrelationPdS_S_S_i, @function
_Z17dipoleCorrelationPdS_S_S_i:
.LFB4258:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z17dipoleCorrelationPdS_S_S_iPdS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4258:
.size _Z17dipoleCorrelationPdS_S_S_i, .-_Z17dipoleCorrelationPdS_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z17dipoleCorrelationPdS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4260:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z17dipoleCorrelationPdS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4260:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.weak _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.type _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function
_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_:
.LFB4388:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4388
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %rbp
movq %rcx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r13d
movl $0, (%rax)
movq %rsp, %rsi
movq %rbp, %rdi
.LEHB0:
call *%r15
movq (%rsp), %rax
cmpq %rbp, %rax
je .L34
cmpl $34, (%rbx)
je .L35
testq %r12, %r12
je .L26
subq %rbp, %rax
movq %rax, (%r12)
.L26:
cmpl $0, (%rbx)
jne .L21
movl %r13d, (%rbx)
.L21:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L37
movq %r14, %rdi
call _ZSt24__throw_invalid_argumentPKc@PLT
.L32:
endbr64
movq %rax, %rdi
cmpl $0, (%rbx)
jne .L29
movl %r13d, (%rbx)
.L29:
movq 8(%rsp), %rax
subq %fs:40, %rax
je .L30
call __stack_chk_fail@PLT
.L37:
call __stack_chk_fail@PLT
.L35:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L38
movq %r14, %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE0:
.L38:
call __stack_chk_fail@PLT
.L30:
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4388:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.LLSDA4388:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4388-.LLSDACSB4388
.LLSDACSB4388:
.uleb128 .LEHB0-.LFB4388
.uleb128 .LEHE0-.LEHB0
.uleb128 .L32-.LFB4388
.uleb128 0
.uleb128 .LEHB1-.LFB4388
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE4388:
.section .text._ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.size _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.section .text._ZNSt6vectorIdSaIdEED2Ev,"axG",@progbits,_ZNSt6vectorIdSaIdEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEED2Ev
.type _ZNSt6vectorIdSaIdEED2Ev, @function
_ZNSt6vectorIdSaIdEED2Ev:
.LFB4589:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L42
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L42:
ret
.cfi_endproc
.LFE4589:
.size _ZNSt6vectorIdSaIdEED2Ev, .-_ZNSt6vectorIdSaIdEED2Ev
.weak _ZNSt6vectorIdSaIdEED1Ev
.set _ZNSt6vectorIdSaIdEED1Ev,_ZNSt6vectorIdSaIdEED2Ev
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag:
.LFB4712:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
subq %rsi, %rdx
movq %rdx, %rbp
movq %rdx, (%rsp)
cmpq $15, %rdx
ja .L52
movq (%rdi), %rdi
cmpq $1, %rdx
jne .L48
movzbl (%rsi), %eax
movb %al, (%rdi)
.L49:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movq %rsp, %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L47:
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L49
.L48:
testq %rdx, %rdx
je .L49
jmp .L47
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4712:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.section .rodata._ZNSt6vectorIdSaIdEE17_M_realloc_insertIJdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC2:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIdSaIdEE17_M_realloc_insertIJdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIdSaIdEE17_M_realloc_insertIJdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEE17_M_realloc_insertIJdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_
.type _ZNSt6vectorIdSaIdEE17_M_realloc_insertIJdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_, @function
_ZNSt6vectorIdSaIdEE17_M_realloc_insertIJdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_:
.LFB4941:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L71
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L57
movabsq $1152921504606846975, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L58
jmp .L65
.L71:
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L72:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L60
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L64
.L57:
movq (%rsp), %r15
subq %r13, %r15
movabsq $1152921504606846975, %r14
.L65:
leaq 0(,%r14,8), %rdi
call _Znwm@PLT
movq %rax, %r12
.L58:
movq 8(%rsp), %rax
movsd (%rax), %xmm0
movsd %xmm0, (%r12,%r15)
testq %r15, %r15
jg .L72
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L62
.L60:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L62:
addq %rbp, %r15
testq %r13, %r13
je .L63
movq 16(%rbx), %rsi
subq %r13, %rsi
.L64:
movq %r13, %rdi
call _ZdlPvm@PLT
.L63:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,8), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4941:
.size _ZNSt6vectorIdSaIdEE17_M_realloc_insertIJdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_, .-_ZNSt6vectorIdSaIdEE17_M_realloc_insertIJdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_
.section .text._ZNSt6vectorIdSaIdEE12emplace_backIJdEEERdDpOT_,"axG",@progbits,_ZNSt6vectorIdSaIdEE12emplace_backIJdEEERdDpOT_,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEE12emplace_backIJdEEERdDpOT_
.type _ZNSt6vectorIdSaIdEE12emplace_backIJdEEERdDpOT_, @function
_ZNSt6vectorIdSaIdEE12emplace_backIJdEEERdDpOT_:
.LFB4829:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rax
cmpq 16(%rdi), %rax
je .L74
movsd (%rsi), %xmm0
movsd %xmm0, (%rax)
addq $8, 8(%rdi)
.L75:
movq 8(%rbx), %rax
subq $8, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L74:
.cfi_restore_state
movq %rsi, %rdx
movq %rax, %rsi
call _ZNSt6vectorIdSaIdEE17_M_realloc_insertIJdEEEvN9__gnu_cxx17__normal_iteratorIPdS1_EEDpOT_
jmp .L75
.cfi_endproc
.LFE4829:
.size _ZNSt6vectorIdSaIdEE12emplace_backIJdEEERdDpOT_, .-_ZNSt6vectorIdSaIdEE12emplace_backIJdEEERdDpOT_
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Platinum_nanosphere_run2.stat"
.LC4:
.string "CorrfuncCuda.wcorr"
.LC5:
.string "Error in opening file"
.section .rodata.str1.8
.align 8
.LC6:
.string "basic_string: construction from null is not valid"
.section .rodata.str1.1
.LC7:
.string "##"
.LC8:
.string "stod"
.LC9:
.string "Dipole vector list created"
.section .rodata.str1.8
.align 8
.LC10:
.string "Finding the correlation funciton"
.align 8
.LC11:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Hemanta-Bhattarai/Self_Learning/master/CUDA/correlation_function/stat2dipole.cu"
.align 8
.LC12:
.string "## charge velocity autocorrelation function"
.section .rodata.str1.1
.LC13:
.string "# time(tau)\t wcorr"
.LC14:
.string "\t"
.text
.globl main
.type main, @function
main:
.LFB4221:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4221
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1416, %rsp
.cfi_def_cfa_offset 1472
movq %fs:40, %rax
movq %rax, 1400(%rsp)
xorl %eax, %eax
leaq 224(%rsp), %rax
movq %rax, 208(%rsp)
movq $0, 216(%rsp)
movb $0, 224(%rsp)
leaq 256(%rsp), %rax
movq %rax, 240(%rsp)
movq $0, 248(%rsp)
movb $0, 256(%rsp)
leaq 288(%rsp), %rax
movq %rax, 272(%rsp)
movq $0, 280(%rsp)
movb $0, 288(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movq $0, 112(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movq $0, 144(%rsp)
movq $0, 152(%rsp)
movq $0, 160(%rsp)
movq $0, 176(%rsp)
movq $0, 184(%rsp)
movq $0, 192(%rsp)
leaq 304(%rsp), %rdi
leaq 320(%rsp), %rax
movq %rax, 304(%rsp)
leaq 29+.LC3(%rip), %rdx
leaq -29(%rdx), %rsi
.LEHB2:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE2:
leaq 336(%rsp), %rdi
leaq 352(%rsp), %rax
movq %rax, 336(%rsp)
leaq 18+.LC4(%rip), %rdx
leaq -18(%rdx), %rsi
.LEHB3:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
.LEHE3:
leaq 880(%rsp), %rdi
.LEHB4:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE4:
leaq 304(%rsp), %rsi
leaq 880(%rsp), %rdi
movl $8, %edx
.LEHB5:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@PLT
movl 1168(%rsp), %eax
movl %eax, %ecx
andl $5, %ecx
movl %ecx, 12(%rsp)
jne .L78
leaq .LC8(%rip), %r13
andl $2, %eax
movl %eax, 8(%rsp)
je .L79
.L80:
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L149
.L78:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L150
.L157:
movq 1400(%rsp), %rax
subq %fs:40, %rax
jne .L151
call _ZSt16__throw_bad_castv@PLT
.L133:
endbr64
movq %rax, %rbx
jmp .L99
.L151:
call __stack_chk_fail@PLT
.L84:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
.LEHE5:
movl %eax, %edx
jmp .L85
.L158:
leaq 368(%rsp), %rbx
leaq 496(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 496(%rsp)
movq $0, 712(%rsp)
movb $0, 720(%rsp)
movb $0, 721(%rsp)
movq $0, 728(%rsp)
movq $0, 736(%rsp)
movq $0, 744(%rsp)
movq $0, 752(%rsp)
movq 16+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 368(%rsp)
movq -24(%rax), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 368(%rsp,%rax)
movq $0, 376(%rsp)
movq 368(%rsp), %rax
addq -24(%rax), %rbx
movq %rbx, %rdi
movl $0, %esi
.LEHB6:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE6:
movq 32+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 384(%rsp)
movq -24(%rax), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 384(%rsp,%rax)
movq 384(%rsp), %rax
movq -24(%rax), %rax
leaq 384(%rsp,%rax), %rdi
movl $0, %esi
.LEHB7:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE7:
movq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 368(%rsp)
movq -24(%rax), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 368(%rsp,%rax)
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 368(%rsp)
leaq 80(%rax), %rax
movq %rax, 496(%rsp)
leaq -40(%rax), %rax
movq %rax, 384(%rsp)
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 392(%rsp)
movq $0, 400(%rsp)
movq $0, 408(%rsp)
movq $0, 416(%rsp)
movq $0, 424(%rsp)
movq $0, 432(%rsp)
movq $0, 440(%rsp)
leaq 448(%rsp), %rdi
call _ZNSt6localeC1Ev@PLT
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 392(%rsp)
movl $0, 456(%rsp)
movq 248(%rsp), %rdx
movq 240(%rsp), %rsi
leaq 480(%rsp), %rax
movq %rax, 464(%rsp)
testq %rsi, %rsi
jne .L88
testq %rdx, %rdx
jne .L152
.L88:
addq %rsi, %rdx
leaq 464(%rsp), %rdi
.LEHB8:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPKcEEvT_S8_St20forward_iterator_tag
jmp .L153
.L138:
endbr64
movq %rax, %rbx
movq 16+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 368(%rsp)
movq -24(%rax), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 368(%rsp,%rax)
movq $0, 376(%rsp)
.L90:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 496(%rsp)
leaq 496(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
.L99:
leaq 880(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L121:
leaq 336(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L122:
leaq 304(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L123:
leaq 176(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 144(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 112(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 272(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 240(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 208(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 1400(%rsp), %rax
subq %fs:40, %rax
je .L124
call __stack_chk_fail@PLT
.L152:
movq 1400(%rsp), %rax
subq %fs:40, %rax
jne .L154
leaq .LC6(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.LEHE8:
.L139:
endbr64
movq %rax, %rbx
jmp .L94
.L154:
call __stack_chk_fail@PLT
.L153:
movl $24, 456(%rsp)
leaq 392(%rsp), %rdi
movl $0, %ecx
movl $0, %edx
movq 464(%rsp), %rsi
.LEHB9:
call _ZNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEE7_M_syncEPcmm@PLT
.LEHE9:
jmp .L155
.L140:
endbr64
movq %rax, %rbx
leaq 464(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L94:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 392(%rsp)
leaq 448(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
.L95:
leaq 368(%rsp), %rdi
leaq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
call _ZNSdD2Ev@PLT
jmp .L90
.L155:
leaq 392(%rsp), %rsi
leaq 496(%rsp), %rdi
.LEHB10:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE10:
jmp .L156
.L137:
endbr64
movq %rax, %rbx
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 392(%rsp)
movq 464(%rsp), %rdi
leaq 480(%rsp), %rax
cmpq %rax, %rdi
je .L98
movq 480(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L98:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 392(%rsp)
leaq 448(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
jmp .L95
.L136:
endbr64
movq %rax, %rbx
jmp .L90
.L164:
movl $0, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq strtod@GOTPCREL(%rip), %rdi
.LEHB11:
call _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
movsd %xmm0, 64(%rsp)
leaq 64(%rsp), %rsi
leaq 176(%rsp), %rdi
call _ZNSt6vectorIdSaIdEE12emplace_backIJdEEERdDpOT_
jmp .L106
.L165:
movl $0, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq strtod@GOTPCREL(%rip), %rdi
call _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
movsd %xmm0, 64(%rsp)
leaq 64(%rsp), %rsi
leaq 80(%rsp), %rdi
call _ZNSt6vectorIdSaIdEE12emplace_backIJdEEERdDpOT_
jmp .L108
.L166:
movl $0, %ecx
movq 272(%rsp), %rdx
movq %r13, %rsi
movq strtod@GOTPCREL(%rip), %rdi
call _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
movsd %xmm0, 64(%rsp)
leaq 64(%rsp), %rsi
leaq 112(%rsp), %rdi
call _ZNSt6vectorIdSaIdEE12emplace_backIJdEEERdDpOT_
jmp .L108
.L167:
movl $0, %ecx
movq 272(%rsp), %rdx
movq %r13, %rsi
movq strtod@GOTPCREL(%rip), %rdi
call _ZN9__gnu_cxx6__stoaIddcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
movsd %xmm0, 64(%rsp)
leaq 64(%rsp), %rsi
leaq 144(%rsp), %rdi
call _ZNSt6vectorIdSaIdEE12emplace_backIJdEEERdDpOT_
.LEHE11:
jmp .L108
.L156:
movl 8(%rsp), %ebp
leaq .LC7(%rip), %r15
movl $2147483648, %r14d
jmp .L96
.L168:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L102
movq 280(%rsp), %rbx
movq 272(%rsp), %r12
testq %rbx, %rbx
je .L100
cmpb $35, (%r12)
jne .L101
leaq -1(%rbx), %rax
cmpq %r14, %rax
jge .L101
movabsq $-2147483649, %rcx
cmpq %rcx, %rax
jg .L126
.L101:
movl $2, %edx
cmpq %rdx, %rbx
cmovbe %rbx, %rdx
movq %r15, %rsi
movq %r12, %rdi
call memcmp@PLT
testl %eax, %eax
jne .L104
leaq -2(%rbx), %rax
cmpq %r14, %rax
jge .L104
movabsq $-2147483649, %rcx
cmpq %rcx, %rax
jg .L125
jmp .L104
.L102:
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 368(%rsp)
leaq 80(%rax), %rax
movq %rax, 496(%rsp)
leaq -40(%rax), %rax
movq %rax, 384(%rsp)
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 392(%rsp)
movq 464(%rsp), %rdi
leaq 480(%rsp), %rax
cmpq %rax, %rdi
je .L110
movq 480(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L110:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 392(%rsp)
leaq 448(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 368(%rsp)
movq -24(%rax), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 368(%rsp,%rax)
movq 32+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 384(%rsp)
movq -24(%rax), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 384(%rsp,%rax)
movq 16+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 368(%rsp)
movq -24(%rax), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 368(%rsp,%rax)
movq $0, 376(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 496(%rsp)
leaq 496(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
testb $2, 1168(%rsp)
jne .L80
.L79:
movq 880(%rsp), %rax
movq -24(%rax), %rax
movq 1120(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L157
cmpb $0, 56(%rbx)
je .L84
movzbl 67(%rbx), %edx
.L85:
movsbl %dl, %edx
leaq 240(%rsp), %rsi
leaq 880(%rsp), %rdi
.LEHB12:
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L158
.L149:
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 368(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE12:
leaq 336(%rsp), %rsi
leaq 368(%rsp), %rdi
movl $16, %edx
.LEHB13:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE4openERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@PLT
movq 80(%rsp), %r12
movq 88(%rsp), %rbp
subq %r12, %rbp
sarq $3, %rbp
movq 112(%rsp), %r15
movq 144(%rsp), %r14
movslq %ebp, %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $119, %edx
leaq .LC11(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $120, %edx
leaq .LC11(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $121, %edx
leaq .LC11(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $122, %edx
leaq .LC11(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $136, %edx
leaq .LC11(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $137, %edx
leaq .LC11(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $138, %edx
leaq .LC11(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $139, %edx
leaq .LC11(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
leal 1023(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L111
movl %ebp, %r8d
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z44__device_stub__Z17dipoleCorrelationPdS_S_S_iPdS_S_S_i
.L111:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $146, %edx
leaq .LC11(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $148, %edx
leaq .LC11(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 368(%rsp), %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 368(%rsp), %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %ebp, %ebp
jle .L112
leal -1(%rbp), %eax
leaq 8(,%rax,8), %r14
movl $0, %ebp
leaq .LC14(%rip), %r15
jmp .L117
.L162:
movq %rax, %rbx
movl $1, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 0(%r13,%rbp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L159
cmpb $0, 56(%r12)
je .L115
movzbl 67(%r12), %esi
.L116:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L160
.L159:
movq 1400(%rsp), %rax
subq %fs:40, %rax
jne .L161
call _ZSt16__throw_bad_castv@PLT
.L135:
endbr64
movq %rax, %rbx
leaq 368(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
jmp .L99
.L161:
call __stack_chk_fail@PLT
.L115:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L116
.L160:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rbp
cmpq %r14, %rbp
je .L112
.L117:
movq 176(%rsp), %rax
movsd (%rax,%rbp), %xmm0
leaq 368(%rsp), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L162
.L112:
leaq 368(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
testq %r13, %r13
je .L118
movq %r13, %rdi
call _ZdaPv@PLT
.L118:
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $166, %edx
leaq .LC11(%rip), %rsi
call _Z9gpuAssert9cudaErrorPKcib
.LEHE13:
leaq 368(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L81:
leaq 880(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 336(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 304(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 176(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 144(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 112(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 272(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 240(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 208(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 1400(%rsp), %rax
subq %fs:40, %rax
jne .L163
movl 12(%rsp), %eax
addq $1416, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L150:
.cfi_restore_state
movl $-1, 12(%rsp)
jmp .L81
.L134:
endbr64
movq %rax, %rbx
leaq 368(%rsp), %rdi
call _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@PLT
jmp .L99
.L132:
endbr64
movq %rax, %rbx
jmp .L121
.L131:
endbr64
movq %rax, %rbx
jmp .L122
.L130:
endbr64
movq %rax, %rbx
jmp .L123
.L124:
movq %rbx, %rdi
.LEHB14:
call _Unwind_Resume@PLT
.LEHE14:
.L100:
leaq -1(%rbx), %rax
.L126:
testl %eax, %eax
je .L102
leaq -2(%rbx), %rax
testq %rbx, %rbx
jne .L101
.L125:
testl %eax, %eax
je .L102
.L104:
testl %ebp, %ebp
je .L164
cmpl $8, %ebp
je .L165
cmpl $9, %ebp
je .L166
.L106:
cmpl $10, %ebp
je .L167
.L108:
addl $1, %ebp
.L96:
leaq 272(%rsp), %rsi
leaq 368(%rsp), %rdi
.LEHB15:
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
.LEHE15:
jmp .L168
.L163:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4221:
.section .gcc_except_table,"a",@progbits
.LLSDA4221:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4221-.LLSDACSB4221
.LLSDACSB4221:
.uleb128 .LEHB2-.LFB4221
.uleb128 .LEHE2-.LEHB2
.uleb128 .L130-.LFB4221
.uleb128 0
.uleb128 .LEHB3-.LFB4221
.uleb128 .LEHE3-.LEHB3
.uleb128 .L131-.LFB4221
.uleb128 0
.uleb128 .LEHB4-.LFB4221
.uleb128 .LEHE4-.LEHB4
.uleb128 .L132-.LFB4221
.uleb128 0
.uleb128 .LEHB5-.LFB4221
.uleb128 .LEHE5-.LEHB5
.uleb128 .L133-.LFB4221
.uleb128 0
.uleb128 .LEHB6-.LFB4221
.uleb128 .LEHE6-.LEHB6
.uleb128 .L136-.LFB4221
.uleb128 0
.uleb128 .LEHB7-.LFB4221
.uleb128 .LEHE7-.LEHB7
.uleb128 .L138-.LFB4221
.uleb128 0
.uleb128 .LEHB8-.LFB4221
.uleb128 .LEHE8-.LEHB8
.uleb128 .L139-.LFB4221
.uleb128 0
.uleb128 .LEHB9-.LFB4221
.uleb128 .LEHE9-.LEHB9
.uleb128 .L140-.LFB4221
.uleb128 0
.uleb128 .LEHB10-.LFB4221
.uleb128 .LEHE10-.LEHB10
.uleb128 .L137-.LFB4221
.uleb128 0
.uleb128 .LEHB11-.LFB4221
.uleb128 .LEHE11-.LEHB11
.uleb128 .L134-.LFB4221
.uleb128 0
.uleb128 .LEHB12-.LFB4221
.uleb128 .LEHE12-.LEHB12
.uleb128 .L133-.LFB4221
.uleb128 0
.uleb128 .LEHB13-.LFB4221
.uleb128 .LEHE13-.LEHB13
.uleb128 .L135-.LFB4221
.uleb128 0
.uleb128 .LEHB14-.LFB4221
.uleb128 .LEHE14-.LEHB14
.uleb128 0
.uleb128 0
.uleb128 .LEHB15-.LFB4221
.uleb128 .LEHE15-.LEHB15
.uleb128 .L134-.LFB4221
.uleb128 0
.LLSDACSE4221:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <fstream>
#include <vector>
#include <string>
#include <sstream>
using namespace std;
#define gpuErrchk(ans){gpuAssert((ans), __FILE__, __LINE__);}
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort = true)
{
if(code != cudaSuccess)
{
fprintf(stderr, "GPUassert : %s %s %d\n", cudaGetErrorString(code), file, line);
if(abort) exit(code);
}
}
__global__ void dipoleCorrelation(double *px, double *py, double *pz, double *corr, int N)
{
int tau = threadIdx.x + blockDim.x * blockIdx.x;
double local_corr = 0;
if(tau < N)
{
for(int index = 0; index < N - tau; ++index)
{
local_corr += px[index] * px[index + tau]
+ py[index] * py[index + tau]
+ pz[index] * pz[index + tau];
}
local_corr = local_corr/(N-tau);
corr[tau] = local_corr;
}
__syncthreads();
}
int main()
{
string data, line, word;
int pos(8);
vector< double > dipole_x, dipole_y, dipole_z;
vector< double > t;
const string fileName = "Platinum_nanosphere_run2.stat";
const string fileOut = "CorrfuncCuda.wcorr";
ifstream file;
//open file
file.open(fileName,ios::in);
if(!file)
{
cout<<"Error in opening file"<<endl;
return -1;
}
while(!file.eof())
{
getline(file, line);
int i = 0;
stringstream is(line);
while( is >> word )
{
if (word.compare("#") == 0 || word.compare("##") == 0 ) break;
if(i == 0) t.push_back(stod(word));
if(i == pos)
{
dipole_x.push_back(stod(word));
}
if(i == pos + 1)
{
dipole_y.push_back(stod(word));
}
if(i == pos + 2)
{
dipole_z.push_back(stod(word));
}
i++;
}
}
cout<<"Dipole vector list created"<<endl;
//vector<double> dipole_corr, corr_time;
// calculation of co-orelation function
ofstream outfile;
outfile.open(fileOut);
int N = dipole_x.size();
double *xcomp_dipole = &dipole_x[0]; //convert dipole_x vector to array
double *ycomp_dipole = &dipole_y[0];
double *zcomp_dipole = &dipole_z[0];
double *xcomp_dipole_d, *ycomp_dipole_d, *zcomp_dipole_d;
double *corr_h, *corr_d;
corr_h = (double*)malloc(N*sizeof(double));
double dt = t[1]-t[0];
cout<<"Finding the correlation funciton"<<endl;
gpuErrchk(cudaMalloc((void**)&xcomp_dipole_d, N * sizeof(double)));
gpuErrchk(cudaMalloc((void**)&ycomp_dipole_d, N * sizeof(double)));
gpuErrchk(cudaMalloc((void**)&zcomp_dipole_d, N * sizeof(double)));
gpuErrchk(cudaMalloc((void**)&corr_d, N * sizeof(double)));
/*
for(int index =0; index < N ; ++index)
{
printf("Index: %d Px: %e, Py: %e, Pz: %e\n",index,xcomp_dipole[index],ycomp_dipole[index],zcomp_dipole[index]);
printf("Index: %d Px: %e, Py: %e, Pz: %e\n",index,dipole_x[index],dipole_y[index],dipole_z[index]);
}
*/
gpuErrchk(cudaMemcpy(xcomp_dipole_d, xcomp_dipole, N * sizeof(double), cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(ycomp_dipole_d, ycomp_dipole, N * sizeof(double), cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(zcomp_dipole_d, zcomp_dipole, N * sizeof(double), cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(corr_d, corr_h, N * sizeof(double), cudaMemcpyHostToDevice));
int number_of_blocks;
number_of_blocks = ( N/1024 ) + 1;
dipoleCorrelation<<<number_of_blocks,1024>>> (xcomp_dipole_d, ycomp_dipole_d, zcomp_dipole_d, corr_d, N);
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(corr_h, corr_d, N * sizeof(double), cudaMemcpyDeviceToHost));
outfile<<"## charge velocity autocorrelation function"<<endl;
outfile<<"# time(tau)\t wcorr"<<endl;
for(int count= 0; count < N ; ++count )
{
outfile << t[count] << "\t" << corr_h[count]<<endl;
// cout << t[count] << "\t" << corr_h[count]<<endl;
//dipole_corr.push_back(local_corr/(length - tau));
//corr_time.push_back(tau * dt);
}
outfile.close();
delete [] corr_h;
corr_h = NULL;
gpuErrchk(cudaFree(corr_d));
} | #include "hip/hip_runtime.h"
#include <iostream>
#include <fstream>
#include <vector>
#include <string>
#include <sstream>
using namespace std;
#define gpuErrchk(ans){gpuAssert((ans), __FILE__, __LINE__);}
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort = true)
{
if(code != hipSuccess)
{
fprintf(stderr, "GPUassert : %s %s %d\n", hipGetErrorString(code), file, line);
if(abort) exit(code);
}
}
__global__ void dipoleCorrelation(double *px, double *py, double *pz, double *corr, int N)
{
int tau = threadIdx.x + blockDim.x * blockIdx.x;
double local_corr = 0;
if(tau < N)
{
for(int index = 0; index < N - tau; ++index)
{
local_corr += px[index] * px[index + tau]
+ py[index] * py[index + tau]
+ pz[index] * pz[index + tau];
}
local_corr = local_corr/(N-tau);
corr[tau] = local_corr;
}
__syncthreads();
}
int main()
{
string data, line, word;
int pos(8);
vector< double > dipole_x, dipole_y, dipole_z;
vector< double > t;
const string fileName = "Platinum_nanosphere_run2.stat";
const string fileOut = "CorrfuncCuda.wcorr";
ifstream file;
//open file
file.open(fileName,ios::in);
if(!file)
{
cout<<"Error in opening file"<<endl;
return -1;
}
while(!file.eof())
{
getline(file, line);
int i = 0;
stringstream is(line);
while( is >> word )
{
if (word.compare("#") == 0 || word.compare("##") == 0 ) break;
if(i == 0) t.push_back(stod(word));
if(i == pos)
{
dipole_x.push_back(stod(word));
}
if(i == pos + 1)
{
dipole_y.push_back(stod(word));
}
if(i == pos + 2)
{
dipole_z.push_back(stod(word));
}
i++;
}
}
cout<<"Dipole vector list created"<<endl;
//vector<double> dipole_corr, corr_time;
// calculation of co-orelation function
ofstream outfile;
outfile.open(fileOut);
int N = dipole_x.size();
double *xcomp_dipole = &dipole_x[0]; //convert dipole_x vector to array
double *ycomp_dipole = &dipole_y[0];
double *zcomp_dipole = &dipole_z[0];
double *xcomp_dipole_d, *ycomp_dipole_d, *zcomp_dipole_d;
double *corr_h, *corr_d;
corr_h = (double*)malloc(N*sizeof(double));
double dt = t[1]-t[0];
cout<<"Finding the correlation funciton"<<endl;
gpuErrchk(hipMalloc((void**)&xcomp_dipole_d, N * sizeof(double)));
gpuErrchk(hipMalloc((void**)&ycomp_dipole_d, N * sizeof(double)));
gpuErrchk(hipMalloc((void**)&zcomp_dipole_d, N * sizeof(double)));
gpuErrchk(hipMalloc((void**)&corr_d, N * sizeof(double)));
/*
for(int index =0; index < N ; ++index)
{
printf("Index: %d Px: %e, Py: %e, Pz: %e\n",index,xcomp_dipole[index],ycomp_dipole[index],zcomp_dipole[index]);
printf("Index: %d Px: %e, Py: %e, Pz: %e\n",index,dipole_x[index],dipole_y[index],dipole_z[index]);
}
*/
gpuErrchk(hipMemcpy(xcomp_dipole_d, xcomp_dipole, N * sizeof(double), hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(ycomp_dipole_d, ycomp_dipole, N * sizeof(double), hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(zcomp_dipole_d, zcomp_dipole, N * sizeof(double), hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(corr_d, corr_h, N * sizeof(double), hipMemcpyHostToDevice));
int number_of_blocks;
number_of_blocks = ( N/1024 ) + 1;
dipoleCorrelation<<<number_of_blocks,1024>>> (xcomp_dipole_d, ycomp_dipole_d, zcomp_dipole_d, corr_d, N);
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipMemcpy(corr_h, corr_d, N * sizeof(double), hipMemcpyDeviceToHost));
outfile<<"## charge velocity autocorrelation function"<<endl;
outfile<<"# time(tau)\t wcorr"<<endl;
for(int count= 0; count < N ; ++count )
{
outfile << t[count] << "\t" << corr_h[count]<<endl;
// cout << t[count] << "\t" << corr_h[count]<<endl;
//dipole_corr.push_back(local_corr/(length - tau));
//corr_time.push_back(tau * dt);
}
outfile.close();
delete [] corr_h;
corr_h = NULL;
gpuErrchk(hipFree(corr_d));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <iostream>
#include <fstream>
#include <vector>
#include <string>
#include <sstream>
using namespace std;
#define gpuErrchk(ans){gpuAssert((ans), __FILE__, __LINE__);}
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort = true)
{
if(code != hipSuccess)
{
fprintf(stderr, "GPUassert : %s %s %d\n", hipGetErrorString(code), file, line);
if(abort) exit(code);
}
}
__global__ void dipoleCorrelation(double *px, double *py, double *pz, double *corr, int N)
{
int tau = threadIdx.x + blockDim.x * blockIdx.x;
double local_corr = 0;
if(tau < N)
{
for(int index = 0; index < N - tau; ++index)
{
local_corr += px[index] * px[index + tau]
+ py[index] * py[index + tau]
+ pz[index] * pz[index + tau];
}
local_corr = local_corr/(N-tau);
corr[tau] = local_corr;
}
__syncthreads();
}
int main()
{
string data, line, word;
int pos(8);
vector< double > dipole_x, dipole_y, dipole_z;
vector< double > t;
const string fileName = "Platinum_nanosphere_run2.stat";
const string fileOut = "CorrfuncCuda.wcorr";
ifstream file;
//open file
file.open(fileName,ios::in);
if(!file)
{
cout<<"Error in opening file"<<endl;
return -1;
}
while(!file.eof())
{
getline(file, line);
int i = 0;
stringstream is(line);
while( is >> word )
{
if (word.compare("#") == 0 || word.compare("##") == 0 ) break;
if(i == 0) t.push_back(stod(word));
if(i == pos)
{
dipole_x.push_back(stod(word));
}
if(i == pos + 1)
{
dipole_y.push_back(stod(word));
}
if(i == pos + 2)
{
dipole_z.push_back(stod(word));
}
i++;
}
}
cout<<"Dipole vector list created"<<endl;
//vector<double> dipole_corr, corr_time;
// calculation of co-orelation function
ofstream outfile;
outfile.open(fileOut);
int N = dipole_x.size();
double *xcomp_dipole = &dipole_x[0]; //convert dipole_x vector to array
double *ycomp_dipole = &dipole_y[0];
double *zcomp_dipole = &dipole_z[0];
double *xcomp_dipole_d, *ycomp_dipole_d, *zcomp_dipole_d;
double *corr_h, *corr_d;
corr_h = (double*)malloc(N*sizeof(double));
double dt = t[1]-t[0];
cout<<"Finding the correlation funciton"<<endl;
gpuErrchk(hipMalloc((void**)&xcomp_dipole_d, N * sizeof(double)));
gpuErrchk(hipMalloc((void**)&ycomp_dipole_d, N * sizeof(double)));
gpuErrchk(hipMalloc((void**)&zcomp_dipole_d, N * sizeof(double)));
gpuErrchk(hipMalloc((void**)&corr_d, N * sizeof(double)));
/*
for(int index =0; index < N ; ++index)
{
printf("Index: %d Px: %e, Py: %e, Pz: %e\n",index,xcomp_dipole[index],ycomp_dipole[index],zcomp_dipole[index]);
printf("Index: %d Px: %e, Py: %e, Pz: %e\n",index,dipole_x[index],dipole_y[index],dipole_z[index]);
}
*/
gpuErrchk(hipMemcpy(xcomp_dipole_d, xcomp_dipole, N * sizeof(double), hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(ycomp_dipole_d, ycomp_dipole, N * sizeof(double), hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(zcomp_dipole_d, zcomp_dipole, N * sizeof(double), hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(corr_d, corr_h, N * sizeof(double), hipMemcpyHostToDevice));
int number_of_blocks;
number_of_blocks = ( N/1024 ) + 1;
dipoleCorrelation<<<number_of_blocks,1024>>> (xcomp_dipole_d, ycomp_dipole_d, zcomp_dipole_d, corr_d, N);
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipMemcpy(corr_h, corr_d, N * sizeof(double), hipMemcpyDeviceToHost));
outfile<<"## charge velocity autocorrelation function"<<endl;
outfile<<"# time(tau)\t wcorr"<<endl;
for(int count= 0; count < N ; ++count )
{
outfile << t[count] << "\t" << corr_h[count]<<endl;
// cout << t[count] << "\t" << corr_h[count]<<endl;
//dipole_corr.push_back(local_corr/(length - tau));
//corr_time.push_back(tau * dt);
}
outfile.close();
delete [] corr_h;
corr_h = NULL;
gpuErrchk(hipFree(corr_d));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17dipoleCorrelationPdS_S_S_i
.globl _Z17dipoleCorrelationPdS_S_S_i
.p2align 8
.type _Z17dipoleCorrelationPdS_S_S_i,@function
_Z17dipoleCorrelationPdS_S_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x20
s_mov_b32 s14, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v2, 0
v_sub_nc_u32_e32 v0, s2, v1
v_mov_b32_e32 v3, 0
s_mov_b32 s16, 0
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e32 0, v0
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s17, 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[8:9], s[2:3]
s_mov_b64 s[10:11], s[6:7]
s_mov_b64 s[12:13], s[4:5]
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
v_add_nc_u32_e32 v4, s17, v1
s_load_b64 s[18:19], s[10:11], 0x0
s_add_i32 s17, s17, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v5, vcc_lo
global_load_b64 v[6:7], v[6:7], off
v_add_co_u32 v4, vcc_lo, s2, v4
global_load_b64 v[8:9], v[8:9], off
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, s17, v0
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(2) lgkmcnt(0)
v_mul_f64 v[6:7], s[18:19], v[6:7]
s_load_b64 s[18:19], s[12:13], 0x0
s_add_u32 s12, s12, 8
s_addc_u32 s13, s13, 0
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_waitcnt vmcnt(1) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[6:7], s[18:19], v[8:9], v[6:7]
s_load_b64 s[18:19], s[8:9], 0x0
s_add_u32 s8, s8, 8
s_addc_u32 s9, s9, 0
s_or_b32 s16, vcc_lo, s16
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], s[18:19], v[4:5], v[6:7]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB0_3
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s16
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s15
v_cvt_f64_i32_e32 v[4:5], v0
s_load_b64 s[0:1], s[0:1], 0x18
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[10:11], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
v_div_fixup_f64 v[3:4], v[6:7], v[4:5], v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17dipoleCorrelationPdS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17dipoleCorrelationPdS_S_S_i, .Lfunc_end0-_Z17dipoleCorrelationPdS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17dipoleCorrelationPdS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z17dipoleCorrelationPdS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17dipoleCorrelationPdS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ BSSY B0, 0xaa0 ; /* 0x00000a7000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R7, R2, c[0x0][0x0], R3 ; /* 0x0000000002077a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x180], PT ; /* 0x0000600007007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 BRA 0xa90 ; /* 0x00000a2000000947 */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R6, -R7, c[0x0][0x180], RZ ; /* 0x0000600007067a10 */
/* 0x000fe20007ffe1ff */
/*0080*/ BSSY B1, 0x8e0 ; /* 0x0000085000017945 */
/* 0x000fe20003800000 */
/*0090*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe4000001ff00 */
/*00a0*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f06270 */
/*00b0*/ @!P0 BRA 0x8d0 ; /* 0x0000081000008947 */
/* 0x000fea0003800000 */
/*00c0*/ LOP3.LUT R0, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff007212 */
/* 0x000fe200078e33ff */
/*00d0*/ BSSY B2, 0x710 ; /* 0x0000063000027945 */
/* 0x000fe20003800000 */
/*00e0*/ LOP3.LUT R5, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306057812 */
/* 0x000fe200078ec0ff */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a10 */
/* 0x000fe20007ffe0ff */
/*0110*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*0120*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0130*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f26070 */
/*0140*/ @!P1 BRA 0x700 ; /* 0x000005b000009947 */
/* 0x000fea0003800000 */
/*0150*/ ULDC.64 UR8, c[0x0][0x160] ; /* 0x0000580000087ab9 */
/* 0x000fe20000000a00 */
/*0160*/ IMAD.MOV R0, RZ, RZ, -R2 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0a02 */
/*0170*/ UIADD3 UR8, UP0, UR8, 0x10, URZ ; /* 0x0000001008087890 */
/* 0x000fe2000ff1e03f */
/*0180*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*0190*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*01a0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x8 ; /* 0x00000008ff087424 */
/* 0x000fe200078e00ff */
/*01b0*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*01c0*/ IMAD R0, R0, R9, c[0x0][0x180] ; /* 0x0000600000007624 */
/* 0x000fe200078e0209 */
/*01d0*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*01e0*/ IMAD.WIDE R8, R7, R8, c[0x2][0x0] ; /* 0x0080000007087625 */
/* 0x000fe200078e0208 */
/*01f0*/ UIADD3 UR6, UP1, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff3e03f */
/*0200*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*0210*/ UIADD3 UR4, UP0, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000ff1e03f */
/*0220*/ IADD3 R3, -R3, R0, -R5 ; /* 0x0000000003037210 */
/* 0x000fe20007ffe905 */
/*0230*/ UIADD3.X UR7, URZ, UR7, URZ, UP1, !UPT ; /* 0x000000073f077290 */
/* 0x000fe20008ffe43f */
/*0240*/ IADD3 R2, P1, R8.reuse, c[0x0][0x160], RZ ; /* 0x0000580008027a10 */
/* 0x040fe20007f3e0ff */
/*0250*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0260*/ IADD3 R10, P2, R8.reuse, c[0x0][0x168], RZ ; /* 0x00005a00080a7a10 */
/* 0x040fe20007f5e0ff */
/*0270*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0280*/ IADD3 R0, P3, R8, c[0x0][0x170], RZ ; /* 0x00005c0008007a10 */
/* 0x000fe20007f7e0ff */
/*0290*/ IMAD.U32 R12, RZ, RZ, UR8 ; /* 0x00000008ff0c7e24 */
/* 0x000fe2000f8e00ff */
/*02a0*/ IADD3.X R15, R9.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x00005900090f7a10 */
/* 0x040fe20000ffe4ff */
/*02b0*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*02c0*/ IADD3.X R11, R9.reuse, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b00090b7a10 */
/* 0x040fe200017fe4ff */
/*02d0*/ IMAD.U32 R24, RZ, RZ, UR4 ; /* 0x00000004ff187e24 */
/* 0x000fe2000f8e00ff */
/*02e0*/ IADD3.X R23, R9, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0009177a10 */
/* 0x000fe20001ffe4ff */
/*02f0*/ IMAD.U32 R13, RZ, RZ, UR9 ; /* 0x00000009ff0d7e24 */
/* 0x000fc4000f8e00ff */
/*0300*/ IMAD.U32 R9, RZ, RZ, UR7 ; /* 0x00000007ff097e24 */
/* 0x000fe4000f8e00ff */
/*0310*/ IMAD.U32 R25, RZ, RZ, UR5 ; /* 0x00000005ff197e24 */
/* 0x000fe4000f8e00ff */
/*0320*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0330*/ IMAD.MOV.U32 R14, RZ, RZ, R2 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0002 */
/*0340*/ LDG.E.64 R18, [R10.64+-0x10] ; /* 0xfffff0040a127981 */
/* 0x000ea8000c1e1b00 */
/*0350*/ LDG.E.64 R16, [R8.64+-0x10] ; /* 0xfffff00408107981 */
/* 0x000ea8000c1e1b00 */
/*0360*/ LDG.E.64 R28, [R14.64+-0x10] ; /* 0xfffff0040e1c7981 */
/* 0x000ee8000c1e1b00 */
/*0370*/ LDG.E.64 R26, [R12.64+-0x10] ; /* 0xfffff0040c1a7981 */
/* 0x000ee2000c1e1b00 */
/*0380*/ DMUL R16, R18, R16 ; /* 0x0000001012107228 */
/* 0x0040c40000000000 */
/*0390*/ IMAD.MOV.U32 R18, RZ, RZ, R0 ; /* 0x000000ffff127224 */
/* 0x001fe400078e0000 */
/*03a0*/ IMAD.MOV.U32 R19, RZ, RZ, R23 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0017 */
/*03b0*/ LDG.E.64 R22, [R8.64+-0x8] ; /* 0xfffff80408167981 */
/* 0x000ea2000c1e1b00 */
/*03c0*/ DFMA R26, R28, R26, R16 ; /* 0x0000001a1c1a722b */
/* 0x0080640000000010 */
/*03d0*/ IMAD.MOV.U32 R16, RZ, RZ, R24 ; /* 0x000000ffff107224 */
/* 0x001fe200078e0018 */
/*03e0*/ LDG.E.64 R30, [R18.64+-0x10] ; /* 0xfffff004121e7981 */
/* 0x000e62000c1e1b00 */
/*03f0*/ IMAD.MOV.U32 R17, RZ, RZ, R25 ; /* 0x000000ffff117224 */
/* 0x000fc600078e0019 */
/*0400*/ LDG.E.64 R24, [R10.64+-0x8] ; /* 0xfffff8040a187981 */
/* 0x000ea8000c1e1b00 */
/*0410*/ LDG.E.64 R28, [R16.64+-0x10] ; /* 0xfffff004101c7981 */
/* 0x000e64000c1e1b00 */
/*0420*/ DFMA R30, R30, R28, R26 ; /* 0x0000001c1e1e722b */
/* 0x002064000000001a */
/*0430*/ LDG.E.64 R28, [R14.64+-0x8] ; /* 0xfffff8040e1c7981 */
/* 0x001ee8000c1e1b00 */
/*0440*/ LDG.E.64 R26, [R12.64+-0x8] ; /* 0xfffff8040c1a7981 */
/* 0x000ee2000c1e1b00 */
/*0450*/ DMUL R22, R24, R22 ; /* 0x0000001618167228 */
/* 0x0040c60000000000 */
/*0460*/ LDG.E.64 R24, [R16.64+-0x8] ; /* 0xfffff80410187981 */
/* 0x001ea2000c1e1b00 */
/*0470*/ DADD R30, R30, R20 ; /* 0x000000001e1e7229 */
/* 0x0021c60000000014 */
/*0480*/ LDG.E.64 R20, [R18.64+-0x8] ; /* 0xfffff80412147981 */
/* 0x001ea2000c1e1b00 */
/*0490*/ DFMA R22, R28, R26, R22 ; /* 0x0000001a1c16722b */
/* 0x0080860000000016 */
/*04a0*/ LDG.E.64 R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x001ee8000c1e1b00 */
/*04b0*/ LDG.E.64 R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x000f22000c1e1b00 */
/*04c0*/ DFMA R20, R20, R24, R22 ; /* 0x000000181414722b */
/* 0x0040460000000016 */
/*04d0*/ LDG.E.64 R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x001ea8000c1e1b00 */
/*04e0*/ LDG.E.64 R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ea2000c1e1b00 */
/*04f0*/ DADD R20, R30, R20 ; /* 0x000000001e147229 */
/* 0x0021c60000000014 */
/*0500*/ LDG.E.64 R30, [R12.64] ; /* 0x000000040c1e7981 */
/* 0x001ee2000c1e1b00 */
/*0510*/ DMUL R22, R24, R22 ; /* 0x0000001618167228 */
/* 0x0040c60000000000 */
/*0520*/ LDG.E.64 R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x001f26000c1e1b00 */
/*0530*/ DFMA R30, R26, R30, R22 ; /* 0x0000001e1a1e722b */
/* 0x0081240000000016 */
/*0540*/ LDG.E.64 R26, [R10.64+0x8] ; /* 0x000008040a1a7981 */
/* 0x001ea8000c1e1b00 */
/*0550*/ LDG.E.64 R22, [R8.64+0x8] ; /* 0x0000080408167981 */
/* 0x000ea2000c1e1b00 */
/*0560*/ DFMA R24, R28, R24, R30 ; /* 0x000000181c18722b */
/* 0x010046000000001e */
/*0570*/ LDG.E.64 R30, [R14.64+0x8] ; /* 0x000008040e1e7981 */
/* 0x0010e8000c1e1b00 */
/*0580*/ LDG.E.64 R28, [R12.64+0x8] ; /* 0x000008040c1c7981 */
/* 0x0008e2000c1e1b00 */
/*0590*/ DADD R20, R20, R24 ; /* 0x0000000014147229 */
/* 0x0023c60000000018 */
/*05a0*/ LDG.E.64 R24, [R16.64+0x8] ; /* 0x0000080410187981 */
/* 0x002f62000c1e1b00 */
/*05b0*/ DMUL R26, R26, R22 ; /* 0x000000161a1a7228 */
/* 0x0042c60000000000 */
/*05c0*/ LDG.E.64 R22, [R18.64+0x8] ; /* 0x0000080412167981 */
/* 0x002f62000c1e1b00 */
/*05d0*/ IADD3 R12, P1, R12, 0x20, RZ ; /* 0x000000200c0c7810 */
/* 0x010fe40007f3e0ff */
/*05e0*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fc60007ffe0ff */
/*05f0*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e060d */
/*0600*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f25270 */
/*0610*/ IADD3 R2, P2, R14, 0x20, RZ ; /* 0x000000200e027810 */
/* 0x000fe40007f5e0ff */
/*0620*/ IADD3 R10, P3, R10, 0x20, RZ ; /* 0x000000200a0a7810 */
/* 0x000fe40007f7e0ff */
/*0630*/ IADD3 R0, P5, R18, 0x20, RZ ; /* 0x0000002012007810 */
/* 0x000fe20007fbe0ff */
/*0640*/ IMAD.X R15, RZ, RZ, R15, P2 ; /* 0x000000ffff0f7224 */
/* 0x001fe200010e060f */
/*0650*/ IADD3 R8, P2, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x000fe20007f5e0ff */
/*0660*/ IMAD.X R11, RZ, RZ, R11, P3 ; /* 0x000000ffff0b7224 */
/* 0x000fe200018e060b */
/*0670*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0680*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*0690*/ DFMA R26, R30, R28, R26 ; /* 0x0000001c1e1a722b */
/* 0x008f4c000000001a */
/*06a0*/ DFMA R22, R22, R24, R26 ; /* 0x000000181616722b */
/* 0x020064000000001a */
/*06b0*/ IADD3 R24, P4, R16, 0x20, RZ ; /* 0x0000002010187810 */
/* 0x001fc80007f9e0ff */
/*06c0*/ DADD R20, R20, R22 ; /* 0x0000000014147229 */
/* 0x0020620000000016 */
/*06d0*/ IMAD.X R25, RZ, RZ, R17, P4 ; /* 0x000000ffff197224 */
/* 0x000fe400020e0611 */
/*06e0*/ IMAD.X R23, RZ, RZ, R19, P5 ; /* 0x000000ffff177224 */
/* 0x001fe200028e0613 */
/*06f0*/ @P1 BRA 0x320 ; /* 0xfffffc2000001947 */
/* 0x002fea000383ffff */
/*0700*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0710*/ @!P0 BRA 0x8d0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0720*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fc800078e00ff */
/*0730*/ IMAD.WIDE R14, R4, R9, c[0x0][0x170] ; /* 0x00005c00040e7625 */
/* 0x000fc800078e0209 */
/*0740*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0209 */
/*0750*/ IMAD.WIDE R8, R4, R9, c[0x0][0x160] ; /* 0x0000580004087625 */
/* 0x000fc800078e0209 */
/*0760*/ IMAD.WIDE R12, R7.reuse, 0x8, R2 ; /* 0x00000008070c7825 */
/* 0x040fe200078e0202 */
/*0770*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0780*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x0010a2000c1e1b00 */
/*0790*/ IMAD.WIDE R24, R7, 0x8, R8 ; /* 0x0000000807187825 */
/* 0x000fc600078e0208 */
/*07a0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*07b0*/ IMAD.WIDE R18, R7, 0x8, R14 ; /* 0x0000000807127825 */
/* 0x000fc600078e020e */
/*07c0*/ LDG.E.64 R16, [R8.64] ; /* 0x0000000408107981 */
/* 0x0022e8000c1e1b00 */
/*07d0*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ee8000c1e1b00 */
/*07e0*/ LDG.E.64 R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000968000c1e1b00 */
/*07f0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f62000c1e1b00 */
/*0800*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0810*/ IADD3 R2, P2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x001fe40007f5e0ff */
/*0820*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0830*/ IADD3 R14, P1, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x010fe20007f3e0ff */
/*0840*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0850*/ IADD3 R8, P3, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x002fc60007f7e0ff */
/*0860*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe400008e060f */
/*0870*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe200018e0609 */
/*0880*/ DMUL R10, R12, R10 ; /* 0x0000000a0c0a7228 */
/* 0x004ecc0000000000 */
/*0890*/ DFMA R10, R24, R16, R10 ; /* 0x00000010180a722b */
/* 0x008f4c000000000a */
/*08a0*/ DFMA R10, R18, R22, R10 ; /* 0x00000016120a722b */
/* 0x020e0c000000000a */
/*08b0*/ DADD R20, R10, R20 ; /* 0x000000000a147229 */
/* 0x0010620000000014 */
/*08c0*/ @P0 BRA 0x760 ; /* 0xfffffe9000000947 */
/* 0x000fea000383ffff */
/*08d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08e0*/ I2F.F64 R8, R6 ; /* 0x0000000600087312 */
/* 0x000ea20000201c00 */
/*08f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0900*/ FSETP.GEU.AND P1, PT, |R21|, 6.5827683646048100446e-37, PT ; /* 0x036000001500780b */
/* 0x002fe20003f2e200 */
/*0910*/ BSSY B1, 0xa50 ; /* 0x0000013000017945 */
/* 0x000fea0003800000 */
/*0920*/ MUFU.RCP64H R3, R9 ; /* 0x0000000900037308 */
/* 0x004e640000001800 */
/*0930*/ DFMA R4, -R8, R2, 1 ; /* 0x3ff000000804742b */
/* 0x002e4c0000000102 */
/*0940*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x002e4c0000000004 */
/*0950*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x002e4c0000000002 */
/*0960*/ DFMA R2, -R8, R4, 1 ; /* 0x3ff000000802742b */
/* 0x002e4c0000000104 */
/*0970*/ DFMA R2, R4, R2, R4 ; /* 0x000000020402722b */
/* 0x002e4c0000000004 */
/*0980*/ DMUL R4, R2, R20 ; /* 0x0000001402047228 */
/* 0x002e4c0000000000 */
/*0990*/ DFMA R10, -R8, R4, R20 ; /* 0x00000004080a722b */
/* 0x003e0c0000000114 */
/*09a0*/ DFMA R2, R2, R10, R4 ; /* 0x0000000a0202722b */
/* 0x001e140000000004 */
/*09b0*/ FFMA R0, RZ, R9, R3 ; /* 0x00000009ff007223 */
/* 0x001fca0000000003 */
/*09c0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*09d0*/ @P0 BRA P1, 0xa40 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*09e0*/ IMAD.MOV.U32 R2, RZ, RZ, R20 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0014 */
/*09f0*/ MOV R0, 0xa20 ; /* 0x00000a2000007802 */
/* 0x000fe20000000f00 */
/*0a00*/ IMAD.MOV.U32 R3, RZ, RZ, R21 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0015 */
/*0a10*/ CALL.REL.NOINC 0xac0 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0a20*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000c */
/*0a30*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0a40*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a50*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fe200078e00ff */
/*0a60*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0a70*/ IMAD.WIDE R4, R7, R4, c[0x0][0x178] ; /* 0x00005e0007047625 */
/* 0x000fca00078e0204 */
/*0a80*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x0005e4000c101b04 */
/*0a90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0aa0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ab0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ac0*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0ad0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0c7424 */
/* 0x000fe200078e00ff */
/*0ae0*/ LOP3.LUT R4, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09047812 */
/* 0x000fe200078ec0ff */
/*0af0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0b00*/ FSETP.GEU.AND P2, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f4e200 */
/*0b10*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*0b20*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0b30*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*0b40*/ LOP3.LUT R6, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003067812 */
/* 0x000fe200078ec0ff */
/*0b50*/ BSSY B2, 0x1060 ; /* 0x0000050000027945 */
/* 0x000fe20003800000 */
/*0b60*/ LOP3.LUT R13, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090d7812 */
/* 0x000fc600078ec0ff */
/*0b70*/ @!P0 DMUL R4, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008048828 */
/* 0x000e220000000000 */
/*0b80*/ ISETP.GE.U32.AND P1, PT, R6, R13, PT ; /* 0x0000000d0600720c */
/* 0x000fc60003f26070 */
/*0b90*/ @!P2 LOP3.LUT R11, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090ba812 */
/* 0x000fe200078ec0ff */
/*0ba0*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff12a224 */
/* 0x000fe200078e00ff */
/*0bb0*/ MUFU.RCP64H R15, R5 ; /* 0x00000005000f7308 */
/* 0x001e240000001800 */
/*0bc0*/ @!P2 ISETP.GE.U32.AND P3, PT, R6, R11, PT ; /* 0x0000000b0600a20c */
/* 0x000fe40003f66070 */
/*0bd0*/ SEL R11, R12.reuse, 0x63400000, !P1 ; /* 0x634000000c0b7807 */
/* 0x040fe40004800000 */
/*0be0*/ @!P2 SEL R19, R12, 0x63400000, !P3 ; /* 0x634000000c13a807 */
/* 0x000fe40005800000 */
/*0bf0*/ LOP3.LUT R11, R11, 0x800fffff, R3, 0xf8, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fc400078ef803 */
/*0c00*/ @!P2 LOP3.LUT R19, R19, 0x80000000, R3, 0xf8, !PT ; /* 0x800000001313a812 */
/* 0x000fc800078ef803 */
/*0c10*/ @!P2 LOP3.LUT R19, R19, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001313a812 */
/* 0x000fe200078efcff */
/*0c20*/ DFMA R16, R14, -R4, 1 ; /* 0x3ff000000e10742b */
/* 0x001e0a0000000804 */
/*0c30*/ @!P2 DFMA R10, R10, 2, -R18 ; /* 0x400000000a0aa82b */
/* 0x000fc80000000812 */
/*0c40*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0c50*/ DFMA R14, R14, R16, R14 ; /* 0x000000100e0e722b */
/* 0x001064000000000e */
/*0c60*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x001fe200078e0006 */
/*0c70*/ @!P2 LOP3.LUT R16, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b10a812 */
/* 0x000fe200078ec0ff */
/*0c80*/ IMAD.MOV.U32 R17, RZ, RZ, R13 ; /* 0x000000ffff117224 */
/* 0x000fe200078e000d */
/*0c90*/ @!P0 LOP3.LUT R17, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005118812 */
/* 0x000fe200078ec0ff */
/*0ca0*/ DFMA R18, R14.reuse, -R4, 1 ; /* 0x3ff000000e12742b */
/* 0x042e220000000804 */
/*0cb0*/ IADD3 R13, R16, -0x1, RZ ; /* 0xffffffff100d7810 */
/* 0x000fe40007ffe0ff */
/*0cc0*/ IADD3 R22, R17, -0x1, RZ ; /* 0xffffffff11167810 */
/* 0x000fe40007ffe0ff */
/*0cd0*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fe20003f04070 */
/*0ce0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e06000000000e */
/*0cf0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fc60000704470 */
/*0d00*/ DMUL R18, R14, R10 ; /* 0x0000000a0e127228 */
/* 0x001e0c0000000000 */
/*0d10*/ DFMA R20, R18, -R4, R10 ; /* 0x800000041214722b */
/* 0x001e0c000000000a */
/*0d20*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*0d30*/ @P0 BRA 0xf00 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0d40*/ LOP3.LUT R3, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009037812 */
/* 0x000fc800078ec0ff */
/*0d50*/ ISETP.GE.U32.AND P0, PT, R6.reuse, R3, PT ; /* 0x000000030600720c */
/* 0x040fe20003f06070 */
/*0d60*/ IMAD.IADD R2, R6, 0x1, -R3 ; /* 0x0000000106027824 */
/* 0x000fc600078e0a03 */
/*0d70*/ SEL R3, R12, 0x63400000, !P0 ; /* 0x634000000c037807 */
/* 0x000fe40004000000 */
/*0d80*/ IMNMX R2, R2, -0x46a00000, !PT ; /* 0xb960000002027817 */
/* 0x000fc80007800200 */
/*0d90*/ IMNMX R2, R2, 0x46a00000, PT ; /* 0x46a0000002027817 */
/* 0x000fca0003800200 */
/*0da0*/ IMAD.IADD R6, R2, 0x1, -R3 ; /* 0x0000000102067824 */
/* 0x000fe400078e0a03 */
/*0db0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0dc0*/ IADD3 R3, R6, 0x7fe00000, RZ ; /* 0x7fe0000006037810 */
/* 0x000fcc0007ffe0ff */
/*0dd0*/ DMUL R12, R14, R2 ; /* 0x000000020e0c7228 */
/* 0x002e540000000000 */
/*0de0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*0df0*/ @P0 BRA 0x1050 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0e00*/ DFMA R4, R14, -R4, R10 ; /* 0x800000040e04722b */
/* 0x000e62000000000a */
/*0e10*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fd200078e00ff */
/*0e20*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x042fe40003f0d000 */
/*0e30*/ LOP3.LUT R9, R5, 0x80000000, R9, 0x48, !PT ; /* 0x8000000005097812 */
/* 0x000fc800078e4809 */
/*0e40*/ LOP3.LUT R3, R9, R3, RZ, 0xfc, !PT ; /* 0x0000000309037212 */
/* 0x000fce00078efcff */
/*0e50*/ @!P0 BRA 0x1050 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0e60*/ IMAD.MOV R5, RZ, RZ, -R6 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a06 */
/*0e70*/ DMUL.RP R2, R14, R2 ; /* 0x000000020e027228 */
/* 0x000e620000008000 */
/*0e80*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0e90*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e86000000000e */
/*0ea0*/ LOP3.LUT R9, R3, R9, RZ, 0x3c, !PT ; /* 0x0000000903097212 */
/* 0x002fc600078e3cff */
/*0eb0*/ IADD3 R4, -R6, -0x43300000, RZ ; /* 0xbcd0000006047810 */
/* 0x004fc80007ffe1ff */
/*0ec0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0ed0*/ FSEL R12, R2, R12, !P0 ; /* 0x0000000c020c7208 */
/* 0x000fe40004000000 */
/*0ee0*/ FSEL R13, R9, R13, !P0 ; /* 0x0000000d090d7208 */
/* 0x000fe20004000000 */
/*0ef0*/ BRA 0x1050 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0f00*/ DSETP.NAN.AND P0, PT, R2, R2, PT ; /* 0x000000020200722a */
/* 0x000e9c0003f08000 */
/*0f10*/ @P0 BRA 0x1030 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0f20*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e9c0003f08000 */
/*0f30*/ @P0 BRA 0x1000 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0f40*/ ISETP.NE.AND P0, PT, R16, R17, PT ; /* 0x000000111000720c */
/* 0x000fe20003f05270 */
/*0f50*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0f60*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0f70*/ @!P0 BRA 0x1050 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0f80*/ ISETP.NE.AND P0, PT, R16, 0x7ff00000, PT ; /* 0x7ff000001000780c */
/* 0x000fe40003f05270 */
/*0f90*/ LOP3.LUT R13, R3, 0x80000000, R9, 0x48, !PT ; /* 0x80000000030d7812 */
/* 0x000fe400078e4809 */
/*0fa0*/ ISETP.EQ.OR P0, PT, R17, RZ, !P0 ; /* 0x000000ff1100720c */
/* 0x000fda0004702670 */
/*0fb0*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0fc0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0fd0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0fe0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*0ff0*/ BRA 0x1050 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1000*/ LOP3.LUT R13, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090d7812 */
/* 0x000fe200078efcff */
/*1010*/ IMAD.MOV.U32 R12, RZ, RZ, R8 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0008 */
/*1020*/ BRA 0x1050 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*1030*/ LOP3.LUT R13, R3, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000030d7812 */
/* 0x000fe200078efcff */
/*1040*/ IMAD.MOV.U32 R12, RZ, RZ, R2 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0002 */
/*1050*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1060*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*1070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*1080*/ RET.REL.NODEC R2 0x0 ; /* 0xffffef7002007950 */
/* 0x000fea0003c3ffff */
/*1090*/ BRA 0x1090; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17dipoleCorrelationPdS_S_S_i
.globl _Z17dipoleCorrelationPdS_S_S_i
.p2align 8
.type _Z17dipoleCorrelationPdS_S_S_i,@function
_Z17dipoleCorrelationPdS_S_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x20
s_mov_b32 s14, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v2, 0
v_sub_nc_u32_e32 v0, s2, v1
v_mov_b32_e32 v3, 0
s_mov_b32 s16, 0
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e32 0, v0
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_mov_b32 s17, 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[8:9], s[2:3]
s_mov_b64 s[10:11], s[6:7]
s_mov_b64 s[12:13], s[4:5]
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
v_add_nc_u32_e32 v4, s17, v1
s_load_b64 s[18:19], s[10:11], 0x0
s_add_i32 s17, s17, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v5, vcc_lo
global_load_b64 v[6:7], v[6:7], off
v_add_co_u32 v4, vcc_lo, s2, v4
global_load_b64 v[8:9], v[8:9], off
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, s17, v0
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(2) lgkmcnt(0)
v_mul_f64 v[6:7], s[18:19], v[6:7]
s_load_b64 s[18:19], s[12:13], 0x0
s_add_u32 s12, s12, 8
s_addc_u32 s13, s13, 0
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_waitcnt vmcnt(1) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[6:7], s[18:19], v[8:9], v[6:7]
s_load_b64 s[18:19], s[8:9], 0x0
s_add_u32 s8, s8, 8
s_addc_u32 s9, s9, 0
s_or_b32 s16, vcc_lo, s16
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], s[18:19], v[4:5], v[6:7]
v_add_f64 v[2:3], v[2:3], v[4:5]
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execnz .LBB0_3
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s16
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s15
v_cvt_f64_i32_e32 v[4:5], v0
s_load_b64 s[0:1], s[0:1], 0x18
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[10:11], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
v_div_fixup_f64 v[3:4], v[6:7], v[4:5], v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17dipoleCorrelationPdS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17dipoleCorrelationPdS_S_S_i, .Lfunc_end0-_Z17dipoleCorrelationPdS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17dipoleCorrelationPdS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z17dipoleCorrelationPdS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void wave1Dmac1(double * f_tmp1, double * f_in,
double u, double dt, double dx,
int N){
int tid = threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p == N) x_p = 0;
double f_tmp = f_in[tid];
f_tmp1[tid]= f_tmp - u*(dt/dx)*(f_in[x_p] - f_tmp);
}
} | code for sm_80
Function : _Z10wave1Dmac1PdS_dddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R15, SR_CTAID.X ; /* 0x00000000000f7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R15, R15, c[0x0][0x0], R0 ; /* 0x000000000f0f7a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R15, c[0x0][0x188], PT ; /* 0x000062000f007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MUFU.RCP64H R3, c[0x0][0x184] ; /* 0x0000610000037b08 */
/* 0x000e220000001800 */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R14, R15, 0x1, RZ ; /* 0x000000010f0e7810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff077624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.NE.AND P0, PT, R14, c[0x0][0x188], PT ; /* 0x000062000e007a0c */
/* 0x000fc80003f05270 */
/*00d0*/ SEL R14, R14, RZ, P0 ; /* 0x000000ff0e0e7207 */
/* 0x000fe20000000000 */
/*00e0*/ DFMA R4, R2, -R6, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c0000000806 */
/*00f0*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*0100*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x001e0c0000000002 */
/*0110*/ DFMA R2, R4, -R6, 1 ; /* 0x3ff000000402742b */
/* 0x001e0c0000000806 */
/*0120*/ DFMA R2, R4, R2, R4 ; /* 0x000000020402722b */
/* 0x001e0c0000000004 */
/*0130*/ DMUL R4, R2, c[0x0][0x178] ; /* 0x00005e0002047a28 */
/* 0x001e0c0000000000 */
/*0140*/ DFMA R6, R4, -R6, c[0x0][0x178] ; /* 0x00005e000406762b */
/* 0x001e0c0000000806 */
/*0150*/ DFMA R4, R2, R6, R4 ; /* 0x000000060204722b */
/* 0x0010640000000004 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x001fca00078e00ff */
/*0170*/ FSETP.GEU.AND P2, PT, |R2|, 6.5827683646048100446e-37, PT ; /* 0x036000000200780b */
/* 0x000fe20003f4e200 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, 0x8 ; /* 0x00000008ff027424 */
/* 0x000fe400078e00ff */
/*0190*/ FFMA R0, RZ, c[0x0][0x184], R5 ; /* 0x00006100ff007a23 */
/* 0x002fe40000000005 */
/*01a0*/ IMAD.WIDE R2, R15, R2, c[0x0][0x168] ; /* 0x00005a000f027625 */
/* 0x000fc600078e0202 */
/*01b0*/ FSETP.GT.AND P1, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f24200 */
/*01c0*/ @P1 BRA P2, 0x1f0 ; /* 0x0000002000001947 */
/* 0x000fea0001000000 */
/*01d0*/ MOV R16, 0x1f0 ; /* 0x000001f000107802 */
/* 0x000fe40000000f00 */
/*01e0*/ CALL.REL.NOINC 0x290 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*01f0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x8 ; /* 0x00000008ff007424 */
/* 0x000fe200078e00ff */
/*0200*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea6000c1e1b00 */
/*0210*/ IMAD.WIDE R6, R14, R0, c[0x0][0x168] ; /* 0x00005a000e067625 */
/* 0x000fcc00078e0200 */
/*0220*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0230*/ DMUL R4, R4, c[0x0][0x170] ; /* 0x00005c0004047a28 */
/* 0x000fc80000000000 */
/*0240*/ DADD R8, R6, -R2 ; /* 0x0000000006087229 */
/* 0x004e0c0000000802 */
/*0250*/ DFMA R4, -R4, R8, R2 ; /* 0x000000080404722b */
/* 0x0010a40000000102 */
/*0260*/ IMAD.WIDE R8, R15, R0, c[0x0][0x160] ; /* 0x000058000f087625 */
/* 0x001fca00078e0200 */
/*0270*/ STG.E.64 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x004fe2000c101b04 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff117624 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff007624 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff157424 */
/* 0x000fe200078e00ff */
/*02c0*/ FSETP.GEU.AND P0, PT, |R17|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000001100780b */
/* 0x040fe20003f0e200 */
/*02d0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*02e0*/ LOP3.LUT R4, R17, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff11047812 */
/* 0x000fe400078ec0ff */
/*02f0*/ FSETP.GEU.AND P2, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fc40003f4e200 */
/*0300*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0310*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe200078e00ff */
/*0320*/ LOP3.LUT R18, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000011127812 */
/* 0x000fe400078ec0ff */
/*0330*/ LOP3.LUT R19, R0, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000000137812 */
/* 0x000fc600078ec0ff */
/*0340*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff068624 */
/* 0x000fe200078e00ff */
/*0350*/ ISETP.GE.U32.AND P1, PT, R19, R18, PT ; /* 0x000000121300720c */
/* 0x000fe20003f26070 */
/*0360*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff078624 */
/* 0x000fe400078e00ff */
/*0370*/ IMAD.MOV.U32 R20, RZ, RZ, R19 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0013 */
/*0380*/ SEL R21, R21, 0x63400000, !P1 ; /* 0x6340000015157807 */
/* 0x000fe20004800000 */
/*0390*/ IMAD.MOV.U32 R23, RZ, RZ, R18 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0012 */
/*03a0*/ @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006048828 */
/* 0x0000620000000000 */
/*03b0*/ @!P2 LOP3.LUT R8, R21.reuse, 0x80000000, R0.reuse, 0xf8, !PT ; /* 0x800000001508a812 */
/* 0x140fe200078ef800 */
/*03c0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x001fe200078e00ff */
/*03d0*/ LOP3.LUT R7, R21, 0x800fffff, R0, 0xf8, !PT ; /* 0x800fffff15077812 */
/* 0x000fc400078ef800 */
/*03e0*/ @!P2 LOP3.LUT R9, R8, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000809a812 */
/* 0x000fe200078efcff */
/*03f0*/ MUFU.RCP64H R11, R5 ; /* 0x00000005000b7308 */
/* 0x002e220000001800 */
/*0400*/ @!P2 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff08a224 */
/* 0x000fc600078e00ff */
/*0410*/ @!P0 LOP3.LUT R23, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005178812 */
/* 0x000fc600078ec0ff */
/*0420*/ @!P2 DFMA R6, R6, 2, -R8 ; /* 0x400000000606a82b */
/* 0x000e620000000808 */
/*0430*/ IADD3 R22, R23, -0x1, RZ ; /* 0xffffffff17167810 */
/* 0x000fc60007ffe0ff */
/*0440*/ DFMA R12, R10, -R4, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c0000000804 */
/*0450*/ @!P2 LOP3.LUT R20, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000714a812 */
/* 0x002fe200078ec0ff */
/*0460*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0470*/ DFMA R10, R10, R12, R10 ; /* 0x0000000c0a0a722b */
/* 0x001064000000000a */
/*0480*/ IADD3 R12, R20, -0x1, RZ ; /* 0xffffffff140c7810 */
/* 0x001fc80007ffe0ff */
/*0490*/ DFMA R8, R10, -R4, 1 ; /* 0x3ff000000a08742b */
/* 0x002e220000000804 */
/*04a0*/ ISETP.GT.U32.AND P0, PT, R12, 0x7feffffe, PT ; /* 0x7feffffe0c00780c */
/* 0x000fc80003f04070 */
/*04b0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fe20000704470 */
/*04c0*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*04d0*/ DMUL R10, R8, R6 ; /* 0x00000006080a7228 */
/* 0x001e0c0000000000 */
/*04e0*/ DFMA R12, R10, -R4, R6 ; /* 0x800000040a0c722b */
/* 0x001e0c0000000006 */
/*04f0*/ DFMA R12, R8, R12, R10 ; /* 0x0000000c080c722b */
/* 0x001062000000000a */
/*0500*/ @P0 BRA 0x6b0 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0510*/ IMAD.IADD R18, R19, 0x1, -R18 ; /* 0x0000000113127824 */
/* 0x000fe400078e0a12 */
/*0520*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x001fc600078e00ff */
/*0530*/ IMNMX R18, R18, -0x46a00000, !PT ; /* 0xb960000012127817 */
/* 0x000fc80007800200 */
/*0540*/ IMNMX R18, R18, 0x46a00000, PT ; /* 0x46a0000012127817 */
/* 0x000fca0003800200 */
/*0550*/ IMAD.IADD R18, R18, 0x1, -R21 ; /* 0x0000000112127824 */
/* 0x000fca00078e0a15 */
/*0560*/ IADD3 R11, R18, 0x7fe00000, RZ ; /* 0x7fe00000120b7810 */
/* 0x000fcc0007ffe0ff */
/*0570*/ DMUL R8, R12, R10 ; /* 0x0000000a0c087228 */
/* 0x002e140000000000 */
/*0580*/ FSETP.GTU.AND P0, PT, |R9|, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x001fda0003f0c200 */
/*0590*/ @P0 BRA 0x850 ; /* 0x000002b000000947 */
/* 0x000fea0003800000 */
/*05a0*/ DFMA R4, R12, -R4, R6 ; /* 0x800000040c04722b */
/* 0x000e220000000006 */
/*05b0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fd200078e00ff */
/*05c0*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*05d0*/ LOP3.LUT R0, R5, c[0x0][0x184], RZ, 0x3c, !PT ; /* 0x0000610005007a12 */
/* 0x000fc800078e3cff */
/*05e0*/ LOP3.LUT R7, R0, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000000077812 */
/* 0x000fc800078ec0ff */
/*05f0*/ LOP3.LUT R11, R7, R11, RZ, 0xfc, !PT ; /* 0x0000000b070b7212 */
/* 0x000fc600078efcff */
/*0600*/ @!P0 BRA 0x850 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*0610*/ IMAD.MOV R5, RZ, RZ, -R18 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a12 */
/*0620*/ DMUL.RP R10, R12, R10 ; /* 0x0000000a0c0a7228 */
/* 0x000e220000008000 */
/*0630*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0640*/ DFMA R4, R8, -R4, R12 ; /* 0x800000040804722b */
/* 0x000e46000000000c */
/*0650*/ LOP3.LUT R7, R11, R7, RZ, 0x3c, !PT ; /* 0x000000070b077212 */
/* 0x001fc600078e3cff */
/*0660*/ IADD3 R4, -R18, -0x43300000, RZ ; /* 0xbcd0000012047810 */
/* 0x002fc80007ffe1ff */
/*0670*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0680*/ FSEL R8, R10, R8, !P0 ; /* 0x000000080a087208 */
/* 0x000fe40004000000 */
/*0690*/ FSEL R9, R7, R9, !P0 ; /* 0x0000000907097208 */
/* 0x000fe20004000000 */
/*06a0*/ BRA 0x850 ; /* 0x000001a000007947 */
/* 0x000fea0003800000 */
/*06b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*06c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fcc00078e00ff */
/*06d0*/ DSETP.NAN.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e000400762a */
/* 0x000e9c0003f08000 */
/*06e0*/ @P0 BRA 0x830 ; /* 0x0000014000000947 */
/* 0x004fea0003800000 */
/*06f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe400078e00ff */
/*0700*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff057624 */
/* 0x000fcc00078e00ff */
/*0710*/ DSETP.NAN.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x000060000400762a */
/* 0x000e9c0003f08000 */
/*0720*/ @P0 BRA 0x800 ; /* 0x000000d000000947 */
/* 0x004fea0003800000 */
/*0730*/ ISETP.NE.AND P0, PT, R20, R23, PT ; /* 0x000000171400720c */
/* 0x000fe20003f05270 */
/*0740*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x001fe400078e00ff */
/*0750*/ IMAD.MOV.U32 R9, RZ, RZ, -0x80000 ; /* 0xfff80000ff097424 */
/* 0x000fd400078e00ff */
/*0760*/ @!P0 BRA 0x850 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0780*/ LOP3.LUT R0, R0, c[0x0][0x184], RZ, 0x3c, !PT ; /* 0x0000610000007a12 */
/* 0x000fe400078e3cff */
/*0790*/ ISETP.EQ.OR P0, PT, R23, RZ, !P0 ; /* 0x000000ff1700720c */
/* 0x000fe40004702670 */
/*07a0*/ LOP3.LUT R9, R0, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000000097812 */
/* 0x000fd600078ec0ff */
/*07b0*/ @P0 LOP3.LUT R0, R9, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000009000812 */
/* 0x000fe200078efcff */
/*07c0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe400078e00ff */
/*07d0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*07e0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, R0 ; /* 0x000000ffff090224 */
/* 0x000fe200078e0000 */
/*07f0*/ BRA 0x850 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R9, R17, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000011097812 */
/* 0x001fe200078efcff */
/*0810*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x000fe200078e00ff */
/*0820*/ BRA 0x850 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R9, R0, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000000097812 */
/* 0x001fe200078efcff */
/*0840*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff087624 */
/* 0x000fe400078e00ff */
/*0850*/ IMAD.MOV.U32 R17, RZ, RZ, 0x0 ; /* 0x00000000ff117424 */
/* 0x000fe400078e00ff */
/*0860*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fc400078e0008 */
/*0870*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0880*/ RET.REL.NODEC R16 0x0 ; /* 0xfffff77010007950 */
/* 0x000fec0003c3ffff */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void wave1Dmac1(double * f_tmp1, double * f_in,
double u, double dt, double dx,
int N){
int tid = threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p == N) x_p = 0;
double f_tmp = f_in[tid];
f_tmp1[tid]= f_tmp - u*(dt/dx)*(f_in[x_p] - f_tmp);
}
} | .file "tmpxft_00090652_00000000-6_wave1Dmac1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10wave1Dmac1PdS_dddiPdS_dddi
.type _Z36__device_stub__Z10wave1Dmac1PdS_dddiPdS_dddi, @function
_Z36__device_stub__Z10wave1Dmac1PdS_dddiPdS_dddi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10wave1Dmac1PdS_dddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z10wave1Dmac1PdS_dddiPdS_dddi, .-_Z36__device_stub__Z10wave1Dmac1PdS_dddiPdS_dddi
.globl _Z10wave1Dmac1PdS_dddi
.type _Z10wave1Dmac1PdS_dddi, @function
_Z10wave1Dmac1PdS_dddi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10wave1Dmac1PdS_dddiPdS_dddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10wave1Dmac1PdS_dddi, .-_Z10wave1Dmac1PdS_dddi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10wave1Dmac1PdS_dddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10wave1Dmac1PdS_dddi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void wave1Dmac1(double * f_tmp1, double * f_in,
double u, double dt, double dx,
int N){
int tid = threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p == N) x_p = 0;
double f_tmp = f_in[tid];
f_tmp1[tid]= f_tmp - u*(dt/dx)*(f_in[x_p] - f_tmp);
}
} | #include <hip/hip_runtime.h>
__global__ void wave1Dmac1(double * f_tmp1, double * f_in,
double u, double dt, double dx,
int N){
int tid = threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p == N) x_p = 0;
double f_tmp = f_in[tid];
f_tmp1[tid]= f_tmp - u*(dt/dx)*(f_in[x_p] - f_tmp);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void wave1Dmac1(double * f_tmp1, double * f_in,
double u, double dt, double dx,
int N){
int tid = threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p == N) x_p = 0;
double f_tmp = f_in[tid];
f_tmp1[tid]= f_tmp - u*(dt/dx)*(f_in[x_p] - f_tmp);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10wave1Dmac1PdS_dddi
.globl _Z10wave1Dmac1PdS_dddi
.p2align 8
.type _Z10wave1Dmac1PdS_dddi,@function
_Z10wave1Dmac1PdS_dddi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
v_add_nc_u32_e32 v0, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v7, 0, v0, vcc_lo
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s6, v0
v_div_scale_f64 v[3:4], null, s[0:1], s[0:1], s[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_clause 0x1
global_load_b64 v[9:10], v[9:10], off
global_load_b64 v[7:8], v[7:8], off
v_div_scale_f64 v[13:14], vcc_lo, s[10:11], s[0:1], s[10:11]
v_rcp_f64_e32 v[5:6], v[3:4]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[3:4], v[5:6], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], v[11:12], v[5:6]
v_fma_f64 v[11:12], -v[3:4], v[5:6], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], v[11:12], v[5:6]
v_mul_f64 v[11:12], v[13:14], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], -v[3:4], v[11:12], v[13:14]
v_div_fmas_f64 v[2:3], v[2:3], v[5:6], v[11:12]
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[7:8], -v[9:10]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[2:3], s[0:1], s[10:11]
v_mul_f64 v[2:3], v[2:3], s[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], -v[2:3], v[4:5], v[9:10]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10wave1Dmac1PdS_dddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10wave1Dmac1PdS_dddi, .Lfunc_end0-_Z10wave1Dmac1PdS_dddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10wave1Dmac1PdS_dddi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10wave1Dmac1PdS_dddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void wave1Dmac1(double * f_tmp1, double * f_in,
double u, double dt, double dx,
int N){
int tid = threadIdx.x+blockIdx.x*blockDim.x;
if(tid<N){
int x_p = tid+1;
if(x_p == N) x_p = 0;
double f_tmp = f_in[tid];
f_tmp1[tid]= f_tmp - u*(dt/dx)*(f_in[x_p] - f_tmp);
}
} | .text
.file "wave1Dmac1.hip"
.globl _Z25__device_stub__wave1Dmac1PdS_dddi # -- Begin function _Z25__device_stub__wave1Dmac1PdS_dddi
.p2align 4, 0x90
.type _Z25__device_stub__wave1Dmac1PdS_dddi,@function
_Z25__device_stub__wave1Dmac1PdS_dddi: # @_Z25__device_stub__wave1Dmac1PdS_dddi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
movl %edx, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10wave1Dmac1PdS_dddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__wave1Dmac1PdS_dddi, .Lfunc_end0-_Z25__device_stub__wave1Dmac1PdS_dddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10wave1Dmac1PdS_dddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10wave1Dmac1PdS_dddi,@object # @_Z10wave1Dmac1PdS_dddi
.section .rodata,"a",@progbits
.globl _Z10wave1Dmac1PdS_dddi
.p2align 3, 0x0
_Z10wave1Dmac1PdS_dddi:
.quad _Z25__device_stub__wave1Dmac1PdS_dddi
.size _Z10wave1Dmac1PdS_dddi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10wave1Dmac1PdS_dddi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__wave1Dmac1PdS_dddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10wave1Dmac1PdS_dddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10wave1Dmac1PdS_dddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R15, SR_CTAID.X ; /* 0x00000000000f7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R15, R15, c[0x0][0x0], R0 ; /* 0x000000000f0f7a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R15, c[0x0][0x188], PT ; /* 0x000062000f007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MUFU.RCP64H R3, c[0x0][0x184] ; /* 0x0000610000037b08 */
/* 0x000e220000001800 */
/*0070*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R14, R15, 0x1, RZ ; /* 0x000000010f0e7810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff077624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.NE.AND P0, PT, R14, c[0x0][0x188], PT ; /* 0x000062000e007a0c */
/* 0x000fc80003f05270 */
/*00d0*/ SEL R14, R14, RZ, P0 ; /* 0x000000ff0e0e7207 */
/* 0x000fe20000000000 */
/*00e0*/ DFMA R4, R2, -R6, 1 ; /* 0x3ff000000204742b */
/* 0x001e0c0000000806 */
/*00f0*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*0100*/ DFMA R4, R2, R4, R2 ; /* 0x000000040204722b */
/* 0x001e0c0000000002 */
/*0110*/ DFMA R2, R4, -R6, 1 ; /* 0x3ff000000402742b */
/* 0x001e0c0000000806 */
/*0120*/ DFMA R2, R4, R2, R4 ; /* 0x000000020402722b */
/* 0x001e0c0000000004 */
/*0130*/ DMUL R4, R2, c[0x0][0x178] ; /* 0x00005e0002047a28 */
/* 0x001e0c0000000000 */
/*0140*/ DFMA R6, R4, -R6, c[0x0][0x178] ; /* 0x00005e000406762b */
/* 0x001e0c0000000806 */
/*0150*/ DFMA R4, R2, R6, R4 ; /* 0x000000060204722b */
/* 0x0010640000000004 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x001fca00078e00ff */
/*0170*/ FSETP.GEU.AND P2, PT, |R2|, 6.5827683646048100446e-37, PT ; /* 0x036000000200780b */
/* 0x000fe20003f4e200 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, 0x8 ; /* 0x00000008ff027424 */
/* 0x000fe400078e00ff */
/*0190*/ FFMA R0, RZ, c[0x0][0x184], R5 ; /* 0x00006100ff007a23 */
/* 0x002fe40000000005 */
/*01a0*/ IMAD.WIDE R2, R15, R2, c[0x0][0x168] ; /* 0x00005a000f027625 */
/* 0x000fc600078e0202 */
/*01b0*/ FSETP.GT.AND P1, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f24200 */
/*01c0*/ @P1 BRA P2, 0x1f0 ; /* 0x0000002000001947 */
/* 0x000fea0001000000 */
/*01d0*/ MOV R16, 0x1f0 ; /* 0x000001f000107802 */
/* 0x000fe40000000f00 */
/*01e0*/ CALL.REL.NOINC 0x290 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*01f0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x8 ; /* 0x00000008ff007424 */
/* 0x000fe200078e00ff */
/*0200*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea6000c1e1b00 */
/*0210*/ IMAD.WIDE R6, R14, R0, c[0x0][0x168] ; /* 0x00005a000e067625 */
/* 0x000fcc00078e0200 */
/*0220*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0230*/ DMUL R4, R4, c[0x0][0x170] ; /* 0x00005c0004047a28 */
/* 0x000fc80000000000 */
/*0240*/ DADD R8, R6, -R2 ; /* 0x0000000006087229 */
/* 0x004e0c0000000802 */
/*0250*/ DFMA R4, -R4, R8, R2 ; /* 0x000000080404722b */
/* 0x0010a40000000102 */
/*0260*/ IMAD.WIDE R8, R15, R0, c[0x0][0x160] ; /* 0x000058000f087625 */
/* 0x001fca00078e0200 */
/*0270*/ STG.E.64 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x004fe2000c101b04 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff117624 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff007624 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff157424 */
/* 0x000fe200078e00ff */
/*02c0*/ FSETP.GEU.AND P0, PT, |R17|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000001100780b */
/* 0x040fe20003f0e200 */
/*02d0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*02e0*/ LOP3.LUT R4, R17, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff11047812 */
/* 0x000fe400078ec0ff */
/*02f0*/ FSETP.GEU.AND P2, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fc40003f4e200 */
/*0300*/ LOP3.LUT R5, R4, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000004057812 */
/* 0x000fe200078efcff */
/*0310*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe200078e00ff */
/*0320*/ LOP3.LUT R18, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000011127812 */
/* 0x000fe400078ec0ff */
/*0330*/ LOP3.LUT R19, R0, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000000137812 */
/* 0x000fc600078ec0ff */
/*0340*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff068624 */
/* 0x000fe200078e00ff */
/*0350*/ ISETP.GE.U32.AND P1, PT, R19, R18, PT ; /* 0x000000121300720c */
/* 0x000fe20003f26070 */
/*0360*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff078624 */
/* 0x000fe400078e00ff */
/*0370*/ IMAD.MOV.U32 R20, RZ, RZ, R19 ; /* 0x000000ffff147224 */
/* 0x000fe200078e0013 */
/*0380*/ SEL R21, R21, 0x63400000, !P1 ; /* 0x6340000015157807 */
/* 0x000fe20004800000 */
/*0390*/ IMAD.MOV.U32 R23, RZ, RZ, R18 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0012 */
/*03a0*/ @!P0 DMUL R4, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006048828 */
/* 0x0000620000000000 */
/*03b0*/ @!P2 LOP3.LUT R8, R21.reuse, 0x80000000, R0.reuse, 0xf8, !PT ; /* 0x800000001508a812 */
/* 0x140fe200078ef800 */
/*03c0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x001fe200078e00ff */
/*03d0*/ LOP3.LUT R7, R21, 0x800fffff, R0, 0xf8, !PT ; /* 0x800fffff15077812 */
/* 0x000fc400078ef800 */
/*03e0*/ @!P2 LOP3.LUT R9, R8, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000809a812 */
/* 0x000fe200078efcff */
/*03f0*/ MUFU.RCP64H R11, R5 ; /* 0x00000005000b7308 */
/* 0x002e220000001800 */
/*0400*/ @!P2 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff08a224 */
/* 0x000fc600078e00ff */
/*0410*/ @!P0 LOP3.LUT R23, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005178812 */
/* 0x000fc600078ec0ff */
/*0420*/ @!P2 DFMA R6, R6, 2, -R8 ; /* 0x400000000606a82b */
/* 0x000e620000000808 */
/*0430*/ IADD3 R22, R23, -0x1, RZ ; /* 0xffffffff17167810 */
/* 0x000fc60007ffe0ff */
/*0440*/ DFMA R12, R10, -R4, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c0000000804 */
/*0450*/ @!P2 LOP3.LUT R20, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000714a812 */
/* 0x002fe200078ec0ff */
/*0460*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*0470*/ DFMA R10, R10, R12, R10 ; /* 0x0000000c0a0a722b */
/* 0x001064000000000a */
/*0480*/ IADD3 R12, R20, -0x1, RZ ; /* 0xffffffff140c7810 */
/* 0x001fc80007ffe0ff */
/*0490*/ DFMA R8, R10, -R4, 1 ; /* 0x3ff000000a08742b */
/* 0x002e220000000804 */
/*04a0*/ ISETP.GT.U32.AND P0, PT, R12, 0x7feffffe, PT ; /* 0x7feffffe0c00780c */
/* 0x000fc80003f04070 */
/*04b0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fe20000704470 */
/*04c0*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*04d0*/ DMUL R10, R8, R6 ; /* 0x00000006080a7228 */
/* 0x001e0c0000000000 */
/*04e0*/ DFMA R12, R10, -R4, R6 ; /* 0x800000040a0c722b */
/* 0x001e0c0000000006 */
/*04f0*/ DFMA R12, R8, R12, R10 ; /* 0x0000000c080c722b */
/* 0x001062000000000a */
/*0500*/ @P0 BRA 0x6b0 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0510*/ IMAD.IADD R18, R19, 0x1, -R18 ; /* 0x0000000113127824 */
/* 0x000fe400078e0a12 */
/*0520*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x001fc600078e00ff */
/*0530*/ IMNMX R18, R18, -0x46a00000, !PT ; /* 0xb960000012127817 */
/* 0x000fc80007800200 */
/*0540*/ IMNMX R18, R18, 0x46a00000, PT ; /* 0x46a0000012127817 */
/* 0x000fca0003800200 */
/*0550*/ IMAD.IADD R18, R18, 0x1, -R21 ; /* 0x0000000112127824 */
/* 0x000fca00078e0a15 */
/*0560*/ IADD3 R11, R18, 0x7fe00000, RZ ; /* 0x7fe00000120b7810 */
/* 0x000fcc0007ffe0ff */
/*0570*/ DMUL R8, R12, R10 ; /* 0x0000000a0c087228 */
/* 0x002e140000000000 */
/*0580*/ FSETP.GTU.AND P0, PT, |R9|, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x001fda0003f0c200 */
/*0590*/ @P0 BRA 0x850 ; /* 0x000002b000000947 */
/* 0x000fea0003800000 */
/*05a0*/ DFMA R4, R12, -R4, R6 ; /* 0x800000040c04722b */
/* 0x000e220000000006 */
/*05b0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fd200078e00ff */
/*05c0*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*05d0*/ LOP3.LUT R0, R5, c[0x0][0x184], RZ, 0x3c, !PT ; /* 0x0000610005007a12 */
/* 0x000fc800078e3cff */
/*05e0*/ LOP3.LUT R7, R0, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000000077812 */
/* 0x000fc800078ec0ff */
/*05f0*/ LOP3.LUT R11, R7, R11, RZ, 0xfc, !PT ; /* 0x0000000b070b7212 */
/* 0x000fc600078efcff */
/*0600*/ @!P0 BRA 0x850 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*0610*/ IMAD.MOV R5, RZ, RZ, -R18 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a12 */
/*0620*/ DMUL.RP R10, R12, R10 ; /* 0x0000000a0c0a7228 */
/* 0x000e220000008000 */
/*0630*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0640*/ DFMA R4, R8, -R4, R12 ; /* 0x800000040804722b */
/* 0x000e46000000000c */
/*0650*/ LOP3.LUT R7, R11, R7, RZ, 0x3c, !PT ; /* 0x000000070b077212 */
/* 0x001fc600078e3cff */
/*0660*/ IADD3 R4, -R18, -0x43300000, RZ ; /* 0xbcd0000012047810 */
/* 0x002fc80007ffe1ff */
/*0670*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0680*/ FSEL R8, R10, R8, !P0 ; /* 0x000000080a087208 */
/* 0x000fe40004000000 */
/*0690*/ FSEL R9, R7, R9, !P0 ; /* 0x0000000907097208 */
/* 0x000fe20004000000 */
/*06a0*/ BRA 0x850 ; /* 0x000001a000007947 */
/* 0x000fea0003800000 */
/*06b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*06c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fcc00078e00ff */
/*06d0*/ DSETP.NAN.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e000400762a */
/* 0x000e9c0003f08000 */
/*06e0*/ @P0 BRA 0x830 ; /* 0x0000014000000947 */
/* 0x004fea0003800000 */
/*06f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff047624 */
/* 0x000fe400078e00ff */
/*0700*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff057624 */
/* 0x000fcc00078e00ff */
/*0710*/ DSETP.NAN.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x000060000400762a */
/* 0x000e9c0003f08000 */
/*0720*/ @P0 BRA 0x800 ; /* 0x000000d000000947 */
/* 0x004fea0003800000 */
/*0730*/ ISETP.NE.AND P0, PT, R20, R23, PT ; /* 0x000000171400720c */
/* 0x000fe20003f05270 */
/*0740*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x001fe400078e00ff */
/*0750*/ IMAD.MOV.U32 R9, RZ, RZ, -0x80000 ; /* 0xfff80000ff097424 */
/* 0x000fd400078e00ff */
/*0760*/ @!P0 BRA 0x850 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0770*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0780*/ LOP3.LUT R0, R0, c[0x0][0x184], RZ, 0x3c, !PT ; /* 0x0000610000007a12 */
/* 0x000fe400078e3cff */
/*0790*/ ISETP.EQ.OR P0, PT, R23, RZ, !P0 ; /* 0x000000ff1700720c */
/* 0x000fe40004702670 */
/*07a0*/ LOP3.LUT R9, R0, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000000097812 */
/* 0x000fd600078ec0ff */
/*07b0*/ @P0 LOP3.LUT R0, R9, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000009000812 */
/* 0x000fe200078efcff */
/*07c0*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe400078e00ff */
/*07d0*/ @P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff080224 */
/* 0x000fe400078e00ff */
/*07e0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, R0 ; /* 0x000000ffff090224 */
/* 0x000fe200078e0000 */
/*07f0*/ BRA 0x850 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R9, R17, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000011097812 */
/* 0x001fe200078efcff */
/*0810*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x000fe200078e00ff */
/*0820*/ BRA 0x850 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R9, R0, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000000097812 */
/* 0x001fe200078efcff */
/*0840*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff087624 */
/* 0x000fe400078e00ff */
/*0850*/ IMAD.MOV.U32 R17, RZ, RZ, 0x0 ; /* 0x00000000ff117424 */
/* 0x000fe400078e00ff */
/*0860*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fc400078e0008 */
/*0870*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0880*/ RET.REL.NODEC R16 0x0 ; /* 0xfffff77010007950 */
/* 0x000fec0003c3ffff */
/*0890*/ BRA 0x890; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10wave1Dmac1PdS_dddi
.globl _Z10wave1Dmac1PdS_dddi
.p2align 8
.type _Z10wave1Dmac1PdS_dddi,@function
_Z10wave1Dmac1PdS_dddi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s2, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
v_add_nc_u32_e32 v0, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, s2, v0
v_cndmask_b32_e32 v7, 0, v0, vcc_lo
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s6, v0
v_div_scale_f64 v[3:4], null, s[0:1], s[0:1], s[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_clause 0x1
global_load_b64 v[9:10], v[9:10], off
global_load_b64 v[7:8], v[7:8], off
v_div_scale_f64 v[13:14], vcc_lo, s[10:11], s[0:1], s[10:11]
v_rcp_f64_e32 v[5:6], v[3:4]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[3:4], v[5:6], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], v[11:12], v[5:6]
v_fma_f64 v[11:12], -v[3:4], v[5:6], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], v[11:12], v[5:6]
v_mul_f64 v[11:12], v[13:14], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], -v[3:4], v[11:12], v[13:14]
v_div_fmas_f64 v[2:3], v[2:3], v[5:6], v[11:12]
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[7:8], -v[9:10]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[2:3], v[2:3], s[0:1], s[10:11]
v_mul_f64 v[2:3], v[2:3], s[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], -v[2:3], v[4:5], v[9:10]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10wave1Dmac1PdS_dddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10wave1Dmac1PdS_dddi, .Lfunc_end0-_Z10wave1Dmac1PdS_dddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10wave1Dmac1PdS_dddi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10wave1Dmac1PdS_dddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00090652_00000000-6_wave1Dmac1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10wave1Dmac1PdS_dddiPdS_dddi
.type _Z36__device_stub__Z10wave1Dmac1PdS_dddiPdS_dddi, @function
_Z36__device_stub__Z10wave1Dmac1PdS_dddiPdS_dddi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movsd %xmm1, 16(%rsp)
movsd %xmm2, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10wave1Dmac1PdS_dddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z10wave1Dmac1PdS_dddiPdS_dddi, .-_Z36__device_stub__Z10wave1Dmac1PdS_dddiPdS_dddi
.globl _Z10wave1Dmac1PdS_dddi
.type _Z10wave1Dmac1PdS_dddi, @function
_Z10wave1Dmac1PdS_dddi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10wave1Dmac1PdS_dddiPdS_dddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10wave1Dmac1PdS_dddi, .-_Z10wave1Dmac1PdS_dddi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10wave1Dmac1PdS_dddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10wave1Dmac1PdS_dddi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "wave1Dmac1.hip"
.globl _Z25__device_stub__wave1Dmac1PdS_dddi # -- Begin function _Z25__device_stub__wave1Dmac1PdS_dddi
.p2align 4, 0x90
.type _Z25__device_stub__wave1Dmac1PdS_dddi,@function
_Z25__device_stub__wave1Dmac1PdS_dddi: # @_Z25__device_stub__wave1Dmac1PdS_dddi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
movl %edx, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10wave1Dmac1PdS_dddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__wave1Dmac1PdS_dddi, .Lfunc_end0-_Z25__device_stub__wave1Dmac1PdS_dddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10wave1Dmac1PdS_dddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10wave1Dmac1PdS_dddi,@object # @_Z10wave1Dmac1PdS_dddi
.section .rodata,"a",@progbits
.globl _Z10wave1Dmac1PdS_dddi
.p2align 3, 0x0
_Z10wave1Dmac1PdS_dddi:
.quad _Z25__device_stub__wave1Dmac1PdS_dddi
.size _Z10wave1Dmac1PdS_dddi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10wave1Dmac1PdS_dddi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__wave1Dmac1PdS_dddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10wave1Dmac1PdS_dddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
/**
* @brief
*
* @param m
* @param n
* @param A
* @param lda
* @param name
*/
void printMatrix(int m, int n, const float *A, int lda, const char *name) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[row + col * lda];
printf("%s(%d,%d) = %.3f\n", name, row + 1, col + 1, Areg);
}
}
}
/**
* @brief Prints m x n matrix A on host memory.
*/
void print_cpu_matrix(int m, int n, const float *A) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[col + row * n];
printf("(%d,%d)%.3f,", row, col, Areg);
}
printf("\n");
}
}
/**
* @brief Prints m x n matrix A on device memory.
*/
void print_device_matrix(int m, int n, const float *A) {
float *tempmatrix;
tempmatrix = (float *)malloc(sizeof(float) * m * n);
cudaMemcpy(tempmatrix, A, sizeof(float) * m * n, cudaMemcpyDeviceToHost);
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = tempmatrix[col + row * n];
printf("(%d,%d)%.3f,", row, col, Areg);
}
printf("\n");
}
}
/**
* @brief Prints m vector A on device memory.
*/
void print_device_vector(int m, const float *A) {
float *tempmatrix;
tempmatrix = (float *)malloc(sizeof(float) * m);
cudaMemcpy(tempmatrix, A, sizeof(float) * m, cudaMemcpyDeviceToHost);
for (int row = 0; row < m; row++) {
float Areg = tempmatrix[row];
printf("(%d)%.3f,", row, Areg);
}
printf("\n");
}
void printVector(int m, const float *A, const char *name) {
for (int i = 0; i < m; i++) {
float Areg = A[i];
printf("%.6f\n", Areg);
printf("%s(%d) = %.3f\n", name, i, Areg);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
/**
* @brief
*
* @param m
* @param n
* @param A
* @param lda
* @param name
*/
void printMatrix(int m, int n, const float *A, int lda, const char *name) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[row + col * lda];
printf("%s(%d,%d) = %.3f\n", name, row + 1, col + 1, Areg);
}
}
}
/**
* @brief Prints m x n matrix A on host memory.
*/
void print_cpu_matrix(int m, int n, const float *A) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[col + row * n];
printf("(%d,%d)%.3f,", row, col, Areg);
}
printf("\n");
}
}
/**
* @brief Prints m x n matrix A on device memory.
*/
void print_device_matrix(int m, int n, const float *A) {
float *tempmatrix;
tempmatrix = (float *)malloc(sizeof(float) * m * n);
cudaMemcpy(tempmatrix, A, sizeof(float) * m * n, cudaMemcpyDeviceToHost);
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = tempmatrix[col + row * n];
printf("(%d,%d)%.3f,", row, col, Areg);
}
printf("\n");
}
}
/**
* @brief Prints m vector A on device memory.
*/
void print_device_vector(int m, const float *A) {
float *tempmatrix;
tempmatrix = (float *)malloc(sizeof(float) * m);
cudaMemcpy(tempmatrix, A, sizeof(float) * m, cudaMemcpyDeviceToHost);
for (int row = 0; row < m; row++) {
float Areg = tempmatrix[row];
printf("(%d)%.3f,", row, Areg);
}
printf("\n");
}
void printVector(int m, const float *A, const char *name) {
for (int i = 0; i < m; i++) {
float Areg = A[i];
printf("%.6f\n", Areg);
printf("%s(%d) = %.3f\n", name, i, Areg);
}
} | .file "tmpxft_000395f2_00000000-6_debugFunctions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s(%d,%d) = %.3f\n"
.text
.globl _Z11printMatrixiiPKfiPKc
.type _Z11printMatrixiiPKfiPKc, @function
_Z11printMatrixiiPKfiPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, 28(%rsp)
movq %r8, 8(%rsp)
testl %edi, %edi
jle .L3
movl %esi, %r13d
movq %rdx, 16(%rsp)
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r14
movl $1, %r12d
leaq .LC0(%rip), %r15
jmp .L5
.L6:
addl $1, %ebx
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movl %ebx, %r8d
movl %r12d, %ecx
movq 8(%rsp), %rdx
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq %r14, %rbp
cmpl %r13d, %ebx
jne .L6
.L7:
leal 1(%r12), %eax
addq $4, 16(%rsp)
movl 28(%rsp), %edi
cmpl %edi, %r12d
je .L3
movl %eax, %r12d
.L5:
movq 16(%rsp), %rbp
movl $0, %ebx
testl %r13d, %r13d
jg .L6
jmp .L7
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixiiPKfiPKc, .-_Z11printMatrixiiPKfiPKc
.section .rodata.str1.1
.LC1:
.string "(%d,%d)%.3f,"
.LC2:
.string "\n"
.text
.globl _Z16print_cpu_matrixiiPKf
.type _Z16print_cpu_matrixiiPKf, @function
_Z16print_cpu_matrixiiPKf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 8(%rsp)
testl %edi, %edi
jle .L12
movl $0, %r15d
movl $0, %ebp
movslq %esi, %r14
leaq .LC1(%rip), %r13
jmp .L14
.L16:
movslq %r15d, %rax
movq 8(%rsp), %rdx
leaq (%rdx,%rax,4), %r12
movl $0, %ebx
.L15:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movl %ebx, %ecx
movl %ebp, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r14, %rbx
jne .L15
.L17:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl (%rsp), %eax
addl %eax, %r15d
cmpl %ebp, 4(%rsp)
je .L12
.L14:
cmpl $0, (%rsp)
jg .L16
jmp .L17
.L12:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z16print_cpu_matrixiiPKf, .-_Z16print_cpu_matrixiiPKf
.globl _Z19print_device_matrixiiPKf
.type _Z19print_device_matrixiiPKf, @function
_Z19print_device_matrixiiPKf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, %r15d
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, %rbp
movslq %esi, %r13
movslq %edi, %rbx
imulq %r13, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movl $2, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
testl %r15d, %r15d
jle .L20
movl $0, %r15d
movl $0, %ebp
leaq .LC1(%rip), %r14
jmp .L22
.L24:
movslq %r15d, %rax
movq 8(%rsp), %rdx
leaq (%rdx,%rax,4), %r12
movl $0, %ebx
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movl %ebx, %ecx
movl %ebp, %edx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r13
jne .L23
.L25:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl (%rsp), %eax
addl %eax, %r15d
cmpl %ebp, 4(%rsp)
je .L20
.L22:
cmpl $0, (%rsp)
jg .L24
jmp .L25
.L20:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z19print_device_matrixiiPKf, .-_Z19print_device_matrixiiPKf
.section .rodata.str1.1
.LC3:
.string "(%d)%.3f,"
.text
.globl _Z19print_device_vectoriPKf
.type _Z19print_device_vectoriPKf, @function
_Z19print_device_vectoriPKf:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edi, %ebx
movq %rsi, %r13
movslq %edi, %r12
leaq 0(,%r12,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L29
movl $0, %ebx
leaq .LC3(%rip), %r13
.L30:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r12
jne .L30
.L29:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z19print_device_vectoriPKf, .-_Z19print_device_vectoriPKf
.section .rodata.str1.1
.LC4:
.string "%.6f\n"
.LC5:
.string "%s(%d) = %.3f\n"
.text
.globl _Z11printVectoriPKfPKc
.type _Z11printVectoriPKfPKc, @function
_Z11printVectoriPKfPKc:
.LFB2061:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L38
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r12
movq %rdx, %r15
movslq %edi, %rbp
movl $0, %ebx
leaq .LC4(%rip), %r14
leaq .LC5(%rip), %r13
.L35:
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx,4), %xmm1
movapd %xmm1, %xmm0
movsd %xmm1, 8(%rsp)
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
movl %ebx, %ecx
movq %r15, %rdx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L35
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2061:
.size _Z11printVectoriPKfPKc, .-_Z11printVectoriPKfPKc
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
/**
* @brief
*
* @param m
* @param n
* @param A
* @param lda
* @param name
*/
void printMatrix(int m, int n, const float *A, int lda, const char *name) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[row + col * lda];
printf("%s(%d,%d) = %.3f\n", name, row + 1, col + 1, Areg);
}
}
}
/**
* @brief Prints m x n matrix A on host memory.
*/
void print_cpu_matrix(int m, int n, const float *A) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[col + row * n];
printf("(%d,%d)%.3f,", row, col, Areg);
}
printf("\n");
}
}
/**
* @brief Prints m x n matrix A on device memory.
*/
void print_device_matrix(int m, int n, const float *A) {
float *tempmatrix;
tempmatrix = (float *)malloc(sizeof(float) * m * n);
cudaMemcpy(tempmatrix, A, sizeof(float) * m * n, cudaMemcpyDeviceToHost);
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = tempmatrix[col + row * n];
printf("(%d,%d)%.3f,", row, col, Areg);
}
printf("\n");
}
}
/**
* @brief Prints m vector A on device memory.
*/
void print_device_vector(int m, const float *A) {
float *tempmatrix;
tempmatrix = (float *)malloc(sizeof(float) * m);
cudaMemcpy(tempmatrix, A, sizeof(float) * m, cudaMemcpyDeviceToHost);
for (int row = 0; row < m; row++) {
float Areg = tempmatrix[row];
printf("(%d)%.3f,", row, Areg);
}
printf("\n");
}
void printVector(int m, const float *A, const char *name) {
for (int i = 0; i < m; i++) {
float Areg = A[i];
printf("%.6f\n", Areg);
printf("%s(%d) = %.3f\n", name, i, Areg);
}
} | #include <stdio.h>
#include <hip/hip_runtime.h>
/**
* @brief
*
* @param m
* @param n
* @param A
* @param lda
* @param name
*/
void printMatrix(int m, int n, const float *A, int lda, const char *name) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[row + col * lda];
printf("%s(%d,%d) = %.3f\n", name, row + 1, col + 1, Areg);
}
}
}
/**
* @brief Prints m x n matrix A on host memory.
*/
void print_cpu_matrix(int m, int n, const float *A) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[col + row * n];
printf("(%d,%d)%.3f,", row, col, Areg);
}
printf("\n");
}
}
/**
* @brief Prints m x n matrix A on device memory.
*/
void print_device_matrix(int m, int n, const float *A) {
float *tempmatrix;
tempmatrix = (float *)malloc(sizeof(float) * m * n);
hipMemcpy(tempmatrix, A, sizeof(float) * m * n, hipMemcpyDeviceToHost);
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = tempmatrix[col + row * n];
printf("(%d,%d)%.3f,", row, col, Areg);
}
printf("\n");
}
}
/**
* @brief Prints m vector A on device memory.
*/
void print_device_vector(int m, const float *A) {
float *tempmatrix;
tempmatrix = (float *)malloc(sizeof(float) * m);
hipMemcpy(tempmatrix, A, sizeof(float) * m, hipMemcpyDeviceToHost);
for (int row = 0; row < m; row++) {
float Areg = tempmatrix[row];
printf("(%d)%.3f,", row, Areg);
}
printf("\n");
}
void printVector(int m, const float *A, const char *name) {
for (int i = 0; i < m; i++) {
float Areg = A[i];
printf("%.6f\n", Areg);
printf("%s(%d) = %.3f\n", name, i, Areg);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
/**
* @brief
*
* @param m
* @param n
* @param A
* @param lda
* @param name
*/
void printMatrix(int m, int n, const float *A, int lda, const char *name) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[row + col * lda];
printf("%s(%d,%d) = %.3f\n", name, row + 1, col + 1, Areg);
}
}
}
/**
* @brief Prints m x n matrix A on host memory.
*/
void print_cpu_matrix(int m, int n, const float *A) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[col + row * n];
printf("(%d,%d)%.3f,", row, col, Areg);
}
printf("\n");
}
}
/**
* @brief Prints m x n matrix A on device memory.
*/
void print_device_matrix(int m, int n, const float *A) {
float *tempmatrix;
tempmatrix = (float *)malloc(sizeof(float) * m * n);
hipMemcpy(tempmatrix, A, sizeof(float) * m * n, hipMemcpyDeviceToHost);
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = tempmatrix[col + row * n];
printf("(%d,%d)%.3f,", row, col, Areg);
}
printf("\n");
}
}
/**
* @brief Prints m vector A on device memory.
*/
void print_device_vector(int m, const float *A) {
float *tempmatrix;
tempmatrix = (float *)malloc(sizeof(float) * m);
hipMemcpy(tempmatrix, A, sizeof(float) * m, hipMemcpyDeviceToHost);
for (int row = 0; row < m; row++) {
float Areg = tempmatrix[row];
printf("(%d)%.3f,", row, Areg);
}
printf("\n");
}
void printVector(int m, const float *A, const char *name) {
for (int i = 0; i < m; i++) {
float Areg = A[i];
printf("%.6f\n", Areg);
printf("%s(%d) = %.3f\n", name, i, Areg);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
/**
* @brief
*
* @param m
* @param n
* @param A
* @param lda
* @param name
*/
void printMatrix(int m, int n, const float *A, int lda, const char *name) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[row + col * lda];
printf("%s(%d,%d) = %.3f\n", name, row + 1, col + 1, Areg);
}
}
}
/**
* @brief Prints m x n matrix A on host memory.
*/
void print_cpu_matrix(int m, int n, const float *A) {
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = A[col + row * n];
printf("(%d,%d)%.3f,", row, col, Areg);
}
printf("\n");
}
}
/**
* @brief Prints m x n matrix A on device memory.
*/
void print_device_matrix(int m, int n, const float *A) {
float *tempmatrix;
tempmatrix = (float *)malloc(sizeof(float) * m * n);
hipMemcpy(tempmatrix, A, sizeof(float) * m * n, hipMemcpyDeviceToHost);
for (int row = 0; row < m; row++) {
for (int col = 0; col < n; col++) {
float Areg = tempmatrix[col + row * n];
printf("(%d,%d)%.3f,", row, col, Areg);
}
printf("\n");
}
}
/**
* @brief Prints m vector A on device memory.
*/
void print_device_vector(int m, const float *A) {
float *tempmatrix;
tempmatrix = (float *)malloc(sizeof(float) * m);
hipMemcpy(tempmatrix, A, sizeof(float) * m, hipMemcpyDeviceToHost);
for (int row = 0; row < m; row++) {
float Areg = tempmatrix[row];
printf("(%d)%.3f,", row, Areg);
}
printf("\n");
}
void printVector(int m, const float *A, const char *name) {
for (int i = 0; i < m; i++) {
float Areg = A[i];
printf("%.6f\n", Areg);
printf("%s(%d) = %.3f\n", name, i, Areg);
}
} | .text
.file "debugFunctions.hip"
.globl _Z11printMatrixiiPKfiPKc # -- Begin function _Z11printMatrixiiPKfiPKc
.p2align 4, 0x90
.type _Z11printMatrixiiPKfiPKc,@function
_Z11printMatrixiiPKfiPKc: # @_Z11printMatrixiiPKfiPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 24(%rsp) # 8-byte Spill
movl %esi, 12(%rsp) # 4-byte Spill
testl %edi, %edi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movq %r8, %rbx
movslq %ecx, %r13
movl %edi, %eax
movq %rax, 32(%rsp) # 8-byte Spill
movl 12(%rsp), %ebp # 4-byte Reload
shlq $2, %r13
xorl %eax, %eax
movq %rax, 16(%rsp) # 8-byte Spill
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movq 16(%rsp), %rcx # 8-byte Reload
incq %rcx
addq $4, 24(%rsp) # 8-byte Folded Spill
movq %rcx, %rax
movq %rcx, 16(%rsp) # 8-byte Spill
cmpq 32(%rsp), %rcx # 8-byte Folded Reload
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
cmpl $0, 12(%rsp) # 4-byte Folded Reload
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movq 16(%rsp), %rax # 8-byte Reload
leal 1(%rax), %r15d
movq 24(%rsp), %r14 # 8-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
incq %r12
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movq %rbx, %rsi
movl %r15d, %edx
movl %r12d, %ecx
movb $1, %al
callq printf
addq %r13, %r14
cmpq %r12, %rbp
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge16
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11printMatrixiiPKfiPKc, .Lfunc_end0-_Z11printMatrixiiPKfiPKc
.cfi_endproc
# -- End function
.globl _Z16print_cpu_matrixiiPKf # -- Begin function _Z16print_cpu_matrixiiPKf
.p2align 4, 0x90
.type _Z16print_cpu_matrixiiPKf,@function
_Z16print_cpu_matrixiiPKf: # @_Z16print_cpu_matrixiiPKf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 8(%rsp) # 8-byte Spill
testl %edi, %edi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebp
movl %edi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %esi, %r13d
xorl %ebx, %ebx
xorl %r14d, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl %ebp, %ebx
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebp, %ebp
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %ebx, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r14d, %esi
movl %r15d, %edx
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r13
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge16
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z16print_cpu_matrixiiPKf, .Lfunc_end1-_Z16print_cpu_matrixiiPKf
.cfi_endproc
# -- End function
.globl _Z19print_device_matrixiiPKf # -- Begin function _Z19print_device_matrixiiPKf
.p2align 4, 0x90
.type _Z19print_device_matrixiiPKf,@function
_Z19print_device_matrixiiPKf: # @_Z19print_device_matrixiiPKf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r15
movl %esi, %ebx
movl %edi, %ebp
movslq %edi, %r14
movslq %esi, %r12
imulq %r14, %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movq %rax, %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r14d, %r14d
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebx, %ebp
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addl %ebx, %r14d
cmpq 16(%rsp), %r15 # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %ebx, %ebx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r14d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r15d, %esi
movl %r12d, %edx
movb $1, %al
callq printf
incq %r12
cmpq %r12, %rbp
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge22
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z19print_device_matrixiiPKf, .Lfunc_end2-_Z19print_device_matrixiiPKf
.cfi_endproc
# -- End function
.globl _Z19print_device_vectoriPKf # -- Begin function _Z19print_device_vectoriPKf
.p2align 4, 0x90
.type _Z19print_device_vectoriPKf,@function
_Z19print_device_vectoriPKf: # @_Z19print_device_vectoriPKf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebp
movslq %edi, %r12
leaq (,%r12,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r12d, %r12d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB3_2
.LBB3_3: # %._crit_edge
movl $10, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z19print_device_vectoriPKf, .Lfunc_end3-_Z19print_device_vectoriPKf
.cfi_endproc
# -- End function
.globl _Z11printVectoriPKfPKc # -- Begin function _Z11printVectoriPKfPKc
.p2align 4, 0x90
.type _Z11printVectoriPKfPKc,@function
_Z11printVectoriPKfPKc: # @_Z11printVectoriPKfPKc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB4_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movl %edi, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.L.str.5, %edi
movq %rbx, %rsi
movl %r15d, %edx
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB4_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB4_4: # %._crit_edge
retq
.Lfunc_end4:
.size _Z11printVectoriPKfPKc, .Lfunc_end4-_Z11printVectoriPKfPKc
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s(%d,%d) = %.3f\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "(%d,%d)%.3f,"
.size .L.str.1, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "(%d)%.3f,"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%.6f\n"
.size .L.str.4, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s(%d) = %.3f\n"
.size .L.str.5, 15
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000395f2_00000000-6_debugFunctions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s(%d,%d) = %.3f\n"
.text
.globl _Z11printMatrixiiPKfiPKc
.type _Z11printMatrixiiPKfiPKc, @function
_Z11printMatrixiiPKfiPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, 28(%rsp)
movq %r8, 8(%rsp)
testl %edi, %edi
jle .L3
movl %esi, %r13d
movq %rdx, 16(%rsp)
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r14
movl $1, %r12d
leaq .LC0(%rip), %r15
jmp .L5
.L6:
addl $1, %ebx
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movl %ebx, %r8d
movl %r12d, %ecx
movq 8(%rsp), %rdx
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq %r14, %rbp
cmpl %r13d, %ebx
jne .L6
.L7:
leal 1(%r12), %eax
addq $4, 16(%rsp)
movl 28(%rsp), %edi
cmpl %edi, %r12d
je .L3
movl %eax, %r12d
.L5:
movq 16(%rsp), %rbp
movl $0, %ebx
testl %r13d, %r13d
jg .L6
jmp .L7
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixiiPKfiPKc, .-_Z11printMatrixiiPKfiPKc
.section .rodata.str1.1
.LC1:
.string "(%d,%d)%.3f,"
.LC2:
.string "\n"
.text
.globl _Z16print_cpu_matrixiiPKf
.type _Z16print_cpu_matrixiiPKf, @function
_Z16print_cpu_matrixiiPKf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 8(%rsp)
testl %edi, %edi
jle .L12
movl $0, %r15d
movl $0, %ebp
movslq %esi, %r14
leaq .LC1(%rip), %r13
jmp .L14
.L16:
movslq %r15d, %rax
movq 8(%rsp), %rdx
leaq (%rdx,%rax,4), %r12
movl $0, %ebx
.L15:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movl %ebx, %ecx
movl %ebp, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r14, %rbx
jne .L15
.L17:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl (%rsp), %eax
addl %eax, %r15d
cmpl %ebp, 4(%rsp)
je .L12
.L14:
cmpl $0, (%rsp)
jg .L16
jmp .L17
.L12:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z16print_cpu_matrixiiPKf, .-_Z16print_cpu_matrixiiPKf
.globl _Z19print_device_matrixiiPKf
.type _Z19print_device_matrixiiPKf, @function
_Z19print_device_matrixiiPKf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, %r15d
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, %rbp
movslq %esi, %r13
movslq %edi, %rbx
imulq %r13, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movl $2, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
testl %r15d, %r15d
jle .L20
movl $0, %r15d
movl $0, %ebp
leaq .LC1(%rip), %r14
jmp .L22
.L24:
movslq %r15d, %rax
movq 8(%rsp), %rdx
leaq (%rdx,%rax,4), %r12
movl $0, %ebx
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movl %ebx, %ecx
movl %ebp, %edx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r13
jne .L23
.L25:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl (%rsp), %eax
addl %eax, %r15d
cmpl %ebp, 4(%rsp)
je .L20
.L22:
cmpl $0, (%rsp)
jg .L24
jmp .L25
.L20:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z19print_device_matrixiiPKf, .-_Z19print_device_matrixiiPKf
.section .rodata.str1.1
.LC3:
.string "(%d)%.3f,"
.text
.globl _Z19print_device_vectoriPKf
.type _Z19print_device_vectoriPKf, @function
_Z19print_device_vectoriPKf:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edi, %ebx
movq %rsi, %r13
movslq %edi, %r12
leaq 0(,%r12,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L29
movl $0, %ebx
leaq .LC3(%rip), %r13
.L30:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r12
jne .L30
.L29:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z19print_device_vectoriPKf, .-_Z19print_device_vectoriPKf
.section .rodata.str1.1
.LC4:
.string "%.6f\n"
.LC5:
.string "%s(%d) = %.3f\n"
.text
.globl _Z11printVectoriPKfPKc
.type _Z11printVectoriPKfPKc, @function
_Z11printVectoriPKfPKc:
.LFB2061:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L38
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r12
movq %rdx, %r15
movslq %edi, %rbp
movl $0, %ebx
leaq .LC4(%rip), %r14
leaq .LC5(%rip), %r13
.L35:
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx,4), %xmm1
movapd %xmm1, %xmm0
movsd %xmm1, 8(%rsp)
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
movl %ebx, %ecx
movq %r15, %rdx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L35
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2061:
.size _Z11printVectoriPKfPKc, .-_Z11printVectoriPKfPKc
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "debugFunctions.hip"
.globl _Z11printMatrixiiPKfiPKc # -- Begin function _Z11printMatrixiiPKfiPKc
.p2align 4, 0x90
.type _Z11printMatrixiiPKfiPKc,@function
_Z11printMatrixiiPKfiPKc: # @_Z11printMatrixiiPKfiPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 24(%rsp) # 8-byte Spill
movl %esi, 12(%rsp) # 4-byte Spill
testl %edi, %edi
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movq %r8, %rbx
movslq %ecx, %r13
movl %edi, %eax
movq %rax, 32(%rsp) # 8-byte Spill
movl 12(%rsp), %ebp # 4-byte Reload
shlq $2, %r13
xorl %eax, %eax
movq %rax, 16(%rsp) # 8-byte Spill
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movq 16(%rsp), %rcx # 8-byte Reload
incq %rcx
addq $4, 24(%rsp) # 8-byte Folded Spill
movq %rcx, %rax
movq %rcx, 16(%rsp) # 8-byte Spill
cmpq 32(%rsp), %rcx # 8-byte Folded Reload
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
cmpl $0, 12(%rsp) # 4-byte Folded Reload
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movq 16(%rsp), %rax # 8-byte Reload
leal 1(%rax), %r15d
movq 24(%rsp), %r14 # 8-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
incq %r12
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movq %rbx, %rsi
movl %r15d, %edx
movl %r12d, %ecx
movb $1, %al
callq printf
addq %r13, %r14
cmpq %r12, %rbp
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge16
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11printMatrixiiPKfiPKc, .Lfunc_end0-_Z11printMatrixiiPKfiPKc
.cfi_endproc
# -- End function
.globl _Z16print_cpu_matrixiiPKf # -- Begin function _Z16print_cpu_matrixiiPKf
.p2align 4, 0x90
.type _Z16print_cpu_matrixiiPKf,@function
_Z16print_cpu_matrixiiPKf: # @_Z16print_cpu_matrixiiPKf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 8(%rsp) # 8-byte Spill
testl %edi, %edi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebp
movl %edi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %esi, %r13d
xorl %ebx, %ebx
xorl %r14d, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addl %ebp, %ebx
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebp, %ebp
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %ebx, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r14d, %esi
movl %r15d, %edx
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r13
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge16
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z16print_cpu_matrixiiPKf, .Lfunc_end1-_Z16print_cpu_matrixiiPKf
.cfi_endproc
# -- End function
.globl _Z19print_device_matrixiiPKf # -- Begin function _Z19print_device_matrixiiPKf
.p2align 4, 0x90
.type _Z19print_device_matrixiiPKf,@function
_Z19print_device_matrixiiPKf: # @_Z19print_device_matrixiiPKf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r15
movl %esi, %ebx
movl %edi, %ebp
movslq %edi, %r14
movslq %esi, %r12
imulq %r14, %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movq %rax, %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r14d, %r14d
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebx, %ebp
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addl %ebx, %r14d
cmpq 16(%rsp), %r15 # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %ebx, %ebx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r14d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r15d, %esi
movl %r12d, %edx
movb $1, %al
callq printf
incq %r12
cmpq %r12, %rbp
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge22
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z19print_device_matrixiiPKf, .Lfunc_end2-_Z19print_device_matrixiiPKf
.cfi_endproc
# -- End function
.globl _Z19print_device_vectoriPKf # -- Begin function _Z19print_device_vectoriPKf
.p2align 4, 0x90
.type _Z19print_device_vectoriPKf,@function
_Z19print_device_vectoriPKf: # @_Z19print_device_vectoriPKf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebp
movslq %edi, %r12
leaq (,%r12,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r12d, %r12d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movl %r14d, %esi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r15
jne .LBB3_2
.LBB3_3: # %._crit_edge
movl $10, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z19print_device_vectoriPKf, .Lfunc_end3-_Z19print_device_vectoriPKf
.cfi_endproc
# -- End function
.globl _Z11printVectoriPKfPKc # -- Begin function _Z11printVectoriPKfPKc
.p2align 4, 0x90
.type _Z11printVectoriPKfPKc,@function
_Z11printVectoriPKfPKc: # @_Z11printVectoriPKfPKc
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB4_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movl %edi, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.L.str.5, %edi
movq %rbx, %rsi
movl %r15d, %edx
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB4_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB4_4: # %._crit_edge
retq
.Lfunc_end4:
.size _Z11printVectoriPKfPKc, .Lfunc_end4-_Z11printVectoriPKfPKc
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s(%d,%d) = %.3f\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "(%d,%d)%.3f,"
.size .L.str.1, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "(%d)%.3f,"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%.6f\n"
.size .L.str.4, 6
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s(%d) = %.3f\n"
.size .L.str.5, 15
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Checked C extension is not supported for CUDA. Make sure driver
// rejects the flag.
//
// RUN: %clang -fcheckedc-extension -nocudalib -nocudainc -fsyntax-only -c %s 2>&1 | FileCheck %s
// CHECK: warning: Checked C extension not supported with 'CUDA'; ignoring '-fcheckedc-extension'
//
// Have clang compile this file as a C file.
// RUN: %clang -c -fcheckedc-extension -x c -o %t %s
//
// Have clang-cl compile this file as a C file.
// RUN: %clang_cl -c -Xclang -fcheckedc-extension /TC /Fo%t -- %s
void f() {} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Checked C extension is not supported for CUDA. Make sure driver
// rejects the flag.
//
// RUN: %clang -fcheckedc-extension -nocudalib -nocudainc -fsyntax-only -c %s 2>&1 | FileCheck %s
// CHECK: warning: Checked C extension not supported with 'CUDA'; ignoring '-fcheckedc-extension'
//
// Have clang compile this file as a C file.
// RUN: %clang -c -fcheckedc-extension -x c -o %t %s
//
// Have clang-cl compile this file as a C file.
// RUN: %clang_cl -c -Xclang -fcheckedc-extension /TC /Fo%t -- %s
void f() {} | .file "tmpxft_0018a879_00000000-6_checkedc-notsupported-cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1fv
.type _Z1fv, @function
_Z1fv:
.LFB2027:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2027:
.size _Z1fv, .-_Z1fv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Checked C extension is not supported for CUDA. Make sure driver
// rejects the flag.
//
// RUN: %clang -fcheckedc-extension -nocudalib -nocudainc -fsyntax-only -c %s 2>&1 | FileCheck %s
// CHECK: warning: Checked C extension not supported with 'CUDA'; ignoring '-fcheckedc-extension'
//
// Have clang compile this file as a C file.
// RUN: %clang -c -fcheckedc-extension -x c -o %t %s
//
// Have clang-cl compile this file as a C file.
// RUN: %clang_cl -c -Xclang -fcheckedc-extension /TC /Fo%t -- %s
void f() {} | #include <hip/hip_runtime.h>
// Checked C extension is not supported for CUDA. Make sure driver
// rejects the flag.
//
// RUN: %clang -fcheckedc-extension -nocudalib -nocudainc -fsyntax-only -c %s 2>&1 | FileCheck %s
// CHECK: warning: Checked C extension not supported with 'CUDA'; ignoring '-fcheckedc-extension'
//
// Have clang compile this file as a C file.
// RUN: %clang -c -fcheckedc-extension -x c -o %t %s
//
// Have clang-cl compile this file as a C file.
// RUN: %clang_cl -c -Xclang -fcheckedc-extension /TC /Fo%t -- %s
void f() {} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// Checked C extension is not supported for CUDA. Make sure driver
// rejects the flag.
//
// RUN: %clang -fcheckedc-extension -nocudalib -nocudainc -fsyntax-only -c %s 2>&1 | FileCheck %s
// CHECK: warning: Checked C extension not supported with 'CUDA'; ignoring '-fcheckedc-extension'
//
// Have clang compile this file as a C file.
// RUN: %clang -c -fcheckedc-extension -x c -o %t %s
//
// Have clang-cl compile this file as a C file.
// RUN: %clang_cl -c -Xclang -fcheckedc-extension /TC /Fo%t -- %s
void f() {} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// Checked C extension is not supported for CUDA. Make sure driver
// rejects the flag.
//
// RUN: %clang -fcheckedc-extension -nocudalib -nocudainc -fsyntax-only -c %s 2>&1 | FileCheck %s
// CHECK: warning: Checked C extension not supported with 'CUDA'; ignoring '-fcheckedc-extension'
//
// Have clang compile this file as a C file.
// RUN: %clang -c -fcheckedc-extension -x c -o %t %s
//
// Have clang-cl compile this file as a C file.
// RUN: %clang_cl -c -Xclang -fcheckedc-extension /TC /Fo%t -- %s
void f() {} | .text
.file "checkedc-notsupported-cuda.hip"
.globl _Z1fv # -- Begin function _Z1fv
.p2align 4, 0x90
.type _Z1fv,@function
_Z1fv: # @_Z1fv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z1fv, .Lfunc_end0-_Z1fv
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018a879_00000000-6_checkedc-notsupported-cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1fv
.type _Z1fv, @function
_Z1fv:
.LFB2027:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2027:
.size _Z1fv, .-_Z1fv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "checkedc-notsupported-cuda.hip"
.globl _Z1fv # -- Begin function _Z1fv
.p2align 4, 0x90
.type _Z1fv,@function
_Z1fv: # @_Z1fv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z1fv, .Lfunc_end0-_Z1fv
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C" {
}
__global__ void broadcast(const float* x, float* y, unsigned int c, unsigned int len) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < len) {
y[tid] = x[tid % c];
}
} | code for sm_80
Function : _Z9broadcastPKfPfjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ I2F.U32.RP R0, c[0x0][0x170] ; /* 0x00005c0000007b06 */
/* 0x000e220000209000 */
/*0070*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f25070 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fcc0000000a00 */
/*0090*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00a0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00d0*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*00e0*/ IMAD R5, R5, c[0x0][0x170], RZ ; /* 0x00005c0005057a24 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fc800078e0002 */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fca00078e00ff */
/*0120*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fca0007ffe1ff */
/*0130*/ IMAD R3, R3, c[0x0][0x170], R4 ; /* 0x00005c0003037a24 */
/* 0x000fca00078e0204 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06070 */
/*0150*/ @P0 IADD3 R3, R3, -c[0x0][0x170], RZ ; /* 0x80005c0003030a10 */
/* 0x000fc80007ffe0ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06070 */
/*0170*/ @P0 IADD3 R3, R3, -c[0x0][0x170], RZ ; /* 0x80005c0003030a10 */
/* 0x000fe40007ffe0ff */
/*0180*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff039a12 */
/* 0x000fca00078e33ff */
/*0190*/ IMAD.WIDE.U32 R2, R3, R5, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0005 */
/*01a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*01c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C" {
}
__global__ void broadcast(const float* x, float* y, unsigned int c, unsigned int len) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < len) {
y[tid] = x[tid % c];
}
} | .file "tmpxft_00113cc1_00000000-6_broadcast.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9broadcastPKfPfjjPKfPfjj
.type _Z33__device_stub__Z9broadcastPKfPfjjPKfPfjj, @function
_Z33__device_stub__Z9broadcastPKfPfjjPKfPfjj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9broadcastPKfPfjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9broadcastPKfPfjjPKfPfjj, .-_Z33__device_stub__Z9broadcastPKfPfjjPKfPfjj
.globl _Z9broadcastPKfPfjj
.type _Z9broadcastPKfPfjj, @function
_Z9broadcastPKfPfjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9broadcastPKfPfjjPKfPfjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9broadcastPKfPfjj, .-_Z9broadcastPKfPfjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9broadcastPKfPfjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9broadcastPKfPfjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C" {
}
__global__ void broadcast(const float* x, float* y, unsigned int c, unsigned int len) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < len) {
y[tid] = x[tid % c];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
__global__ void broadcast(const float* x, float* y, unsigned int c, unsigned int len) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < len) {
y[tid] = x[tid % c];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
__global__ void broadcast(const float* x, float* y, unsigned int c, unsigned int len) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < len) {
y[tid] = x[tid % c];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9broadcastPKfPfjj
.globl _Z9broadcastPKfPfjj
.p2align 8
.type _Z9broadcastPKfPfjj,@function
_Z9broadcastPKfPfjj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b32 s4, s[0:1], 0x10
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s2, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s2, v0
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s4
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v2, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9broadcastPKfPfjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9broadcastPKfPfjj, .Lfunc_end0-_Z9broadcastPKfPfjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9broadcastPKfPfjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9broadcastPKfPfjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
__global__ void broadcast(const float* x, float* y, unsigned int c, unsigned int len) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < len) {
y[tid] = x[tid % c];
}
} | .text
.file "broadcast.hip"
.globl _Z24__device_stub__broadcastPKfPfjj # -- Begin function _Z24__device_stub__broadcastPKfPfjj
.p2align 4, 0x90
.type _Z24__device_stub__broadcastPKfPfjj,@function
_Z24__device_stub__broadcastPKfPfjj: # @_Z24__device_stub__broadcastPKfPfjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9broadcastPKfPfjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__broadcastPKfPfjj, .Lfunc_end0-_Z24__device_stub__broadcastPKfPfjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9broadcastPKfPfjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9broadcastPKfPfjj,@object # @_Z9broadcastPKfPfjj
.section .rodata,"a",@progbits
.globl _Z9broadcastPKfPfjj
.p2align 3, 0x0
_Z9broadcastPKfPfjj:
.quad _Z24__device_stub__broadcastPKfPfjj
.size _Z9broadcastPKfPfjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9broadcastPKfPfjj"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__broadcastPKfPfjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9broadcastPKfPfjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9broadcastPKfPfjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ I2F.U32.RP R0, c[0x0][0x170] ; /* 0x00005c0000007b06 */
/* 0x000e220000209000 */
/*0070*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f25070 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fcc0000000a00 */
/*0090*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00a0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00d0*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*00e0*/ IMAD R5, R5, c[0x0][0x170], RZ ; /* 0x00005c0005057a24 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fc800078e0002 */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fca00078e00ff */
/*0120*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fca0007ffe1ff */
/*0130*/ IMAD R3, R3, c[0x0][0x170], R4 ; /* 0x00005c0003037a24 */
/* 0x000fca00078e0204 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06070 */
/*0150*/ @P0 IADD3 R3, R3, -c[0x0][0x170], RZ ; /* 0x80005c0003030a10 */
/* 0x000fc80007ffe0ff */
/*0160*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06070 */
/*0170*/ @P0 IADD3 R3, R3, -c[0x0][0x170], RZ ; /* 0x80005c0003030a10 */
/* 0x000fe40007ffe0ff */
/*0180*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff039a12 */
/* 0x000fca00078e33ff */
/*0190*/ IMAD.WIDE.U32 R2, R3, R5, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0005 */
/*01a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*01c0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9broadcastPKfPfjj
.globl _Z9broadcastPKfPfjj
.p2align 8
.type _Z9broadcastPKfPfjj,@function
_Z9broadcastPKfPfjj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b32 s4, s[0:1], 0x10
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s2, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s2, v0
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s4
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v2, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v3, v[2:3], off
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9broadcastPKfPfjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9broadcastPKfPfjj, .Lfunc_end0-_Z9broadcastPKfPfjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9broadcastPKfPfjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9broadcastPKfPfjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00113cc1_00000000-6_broadcast.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9broadcastPKfPfjjPKfPfjj
.type _Z33__device_stub__Z9broadcastPKfPfjjPKfPfjj, @function
_Z33__device_stub__Z9broadcastPKfPfjjPKfPfjj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9broadcastPKfPfjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9broadcastPKfPfjjPKfPfjj, .-_Z33__device_stub__Z9broadcastPKfPfjjPKfPfjj
.globl _Z9broadcastPKfPfjj
.type _Z9broadcastPKfPfjj, @function
_Z9broadcastPKfPfjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9broadcastPKfPfjjPKfPfjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9broadcastPKfPfjj, .-_Z9broadcastPKfPfjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9broadcastPKfPfjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9broadcastPKfPfjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "broadcast.hip"
.globl _Z24__device_stub__broadcastPKfPfjj # -- Begin function _Z24__device_stub__broadcastPKfPfjj
.p2align 4, 0x90
.type _Z24__device_stub__broadcastPKfPfjj,@function
_Z24__device_stub__broadcastPKfPfjj: # @_Z24__device_stub__broadcastPKfPfjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9broadcastPKfPfjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__broadcastPKfPfjj, .Lfunc_end0-_Z24__device_stub__broadcastPKfPfjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9broadcastPKfPfjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9broadcastPKfPfjj,@object # @_Z9broadcastPKfPfjj
.section .rodata,"a",@progbits
.globl _Z9broadcastPKfPfjj
.p2align 3, 0x0
_Z9broadcastPKfPfjj:
.quad _Z24__device_stub__broadcastPKfPfjj
.size _Z9broadcastPKfPfjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9broadcastPKfPfjj"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__broadcastPKfPfjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9broadcastPKfPfjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //This file is take from caffe/crfasrnn
#define modHash(n) ((n)%(2*table_capacity));
namespace caffe {
template<int kd>
__device__ __host__ static unsigned int hash(signed short *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ __host__ static unsigned int has(int *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ static int hashTableInsert(unsigned int fh, signed short *key,
signed short * table_keys,
int* table_entries,
int table_capacity,
unsigned int slot)
{
int h = modHash(fh);
while (1) {
int *e = &table_entries[h];
// if the cell is empty (-1), lock it (-2)
int contents = atomicCAS(e, -1, -2);
if (contents == -2) {
// If it was locked already, move on the next cell
} else if (contents == -1) {
// If it was empty, we successfully locked it, write our key
for (int i = 0; i < kd; i++) {
table_keys[slot*kd+i] = key[i];
}
// Unlock
atomicExch(e, slot);
return h;
} else {
// The cell is unlocked and has a key in it, check if it matches
bool match = true;
for (int i = 0; i < kd && match; i++) {
match = (table_keys[contents*kd+i] == key[i]);
}
if (match) return h;
}
// increment the bucket with wraparound
h++;
if (h == table_capacity*2) h = 0;
}
}
template<int kd>
__device__ static int hashTableInsert(signed short *key,
signed short* table_keys,
int* table_entries,
int table_capacity,
unsigned int slot) {
unsigned int myHash = hash<kd>(key);
return hashTableInsert<kd>(myHash, key, table_keys, table_entries, table_capacity, slot);
}
template<int kd>
__device__ static int hashTableRetrieve(signed short*key,
const int * table_entries,
const signed short* table_keys,
const int table_capacity) {
int h = modHash(hash<kd>(key));
while (1) {
const int *e = table_entries + h;
if (*e == -1) return -1;
bool match = true;
for (int i = 0; i < kd && match; i++) {
match = (table_keys[(*e)*kd+i] == key[i]);
}
if (match) return *e;
h++;
if (h == table_capacity*2) h = 0;
}
}
} //namespace caffe | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //This file is take from caffe/crfasrnn
#define modHash(n) ((n)%(2*table_capacity));
namespace caffe {
template<int kd>
__device__ __host__ static unsigned int hash(signed short *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ __host__ static unsigned int has(int *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ static int hashTableInsert(unsigned int fh, signed short *key,
signed short * table_keys,
int* table_entries,
int table_capacity,
unsigned int slot)
{
int h = modHash(fh);
while (1) {
int *e = &table_entries[h];
// if the cell is empty (-1), lock it (-2)
int contents = atomicCAS(e, -1, -2);
if (contents == -2) {
// If it was locked already, move on the next cell
} else if (contents == -1) {
// If it was empty, we successfully locked it, write our key
for (int i = 0; i < kd; i++) {
table_keys[slot*kd+i] = key[i];
}
// Unlock
atomicExch(e, slot);
return h;
} else {
// The cell is unlocked and has a key in it, check if it matches
bool match = true;
for (int i = 0; i < kd && match; i++) {
match = (table_keys[contents*kd+i] == key[i]);
}
if (match) return h;
}
// increment the bucket with wraparound
h++;
if (h == table_capacity*2) h = 0;
}
}
template<int kd>
__device__ static int hashTableInsert(signed short *key,
signed short* table_keys,
int* table_entries,
int table_capacity,
unsigned int slot) {
unsigned int myHash = hash<kd>(key);
return hashTableInsert<kd>(myHash, key, table_keys, table_entries, table_capacity, slot);
}
template<int kd>
__device__ static int hashTableRetrieve(signed short*key,
const int * table_entries,
const signed short* table_keys,
const int table_capacity) {
int h = modHash(hash<kd>(key));
while (1) {
const int *e = table_entries + h;
if (*e == -1) return -1;
bool match = true;
for (int i = 0; i < kd && match; i++) {
match = (table_keys[(*e)*kd+i] == key[i]);
}
if (match) return *e;
h++;
if (h == table_capacity*2) h = 0;
}
}
} //namespace caffe | .file "tmpxft_00017bc0_00000000-6_hash_helper.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //This file is take from caffe/crfasrnn
#define modHash(n) ((n)%(2*table_capacity));
namespace caffe {
template<int kd>
__device__ __host__ static unsigned int hash(signed short *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ __host__ static unsigned int has(int *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ static int hashTableInsert(unsigned int fh, signed short *key,
signed short * table_keys,
int* table_entries,
int table_capacity,
unsigned int slot)
{
int h = modHash(fh);
while (1) {
int *e = &table_entries[h];
// if the cell is empty (-1), lock it (-2)
int contents = atomicCAS(e, -1, -2);
if (contents == -2) {
// If it was locked already, move on the next cell
} else if (contents == -1) {
// If it was empty, we successfully locked it, write our key
for (int i = 0; i < kd; i++) {
table_keys[slot*kd+i] = key[i];
}
// Unlock
atomicExch(e, slot);
return h;
} else {
// The cell is unlocked and has a key in it, check if it matches
bool match = true;
for (int i = 0; i < kd && match; i++) {
match = (table_keys[contents*kd+i] == key[i]);
}
if (match) return h;
}
// increment the bucket with wraparound
h++;
if (h == table_capacity*2) h = 0;
}
}
template<int kd>
__device__ static int hashTableInsert(signed short *key,
signed short* table_keys,
int* table_entries,
int table_capacity,
unsigned int slot) {
unsigned int myHash = hash<kd>(key);
return hashTableInsert<kd>(myHash, key, table_keys, table_entries, table_capacity, slot);
}
template<int kd>
__device__ static int hashTableRetrieve(signed short*key,
const int * table_entries,
const signed short* table_keys,
const int table_capacity) {
int h = modHash(hash<kd>(key));
while (1) {
const int *e = table_entries + h;
if (*e == -1) return -1;
bool match = true;
for (int i = 0; i < kd && match; i++) {
match = (table_keys[(*e)*kd+i] == key[i]);
}
if (match) return *e;
h++;
if (h == table_capacity*2) h = 0;
}
}
} //namespace caffe | #include <hip/hip_runtime.h>
//This file is take from caffe/crfasrnn
#define modHash(n) ((n)%(2*table_capacity));
namespace caffe {
template<int kd>
__device__ __host__ static unsigned int hash(signed short *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ __host__ static unsigned int has(int *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ static int hashTableInsert(unsigned int fh, signed short *key,
signed short * table_keys,
int* table_entries,
int table_capacity,
unsigned int slot)
{
int h = modHash(fh);
while (1) {
int *e = &table_entries[h];
// if the cell is empty (-1), lock it (-2)
int contents = atomicCAS(e, -1, -2);
if (contents == -2) {
// If it was locked already, move on the next cell
} else if (contents == -1) {
// If it was empty, we successfully locked it, write our key
for (int i = 0; i < kd; i++) {
table_keys[slot*kd+i] = key[i];
}
// Unlock
atomicExch(e, slot);
return h;
} else {
// The cell is unlocked and has a key in it, check if it matches
bool match = true;
for (int i = 0; i < kd && match; i++) {
match = (table_keys[contents*kd+i] == key[i]);
}
if (match) return h;
}
// increment the bucket with wraparound
h++;
if (h == table_capacity*2) h = 0;
}
}
template<int kd>
__device__ static int hashTableInsert(signed short *key,
signed short* table_keys,
int* table_entries,
int table_capacity,
unsigned int slot) {
unsigned int myHash = hash<kd>(key);
return hashTableInsert<kd>(myHash, key, table_keys, table_entries, table_capacity, slot);
}
template<int kd>
__device__ static int hashTableRetrieve(signed short*key,
const int * table_entries,
const signed short* table_keys,
const int table_capacity) {
int h = modHash(hash<kd>(key));
while (1) {
const int *e = table_entries + h;
if (*e == -1) return -1;
bool match = true;
for (int i = 0; i < kd && match; i++) {
match = (table_keys[(*e)*kd+i] == key[i]);
}
if (match) return *e;
h++;
if (h == table_capacity*2) h = 0;
}
}
} //namespace caffe |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//This file is take from caffe/crfasrnn
#define modHash(n) ((n)%(2*table_capacity));
namespace caffe {
template<int kd>
__device__ __host__ static unsigned int hash(signed short *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ __host__ static unsigned int has(int *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ static int hashTableInsert(unsigned int fh, signed short *key,
signed short * table_keys,
int* table_entries,
int table_capacity,
unsigned int slot)
{
int h = modHash(fh);
while (1) {
int *e = &table_entries[h];
// if the cell is empty (-1), lock it (-2)
int contents = atomicCAS(e, -1, -2);
if (contents == -2) {
// If it was locked already, move on the next cell
} else if (contents == -1) {
// If it was empty, we successfully locked it, write our key
for (int i = 0; i < kd; i++) {
table_keys[slot*kd+i] = key[i];
}
// Unlock
atomicExch(e, slot);
return h;
} else {
// The cell is unlocked and has a key in it, check if it matches
bool match = true;
for (int i = 0; i < kd && match; i++) {
match = (table_keys[contents*kd+i] == key[i]);
}
if (match) return h;
}
// increment the bucket with wraparound
h++;
if (h == table_capacity*2) h = 0;
}
}
template<int kd>
__device__ static int hashTableInsert(signed short *key,
signed short* table_keys,
int* table_entries,
int table_capacity,
unsigned int slot) {
unsigned int myHash = hash<kd>(key);
return hashTableInsert<kd>(myHash, key, table_keys, table_entries, table_capacity, slot);
}
template<int kd>
__device__ static int hashTableRetrieve(signed short*key,
const int * table_entries,
const signed short* table_keys,
const int table_capacity) {
int h = modHash(hash<kd>(key));
while (1) {
const int *e = table_entries + h;
if (*e == -1) return -1;
bool match = true;
for (int i = 0; i < kd && match; i++) {
match = (table_keys[(*e)*kd+i] == key[i]);
}
if (match) return *e;
h++;
if (h == table_capacity*2) h = 0;
}
}
} //namespace caffe | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//This file is take from caffe/crfasrnn
#define modHash(n) ((n)%(2*table_capacity));
namespace caffe {
template<int kd>
__device__ __host__ static unsigned int hash(signed short *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ __host__ static unsigned int has(int *key) {
unsigned int k = 0;
for (int i = 0; i < kd; i++) {
k += key[i];
k = k * 1664525;
}
return k;
}
template<int kd>
__device__ static int hashTableInsert(unsigned int fh, signed short *key,
signed short * table_keys,
int* table_entries,
int table_capacity,
unsigned int slot)
{
int h = modHash(fh);
while (1) {
int *e = &table_entries[h];
// if the cell is empty (-1), lock it (-2)
int contents = atomicCAS(e, -1, -2);
if (contents == -2) {
// If it was locked already, move on the next cell
} else if (contents == -1) {
// If it was empty, we successfully locked it, write our key
for (int i = 0; i < kd; i++) {
table_keys[slot*kd+i] = key[i];
}
// Unlock
atomicExch(e, slot);
return h;
} else {
// The cell is unlocked and has a key in it, check if it matches
bool match = true;
for (int i = 0; i < kd && match; i++) {
match = (table_keys[contents*kd+i] == key[i]);
}
if (match) return h;
}
// increment the bucket with wraparound
h++;
if (h == table_capacity*2) h = 0;
}
}
template<int kd>
__device__ static int hashTableInsert(signed short *key,
signed short* table_keys,
int* table_entries,
int table_capacity,
unsigned int slot) {
unsigned int myHash = hash<kd>(key);
return hashTableInsert<kd>(myHash, key, table_keys, table_entries, table_capacity, slot);
}
template<int kd>
__device__ static int hashTableRetrieve(signed short*key,
const int * table_entries,
const signed short* table_keys,
const int table_capacity) {
int h = modHash(hash<kd>(key));
while (1) {
const int *e = table_entries + h;
if (*e == -1) return -1;
bool match = true;
for (int i = 0; i < kd && match; i++) {
match = (table_keys[(*e)*kd+i] == key[i]);
}
if (match) return *e;
h++;
if (h == table_capacity*2) h = 0;
}
}
} //namespace caffe | .text
.file "hash_helper.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00017bc0_00000000-6_hash_helper.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2034:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hash_helper.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void timeFilter(const double *Params, const float *data, const float *W,float *conv_sig){
volatile __shared__ float sW2[81*NrankMax], sW[81*NrankMax], sdata[(Nthreads+81)*NrankMax];
float x;
int tid, tid0, bid, i, nid, Nrank, NT, Nfilt, nt0;
tid = threadIdx.x;
bid = blockIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
nt0 = (int) Params[4];
if(tid<nt0*Nrank)
sW[tid] = W[tid%nt0 + (bid + Nfilt * (tid/nt0))* nt0];
__syncthreads();
tid0 = 0;
while (tid0<NT-Nthreads-nt0+1){
if (tid<nt0*NrankMax)
sdata[tid%nt0 + (tid/nt0)*(Nthreads+nt0)] =
data[tid0 + tid%nt0+ NT*(bid + Nfilt*(tid/nt0))];
#pragma unroll 3
for(nid=0;nid<Nrank;nid++){
sdata[tid + nt0+nid*(Nthreads+nt0)] = data[nt0+tid0 + tid+ NT*(bid +nid*Nfilt)];
}
__syncthreads();
x = 0.0f;
for(nid=0;nid<Nrank;nid++){
#pragma unroll 4
for(i=0;i<nt0;i++)
x += sW[i + nid*nt0] * sdata[i+tid + nid*(Nthreads+nt0)];
}
conv_sig[tid0 + tid + NT*bid] = x;
tid0+=Nthreads;
__syncthreads();
}
} | code for sm_80
Function : _Z10timeFilterPKdPKfS2_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR14, c[0x0][0x118] ; /* 0x00004600000e7ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E.64 R8, [R2.64+0x30] ; /* 0x0000300e02087981 */
/* 0x000ea8000c1e1b00 */
/*0050*/ LDG.E.64 R10, [R2.64+0x20] ; /* 0x0000200e020a7981 */
/* 0x000ee8000c1e1b00 */
/*0060*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000e02047981 */
/* 0x000f28000c1e1b00 */
/*0070*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080e02067981 */
/* 0x000f62000c1e1b00 */
/*0080*/ S2UR UR23, SR_CTAID.X ; /* 0x00000000001779c3 */
/* 0x000e220000002500 */
/*0090*/ BSSY B0, 0x380 ; /* 0x000002e000007945 */
/* 0x000fe40003800000 */
/*00a0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*00b0*/ F2I.F64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x004eb0000030d100 */
/*00c0*/ F2I.F64.TRUNC R10, R10 ; /* 0x0000000a000a7311 */
/* 0x008ef0000030d100 */
/*00d0*/ F2I.F64.TRUNC R4, R4 ; /* 0x0000000400047311 */
/* 0x010f22000030d100 */
/*00e0*/ R2UR UR16, R8 ; /* 0x00000000081073c2 */
/* 0x004eae00000e0000 */
/*00f0*/ F2I.F64.TRUNC R2, R6 ; /* 0x0000000600027311 */
/* 0x020022000030d100 */
/*0100*/ R2UR UR17, R10 ; /* 0x000000000a1173c2 */
/* 0x008eb000000e0000 */
/*0110*/ R2UR UR13, R4 ; /* 0x00000000040d73c2 */
/* 0x010ee200000e0000 */
/*0120*/ UIMAD UR4, UR16, UR17, URZ ; /* 0x00000011100472a4 */
/* 0x004fcc000f8e023f */
/*0130*/ ISETP.GE.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x002fe2000bf26270 */
/*0140*/ UIADD3 UR18, -UR17, -0x400, UR13 ; /* 0xfffffc0011127890 */
/* 0x008fcc000fffe10d */
/*0150*/ ISETP.LE.AND P0, PT, RZ, UR18, PT ; /* 0x00000012ff007c0c */
/* 0x000fcc000bf03270 */
/*0160*/ @P1 BRA 0x370 ; /* 0x0000020000001947 */
/* 0x000fea0003800000 */
/*0170*/ IABS R6, UR17 ; /* 0x0000001100067c13 */
/* 0x001fe40008000000 */
/*0180*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fe40000000000 */
/*0190*/ I2F.RP R3, R6 ; /* 0x0000000600037306 */
/* 0x000e220000209400 */
/*01a0*/ IABS R9, UR17 ; /* 0x0000001100097c13 */
/* 0x000fce0008000000 */
/*01b0*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*01c0*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x001fe20007ffe0ff */
/*01d0*/ IMAD.MOV R3, RZ, RZ, -R9 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0a09 */
/*01e0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe200078e00ff */
/*0200*/ IADD3 R7, RZ, -R5, RZ ; /* 0x80000005ff077210 */
/* 0x002fca0007ffe0ff */
/*0210*/ IMAD R7, R7, R6, RZ ; /* 0x0000000607077224 */
/* 0x000fc800078e02ff */
/*0220*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fcc00078e0004 */
/*0230*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD R3, R5, R3, R8 ; /* 0x0000000305037224 */
/* 0x000fca00078e0208 */
/*0250*/ ISETP.GT.U32.AND P3, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f64070 */
/*0260*/ @!P3 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x000000010303b824 */
/* 0x000fe200078e0a06 */
/*0270*/ @!P3 IADD3 R5, R5, 0x1, RZ ; /* 0x000000010505b810 */
/* 0x000fe40007ffe0ff */
/*0280*/ ISETP.NE.AND P3, PT, RZ, UR17, PT ; /* 0x00000011ff007c0c */
/* 0x000fe4000bf65270 */
/*0290*/ ISETP.GE.U32.AND P1, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe40003f26070 */
/*02a0*/ LOP3.LUT R3, R0, UR17, RZ, 0x3c, !PT ; /* 0x0000001100037c12 */
/* 0x000fc8000f8e3cff */
/*02b0*/ ISETP.GE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f46270 */
/*02c0*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fcc0007ffe0ff */
/*02d0*/ @!P2 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff0505a210 */
/* 0x000fe40007ffe1ff */
/*02e0*/ @!P3 LOP3.LUT R5, RZ, UR17, RZ, 0x33, !PT ; /* 0x00000011ff05bc12 */
/* 0x000fca000f8e33ff */
/*02f0*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a05 */
/*0300*/ IMAD R5, R2, R5, UR23 ; /* 0x0000001702057e24 */
/* 0x000fe4000f8e0205 */
/*0310*/ IMAD R4, R3, UR17, R0 ; /* 0x0000001103047c24 */
/* 0x000fe4000f8e0200 */
/*0320*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0330*/ IMAD R4, R5, UR17, R4 ; /* 0x0000001105047c24 */
/* 0x000fc8000f8e0204 */
/*0340*/ IMAD.WIDE R4, R4, R3, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fcc00078e0203 */
/*0350*/ LDG.E R5, [R4.64] ; /* 0x0000000e04057981 */
/* 0x000ea8000c1e1900 */
/*0360*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x0041e40000004800 */
/*0370*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03a0*/ UIADD3 UR20, UR16, -0x1, URZ ; /* 0xffffffff10147890 */
/* 0x000fe2000fffe03f */
/*03b0*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*03c0*/ IADD3 R4, R0, UR17, RZ ; /* 0x0000001100047c10 */
/* 0x000fe2000fffe0ff */
/*03d0*/ UIMAD UR8, UR17, 0x3, URZ ; /* 0x00000003110878a4 */
/* 0x000fe2000f8e023f */
/*03e0*/ IADD3 R5, R2.reuse, UR23, RZ ; /* 0x0000001702057c10 */
/* 0x040fe2000fffe0ff */
/*03f0*/ UIMAD.WIDE.U32 UR4, UR20, -0x55555555, URZ ; /* 0xaaaaaaab140478a5 */
/* 0x000fe2000f8e003f */
/*0400*/ LEA R7, R2.reuse, UR23, 0x1 ; /* 0x0000001702077c11 */
/* 0x040fe2000f8e08ff */
/*0410*/ IMAD R6, R2, UR13, RZ ; /* 0x0000000d02067c24 */
/* 0x000fe2000f8e02ff */
/*0420*/ UIADD3 UR10, UR17, -0x1, URZ ; /* 0xffffffff110a7890 */
/* 0x000fe2000fffe03f */
/*0430*/ IMAD R5, R5, UR13, R4.reuse ; /* 0x0000000d05057c24 */
/* 0x100fe2000f8e0204 */
/*0440*/ USHF.R.U32.HI UR4, URZ, 0x1, UR5 ; /* 0x000000013f047899 */
/* 0x000fe20008011605 */
/*0450*/ IMAD R6, R6, 0x3, RZ ; /* 0x0000000306067824 */
/* 0x000fe200078e02ff */
/*0460*/ UISETP.GE.AND UP0, UPT, UR17, 0x1, UPT ; /* 0x000000011100788c */
/* 0x000fe2000bf06270 */
/*0470*/ IMAD R7, R7, UR13, R4 ; /* 0x0000000d07077c24 */
/* 0x000fe2000f8e0204 */
/*0480*/ UIMAD UR4, UR4, -0x3, UR20 ; /* 0xfffffffd040478a4 */
/* 0x000fe2000f8e0214 */
/*0490*/ LEA R8, R4, 0x3cc, 0x2 ; /* 0x000003cc04087811 */
/* 0x000fe200078e10ff */
/*04a0*/ ULOP3.LUT UR21, UR17, 0x3, URZ, 0xc0, !UPT ; /* 0x0000000311157892 */
/* 0x000fe2000f8ec03f */
/*04b0*/ ISETP.GE.AND P0, PT, R0, UR8, PT ; /* 0x0000000800007c0c */
/* 0x000fe2000bf06270 */
/*04c0*/ UIADD3 UR6, UR4, 0x1, URZ ; /* 0x0000000104067890 */
/* 0x000fc4000fffe03f */
/*04d0*/ UIADD3 UR19, UR17, 0x400, URZ ; /* 0x0000040011137890 */
/* 0x000fe4000fffe03f */
/*04e0*/ UIMAD.WIDE.U32 UR4, UR6, -0x55555555, URZ ; /* 0xaaaaaaab060478a5 */
/* 0x000fe4000f8e003f */
/*04f0*/ ULEA UR22, UR17, 0x1000, 0x2 ; /* 0x0000100011167891 */
/* 0x000fe2000f8e103f */
/*0500*/ IMAD R16, R3.reuse, UR13, R0 ; /* 0x0000000d03107c24 */
/* 0x041fe2000f8e0200 */
/*0510*/ USHF.R.U32.HI UR4, URZ, 0x1, UR5 ; /* 0x000000013f047899 */
/* 0x000fe20008011605 */
/*0520*/ IMAD R3, R3, UR13, R4 ; /* 0x0000000d03037c24 */
/* 0x000fe2000f8e0204 */
/*0530*/ UISETP.LT.OR UP0, UPT, UR16, 0x1, !UP0 ; /* 0x000000011000788c */
/* 0x000fe4000c701670 */
/*0540*/ UIMAD UR7, UR4, -0x3, UR6 ; /* 0xfffffffd040778a4 */
/* 0x000fc4000f8e0206 */
/*0550*/ UIADD3 UR9, UR17, -UR21, URZ ; /* 0x8000001511097290 */
/* 0x000fe4000fffe03f */
/*0560*/ UISETP.GE.U32.AND UP1, UPT, UR10, 0x3, UPT ; /* 0x000000030a00788c */
/* 0x000fe4000bf26070 */
/*0570*/ UIADD3 UR8, UR16, -UR7, URZ ; /* 0x8000000710087290 */
/* 0x000fe4000fffe03f */
/*0580*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc80008000000 */
/*0590*/ BSSY B0, 0x800 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*05a0*/ @P0 BRA 0x7f0 ; /* 0x0000024000000947 */
/* 0x002fea0003800000 */
/*05b0*/ IABS R9, UR17 ; /* 0x0000001100097c13 */
/* 0x000fe40008000000 */
/*05c0*/ IABS R15, R0 ; /* 0x00000000000f7213 */
/* 0x000fe40000000000 */
/*05d0*/ I2F.RP R12, R9 ; /* 0x00000009000c7306 */
/* 0x000e220000209400 */
/*05e0*/ IABS R17, UR17 ; /* 0x0000001100117c13 */
/* 0x000fce0008000000 */
/*05f0*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x001e240000001000 */
/*0600*/ IADD3 R10, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c0a7810 */
/* 0x001fcc0007ffe0ff */
/*0610*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x000064000021f000 */
/*0620*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e00ff */
/*0630*/ IMAD.MOV R14, RZ, RZ, -R11 ; /* 0x000000ffff0e7224 */
/* 0x002fc800078e0a0b */
/*0640*/ IMAD R13, R14, R9, RZ ; /* 0x000000090e0d7224 */
/* 0x000fe200078e02ff */
/*0650*/ MOV R14, R15 ; /* 0x0000000f000e7202 */
/* 0x000fc60000000f00 */
/*0660*/ IMAD.HI.U32 R13, R11, R13, R10 ; /* 0x0000000d0b0d7227 */
/* 0x000fc800078e000a */
/*0670*/ IMAD.MOV R11, RZ, RZ, -R17 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0a11 */
/*0680*/ IMAD.HI.U32 R13, R13, R14, RZ ; /* 0x0000000e0d0d7227 */
/* 0x000fc800078e00ff */
/*0690*/ IMAD R14, R13, R11, R14 ; /* 0x0000000b0d0e7224 */
/* 0x000fca00078e020e */
/*06a0*/ ISETP.GT.U32.AND P3, PT, R9, R14, PT ; /* 0x0000000e0900720c */
/* 0x000fda0003f64070 */
/*06b0*/ @!P3 IMAD.IADD R14, R14, 0x1, -R9 ; /* 0x000000010e0eb824 */
/* 0x000fe200078e0a09 */
/*06c0*/ @!P3 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0db810 */
/* 0x000fe40007ffe0ff */
/*06d0*/ ISETP.NE.AND P3, PT, RZ, UR17, PT ; /* 0x00000011ff007c0c */
/* 0x000fe4000bf65270 */
/*06e0*/ ISETP.GE.U32.AND P2, PT, R14, R9, PT ; /* 0x000000090e00720c */
/* 0x000fe40003f46070 */
/*06f0*/ LOP3.LUT R9, R0, UR17, RZ, 0x3c, !PT ; /* 0x0000001100097c12 */
/* 0x000fc8000f8e3cff */
/*0700*/ ISETP.GE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fce0003f26270 */
/*0710*/ @P2 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d2810 */
/* 0x000fc80007ffe0ff */
/*0720*/ MOV R9, R13 ; /* 0x0000000d00097202 */
/* 0x000fe20000000f00 */
/*0730*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*0740*/ @!P1 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff099224 */
/* 0x000fe200078e0a09 */
/*0750*/ @!P3 LOP3.LUT R9, RZ, UR17, RZ, 0x33, !PT ; /* 0x00000011ff09bc12 */
/* 0x000fca000f8e33ff */
/*0760*/ IMAD.MOV R11, RZ, RZ, -R9 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0a09 */
/*0770*/ IMAD R12, R11, UR17, R0 ; /* 0x000000110b0c7c24 */
/* 0x000fe4000f8e0200 */
/*0780*/ IMAD R11, R2, R9, UR23 ; /* 0x00000017020b7e24 */
/* 0x000fc6000f8e0209 */
/*0790*/ IADD3 R10, R12, UR4, RZ ; /* 0x000000040c0a7c10 */
/* 0x000fca000fffe0ff */
/*07a0*/ IMAD R10, R11, UR13, R10 ; /* 0x0000000d0b0a7c24 */
/* 0x000fc8000f8e020a */
/*07b0*/ IMAD.WIDE R10, R10, R13, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fcc00078e020d */
/*07c0*/ LDG.E R10, [R10.64] ; /* 0x0000000e0a0a7981 */
/* 0x000ea2000c1e1900 */
/*07d0*/ IMAD R9, R9, UR19, R12 ; /* 0x0000001309097c24 */
/* 0x000fca000f8e020c */
/*07e0*/ STS [R9.X4+0x3cc], R10 ; /* 0x0003cc0a09007388 */
/* 0x0041e40000004800 */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0800*/ UISETP.GE.AND UP2, UPT, UR16, 0x1, UPT ; /* 0x000000011000788c */
/* 0x000fcc000bf46270 */
/*0810*/ PLOP3.LUT P1, PT, PT, PT, UP2, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f2f028 */
/*0820*/ @!P1 BRA 0xb50 ; /* 0x0000032000009947 */
/* 0x000fea0003800000 */
/*0830*/ UISETP.GE.U32.AND UP2, UPT, UR20, 0x2, UPT ; /* 0x000000021400788c */
/* 0x000fe2000bf46070 */
/*0840*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x001fe200000001ff */
/*0850*/ ISETP.NE.AND P2, PT, RZ, UR7, PT ; /* 0x00000007ff007c0c */
/* 0x000fc8000bf45270 */
/*0860*/ PLOP3.LUT P1, PT, PT, PT, UP2, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f2f028 */
/*0870*/ @!P1 BRA 0xa20 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*0880*/ IADD3 R10, R3, UR4, RZ ; /* 0x00000004030a7c10 */
/* 0x000fe2000fffe0ff */
/*0890*/ IMAD.MOV.U32 R24, RZ, RZ, 0x4 ; /* 0x00000004ff187424 */
/* 0x000fe200078e00ff */
/*08a0*/ IADD3 R17, R5, UR4, RZ ; /* 0x0000000405117c10 */
/* 0x000fe2000fffe0ff */
/*08b0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*08c0*/ IADD3 R19, R7, UR4, RZ ; /* 0x0000000407137c10 */
/* 0x000fe2000fffe0ff */
/*08d0*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0008 */
/*08e0*/ UMOV UR5, UR8 ; /* 0x0000000800057c82 */
/* 0x000fe20008000000 */
/*08f0*/ IMAD.WIDE R10, R10, R24, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fc800078e0218 */
/*0900*/ IMAD.WIDE R12, R17, R24.reuse, c[0x0][0x168] ; /* 0x00005a00110c7625 */
/* 0x080fe200078e0218 */
/*0910*/ LDG.E R21, [R10.64] ; /* 0x0000000e0a157981 */
/* 0x0000a6000c1e1900 */
/*0920*/ IMAD.WIDE R14, R19, R24, c[0x0][0x168] ; /* 0x00005a00130e7625 */
/* 0x002fc400078e0218 */
/*0930*/ LDG.E R13, [R12.64] ; /* 0x0000000e0c0d7981 */
/* 0x000ee8000c1e1900 */
/*0940*/ LDG.E R15, [R14.64] ; /* 0x0000000e0e0f7981 */
/* 0x000f22000c1e1900 */
/*0950*/ IADD3 R20, R18, UR22, RZ ; /* 0x0000001612147c10 */
/* 0x000fe2000fffe0ff */
/*0960*/ UIADD3 UR5, UR5, -0x3, URZ ; /* 0xfffffffd05057890 */
/* 0x000fcc000fffe03f */
/*0970*/ ISETP.NE.AND P1, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fe4000bf25270 */
/*0980*/ IADD3 R22, R20, UR22, RZ ; /* 0x0000001614167c10 */
/* 0x000fe2000fffe0ff */
/*0990*/ IMAD.IADD R19, R6.reuse, 0x1, R19 ; /* 0x0000000106137824 */
/* 0x040fe200078e0213 */
/*09a0*/ IADD3 R9, R9, 0x3, RZ ; /* 0x0000000309097810 */
/* 0x000fe20007ffe0ff */
/*09b0*/ IMAD.WIDE R10, R6.reuse, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x041fe200078e020a */
/*09c0*/ IADD3 R17, R6, R17, RZ ; /* 0x0000001106117210 */
/* 0x000fe20007ffe0ff */
/*09d0*/ STS [R18], R21 ; /* 0x0000001512007388 */
/* 0x004fe80000000800 */
/*09e0*/ STS [R18+UR22], R13 ; /* 0x0000000d12007988 */
/* 0x0081e80008000816 */
/*09f0*/ STS [R20+UR22], R15 ; /* 0x0000000f14007988 */
/* 0x0103e20008000816 */
/*0a00*/ IADD3 R18, R22, UR22, RZ ; /* 0x0000001616127c10 */
/* 0x001fe2000fffe0ff */
/*0a10*/ @P1 BRA 0x900 ; /* 0xfffffee000001947 */
/* 0x000fea000383ffff */
/*0a20*/ IADD3 R12, R4, UR4, RZ ; /* 0x00000004040c7c10 */
/* 0x000fe2000fffe0ff */
/*0a30*/ @!P2 BRA 0xb50 ; /* 0x000001100000a947 */
/* 0x000fea0003800000 */
/*0a40*/ IMAD.U32 R10, RZ, RZ, UR7 ; /* 0x00000007ff0a7e24 */
/* 0x000fe4000f8e00ff */
/*0a50*/ IMAD R13, R2, R9, UR23 ; /* 0x00000017020d7e24 */
/* 0x000fc4000f8e0209 */
/*0a60*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x002fe200078e00ff */
/*0a70*/ ISETP.NE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f25270 */
/*0a80*/ IMAD R10, R13, UR13, R12 ; /* 0x0000000d0d0a7c24 */
/* 0x000fd8000f8e020c */
/*0a90*/ @P1 IADD3 R11, R2, R13, RZ ; /* 0x0000000d020b1210 */
/* 0x000fca0007ffe0ff */
/*0aa0*/ @P1 IMAD R12, R11, UR13, R12 ; /* 0x0000000d0b0c1c24 */
/* 0x000fe4000f8e020c */
/*0ab0*/ IMAD.WIDE R10, R10, R15, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fc800078e020f */
/*0ac0*/ @P1 IMAD.WIDE R12, R12, R15, c[0x0][0x168] ; /* 0x00005a000c0c1625 */
/* 0x000fe400078e020f */
/*0ad0*/ LDG.E R10, [R10.64] ; /* 0x0000000e0a0a7981 */
/* 0x000ea8000c1e1900 */
/*0ae0*/ @P1 LDG.E R12, [R12.64] ; /* 0x0000000e0c0c1981 */
/* 0x000ee2000c1e1900 */
/*0af0*/ IMAD R9, R9, UR19, R4 ; /* 0x0000001309097c24 */
/* 0x000fe4000f8e0204 */
/*0b00*/ IMAD.U32 R14, RZ, RZ, UR17 ; /* 0x00000011ff0e7e24 */
/* 0x000fc6000f8e00ff */
/*0b10*/ LEA R15, R9, 0x3cc, 0x2 ; /* 0x000003cc090f7811 */
/* 0x000fc800078e10ff */
/*0b20*/ @P1 LEA R15, R14, R15, 0x2 ; /* 0x0000000f0e0f1211 */
/* 0x000fe200078e10ff */
/*0b30*/ STS [R9.X4+0x3cc], R10 ; /* 0x0003cc0a09007388 */
/* 0x0041e80000004800 */
/*0b40*/ @P1 STS [R15+0x1000], R12 ; /* 0x0010000c0f001388 */
/* 0x0081e40000000800 */
/*0b50*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0b60*/ PLOP3.LUT P1, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f2f008 */
/*0b70*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x001fd800078e00ff */
/*0b80*/ @P1 BRA 0xee0 ; /* 0x0000035000001947 */
/* 0x000fea0003800000 */
/*0b90*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0ba0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*0bb0*/ PLOP3.LUT P1, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f2f018 */
/*0bc0*/ UIMAD UR12, UR17, UR5, URZ ; /* 0x00000005110c72a4 */
/* 0x000fe2000f8e023f */
/*0bd0*/ ISETP.NE.AND P2, PT, RZ, UR21, PT ; /* 0x00000015ff007c0c */
/* 0x000fe2000bf45270 */
/*0be0*/ UMOV UR6, URZ ; /* 0x0000003f00067c82 */
/* 0x000fe40008000000 */
/*0bf0*/ ULEA UR10, UR5, UR12, 0xa ; /* 0x0000000c050a7291 */
/* 0x000fe4000f8e503f */
/*0c00*/ UIADD3 UR5, UR5, 0x1, URZ ; /* 0x0000000105057890 */
/* 0x000fc8000fffe03f */
/*0c10*/ UISETP.GE.AND UP3, UPT, UR5, UR16, UPT ; /* 0x000000100500728c */
/* 0x000fe2000bf66270 */
/*0c20*/ IADD3 R19, R0, UR10, RZ ; /* 0x0000000a00137c10 */
/* 0x000fe2000fffe0ff */
/*0c30*/ @!P1 BRA 0xd90 ; /* 0x0000015000009947 */
/* 0x002fea0003800000 */
/*0c40*/ UMOV UR6, URZ ; /* 0x0000003f00067c82 */
/* 0x000fe40008000000 */
/*0c50*/ UMOV UR10, UR9 ; /* 0x00000009000a7c82 */
/* 0x000fc60008000000 */
/*0c60*/ UIADD3 UR11, UR12, UR6, URZ ; /* 0x000000060c0b7290 */
/* 0x000fe2000fffe03f */
/*0c70*/ IADD3 R10, R19, UR6, RZ ; /* 0x00000006130a7c10 */
/* 0x000fe2000fffe0ff */
/*0c80*/ UIADD3 UR10, UR10, -0x4, URZ ; /* 0xfffffffc0a0a7890 */
/* 0x000fe4000fffe03f */
/*0c90*/ USHF.L.U32 UR11, UR11, 0x2, URZ ; /* 0x000000020b0b7899 */
/* 0x000fe4000800063f */
/*0ca0*/ LDS R12, [R10.X4+0x3cc] ; /* 0x0003cc000a0c7984 */
/* 0x000fe20000004800 */
/*0cb0*/ UIADD3 UR6, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000fffe03f */
/*0cc0*/ ISETP.NE.AND P1, PT, RZ, UR10, PT ; /* 0x0000000aff007c0c */
/* 0x000fca000bf25270 */
/*0cd0*/ LDS R11, [UR11] ; /* 0x0000000bff0b7984 */
/* 0x000e280008000800 */
/*0ce0*/ LDS R14, [R10.X4+0x3d0] ; /* 0x0003d0000a0e7984 */
/* 0x000fe80000004800 */
/*0cf0*/ LDS R13, [UR11+0x4] ; /* 0x0000040bff0d7984 */
/* 0x000ea80008000800 */
/*0d00*/ LDS R18, [R10.X4+0x3d4] ; /* 0x0003d4000a127984 */
/* 0x000fe80000004800 */
/*0d10*/ LDS R15, [UR11+0x8] ; /* 0x0000080bff0f7984 */
/* 0x002e680008000800 */
/*0d20*/ LDS R20, [R10.X4+0x3d8] ; /* 0x0003d8000a147984 */
/* 0x000fe80000004800 */
/*0d30*/ LDS R17, [UR11+0xc] ; /* 0x00000c0bff117984 */
/* 0x000ee20008000800 */
/*0d40*/ FFMA R11, R12, R11, R9 ; /* 0x0000000b0c0b7223 */
/* 0x001fc80000000009 */
/*0d50*/ FFMA R11, R14, R13, R11 ; /* 0x0000000d0e0b7223 */
/* 0x004fc8000000000b */
/*0d60*/ FFMA R11, R18, R15, R11 ; /* 0x0000000f120b7223 */
/* 0x002fc8000000000b */
/*0d70*/ FFMA R9, R20, R17, R11 ; /* 0x0000001114097223 */
/* 0x008fe2000000000b */
/*0d80*/ @P1 BRA 0xc60 ; /* 0xfffffed000001947 */
/* 0x000fea000383ffff */
/*0d90*/ @!P2 BRA 0xec0 ; /* 0x000001200000a947 */
/* 0x000fea0003800000 */
/*0da0*/ UIADD3 UR10, UR12, UR6, URZ ; /* 0x000000060c0a7290 */
/* 0x000fe2000fffe03f */
/*0db0*/ IADD3 R10, R19, UR6, RZ ; /* 0x00000006130a7c10 */
/* 0x000fe2000fffe0ff */
/*0dc0*/ UISETP.NE.AND UP2, UPT, UR21, 0x1, UPT ; /* 0x000000011500788c */
/* 0x000fe4000bf45270 */
/*0dd0*/ USHF.L.U32 UR10, UR10, 0x2, URZ ; /* 0x000000020a0a7899 */
/* 0x000fe2000800063f */
/*0de0*/ LEA R14, R10, 0x3cc, 0x2 ; /* 0x000003cc0a0e7811 */
/* 0x000fe200078e10ff */
/*0df0*/ LDS R12, [R10.X4+0x3cc] ; /* 0x0003cc000a0c7984 */
/* 0x000fe40000004800 */
/*0e00*/ PLOP3.LUT P1, PT, PT, PT, UP2, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fca0003f2f028 */
/*0e10*/ LDS R11, [UR10] ; /* 0x0000000aff0b7984 */
/* 0x000e240008000800 */
/*0e20*/ FFMA R9, R12, R11, R9 ; /* 0x0000000b0c097223 */
/* 0x001fcc0000000009 */
/*0e30*/ @!P1 BRA 0xec0 ; /* 0x0000008000009947 */
/* 0x000fea0003800000 */
/*0e40*/ MOV R10, UR21 ; /* 0x00000015000a7c02 */
/* 0x000fc80008000f00 */
/*0e50*/ ISETP.NE.AND P1, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x000fe40003f25270 */
/*0e60*/ LDS R10, [R14+0x4] ; /* 0x000004000e0a7984 */
/* 0x000fe80000000800 */
/*0e70*/ LDS R11, [UR10+0x4] ; /* 0x0000040aff0b7984 */
/* 0x000e2e0008000800 */
/*0e80*/ @P1 LDS R12, [R14+0x8] ; /* 0x000008000e0c1984 */
/* 0x000fe80000000800 */
/*0e90*/ @P1 LDS R13, [UR10+0x8] ; /* 0x0000080aff0d1984 */
/* 0x000ea20008000800 */
/*0ea0*/ FFMA R9, R10, R11, R9 ; /* 0x0000000b0a097223 */
/* 0x001fc80000000009 */
/*0eb0*/ @P1 FFMA R9, R12, R13, R9 ; /* 0x0000000d0c091223 */
/* 0x004fe40000000009 */
/*0ec0*/ PLOP3.LUT P1, PT, PT, PT, UP3, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f2f038 */
/*0ed0*/ @!P1 BRA 0xbb0 ; /* 0xfffffcd000009947 */
/* 0x000fea000383ffff */
/*0ee0*/ IADD3 R10, R16, UR4, RZ ; /* 0x00000004100a7c10 */
/* 0x000fe2000fffe0ff */
/*0ef0*/ UIADD3 UR4, UR4, 0x400, URZ ; /* 0x0000040004047890 */
/* 0x000fe2000fffe03f */
/*0f00*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc600078e00ff */
/*0f10*/ UISETP.GT.AND UP2, UPT, UR4, UR18, UPT ; /* 0x000000120400728c */
/* 0x000fe2000bf44270 */
/*0f20*/ IMAD.WIDE R10, R10, R11, c[0x0][0x178] ; /* 0x00005e000a0a7625 */
/* 0x000fca00078e020b */
/*0f30*/ PLOP3.LUT P1, PT, PT, PT, UP2, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f2f028 */
/*0f40*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x0001e8000c10190e */
/*0f50*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0f60*/ @!P1 BRA 0x590 ; /* 0xfffff62000009947 */
/* 0x001fea000383ffff */
/*0f70*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f80*/ BRA 0xf80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void timeFilter(const double *Params, const float *data, const float *W,float *conv_sig){
volatile __shared__ float sW2[81*NrankMax], sW[81*NrankMax], sdata[(Nthreads+81)*NrankMax];
float x;
int tid, tid0, bid, i, nid, Nrank, NT, Nfilt, nt0;
tid = threadIdx.x;
bid = blockIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
nt0 = (int) Params[4];
if(tid<nt0*Nrank)
sW[tid] = W[tid%nt0 + (bid + Nfilt * (tid/nt0))* nt0];
__syncthreads();
tid0 = 0;
while (tid0<NT-Nthreads-nt0+1){
if (tid<nt0*NrankMax)
sdata[tid%nt0 + (tid/nt0)*(Nthreads+nt0)] =
data[tid0 + tid%nt0+ NT*(bid + Nfilt*(tid/nt0))];
#pragma unroll 3
for(nid=0;nid<Nrank;nid++){
sdata[tid + nt0+nid*(Nthreads+nt0)] = data[nt0+tid0 + tid+ NT*(bid +nid*Nfilt)];
}
__syncthreads();
x = 0.0f;
for(nid=0;nid<Nrank;nid++){
#pragma unroll 4
for(i=0;i<nt0;i++)
x += sW[i + nid*nt0] * sdata[i+tid + nid*(Nthreads+nt0)];
}
conv_sig[tid0 + tid + NT*bid] = x;
tid0+=Nthreads;
__syncthreads();
}
} | .file "tmpxft_00158dba_00000000-6_timeFilter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z10timeFilterPKdPKfS2_PfPKdPKfS2_Pf
.type _Z39__device_stub__Z10timeFilterPKdPKfS2_PfPKdPKfS2_Pf, @function
_Z39__device_stub__Z10timeFilterPKdPKfS2_PfPKdPKfS2_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10timeFilterPKdPKfS2_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z10timeFilterPKdPKfS2_PfPKdPKfS2_Pf, .-_Z39__device_stub__Z10timeFilterPKdPKfS2_PfPKdPKfS2_Pf
.globl _Z10timeFilterPKdPKfS2_Pf
.type _Z10timeFilterPKdPKfS2_Pf, @function
_Z10timeFilterPKdPKfS2_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z10timeFilterPKdPKfS2_PfPKdPKfS2_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10timeFilterPKdPKfS2_Pf, .-_Z10timeFilterPKdPKfS2_Pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10timeFilterPKdPKfS2_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10timeFilterPKdPKfS2_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void timeFilter(const double *Params, const float *data, const float *W,float *conv_sig){
volatile __shared__ float sW2[81*NrankMax], sW[81*NrankMax], sdata[(Nthreads+81)*NrankMax];
float x;
int tid, tid0, bid, i, nid, Nrank, NT, Nfilt, nt0;
tid = threadIdx.x;
bid = blockIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
nt0 = (int) Params[4];
if(tid<nt0*Nrank)
sW[tid] = W[tid%nt0 + (bid + Nfilt * (tid/nt0))* nt0];
__syncthreads();
tid0 = 0;
while (tid0<NT-Nthreads-nt0+1){
if (tid<nt0*NrankMax)
sdata[tid%nt0 + (tid/nt0)*(Nthreads+nt0)] =
data[tid0 + tid%nt0+ NT*(bid + Nfilt*(tid/nt0))];
#pragma unroll 3
for(nid=0;nid<Nrank;nid++){
sdata[tid + nt0+nid*(Nthreads+nt0)] = data[nt0+tid0 + tid+ NT*(bid +nid*Nfilt)];
}
__syncthreads();
x = 0.0f;
for(nid=0;nid<Nrank;nid++){
#pragma unroll 4
for(i=0;i<nt0;i++)
x += sW[i + nid*nt0] * sdata[i+tid + nid*(Nthreads+nt0)];
}
conv_sig[tid0 + tid + NT*bid] = x;
tid0+=Nthreads;
__syncthreads();
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void timeFilter(const double *Params, const float *data, const float *W,float *conv_sig){
volatile __shared__ float sW2[81*NrankMax], sW[81*NrankMax], sdata[(Nthreads+81)*NrankMax];
float x;
int tid, tid0, bid, i, nid, Nrank, NT, Nfilt, nt0;
tid = threadIdx.x;
bid = blockIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
nt0 = (int) Params[4];
if(tid<nt0*Nrank)
sW[tid] = W[tid%nt0 + (bid + Nfilt * (tid/nt0))* nt0];
__syncthreads();
tid0 = 0;
while (tid0<NT-Nthreads-nt0+1){
if (tid<nt0*NrankMax)
sdata[tid%nt0 + (tid/nt0)*(Nthreads+nt0)] =
data[tid0 + tid%nt0+ NT*(bid + Nfilt*(tid/nt0))];
#pragma unroll 3
for(nid=0;nid<Nrank;nid++){
sdata[tid + nt0+nid*(Nthreads+nt0)] = data[nt0+tid0 + tid+ NT*(bid +nid*Nfilt)];
}
__syncthreads();
x = 0.0f;
for(nid=0;nid<Nrank;nid++){
#pragma unroll 4
for(i=0;i<nt0;i++)
x += sW[i + nid*nt0] * sdata[i+tid + nid*(Nthreads+nt0)];
}
conv_sig[tid0 + tid + NT*bid] = x;
tid0+=Nthreads;
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void timeFilter(const double *Params, const float *data, const float *W,float *conv_sig){
volatile __shared__ float sW2[81*NrankMax], sW[81*NrankMax], sdata[(Nthreads+81)*NrankMax];
float x;
int tid, tid0, bid, i, nid, Nrank, NT, Nfilt, nt0;
tid = threadIdx.x;
bid = blockIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
nt0 = (int) Params[4];
if(tid<nt0*Nrank)
sW[tid] = W[tid%nt0 + (bid + Nfilt * (tid/nt0))* nt0];
__syncthreads();
tid0 = 0;
while (tid0<NT-Nthreads-nt0+1){
if (tid<nt0*NrankMax)
sdata[tid%nt0 + (tid/nt0)*(Nthreads+nt0)] =
data[tid0 + tid%nt0+ NT*(bid + Nfilt*(tid/nt0))];
#pragma unroll 3
for(nid=0;nid<Nrank;nid++){
sdata[tid + nt0+nid*(Nthreads+nt0)] = data[nt0+tid0 + tid+ NT*(bid +nid*Nfilt)];
}
__syncthreads();
x = 0.0f;
for(nid=0;nid<Nrank;nid++){
#pragma unroll 4
for(i=0;i<nt0;i++)
x += sW[i + nid*nt0] * sdata[i+tid + nid*(Nthreads+nt0)];
}
conv_sig[tid0 + tid + NT*bid] = x;
tid0+=Nthreads;
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10timeFilterPKdPKfS2_Pf
.globl _Z10timeFilterPKdPKfS2_Pf
.p2align 8
.type _Z10timeFilterPKdPKfS2_Pf,@function
_Z10timeFilterPKdPKfS2_Pf:
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s8, s15
s_waitcnt lgkmcnt(0)
s_clause 0x2
s_load_b64 s[10:11], s[2:3], 0x30
s_load_b64 s[12:13], s[2:3], 0x20
s_load_b128 s[4:7], s[2:3], 0x0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cvt_i32_f64_e32 v1, s[10:11]
v_cvt_i32_f64_e32 v2, s[12:13]
v_cvt_i32_f64_e32 v3, s[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s9, v1
v_readfirstlane_b32 s11, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s10, v3
v_mul_lo_u32 v1, s9, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v0, v1
s_cbranch_execz .LBB0_2
s_ashr_i32 s3, s11, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s11, s3
s_xor_b32 s6, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s7, 0, s6
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_mul_lo_u32 v2, v1, s6
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
v_subrev_nc_u32_e32 v4, s6, v2
v_cmp_le_u32_e32 vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v1, v3
v_subrev_nc_u32_e32 v1, s6, v2
v_cmp_le_u32_e32 vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v3
s_load_b64 s[6:7], s[0:1], 0x10
v_dual_cndmask_b32 v1, v2, v1 :: v_dual_cndmask_b32 v2, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, s3, v2
v_subrev_nc_u32_e32 v4, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v4, s10, s[8:9]
v_mad_u64_u32 v[3:4], null, v2, s11, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_mov_b64 s[6:7], src_shared_base
global_load_b32 v3, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0x33d0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v1
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0, s7, vcc_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_cvt_i32_f64_e32 v1, s[4:5]
s_mov_b32 s14, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_readfirstlane_b32 s12, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s13, s12, s11
s_addk_i32 s13, 0xfc00
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s13, 0
s_cbranch_scc1 .LBB0_25
s_add_i32 s15, s11, 0x400
s_cmp_gt_i32 s9, 0
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b64 s[6:7], s[0:1], 0x18
s_cselect_b32 s16, -1, 0
s_cmp_gt_i32 s11, 0
v_add_nc_u32_e32 v4, s11, v0
s_cselect_b32 s17, -1, 0
s_add_i32 s2, s9, -1
v_lshlrev_b32_e32 v6, 2, v0
s_mul_hi_u32 s3, s2, 0xaaaaaaab
v_mov_b32_e32 v1, v4
s_lshr_b32 s3, s3, 1
s_mul_i32 s0, s11, 3
s_mul_i32 s3, s3, 3
s_mul_i32 s24, s11, 12
s_sub_i32 s2, s2, s3
v_cmp_gt_i32_e64 s0, s0, v0
s_add_i32 s2, s2, 1
v_add3_u32 v8, s24, v6, 0x2000
s_cmp_lg_u32 s2, 3
v_lshlrev_b32_e32 v10, 2, v4
s_cselect_b32 s1, -1, 0
s_mul_i32 s25, s10, s12
v_cndmask_b32_e64 v5, 0, 1, s1
s_and_b32 s1, s1, exec_lo
s_cselect_b32 s18, s2, 0
s_cmp_gt_u32 s9, 2
s_mul_i32 s1, s8, s12
s_cselect_b32 s19, -1, 0
s_sub_i32 s20, s9, s18
s_and_b32 s2, s11, 3
s_cmp_gt_u32 s11, 3
v_add_nc_u32_e32 v7, s1, v0
s_cselect_b32 s21, -1, 0
s_and_b32 s22, s11, 0x7ffffffc
s_cmp_lg_u32 s2, 0
s_mul_i32 s27, s25, 3
s_cselect_b32 s23, -1, 0
s_lshl_b32 s3, s10, 1
s_lshl_b32 s28, s11, 3
s_add_i32 s3, s8, s3
v_add3_u32 v9, s28, v6, 0x1000
s_mul_i32 s3, s12, s3
s_lshl_b32 s30, s11, 2
s_add_i32 s26, s11, s3
s_add_i32 s3, s8, s10
s_addk_i32 s24, 0x3000
s_mul_i32 s3, s12, s3
s_add_i32 s29, s11, s1
s_add_i32 s28, s11, s3
s_add_i32 s31, s30, 0x1000
s_lshl_b32 s33, s2, 2
s_mov_b64 s[2:3], src_shared_base
s_branch .LBB0_5
.LBB0_4:
v_add_nc_u32_e32 v11, s14, v7
v_add_nc_u32_e32 v1, 0x400, v1
s_addk_i32 s14, 0x400
s_addk_i32 s26, 0x400
s_addk_i32 s28, 0x400
v_ashrrev_i32_e32 v12, 31, v11
s_addk_i32 s29, 0x400
s_cmp_le_i32 s14, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v11, vcc_lo, s6, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_store_b32 v[11:12], v2, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_25
.LBB0_5:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_7
s_ashr_i32 s2, s11, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s34, s11, s2
s_xor_b32 s34, s34, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v2, s34
s_sub_i32 s35, 0, s34
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v3, s35, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_add_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_mul_lo_u32 v3, v2, s34
v_add_nc_u32_e32 v11, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v0, v3
v_subrev_nc_u32_e32 v12, s34, v3
v_cmp_le_u32_e32 vcc_lo, s34, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
v_cmp_le_u32_e32 vcc_lo, s34, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, 1, v2
v_cndmask_b32_e32 v2, v2, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, s2, v2
v_subrev_nc_u32_e32 v13, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v13, s11
v_sub_nc_u32_e32 v14, v0, v2
v_mad_u64_u32 v[2:3], null, v13, s10, s[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v3, s14, v14
v_mad_u64_u32 v[11:12], null, v2, s12, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[2:3], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v11, v[2:3], off
v_mul_lo_u32 v2, v13, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_lshl_u32 v2, v2, v14, 2
v_cmp_ne_u32_e32 vcc_lo, -1, v2
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cndmask_b32_e64 v3, 0, s3, vcc_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v11 dlc
s_waitcnt_vscnt null, 0x0
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s16
s_cbranch_vccnz .LBB0_14
s_and_not1_b32 vcc_lo, exec_lo, s19
s_mov_b32 s1, 0
s_cbranch_vccnz .LBB0_11
v_mov_b32_e32 v2, v0
s_mov_b32 s2, 0
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, s29, v2
v_add_nc_u32_e32 v13, s2, v10
s_add_i32 s1, s1, 3
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v13
global_load_b32 v3, v[11:12], off
v_add_nc_u32_e32 v11, s28, v2
v_cndmask_b32_e32 v13, 0, v13, vcc_lo
v_cndmask_b32_e64 v14, 0, s3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[13:14], v3 dlc
s_waitcnt_vscnt null, 0x0
global_load_b32 v3, v[11:12], off
v_add_nc_u32_e32 v11, s26, v2
v_add_nc_u32_e32 v2, s27, v2
v_add_nc_u32_e32 v13, s2, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_cmp_ne_u32_e32 vcc_lo, -1, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_cndmask_b32_e32 v13, 0, v13, vcc_lo
v_cndmask_b32_e64 v14, 0, s3, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[13:14], v3 dlc
s_waitcnt_vscnt null, 0x0
global_load_b32 v3, v[11:12], off
v_add_nc_u32_e32 v11, s2, v8
s_add_i32 s2, s2, s24
s_cmp_lg_u32 s20, s1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v11
v_cndmask_b32_e32 v11, 0, v11, vcc_lo
v_cndmask_b32_e64 v12, 0, s3, vcc_lo
s_waitcnt vmcnt(0)
flat_store_b32 v[11:12], v3 dlc
s_waitcnt_vscnt null, 0x0
s_cbranch_scc1 .LBB0_10
.LBB0_11:
v_cmp_ne_u32_e32 vcc_lo, 1, v5
s_cbranch_vccnz .LBB0_14
s_mul_i32 s2, s10, s1
s_mul_i32 s1, s15, s1
s_add_i32 s2, s8, s2
v_add_lshl_u32 v11, v4, s1, 2
v_mad_u64_u32 v[2:3], null, s12, s2, v[1:2]
s_mov_b32 s1, s18
.p2align 6
.LBB0_13:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s1, s1, -1
s_cmp_lg_u32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[2:3]
v_add_nc_u32_e32 v2, s25, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s4, v12
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v11
global_load_b32 v3, v[12:13], off
v_cndmask_b32_e64 v13, 0, s3, vcc_lo
v_cndmask_b32_e32 v12, 0, v11, vcc_lo
v_add_nc_u32_e32 v11, s31, v11
s_waitcnt vmcnt(0)
flat_store_b32 v[12:13], v3 dlc
s_waitcnt_vscnt null, 0x0
s_cbranch_scc1 .LBB0_13
.LBB0_14:
v_mov_b32_e32 v2, 0
s_and_not1_b32 vcc_lo, exec_lo, s16
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_4
v_mov_b32_e32 v3, v6
s_mov_b32 s34, 0
s_mov_b32 s35, 0
s_branch .LBB0_17
.LBB0_16:
v_add_nc_u32_e32 v3, s31, v3
s_add_i32 s35, s35, 1
s_add_i32 s34, s34, s30
s_cmp_lg_u32 s35, s9
s_cbranch_scc0 .LBB0_4
.LBB0_17:
s_and_not1_b32 vcc_lo, exec_lo, s17
s_cbranch_vccnz .LBB0_16
s_and_not1_b32 vcc_lo, exec_lo, s21
s_cbranch_vccnz .LBB0_22
v_mov_b32_e32 v11, v3
s_mov_b32 s36, 0
s_mov_b32 s37, s34
.LBB0_20:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s1, s37, 0x33d0
v_cmp_ne_u32_e32 vcc_lo, -1, v11
s_cmp_lg_u32 s1, -1
s_cselect_b32 s39, s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v21, s39 :: v_dual_add_nc_u32 v14, 4, v11
s_cselect_b32 s38, s1, 0
s_add_i32 s40, s37, 0x33d4
v_dual_mov_b32 v20, s38 :: v_dual_add_nc_u32 v17, 12, v11
s_cmp_lg_u32 s40, -1
v_cndmask_b32_e64 v13, 0, s3, vcc_lo
s_cselect_b32 s39, s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_cndmask_b32 v12, 0, v11 :: v_dual_mov_b32 v23, s39
v_cmp_ne_u32_e32 vcc_lo, -1, v14
v_add_nc_u32_e32 v15, 8, v11
v_cmp_ne_u32_e64 s2, -1, v17
s_cselect_b32 s38, s40, 0
s_add_i32 s40, s37, 0x33d8
v_cndmask_b32_e32 v14, 0, v14, vcc_lo
v_cmp_ne_u32_e64 s1, -1, v15
s_cmp_lg_u32 s40, -1
v_cndmask_b32_e64 v18, 0, v17, s2
v_cndmask_b32_e64 v19, 0, s3, s2
flat_load_b32 v20, v[20:21] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v21, v[12:13] glc dlc
s_waitcnt vmcnt(0)
s_cselect_b32 s2, s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v22, s38 :: v_dual_mov_b32 v13, s2
v_cndmask_b32_e64 v16, 0, v15, s1
v_cndmask_b32_e64 v15, 0, s3, vcc_lo
v_cndmask_b32_e64 v17, 0, s3, s1
s_cselect_b32 s1, s40, 0
s_add_i32 s38, s37, 0x33dc
flat_load_b32 v22, v[22:23] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v23, v[14:15] glc dlc
s_waitcnt vmcnt(0)
s_cmp_lg_u32 s38, -1
v_add_nc_u32_e32 v11, 16, v11
s_cselect_b32 s2, s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v12, s1 :: v_dual_mov_b32 v15, s2
s_cselect_b32 s1, s38, 0
s_add_i32 s36, s36, 4
v_mov_b32_e32 v14, s1
flat_load_b32 v12, v[12:13] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v13, v[16:17] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v14, v[14:15] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v15, v[18:19] glc dlc
s_waitcnt vmcnt(0)
s_add_i32 s37, s37, 16
s_cmp_lg_u32 s22, s36
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v2, v20, v21
s_waitcnt lgkmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v22, v23
s_waitcnt lgkmcnt(2)
v_fmac_f32_e32 v2, v12, v13
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, v14, v15
s_cbranch_scc1 .LBB0_20
s_and_not1_b32 vcc_lo, exec_lo, s23
s_cbranch_vccz .LBB0_23
s_branch .LBB0_16
.LBB0_22:
s_mov_b32 s36, 0
s_and_not1_b32 vcc_lo, exec_lo, s23
s_cbranch_vccnz .LBB0_16
.LBB0_23:
s_lshl_b32 s1, s36, 2
s_mov_b32 s2, 0
v_add_nc_u32_e32 v11, s1, v3
s_add_i32 s1, s1, s34
.p2align 6
.LBB0_24:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s36, s1, s2
s_addk_i32 s36, 0x33d0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s36, -1
s_cselect_b32 s37, s3, 0
v_dual_mov_b32 v15, s37 :: v_dual_add_nc_u32 v12, s2, v11
s_cselect_b32 s36, s36, 0
s_add_i32 s2, s2, 4
v_mov_b32_e32 v14, s36
s_delay_alu instid0(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, -1, v12
s_cmp_lg_u32 s33, s2
v_cndmask_b32_e32 v12, 0, v12, vcc_lo
v_cndmask_b32_e64 v13, 0, s3, vcc_lo
flat_load_b32 v14, v[14:15] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v12, v[12:13] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v2, v14, v12
s_cbranch_scc1 .LBB0_24
s_branch .LBB0_16
.LBB0_25:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10timeFilterPKdPKfS2_Pf
.amdhsa_group_segment_fixed_size 14236
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 41
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10timeFilterPKdPKfS2_Pf, .Lfunc_end0-_Z10timeFilterPKdPKfS2_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 14236
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10timeFilterPKdPKfS2_Pf
.private_segment_fixed_size: 0
.sgpr_count: 43
.sgpr_spill_count: 0
.symbol: _Z10timeFilterPKdPKfS2_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
const int Nthreads = 1024, maxFR = 100000, NrankMax = 3, nmaxiter = 500, NchanMax = 32;
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
// THIS UPDATE DOES NOT UPDATE ELOSS?
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////
__global__ void timeFilter(const double *Params, const float *data, const float *W,float *conv_sig){
volatile __shared__ float sW2[81*NrankMax], sW[81*NrankMax], sdata[(Nthreads+81)*NrankMax];
float x;
int tid, tid0, bid, i, nid, Nrank, NT, Nfilt, nt0;
tid = threadIdx.x;
bid = blockIdx.x;
NT = (int) Params[0];
Nfilt = (int) Params[1];
Nrank = (int) Params[6];
nt0 = (int) Params[4];
if(tid<nt0*Nrank)
sW[tid] = W[tid%nt0 + (bid + Nfilt * (tid/nt0))* nt0];
__syncthreads();
tid0 = 0;
while (tid0<NT-Nthreads-nt0+1){
if (tid<nt0*NrankMax)
sdata[tid%nt0 + (tid/nt0)*(Nthreads+nt0)] =
data[tid0 + tid%nt0+ NT*(bid + Nfilt*(tid/nt0))];
#pragma unroll 3
for(nid=0;nid<Nrank;nid++){
sdata[tid + nt0+nid*(Nthreads+nt0)] = data[nt0+tid0 + tid+ NT*(bid +nid*Nfilt)];
}
__syncthreads();
x = 0.0f;
for(nid=0;nid<Nrank;nid++){
#pragma unroll 4
for(i=0;i<nt0;i++)
x += sW[i + nid*nt0] * sdata[i+tid + nid*(Nthreads+nt0)];
}
conv_sig[tid0 + tid + NT*bid] = x;
tid0+=Nthreads;
__syncthreads();
}
} | .text
.file "timeFilter.hip"
.globl _Z25__device_stub__timeFilterPKdPKfS2_Pf # -- Begin function _Z25__device_stub__timeFilterPKdPKfS2_Pf
.p2align 4, 0x90
.type _Z25__device_stub__timeFilterPKdPKfS2_Pf,@function
_Z25__device_stub__timeFilterPKdPKfS2_Pf: # @_Z25__device_stub__timeFilterPKdPKfS2_Pf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10timeFilterPKdPKfS2_Pf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__timeFilterPKdPKfS2_Pf, .Lfunc_end0-_Z25__device_stub__timeFilterPKdPKfS2_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10timeFilterPKdPKfS2_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10timeFilterPKdPKfS2_Pf,@object # @_Z10timeFilterPKdPKfS2_Pf
.section .rodata,"a",@progbits
.globl _Z10timeFilterPKdPKfS2_Pf
.p2align 3, 0x0
_Z10timeFilterPKdPKfS2_Pf:
.quad _Z25__device_stub__timeFilterPKdPKfS2_Pf
.size _Z10timeFilterPKdPKfS2_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10timeFilterPKdPKfS2_Pf"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__timeFilterPKdPKfS2_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10timeFilterPKdPKfS2_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00158dba_00000000-6_timeFilter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z10timeFilterPKdPKfS2_PfPKdPKfS2_Pf
.type _Z39__device_stub__Z10timeFilterPKdPKfS2_PfPKdPKfS2_Pf, @function
_Z39__device_stub__Z10timeFilterPKdPKfS2_PfPKdPKfS2_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10timeFilterPKdPKfS2_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z10timeFilterPKdPKfS2_PfPKdPKfS2_Pf, .-_Z39__device_stub__Z10timeFilterPKdPKfS2_PfPKdPKfS2_Pf
.globl _Z10timeFilterPKdPKfS2_Pf
.type _Z10timeFilterPKdPKfS2_Pf, @function
_Z10timeFilterPKdPKfS2_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z10timeFilterPKdPKfS2_PfPKdPKfS2_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10timeFilterPKdPKfS2_Pf, .-_Z10timeFilterPKdPKfS2_Pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10timeFilterPKdPKfS2_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10timeFilterPKdPKfS2_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "timeFilter.hip"
.globl _Z25__device_stub__timeFilterPKdPKfS2_Pf # -- Begin function _Z25__device_stub__timeFilterPKdPKfS2_Pf
.p2align 4, 0x90
.type _Z25__device_stub__timeFilterPKdPKfS2_Pf,@function
_Z25__device_stub__timeFilterPKdPKfS2_Pf: # @_Z25__device_stub__timeFilterPKdPKfS2_Pf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10timeFilterPKdPKfS2_Pf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__timeFilterPKdPKfS2_Pf, .Lfunc_end0-_Z25__device_stub__timeFilterPKdPKfS2_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10timeFilterPKdPKfS2_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10timeFilterPKdPKfS2_Pf,@object # @_Z10timeFilterPKdPKfS2_Pf
.section .rodata,"a",@progbits
.globl _Z10timeFilterPKdPKfS2_Pf
.p2align 3, 0x0
_Z10timeFilterPKdPKfS2_Pf:
.quad _Z25__device_stub__timeFilterPKdPKfS2_Pf
.size _Z10timeFilterPKdPKfS2_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10timeFilterPKdPKfS2_Pf"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__timeFilterPKdPKfS2_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10timeFilterPKdPKfS2_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Molecular dynamics simulation linear code for binary Lennard-Jones liquid under NVE ensemble;
Author: You-Liang Zhu, Email: [email protected]
Copyright: You-Liang Zhu
This code is free: you can redistribute it and/or modify it under the terms of the GNU General Public License.*/
#include <stdio.h>
#include <string.h>
#include <ctype.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <cuda_runtime.h>
// periodic boundary condition
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(-1);
}
}
__host__ __device__ float pbc(float x, float box_len) // implement periodic bondary condition
{
float box_half = box_len * 0.5;
if (x > box_half) x -= box_len;
else if (x < -box_half) x += box_len;
return x;
}
// randome number generator [0.0-1.0)
float R2S()
{
int ran = rand();
float fran = (float)ran/(float)RAND_MAX;
return fran;
}
// initially generate the position and mass of particles
void init(unsigned int np, float4* r, float4* v, float3 box, float min_dis)
{
for (unsigned int i=0; i<np; i++)
{
bool find_pos = false;
float4 ri;
while(!find_pos)
{
ri.x = ( R2S() - 0.5 ) * box.x;
ri.y = ( R2S() - 0.5 ) * box.y;
ri.z = ( R2S() - 0.5 ) * box.z;
find_pos = true;
for(unsigned int j=0; j<i; j++)
{
float dx = pbc(ri.x - r[j].x, box.x);
float dy = pbc(ri.y - r[j].y, box.y);
float dz = pbc(ri.z - r[j].z, box.z);
float r = sqrt(dx*dx + dy*dy + dz*dz);
if(r<min_dis) // a minimum safe distance to avoid the overlap of LJ particles
{
find_pos = false;
break;
}
}
}
if(R2S()>0.5) // randomly generate the type of particle, 1.0 represent type A and 2.0 represent type B
ri.w =1.0;
else
ri.w =2.0;
r[i] = ri;
v[i].w = 1.0;
}
}
// first step integration of velocity verlet algorithm
extern "C" __global__ void first_integration_kernel(unsigned int np, float dt, float3 box, float4* r, float4* v, float4* f)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<np)
{
float4 ri = r[i];
float mass = v[i].w;
v[i].x += 0.5 * dt * f[i].x / mass;
v[i].y += 0.5 * dt * f[i].y / mass;
v[i].z += 0.5 * dt * f[i].z / mass;
ri.x += dt * v[i].x;
ri.y += dt * v[i].y;
ri.z += dt * v[i].z;
r[i].x = pbc(ri.x, box.x);
r[i].y = pbc(ri.y, box.y);
r[i].z = pbc(ri.z, box.z);
}
}
void first_integration(unsigned int np, float dt, float3 box, float4* r, float4* v, float4* f, unsigned int block_size)
{
dim3 grid( (np/block_size) + 1, 1, 1);
dim3 block(block_size, 1, 1);
first_integration_kernel<<< grid, block >>>(np, dt, box, r, v, f);
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
}
// non-bonded force calculation
extern "C" __global__ void force_calculation_kernel(unsigned int np, float3 box, float3 epsilon, float3 sigma, float4* r, float4* f, float rcut)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<np)
{
float4 force = make_float4(0.0, 0.0, 0.0, 0.0);
for(unsigned int j=0; j<np; j++)
{
/* particles have no interactions with themselves */
if (i==j) continue;
/* calculated the shortest distance between particle i and j */
float dx = pbc(r[i].x - r[j].x, box.x);
float dy = pbc(r[i].y - r[j].y, box.y);
float dz = pbc(r[i].z - r[j].z, box.z);
float type = r[i].w + r[j].w;
float r = sqrt(dx*dx + dy*dy + dz*dz);
/* compute force and energy if within cutoff */
if (r < rcut)
{
float epsilonij, sigmaij;
if(type==2.0) // i=1.0, j=1.0
{
epsilonij = epsilon.x;
sigmaij = sigma.x;
}
else if(type==3.0) // i=1.0, j=2.0; or i=2.0, j=1.0
{
epsilonij = epsilon.y;
sigmaij = sigma.y;
}
else if(type==4.0) // i=2.0, j=2.0
{
epsilonij = epsilon.z;
sigmaij = sigma.z;
}
float ffac = -4.0*epsilonij*(-12.0*__powf(sigmaij/r,12.0)/r + 6.0*__powf(sigmaij/r,6.0)/r); // force between particle i and j
float epot = 0.5*4.0*epsilonij*(__powf(sigmaij/r,12.0) - __powf(sigmaij/r,6.0)); // potential between particle i and j
force.x += ffac*dx/r;
force.y += ffac*dy/r;
force.z += ffac*dz/r;
force.w += epot;
}
}
f[i] = force;
// printf("%d %f %f %f %f \n", i, force.x, force.y, force.z, force.w);
}
}
void force_calculation(unsigned int np, float3 box, float3 epsilon, float3 sigma, float4* r, float4* f, float rcut, unsigned int block_size)
{
dim3 grid( (np/block_size) + 1, 1, 1);
dim3 block(block_size, 1, 1);
force_calculation_kernel<<< grid, block >>>(np, box, epsilon, sigma, r, f, rcut);
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
}
// second step integration of velocity verlet algorithm
extern "C" __global__ void second_integration_kernel(unsigned int np, float dt, float4* v, float4* f)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<np)
{
float mass = v[i].w;
v[i].x += 0.5 * dt * f[i].x / mass;
v[i].y += 0.5 * dt * f[i].y / mass;
v[i].z += 0.5 * dt * f[i].z / mass;
}
}
void second_integration(unsigned int np, float dt, float4* v, float4* f, unsigned int block_size)
{
dim3 grid( (np/block_size) + 1, 1, 1);
dim3 block(block_size, 1, 1);
second_integration_kernel<<< grid, block >>>(np, dt, v, f);
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
}
// system information collection for temperature, kinetic energy, potential and total energy
extern __shared__ float2 sdata[];
__global__ void compute_info_sums_kernel(unsigned int np, float4* v, float4* f, float2* scratch)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
float2 tempo;
if (i < np)
{
float4 vi = v[i];
float mass = vi.w;
tempo.x = mass * (vi.x*vi.x + vi.y*vi.y + vi.z*vi.z);
tempo.y = f[i].w;
}
else
{
tempo.x = float(0.0);
tempo.y = float(0.0);
}
sdata[threadIdx.x] = tempo;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0)
{
if (threadIdx.x < offs)
{
sdata[threadIdx.x].x += sdata[threadIdx.x + offs].x;
sdata[threadIdx.x].y += sdata[threadIdx.x + offs].y;
}
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
{
scratch[blockIdx.x].x = sdata[0].x;
scratch[blockIdx.x].y = sdata[0].y;
}
}
__global__ void compute_info_final_kernel(unsigned int np, float* info, float2* scratch, unsigned int num_partial_sums)
{
float2 final_sum = make_float2(0.0, 0.0);
for (int start = 0; start < num_partial_sums; start += blockDim.x)
{
__syncthreads();
if (start + threadIdx.x < num_partial_sums)
{
float2 scr = scratch[start + threadIdx.x];
sdata[threadIdx.x].x = scr.x;
sdata[threadIdx.x].y = scr.y;
}
else
{
sdata[threadIdx.x].x = float(0.0);
sdata[threadIdx.x].y = float(0.0);
}
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0)
{
if (threadIdx.x < offs)
{
sdata[threadIdx.x].x += sdata[threadIdx.x + offs].x;
sdata[threadIdx.x].y += sdata[threadIdx.x + offs].y;
}
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
{
final_sum.x += sdata[0].x;
final_sum.y += sdata[0].y;
}
}
if (threadIdx.x == 0)
{
float ekin = 0.5*final_sum.x;
float potential = final_sum.y;
unsigned int nfreedom = 3 * np - 3;
float temp = 2.0*ekin/float(nfreedom);
float energy = ekin + potential;
info[0] = temp;
info[1] = potential;
info[2] = energy;
}
}
void compute_info(unsigned int np, float4* v, float4* f, float2* scratch, float* info, unsigned int block_size)
{
unsigned int n_blocks = (int)ceil((float)np / (float)block_size);
dim3 grid(n_blocks, 1, 1);
dim3 threads(block_size, 1, 1);
unsigned int shared_bytes = sizeof(float2)*block_size;
compute_info_sums_kernel<<<grid,threads, shared_bytes>>>(np, v, f, scratch);
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
int final_block_size = 512;
grid = dim3(1, 1, 1);
threads = dim3(final_block_size, 1, 1);
shared_bytes = sizeof(float2)*final_block_size;
compute_info_final_kernel<<<grid, threads, shared_bytes>>>(np, info, scratch, n_blocks);
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
}
// output system information and frame in XYZ formation which can be read by VMD
void output(FILE *traj, unsigned int step, float* info, float4* r, unsigned int np)
{
float temp = info[0];
float potential = info[1];
float energy = info[2];
fprintf(traj,"%d\n step=%d temp=%20.8f pot=%20.8f ener=%20.8f\n", np, step, temp, potential, energy);
for (unsigned int i=0; i<np; i++)
{
float4 ri = r[i];
if (ri.w == 1.0)
fprintf(traj, "A %20.8f %20.8f %20.8f\n", ri.x, ri.y, ri.z);
else if (ri.w == 2.0)
fprintf(traj, "B %20.8f %20.8f %20.8f\n", ri.x, ri.y, ri.z);
}
}
// main function
int main(int argc, char **argv)
{
//running parameters
unsigned int np = 2700; // the number of particles
unsigned int nsteps = 500; // the number of time steps
float dt = 0.001; // integration time step
float rcut = 3.0; // the cutoff radius of interactions
unsigned int nprint = 100; // period for data output
unsigned int block_size = 256; // the number of threads in a block
timeval start; // start time
timeval end; // end time
float3 box =make_float3(15.0, 15.0, 15.0); // box size in x, y, and z directions
float3 epsilon = make_float3(1.0, 0.5, 1.0); // epsilon.x for type 1.0 and 1.0; epsilon.y for type 1.0 and 2.0; epsilon.z for type 1.0 and 2.0
float3 sigma = make_float3(1.0, 1.0, 1.0); // sigma.x for type 1.0 and 1.0; sigma.y for type 1.0 and 2.0; sigma.z for type 1.0 and 2.0
float min_dis = sigma.x*0.9; // the minimum distance between particles for system generation
//host memory allocation
float4* h_r = (float4 *)malloc(np*sizeof(float4)); // rx, ry, rz, type(0, 1, 2 ...)
float4* h_v = (float4 *)malloc(np*sizeof(float4)); // vx, vy, vz, mass
float4* h_f = (float4 *)malloc(np*sizeof(float4)); // fx, fy, fz, potential
float* h_info = (float *)malloc(16*sizeof(float)); // temperature, potential, energy ...
//device memory allocation
float4* d_r;
float4* d_v;
float4* d_f;
float* d_info;
float2* d_scratch;
cudaMalloc( (void **) &d_r, np*sizeof(float4) ); // rx, ry, rz, type(0, 1, 2 ...)
cudaMalloc( (void **) &d_v, np*sizeof(float4) ); // vx, vy, vz, mass
cudaMalloc( (void **) &d_f, np*sizeof(float4) ); // fx, fy, fz, potential
cudaMalloc( (void **) &d_info, 16*sizeof(float) ); // temperature, potential, energy ...
cudaMalloc( (void **) &d_scratch, (np/block_size + 1)*sizeof(float2) ); // temporary data ...
FILE *traj=fopen("traj.xyz","w"); // trajectory file in XYZ format that can be open by VMD
/* generate system information */
printf("Starting simulation with %d atoms for %d steps.\n", np, nsteps);
printf("Generating system.\n", np, nsteps);
init(np, h_r, h_v, box, min_dis);
cudaMemcpy( d_r, h_r, np*sizeof(float4), cudaMemcpyHostToDevice );
cudaMemcpy( d_v, h_v, np*sizeof(float4), cudaMemcpyHostToDevice );
gettimeofday(&start,NULL); //get start time
/* main MD loop */
printf("Running simulation.\n", np, nsteps);
for(unsigned int step =0; step <= nsteps; step++) //running simulation loop
{
/* first integration for velverlet */
first_integration(np, dt, box, d_r, d_v, d_f, block_size);
/* force calculation */
force_calculation(np, box, epsilon, sigma, d_r, d_f, rcut, block_size);
/* compute temperature and potential */
compute_info(np, d_v, d_f, d_scratch, d_info, block_size);
/* second integration for velverlet */
second_integration(np, dt, d_v, d_f, block_size);
/* write output frames and system information, if requested */
if ((step % nprint) == 0)
{
cudaMemcpy(h_r, d_r, np*sizeof(float4), cudaMemcpyDeviceToHost);
cudaMemcpy(h_info, d_info, 16*sizeof(float), cudaMemcpyDeviceToHost);
output(traj, step, h_info, h_r, np);
printf("time step %d \n", step);
}
}
gettimeofday(&end,NULL); // get end time
long timeusr=(end.tv_sec-start.tv_sec)*1000000+(end.tv_usec-start.tv_usec);
printf("time is %ld microseconds\n",timeusr); // the spending time on simulation in microseconds
fclose(traj);
free(h_r);
free(h_v);
free(h_f);
free(h_info);
cudaFree(d_r);
cudaFree(d_v);
cudaFree(d_f);
cudaFree(d_info);
return 0;
} | .file "tmpxft_00027b09_00000000-6_md_teacher.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z3pbcff
.type _Z3pbcff, @function
_Z3pbcff:
.LFB2058:
.cfi_startproc
endbr64
movaps %xmm1, %xmm2
mulss .LC1(%rip), %xmm2
comiss %xmm2, %xmm0
jbe .L15
subss %xmm1, %xmm0
ret
.L15:
xorps .LC2(%rip), %xmm2
comiss %xmm0, %xmm2
jbe .L7
addss %xmm1, %xmm0
.L7:
ret
.cfi_endproc
.LFE2058:
.size _Z3pbcff, .-_Z3pbcff
.globl _Z3R2Sv
.type _Z3R2Sv, @function
_Z3R2Sv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC3(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z3R2Sv, .-_Z3R2Sv
.globl _Z4initjP6float4S0_6float3f
.type _Z4initjP6float4S0_6float3f, @function
_Z4initjP6float4S0_6float3f:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movss %xmm1, 40(%rsp)
movss %xmm2, 44(%rsp)
movq %xmm0, 48(%rsp)
movss %xmm1, 56(%rsp)
movss 48(%rsp), %xmm7
movss %xmm7, 32(%rsp)
movss 52(%rsp), %xmm7
movss %xmm7, 36(%rsp)
testl %edi, %edi
je .L19
movl %edi, %r15d
movq %rsi, %r13
movq %rdx, %r14
addq $12, %r14
movq %rsi, %rbp
movl $0, %r12d
.L23:
call _Z3R2Sv
cvtss2sd %xmm0, %xmm0
subsd .LC6(%rip), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 32(%rsp), %xmm1
mulsd %xmm1, %xmm0
pxor %xmm6, %xmm6
cvtsd2ss %xmm0, %xmm6
movss %xmm6, 20(%rsp)
call _Z3R2Sv
cvtss2sd %xmm0, %xmm0
subsd .LC6(%rip), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 36(%rsp), %xmm1
mulsd %xmm1, %xmm0
pxor %xmm7, %xmm7
cvtsd2ss %xmm0, %xmm7
movss %xmm7, 24(%rsp)
call _Z3R2Sv
cvtss2sd %xmm0, %xmm0
subsd .LC6(%rip), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 40(%rsp), %xmm1
mulsd %xmm1, %xmm0
pxor %xmm6, %xmm6
cvtsd2ss %xmm0, %xmm6
movss %xmm6, 28(%rsp)
testl %r12d, %r12d
je .L22
movq %r13, %rbx
.L24:
movss 20(%rsp), %xmm0
subss (%rbx), %xmm0
movss 32(%rsp), %xmm1
call _Z3pbcff
movss %xmm0, 12(%rsp)
movss 24(%rsp), %xmm3
subss 4(%rbx), %xmm3
movaps %xmm3, %xmm0
movss 36(%rsp), %xmm1
call _Z3pbcff
movss %xmm0, 16(%rsp)
movss 28(%rsp), %xmm4
subss 8(%rbx), %xmm4
movaps %xmm4, %xmm0
movss 40(%rsp), %xmm1
call _Z3pbcff
movss 12(%rsp), %xmm1
mulss %xmm1, %xmm1
movss 16(%rsp), %xmm2
mulss %xmm2, %xmm2
addss %xmm2, %xmm1
mulss %xmm0, %xmm0
addss %xmm0, %xmm1
sqrtss %xmm1, %xmm1
movss 44(%rsp), %xmm5
comiss %xmm1, %xmm5
ja .L23
addq $16, %rbx
cmpq %rbp, %rbx
jne .L24
.L22:
call _Z3R2Sv
movss .LC4(%rip), %xmm2
movss .LC1(%rip), %xmm1
cmpltss %xmm0, %xmm1
andps %xmm1, %xmm2
movss .LC5(%rip), %xmm7
andnps %xmm7, %xmm1
orps %xmm1, %xmm2
movss 20(%rsp), %xmm7
movss %xmm7, 0(%rbp)
movss 24(%rsp), %xmm7
movss %xmm7, 4(%rbp)
movss 28(%rsp), %xmm7
movss %xmm7, 8(%rbp)
movss %xmm2, 12(%rbp)
movl $0x3f800000, (%r14)
addl $1, %r12d
addq $16, %rbp
addq $16, %r14
cmpl %r12d, %r15d
jne .L23
.L19:
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z4initjP6float4S0_6float3f, .-_Z4initjP6float4S0_6float3f
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "%d\n step=%d temp=%20.8f pot=%20.8f ener=%20.8f\n"
.section .rodata.str1.1
.LC8:
.string "A %20.8f %20.8f %20.8f\n"
.LC9:
.string "B %20.8f %20.8f %20.8f\n"
.text
.globl _Z6outputP8_IO_FILEjPfP6float4j
.type _Z6outputP8_IO_FILEjPfP6float4j, @function
_Z6outputP8_IO_FILEjPfP6float4j:
.LFB2065:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movq %rcx, %rbp
movl %r8d, %r13d
pxor %xmm0, %xmm0
cvtss2sd (%rdx), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 8(%rdx), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 4(%rdx), %xmm1
movl %esi, %r8d
movl %r13d, %ecx
leaq .LC7(%rip), %rdx
movl $2, %esi
movl $3, %eax
call __fprintf_chk@PLT
testl %r13d, %r13d
je .L32
movq %rbp, %rbx
movl %r13d, %r13d
salq $4, %r13
addq %r13, %rbp
leaq .LC9(%rip), %r14
leaq .LC8(%rip), %r13
jmp .L38
.L43:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm1, %xmm1
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $3, %eax
call __fprintf_chk@PLT
.L36:
addq $16, %rbx
cmpq %rbp, %rbx
je .L32
.L38:
movss (%rbx), %xmm0
movss 4(%rbx), %xmm1
movss 8(%rbx), %xmm2
movss 12(%rbx), %xmm3
ucomiss .LC4(%rip), %xmm3
jp .L34
je .L43
.L34:
ucomiss .LC5(%rip), %xmm3
jp .L36
jne .L36
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm1, %xmm1
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $3, %eax
call __fprintf_chk@PLT
jmp .L36
.L32:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _Z6outputP8_IO_FILEjPfP6float4j, .-_Z6outputP8_IO_FILEjPfP6float4j
.globl _Z65__device_stub__Z24first_integration_kerneljf6float3P6float4S1_S1_jfR6float3P6float4S2_S2_
.type _Z65__device_stub__Z24first_integration_kerneljf6float3P6float4S1_S1_jfR6float3P6float4S2_S2_, @function
_Z65__device_stub__Z24first_integration_kerneljf6float3P6float4S1_S1_jfR6float3P6float4S2_S2_:
.LFB2091:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsi, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq first_integration_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z65__device_stub__Z24first_integration_kerneljf6float3P6float4S1_S1_jfR6float3P6float4S2_S2_, .-_Z65__device_stub__Z24first_integration_kerneljf6float3P6float4S1_S1_jfR6float3P6float4S2_S2_
.globl first_integration_kernel
.type first_integration_kernel, @function
first_integration_kernel:
.LFB2092:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rcx, %r8
movq %xmm1, (%rsp)
movss %xmm2, 8(%rsp)
movq %rsp, %rax
movq %rdx, %rcx
movq %rsi, %rdx
movq %rax, %rsi
call _Z65__device_stub__Z24first_integration_kerneljf6float3P6float4S1_S1_jfR6float3P6float4S2_S2_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size first_integration_kernel, .-first_integration_kernel
.section .rodata.str1.1
.LC10:
.string "kernel execution"
.text
.globl _Z17first_integrationjf6float3P6float4S1_S1_j
.type _Z17first_integrationjf6float3P6float4S1_S1_j, @function
_Z17first_integrationjf6float3P6float4S1_S1_j:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebx
movss %xmm0, 12(%rsp)
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %xmm1, 16(%rsp)
movss %xmm2, 24(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %edi, %eax
movl $0, %edx
divl %r8d
addl $1, %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl %r8d, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L53:
call cudaThreadSynchronize@PLT
leaq .LC10(%rip), %rdi
call _Z14checkCUDAErrorPKc
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L57
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
movq 16(%rsp), %rax
movq %rax, 60(%rsp)
movl 24(%rsp), %eax
movl %eax, 68(%rsp)
leaq 60(%rsp), %rsi
movq %r13, %r8
movq %r12, %rcx
movq %rbp, %rdx
movss 12(%rsp), %xmm0
movl %ebx, %edi
call _Z65__device_stub__Z24first_integration_kerneljf6float3P6float4S1_S1_jfR6float3P6float4S2_S2_
jmp .L53
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z17first_integrationjf6float3P6float4S1_S1_j, .-_Z17first_integrationjf6float3P6float4S1_S1_j
.globl _Z66__device_stub__Z24force_calculation_kernelj6float3S_S_P6float4S1_fjR6float3S0_S0_P6float4S2_f
.type _Z66__device_stub__Z24force_calculation_kernelj6float3S_S_P6float4S1_fjR6float3S0_S0_P6float4S2_f, @function
_Z66__device_stub__Z24force_calculation_kernelj6float3S_S_P6float4S1_fjR6float3S0_S0_P6float4S2_f:
.LFB2093:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movss %xmm0, 24(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 104(%rsp)
movq %rdx, 112(%rsp)
movq %rcx, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L62
.L58:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L63
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq force_calculation_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L58
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z66__device_stub__Z24force_calculation_kernelj6float3S_S_P6float4S1_fjR6float3S0_S0_P6float4S2_f, .-_Z66__device_stub__Z24force_calculation_kernelj6float3S_S_P6float4S1_fjR6float3S0_S0_P6float4S2_f
.globl force_calculation_kernel
.type force_calculation_kernel, @function
force_calculation_kernel:
.LFB2094:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movdqa %xmm0, %xmm7
movq %rsi, %r8
movq %rdx, %r9
movaps %xmm6, %xmm0
movq %xmm7, 32(%rsp)
movss %xmm1, 40(%rsp)
movq %xmm2, 16(%rsp)
movss %xmm3, 24(%rsp)
movq %xmm4, (%rsp)
movss %xmm5, 8(%rsp)
movq %rsp, %rcx
leaq 16(%rsp), %rdx
leaq 32(%rsp), %rsi
call _Z66__device_stub__Z24force_calculation_kernelj6float3S_S_P6float4S1_fjR6float3S0_S0_P6float4S2_f
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size force_calculation_kernel, .-force_calculation_kernel
.globl _Z17force_calculationj6float3S_S_P6float4S1_fj
.type _Z17force_calculationj6float3S_S_P6float4S1_fj, @function
_Z17force_calculationj6float3S_S_P6float4S1_fj:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $144, %rsp
.cfi_def_cfa_offset 176
movl %edi, %ebx
movq %rsi, %rbp
movq %rdx, %r12
movss %xmm6, 12(%rsp)
movq %xmm0, 48(%rsp)
movss %xmm1, 56(%rsp)
movq %xmm2, 32(%rsp)
movss %xmm3, 40(%rsp)
movq %xmm4, 16(%rsp)
movss %xmm5, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl %edi, %eax
movl $0, %edx
divl %ecx
addl $1, %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl %ecx, 88(%rsp)
movl $1, 92(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L70
.L67:
call cudaThreadSynchronize@PLT
leaq .LC10(%rip), %rdi
call _Z14checkCUDAErrorPKc
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L71
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L70:
.cfi_restore_state
movq 48(%rsp), %rax
movq %rax, 100(%rsp)
movl 56(%rsp), %eax
movl %eax, 108(%rsp)
movq 32(%rsp), %rax
movq %rax, 112(%rsp)
movl 40(%rsp), %eax
movl %eax, 120(%rsp)
movq 16(%rsp), %rax
movq %rax, 124(%rsp)
movl 24(%rsp), %eax
movl %eax, 132(%rsp)
leaq 124(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 100(%rsp), %rsi
movss 12(%rsp), %xmm0
movq %r12, %r9
movq %rbp, %r8
movl %ebx, %edi
call _Z66__device_stub__Z24force_calculation_kernelj6float3S_S_P6float4S1_fjR6float3S0_S0_P6float4S2_f
jmp .L67
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z17force_calculationj6float3S_S_P6float4S1_fj, .-_Z17force_calculationj6float3S_S_P6float4S1_fj
.globl _Z56__device_stub__Z25second_integration_kerneljfP6float4S0_jfP6float4S0_
.type _Z56__device_stub__Z25second_integration_kerneljfP6float4S0_jfP6float4S0_, @function
_Z56__device_stub__Z25second_integration_kerneljfP6float4S0_jfP6float4S0_:
.LFB2095:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L76
.L72:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L77
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L76:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq second_integration_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L72
.L77:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z56__device_stub__Z25second_integration_kerneljfP6float4S0_jfP6float4S0_, .-_Z56__device_stub__Z25second_integration_kerneljfP6float4S0_jfP6float4S0_
.globl second_integration_kernel
.type second_integration_kernel, @function
second_integration_kernel:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z25second_integration_kerneljfP6float4S0_jfP6float4S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size second_integration_kernel, .-second_integration_kernel
.globl _Z18second_integrationjfP6float4S0_j
.type _Z18second_integrationjfP6float4S0_j, @function
_Z18second_integrationjfP6float4S0_j:
.LFB2063:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movss %xmm0, 12(%rsp)
movq %rsi, %rbp
movq %rdx, %r12
movl %edi, %eax
movl $0, %edx
divl %ecx
addl $1, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl %ecx, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L83
.L81:
call cudaThreadSynchronize@PLT
leaq .LC10(%rip), %rdi
call _Z14checkCUDAErrorPKc
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L83:
.cfi_restore_state
movq %r12, %rdx
movq %rbp, %rsi
movss 12(%rsp), %xmm0
movl %ebx, %edi
call _Z56__device_stub__Z25second_integration_kerneljfP6float4S0_jfP6float4S0_
jmp .L81
.cfi_endproc
.LFE2063:
.size _Z18second_integrationjfP6float4S0_j, .-_Z18second_integrationjfP6float4S0_j
.globl _Z62__device_stub__Z24compute_info_sums_kerneljP6float4S0_P6float2jP6float4S0_P6float2
.type _Z62__device_stub__Z24compute_info_sums_kerneljP6float4S0_P6float2jP6float4S0_P6float2, @function
_Z62__device_stub__Z24compute_info_sums_kerneljP6float4S0_P6float2jP6float4S0_P6float2:
.LFB2097:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L88
.L84:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L89
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L88:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24compute_info_sums_kerneljP6float4S0_P6float2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L84
.L89:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size _Z62__device_stub__Z24compute_info_sums_kerneljP6float4S0_P6float2jP6float4S0_P6float2, .-_Z62__device_stub__Z24compute_info_sums_kerneljP6float4S0_P6float2jP6float4S0_P6float2
.globl _Z24compute_info_sums_kerneljP6float4S0_P6float2
.type _Z24compute_info_sums_kerneljP6float4S0_P6float2, @function
_Z24compute_info_sums_kerneljP6float4S0_P6float2:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z62__device_stub__Z24compute_info_sums_kerneljP6float4S0_P6float2jP6float4S0_P6float2
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _Z24compute_info_sums_kerneljP6float4S0_P6float2, .-_Z24compute_info_sums_kerneljP6float4S0_P6float2
.globl _Z55__device_stub__Z25compute_info_final_kerneljPfP6float2jjPfP6float2j
.type _Z55__device_stub__Z25compute_info_final_kerneljPfP6float2jjPfP6float2j, @function
_Z55__device_stub__Z25compute_info_final_kerneljPfP6float2jjPfP6float2j:
.LFB2099:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L96
.L92:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L97
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L96:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25compute_info_final_kerneljPfP6float2j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L92
.L97:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2099:
.size _Z55__device_stub__Z25compute_info_final_kerneljPfP6float2jjPfP6float2j, .-_Z55__device_stub__Z25compute_info_final_kerneljPfP6float2jjPfP6float2j
.globl _Z25compute_info_final_kerneljPfP6float2j
.type _Z25compute_info_final_kerneljPfP6float2j, @function
_Z25compute_info_final_kerneljPfP6float2j:
.LFB2100:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z25compute_info_final_kerneljPfP6float2jjPfP6float2j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _Z25compute_info_final_kerneljPfP6float2j, .-_Z25compute_info_final_kerneljPfP6float2j
.globl _Z12compute_infojP6float4S0_P6float2Pfj
.type _Z12compute_infojP6float4S0_P6float2Pfj, @function
_Z12compute_infojP6float4S0_P6float2Pfj:
.LFB2064:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movq %rsi, %r13
movq %rdx, %r14
movq %rcx, %rbp
movq %r8, %r12
movl %r9d, %eax
movl %edi, %edx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
movl %r9d, %edx
pxor %xmm1, %xmm1
cvtsi2ssq %rdx, %xmm1
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC13(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC11(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L105
cvttss2sil %xmm0, %edx
pxor %xmm1, %xmm1
cvtsi2ssl %edx, %xmm1
cmpnless %xmm1, %xmm3
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L105:
cvttss2sil %xmm3, %r15d
movl %r15d, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
leal 0(,%rax,8), %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L109
.L106:
call cudaThreadSynchronize@PLT
leaq .LC10(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $1, 8(%rsp)
movl $512, 20(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $4096, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl 16(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L110
.L107:
call cudaThreadSynchronize@PLT
leaq .LC10(%rip), %rdi
call _Z14checkCUDAErrorPKc
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L109:
.cfi_restore_state
movq %rbp, %rcx
movq %r14, %rdx
movq %r13, %rsi
movl %ebx, %edi
call _Z62__device_stub__Z24compute_info_sums_kerneljP6float4S0_P6float2jP6float4S0_P6float2
jmp .L106
.L110:
movl %r15d, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movl %ebx, %edi
call _Z55__device_stub__Z25compute_info_final_kerneljPfP6float2jjPfP6float2j
jmp .L107
.cfi_endproc
.LFE2064:
.size _Z12compute_infojP6float4S0_P6float2Pfj, .-_Z12compute_infojP6float4S0_P6float2Pfj
.section .rodata.str1.1
.LC15:
.string "w"
.LC16:
.string "traj.xyz"
.section .rodata.str1.8
.align 8
.LC17:
.string "Starting simulation with %d atoms for %d steps.\n"
.section .rodata.str1.1
.LC18:
.string "Generating system.\n"
.LC20:
.string "Running simulation.\n"
.LC23:
.string "time step %d \n"
.LC24:
.string "time is %ld microseconds\n"
.text
.globl main
.type main, @function
main:
.LFB2066:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movss .LC14(%rip), %xmm0
movss %xmm0, 44(%rsp)
movss %xmm0, 48(%rsp)
movss %xmm0, 52(%rsp)
movss .LC4(%rip), %xmm0
movss %xmm0, 56(%rsp)
movl $0x3f000000, 60(%rsp)
movss %xmm0, 64(%rsp)
movss %xmm0, 68(%rsp)
movss %xmm0, 72(%rsp)
movss %xmm0, 76(%rsp)
movl $43200, %edi
call malloc@PLT
movq %rax, %rbp
movl $43200, %edi
call malloc@PLT
movq %rax, %r15
movl $64, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
movl $43200, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $43200, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $43200, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $88, %esi
call cudaMalloc@PLT
leaq .LC15(%rip), %rsi
leaq .LC16(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movl $500, %ecx
movl $2700, %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $500, %ecx
movl $2700, %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movss .LC19(%rip), %xmm2
movq 44(%rsp), %xmm0
movss 52(%rsp), %xmm1
movq %r15, %rdx
movq %rbp, %rsi
movl $2700, %edi
call _Z4initjP6float4S0_6float3f
movl $1, %ecx
movl $43200, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $43200, %edx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $500, %ecx
movl $2700, %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC23(%rip), %r14
jmp .L113
.L112:
addl $1, %ebx
cmpl $501, %ebx
je .L117
.L113:
movl $256, %r8d
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq 44(%rsp), %xmm1
movss 52(%rsp), %xmm2
movss .LC21(%rip), %xmm0
movl $2700, %edi
call _Z17first_integrationjf6float3P6float4S1_S1_j
movl $256, %ecx
movss .LC22(%rip), %xmm6
movq 16(%rsp), %rdx
movq (%rsp), %rsi
movq 68(%rsp), %xmm4
movss 76(%rsp), %xmm5
movq 56(%rsp), %xmm2
movss 64(%rsp), %xmm3
movq 44(%rsp), %xmm0
movss 52(%rsp), %xmm1
movl $2700, %edi
call _Z17force_calculationj6float3S_S_P6float4S1_fj
movl $256, %r9d
movq 24(%rsp), %r8
movq 32(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $2700, %edi
call _Z12compute_infojP6float4S0_P6float2Pfj
movl $256, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movss .LC21(%rip), %xmm0
movl $2700, %edi
call _Z18second_integrationjfP6float4S0_j
movl %ebx, %eax
imulq $1374389535, %rax, %rax
shrq $37, %rax
imull $100, %eax, %eax
cmpl %eax, %ebx
jne .L112
movl $2, %ecx
movl $43200, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $64, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2700, %r8d
movq %rbp, %rcx
movq %r12, %rdx
movl %ebx, %esi
movq %r13, %rdi
call _Z6outputP8_IO_FILEjPfP6float4j
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L112
.L117:
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rdx
subq 80(%rsp), %rdx
imulq $1000000, %rdx, %rdx
addq 104(%rsp), %rdx
subq 88(%rsp), %rdx
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call fclose@PLT
movq %rbp, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L118
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L118:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2066:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC25:
.string "_Z25compute_info_final_kerneljPfP6float2j"
.align 8
.LC26:
.string "_Z24compute_info_sums_kerneljP6float4S0_P6float2"
.section .rodata.str1.1
.LC27:
.string "second_integration_kernel"
.LC28:
.string "force_calculation_kernel"
.LC29:
.string "first_integration_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2102:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z25compute_info_final_kerneljPfP6float2j(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _Z24compute_info_sums_kerneljP6float4S0_P6float2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq second_integration_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq force_calculation_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq first_integration_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2102:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1056964608
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC3:
.long 805306368
.align 4
.LC4:
.long 1065353216
.align 4
.LC5:
.long 1073741824
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1071644672
.section .rodata.cst4
.align 4
.LC11:
.long 1258291200
.align 4
.LC13:
.long 2147483647
.align 4
.LC14:
.long 1097859072
.align 4
.LC19:
.long 1063675494
.align 4
.LC21:
.long 981668463
.align 4
.LC22:
.long 1077936128
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Molecular dynamics simulation linear code for binary Lennard-Jones liquid under NVE ensemble;
Author: You-Liang Zhu, Email: [email protected]
Copyright: You-Liang Zhu
This code is free: you can redistribute it and/or modify it under the terms of the GNU General Public License.*/
#include <stdio.h>
#include <string.h>
#include <ctype.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <cuda_runtime.h>
// periodic boundary condition
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(-1);
}
}
__host__ __device__ float pbc(float x, float box_len) // implement periodic bondary condition
{
float box_half = box_len * 0.5;
if (x > box_half) x -= box_len;
else if (x < -box_half) x += box_len;
return x;
}
// randome number generator [0.0-1.0)
float R2S()
{
int ran = rand();
float fran = (float)ran/(float)RAND_MAX;
return fran;
}
// initially generate the position and mass of particles
void init(unsigned int np, float4* r, float4* v, float3 box, float min_dis)
{
for (unsigned int i=0; i<np; i++)
{
bool find_pos = false;
float4 ri;
while(!find_pos)
{
ri.x = ( R2S() - 0.5 ) * box.x;
ri.y = ( R2S() - 0.5 ) * box.y;
ri.z = ( R2S() - 0.5 ) * box.z;
find_pos = true;
for(unsigned int j=0; j<i; j++)
{
float dx = pbc(ri.x - r[j].x, box.x);
float dy = pbc(ri.y - r[j].y, box.y);
float dz = pbc(ri.z - r[j].z, box.z);
float r = sqrt(dx*dx + dy*dy + dz*dz);
if(r<min_dis) // a minimum safe distance to avoid the overlap of LJ particles
{
find_pos = false;
break;
}
}
}
if(R2S()>0.5) // randomly generate the type of particle, 1.0 represent type A and 2.0 represent type B
ri.w =1.0;
else
ri.w =2.0;
r[i] = ri;
v[i].w = 1.0;
}
}
// first step integration of velocity verlet algorithm
extern "C" __global__ void first_integration_kernel(unsigned int np, float dt, float3 box, float4* r, float4* v, float4* f)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<np)
{
float4 ri = r[i];
float mass = v[i].w;
v[i].x += 0.5 * dt * f[i].x / mass;
v[i].y += 0.5 * dt * f[i].y / mass;
v[i].z += 0.5 * dt * f[i].z / mass;
ri.x += dt * v[i].x;
ri.y += dt * v[i].y;
ri.z += dt * v[i].z;
r[i].x = pbc(ri.x, box.x);
r[i].y = pbc(ri.y, box.y);
r[i].z = pbc(ri.z, box.z);
}
}
void first_integration(unsigned int np, float dt, float3 box, float4* r, float4* v, float4* f, unsigned int block_size)
{
dim3 grid( (np/block_size) + 1, 1, 1);
dim3 block(block_size, 1, 1);
first_integration_kernel<<< grid, block >>>(np, dt, box, r, v, f);
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
}
// non-bonded force calculation
extern "C" __global__ void force_calculation_kernel(unsigned int np, float3 box, float3 epsilon, float3 sigma, float4* r, float4* f, float rcut)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<np)
{
float4 force = make_float4(0.0, 0.0, 0.0, 0.0);
for(unsigned int j=0; j<np; j++)
{
/* particles have no interactions with themselves */
if (i==j) continue;
/* calculated the shortest distance between particle i and j */
float dx = pbc(r[i].x - r[j].x, box.x);
float dy = pbc(r[i].y - r[j].y, box.y);
float dz = pbc(r[i].z - r[j].z, box.z);
float type = r[i].w + r[j].w;
float r = sqrt(dx*dx + dy*dy + dz*dz);
/* compute force and energy if within cutoff */
if (r < rcut)
{
float epsilonij, sigmaij;
if(type==2.0) // i=1.0, j=1.0
{
epsilonij = epsilon.x;
sigmaij = sigma.x;
}
else if(type==3.0) // i=1.0, j=2.0; or i=2.0, j=1.0
{
epsilonij = epsilon.y;
sigmaij = sigma.y;
}
else if(type==4.0) // i=2.0, j=2.0
{
epsilonij = epsilon.z;
sigmaij = sigma.z;
}
float ffac = -4.0*epsilonij*(-12.0*__powf(sigmaij/r,12.0)/r + 6.0*__powf(sigmaij/r,6.0)/r); // force between particle i and j
float epot = 0.5*4.0*epsilonij*(__powf(sigmaij/r,12.0) - __powf(sigmaij/r,6.0)); // potential between particle i and j
force.x += ffac*dx/r;
force.y += ffac*dy/r;
force.z += ffac*dz/r;
force.w += epot;
}
}
f[i] = force;
// printf("%d %f %f %f %f \n", i, force.x, force.y, force.z, force.w);
}
}
void force_calculation(unsigned int np, float3 box, float3 epsilon, float3 sigma, float4* r, float4* f, float rcut, unsigned int block_size)
{
dim3 grid( (np/block_size) + 1, 1, 1);
dim3 block(block_size, 1, 1);
force_calculation_kernel<<< grid, block >>>(np, box, epsilon, sigma, r, f, rcut);
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
}
// second step integration of velocity verlet algorithm
extern "C" __global__ void second_integration_kernel(unsigned int np, float dt, float4* v, float4* f)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<np)
{
float mass = v[i].w;
v[i].x += 0.5 * dt * f[i].x / mass;
v[i].y += 0.5 * dt * f[i].y / mass;
v[i].z += 0.5 * dt * f[i].z / mass;
}
}
void second_integration(unsigned int np, float dt, float4* v, float4* f, unsigned int block_size)
{
dim3 grid( (np/block_size) + 1, 1, 1);
dim3 block(block_size, 1, 1);
second_integration_kernel<<< grid, block >>>(np, dt, v, f);
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
}
// system information collection for temperature, kinetic energy, potential and total energy
extern __shared__ float2 sdata[];
__global__ void compute_info_sums_kernel(unsigned int np, float4* v, float4* f, float2* scratch)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
float2 tempo;
if (i < np)
{
float4 vi = v[i];
float mass = vi.w;
tempo.x = mass * (vi.x*vi.x + vi.y*vi.y + vi.z*vi.z);
tempo.y = f[i].w;
}
else
{
tempo.x = float(0.0);
tempo.y = float(0.0);
}
sdata[threadIdx.x] = tempo;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0)
{
if (threadIdx.x < offs)
{
sdata[threadIdx.x].x += sdata[threadIdx.x + offs].x;
sdata[threadIdx.x].y += sdata[threadIdx.x + offs].y;
}
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
{
scratch[blockIdx.x].x = sdata[0].x;
scratch[blockIdx.x].y = sdata[0].y;
}
}
__global__ void compute_info_final_kernel(unsigned int np, float* info, float2* scratch, unsigned int num_partial_sums)
{
float2 final_sum = make_float2(0.0, 0.0);
for (int start = 0; start < num_partial_sums; start += blockDim.x)
{
__syncthreads();
if (start + threadIdx.x < num_partial_sums)
{
float2 scr = scratch[start + threadIdx.x];
sdata[threadIdx.x].x = scr.x;
sdata[threadIdx.x].y = scr.y;
}
else
{
sdata[threadIdx.x].x = float(0.0);
sdata[threadIdx.x].y = float(0.0);
}
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0)
{
if (threadIdx.x < offs)
{
sdata[threadIdx.x].x += sdata[threadIdx.x + offs].x;
sdata[threadIdx.x].y += sdata[threadIdx.x + offs].y;
}
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
{
final_sum.x += sdata[0].x;
final_sum.y += sdata[0].y;
}
}
if (threadIdx.x == 0)
{
float ekin = 0.5*final_sum.x;
float potential = final_sum.y;
unsigned int nfreedom = 3 * np - 3;
float temp = 2.0*ekin/float(nfreedom);
float energy = ekin + potential;
info[0] = temp;
info[1] = potential;
info[2] = energy;
}
}
void compute_info(unsigned int np, float4* v, float4* f, float2* scratch, float* info, unsigned int block_size)
{
unsigned int n_blocks = (int)ceil((float)np / (float)block_size);
dim3 grid(n_blocks, 1, 1);
dim3 threads(block_size, 1, 1);
unsigned int shared_bytes = sizeof(float2)*block_size;
compute_info_sums_kernel<<<grid,threads, shared_bytes>>>(np, v, f, scratch);
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
int final_block_size = 512;
grid = dim3(1, 1, 1);
threads = dim3(final_block_size, 1, 1);
shared_bytes = sizeof(float2)*final_block_size;
compute_info_final_kernel<<<grid, threads, shared_bytes>>>(np, info, scratch, n_blocks);
// block until the device has completed
cudaThreadSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
}
// output system information and frame in XYZ formation which can be read by VMD
void output(FILE *traj, unsigned int step, float* info, float4* r, unsigned int np)
{
float temp = info[0];
float potential = info[1];
float energy = info[2];
fprintf(traj,"%d\n step=%d temp=%20.8f pot=%20.8f ener=%20.8f\n", np, step, temp, potential, energy);
for (unsigned int i=0; i<np; i++)
{
float4 ri = r[i];
if (ri.w == 1.0)
fprintf(traj, "A %20.8f %20.8f %20.8f\n", ri.x, ri.y, ri.z);
else if (ri.w == 2.0)
fprintf(traj, "B %20.8f %20.8f %20.8f\n", ri.x, ri.y, ri.z);
}
}
// main function
int main(int argc, char **argv)
{
//running parameters
unsigned int np = 2700; // the number of particles
unsigned int nsteps = 500; // the number of time steps
float dt = 0.001; // integration time step
float rcut = 3.0; // the cutoff radius of interactions
unsigned int nprint = 100; // period for data output
unsigned int block_size = 256; // the number of threads in a block
timeval start; // start time
timeval end; // end time
float3 box =make_float3(15.0, 15.0, 15.0); // box size in x, y, and z directions
float3 epsilon = make_float3(1.0, 0.5, 1.0); // epsilon.x for type 1.0 and 1.0; epsilon.y for type 1.0 and 2.0; epsilon.z for type 1.0 and 2.0
float3 sigma = make_float3(1.0, 1.0, 1.0); // sigma.x for type 1.0 and 1.0; sigma.y for type 1.0 and 2.0; sigma.z for type 1.0 and 2.0
float min_dis = sigma.x*0.9; // the minimum distance between particles for system generation
//host memory allocation
float4* h_r = (float4 *)malloc(np*sizeof(float4)); // rx, ry, rz, type(0, 1, 2 ...)
float4* h_v = (float4 *)malloc(np*sizeof(float4)); // vx, vy, vz, mass
float4* h_f = (float4 *)malloc(np*sizeof(float4)); // fx, fy, fz, potential
float* h_info = (float *)malloc(16*sizeof(float)); // temperature, potential, energy ...
//device memory allocation
float4* d_r;
float4* d_v;
float4* d_f;
float* d_info;
float2* d_scratch;
cudaMalloc( (void **) &d_r, np*sizeof(float4) ); // rx, ry, rz, type(0, 1, 2 ...)
cudaMalloc( (void **) &d_v, np*sizeof(float4) ); // vx, vy, vz, mass
cudaMalloc( (void **) &d_f, np*sizeof(float4) ); // fx, fy, fz, potential
cudaMalloc( (void **) &d_info, 16*sizeof(float) ); // temperature, potential, energy ...
cudaMalloc( (void **) &d_scratch, (np/block_size + 1)*sizeof(float2) ); // temporary data ...
FILE *traj=fopen("traj.xyz","w"); // trajectory file in XYZ format that can be open by VMD
/* generate system information */
printf("Starting simulation with %d atoms for %d steps.\n", np, nsteps);
printf("Generating system.\n", np, nsteps);
init(np, h_r, h_v, box, min_dis);
cudaMemcpy( d_r, h_r, np*sizeof(float4), cudaMemcpyHostToDevice );
cudaMemcpy( d_v, h_v, np*sizeof(float4), cudaMemcpyHostToDevice );
gettimeofday(&start,NULL); //get start time
/* main MD loop */
printf("Running simulation.\n", np, nsteps);
for(unsigned int step =0; step <= nsteps; step++) //running simulation loop
{
/* first integration for velverlet */
first_integration(np, dt, box, d_r, d_v, d_f, block_size);
/* force calculation */
force_calculation(np, box, epsilon, sigma, d_r, d_f, rcut, block_size);
/* compute temperature and potential */
compute_info(np, d_v, d_f, d_scratch, d_info, block_size);
/* second integration for velverlet */
second_integration(np, dt, d_v, d_f, block_size);
/* write output frames and system information, if requested */
if ((step % nprint) == 0)
{
cudaMemcpy(h_r, d_r, np*sizeof(float4), cudaMemcpyDeviceToHost);
cudaMemcpy(h_info, d_info, 16*sizeof(float), cudaMemcpyDeviceToHost);
output(traj, step, h_info, h_r, np);
printf("time step %d \n", step);
}
}
gettimeofday(&end,NULL); // get end time
long timeusr=(end.tv_sec-start.tv_sec)*1000000+(end.tv_usec-start.tv_usec);
printf("time is %ld microseconds\n",timeusr); // the spending time on simulation in microseconds
fclose(traj);
free(h_r);
free(h_v);
free(h_f);
free(h_info);
cudaFree(d_r);
cudaFree(d_v);
cudaFree(d_f);
cudaFree(d_info);
return 0;
} | /* Molecular dynamics simulation linear code for binary Lennard-Jones liquid under NVE ensemble;
Author: You-Liang Zhu, Email: [email protected]
Copyright: You-Liang Zhu
This code is free: you can redistribute it and/or modify it under the terms of the GNU General Public License.*/
#include <stdio.h>
#include <string.h>
#include <ctype.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
// periodic boundary condition
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(-1);
}
}
__host__ __device__ float pbc(float x, float box_len) // implement periodic bondary condition
{
float box_half = box_len * 0.5;
if (x > box_half) x -= box_len;
else if (x < -box_half) x += box_len;
return x;
}
// randome number generator [0.0-1.0)
float R2S()
{
int ran = rand();
float fran = (float)ran/(float)RAND_MAX;
return fran;
}
// initially generate the position and mass of particles
void init(unsigned int np, float4* r, float4* v, float3 box, float min_dis)
{
for (unsigned int i=0; i<np; i++)
{
bool find_pos = false;
float4 ri;
while(!find_pos)
{
ri.x = ( R2S() - 0.5 ) * box.x;
ri.y = ( R2S() - 0.5 ) * box.y;
ri.z = ( R2S() - 0.5 ) * box.z;
find_pos = true;
for(unsigned int j=0; j<i; j++)
{
float dx = pbc(ri.x - r[j].x, box.x);
float dy = pbc(ri.y - r[j].y, box.y);
float dz = pbc(ri.z - r[j].z, box.z);
float r = sqrt(dx*dx + dy*dy + dz*dz);
if(r<min_dis) // a minimum safe distance to avoid the overlap of LJ particles
{
find_pos = false;
break;
}
}
}
if(R2S()>0.5) // randomly generate the type of particle, 1.0 represent type A and 2.0 represent type B
ri.w =1.0;
else
ri.w =2.0;
r[i] = ri;
v[i].w = 1.0;
}
}
// first step integration of velocity verlet algorithm
extern "C" __global__ void first_integration_kernel(unsigned int np, float dt, float3 box, float4* r, float4* v, float4* f)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<np)
{
float4 ri = r[i];
float mass = v[i].w;
v[i].x += 0.5 * dt * f[i].x / mass;
v[i].y += 0.5 * dt * f[i].y / mass;
v[i].z += 0.5 * dt * f[i].z / mass;
ri.x += dt * v[i].x;
ri.y += dt * v[i].y;
ri.z += dt * v[i].z;
r[i].x = pbc(ri.x, box.x);
r[i].y = pbc(ri.y, box.y);
r[i].z = pbc(ri.z, box.z);
}
}
void first_integration(unsigned int np, float dt, float3 box, float4* r, float4* v, float4* f, unsigned int block_size)
{
dim3 grid( (np/block_size) + 1, 1, 1);
dim3 block(block_size, 1, 1);
first_integration_kernel<<< grid, block >>>(np, dt, box, r, v, f);
// block until the device has completed
hipDeviceSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
}
// non-bonded force calculation
extern "C" __global__ void force_calculation_kernel(unsigned int np, float3 box, float3 epsilon, float3 sigma, float4* r, float4* f, float rcut)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<np)
{
float4 force = make_float4(0.0, 0.0, 0.0, 0.0);
for(unsigned int j=0; j<np; j++)
{
/* particles have no interactions with themselves */
if (i==j) continue;
/* calculated the shortest distance between particle i and j */
float dx = pbc(r[i].x - r[j].x, box.x);
float dy = pbc(r[i].y - r[j].y, box.y);
float dz = pbc(r[i].z - r[j].z, box.z);
float type = r[i].w + r[j].w;
float r = sqrt(dx*dx + dy*dy + dz*dz);
/* compute force and energy if within cutoff */
if (r < rcut)
{
float epsilonij, sigmaij;
if(type==2.0) // i=1.0, j=1.0
{
epsilonij = epsilon.x;
sigmaij = sigma.x;
}
else if(type==3.0) // i=1.0, j=2.0; or i=2.0, j=1.0
{
epsilonij = epsilon.y;
sigmaij = sigma.y;
}
else if(type==4.0) // i=2.0, j=2.0
{
epsilonij = epsilon.z;
sigmaij = sigma.z;
}
float ffac = -4.0*epsilonij*(-12.0*__powf(sigmaij/r,12.0)/r + 6.0*__powf(sigmaij/r,6.0)/r); // force between particle i and j
float epot = 0.5*4.0*epsilonij*(__powf(sigmaij/r,12.0) - __powf(sigmaij/r,6.0)); // potential between particle i and j
force.x += ffac*dx/r;
force.y += ffac*dy/r;
force.z += ffac*dz/r;
force.w += epot;
}
}
f[i] = force;
// printf("%d %f %f %f %f \n", i, force.x, force.y, force.z, force.w);
}
}
void force_calculation(unsigned int np, float3 box, float3 epsilon, float3 sigma, float4* r, float4* f, float rcut, unsigned int block_size)
{
dim3 grid( (np/block_size) + 1, 1, 1);
dim3 block(block_size, 1, 1);
force_calculation_kernel<<< grid, block >>>(np, box, epsilon, sigma, r, f, rcut);
// block until the device has completed
hipDeviceSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
}
// second step integration of velocity verlet algorithm
extern "C" __global__ void second_integration_kernel(unsigned int np, float dt, float4* v, float4* f)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i<np)
{
float mass = v[i].w;
v[i].x += 0.5 * dt * f[i].x / mass;
v[i].y += 0.5 * dt * f[i].y / mass;
v[i].z += 0.5 * dt * f[i].z / mass;
}
}
void second_integration(unsigned int np, float dt, float4* v, float4* f, unsigned int block_size)
{
dim3 grid( (np/block_size) + 1, 1, 1);
dim3 block(block_size, 1, 1);
second_integration_kernel<<< grid, block >>>(np, dt, v, f);
// block until the device has completed
hipDeviceSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
}
// system information collection for temperature, kinetic energy, potential and total energy
extern __shared__ float2 sdata[];
__global__ void compute_info_sums_kernel(unsigned int np, float4* v, float4* f, float2* scratch)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
float2 tempo;
if (i < np)
{
float4 vi = v[i];
float mass = vi.w;
tempo.x = mass * (vi.x*vi.x + vi.y*vi.y + vi.z*vi.z);
tempo.y = f[i].w;
}
else
{
tempo.x = float(0.0);
tempo.y = float(0.0);
}
sdata[threadIdx.x] = tempo;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0)
{
if (threadIdx.x < offs)
{
sdata[threadIdx.x].x += sdata[threadIdx.x + offs].x;
sdata[threadIdx.x].y += sdata[threadIdx.x + offs].y;
}
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
{
scratch[blockIdx.x].x = sdata[0].x;
scratch[blockIdx.x].y = sdata[0].y;
}
}
__global__ void compute_info_final_kernel(unsigned int np, float* info, float2* scratch, unsigned int num_partial_sums)
{
float2 final_sum = make_float2(0.0, 0.0);
for (int start = 0; start < num_partial_sums; start += blockDim.x)
{
__syncthreads();
if (start + threadIdx.x < num_partial_sums)
{
float2 scr = scratch[start + threadIdx.x];
sdata[threadIdx.x].x = scr.x;
sdata[threadIdx.x].y = scr.y;
}
else
{
sdata[threadIdx.x].x = float(0.0);
sdata[threadIdx.x].y = float(0.0);
}
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0)
{
if (threadIdx.x < offs)
{
sdata[threadIdx.x].x += sdata[threadIdx.x + offs].x;
sdata[threadIdx.x].y += sdata[threadIdx.x + offs].y;
}
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
{
final_sum.x += sdata[0].x;
final_sum.y += sdata[0].y;
}
}
if (threadIdx.x == 0)
{
float ekin = 0.5*final_sum.x;
float potential = final_sum.y;
unsigned int nfreedom = 3 * np - 3;
float temp = 2.0*ekin/float(nfreedom);
float energy = ekin + potential;
info[0] = temp;
info[1] = potential;
info[2] = energy;
}
}
void compute_info(unsigned int np, float4* v, float4* f, float2* scratch, float* info, unsigned int block_size)
{
unsigned int n_blocks = (int)ceil((float)np / (float)block_size);
dim3 grid(n_blocks, 1, 1);
dim3 threads(block_size, 1, 1);
unsigned int shared_bytes = sizeof(float2)*block_size;
compute_info_sums_kernel<<<grid,threads, shared_bytes>>>(np, v, f, scratch);
// block until the device has completed
hipDeviceSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
int final_block_size = 512;
grid = dim3(1, 1, 1);
threads = dim3(final_block_size, 1, 1);
shared_bytes = sizeof(float2)*final_block_size;
compute_info_final_kernel<<<grid, threads, shared_bytes>>>(np, info, scratch, n_blocks);
// block until the device has completed
hipDeviceSynchronize();
// check if kernel execution generated an error
checkCUDAError("kernel execution");
}
// output system information and frame in XYZ formation which can be read by VMD
void output(FILE *traj, unsigned int step, float* info, float4* r, unsigned int np)
{
float temp = info[0];
float potential = info[1];
float energy = info[2];
fprintf(traj,"%d\n step=%d temp=%20.8f pot=%20.8f ener=%20.8f\n", np, step, temp, potential, energy);
for (unsigned int i=0; i<np; i++)
{
float4 ri = r[i];
if (ri.w == 1.0)
fprintf(traj, "A %20.8f %20.8f %20.8f\n", ri.x, ri.y, ri.z);
else if (ri.w == 2.0)
fprintf(traj, "B %20.8f %20.8f %20.8f\n", ri.x, ri.y, ri.z);
}
}
// main function
int main(int argc, char **argv)
{
//running parameters
unsigned int np = 2700; // the number of particles
unsigned int nsteps = 500; // the number of time steps
float dt = 0.001; // integration time step
float rcut = 3.0; // the cutoff radius of interactions
unsigned int nprint = 100; // period for data output
unsigned int block_size = 256; // the number of threads in a block
timeval start; // start time
timeval end; // end time
float3 box =make_float3(15.0, 15.0, 15.0); // box size in x, y, and z directions
float3 epsilon = make_float3(1.0, 0.5, 1.0); // epsilon.x for type 1.0 and 1.0; epsilon.y for type 1.0 and 2.0; epsilon.z for type 1.0 and 2.0
float3 sigma = make_float3(1.0, 1.0, 1.0); // sigma.x for type 1.0 and 1.0; sigma.y for type 1.0 and 2.0; sigma.z for type 1.0 and 2.0
float min_dis = sigma.x*0.9; // the minimum distance between particles for system generation
//host memory allocation
float4* h_r = (float4 *)malloc(np*sizeof(float4)); // rx, ry, rz, type(0, 1, 2 ...)
float4* h_v = (float4 *)malloc(np*sizeof(float4)); // vx, vy, vz, mass
float4* h_f = (float4 *)malloc(np*sizeof(float4)); // fx, fy, fz, potential
float* h_info = (float *)malloc(16*sizeof(float)); // temperature, potential, energy ...
//device memory allocation
float4* d_r;
float4* d_v;
float4* d_f;
float* d_info;
float2* d_scratch;
hipMalloc( (void **) &d_r, np*sizeof(float4) ); // rx, ry, rz, type(0, 1, 2 ...)
hipMalloc( (void **) &d_v, np*sizeof(float4) ); // vx, vy, vz, mass
hipMalloc( (void **) &d_f, np*sizeof(float4) ); // fx, fy, fz, potential
hipMalloc( (void **) &d_info, 16*sizeof(float) ); // temperature, potential, energy ...
hipMalloc( (void **) &d_scratch, (np/block_size + 1)*sizeof(float2) ); // temporary data ...
FILE *traj=fopen("traj.xyz","w"); // trajectory file in XYZ format that can be open by VMD
/* generate system information */
printf("Starting simulation with %d atoms for %d steps.\n", np, nsteps);
printf("Generating system.\n", np, nsteps);
init(np, h_r, h_v, box, min_dis);
hipMemcpy( d_r, h_r, np*sizeof(float4), hipMemcpyHostToDevice );
hipMemcpy( d_v, h_v, np*sizeof(float4), hipMemcpyHostToDevice );
gettimeofday(&start,NULL); //get start time
/* main MD loop */
printf("Running simulation.\n", np, nsteps);
for(unsigned int step =0; step <= nsteps; step++) //running simulation loop
{
/* first integration for velverlet */
first_integration(np, dt, box, d_r, d_v, d_f, block_size);
/* force calculation */
force_calculation(np, box, epsilon, sigma, d_r, d_f, rcut, block_size);
/* compute temperature and potential */
compute_info(np, d_v, d_f, d_scratch, d_info, block_size);
/* second integration for velverlet */
second_integration(np, dt, d_v, d_f, block_size);
/* write output frames and system information, if requested */
if ((step % nprint) == 0)
{
hipMemcpy(h_r, d_r, np*sizeof(float4), hipMemcpyDeviceToHost);
hipMemcpy(h_info, d_info, 16*sizeof(float), hipMemcpyDeviceToHost);
output(traj, step, h_info, h_r, np);
printf("time step %d \n", step);
}
}
gettimeofday(&end,NULL); // get end time
long timeusr=(end.tv_sec-start.tv_sec)*1000000+(end.tv_usec-start.tv_usec);
printf("time is %ld microseconds\n",timeusr); // the spending time on simulation in microseconds
fclose(traj);
free(h_r);
free(h_v);
free(h_f);
free(h_info);
hipFree(d_r);
hipFree(d_v);
hipFree(d_f);
hipFree(d_info);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int idx = threadIdx.x;
//int iterms = sizeof(d_in);
volatile __shared__ int sdata[128];
__shared__ int tmpbin[24];// 8个线程的 bin
sdata[idx + 0] = d_in[idx + 0]; ++tmpbin[sdata[idx + 0]%BIN_COUNT + 0] ;
sdata[idx + 8] = d_in[idx + 8]; ++tmpbin[sdata[idx + 8]%BIN_COUNT + 0] ;
sdata[idx + 16] = d_in[idx + 16]; ++tmpbin[sdata[idx + 16]%BIN_COUNT + 3] ;
sdata[idx + 24] = d_in[idx + 24]; ++tmpbin[sdata[idx + 24]%BIN_COUNT + 3] ;
sdata[idx + 32] = d_in[idx + 32]; ++tmpbin[sdata[idx + 32]%BIN_COUNT + 6] ;
sdata[idx + 40] = d_in[idx + 40]; ++tmpbin[sdata[idx + 40]%BIN_COUNT + 6] ;
sdata[idx + 48] = d_in[idx + 48]; ++tmpbin[sdata[idx + 48]%BIN_COUNT + 9] ;
sdata[idx + 56] = d_in[idx + 56]; ++tmpbin[sdata[idx + 56]%BIN_COUNT + 9] ;
sdata[idx + 64] = d_in[idx + 64]; ++tmpbin[sdata[idx + 64]%BIN_COUNT + 12] ;
sdata[idx + 72] = d_in[idx + 72]; ++tmpbin[sdata[idx + 72]%BIN_COUNT + 12] ;
sdata[idx + 80] = d_in[idx + 80]; ++tmpbin[sdata[idx + 80]%BIN_COUNT + 15] ;
sdata[idx + 88] = d_in[idx + 88]; ++tmpbin[sdata[idx + 88]%BIN_COUNT + 15] ;
sdata[idx + 96] = d_in[idx + 96]; ++tmpbin[sdata[idx + 96]%BIN_COUNT + 18] ;
sdata[idx + 104] = d_in[idx + 104]; ++tmpbin[sdata[idx + 104]%BIN_COUNT + 18] ;
sdata[idx + 112] = d_in[idx + 112]; ++tmpbin[sdata[idx + 112]%BIN_COUNT + 21] ;
sdata[idx + 120] = d_in[idx + 120]; ++tmpbin[sdata[idx + 120]%BIN_COUNT + 21] ;
__syncthreads();
/*
if(idx > 1)
{
d_bins[0] += tmpbin[idx * 3 - 0];
d_bins[1] += tmpbin[idx * 3 - 2];
d_bins[2] += tmpbin[idx * 3 - 1];
}
if(idx == 0) d_bins[0] + tmpbin[0];
*/
for(int i = 0;i < 24; ++i)
{
d_bins[0] += tmpbin[i%3];
d_bins[1] += tmpbin[i%3];
d_bins[2] += tmpbin[i%3];
}
}
__global__ void simple_histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int myId = threadIdx.x;
int myItem = d_in[myId];
int myBin = myItem % BIN_COUNT;
atomicAdd(&(d_bins[myBin]), 1);//原子锁
}
int main(int argc, char **argv)
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
cudaSetDevice(dev);
cudaDeviceProp devProps;
if (cudaGetDeviceProperties(&devProps, dev) == 0)
{
printf("Using device %d:\n", dev);
printf("%s; global mem: %dB; compute v%d.%d; clock: %d kHz\n",
devProps.name, (int)devProps.totalGlobalMem,
(int)devProps.major, (int)devProps.minor,
(int)devProps.clockRate);
}
const int ARRAY_SIZE = 128;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
const int BIN_COUNT = 3;
const int BIN_BYTES = BIN_COUNT * sizeof(int);
// generate the input array on the host 0~127
int h_in[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = i;
}
int h_bins[BIN_COUNT];
for(int i = 0; i < BIN_COUNT; i++) {
h_bins[i] = 0;
}
// declare GPU memory pointers
int * d_in;
int * d_bins;
// allocate GPU memory
cudaMalloc((void **) &d_in, ARRAY_BYTES);
cudaMalloc((void **) &d_bins, BIN_BYTES);
// transfer the arrays to the GPU
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_bins, h_bins, BIN_BYTES, cudaMemcpyHostToDevice);
histo<<<1, ARRAY_SIZE/16>>>(d_bins, d_in, BIN_COUNT);
//simple_histo<<<1, 128>>>(d_bins, d_in, BIN_COUNT);
// copy back the sum from GPU
cudaMemcpy(h_bins, d_bins, BIN_BYTES, cudaMemcpyDeviceToHost);
for(int i = 0; i < BIN_COUNT; i++) {
printf("bin %d: count %d\n", i, h_bins[i]);
}
// free GPU memory allocation
cudaFree(d_in);
cudaFree(d_bins);
return 0;
} | .file "tmpxft_001b94f5_00000000-6_histo1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5histoPiPKiiPiPKii
.type _Z28__device_stub__Z5histoPiPKiiPiPKii, @function
_Z28__device_stub__Z5histoPiPKiiPiPKii:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5histoPiPKii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z5histoPiPKiiPiPKii, .-_Z28__device_stub__Z5histoPiPKiiPiPKii
.globl _Z5histoPiPKii
.type _Z5histoPiPKii, @function
_Z5histoPiPKii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5histoPiPKiiPiPKii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5histoPiPKii, .-_Z5histoPiPKii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "error: no devices supporting CUDA.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Using device %d:\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "%s; global mem: %dB; compute v%d.%d; clock: %d kHz\n"
.section .rodata.str1.1
.LC3:
.string "bin %d: count %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1624, %rsp
.cfi_def_cfa_offset 1648
movq %fs:40, %rax
movq %rax, 1608(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 4(%rsp)
je .L21
movl $0, %edi
call cudaSetDevice@PLT
leaq 576(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
je .L22
.L13:
movl $0, %eax
.L14:
movl %eax, 64(%rsp,%rax,4)
addq $1, %rax
cmpq $128, %rax
jne .L14
movl $0, 52(%rsp)
movl $0, 56(%rsp)
movl $0, 60(%rsp)
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $512, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 52(%rsp), %rsi
movl $1, %ecx
movl $12, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
leaq 52(%rsp), %rdi
movl $2, %ecx
movl $12, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC3(%rip), %rbp
.L16:
movl 52(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L16
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 1608(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $1624, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L22:
movl $0, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 576(%rsp), %rdx
subq $8, %rsp
.cfi_def_cfa_offset 1656
movl 932(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 1664
movl 956(%rsp), %r9d
movl 952(%rsp), %r8d
movl 880(%rsp), %ecx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1648
jmp .L13
.L23:
movl $3, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z28__device_stub__Z5histoPiPKiiPiPKii
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z36__device_stub__Z12simple_histoPiPKiiPiPKii
.type _Z36__device_stub__Z12simple_histoPiPKiiPiPKii, @function
_Z36__device_stub__Z12simple_histoPiPKiiPiPKii:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12simple_histoPiPKii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z12simple_histoPiPKiiPiPKii, .-_Z36__device_stub__Z12simple_histoPiPKiiPiPKii
.globl _Z12simple_histoPiPKii
.type _Z12simple_histoPiPKii, @function
_Z12simple_histoPiPKii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12simple_histoPiPKiiPiPKii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12simple_histoPiPKii, .-_Z12simple_histoPiPKii
.section .rodata.str1.1
.LC4:
.string "_Z12simple_histoPiPKii"
.LC5:
.string "_Z5histoPiPKii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12simple_histoPiPKii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z5histoPiPKii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int idx = threadIdx.x;
//int iterms = sizeof(d_in);
volatile __shared__ int sdata[128];
__shared__ int tmpbin[24];// 8个线程的 bin
sdata[idx + 0] = d_in[idx + 0]; ++tmpbin[sdata[idx + 0]%BIN_COUNT + 0] ;
sdata[idx + 8] = d_in[idx + 8]; ++tmpbin[sdata[idx + 8]%BIN_COUNT + 0] ;
sdata[idx + 16] = d_in[idx + 16]; ++tmpbin[sdata[idx + 16]%BIN_COUNT + 3] ;
sdata[idx + 24] = d_in[idx + 24]; ++tmpbin[sdata[idx + 24]%BIN_COUNT + 3] ;
sdata[idx + 32] = d_in[idx + 32]; ++tmpbin[sdata[idx + 32]%BIN_COUNT + 6] ;
sdata[idx + 40] = d_in[idx + 40]; ++tmpbin[sdata[idx + 40]%BIN_COUNT + 6] ;
sdata[idx + 48] = d_in[idx + 48]; ++tmpbin[sdata[idx + 48]%BIN_COUNT + 9] ;
sdata[idx + 56] = d_in[idx + 56]; ++tmpbin[sdata[idx + 56]%BIN_COUNT + 9] ;
sdata[idx + 64] = d_in[idx + 64]; ++tmpbin[sdata[idx + 64]%BIN_COUNT + 12] ;
sdata[idx + 72] = d_in[idx + 72]; ++tmpbin[sdata[idx + 72]%BIN_COUNT + 12] ;
sdata[idx + 80] = d_in[idx + 80]; ++tmpbin[sdata[idx + 80]%BIN_COUNT + 15] ;
sdata[idx + 88] = d_in[idx + 88]; ++tmpbin[sdata[idx + 88]%BIN_COUNT + 15] ;
sdata[idx + 96] = d_in[idx + 96]; ++tmpbin[sdata[idx + 96]%BIN_COUNT + 18] ;
sdata[idx + 104] = d_in[idx + 104]; ++tmpbin[sdata[idx + 104]%BIN_COUNT + 18] ;
sdata[idx + 112] = d_in[idx + 112]; ++tmpbin[sdata[idx + 112]%BIN_COUNT + 21] ;
sdata[idx + 120] = d_in[idx + 120]; ++tmpbin[sdata[idx + 120]%BIN_COUNT + 21] ;
__syncthreads();
/*
if(idx > 1)
{
d_bins[0] += tmpbin[idx * 3 - 0];
d_bins[1] += tmpbin[idx * 3 - 2];
d_bins[2] += tmpbin[idx * 3 - 1];
}
if(idx == 0) d_bins[0] + tmpbin[0];
*/
for(int i = 0;i < 24; ++i)
{
d_bins[0] += tmpbin[i%3];
d_bins[1] += tmpbin[i%3];
d_bins[2] += tmpbin[i%3];
}
}
__global__ void simple_histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int myId = threadIdx.x;
int myItem = d_in[myId];
int myBin = myItem % BIN_COUNT;
atomicAdd(&(d_bins[myBin]), 1);//原子锁
}
int main(int argc, char **argv)
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
cudaSetDevice(dev);
cudaDeviceProp devProps;
if (cudaGetDeviceProperties(&devProps, dev) == 0)
{
printf("Using device %d:\n", dev);
printf("%s; global mem: %dB; compute v%d.%d; clock: %d kHz\n",
devProps.name, (int)devProps.totalGlobalMem,
(int)devProps.major, (int)devProps.minor,
(int)devProps.clockRate);
}
const int ARRAY_SIZE = 128;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
const int BIN_COUNT = 3;
const int BIN_BYTES = BIN_COUNT * sizeof(int);
// generate the input array on the host 0~127
int h_in[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = i;
}
int h_bins[BIN_COUNT];
for(int i = 0; i < BIN_COUNT; i++) {
h_bins[i] = 0;
}
// declare GPU memory pointers
int * d_in;
int * d_bins;
// allocate GPU memory
cudaMalloc((void **) &d_in, ARRAY_BYTES);
cudaMalloc((void **) &d_bins, BIN_BYTES);
// transfer the arrays to the GPU
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_bins, h_bins, BIN_BYTES, cudaMemcpyHostToDevice);
histo<<<1, ARRAY_SIZE/16>>>(d_bins, d_in, BIN_COUNT);
//simple_histo<<<1, 128>>>(d_bins, d_in, BIN_COUNT);
// copy back the sum from GPU
cudaMemcpy(h_bins, d_bins, BIN_BYTES, cudaMemcpyDeviceToHost);
for(int i = 0; i < BIN_COUNT; i++) {
printf("bin %d: count %d\n", i, h_bins[i]);
}
// free GPU memory allocation
cudaFree(d_in);
cudaFree(d_bins);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int idx = threadIdx.x;
//int iterms = sizeof(d_in);
volatile __shared__ int sdata[128];
__shared__ int tmpbin[24];// 8个线程的 bin
sdata[idx + 0] = d_in[idx + 0]; ++tmpbin[sdata[idx + 0]%BIN_COUNT + 0] ;
sdata[idx + 8] = d_in[idx + 8]; ++tmpbin[sdata[idx + 8]%BIN_COUNT + 0] ;
sdata[idx + 16] = d_in[idx + 16]; ++tmpbin[sdata[idx + 16]%BIN_COUNT + 3] ;
sdata[idx + 24] = d_in[idx + 24]; ++tmpbin[sdata[idx + 24]%BIN_COUNT + 3] ;
sdata[idx + 32] = d_in[idx + 32]; ++tmpbin[sdata[idx + 32]%BIN_COUNT + 6] ;
sdata[idx + 40] = d_in[idx + 40]; ++tmpbin[sdata[idx + 40]%BIN_COUNT + 6] ;
sdata[idx + 48] = d_in[idx + 48]; ++tmpbin[sdata[idx + 48]%BIN_COUNT + 9] ;
sdata[idx + 56] = d_in[idx + 56]; ++tmpbin[sdata[idx + 56]%BIN_COUNT + 9] ;
sdata[idx + 64] = d_in[idx + 64]; ++tmpbin[sdata[idx + 64]%BIN_COUNT + 12] ;
sdata[idx + 72] = d_in[idx + 72]; ++tmpbin[sdata[idx + 72]%BIN_COUNT + 12] ;
sdata[idx + 80] = d_in[idx + 80]; ++tmpbin[sdata[idx + 80]%BIN_COUNT + 15] ;
sdata[idx + 88] = d_in[idx + 88]; ++tmpbin[sdata[idx + 88]%BIN_COUNT + 15] ;
sdata[idx + 96] = d_in[idx + 96]; ++tmpbin[sdata[idx + 96]%BIN_COUNT + 18] ;
sdata[idx + 104] = d_in[idx + 104]; ++tmpbin[sdata[idx + 104]%BIN_COUNT + 18] ;
sdata[idx + 112] = d_in[idx + 112]; ++tmpbin[sdata[idx + 112]%BIN_COUNT + 21] ;
sdata[idx + 120] = d_in[idx + 120]; ++tmpbin[sdata[idx + 120]%BIN_COUNT + 21] ;
__syncthreads();
/*
if(idx > 1)
{
d_bins[0] += tmpbin[idx * 3 - 0];
d_bins[1] += tmpbin[idx * 3 - 2];
d_bins[2] += tmpbin[idx * 3 - 1];
}
if(idx == 0) d_bins[0] + tmpbin[0];
*/
for(int i = 0;i < 24; ++i)
{
d_bins[0] += tmpbin[i%3];
d_bins[1] += tmpbin[i%3];
d_bins[2] += tmpbin[i%3];
}
}
__global__ void simple_histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int myId = threadIdx.x;
int myItem = d_in[myId];
int myBin = myItem % BIN_COUNT;
atomicAdd(&(d_bins[myBin]), 1);//原子锁
}
int main(int argc, char **argv)
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
hipSetDevice(dev);
hipDeviceProp_t devProps;
if (hipGetDeviceProperties(&devProps, dev) == 0)
{
printf("Using device %d:\n", dev);
printf("%s; global mem: %dB; compute v%d.%d; clock: %d kHz\n",
devProps.name, (int)devProps.totalGlobalMem,
(int)devProps.major, (int)devProps.minor,
(int)devProps.clockRate);
}
const int ARRAY_SIZE = 128;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
const int BIN_COUNT = 3;
const int BIN_BYTES = BIN_COUNT * sizeof(int);
// generate the input array on the host 0~127
int h_in[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = i;
}
int h_bins[BIN_COUNT];
for(int i = 0; i < BIN_COUNT; i++) {
h_bins[i] = 0;
}
// declare GPU memory pointers
int * d_in;
int * d_bins;
// allocate GPU memory
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_bins, BIN_BYTES);
// transfer the arrays to the GPU
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_bins, h_bins, BIN_BYTES, hipMemcpyHostToDevice);
histo<<<1, ARRAY_SIZE/16>>>(d_bins, d_in, BIN_COUNT);
//simple_histo<<<1, 128>>>(d_bins, d_in, BIN_COUNT);
// copy back the sum from GPU
hipMemcpy(h_bins, d_bins, BIN_BYTES, hipMemcpyDeviceToHost);
for(int i = 0; i < BIN_COUNT; i++) {
printf("bin %d: count %d\n", i, h_bins[i]);
}
// free GPU memory allocation
hipFree(d_in);
hipFree(d_bins);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int idx = threadIdx.x;
//int iterms = sizeof(d_in);
volatile __shared__ int sdata[128];
__shared__ int tmpbin[24];// 8个线程的 bin
sdata[idx + 0] = d_in[idx + 0]; ++tmpbin[sdata[idx + 0]%BIN_COUNT + 0] ;
sdata[idx + 8] = d_in[idx + 8]; ++tmpbin[sdata[idx + 8]%BIN_COUNT + 0] ;
sdata[idx + 16] = d_in[idx + 16]; ++tmpbin[sdata[idx + 16]%BIN_COUNT + 3] ;
sdata[idx + 24] = d_in[idx + 24]; ++tmpbin[sdata[idx + 24]%BIN_COUNT + 3] ;
sdata[idx + 32] = d_in[idx + 32]; ++tmpbin[sdata[idx + 32]%BIN_COUNT + 6] ;
sdata[idx + 40] = d_in[idx + 40]; ++tmpbin[sdata[idx + 40]%BIN_COUNT + 6] ;
sdata[idx + 48] = d_in[idx + 48]; ++tmpbin[sdata[idx + 48]%BIN_COUNT + 9] ;
sdata[idx + 56] = d_in[idx + 56]; ++tmpbin[sdata[idx + 56]%BIN_COUNT + 9] ;
sdata[idx + 64] = d_in[idx + 64]; ++tmpbin[sdata[idx + 64]%BIN_COUNT + 12] ;
sdata[idx + 72] = d_in[idx + 72]; ++tmpbin[sdata[idx + 72]%BIN_COUNT + 12] ;
sdata[idx + 80] = d_in[idx + 80]; ++tmpbin[sdata[idx + 80]%BIN_COUNT + 15] ;
sdata[idx + 88] = d_in[idx + 88]; ++tmpbin[sdata[idx + 88]%BIN_COUNT + 15] ;
sdata[idx + 96] = d_in[idx + 96]; ++tmpbin[sdata[idx + 96]%BIN_COUNT + 18] ;
sdata[idx + 104] = d_in[idx + 104]; ++tmpbin[sdata[idx + 104]%BIN_COUNT + 18] ;
sdata[idx + 112] = d_in[idx + 112]; ++tmpbin[sdata[idx + 112]%BIN_COUNT + 21] ;
sdata[idx + 120] = d_in[idx + 120]; ++tmpbin[sdata[idx + 120]%BIN_COUNT + 21] ;
__syncthreads();
/*
if(idx > 1)
{
d_bins[0] += tmpbin[idx * 3 - 0];
d_bins[1] += tmpbin[idx * 3 - 2];
d_bins[2] += tmpbin[idx * 3 - 1];
}
if(idx == 0) d_bins[0] + tmpbin[0];
*/
for(int i = 0;i < 24; ++i)
{
d_bins[0] += tmpbin[i%3];
d_bins[1] += tmpbin[i%3];
d_bins[2] += tmpbin[i%3];
}
}
__global__ void simple_histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int myId = threadIdx.x;
int myItem = d_in[myId];
int myBin = myItem % BIN_COUNT;
atomicAdd(&(d_bins[myBin]), 1);//原子锁
}
int main(int argc, char **argv)
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
hipSetDevice(dev);
hipDeviceProp_t devProps;
if (hipGetDeviceProperties(&devProps, dev) == 0)
{
printf("Using device %d:\n", dev);
printf("%s; global mem: %dB; compute v%d.%d; clock: %d kHz\n",
devProps.name, (int)devProps.totalGlobalMem,
(int)devProps.major, (int)devProps.minor,
(int)devProps.clockRate);
}
const int ARRAY_SIZE = 128;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
const int BIN_COUNT = 3;
const int BIN_BYTES = BIN_COUNT * sizeof(int);
// generate the input array on the host 0~127
int h_in[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = i;
}
int h_bins[BIN_COUNT];
for(int i = 0; i < BIN_COUNT; i++) {
h_bins[i] = 0;
}
// declare GPU memory pointers
int * d_in;
int * d_bins;
// allocate GPU memory
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_bins, BIN_BYTES);
// transfer the arrays to the GPU
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_bins, h_bins, BIN_BYTES, hipMemcpyHostToDevice);
histo<<<1, ARRAY_SIZE/16>>>(d_bins, d_in, BIN_COUNT);
//simple_histo<<<1, 128>>>(d_bins, d_in, BIN_COUNT);
// copy back the sum from GPU
hipMemcpy(h_bins, d_bins, BIN_BYTES, hipMemcpyDeviceToHost);
for(int i = 0; i < BIN_COUNT; i++) {
printf("bin %d: count %d\n", i, h_bins[i]);
}
// free GPU memory allocation
hipFree(d_in);
hipFree(d_bins);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5histoPiPKii
.globl _Z5histoPiPKii
.p2align 8
.type _Z5histoPiPKii,@function
_Z5histoPiPKii:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_mov_b64 s[0:1], src_shared_base
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, -1, v0
v_cndmask_b32_e32 v1, 0, v0, vcc_lo
v_cndmask_b32_e64 v2, 0, s1, vcc_lo
s_waitcnt lgkmcnt(0)
global_load_b32 v3, v0, s[6:7]
s_ashr_i32 s0, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s0
s_xor_b32 s0, s2, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s2, 0, s0
s_waitcnt vmcnt(0)
flat_store_b32 v[1:2], v3 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v1, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_cvt_f32_u32_e32 v3, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, s2, v3
v_mul_hi_u32 v5, v3, v5
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v6, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v7, v1, v6
v_add_nc_u32_e32 v1, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v7, v6
v_mul_hi_u32 v5, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s0
v_sub_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s0, v3
v_cmp_le_u32_e32 vcc_lo, s0, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_add_nc_u32 v2, 32, v0
global_load_b32 v4, v2, s[6:7]
v_subrev_nc_u32_e32 v5, s0, v3
v_cmp_le_u32_e32 vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v2
v_xor_b32_e32 v3, v3, v6
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v6
v_lshlrev_b32_e32 v5, 2, v3
ds_load_b32 v3, v5 offset:512
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v3
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_store_b32 v5, v6 offset:512
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v2, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 64, v0
global_load_b32 v4, v3, s[6:7]
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v1
v_mul_lo_u32 v6, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_dual_cndmask_b32 v2, 0, v3 :: v_dual_lshlrev_b32 v5, 2, v2
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_load_b32 v6, v5 offset:512
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v6
ds_store_b32 v5, v6 offset:512
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v2, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 0x60, v0
global_load_b32 v4, v3, s[6:7]
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v1
v_mul_lo_u32 v6, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_dual_cndmask_b32 v2, 0, v3 :: v_dual_lshlrev_b32 v5, 2, v2
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_load_b32 v6, v5 offset:524
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v6
ds_store_b32 v5, v6 offset:524
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v2, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v1
v_mul_lo_u32 v6, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v3, 0x80, v0
global_load_b32 v4, v3, s[6:7]
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_xor_b32_e32 v2, v2, v5
v_sub_nc_u32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v2, 0, v3 :: v_dual_lshlrev_b32 v5, 2, v2
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_load_b32 v6, v5 offset:524
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v6
ds_store_b32 v5, v6 offset:524
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v2, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v1
v_mul_lo_u32 v6, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v3, 0xa0, v0
global_load_b32 v4, v3, s[6:7]
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v5
v_sub_nc_u32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v2, 0, v3 :: v_dual_lshlrev_b32 v5, 2, v2
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_load_b32 v6, v5 offset:536
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v6
ds_store_b32 v5, v6 offset:536
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v2, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 0xc0, v0
global_load_b32 v4, v3, s[6:7]
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v1
v_mul_lo_u32 v6, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_dual_cndmask_b32 v2, 0, v3 :: v_dual_lshlrev_b32 v5, 2, v2
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_load_b32 v6, v5 offset:536
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v6
ds_store_b32 v5, v6 offset:536
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v2, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 0xe0, v0
global_load_b32 v4, v3, s[6:7]
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v1
v_mul_lo_u32 v6, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_dual_cndmask_b32 v2, 0, v3 :: v_dual_lshlrev_b32 v5, 2, v2
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_load_b32 v6, v5 offset:548
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v6
ds_store_b32 v5, v6 offset:548
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v2, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 0x100, v0
global_load_b32 v4, v3, s[6:7]
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v1
v_mul_lo_u32 v6, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_dual_cndmask_b32 v2, 0, v3 :: v_dual_lshlrev_b32 v5, 2, v2
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_load_b32 v6, v5 offset:548
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v6
ds_store_b32 v5, v6 offset:548
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v2, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 0x120, v0
global_load_b32 v4, v3, s[6:7]
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v1
v_mul_lo_u32 v6, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_dual_cndmask_b32 v2, 0, v3 :: v_dual_lshlrev_b32 v5, 2, v2
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_load_b32 v6, v5 offset:560
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v6
ds_store_b32 v5, v6 offset:560
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v2, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 0x140, v0
global_load_b32 v4, v3, s[6:7]
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v1
v_mul_lo_u32 v6, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_dual_cndmask_b32 v2, 0, v3 :: v_dual_lshlrev_b32 v5, 2, v2
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_load_b32 v6, v5 offset:560
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v6
ds_store_b32 v5, v6 offset:560
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v2, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 0x160, v0
global_load_b32 v4, v3, s[6:7]
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v1
v_mul_lo_u32 v6, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_dual_cndmask_b32 v2, 0, v3 :: v_dual_lshlrev_b32 v5, 2, v2
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_load_b32 v6, v5 offset:572
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v6
ds_store_b32 v5, v6 offset:572
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v2, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 0x180, v0
global_load_b32 v4, v3, s[6:7]
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v1
v_mul_lo_u32 v6, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_dual_cndmask_b32 v2, 0, v3 :: v_dual_lshlrev_b32 v5, 2, v2
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_load_b32 v6, v5 offset:572
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v6
ds_store_b32 v5, v6 offset:572
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v2, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 0x1a0, v0
global_load_b32 v4, v3, s[6:7]
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v1
v_mul_lo_u32 v6, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_dual_cndmask_b32 v2, 0, v3 :: v_dual_lshlrev_b32 v5, 2, v2
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_load_b32 v6, v5 offset:584
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v6
ds_store_b32 v5, v6 offset:584
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v2, v[2:3] glc dlc
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, 0x1c0, v0
v_add_nc_u32_e32 v0, 0x1e0, v0
global_load_b32 v4, v3, s[6:7]
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v5
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v1
v_mul_lo_u32 v6, v6, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v3
v_xor_b32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_dual_cndmask_b32 v2, 0, v3 :: v_dual_lshlrev_b32 v5, 2, v2
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_load_b32 v6, v5 offset:584
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v6, 1, v6
ds_store_b32 v5, v6 offset:584
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v2, v[2:3] glc dlc
s_waitcnt vmcnt(0)
global_load_b32 v4, v0, s[6:7]
s_waitcnt lgkmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v3
v_xor_b32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v2, v1
v_mul_lo_u32 v5, v5, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_subrev_nc_u32_e32 v5, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_subrev_nc_u32_e32 v5, s0, v2
v_cmp_le_u32_e32 vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v0
v_xor_b32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v3
v_dual_cndmask_b32 v2, 0, v0 :: v_dual_lshlrev_b32 v5, 2, v2
ds_load_b32 v3, v5 offset:596
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, 1, v3
v_cndmask_b32_e64 v3, 0, s1, vcc_lo
ds_store_b32 v5, v0 offset:596
s_waitcnt vmcnt(0)
flat_store_b32 v[2:3], v4 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v0, v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_ashrrev_i32_e32 v2, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_mul_lo_u32 v1, v1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v1
v_subrev_nc_u32_e32 v1, s0, v0
v_cmp_le_u32_e32 vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
v_subrev_nc_u32_e32 v1, s0, v0
v_cmp_le_u32_e32 vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_lshlrev_b32_e32 v0, 2, v0
ds_load_b32 v1, v0 offset:596
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, 1, v1
ds_store_b32 v0, v1 offset:596
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s2, s[4:5], 0x8
s_load_b64 s[0:1], s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s1
v_mov_b32_e32 v0, s0
s_mov_b32 s0, 0
s_mov_b32 s1, 24
s_movk_i32 s2, 0x200
.LBB0_1:
s_mul_hi_u32 s3, s0, 0xaaaaaaab
s_add_i32 s1, s1, -1
s_lshr_b32 s3, s3, 1
s_add_i32 s0, s0, 1
s_mul_i32 s3, s3, -12
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s3, s2, s3
s_add_i32 s2, s2, 4
v_mov_b32_e32 v3, s3
s_cmp_eq_u32 s1, 0
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v0, v3
v_add_nc_u32_e32 v1, v1, v3
v_add_nc_u32_e32 v2, v2, v3
s_cbranch_scc0 .LBB0_1
v_mov_b32_e32 v3, 0
global_store_b96 v3, v[0:2], s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5histoPiPKii
.amdhsa_group_segment_fixed_size 608
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5histoPiPKii, .Lfunc_end0-_Z5histoPiPKii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12simple_histoPiPKii
.globl _Z12simple_histoPiPKii
.p2align 8
.type _Z12simple_histoPiPKii,@function
_Z12simple_histoPiPKii:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s1
s_xor_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s0
s_sub_i32 s1, 0, s0
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_lshlrev_b32 v0, 2, v0
global_load_b32 v0, v0, s[6:7]
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s1, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_mov_b32 v2, 1 :: v_dual_add_nc_u32 v1, v1, v2
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v0
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s0
v_sub_nc_u32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s0, v0
v_cmp_le_u32_e32 vcc_lo, s0, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s0, v0
v_cmp_le_u32_e32 vcc_lo, s0, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12simple_histoPiPKii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12simple_histoPiPKii, .Lfunc_end1-_Z12simple_histoPiPKii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 608
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5histoPiPKii
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z5histoPiPKii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12simple_histoPiPKii
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z12simple_histoPiPKii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int idx = threadIdx.x;
//int iterms = sizeof(d_in);
volatile __shared__ int sdata[128];
__shared__ int tmpbin[24];// 8个线程的 bin
sdata[idx + 0] = d_in[idx + 0]; ++tmpbin[sdata[idx + 0]%BIN_COUNT + 0] ;
sdata[idx + 8] = d_in[idx + 8]; ++tmpbin[sdata[idx + 8]%BIN_COUNT + 0] ;
sdata[idx + 16] = d_in[idx + 16]; ++tmpbin[sdata[idx + 16]%BIN_COUNT + 3] ;
sdata[idx + 24] = d_in[idx + 24]; ++tmpbin[sdata[idx + 24]%BIN_COUNT + 3] ;
sdata[idx + 32] = d_in[idx + 32]; ++tmpbin[sdata[idx + 32]%BIN_COUNT + 6] ;
sdata[idx + 40] = d_in[idx + 40]; ++tmpbin[sdata[idx + 40]%BIN_COUNT + 6] ;
sdata[idx + 48] = d_in[idx + 48]; ++tmpbin[sdata[idx + 48]%BIN_COUNT + 9] ;
sdata[idx + 56] = d_in[idx + 56]; ++tmpbin[sdata[idx + 56]%BIN_COUNT + 9] ;
sdata[idx + 64] = d_in[idx + 64]; ++tmpbin[sdata[idx + 64]%BIN_COUNT + 12] ;
sdata[idx + 72] = d_in[idx + 72]; ++tmpbin[sdata[idx + 72]%BIN_COUNT + 12] ;
sdata[idx + 80] = d_in[idx + 80]; ++tmpbin[sdata[idx + 80]%BIN_COUNT + 15] ;
sdata[idx + 88] = d_in[idx + 88]; ++tmpbin[sdata[idx + 88]%BIN_COUNT + 15] ;
sdata[idx + 96] = d_in[idx + 96]; ++tmpbin[sdata[idx + 96]%BIN_COUNT + 18] ;
sdata[idx + 104] = d_in[idx + 104]; ++tmpbin[sdata[idx + 104]%BIN_COUNT + 18] ;
sdata[idx + 112] = d_in[idx + 112]; ++tmpbin[sdata[idx + 112]%BIN_COUNT + 21] ;
sdata[idx + 120] = d_in[idx + 120]; ++tmpbin[sdata[idx + 120]%BIN_COUNT + 21] ;
__syncthreads();
/*
if(idx > 1)
{
d_bins[0] += tmpbin[idx * 3 - 0];
d_bins[1] += tmpbin[idx * 3 - 2];
d_bins[2] += tmpbin[idx * 3 - 1];
}
if(idx == 0) d_bins[0] + tmpbin[0];
*/
for(int i = 0;i < 24; ++i)
{
d_bins[0] += tmpbin[i%3];
d_bins[1] += tmpbin[i%3];
d_bins[2] += tmpbin[i%3];
}
}
__global__ void simple_histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
int myId = threadIdx.x;
int myItem = d_in[myId];
int myBin = myItem % BIN_COUNT;
atomicAdd(&(d_bins[myBin]), 1);//原子锁
}
int main(int argc, char **argv)
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
hipSetDevice(dev);
hipDeviceProp_t devProps;
if (hipGetDeviceProperties(&devProps, dev) == 0)
{
printf("Using device %d:\n", dev);
printf("%s; global mem: %dB; compute v%d.%d; clock: %d kHz\n",
devProps.name, (int)devProps.totalGlobalMem,
(int)devProps.major, (int)devProps.minor,
(int)devProps.clockRate);
}
const int ARRAY_SIZE = 128;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
const int BIN_COUNT = 3;
const int BIN_BYTES = BIN_COUNT * sizeof(int);
// generate the input array on the host 0~127
int h_in[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = i;
}
int h_bins[BIN_COUNT];
for(int i = 0; i < BIN_COUNT; i++) {
h_bins[i] = 0;
}
// declare GPU memory pointers
int * d_in;
int * d_bins;
// allocate GPU memory
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_bins, BIN_BYTES);
// transfer the arrays to the GPU
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_bins, h_bins, BIN_BYTES, hipMemcpyHostToDevice);
histo<<<1, ARRAY_SIZE/16>>>(d_bins, d_in, BIN_COUNT);
//simple_histo<<<1, 128>>>(d_bins, d_in, BIN_COUNT);
// copy back the sum from GPU
hipMemcpy(h_bins, d_bins, BIN_BYTES, hipMemcpyDeviceToHost);
for(int i = 0; i < BIN_COUNT; i++) {
printf("bin %d: count %d\n", i, h_bins[i]);
}
// free GPU memory allocation
hipFree(d_in);
hipFree(d_bins);
return 0;
} | .text
.file "histo1.hip"
.globl _Z20__device_stub__histoPiPKii # -- Begin function _Z20__device_stub__histoPiPKii
.p2align 4, 0x90
.type _Z20__device_stub__histoPiPKii,@function
_Z20__device_stub__histoPiPKii: # @_Z20__device_stub__histoPiPKii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5histoPiPKii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z20__device_stub__histoPiPKii, .Lfunc_end0-_Z20__device_stub__histoPiPKii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__simple_histoPiPKii # -- Begin function _Z27__device_stub__simple_histoPiPKii
.p2align 4, 0x90
.type _Z27__device_stub__simple_histoPiPKii,@function
_Z27__device_stub__simple_histoPiPKii: # @_Z27__device_stub__simple_histoPiPKii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12simple_histoPiPKii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z27__device_stub__simple_histoPiPKii, .Lfunc_end1-_Z27__device_stub__simple_histoPiPKii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $2128, %rsp # imm = 0x850
.cfi_def_cfa_offset 2144
.cfi_offset %rbx, -16
leaq 24(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 24(%rsp)
je .LBB2_10
# %bb.1:
xorl %edi, %edi
callq hipSetDevice
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movl $.L.str.1, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
movl 504(%rsp), %ecx
movl 508(%rsp), %r8d
movl 432(%rsp), %edx
movl 492(%rsp), %r9d
leaq 144(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.LBB2_3:
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_4: # =>This Inner Loop Header: Depth=1
movl %eax, 1616(%rsp,%rax,4)
incq %rax
cmpq $128, %rax
jne .LBB2_4
# %bb.5:
movl $0, 40(%rsp)
movq $0, 32(%rsp)
leaq 16(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 8(%rsp), %rdi
movl $12, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 1616(%rsp), %rsi
movl $512, %edx # imm = 0x200
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $12, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl $3, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5histoPiPKii, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $12, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_8: # =>This Inner Loop Header: Depth=1
movl 32(%rsp,%rbx,4), %edx
movl $.L.str.3, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $3, %rbx
jne .LBB2_8
# %bb.9:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $2128, %rsp # imm = 0x850
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_10:
.cfi_def_cfa_offset 2144
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $35, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5histoPiPKii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12simple_histoPiPKii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5histoPiPKii,@object # @_Z5histoPiPKii
.section .rodata,"a",@progbits
.globl _Z5histoPiPKii
.p2align 3, 0x0
_Z5histoPiPKii:
.quad _Z20__device_stub__histoPiPKii
.size _Z5histoPiPKii, 8
.type _Z12simple_histoPiPKii,@object # @_Z12simple_histoPiPKii
.globl _Z12simple_histoPiPKii
.p2align 3, 0x0
_Z12simple_histoPiPKii:
.quad _Z27__device_stub__simple_histoPiPKii
.size _Z12simple_histoPiPKii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error: no devices supporting CUDA.\n"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Using device %d:\n"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s
.size .L.str.2, 52
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "bin %d: count %d\n"
.size .L.str.3, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5histoPiPKii"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12simple_histoPiPKii"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__histoPiPKii
.addrsig_sym _Z27__device_stub__simple_histoPiPKii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5histoPiPKii
.addrsig_sym _Z12simple_histoPiPKii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
Subsets and Splits