system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
55.5k
|
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You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ __forceinline__ float sigmoid(float a) {
return 1.0 / (1.0 + exp (-a));
}
__global__ void sigmoid_kernel(float *vec, int len) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < len) {
vec[index] = sigmoid(vec[index]);
}
} | .text
.file "sigmoid_kernel.hip"
.globl _Z29__device_stub__sigmoid_kernelPfi # -- Begin function _Z29__device_stub__sigmoid_kernelPfi
.p2align 4, 0x90
.type _Z29__device_stub__sigmoid_kernelPfi,@function
_Z29__device_stub__sigmoid_kernelPfi: # @_Z29__device_stub__sigmoid_kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14sigmoid_kernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__sigmoid_kernelPfi, .Lfunc_end0-_Z29__device_stub__sigmoid_kernelPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sigmoid_kernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sigmoid_kernelPfi,@object # @_Z14sigmoid_kernelPfi
.section .rodata,"a",@progbits
.globl _Z14sigmoid_kernelPfi
.p2align 3, 0x0
_Z14sigmoid_kernelPfi:
.quad _Z29__device_stub__sigmoid_kernelPfi
.size _Z14sigmoid_kernelPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14sigmoid_kernelPfi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sigmoid_kernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sigmoid_kernelPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14sigmoid_kernelPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0.96630859375, -0.0022525787353515625 ; /* 0x3bbb989dff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x437c0000 ; /* 0x437c0000ff077424 */
/* 0x000fe200078e00ff */
/*00c0*/ BSSY B0, 0x250 ; /* 0x0000018000007945 */
/* 0x000ff00003800000 */
/*00d0*/ FFMA.SAT R4, -R0, R5, 0.5 ; /* 0x3f00000000047423 */
/* 0x004fc80000002105 */
/*00e0*/ FFMA.RM R4, R4, R7, 12582913 ; /* 0x4b40000104047423 */
/* 0x000fc80000004007 */
/*00f0*/ FADD R5, R4.reuse, -12583039 ; /* 0xcb40007f04057421 */
/* 0x040fe40000000000 */
/*0100*/ IMAD.SHL.U32 R4, R4, 0x800000, RZ ; /* 0x0080000004047824 */
/* 0x000fe400078e00ff */
/*0110*/ FFMA R5, -R0, 1.4426950216293334961, -R5 ; /* 0x3fb8aa3b00057823 */
/* 0x000fc80000000905 */
/*0120*/ FFMA R0, -R0, 1.925963033500011079e-08, R5 ; /* 0x32a5706000007823 */
/* 0x000fc80000000105 */
/*0130*/ MUFU.EX2 R5, R0 ; /* 0x0000000000057308 */
/* 0x000e240000000800 */
/*0140*/ FMUL R12, R4, R5 ; /* 0x00000005040c7220 */
/* 0x001fcc0000400000 */
/*0150*/ F2F.F64.F32 R4, R12 ; /* 0x0000000c00047310 */
/* 0x000e240000201800 */
/*0160*/ DADD R4, R4, 1 ; /* 0x3ff0000004047429 */
/* 0x001e0c0000000000 */
/*0170*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e280000001800 */
/*0180*/ IADD3 R6, R5, 0x300402, RZ ; /* 0x0030040205067810 */
/* 0x000fc80007ffe0ff */
/*0190*/ FSETP.GEU.AND P0, PT, |R6|, 5.8789094863358348022e-39, PT ; /* 0x004004020600780b */
/* 0x000fe40003f0e200 */
/*01a0*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000106 */
/*01b0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*01c0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*01d0*/ DFMA R10, -R4, R8, 1 ; /* 0x3ff00000040a742b */
/* 0x001e0c0000000108 */
/*01e0*/ DFMA R8, R8, R10, R8 ; /* 0x0000000a0808722b */
/* 0x0010620000000008 */
/*01f0*/ @P0 BRA 0x240 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0200*/ LOP3.LUT R0, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05007812 */
/* 0x000fc800078ec0ff */
/*0210*/ IADD3 R8, R0, -0x100000, RZ ; /* 0xfff0000000087810 */
/* 0x002fe40007ffe0ff */
/*0220*/ MOV R0, 0x240 ; /* 0x0000024000007802 */
/* 0x000fe40000000f00 */
/*0230*/ CALL.REL.NOINC 0x280 ; /* 0x0000004000007944 */
/* 0x001fea0003c00000 */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x002e640000301000 */
/*0260*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x002fe2000c101904 */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ DSETP.GTU.AND P0, PT, |R4|, +INF , PT ; /* 0x7ff000000400742a */
/* 0x000e220003f0c200 */
/*0290*/ BSSY B1, 0x4d0 ; /* 0x0000023000017945 */
/* 0x000fda0003800000 */
/*02a0*/ @P0 BRA 0x4a0 ; /* 0x000001f000000947 */
/* 0x001fea0003800000 */
/*02b0*/ LOP3.LUT R9, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05097812 */
/* 0x000fc800078ec0ff */
/*02c0*/ IADD3 R6, R9, -0x1, RZ ; /* 0xffffffff09067810 */
/* 0x000fc80007ffe0ff */
/*02d0*/ ISETP.GE.U32.AND P0, PT, R6, 0x7fefffff, PT ; /* 0x7fefffff0600780c */
/* 0x000fda0003f06070 */
/*02e0*/ @P0 LOP3.LUT R7, R5, 0x7ff00000, RZ, 0x3c, !PT ; /* 0x7ff0000005070812 */
/* 0x000fe400078e3cff */
/*02f0*/ @P0 MOV R6, RZ ; /* 0x000000ff00060202 */
/* 0x000fe20000000f00 */
/*0300*/ @P0 BRA 0x4c0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GE.U32.AND P0, PT, R9, 0x1000001, PT ; /* 0x010000010900780c */
/* 0x000fda0003f06070 */
/*0320*/ @!P0 BRA 0x400 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0330*/ IADD3 R7, R5, -0x3fe00000, RZ ; /* 0xc020000005077810 */
/* 0x000fe20007ffe0ff */
/*0340*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fc600078e0004 */
/*0350*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x000e260000001800 */
/*0360*/ DFMA R10, -R6, R8, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c0000000108 */
/*0370*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0380*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*0390*/ DFMA R8, -R6, R10, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c000000010a */
/*03a0*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*03b0*/ DMUL R8, R8, 2.2250738585072013831e-308 ; /* 0x0010000008087828 */
/* 0x001e0c0000000000 */
/*03c0*/ DFMA R4, -R4, R8, 1 ; /* 0x3ff000000404742b */
/* 0x001e0c0000000108 */
/*03d0*/ DFMA R4, R4, R4, R4 ; /* 0x000000040404722b */
/* 0x001e0c0000000004 */
/*03e0*/ DFMA R6, R8, R4, R8 ; /* 0x000000040806722b */
/* 0x0010620000000008 */
/*03f0*/ BRA 0x4c0 ; /* 0x000000c000007947 */
/* 0x000fea0003800000 */
/*0400*/ DMUL R4, R4, 8.11296384146066816958e+31 ; /* 0x4690000004047828 */
/* 0x000e220000000000 */
/*0410*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fca00078e0008 */
/*0420*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e240000001800 */
/*0430*/ DFMA R8, -R4, R6, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000106 */
/*0440*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0450*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0460*/ DFMA R6, -R4, R8, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000108 */
/*0470*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x001e0c0000000008 */
/*0480*/ DMUL R6, R6, 8.11296384146066816958e+31 ; /* 0x4690000006067828 */
/* 0x001e220000000000 */
/*0490*/ BRA 0x4c0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*04a0*/ LOP3.LUT R7, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000005077812 */
/* 0x000fe400078efcff */
/*04b0*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x000fe40000000f00 */
/*04c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04d0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x001fe200000001ff */
/*04e0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0000 */
/*04f0*/ MOV R9, R7 ; /* 0x0000000700097202 */
/* 0x002fe20000000f00 */
/*0500*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0006 */
/*0510*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffae004007950 */
/* 0x000fea0003c3ffff */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sigmoid_kernelPfi
.globl _Z14sigmoid_kernelPfi
.p2align 8
.type _Z14sigmoid_kernelPfi,@function
_Z14sigmoid_kernelPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0xbfb8aa3b, v2
v_cmp_nlt_f32_e32 vcc_lo, 0x42ce8ed0, v2
v_fma_f32 v4, v2, 0xbfb8aa3b, -v3
v_rndne_f32_e32 v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmamk_f32 v4, v2, 0xb2a5705f, v4 :: v_dual_sub_f32 v3, v3, v5
v_add_f32_e32 v3, v3, v4
v_cvt_i32_f32_e32 v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v3, v4
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2b17218, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, 0x7f800000, v3, vcc_lo
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], 1.0
v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, 1.0, v[2:3], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[8:9], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sigmoid_kernelPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sigmoid_kernelPfi, .Lfunc_end0-_Z14sigmoid_kernelPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sigmoid_kernelPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14sigmoid_kernelPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001aeb11_00000000-6_sigmoid_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z14sigmoid_kernelPfiPfi
.type _Z35__device_stub__Z14sigmoid_kernelPfiPfi, @function
_Z35__device_stub__Z14sigmoid_kernelPfiPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14sigmoid_kernelPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z35__device_stub__Z14sigmoid_kernelPfiPfi, .-_Z35__device_stub__Z14sigmoid_kernelPfiPfi
.globl _Z14sigmoid_kernelPfi
.type _Z14sigmoid_kernelPfi, @function
_Z14sigmoid_kernelPfi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14sigmoid_kernelPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z14sigmoid_kernelPfi, .-_Z14sigmoid_kernelPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14sigmoid_kernelPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sigmoid_kernelPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sigmoid_kernel.hip"
.globl _Z29__device_stub__sigmoid_kernelPfi # -- Begin function _Z29__device_stub__sigmoid_kernelPfi
.p2align 4, 0x90
.type _Z29__device_stub__sigmoid_kernelPfi,@function
_Z29__device_stub__sigmoid_kernelPfi: # @_Z29__device_stub__sigmoid_kernelPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14sigmoid_kernelPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__sigmoid_kernelPfi, .Lfunc_end0-_Z29__device_stub__sigmoid_kernelPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sigmoid_kernelPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sigmoid_kernelPfi,@object # @_Z14sigmoid_kernelPfi
.section .rodata,"a",@progbits
.globl _Z14sigmoid_kernelPfi
.p2align 3, 0x0
_Z14sigmoid_kernelPfi:
.quad _Z29__device_stub__sigmoid_kernelPfi
.size _Z14sigmoid_kernelPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14sigmoid_kernelPfi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sigmoid_kernelPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sigmoid_kernelPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// This code is based on code from:
// https://en.cppreference.com/w/cpp/algorithm/reduce
// and
//
// This code uses a GPU and thrust to perform a reduction
//
#include <iostream>
#include <chrono>
#include <vector>
#include <numeric>
#include <thrust/reduce.h>
#include <thrust/device_vector.h>
#include <thrust/functional.h>
#include <thrust/host_vector.h>
int main(int argc,char *argv[])
{
if (argc!=2) {
std::cout << "Usage: sample n " << std::endl;
return -1;
}
int n = atoi(argv[1]);
thrust::host_vector<int> hv(n,1);
{
auto t1 = std::chrono::high_resolution_clock::now();
thrust::device_vector<int> dv = hv;
int result = 0;
// initial value of the reduction
int init = 0;
// binary operation used to reduce values
thrust::plus<int> binary_op;
// compute sum on the device
result = thrust::reduce(dv.begin(), dv.end(), init, binary_op);
//result = std::accumulate(v.begin(), v.end(), 0.0);
auto t2 = std::chrono::high_resolution_clock::now();
std::chrono::duration<double, std::milli> ms = t2 - t1;
std::cout << std::fixed << "thrust::reduce " << result
<< " took " << ms.count() << " ms\n";
}
} | //
// This code is based on code from:
// https://en.cppreference.com/w/cpp/algorithm/reduce
// and
//
// This code uses a GPU and thrust to perform a reduction
//
#include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
#include <vector>
#include <numeric>
#include <thrust/reduce.h>
#include <thrust/device_vector.h>
#include <thrust/functional.h>
#include <thrust/host_vector.h>
int main(int argc,char *argv[])
{
if (argc!=2) {
std::cout << "Usage: sample n " << std::endl;
return -1;
}
int n = atoi(argv[1]);
thrust::host_vector<int> hv(n,1);
{
auto t1 = std::chrono::high_resolution_clock::now();
thrust::device_vector<int> dv = hv;
int result = 0;
// initial value of the reduction
int init = 0;
// binary operation used to reduce values
thrust::plus<int> binary_op;
// compute sum on the device
result = thrust::reduce(dv.begin(), dv.end(), init, binary_op);
//result = std::accumulate(v.begin(), v.end(), 0.0);
auto t2 = std::chrono::high_resolution_clock::now();
std::chrono::duration<double, std::milli> ms = t2 - t1;
std::cout << std::fixed << "thrust::reduce " << result
<< " took " << ms.count() << " ms\n";
}
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void vecAdd(float* A, float* B, float* C) {
//threadIdx.x is a build-in variable provided by CUDA runtime
int i = threadIdx.x;
A[i] = 0;
B[i] = 0;
C[i] = A[i] + B[i];
} | code for sm_80
Function : _Z6vecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe200078e0207 */
/*0060*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101904 */
/*0070*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe8000c101904 */
/*0080*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00a0*/ FADD R9, RZ, R0 ; /* 0x00000000ff097221 */
/* 0x004fca0000000000 */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void vecAdd(float* A, float* B, float* C) {
//threadIdx.x is a build-in variable provided by CUDA runtime
int i = threadIdx.x;
A[i] = 0;
B[i] = 0;
C[i] = A[i] + B[i];
} | .file "tmpxft_000c82fd_00000000-6_vecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6vecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6vecAddPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6vecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6vecAddPfS_S_PfS_S_
.globl _Z6vecAddPfS_S_
.type _Z6vecAddPfS_S_, @function
_Z6vecAddPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecAddPfS_S_, .-_Z6vecAddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void vecAdd(float* A, float* B, float* C) {
//threadIdx.x is a build-in variable provided by CUDA runtime
int i = threadIdx.x;
A[i] = 0;
B[i] = 0;
C[i] = A[i] + B[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecAdd(float* A, float* B, float* C) {
//threadIdx.x is a build-in variable provided by CUDA runtime
int i = threadIdx.x;
A[i] = 0;
B[i] = 0;
C[i] = A[i] + B[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecAdd(float* A, float* B, float* C) {
//threadIdx.x is a build-in variable provided by CUDA runtime
int i = threadIdx.x;
A[i] = 0;
B[i] = 0;
C[i] = A[i] + B[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_
.globl _Z6vecAddPfS_S_
.p2align 8
.type _Z6vecAddPfS_S_,@function
_Z6vecAddPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v0, v1, s[4:5]
global_store_b32 v0, v1, s[6:7]
global_load_b32 v1, v0, s[4:5]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, 0, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_, .Lfunc_end0-_Z6vecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecAdd(float* A, float* B, float* C) {
//threadIdx.x is a build-in variable provided by CUDA runtime
int i = threadIdx.x;
A[i] = 0;
B[i] = 0;
C[i] = A[i] + B[i];
} | .text
.file "vecAdd.hip"
.globl _Z21__device_stub__vecAddPfS_S_ # -- Begin function _Z21__device_stub__vecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_,@function
_Z21__device_stub__vecAddPfS_S_: # @_Z21__device_stub__vecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_,@object # @_Z6vecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_
.p2align 3, 0x0
_Z6vecAddPfS_S_:
.quad _Z21__device_stub__vecAddPfS_S_
.size _Z6vecAddPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe200078e0207 */
/*0060*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101904 */
/*0070*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe8000c101904 */
/*0080*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00a0*/ FADD R9, RZ, R0 ; /* 0x00000000ff097221 */
/* 0x004fca0000000000 */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_
.globl _Z6vecAddPfS_S_
.p2align 8
.type _Z6vecAddPfS_S_,@function
_Z6vecAddPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v0, v1, s[4:5]
global_store_b32 v0, v1, s[6:7]
global_load_b32 v1, v0, s[4:5]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, 0, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_, .Lfunc_end0-_Z6vecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c82fd_00000000-6_vecAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6vecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6vecAddPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6vecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6vecAddPfS_S_PfS_S_
.globl _Z6vecAddPfS_S_
.type _Z6vecAddPfS_S_, @function
_Z6vecAddPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6vecAddPfS_S_, .-_Z6vecAddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6vecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecAdd.hip"
.globl _Z21__device_stub__vecAddPfS_S_ # -- Begin function _Z21__device_stub__vecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_,@function
_Z21__device_stub__vecAddPfS_S_: # @_Z21__device_stub__vecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPfS_S_,@object # @_Z6vecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_
.p2align 3, 0x0
_Z6vecAddPfS_S_:
.quad _Z21__device_stub__vecAddPfS_S_
.size _Z6vecAddPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Compiling with nvcc:
nvcc 3d_matrix_allocte.cu -o 3d_matrix_allocte -std=c++11
./3d_matrix_allocte
Sample Output:
Matrix Allocated
Time taken for matrix allocation : 9 microseconds
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// The following code sample allocates a width x height x
// depth 3D array of floating-point values and shows how
// to loop over the array elements in device code
// Device code
__global__ void matrixLoop(cudaPitchedPtr devPitchedPtr,
int width, int height, int depth)
{
char* deice_pointer = (char* )devPitchedPtr.ptr;
size_t pitch = devPitchedPtr.pitch;
size_t slicePitch = pitch * height;
for (int z = 0; z < depth; ++z) {
char* slice = deice_pointer + z * slicePitch;
for (int y = 0; y < height; ++y) {
float* row = (float*)(slice + y * pitch);
for (int x = 0; x < width; ++x) {
float element = row[x];
}
}
}
}
// Host code
int main()
{
int width = 128, height = 128, depth = 128;
//cuda data structure used to dimension o the matrix
cudaExtent extent = make_cudaExtent(width * sizeof(float),
height, depth);
// declare cuda pitched memory pointer
cudaPitchedPtr devPitchedPtr;
// allocate 3d matrix
cudaMalloc3D(&devPitchedPtr, extent);
printf("Matrix Allocated\n");
matrixLoop<<<100, 512>>>(devPitchedPtr, width, height, depth);
} | code for sm_80
Function : _Z10matrixLoop14cudaPitchedPtriii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Compiling with nvcc:
nvcc 3d_matrix_allocte.cu -o 3d_matrix_allocte -std=c++11
./3d_matrix_allocte
Sample Output:
Matrix Allocated
Time taken for matrix allocation : 9 microseconds
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// The following code sample allocates a width x height x
// depth 3D array of floating-point values and shows how
// to loop over the array elements in device code
// Device code
__global__ void matrixLoop(cudaPitchedPtr devPitchedPtr,
int width, int height, int depth)
{
char* deice_pointer = (char* )devPitchedPtr.ptr;
size_t pitch = devPitchedPtr.pitch;
size_t slicePitch = pitch * height;
for (int z = 0; z < depth; ++z) {
char* slice = deice_pointer + z * slicePitch;
for (int y = 0; y < height; ++y) {
float* row = (float*)(slice + y * pitch);
for (int x = 0; x < width; ++x) {
float element = row[x];
}
}
}
}
// Host code
int main()
{
int width = 128, height = 128, depth = 128;
//cuda data structure used to dimension o the matrix
cudaExtent extent = make_cudaExtent(width * sizeof(float),
height, depth);
// declare cuda pitched memory pointer
cudaPitchedPtr devPitchedPtr;
// allocate 3d matrix
cudaMalloc3D(&devPitchedPtr, extent);
printf("Matrix Allocated\n");
matrixLoop<<<100, 512>>>(devPitchedPtr, width, height, depth);
} | .file "tmpxft_0018c5af_00000000-6_3d_matrix_allocte.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z10matrixLoop14cudaPitchedPtriiiR14cudaPitchedPtriii
.type _Z47__device_stub__Z10matrixLoop14cudaPitchedPtriiiR14cudaPitchedPtriii, @function
_Z47__device_stub__Z10matrixLoop14cudaPitchedPtriiiR14cudaPitchedPtriii:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10matrixLoop14cudaPitchedPtriii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z47__device_stub__Z10matrixLoop14cudaPitchedPtriiiR14cudaPitchedPtriii, .-_Z47__device_stub__Z10matrixLoop14cudaPitchedPtriiiR14cudaPitchedPtriii
.globl _Z10matrixLoop14cudaPitchedPtriii
.type _Z10matrixLoop14cudaPitchedPtriii, @function
_Z10matrixLoop14cudaPitchedPtriii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edx, %ecx
movl %esi, %edx
movl %edi, %esi
leaq 16(%rsp), %rdi
call _Z47__device_stub__Z10matrixLoop14cudaPitchedPtriiiR14cudaPitchedPtriii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z10matrixLoop14cudaPitchedPtriii, .-_Z10matrixLoop14cudaPitchedPtriii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Matrix Allocated\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq $512, 32(%rsp)
movq $128, 40(%rsp)
leaq 64(%rsp), %rdi
subq $32, %rsp
.cfi_def_cfa_offset 192
movdqa 64(%rsp), %xmm0
movups %xmm0, (%rsp)
movq $128, 16(%rsp)
call cudaMalloc3D@PLT
addq $32, %rsp
.cfi_def_cfa_offset 160
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $100, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movdqa 64(%rsp), %xmm1
movaps %xmm1, 96(%rsp)
movdqa 80(%rsp), %xmm2
movaps %xmm2, 112(%rsp)
leaq 96(%rsp), %rdi
movl $128, %ecx
movl $128, %edx
movl $128, %esi
call _Z47__device_stub__Z10matrixLoop14cudaPitchedPtriiiR14cudaPitchedPtriii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z10matrixLoop14cudaPitchedPtriii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixLoop14cudaPitchedPtriii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Compiling with nvcc:
nvcc 3d_matrix_allocte.cu -o 3d_matrix_allocte -std=c++11
./3d_matrix_allocte
Sample Output:
Matrix Allocated
Time taken for matrix allocation : 9 microseconds
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// The following code sample allocates a width x height x
// depth 3D array of floating-point values and shows how
// to loop over the array elements in device code
// Device code
__global__ void matrixLoop(cudaPitchedPtr devPitchedPtr,
int width, int height, int depth)
{
char* deice_pointer = (char* )devPitchedPtr.ptr;
size_t pitch = devPitchedPtr.pitch;
size_t slicePitch = pitch * height;
for (int z = 0; z < depth; ++z) {
char* slice = deice_pointer + z * slicePitch;
for (int y = 0; y < height; ++y) {
float* row = (float*)(slice + y * pitch);
for (int x = 0; x < width; ++x) {
float element = row[x];
}
}
}
}
// Host code
int main()
{
int width = 128, height = 128, depth = 128;
//cuda data structure used to dimension o the matrix
cudaExtent extent = make_cudaExtent(width * sizeof(float),
height, depth);
// declare cuda pitched memory pointer
cudaPitchedPtr devPitchedPtr;
// allocate 3d matrix
cudaMalloc3D(&devPitchedPtr, extent);
printf("Matrix Allocated\n");
matrixLoop<<<100, 512>>>(devPitchedPtr, width, height, depth);
} | /*
Compiling with nvcc:
nvcc 3d_matrix_allocte.cu -o 3d_matrix_allocte -std=c++11
./3d_matrix_allocte
Sample Output:
Matrix Allocated
Time taken for matrix allocation : 9 microseconds
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// The following code sample allocates a width x height x
// depth 3D array of floating-point values and shows how
// to loop over the array elements in device code
// Device code
__global__ void matrixLoop(hipPitchedPtr devPitchedPtr,
int width, int height, int depth)
{
char* deice_pointer = (char* )devPitchedPtr.ptr;
size_t pitch = devPitchedPtr.pitch;
size_t slicePitch = pitch * height;
for (int z = 0; z < depth; ++z) {
char* slice = deice_pointer + z * slicePitch;
for (int y = 0; y < height; ++y) {
float* row = (float*)(slice + y * pitch);
for (int x = 0; x < width; ++x) {
float element = row[x];
}
}
}
}
// Host code
int main()
{
int width = 128, height = 128, depth = 128;
//cuda data structure used to dimension o the matrix
hipExtent extent = make_hipExtent(width * sizeof(float),
height, depth);
// declare cuda pitched memory pointer
hipPitchedPtr devPitchedPtr;
// allocate 3d matrix
hipMalloc3D(&devPitchedPtr, extent);
printf("Matrix Allocated\n");
matrixLoop<<<100, 512>>>(devPitchedPtr, width, height, depth);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Compiling with nvcc:
nvcc 3d_matrix_allocte.cu -o 3d_matrix_allocte -std=c++11
./3d_matrix_allocte
Sample Output:
Matrix Allocated
Time taken for matrix allocation : 9 microseconds
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// The following code sample allocates a width x height x
// depth 3D array of floating-point values and shows how
// to loop over the array elements in device code
// Device code
__global__ void matrixLoop(hipPitchedPtr devPitchedPtr,
int width, int height, int depth)
{
char* deice_pointer = (char* )devPitchedPtr.ptr;
size_t pitch = devPitchedPtr.pitch;
size_t slicePitch = pitch * height;
for (int z = 0; z < depth; ++z) {
char* slice = deice_pointer + z * slicePitch;
for (int y = 0; y < height; ++y) {
float* row = (float*)(slice + y * pitch);
for (int x = 0; x < width; ++x) {
float element = row[x];
}
}
}
}
// Host code
int main()
{
int width = 128, height = 128, depth = 128;
//cuda data structure used to dimension o the matrix
hipExtent extent = make_hipExtent(width * sizeof(float),
height, depth);
// declare cuda pitched memory pointer
hipPitchedPtr devPitchedPtr;
// allocate 3d matrix
hipMalloc3D(&devPitchedPtr, extent);
printf("Matrix Allocated\n");
matrixLoop<<<100, 512>>>(devPitchedPtr, width, height, depth);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixLoop13hipPitchedPtriii
.globl _Z10matrixLoop13hipPitchedPtriii
.p2align 8
.type _Z10matrixLoop13hipPitchedPtriii,@function
_Z10matrixLoop13hipPitchedPtriii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixLoop13hipPitchedPtriii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixLoop13hipPitchedPtriii, .Lfunc_end0-_Z10matrixLoop13hipPitchedPtriii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixLoop13hipPitchedPtriii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10matrixLoop13hipPitchedPtriii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Compiling with nvcc:
nvcc 3d_matrix_allocte.cu -o 3d_matrix_allocte -std=c++11
./3d_matrix_allocte
Sample Output:
Matrix Allocated
Time taken for matrix allocation : 9 microseconds
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// The following code sample allocates a width x height x
// depth 3D array of floating-point values and shows how
// to loop over the array elements in device code
// Device code
__global__ void matrixLoop(hipPitchedPtr devPitchedPtr,
int width, int height, int depth)
{
char* deice_pointer = (char* )devPitchedPtr.ptr;
size_t pitch = devPitchedPtr.pitch;
size_t slicePitch = pitch * height;
for (int z = 0; z < depth; ++z) {
char* slice = deice_pointer + z * slicePitch;
for (int y = 0; y < height; ++y) {
float* row = (float*)(slice + y * pitch);
for (int x = 0; x < width; ++x) {
float element = row[x];
}
}
}
}
// Host code
int main()
{
int width = 128, height = 128, depth = 128;
//cuda data structure used to dimension o the matrix
hipExtent extent = make_hipExtent(width * sizeof(float),
height, depth);
// declare cuda pitched memory pointer
hipPitchedPtr devPitchedPtr;
// allocate 3d matrix
hipMalloc3D(&devPitchedPtr, extent);
printf("Matrix Allocated\n");
matrixLoop<<<100, 512>>>(devPitchedPtr, width, height, depth);
} | .text
.file "3d_matrix_allocte.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__matrixLoop13hipPitchedPtriii # -- Begin function _Z25__device_stub__matrixLoop13hipPitchedPtriii
.p2align 4, 0x90
.type _Z25__device_stub__matrixLoop13hipPitchedPtriii,@function
_Z25__device_stub__matrixLoop13hipPitchedPtriii: # @_Z25__device_stub__matrixLoop13hipPitchedPtriii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
leaq 112(%rsp), %rax
movq %rax, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 72(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10matrixLoop13hipPitchedPtriii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__matrixLoop13hipPitchedPtriii, .Lfunc_end0-_Z25__device_stub__matrixLoop13hipPitchedPtriii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq $512, 88(%rsp) # imm = 0x200
movq $128, 96(%rsp)
movq $128, 104(%rsp)
movups 88(%rsp), %xmm0
movups %xmm0, (%rsp)
movq $128, 16(%rsp)
leaq 184(%rsp), %rdi
callq hipMalloc3D
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967396, %rdi # imm = 0x100000064
leaq 412(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movups 184(%rsp), %xmm0
movups 200(%rsp), %xmm1
movaps %xmm1, 160(%rsp)
movaps %xmm0, 144(%rsp)
movl $128, 36(%rsp)
movl $128, 32(%rsp)
movl $128, 28(%rsp)
leaq 144(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rax
movq 40(%rsp), %rdi
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 112(%rsp), %r9
movl $_Z10matrixLoop13hipPitchedPtriii, %edi
callq hipLaunchKernel
.LBB1_2:
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixLoop13hipPitchedPtriii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrixLoop13hipPitchedPtriii,@object # @_Z10matrixLoop13hipPitchedPtriii
.section .rodata,"a",@progbits
.globl _Z10matrixLoop13hipPitchedPtriii
.p2align 3, 0x0
_Z10matrixLoop13hipPitchedPtriii:
.quad _Z25__device_stub__matrixLoop13hipPitchedPtriii
.size _Z10matrixLoop13hipPitchedPtriii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10matrixLoop13hipPitchedPtriii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Matrix Allocated"
.size .Lstr, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixLoop13hipPitchedPtriii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrixLoop13hipPitchedPtriii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10matrixLoop14cudaPitchedPtriii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixLoop13hipPitchedPtriii
.globl _Z10matrixLoop13hipPitchedPtriii
.p2align 8
.type _Z10matrixLoop13hipPitchedPtriii,@function
_Z10matrixLoop13hipPitchedPtriii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixLoop13hipPitchedPtriii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixLoop13hipPitchedPtriii, .Lfunc_end0-_Z10matrixLoop13hipPitchedPtriii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixLoop13hipPitchedPtriii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z10matrixLoop13hipPitchedPtriii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018c5af_00000000-6_3d_matrix_allocte.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z10matrixLoop14cudaPitchedPtriiiR14cudaPitchedPtriii
.type _Z47__device_stub__Z10matrixLoop14cudaPitchedPtriiiR14cudaPitchedPtriii, @function
_Z47__device_stub__Z10matrixLoop14cudaPitchedPtriiiR14cudaPitchedPtriii:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10matrixLoop14cudaPitchedPtriii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z47__device_stub__Z10matrixLoop14cudaPitchedPtriiiR14cudaPitchedPtriii, .-_Z47__device_stub__Z10matrixLoop14cudaPitchedPtriiiR14cudaPitchedPtriii
.globl _Z10matrixLoop14cudaPitchedPtriii
.type _Z10matrixLoop14cudaPitchedPtriii, @function
_Z10matrixLoop14cudaPitchedPtriii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edx, %ecx
movl %esi, %edx
movl %edi, %esi
leaq 16(%rsp), %rdi
call _Z47__device_stub__Z10matrixLoop14cudaPitchedPtriiiR14cudaPitchedPtriii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z10matrixLoop14cudaPitchedPtriii, .-_Z10matrixLoop14cudaPitchedPtriii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Matrix Allocated\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq $512, 32(%rsp)
movq $128, 40(%rsp)
leaq 64(%rsp), %rdi
subq $32, %rsp
.cfi_def_cfa_offset 192
movdqa 64(%rsp), %xmm0
movups %xmm0, (%rsp)
movq $128, 16(%rsp)
call cudaMalloc3D@PLT
addq $32, %rsp
.cfi_def_cfa_offset 160
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $100, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movdqa 64(%rsp), %xmm1
movaps %xmm1, 96(%rsp)
movdqa 80(%rsp), %xmm2
movaps %xmm2, 112(%rsp)
leaq 96(%rsp), %rdi
movl $128, %ecx
movl $128, %edx
movl $128, %esi
call _Z47__device_stub__Z10matrixLoop14cudaPitchedPtriiiR14cudaPitchedPtriii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z10matrixLoop14cudaPitchedPtriii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixLoop14cudaPitchedPtriii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "3d_matrix_allocte.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__matrixLoop13hipPitchedPtriii # -- Begin function _Z25__device_stub__matrixLoop13hipPitchedPtriii
.p2align 4, 0x90
.type _Z25__device_stub__matrixLoop13hipPitchedPtriii,@function
_Z25__device_stub__matrixLoop13hipPitchedPtriii: # @_Z25__device_stub__matrixLoop13hipPitchedPtriii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
leaq 112(%rsp), %rax
movq %rax, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 72(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10matrixLoop13hipPitchedPtriii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__matrixLoop13hipPitchedPtriii, .Lfunc_end0-_Z25__device_stub__matrixLoop13hipPitchedPtriii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq $512, 88(%rsp) # imm = 0x200
movq $128, 96(%rsp)
movq $128, 104(%rsp)
movups 88(%rsp), %xmm0
movups %xmm0, (%rsp)
movq $128, 16(%rsp)
leaq 184(%rsp), %rdi
callq hipMalloc3D
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967396, %rdi # imm = 0x100000064
leaq 412(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movups 184(%rsp), %xmm0
movups 200(%rsp), %xmm1
movaps %xmm1, 160(%rsp)
movaps %xmm0, 144(%rsp)
movl $128, 36(%rsp)
movl $128, 32(%rsp)
movl $128, 28(%rsp)
leaq 144(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rax
movq 40(%rsp), %rdi
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 112(%rsp), %r9
movl $_Z10matrixLoop13hipPitchedPtriii, %edi
callq hipLaunchKernel
.LBB1_2:
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixLoop13hipPitchedPtriii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrixLoop13hipPitchedPtriii,@object # @_Z10matrixLoop13hipPitchedPtriii
.section .rodata,"a",@progbits
.globl _Z10matrixLoop13hipPitchedPtriii
.p2align 3, 0x0
_Z10matrixLoop13hipPitchedPtriii:
.quad _Z25__device_stub__matrixLoop13hipPitchedPtriii
.size _Z10matrixLoop13hipPitchedPtriii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10matrixLoop13hipPitchedPtriii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Matrix Allocated"
.size .Lstr, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixLoop13hipPitchedPtriii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrixLoop13hipPitchedPtriii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
This is the function you need to implement. Quick reference:
- input rows: 0 <= y < ny
- input columns: 0 <= x < nx
- element at row y and column x is stored in data[x + y*nx]
- correlation between rows i and row j has to be stored in result[i + j*ny]
- only parts with 0 <= j <= i < ny need to be filled
*/
#include <cuda_runtime.h>
#include "device_launch_parameters.h"
#include <iostream>
#include <math.h>
#include <vector>
static inline void check(cudaError_t err, const char* context) {
if (err != cudaSuccess) {
std::cerr << "CUDA error: " << context << ": "
<< cudaGetErrorString(err) << std::endl;
std::exit(EXIT_FAILURE);
}
}
#define CHECK(x) check(x, #x)
template <class T>
void cuda_memcpy(T* target, const T* source, std::size_t num, cudaMemcpyKind direction) {
CHECK(cudaMemcpy(target, source, num * sizeof(T), direction));
}
// params:
// data : transposed padding data
__global__ void correlate_gpu(int ny, int nx, const float*data, float *result, int new_ny){
const int nd=16;// nd: nd==blockDim.x==blockDim.y
// compute nd*nd results each thread.
int step=nd*nd;// each block will compute step*step results.
int ia=threadIdx.x;
int ja=threadIdx.y;
int ic=blockIdx.x;
int jc=blockIdx.y;
// int i=threadIdx.x+blockIdx.x*blockDim.x;
// int j=threadIdx.y+blockIdx.y*blockDim.y;
// if(i>=ny || j>=ny) return;
// if (i>j){
// result[i*ny+j]=0;
// return;
// }
float v[nd][nd];
// double temp=0;
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]=0;
}
}
for (int k=0; k<nx; ++k){
float x[nd];
float y[nd];
for(int ib=0; ib<nd; ib++){
int i=ic*step+ib*nd+ia;
x[ib]=data[k*new_ny +i];
}
for(int jb=0; jb<nd; jb++){
int j=jc*step+jb*nd+ja;
y[jb]=data[k*new_ny+j];
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]+=x[ib]*y[jb];
}
}
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
int i=ic*step+ib*nd+ia;
int j=jc*step+jb*nd+ja;
if(i<ny&&j<ny&&i<=j){
result[ny*i+j]=v[ib][jb];
}
}
}
// result[i*ny+j]=temp;
}
__global__ void padding_transpose(int ny, int nx, const float*data, float* result, int new_ny){
//result is padding and transpose data
int ja=threadIdx.x;
int i=blockIdx.y;
for (int jb=0; jb<nx; jb+=blockDim.x){
int j=jb+ja;
if (j>=nx) break;
float v=i<ny?data[i*ny+j]:0; //padding
result[new_ny*j+i]=v; //transpose
}
}
static inline int divup(int a, int b) {
return (a + b - 1)/b;
}
static inline int roundup(int a, int b) {
return divup(a, b) * b;
}
void correlate(int ny, int nx, const float *data, float *result) {
// const int nd=16;//compute nd*nd results each thread. could not less than
const int block_size=16; //16*16 threads
const int step=block_size*block_size; // each block will compute step*step results.
int new_ny=roundup(ny,step);
//allocate memory & copy data to GPU
float *dGPU=NULL;
CHECK(cudaMalloc((void**)&dGPU,ny*nx*sizeof(float)));
float *padding=NULL;
CHECK(cudaMalloc((void**)&padding,new_ny*nx*sizeof(float)));
float *rGPU=NULL;
CHECK(cudaMalloc((void**)&rGPU,ny*ny*sizeof(float)));
// float *avg=new float[ny]{0};
// float *normalized=new float[ny*nx]{0};
// float *sqrtSqureSum=new float[ny]{0};
std::vector<float> avg(ny,0);
std::vector<float> normalized(ny*nx,0);
std::vector<float> sqrtSqureSum(ny,0);
std::vector<float> transposed(nx*new_ny,0);
for (int y=0; y<ny; ++y){
double temp=0;
for (int x=0; x<nx; ++x){
temp+=data[y*nx+x];
}
avg[y]=temp/nx;
}
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
normalized[y*nx+x]=data[y*nx+x]-avg[y];
}
}
// delete[] avg;
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
sqrtSqureSum[y]+=pow(normalized[y*nx+x],2);
}
sqrtSqureSum[y]=sqrt(sqrtSqureSum[y]);
}
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
normalized[y*nx+x]/=sqrtSqureSum[y];
}
}
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
std::cout << normalized[y*nx+x] << " ";
}
std::cout<< std::endl ;
}
cuda_memcpy(dGPU,normalized.data(),ny*nx,cudaMemcpyHostToDevice);
// Run kernel to padding and transpose
{
dim3 dimBlock(64,1);
dim3 dimGrid(1,new_ny);
padding_transpose<<<dimGrid,dimBlock>>>(ny,nx,dGPU,padding,new_ny);
CHECK(cudaGetLastError());
}
cuda_memcpy(transposed.data(), padding, new_ny * nx, cudaMemcpyDeviceToHost);
std::cout << new_ny<<std::endl;
std::cout << transposed.size()<<std::endl;
for(int x=0;x<nx;x++){
for(int y=0;y<new_ny;y++){
std::cout<< transposed[x*new_ny+y] << " ";
}
std::cout<< std::endl<< "----"<< std::endl;
}
// for (int x=0;x<nx;++x){
// for (int y=0; y<ny; ++y){
// transposed[x*ny+y]=normalized[y*nx+x];
// }
// }
// Run kernel to calculate cp
{
dim3 dimBlock(block_size,block_size);
dim3 dimGrid(new_ny/step,new_ny/step);
correlate_gpu<<<dimGrid,dimBlock>>>(ny,nx,padding,rGPU,new_ny);
CHECK(cudaGetLastError());
}
cuda_memcpy(result, rGPU, ny * ny, cudaMemcpyDeviceToHost);
// CHECK(cudaMemcpy(result, rGPU, ny * ny * sizeof(float), cudaMemcpyDeviceToHost));
CHECK(cudaFree(dGPU));
CHECK(cudaFree(padding));
CHECK(cudaFree(rGPU));
// delete[] normalized;
}
int main(){
int ny=3;
int nx=2;
// float data[]={+0.81472367, +0.90579194,
// +0.45150527, +0.49610928}; //result: 1 1 0 1
float data[]={
-1.00000000, +1.00000000,
+1.00000000, -1.00000000,
-1.00000000, +1.00000000
};
// float data[]={-1.0, 1.0, 1.0, -1.0, -1.0,1.0, -1.0, -1.0, 1.0, 1.0,
// -1.0, 1.0, 1.0, -1.0, -1.0,1.0, -1.0, -1.0, 1.0, 1.0,};
float result[9];
correlate(ny, nx, data, result);
std::cout<<"result"<<std::endl;
for (int i=0;i<4;i++){
std::cout<<result[i]<<" ";
}
// int nc=20;
// std::vector<std::tuple<int,int,int>> rows((1+nc)*nc/2);
// // #pragma omp parallel for
// for (int ia = 0; ia < nc; ++ia) {
// for (int ja = ia; ja < nc; ++ja) {
// int ija = _pdep_u32(ia, 0x55555555) | _pdep_u32(ja, 0xAAAAAAAA);
// int p= ia*nc-(ia-1)*ia/2;
// std::cout<<p+ja-ia<<std::endl;
// rows[p+(ja-ia)]=std::make_tuple(ija, ia, ja) ;
// }
// }
// std::sort(rows.begin(), rows.end());
// int i=0;
// std::cout<<"result"<<std::endl;
// for(auto row:rows){
// std::cout<< i << ","<<std::get<0>(row) << ":"
// << std::get<1>(row) << ","
// << std::get<2>(row) << std::endl;
// i++;
// }
// double4_t test={0,1,2,3};
// double4_t sw1=swap1(test);
// double4_t sw2=swap2(test);
// for (int i=0;i<4;i++){
// std::cout<<test[i]<<" ";
// }
// std::cout<<"result"<<std::endl;
// for (int i=0;i<4;i++){
// std::cout<<sw1[i]<<" ";
// }
// std::cout<<"result"<<std::endl;
// for (int i=0;i<4;i++){
// std::cout<<sw2[i]<<" ";
// }
return 0;
} | .file "tmpxft_00041049_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4040:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4040:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
.type _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi, @function
_Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi:
.LFB4062:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13correlate_gpuiiPKfPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4062:
.size _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi, .-_Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
.globl _Z13correlate_gpuiiPKfPfi
.type _Z13correlate_gpuiiPKfPfi, @function
_Z13correlate_gpuiiPKfPfi:
.LFB4063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4063:
.size _Z13correlate_gpuiiPKfPfi, .-_Z13correlate_gpuiiPKfPfi
.globl _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
.type _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi, @function
_Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi:
.LFB4064:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17padding_transposeiiPKfPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4064:
.size _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi, .-_Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
.globl _Z17padding_transposeiiPKfPfi
.type _Z17padding_transposeiiPKfPfi, @function
_Z17padding_transposeiiPKfPfi:
.LFB4065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4065:
.size _Z17padding_transposeiiPKfPfi, .-_Z17padding_transposeiiPKfPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17padding_transposeiiPKfPfi"
.LC1:
.string "_Z13correlate_gpuiiPKfPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4067:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17padding_transposeiiPKfPfi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13correlate_gpuiiPKfPfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4380:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L24
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L24:
ret
.cfi_endproc
.LFE4380:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata._Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind.str1.1,"aMS",@progbits,1
.LC2:
.string "CUDA error: "
.section .rodata._Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "cudaMemcpy(target, source, num * sizeof(T), direction)"
.section .rodata._Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind.str1.1
.LC4:
.string ": "
.section .text._Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind,"axG",@progbits,_Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind,comdat
.weak _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind
.type _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind, @function
_Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind:
.LFB4386:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
salq $2, %rdx
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %ebx
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE4386:
.size _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind, .-_Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "cudaMalloc((void**)&dGPU,ny*nx*sizeof(float))"
.align 8
.LC7:
.string "cudaMalloc((void**)&padding,new_ny*nx*sizeof(float))"
.align 8
.LC8:
.string "cudaMalloc((void**)&rGPU,ny*ny*sizeof(float))"
.align 8
.LC9:
.string "cannot create std::vector larger than max_size()"
.section .rodata.str1.1
.LC11:
.string " "
.LC12:
.string "cudaGetLastError()"
.LC13:
.string "----"
.LC14:
.string "cudaFree(dGPU)"
.LC15:
.string "cudaFree(padding)"
.LC16:
.string "cudaFree(rGPU)"
.text
.globl _Z9correlateiiPKfPf
.type _Z9correlateiiPKfPf, @function
_Z9correlateiiPKfPf:
.LFB4036:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4036
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $312, %rsp
.cfi_def_cfa_offset 368
movl %edi, 120(%rsp)
movl %esi, %r15d
movq %rdx, %rbx
movq %rcx, 112(%rsp)
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
leal 510(%rdi), %eax
movl %edi, %edx
addl $255, %edx
cmovns %edx, %eax
movl %eax, %esi
sarl $8, %esi
movl %esi, 124(%rsp)
movb $0, %al
movl %eax, 16(%rsp)
movq $0, 128(%rsp)
movl %edi, %eax
imull %r15d, %eax
cltq
movq %rax, 48(%rsp)
salq $2, %rax
movq %rax, 88(%rsp)
leaq 128(%rsp), %rdi
movq %rax, %rsi
.LEHB0:
call cudaMalloc@PLT
testl %eax, %eax
jne .L142
movq $0, 136(%rsp)
movl 16(%rsp), %eax
imull %r15d, %eax
cltq
movq %rax, 40(%rsp)
salq $2, %rax
movq %rax, 96(%rsp)
leaq 136(%rsp), %rdi
movq %rax, %rsi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L143
movq $0, 144(%rsp)
movl 120(%rsp), %ecx
movl %ecx, %eax
imull %ecx, %eax
cltq
movq %rax, 104(%rsp)
leaq 0(,%rax,4), %rsi
leaq 144(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, 20(%rsp)
testl %eax, %eax
jne .L144
movslq 120(%rsp), %r13
movq %r13, %rax
shrq $61, %rax
jne .L145
testq %r13, %r13
je .L37
leaq 0(,%r13,4), %r14
movq %r14, 56(%rsp)
movq %r14, %rdi
call _Znwm@PLT
.LEHE0:
movq %rax, 64(%rsp)
movq %rax, 176(%rsp)
leaq (%rax,%r14), %rdx
movq %rdx, 192(%rsp)
.L38:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L38
movq %rdx, 184(%rsp)
movq 48(%rsp), %rax
shrq $61, %rax
jne .L146
.L39:
movq $0, 216(%rsp)
movq $0, 224(%rsp)
cmpq $0, 48(%rsp)
je .L41
movq 88(%rsp), %r14
movq %r14, %rdi
.LEHB1:
call _Znwm@PLT
.LEHE1:
jmp .L147
.L142:
movl %eax, %ebp
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L143:
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L144:
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl 20(%rsp), %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L145:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L148
leaq .LC9(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.LEHE2:
.L148:
call __stack_chk_fail@PLT
.L146:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L149
leaq .LC9(%rip), %rdi
.LEHB3:
call _ZSt20__throw_length_errorPKc@PLT
.LEHE3:
.L125:
endbr64
movq %rax, %rbx
jmp .L116
.L149:
call __stack_chk_fail@PLT
.L147:
movq %rax, %rbp
movq %rax, 208(%rsp)
leaq (%rax,%r14), %rdx
movq %rdx, 224(%rsp)
cmpq %rax, %rdx
je .L119
.L43:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L43
.L42:
movq %rdx, 216(%rsp)
movq $0, 248(%rsp)
movq $0, 256(%rsp)
testq %r13, %r13
je .L44
movq 56(%rsp), %r14
movq %r14, %rdi
.LEHB4:
call _Znwm@PLT
.LEHE4:
jmp .L150
.L119:
movq %rax, %rdx
jmp .L42
.L150:
movq %rax, 80(%rsp)
movq %rax, 240(%rsp)
leaq (%rax,%r14), %rdx
movq %rdx, 256(%rsp)
cmpq %rax, %rdx
je .L120
.L46:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L46
.L45:
movq %rdx, 248(%rsp)
movq 40(%rsp), %rax
shrq $61, %rax
jne .L151
movq $0, 280(%rsp)
movq $0, 288(%rsp)
cmpq $0, 40(%rsp)
je .L49
movq 96(%rsp), %r14
movq %r14, %rdi
.LEHB5:
call _Znwm@PLT
jmp .L152
.L120:
movq 80(%rsp), %rdx
jmp .L45
.L151:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L153
leaq .LC9(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.LEHE5:
.L127:
endbr64
movq %rax, %rbx
jmp .L114
.L153:
call __stack_chk_fail@PLT
.L152:
movq %rax, 24(%rsp)
movq %rax, 272(%rsp)
leaq (%rax,%r14), %rdx
movq %rdx, 72(%rsp)
movq %rdx, 288(%rsp)
cmpq %rax, %rdx
je .L121
.L51:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L51
.L50:
movq 72(%rsp), %rax
movq %rax, 280(%rsp)
cmpl $0, 120(%rsp)
jle .L52
movq 64(%rsp), %rdi
movq %rdi, %rcx
salq $2, %r13
leaq 0(%r13,%rdi), %rsi
movl 20(%rsp), %r8d
movslq %r15d, %r9
.L53:
pxor %xmm0, %xmm0
testl %r15d, %r15d
jle .L57
movslq %r8d, %rdx
leaq (%rbx,%rdx,4), %rax
addq %r9, %rdx
leaq (%rbx,%rdx,4), %rdx
pxor %xmm0, %xmm0
.L54:
pxor %xmm1, %xmm1
cvtss2sd (%rax), %xmm1
addsd %xmm1, %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L54
.L57:
pxor %xmm1, %xmm1
cvtsi2sdl %r15d, %xmm1
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rdi)
addq $4, %rdi
addl %r15d, %r8d
cmpq %rdi, %rsi
jne .L53
movl 20(%rsp), %edi
movslq %r15d, %r8
jmp .L55
.L121:
movq 24(%rsp), %rax
movq %rax, 72(%rsp)
jmp .L50
.L61:
addl %r15d, %edi
addq $4, %rcx
cmpq %rcx, %rsi
je .L154
.L55:
testl %r15d, %r15d
jle .L61
movslq %edi, %rdx
leaq 0(,%rdx,4), %rax
addq %r8, %rdx
salq $2, %rdx
.L58:
movss (%rbx,%rax), %xmm0
subss (%rcx), %xmm0
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L58
jmp .L61
.L154:
movq 80(%rsp), %rbx
addq %rbx, %r13
movl 20(%rsp), %r14d
movslq %r15d, %rax
movq %rax, 8(%rsp)
movq %rbx, 32(%rsp)
jmp .L62
.L69:
movq %rbx, %r12
movss (%rbx), %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L140
sqrtss %xmm0, %xmm0
.L66:
movss %xmm0, (%r12)
addq $4, %rbx
addl %r15d, %r14d
cmpq %rbx, %r13
je .L123
.L62:
testl %r15d, %r15d
jle .L69
movslq %r14d, %rdx
leaq 0(%rbp,%rdx,4), %rax
movq 8(%rsp), %rcx
addq %rcx, %rdx
leaq 0(%rbp,%rdx,4), %rdx
.L63:
pxor %xmm1, %xmm1
cvtss2sd (%rax), %xmm1
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
addq $4, %rax
cmpq %rax, %rdx
jne .L63
jmp .L69
.L140:
call sqrtf@PLT
jmp .L66
.L73:
addq $4, %r12
addl %r15d, %ecx
cmpq %r13, %r12
je .L155
.L67:
testl %r15d, %r15d
jle .L73
movslq %ecx, %rdx
leaq 0(%rbp,%rdx,4), %rax
addq %rsi, %rdx
leaq 0(%rbp,%rdx,4), %rdx
.L70:
movss (%rax), %xmm0
divss (%r12), %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L70
jmp .L73
.L123:
movq 32(%rsp), %r12
movl 20(%rsp), %ecx
movslq %r15d, %rsi
jmp .L67
.L156:
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
.LEHB6:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r13
je .L80
.L74:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L156
.L80:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L157
cmpb $0, 56(%rbx)
je .L77
movzbl 67(%rbx), %esi
.L78:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
jmp .L158
.L157:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L159
call _ZSt16__throw_bad_castv@PLT
.L128:
endbr64
movq %rax, %rbx
leaq 272(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L114:
leaq 240(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L115:
leaq 208(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L116:
leaq 176(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 296(%rsp), %rax
subq %fs:40, %rax
je .L117
call __stack_chk_fail@PLT
.L159:
call __stack_chk_fail@PLT
.L77:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L78
.L158:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, 8(%rsp)
movl 8(%rsp), %eax
addl %r15d, 20(%rsp)
cmpl %eax, 120(%rsp)
je .L52
.L71:
testl %r15d, %r15d
jle .L80
movslq 20(%rsp), %rax
leaq 0(%rbp,%rax,4), %rbx
movq 32(%rsp), %rcx
addq %rcx, %rax
leaq 0(%rbp,%rax,4), %r13
jmp .L74
.L155:
movl $0, 8(%rsp)
movslq %r15d, %rax
movq %rax, 32(%rsp)
leaq _ZSt4cout(%rip), %r12
leaq .LC11(%rip), %r14
jmp .L71
.L52:
movl $1, %ecx
movq 48(%rsp), %rdx
movq %rbp, %rsi
movq 128(%rsp), %rdi
call _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind
movl $64, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl 16(%rsp), %ebx
movl %ebx, 168(%rsp)
movl $1, 172(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 152(%rsp), %rdx
movl $1, %ecx
movq 164(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L81
movl %ebx, %r8d
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movl %r15d, %esi
movl 120(%rsp), %edi
call _Z43__device_stub__Z17padding_transposeiiPKfPfiiiPKfPfi
.L81:
call cudaGetLastError@PLT
movl %eax, 20(%rsp)
testl %eax, %eax
jne .L160
movl $2, %ecx
movq 40(%rsp), %rdx
movq 136(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind
jmp .L161
.L160:
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl 20(%rsp), %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L161:
movl 16(%rsp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L162
cmpb $0, 56(%r12)
je .L85
movzbl 67(%r12), %eax
.L86:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L163
.L162:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L164
call _ZSt16__throw_bad_castv@PLT
.L164:
call __stack_chk_fail@PLT
.L85:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
jmp .L86
.L163:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 72(%rsp), %rsi
movq 24(%rsp), %rax
subq %rax, %rsi
sarq $2, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L165
cmpb $0, 56(%r12)
je .L89
movzbl 67(%r12), %eax
.L90:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L166
.L165:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L167
call _ZSt16__throw_bad_castv@PLT
.L167:
call __stack_chk_fail@PLT
.L89:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
jmp .L90
.L166:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
testl %r15d, %r15d
jle .L91
movl 16(%rsp), %eax
leal -1(%rax), %eax
movq %rax, 32(%rsp)
movl $0, 8(%rsp)
leaq _ZSt4cout(%rip), %r12
leaq .LC11(%rip), %r14
jmp .L92
.L168:
movq %rax, %rdi
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
je .L103
.L93:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L168
.L103:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L169
cmpb $0, 56(%rbx)
je .L96
movzbl 67(%rbx), %esi
.L97:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
jmp .L170
.L169:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L171
call _ZSt16__throw_bad_castv@PLT
.L171:
call __stack_chk_fail@PLT
.L96:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L97
.L170:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %rax, %rbx
movl $4, %edx
leaq .LC13(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r13
testq %r13, %r13
je .L172
cmpb $0, 56(%r13)
je .L100
movzbl 67(%r13), %esi
.L101:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
jmp .L173
.L172:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L174
call _ZSt16__throw_bad_castv@PLT
.L174:
call __stack_chk_fail@PLT
.L100:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L101
.L173:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, 8(%rsp)
movl 8(%rsp), %eax
movl 16(%rsp), %esi
addl %esi, 20(%rsp)
cmpl %eax, %r15d
je .L91
.L92:
cmpl $0, 16(%rsp)
jle .L103
movslq 20(%rsp), %rax
movq 24(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 32(%rsp), %rsi
addq %rsi, %rax
leaq 4(%rcx,%rax,4), %r13
jmp .L93
.L91:
movl $16, 152(%rsp)
movl $16, 156(%rsp)
movl $1, 160(%rsp)
movl 124(%rsp), %eax
movl %eax, 164(%rsp)
movl %eax, 168(%rsp)
movl $1, 172(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 152(%rsp), %rdx
movl $1, %ecx
movq 164(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L104
movl 16(%rsp), %r8d
movq 144(%rsp), %rcx
movq 136(%rsp), %rdx
movl %r15d, %esi
movl 120(%rsp), %edi
call _Z39__device_stub__Z13correlate_gpuiiPKfPfiiiPKfPfi
.L104:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L175
movl $2, %ecx
movq 104(%rsp), %rdx
movq 144(%rsp), %rsi
movq 112(%rsp), %rdi
call _Z11cuda_memcpyIfEvPT_PKS0_m14cudaMemcpyKind
jmp .L176
.L175:
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L176:
movq 128(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L177
movq 136(%rsp), %rdi
call cudaFree@PLT
jmp .L178
.L177:
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC14(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L178:
movl %eax, %ebx
testl %eax, %eax
jne .L179
movq 144(%rsp), %rdi
call cudaFree@PLT
jmp .L180
.L179:
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC15(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L180:
movl %eax, %ebx
testl %eax, %eax
jne .L181
movq 24(%rsp), %rax
testq %rax, %rax
je .L109
movq 96(%rsp), %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
.L109:
movq 80(%rsp), %rax
testq %rax, %rax
je .L110
movq 56(%rsp), %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
.L110:
testq %rbp, %rbp
je .L111
movq 88(%rsp), %rsi
movq %rbp, %rdi
call _ZdlPvm@PLT
.L111:
movq 64(%rsp), %rax
testq %rax, %rax
je .L31
movq 56(%rsp), %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
.L31:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L182
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L181:
.cfi_restore_state
leaq .LC2(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC16(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE6:
movl $1, %edi
call exit@PLT
.L126:
endbr64
movq %rax, %rbx
jmp .L115
.L117:
movq %rbx, %rdi
.LEHB7:
call _Unwind_Resume@PLT
.LEHE7:
.L49:
movq $0, 272(%rsp)
movq $0, 288(%rsp)
movq $0, 24(%rsp)
movq $0, 72(%rsp)
jmp .L50
.L44:
movq $0, 240(%rsp)
movq 56(%rsp), %rax
movq %rax, 256(%rsp)
movq $0, 80(%rsp)
movl $0, %edx
jmp .L45
.L41:
movq $0, 208(%rsp)
movq $0, 224(%rsp)
movl $0, %ebp
movl $0, %edx
jmp .L42
.L37:
movq $0, 176(%rsp)
movq $0, 192(%rsp)
movq $0, 184(%rsp)
movq %r13, 56(%rsp)
movq $0, 64(%rsp)
jmp .L39
.L182:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4036:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4036:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4036-.LLSDACSB4036
.LLSDACSB4036:
.uleb128 .LEHB0-.LFB4036
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4036
.uleb128 .LEHE1-.LEHB1
.uleb128 .L125-.LFB4036
.uleb128 0
.uleb128 .LEHB2-.LFB4036
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4036
.uleb128 .LEHE3-.LEHB3
.uleb128 .L125-.LFB4036
.uleb128 0
.uleb128 .LEHB4-.LFB4036
.uleb128 .LEHE4-.LEHB4
.uleb128 .L126-.LFB4036
.uleb128 0
.uleb128 .LEHB5-.LFB4036
.uleb128 .LEHE5-.LEHB5
.uleb128 .L127-.LFB4036
.uleb128 0
.uleb128 .LEHB6-.LFB4036
.uleb128 .LEHE6-.LEHB6
.uleb128 .L128-.LFB4036
.uleb128 0
.uleb128 .LEHB7-.LFB4036
.uleb128 .LEHE7-.LEHB7
.uleb128 0
.uleb128 0
.LLSDACSE4036:
.text
.size _Z9correlateiiPKfPf, .-_Z9correlateiiPKfPf
.section .rodata.str1.1
.LC19:
.string "result"
.text
.globl main
.type main, @function
main:
.LFB4037:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movss .LC17(%rip), %xmm1
movss %xmm1, (%rsp)
movss .LC18(%rip), %xmm0
movss %xmm0, 4(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm0, 20(%rsp)
leaq 32(%rsp), %rbx
movq %rsp, %rdx
movq %rbx, %rcx
movl $2, %esi
movl $3, %edi
call _Z9correlateiiPKfPf
leaq .LC19(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 48(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC11(%rip), %rbp
.L184:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r13
jne .L184
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L188
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L188:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4037:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC17:
.long -1082130432
.align 4
.LC18:
.long 1065353216
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
This is the function you need to implement. Quick reference:
- input rows: 0 <= y < ny
- input columns: 0 <= x < nx
- element at row y and column x is stored in data[x + y*nx]
- correlation between rows i and row j has to be stored in result[i + j*ny]
- only parts with 0 <= j <= i < ny need to be filled
*/
#include <cuda_runtime.h>
#include "device_launch_parameters.h"
#include <iostream>
#include <math.h>
#include <vector>
static inline void check(cudaError_t err, const char* context) {
if (err != cudaSuccess) {
std::cerr << "CUDA error: " << context << ": "
<< cudaGetErrorString(err) << std::endl;
std::exit(EXIT_FAILURE);
}
}
#define CHECK(x) check(x, #x)
template <class T>
void cuda_memcpy(T* target, const T* source, std::size_t num, cudaMemcpyKind direction) {
CHECK(cudaMemcpy(target, source, num * sizeof(T), direction));
}
// params:
// data : transposed padding data
__global__ void correlate_gpu(int ny, int nx, const float*data, float *result, int new_ny){
const int nd=16;// nd: nd==blockDim.x==blockDim.y
// compute nd*nd results each thread.
int step=nd*nd;// each block will compute step*step results.
int ia=threadIdx.x;
int ja=threadIdx.y;
int ic=blockIdx.x;
int jc=blockIdx.y;
// int i=threadIdx.x+blockIdx.x*blockDim.x;
// int j=threadIdx.y+blockIdx.y*blockDim.y;
// if(i>=ny || j>=ny) return;
// if (i>j){
// result[i*ny+j]=0;
// return;
// }
float v[nd][nd];
// double temp=0;
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]=0;
}
}
for (int k=0; k<nx; ++k){
float x[nd];
float y[nd];
for(int ib=0; ib<nd; ib++){
int i=ic*step+ib*nd+ia;
x[ib]=data[k*new_ny +i];
}
for(int jb=0; jb<nd; jb++){
int j=jc*step+jb*nd+ja;
y[jb]=data[k*new_ny+j];
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]+=x[ib]*y[jb];
}
}
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
int i=ic*step+ib*nd+ia;
int j=jc*step+jb*nd+ja;
if(i<ny&&j<ny&&i<=j){
result[ny*i+j]=v[ib][jb];
}
}
}
// result[i*ny+j]=temp;
}
__global__ void padding_transpose(int ny, int nx, const float*data, float* result, int new_ny){
//result is padding and transpose data
int ja=threadIdx.x;
int i=blockIdx.y;
for (int jb=0; jb<nx; jb+=blockDim.x){
int j=jb+ja;
if (j>=nx) break;
float v=i<ny?data[i*ny+j]:0; //padding
result[new_ny*j+i]=v; //transpose
}
}
static inline int divup(int a, int b) {
return (a + b - 1)/b;
}
static inline int roundup(int a, int b) {
return divup(a, b) * b;
}
void correlate(int ny, int nx, const float *data, float *result) {
// const int nd=16;//compute nd*nd results each thread. could not less than
const int block_size=16; //16*16 threads
const int step=block_size*block_size; // each block will compute step*step results.
int new_ny=roundup(ny,step);
//allocate memory & copy data to GPU
float *dGPU=NULL;
CHECK(cudaMalloc((void**)&dGPU,ny*nx*sizeof(float)));
float *padding=NULL;
CHECK(cudaMalloc((void**)&padding,new_ny*nx*sizeof(float)));
float *rGPU=NULL;
CHECK(cudaMalloc((void**)&rGPU,ny*ny*sizeof(float)));
// float *avg=new float[ny]{0};
// float *normalized=new float[ny*nx]{0};
// float *sqrtSqureSum=new float[ny]{0};
std::vector<float> avg(ny,0);
std::vector<float> normalized(ny*nx,0);
std::vector<float> sqrtSqureSum(ny,0);
std::vector<float> transposed(nx*new_ny,0);
for (int y=0; y<ny; ++y){
double temp=0;
for (int x=0; x<nx; ++x){
temp+=data[y*nx+x];
}
avg[y]=temp/nx;
}
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
normalized[y*nx+x]=data[y*nx+x]-avg[y];
}
}
// delete[] avg;
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
sqrtSqureSum[y]+=pow(normalized[y*nx+x],2);
}
sqrtSqureSum[y]=sqrt(sqrtSqureSum[y]);
}
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
normalized[y*nx+x]/=sqrtSqureSum[y];
}
}
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
std::cout << normalized[y*nx+x] << " ";
}
std::cout<< std::endl ;
}
cuda_memcpy(dGPU,normalized.data(),ny*nx,cudaMemcpyHostToDevice);
// Run kernel to padding and transpose
{
dim3 dimBlock(64,1);
dim3 dimGrid(1,new_ny);
padding_transpose<<<dimGrid,dimBlock>>>(ny,nx,dGPU,padding,new_ny);
CHECK(cudaGetLastError());
}
cuda_memcpy(transposed.data(), padding, new_ny * nx, cudaMemcpyDeviceToHost);
std::cout << new_ny<<std::endl;
std::cout << transposed.size()<<std::endl;
for(int x=0;x<nx;x++){
for(int y=0;y<new_ny;y++){
std::cout<< transposed[x*new_ny+y] << " ";
}
std::cout<< std::endl<< "----"<< std::endl;
}
// for (int x=0;x<nx;++x){
// for (int y=0; y<ny; ++y){
// transposed[x*ny+y]=normalized[y*nx+x];
// }
// }
// Run kernel to calculate cp
{
dim3 dimBlock(block_size,block_size);
dim3 dimGrid(new_ny/step,new_ny/step);
correlate_gpu<<<dimGrid,dimBlock>>>(ny,nx,padding,rGPU,new_ny);
CHECK(cudaGetLastError());
}
cuda_memcpy(result, rGPU, ny * ny, cudaMemcpyDeviceToHost);
// CHECK(cudaMemcpy(result, rGPU, ny * ny * sizeof(float), cudaMemcpyDeviceToHost));
CHECK(cudaFree(dGPU));
CHECK(cudaFree(padding));
CHECK(cudaFree(rGPU));
// delete[] normalized;
}
int main(){
int ny=3;
int nx=2;
// float data[]={+0.81472367, +0.90579194,
// +0.45150527, +0.49610928}; //result: 1 1 0 1
float data[]={
-1.00000000, +1.00000000,
+1.00000000, -1.00000000,
-1.00000000, +1.00000000
};
// float data[]={-1.0, 1.0, 1.0, -1.0, -1.0,1.0, -1.0, -1.0, 1.0, 1.0,
// -1.0, 1.0, 1.0, -1.0, -1.0,1.0, -1.0, -1.0, 1.0, 1.0,};
float result[9];
correlate(ny, nx, data, result);
std::cout<<"result"<<std::endl;
for (int i=0;i<4;i++){
std::cout<<result[i]<<" ";
}
// int nc=20;
// std::vector<std::tuple<int,int,int>> rows((1+nc)*nc/2);
// // #pragma omp parallel for
// for (int ia = 0; ia < nc; ++ia) {
// for (int ja = ia; ja < nc; ++ja) {
// int ija = _pdep_u32(ia, 0x55555555) | _pdep_u32(ja, 0xAAAAAAAA);
// int p= ia*nc-(ia-1)*ia/2;
// std::cout<<p+ja-ia<<std::endl;
// rows[p+(ja-ia)]=std::make_tuple(ija, ia, ja) ;
// }
// }
// std::sort(rows.begin(), rows.end());
// int i=0;
// std::cout<<"result"<<std::endl;
// for(auto row:rows){
// std::cout<< i << ","<<std::get<0>(row) << ":"
// << std::get<1>(row) << ","
// << std::get<2>(row) << std::endl;
// i++;
// }
// double4_t test={0,1,2,3};
// double4_t sw1=swap1(test);
// double4_t sw2=swap2(test);
// for (int i=0;i<4;i++){
// std::cout<<test[i]<<" ";
// }
// std::cout<<"result"<<std::endl;
// for (int i=0;i<4;i++){
// std::cout<<sw1[i]<<" ";
// }
// std::cout<<"result"<<std::endl;
// for (int i=0;i<4;i++){
// std::cout<<sw2[i]<<" ";
// }
return 0;
} | /*
This is the function you need to implement. Quick reference:
- input rows: 0 <= y < ny
- input columns: 0 <= x < nx
- element at row y and column x is stored in data[x + y*nx]
- correlation between rows i and row j has to be stored in result[i + j*ny]
- only parts with 0 <= j <= i < ny need to be filled
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <vector>
static inline void check(hipError_t err, const char* context) {
if (err != hipSuccess) {
std::cerr << "CUDA error: " << context << ": "
<< hipGetErrorString(err) << std::endl;
std::exit(EXIT_FAILURE);
}
}
#define CHECK(x) check(x, #x)
template <class T>
void cuda_memcpy(T* target, const T* source, std::size_t num, hipMemcpyKind direction) {
CHECK(hipMemcpy(target, source, num * sizeof(T), direction));
}
// params:
// data : transposed padding data
__global__ void correlate_gpu(int ny, int nx, const float*data, float *result, int new_ny){
const int nd=16;// nd: nd==blockDim.x==blockDim.y
// compute nd*nd results each thread.
int step=nd*nd;// each block will compute step*step results.
int ia=threadIdx.x;
int ja=threadIdx.y;
int ic=blockIdx.x;
int jc=blockIdx.y;
// int i=threadIdx.x+blockIdx.x*blockDim.x;
// int j=threadIdx.y+blockIdx.y*blockDim.y;
// if(i>=ny || j>=ny) return;
// if (i>j){
// result[i*ny+j]=0;
// return;
// }
float v[nd][nd];
// double temp=0;
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]=0;
}
}
for (int k=0; k<nx; ++k){
float x[nd];
float y[nd];
for(int ib=0; ib<nd; ib++){
int i=ic*step+ib*nd+ia;
x[ib]=data[k*new_ny +i];
}
for(int jb=0; jb<nd; jb++){
int j=jc*step+jb*nd+ja;
y[jb]=data[k*new_ny+j];
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]+=x[ib]*y[jb];
}
}
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
int i=ic*step+ib*nd+ia;
int j=jc*step+jb*nd+ja;
if(i<ny&&j<ny&&i<=j){
result[ny*i+j]=v[ib][jb];
}
}
}
// result[i*ny+j]=temp;
}
__global__ void padding_transpose(int ny, int nx, const float*data, float* result, int new_ny){
//result is padding and transpose data
int ja=threadIdx.x;
int i=blockIdx.y;
for (int jb=0; jb<nx; jb+=blockDim.x){
int j=jb+ja;
if (j>=nx) break;
float v=i<ny?data[i*ny+j]:0; //padding
result[new_ny*j+i]=v; //transpose
}
}
static inline int divup(int a, int b) {
return (a + b - 1)/b;
}
static inline int roundup(int a, int b) {
return divup(a, b) * b;
}
void correlate(int ny, int nx, const float *data, float *result) {
// const int nd=16;//compute nd*nd results each thread. could not less than
const int block_size=16; //16*16 threads
const int step=block_size*block_size; // each block will compute step*step results.
int new_ny=roundup(ny,step);
//allocate memory & copy data to GPU
float *dGPU=NULL;
CHECK(hipMalloc((void**)&dGPU,ny*nx*sizeof(float)));
float *padding=NULL;
CHECK(hipMalloc((void**)&padding,new_ny*nx*sizeof(float)));
float *rGPU=NULL;
CHECK(hipMalloc((void**)&rGPU,ny*ny*sizeof(float)));
// float *avg=new float[ny]{0};
// float *normalized=new float[ny*nx]{0};
// float *sqrtSqureSum=new float[ny]{0};
std::vector<float> avg(ny,0);
std::vector<float> normalized(ny*nx,0);
std::vector<float> sqrtSqureSum(ny,0);
std::vector<float> transposed(nx*new_ny,0);
for (int y=0; y<ny; ++y){
double temp=0;
for (int x=0; x<nx; ++x){
temp+=data[y*nx+x];
}
avg[y]=temp/nx;
}
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
normalized[y*nx+x]=data[y*nx+x]-avg[y];
}
}
// delete[] avg;
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
sqrtSqureSum[y]+=pow(normalized[y*nx+x],2);
}
sqrtSqureSum[y]=sqrt(sqrtSqureSum[y]);
}
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
normalized[y*nx+x]/=sqrtSqureSum[y];
}
}
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
std::cout << normalized[y*nx+x] << " ";
}
std::cout<< std::endl ;
}
cuda_memcpy(dGPU,normalized.data(),ny*nx,hipMemcpyHostToDevice);
// Run kernel to padding and transpose
{
dim3 dimBlock(64,1);
dim3 dimGrid(1,new_ny);
padding_transpose<<<dimGrid,dimBlock>>>(ny,nx,dGPU,padding,new_ny);
CHECK(hipGetLastError());
}
cuda_memcpy(transposed.data(), padding, new_ny * nx, hipMemcpyDeviceToHost);
std::cout << new_ny<<std::endl;
std::cout << transposed.size()<<std::endl;
for(int x=0;x<nx;x++){
for(int y=0;y<new_ny;y++){
std::cout<< transposed[x*new_ny+y] << " ";
}
std::cout<< std::endl<< "----"<< std::endl;
}
// for (int x=0;x<nx;++x){
// for (int y=0; y<ny; ++y){
// transposed[x*ny+y]=normalized[y*nx+x];
// }
// }
// Run kernel to calculate cp
{
dim3 dimBlock(block_size,block_size);
dim3 dimGrid(new_ny/step,new_ny/step);
correlate_gpu<<<dimGrid,dimBlock>>>(ny,nx,padding,rGPU,new_ny);
CHECK(hipGetLastError());
}
cuda_memcpy(result, rGPU, ny * ny, hipMemcpyDeviceToHost);
// CHECK(cudaMemcpy(result, rGPU, ny * ny * sizeof(float), cudaMemcpyDeviceToHost));
CHECK(hipFree(dGPU));
CHECK(hipFree(padding));
CHECK(hipFree(rGPU));
// delete[] normalized;
}
int main(){
int ny=3;
int nx=2;
// float data[]={+0.81472367, +0.90579194,
// +0.45150527, +0.49610928}; //result: 1 1 0 1
float data[]={
-1.00000000, +1.00000000,
+1.00000000, -1.00000000,
-1.00000000, +1.00000000
};
// float data[]={-1.0, 1.0, 1.0, -1.0, -1.0,1.0, -1.0, -1.0, 1.0, 1.0,
// -1.0, 1.0, 1.0, -1.0, -1.0,1.0, -1.0, -1.0, 1.0, 1.0,};
float result[9];
correlate(ny, nx, data, result);
std::cout<<"result"<<std::endl;
for (int i=0;i<4;i++){
std::cout<<result[i]<<" ";
}
// int nc=20;
// std::vector<std::tuple<int,int,int>> rows((1+nc)*nc/2);
// // #pragma omp parallel for
// for (int ia = 0; ia < nc; ++ia) {
// for (int ja = ia; ja < nc; ++ja) {
// int ija = _pdep_u32(ia, 0x55555555) | _pdep_u32(ja, 0xAAAAAAAA);
// int p= ia*nc-(ia-1)*ia/2;
// std::cout<<p+ja-ia<<std::endl;
// rows[p+(ja-ia)]=std::make_tuple(ija, ia, ja) ;
// }
// }
// std::sort(rows.begin(), rows.end());
// int i=0;
// std::cout<<"result"<<std::endl;
// for(auto row:rows){
// std::cout<< i << ","<<std::get<0>(row) << ":"
// << std::get<1>(row) << ","
// << std::get<2>(row) << std::endl;
// i++;
// }
// double4_t test={0,1,2,3};
// double4_t sw1=swap1(test);
// double4_t sw2=swap2(test);
// for (int i=0;i<4;i++){
// std::cout<<test[i]<<" ";
// }
// std::cout<<"result"<<std::endl;
// for (int i=0;i<4;i++){
// std::cout<<sw1[i]<<" ";
// }
// std::cout<<"result"<<std::endl;
// for (int i=0;i<4;i++){
// std::cout<<sw2[i]<<" ";
// }
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
This is the function you need to implement. Quick reference:
- input rows: 0 <= y < ny
- input columns: 0 <= x < nx
- element at row y and column x is stored in data[x + y*nx]
- correlation between rows i and row j has to be stored in result[i + j*ny]
- only parts with 0 <= j <= i < ny need to be filled
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <vector>
static inline void check(hipError_t err, const char* context) {
if (err != hipSuccess) {
std::cerr << "CUDA error: " << context << ": "
<< hipGetErrorString(err) << std::endl;
std::exit(EXIT_FAILURE);
}
}
#define CHECK(x) check(x, #x)
template <class T>
void cuda_memcpy(T* target, const T* source, std::size_t num, hipMemcpyKind direction) {
CHECK(hipMemcpy(target, source, num * sizeof(T), direction));
}
// params:
// data : transposed padding data
__global__ void correlate_gpu(int ny, int nx, const float*data, float *result, int new_ny){
const int nd=16;// nd: nd==blockDim.x==blockDim.y
// compute nd*nd results each thread.
int step=nd*nd;// each block will compute step*step results.
int ia=threadIdx.x;
int ja=threadIdx.y;
int ic=blockIdx.x;
int jc=blockIdx.y;
// int i=threadIdx.x+blockIdx.x*blockDim.x;
// int j=threadIdx.y+blockIdx.y*blockDim.y;
// if(i>=ny || j>=ny) return;
// if (i>j){
// result[i*ny+j]=0;
// return;
// }
float v[nd][nd];
// double temp=0;
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]=0;
}
}
for (int k=0; k<nx; ++k){
float x[nd];
float y[nd];
for(int ib=0; ib<nd; ib++){
int i=ic*step+ib*nd+ia;
x[ib]=data[k*new_ny +i];
}
for(int jb=0; jb<nd; jb++){
int j=jc*step+jb*nd+ja;
y[jb]=data[k*new_ny+j];
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
v[ib][jb]+=x[ib]*y[jb];
}
}
}
for(int ib=0; ib<nd; ib++){
for(int jb=0; jb<nd; jb++){
int i=ic*step+ib*nd+ia;
int j=jc*step+jb*nd+ja;
if(i<ny&&j<ny&&i<=j){
result[ny*i+j]=v[ib][jb];
}
}
}
// result[i*ny+j]=temp;
}
__global__ void padding_transpose(int ny, int nx, const float*data, float* result, int new_ny){
//result is padding and transpose data
int ja=threadIdx.x;
int i=blockIdx.y;
for (int jb=0; jb<nx; jb+=blockDim.x){
int j=jb+ja;
if (j>=nx) break;
float v=i<ny?data[i*ny+j]:0; //padding
result[new_ny*j+i]=v; //transpose
}
}
static inline int divup(int a, int b) {
return (a + b - 1)/b;
}
static inline int roundup(int a, int b) {
return divup(a, b) * b;
}
void correlate(int ny, int nx, const float *data, float *result) {
// const int nd=16;//compute nd*nd results each thread. could not less than
const int block_size=16; //16*16 threads
const int step=block_size*block_size; // each block will compute step*step results.
int new_ny=roundup(ny,step);
//allocate memory & copy data to GPU
float *dGPU=NULL;
CHECK(hipMalloc((void**)&dGPU,ny*nx*sizeof(float)));
float *padding=NULL;
CHECK(hipMalloc((void**)&padding,new_ny*nx*sizeof(float)));
float *rGPU=NULL;
CHECK(hipMalloc((void**)&rGPU,ny*ny*sizeof(float)));
// float *avg=new float[ny]{0};
// float *normalized=new float[ny*nx]{0};
// float *sqrtSqureSum=new float[ny]{0};
std::vector<float> avg(ny,0);
std::vector<float> normalized(ny*nx,0);
std::vector<float> sqrtSqureSum(ny,0);
std::vector<float> transposed(nx*new_ny,0);
for (int y=0; y<ny; ++y){
double temp=0;
for (int x=0; x<nx; ++x){
temp+=data[y*nx+x];
}
avg[y]=temp/nx;
}
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
normalized[y*nx+x]=data[y*nx+x]-avg[y];
}
}
// delete[] avg;
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
sqrtSqureSum[y]+=pow(normalized[y*nx+x],2);
}
sqrtSqureSum[y]=sqrt(sqrtSqureSum[y]);
}
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
normalized[y*nx+x]/=sqrtSqureSum[y];
}
}
for (int y=0; y<ny; ++y){
for (int x=0; x<nx; ++x){
std::cout << normalized[y*nx+x] << " ";
}
std::cout<< std::endl ;
}
cuda_memcpy(dGPU,normalized.data(),ny*nx,hipMemcpyHostToDevice);
// Run kernel to padding and transpose
{
dim3 dimBlock(64,1);
dim3 dimGrid(1,new_ny);
padding_transpose<<<dimGrid,dimBlock>>>(ny,nx,dGPU,padding,new_ny);
CHECK(hipGetLastError());
}
cuda_memcpy(transposed.data(), padding, new_ny * nx, hipMemcpyDeviceToHost);
std::cout << new_ny<<std::endl;
std::cout << transposed.size()<<std::endl;
for(int x=0;x<nx;x++){
for(int y=0;y<new_ny;y++){
std::cout<< transposed[x*new_ny+y] << " ";
}
std::cout<< std::endl<< "----"<< std::endl;
}
// for (int x=0;x<nx;++x){
// for (int y=0; y<ny; ++y){
// transposed[x*ny+y]=normalized[y*nx+x];
// }
// }
// Run kernel to calculate cp
{
dim3 dimBlock(block_size,block_size);
dim3 dimGrid(new_ny/step,new_ny/step);
correlate_gpu<<<dimGrid,dimBlock>>>(ny,nx,padding,rGPU,new_ny);
CHECK(hipGetLastError());
}
cuda_memcpy(result, rGPU, ny * ny, hipMemcpyDeviceToHost);
// CHECK(cudaMemcpy(result, rGPU, ny * ny * sizeof(float), cudaMemcpyDeviceToHost));
CHECK(hipFree(dGPU));
CHECK(hipFree(padding));
CHECK(hipFree(rGPU));
// delete[] normalized;
}
int main(){
int ny=3;
int nx=2;
// float data[]={+0.81472367, +0.90579194,
// +0.45150527, +0.49610928}; //result: 1 1 0 1
float data[]={
-1.00000000, +1.00000000,
+1.00000000, -1.00000000,
-1.00000000, +1.00000000
};
// float data[]={-1.0, 1.0, 1.0, -1.0, -1.0,1.0, -1.0, -1.0, 1.0, 1.0,
// -1.0, 1.0, 1.0, -1.0, -1.0,1.0, -1.0, -1.0, 1.0, 1.0,};
float result[9];
correlate(ny, nx, data, result);
std::cout<<"result"<<std::endl;
for (int i=0;i<4;i++){
std::cout<<result[i]<<" ";
}
// int nc=20;
// std::vector<std::tuple<int,int,int>> rows((1+nc)*nc/2);
// // #pragma omp parallel for
// for (int ia = 0; ia < nc; ++ia) {
// for (int ja = ia; ja < nc; ++ja) {
// int ija = _pdep_u32(ia, 0x55555555) | _pdep_u32(ja, 0xAAAAAAAA);
// int p= ia*nc-(ia-1)*ia/2;
// std::cout<<p+ja-ia<<std::endl;
// rows[p+(ja-ia)]=std::make_tuple(ija, ia, ja) ;
// }
// }
// std::sort(rows.begin(), rows.end());
// int i=0;
// std::cout<<"result"<<std::endl;
// for(auto row:rows){
// std::cout<< i << ","<<std::get<0>(row) << ":"
// << std::get<1>(row) << ","
// << std::get<2>(row) << std::endl;
// i++;
// }
// double4_t test={0,1,2,3};
// double4_t sw1=swap1(test);
// double4_t sw2=swap2(test);
// for (int i=0;i<4;i++){
// std::cout<<test[i]<<" ";
// }
// std::cout<<"result"<<std::endl;
// for (int i=0;i<4;i++){
// std::cout<<sw1[i]<<" ";
// }
// std::cout<<"result"<<std::endl;
// for (int i=0;i<4;i++){
// std::cout<<sw2[i]<<" ";
// }
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13correlate_gpuiiPKfPfi
.globl _Z13correlate_gpuiiPKfPfi
.p2align 8
.type _Z13correlate_gpuiiPKfPfi,@function
_Z13correlate_gpuiiPKfPfi:
v_dual_mov_b32 v1, 16 :: v_dual_mov_b32 v2, 0
s_mov_b32 s2, 0
.LBB0_1:
s_mov_b32 s3, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v3, s3, v1
s_add_i32 s3, s3, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 64
scratch_store_b32 v3, v2, off
s_cbranch_scc0 .LBB0_2
v_add_nc_u32_e32 v1, 64, v1
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 16
s_cbranch_scc0 .LBB0_1
s_load_b32 s6, s[0:1], 0x4
v_and_b32_e32 v35, 0x3ff, v0
v_bfe_u32 v34, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_15
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s7, s[0:1], 0x18
v_lshl_add_u32 v36, s14, 8, v35
v_lshl_add_u32 v37, s15, 8, v34
s_mov_b32 s8, 0
.LBB0_6:
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v32, v36
s_mov_b64 s[4:5], 0
.LBB0_7:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v33, 31, v32
s_mov_b32 m0, s4
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s4, 16
v_lshlrev_b64 v[38:39], 2, v[32:33]
v_add_nc_u32_e32 v32, 16, v32
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v38, vcc_lo, s2, v38
v_add_co_ci_u32_e32 v39, vcc_lo, s3, v39, vcc_lo
global_load_b32 v33, v[38:39], off
s_waitcnt vmcnt(0)
v_movreld_b32_e32 v0, v33
s_cbranch_scc0 .LBB0_7
v_mov_b32_e32 v32, v37
s_mov_b64 s[4:5], 0
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v33, 31, v32
s_mov_b32 m0, s4
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s4, 16
v_lshlrev_b64 v[38:39], 2, v[32:33]
v_add_nc_u32_e32 v32, 16, v32
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v38, vcc_lo, s2, v38
v_add_co_ci_u32_e32 v39, vcc_lo, s3, v39, vcc_lo
global_load_b32 v33, v[38:39], off
s_waitcnt vmcnt(0)
v_movreld_b32_e32 v16, v33
s_cbranch_scc1 .LBB0_9
v_mov_b32_e32 v32, 16
s_mov_b32 s9, 0
.p2align 6
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mov_b32 m0, s9
v_mov_b32_e32 v38, v32
v_movrels_b32_e32 v33, v0
s_mov_b64 s[4:5], 0
.LBB0_12:
scratch_load_b32 v39, v38, off
s_mov_b32 m0, s4
s_add_u32 s4, s4, 1
v_movrels_b32_e32 v40, v16
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s4, 16
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v39, v33, v40
scratch_store_b32 v38, v39, off
v_add_nc_u32_e32 v38, 4, v38
s_cbranch_scc0 .LBB0_12
v_add_nc_u32_e32 v32, 64, v32
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, 16
s_cbranch_scc0 .LBB0_11
v_add_nc_u32_e32 v36, s7, v36
v_add_nc_u32_e32 v37, s7, v37
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s6
s_cbranch_scc0 .LBB0_6
.LBB0_15:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_lshl_add_u32 v0, s14, 8, v35
v_lshl_add_u32 v2, s15, 8, v34
v_mov_b32_e32 v3, 16
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, s4, v0
s_lshl_b32 s1, s4, 4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_17
.p2align 6
.LBB0_16:
v_add_nc_u32_e32 v1, s1, v1
v_add_nc_u32_e32 v3, 64, v3
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 16
s_cbranch_scc1 .LBB0_21
.LBB0_17:
v_lshl_add_u32 v4, s5, 4, v0
v_mov_b32_e32 v5, v2
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s4, v4
s_xor_b32 s6, vcc_lo, -1
s_branch .LBB0_19
.p2align 6
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v5, 16, v5
s_add_i32 s7, s7, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, 64
s_cbranch_scc1 .LBB0_16
.LBB0_19:
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v5
v_cmp_le_i32_e64 s0, v4, v5
s_and_b32 s8, s6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s8, s8, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s8
s_cbranch_execz .LBB0_18
v_add_nc_u32_e32 v6, s7, v3
scratch_load_b32 v8, v6, off
v_add_nc_u32_e32 v6, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v8, off
s_branch .LBB0_18
.LBB0_21:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13correlate_gpuiiPKfPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 1040
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 41
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13correlate_gpuiiPKfPfi, .Lfunc_end0-_Z13correlate_gpuiiPKfPfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17padding_transposeiiPKfPfi
.globl _Z17padding_transposeiiPKfPfi
.p2align 8
.type _Z17padding_transposeiiPKfPfi,@function
_Z17padding_transposeiiPKfPfi:
s_load_b32 s3, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB1_7
s_clause 0x2
s_load_b32 s9, s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s8, s[0:1], 0x18
s_mov_b32 s2, s15
s_mov_b32 s11, 0
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s15, s9
s_mul_i32 s9, s15, s9
s_cselect_b32 s10, -1, 0
s_add_u32 s0, s0, 32
s_addc_u32 s1, s1, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_4
.p2align 6
.LBB1_2:
v_mad_u64_u32 v[3:4], null, v1, s8, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v2, off
s_load_b32 s15, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s15, s15, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s12, s15
s_cmp_ge_i32 s12, s3
s_cselect_b32 s15, -1, 0
s_and_not1_b32 s13, s13, exec_lo
s_and_b32 s15, s15, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s13, s13, s15
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s14, exec_lo, s13
s_or_b32 s11, s14, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB1_7
.LBB1_4:
v_add_nc_u32_e32 v1, s12, v0
s_or_b32 s13, s13, exec_lo
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_3
v_mov_b32_e32 v2, 0
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB1_2
v_add_nc_u32_e32 v2, s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_branch .LBB1_2
.LBB1_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17padding_transposeiiPKfPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17padding_transposeiiPKfPfi, .Lfunc_end1-_Z17padding_transposeiiPKfPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13correlate_gpuiiPKfPfi
.private_segment_fixed_size: 1040
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13correlate_gpuiiPKfPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 41
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17padding_transposeiiPKfPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17padding_transposeiiPKfPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include "../include/gpu_stack.h"
#include <thrust/device_vector.h>
#define def_dvec(t) thrust::device_vector<t>
#define to_ptr(x) thrust::raw_pointer_cast(&x[0])
using namespace std;
const int STACK_SIZE = 100;
__global__ void test(float *output){
gpu_stack<float, STACK_SIZE> stk;
for(int i=1;i<=STACK_SIZE;++i){
stk.push(1.5*i);
}
int idx = 0, k = 0;
while(!stk.empty()){
stk.pop_k(k);
if(stk.empty()) return;
output[idx] = stk.top();
idx += 1;
output[idx] = (float)stk.size();
k += 1;
idx += 1;
}
}
int main(){
def_dvec(float) dev_out(40, 0);
test<<<1, 1>>>(to_ptr(dev_out));
for(auto k:dev_out) cout<<k<<' ';
cout<<endl;
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4testPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ HFMA2.MMA R7, -RZ, RZ, 2.578125, 0 ; /* 0x41280000ff077435 */
/* 0x000fe200000001ff */
/*0020*/ IADD3 R1, R1, -0x198, RZ ; /* 0xfffffe6801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ HFMA2.MMA R11, -RZ, RZ, 2.7578125, 0 ; /* 0x41840000ff0b7435 */
/* 0x000fe200000001ff */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, 0x40c00000 ; /* 0x40c00000ff047424 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R5, 0x40f00000 ; /* 0x40f0000000057802 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R6, RZ, RZ, 0x41100000 ; /* 0x41100000ff067424 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R9, 0x41580000 ; /* 0x4158000000097802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R8, RZ, RZ, 0x41400000 ; /* 0x41400000ff087424 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R13, 0x419c0000 ; /* 0x419c0000000d7802 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x41700000 ; /* 0x41700000ff0a7424 */
/* 0x000fe200078e00ff */
/*00b0*/ STL.64 [R1+0x10], R4 ; /* 0x0000100401007387 */
/* 0x0001e20000100a00 */
/*00c0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x41900000 ; /* 0x41900000ff0c7424 */
/* 0x000fe200078e00ff */
/*00d0*/ HFMA2.MMA R15, -RZ, RZ, 2.8515625, 0 ; /* 0x41b40000ff0f7435 */
/* 0x000fe200000001ff */
/*00e0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x41a80000 ; /* 0x41a80000ff0e7424 */
/* 0x000fe200078e00ff */
/*00f0*/ STL.64 [R1+0x18], R6 ; /* 0x0000180601007387 */
/* 0x0003e20000100a00 */
/*0100*/ IMAD.MOV.U32 R16, RZ, RZ, 0x41f00000 ; /* 0x41f00000ff107424 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R17, 0x41fc0000 ; /* 0x41fc000000117802 */
/* 0x000fe20000000f00 */
/*0120*/ HFMA2.MMA R3, -RZ, RZ, 2.28125, 0 ; /* 0x40900000ff037435 */
/* 0x000fe200000001ff */
/*0130*/ STL.64 [R1+0x20], R8 ; /* 0x0000200801007387 */
/* 0x0005e20000100a00 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, 0x40400000 ; /* 0x40400000ff027424 */
/* 0x000fe200078e00ff */
/*0150*/ MOV R18, 0x43160000 ; /* 0x4316000000127802 */
/* 0x000fe20000000f00 */
/*0160*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0170*/ STL.64 [R1+0x28], R10 ; /* 0x0000280a01007387 */
/* 0x0007e20000100a00 */
/*0180*/ HFMA2.MMA R5, -RZ, RZ, 2.9453125, 0 ; /* 0x41e40000ff057435 */
/* 0x001fe200000001ff */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, 0x41d80000 ; /* 0x41d80000ff047424 */
/* 0x000fe200078e00ff */
/*01a0*/ MOV R0, R1 ; /* 0x0000000100007202 */
/* 0x000fe20000000f00 */
/*01b0*/ HFMA2.MMA R7, -RZ, RZ, 3.01953125, 0 ; /* 0x420a0000ff077435 */
/* 0x002fe200000001ff */
/*01c0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x42040000 ; /* 0x42040000ff067424 */
/* 0x000fe200078e00ff */
/*01d0*/ STL.64 [R1+0x30], R12 ; /* 0x0000300c01007387 */
/* 0x0001e20000100a00 */
/*01e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01f0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x42100000 ; /* 0x42100000ff087424 */
/* 0x004fe200078e00ff */
/*0200*/ MOV R9, 0x42160000 ; /* 0x4216000000097802 */
/* 0x000fe20000000f00 */
/*0210*/ STL.64 [R1+0x48], R4 ; /* 0x0000480401007387 */
/* 0x0003e20000100a00 */
/*0220*/ HFMA2.MMA R11, -RZ, RZ, 3.06640625, 0 ; /* 0x42220000ff0b7435 */
/* 0x008fe200000001ff */
/*0230*/ IMAD.MOV.U32 R10, RZ, RZ, 0x421c0000 ; /* 0x421c0000ff0a7424 */
/* 0x000fc400078e00ff */
/*0240*/ STL.64 [R1+0x60], R8 ; /* 0x0000600801007387 */
/* 0x0005e80000100a00 */
/*0250*/ STL.64 [R1+0x58], R6 ; /* 0x0000580601007387 */
/* 0x0007e20000100a00 */
/*0260*/ IMAD.MOV.U32 R12, RZ, RZ, 0x42280000 ; /* 0x42280000ff0c7424 */
/* 0x001fe200078e00ff */
/*0270*/ MOV R13, 0x422e0000 ; /* 0x422e0000000d7802 */
/* 0x000fe40000000f00 */
/*0280*/ STL.64 [R1+0x68], R10 ; /* 0x0000680a01007387 */
/* 0x0001e20000100a00 */
/*0290*/ HFMA2.MMA R5, -RZ, RZ, 3.16015625, 0 ; /* 0x42520000ff057435 */
/* 0x002fe200000001ff */
/*02a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x424c0000 ; /* 0x424c0000ff047424 */
/* 0x000fe200078e00ff */
/*02b0*/ HFMA2.MMA R9, -RZ, RZ, 3.20703125, 0 ; /* 0x426a0000ff097435 */
/* 0x004fe200000001ff */
/*02c0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x42640000 ; /* 0x42640000ff087424 */
/* 0x000fe200078e00ff */
/*02d0*/ STL.64 [R1+0x38], R14 ; /* 0x0000380e01007387 */
/* 0x0003e20000100a00 */
/*02e0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x42580000 ; /* 0x42580000ff067424 */
/* 0x008fe200078e00ff */
/*02f0*/ MOV R7, 0x425e0000 ; /* 0x425e000000077802 */
/* 0x000fc40000000f00 */
/*0300*/ STL.64 [R1+0x70], R12 ; /* 0x0000700c01007387 */
/* 0x0005e20000100a00 */
/*0310*/ HFMA2.MMA R11, -RZ, RZ, 3.251953125, 0 ; /* 0x42810000ff0b7435 */
/* 0x001fe200000001ff */
/*0320*/ IMAD.MOV.U32 R10, RZ, RZ, 0x427c0000 ; /* 0x427c0000ff0a7424 */
/* 0x000fe400078e00ff */
/*0330*/ STL.64 [R1+0x90], R6 ; /* 0x0000900601007387 */
/* 0x0001e20000100a00 */
/*0340*/ HFMA2.MMA R15, -RZ, RZ, 3.11328125, 0 ; /* 0x423a0000ff0f7435 */
/* 0x002fe200000001ff */
/*0350*/ IMAD.MOV.U32 R14, RZ, RZ, 0x42340000 ; /* 0x42340000ff0e7424 */
/* 0x000fe400078e00ff */
/*0360*/ STL.64 [R1+0x98], R8 ; /* 0x0000980801007387 */
/* 0x0003e20000100a00 */
/*0370*/ IMAD.MOV.U32 R12, RZ, RZ, 0x42840000 ; /* 0x42840000ff0c7424 */
/* 0x004fe200078e00ff */
/*0380*/ MOV R13, 0x42870000 ; /* 0x42870000000d7802 */
/* 0x000fc40000000f00 */
/*0390*/ STL.64 [R1+0x50], R16 ; /* 0x0000501001007387 */
/* 0x0005e20000100a00 */
/*03a0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x429c0000 ; /* 0x429c0000ff067424 */
/* 0x001fe200078e00ff */
/*03b0*/ MOV R7, 0x429f0000 ; /* 0x429f000000077802 */
/* 0x000fe40000000f00 */
/*03c0*/ STL.64 [R1+0x88], R4 ; /* 0x0000880401007387 */
/* 0x0001e20000100a00 */
/*03d0*/ HFMA2.MMA R9, -RZ, RZ, 3.322265625, 0 ; /* 0x42a50000ff097435 */
/* 0x002fc600000001ff */
/*03e0*/ STL.64 [R1+0xa8], R10 ; /* 0x0000a80a01007387 */
/* 0x0003e20000100a00 */
/*03f0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x42a20000 ; /* 0x42a20000ff087424 */
/* 0x000fe400078e00ff */
/*0400*/ IMAD.MOV.U32 R16, RZ, RZ, 0x42700000 ; /* 0x42700000ff107424 */
/* 0x004fe200078e00ff */
/*0410*/ MOV R17, 0x42760000 ; /* 0x4276000000117802 */
/* 0x000fe20000000f00 */
/*0420*/ STL.64 [R1+0x78], R14 ; /* 0x0000780e01007387 */
/* 0x0005e20000100a00 */
/*0430*/ IMAD.MOV.U32 R4, RZ, RZ, 0x42900000 ; /* 0x42900000ff047424 */
/* 0x001fe200078e00ff */
/*0440*/ MOV R5, 0x42930000 ; /* 0x4293000000057802 */
/* 0x000fe40000000f00 */
/*0450*/ STL.64 [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0001e20000100a00 */
/*0460*/ IMAD.MOV.U32 R10, RZ, RZ, 0x42a80000 ; /* 0x42a80000ff0a7424 */
/* 0x002fe200078e00ff */
/*0470*/ MOV R11, 0x42ab0000 ; /* 0x42ab0000000b7802 */
/* 0x000fc40000000f00 */
/*0480*/ STL.64 [R1+0xb0], R12 ; /* 0x0000b00c01007387 */
/* 0x0003e20000100a00 */
/*0490*/ HFMA2.MMA R15, -RZ, RZ, 3.298828125, 0 ; /* 0x42990000ff0f7435 */
/* 0x004fc600000001ff */
/*04a0*/ STL.64 [R1+0xd0], R6 ; /* 0x0000d00601007387 */
/* 0x0005e20000100a00 */
/*04b0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x42960000 ; /* 0x42960000ff0e7424 */
/* 0x000fe400078e00ff */
/*04c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x41c00000 ; /* 0x41c00000ff027424 */
/* 0x001fe200078e00ff */
/*04d0*/ MOV R3, 0x41cc0000 ; /* 0x41cc000000037802 */
/* 0x000fe20000000f00 */
/*04e0*/ STL.64 [R1+0xa0], R16 ; /* 0x0000a01001007387 */
/* 0x0001e20000100a00 */
/*04f0*/ HFMA2.MMA R13, -RZ, RZ, 3.345703125, 0 ; /* 0x42b10000ff0d7435 */
/* 0x002fc600000001ff */
/*0500*/ STL.64 [R1+0xc0], R4 ; /* 0x0000c00401007387 */
/* 0x0003e20000100a00 */
/*0510*/ IMAD.MOV.U32 R12, RZ, RZ, 0x42ae0000 ; /* 0x42ae0000ff0c7424 */
/* 0x000fe200078e00ff */
/*0520*/ HFMA2.MMA R7, -RZ, RZ, 3.392578125, 0 ; /* 0x42c90000ff077435 */
/* 0x004fe400000001ff */
/*0530*/ STL.64 [R1+0xd8], R8 ; /* 0x0000d80801007387 */
/* 0x0005e20000100a00 */
/*0540*/ IMAD.MOV.U32 R6, RZ, RZ, 0x42c60000 ; /* 0x42c60000ff067424 */
/* 0x000fc600078e00ff */
/*0550*/ STL.64 [R1+0xe0], R10 ; /* 0x0000e00a01007387 */
/* 0x0007e20000100a00 */
/*0560*/ IMAD.MOV.U32 R16, RZ, RZ, 0x42b40000 ; /* 0x42b40000ff107424 */
/* 0x001fe200078e00ff */
/*0570*/ MOV R17, 0x42b70000 ; /* 0x42b7000000117802 */
/* 0x000fe20000000f00 */
/*0580*/ IMAD.MOV.U32 R4, RZ, RZ, 0x42c00000 ; /* 0x42c00000ff047424 */
/* 0x002fe200078e00ff */
/*0590*/ MOV R5, 0x42c30000 ; /* 0x42c3000000057802 */
/* 0x000fe20000000f00 */
/*05a0*/ STL.64 [R1+0x40], R2 ; /* 0x0000400201007387 */
/* 0x0001e20000100a00 */
/*05b0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x42cc0000 ; /* 0x42cc0000ff087424 */
/* 0x004fe200078e00ff */
/*05c0*/ MOV R9, 0x42cf0000 ; /* 0x42cf000000097802 */
/* 0x000fe40000000f00 */
/*05d0*/ STL.64 [R1+0xc8], R14 ; /* 0x0000c80e01007387 */
/* 0x0003e20000100a00 */
/*05e0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x42d80000 ; /* 0x42d80000ff0a7424 */
/* 0x008fe200078e00ff */
/*05f0*/ MOV R11, 0x42db0000 ; /* 0x42db0000000b7802 */
/* 0x000fc40000000f00 */
/*0600*/ STL.64 [R1+0xe8], R12 ; /* 0x0000e80c01007387 */
/* 0x0005e20000100a00 */
/*0610*/ IMAD.MOV.U32 R2, RZ, RZ, 0x42400000 ; /* 0x42400000ff027424 */
/* 0x001fe200078e00ff */
/*0620*/ MOV R3, 0x42460000 ; /* 0x4246000000037802 */
/* 0x000fe40000000f00 */
/*0630*/ STL.64 [R1+0xf0], R16 ; /* 0x0000f01001007387 */
/* 0x0001e20000100a00 */
/*0640*/ HFMA2.MMA R15, -RZ, RZ, 3.416015625, 0 ; /* 0x42d50000ff0f7435 */
/* 0x002fe200000001ff */
/*0650*/ IMAD.MOV.U32 R14, RZ, RZ, 0x42d20000 ; /* 0x42d20000ff0e7424 */
/* 0x000fe400078e00ff */
/*0660*/ STL.64 [R1+0x100], R4 ; /* 0x0001000401007387 */
/* 0x0003e20000100a00 */
/*0670*/ HFMA2.MMA R13, -RZ, RZ, 3.439453125, 0 ; /* 0x42e10000ff0d7435 */
/* 0x004fe200000001ff */
/*0680*/ IMAD.MOV.U32 R12, RZ, RZ, 0x42de0000 ; /* 0x42de0000ff0c7424 */
/* 0x000fc400078e00ff */
/*0690*/ STL.64 [R1+0x108], R6 ; /* 0x0001080601007387 */
/* 0x0005e80000100a00 */
/*06a0*/ STL.64 [R1+0x110], R8 ; /* 0x0001100801007387 */
/* 0x0007e20000100a00 */
/*06b0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x42f00000 ; /* 0x42f00000ff107424 */
/* 0x001fe200078e00ff */
/*06c0*/ MOV R17, 0x42f30000 ; /* 0x42f3000000117802 */
/* 0x000fe40000000f00 */
/*06d0*/ STL.64 [R1+0x120], R10 ; /* 0x0001200a01007387 */
/* 0x0001e20000100a00 */
/*06e0*/ HFMA2.MMA R5, -RZ, RZ, 3.462890625, 0 ; /* 0x42ed0000ff057435 */
/* 0x002fe200000001ff */
/*06f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x42ea0000 ; /* 0x42ea0000ff047424 */
/* 0x000fe200078e00ff */
/*0700*/ HFMA2.MMA R7, -RZ, RZ, 3.486328125, 0 ; /* 0x42f90000ff077435 */
/* 0x004fe200000001ff */
/*0710*/ STL.64 [R1+0x80], R2 ; /* 0x0000800201007387 */
/* 0x0003e20000100a00 */
/*0720*/ IMAD.MOV.U32 R6, RZ, RZ, 0x42f60000 ; /* 0x42f60000ff067424 */
/* 0x000fc400078e00ff */
/*0730*/ IMAD.MOV.U32 R8, RZ, RZ, 0x42fc0000 ; /* 0x42fc0000ff087424 */
/* 0x008fe200078e00ff */
/*0740*/ MOV R9, 0x42ff0000 ; /* 0x42ff000000097802 */
/* 0x000fe20000000f00 */
/*0750*/ STL.64 [R1+0x118], R14 ; /* 0x0001180e01007387 */
/* 0x0005e20000100a00 */
/*0760*/ HFMA2.MMA R11, -RZ, RZ, 3.50390625, -0.0 ; /* 0x43028000ff0b7435 */
/* 0x001fe200000001ff */
/*0770*/ IMAD.MOV.U32 R10, RZ, RZ, 0x43010000 ; /* 0x43010000ff0a7424 */
/* 0x000fe400078e00ff */
/*0780*/ STL.64 [R1+0x140], R16 ; /* 0x0001401001007387 */
/* 0x0001e20000100a00 */
/*0790*/ HFMA2.MMA R3, -RZ, RZ, 3.275390625, 0 ; /* 0x428d0000ff037435 */
/* 0x002fe200000001ff */
/*07a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x428a0000 ; /* 0x428a0000ff027424 */
/* 0x000fe400078e00ff */
/*07b0*/ STL.64 [R1+0x150], R8 ; /* 0x0001500801007387 */
/* 0x0003e20000100a00 */
/*07c0*/ HFMA2.MMA R15, -RZ, RZ, 3.515625, -0.0 ; /* 0x43088000ff0f7435 */
/* 0x004fc600000001ff */
/*07d0*/ STL.64 [R1+0x128], R12 ; /* 0x0001280c01007387 */
/* 0x0005e20000100a00 */
/*07e0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x43070000 ; /* 0x43070000ff0e7424 */
/* 0x000fe200078e00ff */
/*07f0*/ HFMA2.MMA R17, -RZ, RZ, 3.52734375, -0.0 ; /* 0x430e8000ff117435 */
/* 0x001fe400000001ff */
/*0800*/ STL.64 [R1+0x138], R4 ; /* 0x0001380401007387 */
/* 0x0001e20000100a00 */
/*0810*/ IMAD.MOV.U32 R16, RZ, RZ, 0x430d0000 ; /* 0x430d0000ff107424 */
/* 0x000fe200078e00ff */
/*0820*/ HFMA2.MMA R9, -RZ, RZ, 3.5390625, -0.0 ; /* 0x43148000ff097435 */
/* 0x002fe400000001ff */
/*0830*/ STL.64 [R1+0x148], R6 ; /* 0x0001480601007387 */
/* 0x0003e20000100a00 */
/*0840*/ IMAD.MOV.U32 R8, RZ, RZ, 0x43130000 ; /* 0x43130000ff087424 */
/* 0x000fe400078e00ff */
/*0850*/ IMAD.MOV.U32 R12, RZ, RZ, 0x43040000 ; /* 0x43040000ff0c7424 */
/* 0x004fe200078e00ff */
/*0860*/ STL.64 [R1+0x158], R10 ; /* 0x0001580a01007387 */
/* 0x0005e20000100a00 */
/*0870*/ MOV R13, 0x43058000 ; /* 0x43058000000d7802 */
/* 0x000fe20000000f00 */
/*0880*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3fc00000 ; /* 0x3fc00000ff047424 */
/* 0x001fc400078e00ff */
/*0890*/ STL.64 [R1+0xb8], R2 ; /* 0x0000b80201007387 */
/* 0x0001e20000100a00 */
/*08a0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x43100000 ; /* 0x43100000ff067424 */
/* 0x002fe200078e00ff */
/*08b0*/ MOV R7, 0x43118000 ; /* 0x4311800000077802 */
/* 0x000fe40000000f00 */
/*08c0*/ STL.64 [R1+0x160], R12 ; /* 0x0001600c01007387 */
/* 0x000fe20000100a00 */
/*08d0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x64 ; /* 0x00000064ff0a7424 */
/* 0x004fc600078e00ff */
/*08e0*/ STL.64 [R1+0x168], R14 ; /* 0x0001680e01007387 */
/* 0x000fe20000100a00 */
/*08f0*/ HFMA2.MMA R3, -RZ, RZ, 3.369140625, 0 ; /* 0x42bd0000ff037435 */
/* 0x001fe200000001ff */
/*0900*/ IMAD.MOV.U32 R2, RZ, RZ, 0x42ba0000 ; /* 0x42ba0000ff027424 */
/* 0x000fe400078e00ff */
/*0910*/ STL.64 [R1+0x178], R16 ; /* 0x0001781001007387 */
/* 0x000fe80000100a00 */
/*0920*/ STL.64 [R1+0x180], R6 ; /* 0x0001800601007387 */
/* 0x000fe80000100a00 */
/*0930*/ STL.64 [R1+0x188], R8 ; /* 0x0001880801007387 */
/* 0x000fe80000100a00 */
/*0940*/ STL [R1+0x4], R4 ; /* 0x0000040401007387 */
/* 0x000fe80000100800 */
/*0950*/ STL [R1+0x190], R18 ; /* 0x0001901201007387 */
/* 0x000fe80000100800 */
/*0960*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x000fe80000100800 */
/*0970*/ STL.64 [R1+0xf8], R2 ; /* 0x0000f80201007387 */
/* 0x0001e40000100a00 */
/*0980*/ IMAD.MOV.U32 R2, RZ, RZ, 0x42e40000 ; /* 0x42e40000ff027424 */
/* 0x001fe200078e00ff */
/*0990*/ MOV R3, 0x42e70000 ; /* 0x42e7000000037802 */
/* 0x000fca0000000f00 */
/*09a0*/ STL.64 [R1+0x130], R2 ; /* 0x0001300201007387 */
/* 0x0001e40000100a00 */
/*09b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x430a0000 ; /* 0x430a0000ff027424 */
/* 0x001fe200078e00ff */
/*09c0*/ MOV R3, 0x430b8000 ; /* 0x430b800000037802 */
/* 0x000fca0000000f00 */
/*09d0*/ STL.64 [R1+0x170], R2 ; /* 0x0001700201007387 */
/* 0x0001e40000100a00 */
/*09e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 5.9604644775390625e-06 ; /* 0x00000064ff027435 */
/* 0x001fe200000001ff */
/*09f0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fd200078e00ff */
/*0a00*/ IMAD R6, R2, 0x4, R0 ; /* 0x0000000402067824 */
/* 0x000fca00078e0200 */
/*0a10*/ LDL R7, [R6] ; /* 0x0000000006077983 */
/* 0x001ea20000100800 */
/*0a20*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0a30*/ I2F R9, R2 ; /* 0x0000000200097306 */
/* 0x0000620000201400 */
/*0a40*/ MOV R4, 0x4 ; /* 0x0000000400047802 */
/* 0x000fc80000000f00 */
/*0a50*/ IMNMX R11, R2, UR4, PT ; /* 0x00000004020b7c17 */
/* 0x000fe2000b800200 */
/*0a60*/ IMAD.WIDE R4, R3.reuse, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x040fe200078e0204 */
/*0a70*/ IADD3 R3, R3, 0x2, RZ ; /* 0x0000000203037810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ IMAD.IADD R2, R2, 0x1, -R11 ; /* 0x0000000102027824 */
/* 0x001fca00078e0a0b */
/*0a90*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e20000100800 */
/*0aa0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f05270 */
/*0ab0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0021e8000c101906 */
/*0ac0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041ec000c101906 */
/*0ad0*/ @P0 BRA 0xa00 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0ae0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0af0*/ BRA 0xaf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include "../include/gpu_stack.h"
#include <thrust/device_vector.h>
#define def_dvec(t) thrust::device_vector<t>
#define to_ptr(x) thrust::raw_pointer_cast(&x[0])
using namespace std;
const int STACK_SIZE = 100;
__global__ void test(float *output){
gpu_stack<float, STACK_SIZE> stk;
for(int i=1;i<=STACK_SIZE;++i){
stk.push(1.5*i);
}
int idx = 0, k = 0;
while(!stk.empty()){
stk.pop_k(k);
if(stk.empty()) return;
output[idx] = stk.top();
idx += 1;
output[idx] = (float)stk.size();
k += 1;
idx += 1;
}
}
int main(){
def_dvec(float) dev_out(40, 0);
test<<<1, 1>>>(to_ptr(dev_out));
for(auto k:dev_out) cout<<k<<' ';
cout<<endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include "../include/gpu_stack.h"
#include <thrust/device_vector.h>
#define def_dvec(t) thrust::device_vector<t>
#define to_ptr(x) thrust::raw_pointer_cast(&x[0])
using namespace std;
const int STACK_SIZE = 100;
__global__ void test(float *output){
gpu_stack<float, STACK_SIZE> stk;
for(int i=1;i<=STACK_SIZE;++i){
stk.push(1.5*i);
}
int idx = 0, k = 0;
while(!stk.empty()){
stk.pop_k(k);
if(stk.empty()) return;
output[idx] = stk.top();
idx += 1;
output[idx] = (float)stk.size();
k += 1;
idx += 1;
}
}
int main(){
def_dvec(float) dev_out(40, 0);
test<<<1, 1>>>(to_ptr(dev_out));
for(auto k:dev_out) cout<<k<<' ';
cout<<endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include "../include/gpu_stack.h"
#include <thrust/device_vector.h>
#define def_dvec(t) thrust::device_vector<t>
#define to_ptr(x) thrust::raw_pointer_cast(&x[0])
using namespace std;
const int STACK_SIZE = 100;
__global__ void test(float *output){
gpu_stack<float, STACK_SIZE> stk;
for(int i=1;i<=STACK_SIZE;++i){
stk.push(1.5*i);
}
int idx = 0, k = 0;
while(!stk.empty()){
stk.pop_k(k);
if(stk.empty()) return;
output[idx] = stk.top();
idx += 1;
output[idx] = (float)stk.size();
k += 1;
idx += 1;
}
}
int main(){
def_dvec(float) dev_out(40, 0);
test<<<1, 1>>>(to_ptr(dev_out));
for(auto k:dev_out) cout<<k<<' ';
cout<<endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testPf
.globl _Z4testPf
.p2align 8
.type _Z4testPf,@function
_Z4testPf:
v_mov_b32_e32 v0, 0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 0x3ff00000
s_mov_b32 s2, 4
scratch_store_b32 off, v2, off offset:4
.LBB0_1:
v_mul_f64 v[2:3], v[0:1], 0x3ff80000
v_add_f64 v[0:1], v[0:1], 1.0
s_add_i32 s3, s2, 4
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmpk_eq_i32 s2, 0x194
v_cvt_f32_f64_e32 v2, v[2:3]
scratch_store_b32 off, v2, s3
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, 0x64 :: v_dual_mov_b32 v0, 0
s_movk_i32 s2, 0x64
s_mov_b32 s3, 0
scratch_store_b32 off, v1, off offset:4
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_6
.LBB0_4:
s_cmp_le_i32 s2, s3
s_mov_b32 s4, -1
s_cbranch_scc1 .LBB0_3
s_min_i32 s4, s3, s2
s_add_i32 s3, s3, 1
s_sub_i32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s4, s2, 2
v_cvt_f32_i32_e32 v2, s2
v_add_nc_u32_e64 v1, s4, 4
s_cmp_eq_u32 s2, 0
s_cselect_b32 s4, -1, 0
scratch_load_b32 v1, v1, off
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b32 v0, v1, s[0:1] offset:-4
global_store_b32 v0, v2, s[0:1]
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
s_branch .LBB0_3
.LBB0_6:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 408
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testPf, .Lfunc_end0-_Z4testPf
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testPf
.private_segment_fixed_size: 408
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z4testPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4testPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ HFMA2.MMA R7, -RZ, RZ, 2.578125, 0 ; /* 0x41280000ff077435 */
/* 0x000fe200000001ff */
/*0020*/ IADD3 R1, R1, -0x198, RZ ; /* 0xfffffe6801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ HFMA2.MMA R11, -RZ, RZ, 2.7578125, 0 ; /* 0x41840000ff0b7435 */
/* 0x000fe200000001ff */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, 0x40c00000 ; /* 0x40c00000ff047424 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R5, 0x40f00000 ; /* 0x40f0000000057802 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R6, RZ, RZ, 0x41100000 ; /* 0x41100000ff067424 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R9, 0x41580000 ; /* 0x4158000000097802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R8, RZ, RZ, 0x41400000 ; /* 0x41400000ff087424 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R13, 0x419c0000 ; /* 0x419c0000000d7802 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x41700000 ; /* 0x41700000ff0a7424 */
/* 0x000fe200078e00ff */
/*00b0*/ STL.64 [R1+0x10], R4 ; /* 0x0000100401007387 */
/* 0x0001e20000100a00 */
/*00c0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x41900000 ; /* 0x41900000ff0c7424 */
/* 0x000fe200078e00ff */
/*00d0*/ HFMA2.MMA R15, -RZ, RZ, 2.8515625, 0 ; /* 0x41b40000ff0f7435 */
/* 0x000fe200000001ff */
/*00e0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x41a80000 ; /* 0x41a80000ff0e7424 */
/* 0x000fe200078e00ff */
/*00f0*/ STL.64 [R1+0x18], R6 ; /* 0x0000180601007387 */
/* 0x0003e20000100a00 */
/*0100*/ IMAD.MOV.U32 R16, RZ, RZ, 0x41f00000 ; /* 0x41f00000ff107424 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R17, 0x41fc0000 ; /* 0x41fc000000117802 */
/* 0x000fe20000000f00 */
/*0120*/ HFMA2.MMA R3, -RZ, RZ, 2.28125, 0 ; /* 0x40900000ff037435 */
/* 0x000fe200000001ff */
/*0130*/ STL.64 [R1+0x20], R8 ; /* 0x0000200801007387 */
/* 0x0005e20000100a00 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, 0x40400000 ; /* 0x40400000ff027424 */
/* 0x000fe200078e00ff */
/*0150*/ MOV R18, 0x43160000 ; /* 0x4316000000127802 */
/* 0x000fe20000000f00 */
/*0160*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0170*/ STL.64 [R1+0x28], R10 ; /* 0x0000280a01007387 */
/* 0x0007e20000100a00 */
/*0180*/ HFMA2.MMA R5, -RZ, RZ, 2.9453125, 0 ; /* 0x41e40000ff057435 */
/* 0x001fe200000001ff */
/*0190*/ IMAD.MOV.U32 R4, RZ, RZ, 0x41d80000 ; /* 0x41d80000ff047424 */
/* 0x000fe200078e00ff */
/*01a0*/ MOV R0, R1 ; /* 0x0000000100007202 */
/* 0x000fe20000000f00 */
/*01b0*/ HFMA2.MMA R7, -RZ, RZ, 3.01953125, 0 ; /* 0x420a0000ff077435 */
/* 0x002fe200000001ff */
/*01c0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x42040000 ; /* 0x42040000ff067424 */
/* 0x000fe200078e00ff */
/*01d0*/ STL.64 [R1+0x30], R12 ; /* 0x0000300c01007387 */
/* 0x0001e20000100a00 */
/*01e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01f0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x42100000 ; /* 0x42100000ff087424 */
/* 0x004fe200078e00ff */
/*0200*/ MOV R9, 0x42160000 ; /* 0x4216000000097802 */
/* 0x000fe20000000f00 */
/*0210*/ STL.64 [R1+0x48], R4 ; /* 0x0000480401007387 */
/* 0x0003e20000100a00 */
/*0220*/ HFMA2.MMA R11, -RZ, RZ, 3.06640625, 0 ; /* 0x42220000ff0b7435 */
/* 0x008fe200000001ff */
/*0230*/ IMAD.MOV.U32 R10, RZ, RZ, 0x421c0000 ; /* 0x421c0000ff0a7424 */
/* 0x000fc400078e00ff */
/*0240*/ STL.64 [R1+0x60], R8 ; /* 0x0000600801007387 */
/* 0x0005e80000100a00 */
/*0250*/ STL.64 [R1+0x58], R6 ; /* 0x0000580601007387 */
/* 0x0007e20000100a00 */
/*0260*/ IMAD.MOV.U32 R12, RZ, RZ, 0x42280000 ; /* 0x42280000ff0c7424 */
/* 0x001fe200078e00ff */
/*0270*/ MOV R13, 0x422e0000 ; /* 0x422e0000000d7802 */
/* 0x000fe40000000f00 */
/*0280*/ STL.64 [R1+0x68], R10 ; /* 0x0000680a01007387 */
/* 0x0001e20000100a00 */
/*0290*/ HFMA2.MMA R5, -RZ, RZ, 3.16015625, 0 ; /* 0x42520000ff057435 */
/* 0x002fe200000001ff */
/*02a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x424c0000 ; /* 0x424c0000ff047424 */
/* 0x000fe200078e00ff */
/*02b0*/ HFMA2.MMA R9, -RZ, RZ, 3.20703125, 0 ; /* 0x426a0000ff097435 */
/* 0x004fe200000001ff */
/*02c0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x42640000 ; /* 0x42640000ff087424 */
/* 0x000fe200078e00ff */
/*02d0*/ STL.64 [R1+0x38], R14 ; /* 0x0000380e01007387 */
/* 0x0003e20000100a00 */
/*02e0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x42580000 ; /* 0x42580000ff067424 */
/* 0x008fe200078e00ff */
/*02f0*/ MOV R7, 0x425e0000 ; /* 0x425e000000077802 */
/* 0x000fc40000000f00 */
/*0300*/ STL.64 [R1+0x70], R12 ; /* 0x0000700c01007387 */
/* 0x0005e20000100a00 */
/*0310*/ HFMA2.MMA R11, -RZ, RZ, 3.251953125, 0 ; /* 0x42810000ff0b7435 */
/* 0x001fe200000001ff */
/*0320*/ IMAD.MOV.U32 R10, RZ, RZ, 0x427c0000 ; /* 0x427c0000ff0a7424 */
/* 0x000fe400078e00ff */
/*0330*/ STL.64 [R1+0x90], R6 ; /* 0x0000900601007387 */
/* 0x0001e20000100a00 */
/*0340*/ HFMA2.MMA R15, -RZ, RZ, 3.11328125, 0 ; /* 0x423a0000ff0f7435 */
/* 0x002fe200000001ff */
/*0350*/ IMAD.MOV.U32 R14, RZ, RZ, 0x42340000 ; /* 0x42340000ff0e7424 */
/* 0x000fe400078e00ff */
/*0360*/ STL.64 [R1+0x98], R8 ; /* 0x0000980801007387 */
/* 0x0003e20000100a00 */
/*0370*/ IMAD.MOV.U32 R12, RZ, RZ, 0x42840000 ; /* 0x42840000ff0c7424 */
/* 0x004fe200078e00ff */
/*0380*/ MOV R13, 0x42870000 ; /* 0x42870000000d7802 */
/* 0x000fc40000000f00 */
/*0390*/ STL.64 [R1+0x50], R16 ; /* 0x0000501001007387 */
/* 0x0005e20000100a00 */
/*03a0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x429c0000 ; /* 0x429c0000ff067424 */
/* 0x001fe200078e00ff */
/*03b0*/ MOV R7, 0x429f0000 ; /* 0x429f000000077802 */
/* 0x000fe40000000f00 */
/*03c0*/ STL.64 [R1+0x88], R4 ; /* 0x0000880401007387 */
/* 0x0001e20000100a00 */
/*03d0*/ HFMA2.MMA R9, -RZ, RZ, 3.322265625, 0 ; /* 0x42a50000ff097435 */
/* 0x002fc600000001ff */
/*03e0*/ STL.64 [R1+0xa8], R10 ; /* 0x0000a80a01007387 */
/* 0x0003e20000100a00 */
/*03f0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x42a20000 ; /* 0x42a20000ff087424 */
/* 0x000fe400078e00ff */
/*0400*/ IMAD.MOV.U32 R16, RZ, RZ, 0x42700000 ; /* 0x42700000ff107424 */
/* 0x004fe200078e00ff */
/*0410*/ MOV R17, 0x42760000 ; /* 0x4276000000117802 */
/* 0x000fe20000000f00 */
/*0420*/ STL.64 [R1+0x78], R14 ; /* 0x0000780e01007387 */
/* 0x0005e20000100a00 */
/*0430*/ IMAD.MOV.U32 R4, RZ, RZ, 0x42900000 ; /* 0x42900000ff047424 */
/* 0x001fe200078e00ff */
/*0440*/ MOV R5, 0x42930000 ; /* 0x4293000000057802 */
/* 0x000fe40000000f00 */
/*0450*/ STL.64 [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0001e20000100a00 */
/*0460*/ IMAD.MOV.U32 R10, RZ, RZ, 0x42a80000 ; /* 0x42a80000ff0a7424 */
/* 0x002fe200078e00ff */
/*0470*/ MOV R11, 0x42ab0000 ; /* 0x42ab0000000b7802 */
/* 0x000fc40000000f00 */
/*0480*/ STL.64 [R1+0xb0], R12 ; /* 0x0000b00c01007387 */
/* 0x0003e20000100a00 */
/*0490*/ HFMA2.MMA R15, -RZ, RZ, 3.298828125, 0 ; /* 0x42990000ff0f7435 */
/* 0x004fc600000001ff */
/*04a0*/ STL.64 [R1+0xd0], R6 ; /* 0x0000d00601007387 */
/* 0x0005e20000100a00 */
/*04b0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x42960000 ; /* 0x42960000ff0e7424 */
/* 0x000fe400078e00ff */
/*04c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x41c00000 ; /* 0x41c00000ff027424 */
/* 0x001fe200078e00ff */
/*04d0*/ MOV R3, 0x41cc0000 ; /* 0x41cc000000037802 */
/* 0x000fe20000000f00 */
/*04e0*/ STL.64 [R1+0xa0], R16 ; /* 0x0000a01001007387 */
/* 0x0001e20000100a00 */
/*04f0*/ HFMA2.MMA R13, -RZ, RZ, 3.345703125, 0 ; /* 0x42b10000ff0d7435 */
/* 0x002fc600000001ff */
/*0500*/ STL.64 [R1+0xc0], R4 ; /* 0x0000c00401007387 */
/* 0x0003e20000100a00 */
/*0510*/ IMAD.MOV.U32 R12, RZ, RZ, 0x42ae0000 ; /* 0x42ae0000ff0c7424 */
/* 0x000fe200078e00ff */
/*0520*/ HFMA2.MMA R7, -RZ, RZ, 3.392578125, 0 ; /* 0x42c90000ff077435 */
/* 0x004fe400000001ff */
/*0530*/ STL.64 [R1+0xd8], R8 ; /* 0x0000d80801007387 */
/* 0x0005e20000100a00 */
/*0540*/ IMAD.MOV.U32 R6, RZ, RZ, 0x42c60000 ; /* 0x42c60000ff067424 */
/* 0x000fc600078e00ff */
/*0550*/ STL.64 [R1+0xe0], R10 ; /* 0x0000e00a01007387 */
/* 0x0007e20000100a00 */
/*0560*/ IMAD.MOV.U32 R16, RZ, RZ, 0x42b40000 ; /* 0x42b40000ff107424 */
/* 0x001fe200078e00ff */
/*0570*/ MOV R17, 0x42b70000 ; /* 0x42b7000000117802 */
/* 0x000fe20000000f00 */
/*0580*/ IMAD.MOV.U32 R4, RZ, RZ, 0x42c00000 ; /* 0x42c00000ff047424 */
/* 0x002fe200078e00ff */
/*0590*/ MOV R5, 0x42c30000 ; /* 0x42c3000000057802 */
/* 0x000fe20000000f00 */
/*05a0*/ STL.64 [R1+0x40], R2 ; /* 0x0000400201007387 */
/* 0x0001e20000100a00 */
/*05b0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x42cc0000 ; /* 0x42cc0000ff087424 */
/* 0x004fe200078e00ff */
/*05c0*/ MOV R9, 0x42cf0000 ; /* 0x42cf000000097802 */
/* 0x000fe40000000f00 */
/*05d0*/ STL.64 [R1+0xc8], R14 ; /* 0x0000c80e01007387 */
/* 0x0003e20000100a00 */
/*05e0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x42d80000 ; /* 0x42d80000ff0a7424 */
/* 0x008fe200078e00ff */
/*05f0*/ MOV R11, 0x42db0000 ; /* 0x42db0000000b7802 */
/* 0x000fc40000000f00 */
/*0600*/ STL.64 [R1+0xe8], R12 ; /* 0x0000e80c01007387 */
/* 0x0005e20000100a00 */
/*0610*/ IMAD.MOV.U32 R2, RZ, RZ, 0x42400000 ; /* 0x42400000ff027424 */
/* 0x001fe200078e00ff */
/*0620*/ MOV R3, 0x42460000 ; /* 0x4246000000037802 */
/* 0x000fe40000000f00 */
/*0630*/ STL.64 [R1+0xf0], R16 ; /* 0x0000f01001007387 */
/* 0x0001e20000100a00 */
/*0640*/ HFMA2.MMA R15, -RZ, RZ, 3.416015625, 0 ; /* 0x42d50000ff0f7435 */
/* 0x002fe200000001ff */
/*0650*/ IMAD.MOV.U32 R14, RZ, RZ, 0x42d20000 ; /* 0x42d20000ff0e7424 */
/* 0x000fe400078e00ff */
/*0660*/ STL.64 [R1+0x100], R4 ; /* 0x0001000401007387 */
/* 0x0003e20000100a00 */
/*0670*/ HFMA2.MMA R13, -RZ, RZ, 3.439453125, 0 ; /* 0x42e10000ff0d7435 */
/* 0x004fe200000001ff */
/*0680*/ IMAD.MOV.U32 R12, RZ, RZ, 0x42de0000 ; /* 0x42de0000ff0c7424 */
/* 0x000fc400078e00ff */
/*0690*/ STL.64 [R1+0x108], R6 ; /* 0x0001080601007387 */
/* 0x0005e80000100a00 */
/*06a0*/ STL.64 [R1+0x110], R8 ; /* 0x0001100801007387 */
/* 0x0007e20000100a00 */
/*06b0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x42f00000 ; /* 0x42f00000ff107424 */
/* 0x001fe200078e00ff */
/*06c0*/ MOV R17, 0x42f30000 ; /* 0x42f3000000117802 */
/* 0x000fe40000000f00 */
/*06d0*/ STL.64 [R1+0x120], R10 ; /* 0x0001200a01007387 */
/* 0x0001e20000100a00 */
/*06e0*/ HFMA2.MMA R5, -RZ, RZ, 3.462890625, 0 ; /* 0x42ed0000ff057435 */
/* 0x002fe200000001ff */
/*06f0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x42ea0000 ; /* 0x42ea0000ff047424 */
/* 0x000fe200078e00ff */
/*0700*/ HFMA2.MMA R7, -RZ, RZ, 3.486328125, 0 ; /* 0x42f90000ff077435 */
/* 0x004fe200000001ff */
/*0710*/ STL.64 [R1+0x80], R2 ; /* 0x0000800201007387 */
/* 0x0003e20000100a00 */
/*0720*/ IMAD.MOV.U32 R6, RZ, RZ, 0x42f60000 ; /* 0x42f60000ff067424 */
/* 0x000fc400078e00ff */
/*0730*/ IMAD.MOV.U32 R8, RZ, RZ, 0x42fc0000 ; /* 0x42fc0000ff087424 */
/* 0x008fe200078e00ff */
/*0740*/ MOV R9, 0x42ff0000 ; /* 0x42ff000000097802 */
/* 0x000fe20000000f00 */
/*0750*/ STL.64 [R1+0x118], R14 ; /* 0x0001180e01007387 */
/* 0x0005e20000100a00 */
/*0760*/ HFMA2.MMA R11, -RZ, RZ, 3.50390625, -0.0 ; /* 0x43028000ff0b7435 */
/* 0x001fe200000001ff */
/*0770*/ IMAD.MOV.U32 R10, RZ, RZ, 0x43010000 ; /* 0x43010000ff0a7424 */
/* 0x000fe400078e00ff */
/*0780*/ STL.64 [R1+0x140], R16 ; /* 0x0001401001007387 */
/* 0x0001e20000100a00 */
/*0790*/ HFMA2.MMA R3, -RZ, RZ, 3.275390625, 0 ; /* 0x428d0000ff037435 */
/* 0x002fe200000001ff */
/*07a0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x428a0000 ; /* 0x428a0000ff027424 */
/* 0x000fe400078e00ff */
/*07b0*/ STL.64 [R1+0x150], R8 ; /* 0x0001500801007387 */
/* 0x0003e20000100a00 */
/*07c0*/ HFMA2.MMA R15, -RZ, RZ, 3.515625, -0.0 ; /* 0x43088000ff0f7435 */
/* 0x004fc600000001ff */
/*07d0*/ STL.64 [R1+0x128], R12 ; /* 0x0001280c01007387 */
/* 0x0005e20000100a00 */
/*07e0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x43070000 ; /* 0x43070000ff0e7424 */
/* 0x000fe200078e00ff */
/*07f0*/ HFMA2.MMA R17, -RZ, RZ, 3.52734375, -0.0 ; /* 0x430e8000ff117435 */
/* 0x001fe400000001ff */
/*0800*/ STL.64 [R1+0x138], R4 ; /* 0x0001380401007387 */
/* 0x0001e20000100a00 */
/*0810*/ IMAD.MOV.U32 R16, RZ, RZ, 0x430d0000 ; /* 0x430d0000ff107424 */
/* 0x000fe200078e00ff */
/*0820*/ HFMA2.MMA R9, -RZ, RZ, 3.5390625, -0.0 ; /* 0x43148000ff097435 */
/* 0x002fe400000001ff */
/*0830*/ STL.64 [R1+0x148], R6 ; /* 0x0001480601007387 */
/* 0x0003e20000100a00 */
/*0840*/ IMAD.MOV.U32 R8, RZ, RZ, 0x43130000 ; /* 0x43130000ff087424 */
/* 0x000fe400078e00ff */
/*0850*/ IMAD.MOV.U32 R12, RZ, RZ, 0x43040000 ; /* 0x43040000ff0c7424 */
/* 0x004fe200078e00ff */
/*0860*/ STL.64 [R1+0x158], R10 ; /* 0x0001580a01007387 */
/* 0x0005e20000100a00 */
/*0870*/ MOV R13, 0x43058000 ; /* 0x43058000000d7802 */
/* 0x000fe20000000f00 */
/*0880*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3fc00000 ; /* 0x3fc00000ff047424 */
/* 0x001fc400078e00ff */
/*0890*/ STL.64 [R1+0xb8], R2 ; /* 0x0000b80201007387 */
/* 0x0001e20000100a00 */
/*08a0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x43100000 ; /* 0x43100000ff067424 */
/* 0x002fe200078e00ff */
/*08b0*/ MOV R7, 0x43118000 ; /* 0x4311800000077802 */
/* 0x000fe40000000f00 */
/*08c0*/ STL.64 [R1+0x160], R12 ; /* 0x0001600c01007387 */
/* 0x000fe20000100a00 */
/*08d0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x64 ; /* 0x00000064ff0a7424 */
/* 0x004fc600078e00ff */
/*08e0*/ STL.64 [R1+0x168], R14 ; /* 0x0001680e01007387 */
/* 0x000fe20000100a00 */
/*08f0*/ HFMA2.MMA R3, -RZ, RZ, 3.369140625, 0 ; /* 0x42bd0000ff037435 */
/* 0x001fe200000001ff */
/*0900*/ IMAD.MOV.U32 R2, RZ, RZ, 0x42ba0000 ; /* 0x42ba0000ff027424 */
/* 0x000fe400078e00ff */
/*0910*/ STL.64 [R1+0x178], R16 ; /* 0x0001781001007387 */
/* 0x000fe80000100a00 */
/*0920*/ STL.64 [R1+0x180], R6 ; /* 0x0001800601007387 */
/* 0x000fe80000100a00 */
/*0930*/ STL.64 [R1+0x188], R8 ; /* 0x0001880801007387 */
/* 0x000fe80000100a00 */
/*0940*/ STL [R1+0x4], R4 ; /* 0x0000040401007387 */
/* 0x000fe80000100800 */
/*0950*/ STL [R1+0x190], R18 ; /* 0x0001901201007387 */
/* 0x000fe80000100800 */
/*0960*/ STL [R1], R10 ; /* 0x0000000a01007387 */
/* 0x000fe80000100800 */
/*0970*/ STL.64 [R1+0xf8], R2 ; /* 0x0000f80201007387 */
/* 0x0001e40000100a00 */
/*0980*/ IMAD.MOV.U32 R2, RZ, RZ, 0x42e40000 ; /* 0x42e40000ff027424 */
/* 0x001fe200078e00ff */
/*0990*/ MOV R3, 0x42e70000 ; /* 0x42e7000000037802 */
/* 0x000fca0000000f00 */
/*09a0*/ STL.64 [R1+0x130], R2 ; /* 0x0001300201007387 */
/* 0x0001e40000100a00 */
/*09b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x430a0000 ; /* 0x430a0000ff027424 */
/* 0x001fe200078e00ff */
/*09c0*/ MOV R3, 0x430b8000 ; /* 0x430b800000037802 */
/* 0x000fca0000000f00 */
/*09d0*/ STL.64 [R1+0x170], R2 ; /* 0x0001700201007387 */
/* 0x0001e40000100a00 */
/*09e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 5.9604644775390625e-06 ; /* 0x00000064ff027435 */
/* 0x001fe200000001ff */
/*09f0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fd200078e00ff */
/*0a00*/ IMAD R6, R2, 0x4, R0 ; /* 0x0000000402067824 */
/* 0x000fca00078e0200 */
/*0a10*/ LDL R7, [R6] ; /* 0x0000000006077983 */
/* 0x001ea20000100800 */
/*0a20*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0a30*/ I2F R9, R2 ; /* 0x0000000200097306 */
/* 0x0000620000201400 */
/*0a40*/ MOV R4, 0x4 ; /* 0x0000000400047802 */
/* 0x000fc80000000f00 */
/*0a50*/ IMNMX R11, R2, UR4, PT ; /* 0x00000004020b7c17 */
/* 0x000fe2000b800200 */
/*0a60*/ IMAD.WIDE R4, R3.reuse, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x040fe200078e0204 */
/*0a70*/ IADD3 R3, R3, 0x2, RZ ; /* 0x0000000203037810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ IMAD.IADD R2, R2, 0x1, -R11 ; /* 0x0000000102027824 */
/* 0x001fca00078e0a0b */
/*0a90*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e20000100800 */
/*0aa0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f05270 */
/*0ab0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0021e8000c101906 */
/*0ac0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0041ec000c101906 */
/*0ad0*/ @P0 BRA 0xa00 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0ae0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0af0*/ BRA 0xaf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testPf
.globl _Z4testPf
.p2align 8
.type _Z4testPf,@function
_Z4testPf:
v_mov_b32_e32 v0, 0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 0x3ff00000
s_mov_b32 s2, 4
scratch_store_b32 off, v2, off offset:4
.LBB0_1:
v_mul_f64 v[2:3], v[0:1], 0x3ff80000
v_add_f64 v[0:1], v[0:1], 1.0
s_add_i32 s3, s2, 4
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmpk_eq_i32 s2, 0x194
v_cvt_f32_f64_e32 v2, v[2:3]
scratch_store_b32 off, v2, s3
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v1, 0x64 :: v_dual_mov_b32 v0, 0
s_movk_i32 s2, 0x64
s_mov_b32 s3, 0
scratch_store_b32 off, v1, off offset:4
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_6
.LBB0_4:
s_cmp_le_i32 s2, s3
s_mov_b32 s4, -1
s_cbranch_scc1 .LBB0_3
s_min_i32 s4, s3, s2
s_add_i32 s3, s3, 1
s_sub_i32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s4, s2, 2
v_cvt_f32_i32_e32 v2, s2
v_add_nc_u32_e64 v1, s4, 4
s_cmp_eq_u32 s2, 0
s_cselect_b32 s4, -1, 0
scratch_load_b32 v1, v1, off
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b32 v0, v1, s[0:1] offset:-4
global_store_b32 v0, v2, s[0:1]
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
s_branch .LBB0_3
.LBB0_6:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 408
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testPf, .Lfunc_end0-_Z4testPf
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testPf
.private_segment_fixed_size: 408
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z4testPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
============================================================================
Name : LAB3.cu
Author : Kineibe
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <string>
#include <fstream>
#include <sstream>
using namespace std;
static void CheckCudaErrorAux (const char *, unsigned, const char *, cudaError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
#define H_T 0.0001
#define H_X 0.5
#define TOTAL_TIME 10
#define EPSILON 0.001
#define RIGHT_COND 1
#define LEFT_COND 0
#define BLOCK_SIZE_AMOUNT 256
const double A = H_T / (H_X * H_X);
const double B = 2 * A + 1;
double countSum(int k, double* t, int size) {
if (k == 0) {
return t[k] * 1;
} else if (k == size - 1) {
return -1 * t[k - 1] / H_X + t[k] / H_X;
} else {
return -1 * A * t[k - 1] + t[k] / B - A * t[k + 1];
}
}
double iterationPart(double prev, double multiplier, double f, double sum) {
return prev + (f - sum) / multiplier;
}
void iteration(double* t_prev, int size, double* f, double* t_result) {
for (int i = 0; i < size; ++i) {
double a;
if (i == 0)
a = 1;
else if (i == size - 1)
a = 1 / H_X;
else
a = B;
double sum = countSum(i, t_prev, size);
double newT = iterationPart(t_prev[i], a, f[i], sum);
t_result[i] = newT;
}
}
bool condition(double* t_prev, double* t_result, int size) {
double result = 0;
for (int i = 0; i < size; ++i) {
result += abs(t_prev[i] - t_result[i]);
}
return result < EPSILON;
}
void iterationManager(double* t_prev, int size, double* f, double* t_target) {
bool check = true;
double* t_result = new double[size];
do {
iteration(t_prev, size, f, t_result);
check = condition(t_prev, t_result, size);
double* temp = t_result;
t_result = t_prev;
t_prev = temp;
} while(!check);
for (int i = 0; i < size; ++i) {
t_target[i] = t_prev[i];
}
delete[] t_result;
}
void printMas(double* arr, int size) {
for (int i = 0; i < size; ++i) {
cout << arr[i] << ' ';
}
cout << endl;
}
void model(int size) {
double* t = new double[size];
for (int i = 0; i < size; ++i) {
t[i] = 0;
}
double* t_next = new double[size];
double* f = new double[size];
f[0] = LEFT_COND;
f[size - 1] = RIGHT_COND;
// int iterationAmount = TOTAL_TIME / H_T;
int iterationAmount = 10;
for (int i = 0; i < iterationAmount; ++i) {
cout << "Iteration num " << i << endl;
for (int i = 1; i < size - 1; ++i) {
f[i] = t[i];
}
cout << "F array" << endl;
printMas(f, size);
iterationManager(t, size, f, t_next);
printMas(t_next, size);
double* temp = t_next;
t_next = t;
t = temp;
}
delete[] t_next;
delete[] f;
delete[] t;
}
/**
* CUDA kernel that computes reciprocal values for a given vector
*/
__global__ void reciprocalKernel(float *data, float *newData, unsigned vectorSize) {
unsigned idx = blockIdx.x*blockDim.x+threadIdx.x;
if (idx < vectorSize) {
if (idx == vectorSize - 1) {
newData[idx] = RIGHT_COND * H_T + data[idx];
} else if (idx == 0) {
newData[idx] = LEFT_COND;
} else {
newData[idx] = data[idx] + (data[idx - 1] - 2 * data[idx] + data[idx + 1]) * H_T / (H_X * H_X);
}
}
}
/**
* Host function that copies the data and launches the work on GPU
*/
void gpuReciprocal(float *data, unsigned size)
{
cudaEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
float *rc = new float[size];
float *gpuOldData;
float *gpuNewData;
int iterationAmount = TOTAL_TIME / H_T;
static const int BLOCK_SIZE = BLOCK_SIZE_AMOUNT;
const int blockCount = 1000;
CUDA_CHECK_RETURN(cudaMalloc((void **)&gpuOldData, sizeof(float)*size));
CUDA_CHECK_RETURN(cudaMalloc((void **)&gpuNewData, sizeof(float)*size));
CUDA_CHECK_RETURN(cudaMemcpy(gpuOldData, data, sizeof(float)*size, cudaMemcpyHostToDevice));
cudaEventCreate(&GPUstart);
cudaEventCreate(&GPUstop);
for (int i = 0; i < iterationAmount; ++i) {
cudaEventRecord(GPUstart, 0);
if (i % 2 == 0) {
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuOldData, gpuNewData, size);
cudaEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(cudaMemcpy(rc, gpuNewData, sizeof(float)*size, cudaMemcpyDeviceToHost));
} else {
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuNewData, gpuOldData, size);
cudaEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(cudaMemcpy(rc, gpuOldData, sizeof(float)*size, cudaMemcpyDeviceToHost));
}
cudaEventSynchronize(GPUstop);
float temp;
cudaEventElapsedTime(&temp, GPUstart, GPUstop);
GPUtime += temp;
//
// for (int i = 0; i < size; ++i) {
// std::cout << "t[" << i << "] = " << rc[i] << std::endl;
// }
// std::cout << std::endl;
}
printf("GPU time : %.3f ms\n", GPUtime);
CUDA_CHECK_RETURN(cudaFree(gpuOldData));
CUDA_CHECK_RETURN(cudaFree(gpuNewData));
}
void initialize(float *data, unsigned size)
{
for (unsigned i = 0; i < size; ++i)
data[i] = 0;
}
void cpuIteration(float *data, float *newData, unsigned vectorSize) {
for (int idx = 0; idx < vectorSize; ++idx) {
if (idx == vectorSize - 1) {
newData[idx] = RIGHT_COND * H_T + data[idx];
} else if (idx == 0) {
newData[idx] = LEFT_COND;
} else {
newData[idx] = data[idx] + (data[idx - 1] - 2 * data[idx] + data[idx + 1]) * H_T / (H_X * H_X);
}
}
}
void cpuReciprocal(float *data, unsigned size)
{
float *rc = new float[size];
float *oldData = new float[size];
float* result;
float CPUstart, CPUstop;
float CPUtime = 0.0f;
int iterationAmount = TOTAL_TIME / H_T;
for (int i = 0; i < iterationAmount; ++i) {
CPUstart = clock();
if (i % 2 == 0) {
cpuIteration(oldData, rc, size);
result = rc;
} else {
cpuIteration(rc, oldData, size);
result = oldData;
}
CPUstop = clock();
CPUtime += 1000.*(CPUstop - CPUstart) / CLOCKS_PER_SEC;
//
// for (int i = 0; i < size; ++i) {
// std::cout << "t[" << i << "] = " << result[i] << std::endl;
// }
// std::cout << std::endl;
}
printf("CPU time : %.3f ms\n", CPUtime);
}
bool checkShodimost() {
return true;
}
int main(void)
{
static const int WORK_SIZE = 256000;
float *data = new float[WORK_SIZE];
model(5);
/* Free memory */
delete[] data;
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, cudaError_t err)
{
if (err == cudaSuccess)
return;
std::cerr << statement<<" returned " << cudaGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} | code for sm_80
Function : _Z16reciprocalKernelPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0070*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0080*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fcc000fffe03f */
/*0090*/ ISETP.NE.AND P0, PT, R0.reuse, UR4, PT ; /* 0x0000000400007c0c */
/* 0x040fe2000bf05270 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ IMAD.WIDE.U32 R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e000b */
/*00c0*/ IMAD.WIDE.U32 R2, R0, R11, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e000b */
/*00d0*/ @!P0 BRA 0x230 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*00f0*/ @!P0 BRA 0x210 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R8, R0.reuse, -0x1, RZ ; /* 0xffffffff00087810 */
/* 0x040fe20007ffe0ff */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R10, R0, 0x1, RZ ; /* 0x00000001000a7810 */
/* 0x000fc60007ffe0ff */
/*0130*/ IMAD.WIDE.U32 R8, R8, R11, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e000b */
/*0140*/ IMAD.WIDE.U32 R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fe400078e000b */
/*0150*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f22000c1e1900 */
/*0170*/ FADD R7, R4, R4 ; /* 0x0000000404077221 */
/* 0x004fc80000000000 */
/*0180*/ FADD R7, R8, -R7 ; /* 0x8000000708077221 */
/* 0x008fc80000000000 */
/*0190*/ FADD R0, R7, R10 ; /* 0x0000000a07007221 */
/* 0x010fc80000000000 */
/*01a0*/ F2F.F64.F32 R12, R0 ; /* 0x00000000000c7310 */
/* 0x000e300000201800 */
/*01b0*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */
/* 0x000e620000201800 */
/*01c0*/ DMUL R12, R12, c[0x2][0x0] ; /* 0x008000000c0c7a28 */
/* 0x001e4c0000000000 */
/*01d0*/ DFMA R6, R12, 4, R6 ; /* 0x401000000c06782b */
/* 0x002e140000000006 */
/*01e0*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*01f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0240*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */
/* 0x004e240000201800 */
/*0250*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x001e140000000000 */
/*0260*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*0270*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
============================================================================
Name : LAB3.cu
Author : Kineibe
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <string>
#include <fstream>
#include <sstream>
using namespace std;
static void CheckCudaErrorAux (const char *, unsigned, const char *, cudaError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
#define H_T 0.0001
#define H_X 0.5
#define TOTAL_TIME 10
#define EPSILON 0.001
#define RIGHT_COND 1
#define LEFT_COND 0
#define BLOCK_SIZE_AMOUNT 256
const double A = H_T / (H_X * H_X);
const double B = 2 * A + 1;
double countSum(int k, double* t, int size) {
if (k == 0) {
return t[k] * 1;
} else if (k == size - 1) {
return -1 * t[k - 1] / H_X + t[k] / H_X;
} else {
return -1 * A * t[k - 1] + t[k] / B - A * t[k + 1];
}
}
double iterationPart(double prev, double multiplier, double f, double sum) {
return prev + (f - sum) / multiplier;
}
void iteration(double* t_prev, int size, double* f, double* t_result) {
for (int i = 0; i < size; ++i) {
double a;
if (i == 0)
a = 1;
else if (i == size - 1)
a = 1 / H_X;
else
a = B;
double sum = countSum(i, t_prev, size);
double newT = iterationPart(t_prev[i], a, f[i], sum);
t_result[i] = newT;
}
}
bool condition(double* t_prev, double* t_result, int size) {
double result = 0;
for (int i = 0; i < size; ++i) {
result += abs(t_prev[i] - t_result[i]);
}
return result < EPSILON;
}
void iterationManager(double* t_prev, int size, double* f, double* t_target) {
bool check = true;
double* t_result = new double[size];
do {
iteration(t_prev, size, f, t_result);
check = condition(t_prev, t_result, size);
double* temp = t_result;
t_result = t_prev;
t_prev = temp;
} while(!check);
for (int i = 0; i < size; ++i) {
t_target[i] = t_prev[i];
}
delete[] t_result;
}
void printMas(double* arr, int size) {
for (int i = 0; i < size; ++i) {
cout << arr[i] << ' ';
}
cout << endl;
}
void model(int size) {
double* t = new double[size];
for (int i = 0; i < size; ++i) {
t[i] = 0;
}
double* t_next = new double[size];
double* f = new double[size];
f[0] = LEFT_COND;
f[size - 1] = RIGHT_COND;
// int iterationAmount = TOTAL_TIME / H_T;
int iterationAmount = 10;
for (int i = 0; i < iterationAmount; ++i) {
cout << "Iteration num " << i << endl;
for (int i = 1; i < size - 1; ++i) {
f[i] = t[i];
}
cout << "F array" << endl;
printMas(f, size);
iterationManager(t, size, f, t_next);
printMas(t_next, size);
double* temp = t_next;
t_next = t;
t = temp;
}
delete[] t_next;
delete[] f;
delete[] t;
}
/**
* CUDA kernel that computes reciprocal values for a given vector
*/
__global__ void reciprocalKernel(float *data, float *newData, unsigned vectorSize) {
unsigned idx = blockIdx.x*blockDim.x+threadIdx.x;
if (idx < vectorSize) {
if (idx == vectorSize - 1) {
newData[idx] = RIGHT_COND * H_T + data[idx];
} else if (idx == 0) {
newData[idx] = LEFT_COND;
} else {
newData[idx] = data[idx] + (data[idx - 1] - 2 * data[idx] + data[idx + 1]) * H_T / (H_X * H_X);
}
}
}
/**
* Host function that copies the data and launches the work on GPU
*/
void gpuReciprocal(float *data, unsigned size)
{
cudaEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
float *rc = new float[size];
float *gpuOldData;
float *gpuNewData;
int iterationAmount = TOTAL_TIME / H_T;
static const int BLOCK_SIZE = BLOCK_SIZE_AMOUNT;
const int blockCount = 1000;
CUDA_CHECK_RETURN(cudaMalloc((void **)&gpuOldData, sizeof(float)*size));
CUDA_CHECK_RETURN(cudaMalloc((void **)&gpuNewData, sizeof(float)*size));
CUDA_CHECK_RETURN(cudaMemcpy(gpuOldData, data, sizeof(float)*size, cudaMemcpyHostToDevice));
cudaEventCreate(&GPUstart);
cudaEventCreate(&GPUstop);
for (int i = 0; i < iterationAmount; ++i) {
cudaEventRecord(GPUstart, 0);
if (i % 2 == 0) {
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuOldData, gpuNewData, size);
cudaEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(cudaMemcpy(rc, gpuNewData, sizeof(float)*size, cudaMemcpyDeviceToHost));
} else {
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuNewData, gpuOldData, size);
cudaEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(cudaMemcpy(rc, gpuOldData, sizeof(float)*size, cudaMemcpyDeviceToHost));
}
cudaEventSynchronize(GPUstop);
float temp;
cudaEventElapsedTime(&temp, GPUstart, GPUstop);
GPUtime += temp;
//
// for (int i = 0; i < size; ++i) {
// std::cout << "t[" << i << "] = " << rc[i] << std::endl;
// }
// std::cout << std::endl;
}
printf("GPU time : %.3f ms\n", GPUtime);
CUDA_CHECK_RETURN(cudaFree(gpuOldData));
CUDA_CHECK_RETURN(cudaFree(gpuNewData));
}
void initialize(float *data, unsigned size)
{
for (unsigned i = 0; i < size; ++i)
data[i] = 0;
}
void cpuIteration(float *data, float *newData, unsigned vectorSize) {
for (int idx = 0; idx < vectorSize; ++idx) {
if (idx == vectorSize - 1) {
newData[idx] = RIGHT_COND * H_T + data[idx];
} else if (idx == 0) {
newData[idx] = LEFT_COND;
} else {
newData[idx] = data[idx] + (data[idx - 1] - 2 * data[idx] + data[idx + 1]) * H_T / (H_X * H_X);
}
}
}
void cpuReciprocal(float *data, unsigned size)
{
float *rc = new float[size];
float *oldData = new float[size];
float* result;
float CPUstart, CPUstop;
float CPUtime = 0.0f;
int iterationAmount = TOTAL_TIME / H_T;
for (int i = 0; i < iterationAmount; ++i) {
CPUstart = clock();
if (i % 2 == 0) {
cpuIteration(oldData, rc, size);
result = rc;
} else {
cpuIteration(rc, oldData, size);
result = oldData;
}
CPUstop = clock();
CPUtime += 1000.*(CPUstop - CPUstart) / CLOCKS_PER_SEC;
//
// for (int i = 0; i < size; ++i) {
// std::cout << "t[" << i << "] = " << result[i] << std::endl;
// }
// std::cout << std::endl;
}
printf("CPU time : %.3f ms\n", CPUtime);
}
bool checkShodimost() {
return true;
}
int main(void)
{
static const int WORK_SIZE = 256000;
float *data = new float[WORK_SIZE];
model(5);
/* Free memory */
delete[] data;
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, cudaError_t err)
{
if (err == cudaSuccess)
return;
std::cerr << statement<<" returned " << cudaGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} | .file "tmpxft_001272f1_00000000-6_LAB2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " returned "
.LC1:
.string "("
.LC2:
.string ") at "
.LC3:
.string ":"
#NO_APP
.text
.type _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, @function
_ZL17CheckCudaErrorAuxPKcjS0_9cudaError:
.LFB3909:
.cfi_startproc
testl %ecx, %ecx
jne .L7
ret
.L7:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %r12d
movl %ecx, %ebx
movq %rdx, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %r13
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3909:
.size _ZL17CheckCudaErrorAuxPKcjS0_9cudaError, .-_ZL17CheckCudaErrorAuxPKcjS0_9cudaError
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3912:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3912:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8countSumiPdi
.type _Z8countSumiPdi, @function
_Z8countSumiPdi:
.LFB3896:
.cfi_startproc
endbr64
testl %edi, %edi
je .L14
subl $1, %edx
cmpl %edi, %edx
je .L15
movslq %edi, %rdi
movsd .LC5(%rip), %xmm0
mulsd -8(%rsi,%rdi,8), %xmm0
movsd (%rsi,%rdi,8), %xmm1
divsd .LC6(%rip), %xmm1
addsd %xmm1, %xmm0
movsd .LC7(%rip), %xmm1
mulsd 8(%rsi,%rdi,8), %xmm1
subsd %xmm1, %xmm0
ret
.L14:
movsd (%rsi), %xmm0
ret
.L15:
movslq %edi, %rdi
movsd -8(%rsi,%rdi,8), %xmm0
xorpd .LC4(%rip), %xmm0
addsd %xmm0, %xmm0
movsd (%rsi,%rdi,8), %xmm1
addsd %xmm1, %xmm1
addsd %xmm1, %xmm0
ret
.cfi_endproc
.LFE3896:
.size _Z8countSumiPdi, .-_Z8countSumiPdi
.globl _Z13iterationPartdddd
.type _Z13iterationPartdddd, @function
_Z13iterationPartdddd:
.LFB3897:
.cfi_startproc
endbr64
subsd %xmm3, %xmm2
divsd %xmm1, %xmm2
addsd %xmm2, %xmm0
ret
.cfi_endproc
.LFE3897:
.size _Z13iterationPartdddd, .-_Z13iterationPartdddd
.globl _Z9iterationPdiS_S_
.type _Z9iterationPdiS_S_, @function
_Z9iterationPdiS_S_:
.LFB3898:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L25
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $16, %rsp
.cfi_def_cfa_offset 72
movq %rdi, %rbp
movl %esi, %r12d
movq %rdx, %r13
movq %rcx, %r14
movslq %esi, %r15
movl $0, %ebx
leal -1(%rsi), %eax
movl %eax, 12(%rsp)
jmp .L20
.L19:
movl %r12d, %edx
movq %rbp, %rsi
call _Z8countSumiPdi
movapd %xmm0, %xmm1
movsd 0(%r13,%rbx,8), %xmm0
subsd %xmm1, %xmm0
divsd (%rsp), %xmm0
addsd 0(%rbp,%rbx,8), %xmm0
movsd %xmm0, (%r14,%rbx,8)
addq $1, %rbx
cmpq %r15, %rbx
je .L28
.L20:
movl %ebx, %edi
movsd .LC8(%rip), %xmm2
movsd %xmm2, (%rsp)
testl %ebx, %ebx
je .L19
movsd .LC6(%rip), %xmm4
movsd %xmm4, (%rsp)
cmpl %ebx, 12(%rsp)
jne .L19
movsd .LC9(%rip), %xmm5
movsd %xmm5, (%rsp)
jmp .L19
.L28:
addq $16, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE3898:
.size _Z9iterationPdiS_S_, .-_Z9iterationPdiS_S_
.globl _Z9conditionPdS_i
.type _Z9conditionPdS_i, @function
_Z9conditionPdS_i:
.LFB3899:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L32
movslq %edx, %rdx
salq $3, %rdx
movl $0, %eax
pxor %xmm1, %xmm1
movq .LC11(%rip), %xmm2
.L31:
movsd (%rdi,%rax), %xmm0
subsd (%rsi,%rax), %xmm0
andpd %xmm2, %xmm0
addsd %xmm0, %xmm1
addq $8, %rax
cmpq %rax, %rdx
jne .L31
.L30:
movsd .LC12(%rip), %xmm0
comisd %xmm1, %xmm0
seta %al
ret
.L32:
pxor %xmm1, %xmm1
jmp .L30
.cfi_endproc
.LFE3899:
.size _Z9conditionPdS_i, .-_Z9conditionPdS_i
.globl _Z16iterationManagerPdiS_S_
.type _Z16iterationManagerPdiS_S_, @function
_Z16iterationManagerPdiS_S_:
.LFB3900:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movslq %esi, %r13
movq %r13, %rax
shrq $60, %rax
jne .L35
movq %rdi, %rbp
movl %esi, %r12d
movq %rdx, %r15
movq %rcx, %r14
salq $3, %r13
movq %r13, %rdi
call _Znam@PLT
movq %rax, %rbx
jmp .L36
.L35:
call __cxa_throw_bad_array_new_length@PLT
.L40:
movq %rbp, %rax
movq %rbx, %rbp
movq %rax, %rbx
.L36:
movq %rbx, %rcx
movq %r15, %rdx
movl %r12d, %esi
movq %rbp, %rdi
call _Z9iterationPdiS_S_
movl %r12d, %edx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z9conditionPdS_i
testb %al, %al
je .L40
testl %r12d, %r12d
jle .L37
movl $0, %eax
.L38:
movsd (%rbx,%rax), %xmm0
movsd %xmm0, (%r14,%rax)
addq $8, %rax
cmpq %rax, %r13
jne .L38
.L37:
testq %rbp, %rbp
je .L34
movq %rbp, %rdi
call _ZdaPv@PLT
.L34:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3900:
.size _Z16iterationManagerPdiS_S_, .-_Z16iterationManagerPdiS_S_
.globl _Z8printMasPdi
.type _Z8printMasPdi, @function
_Z8printMasPdi:
.LFB3901:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
testl %esi, %esi
jle .L44
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %r12
leaq _ZSt4cout(%rip), %rbp
jmp .L47
.L45:
movl $32, %esi
call _ZNSo3putEc@PLT
.L46:
addq $8, %rbx
cmpq %r12, %rbx
je .L44
.L47:
movsd (%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $32, 7(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L45
leaq 7(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L46
.L44:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L55
cmpb $0, 56(%rbx)
je .L50
movzbl 67(%rbx), %esi
.L51:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L57
call _ZSt16__throw_bad_castv@PLT
.L57:
call __stack_chk_fail@PLT
.L50:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3901:
.size _Z8printMasPdi, .-_Z8printMasPdi
.section .rodata.str1.1
.LC13:
.string "Iteration num "
.LC14:
.string "F array"
.text
.globl _Z5modeli
.type _Z5modeli, @function
_Z5modeli:
.LFB3902:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, 8(%rsp)
movslq %edi, %r12
movq %r12, %rax
shrq $60, %rax
jne .L59
movl %edi, %r15d
salq $3, %r12
movq %r12, %rdi
call _Znam@PLT
movq %rax, %rbx
leaq (%r12,%rax), %rdx
testl %r15d, %r15d
jle .L61
.L62:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L62
.L61:
movq %r12, %rdi
call _Znam@PLT
movq %rax, (%rsp)
movq %r12, %rdi
call _Znam@PLT
movq %rax, %rbp
movq $0x000000000, (%rax)
movq .LC8(%rip), %rax
movq %rax, -8(%rbp,%r12)
movl $0, %r15d
leaq _ZSt4cout(%rip), %r12
movl 8(%rsp), %eax
subl $1, %eax
movl %eax, 12(%rsp)
jmp .L71
.L59:
call __cxa_throw_bad_array_new_length@PLT
.L80:
call _ZSt16__throw_bad_castv@PLT
.L64:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L65
.L81:
call _ZSt16__throw_bad_castv@PLT
.L82:
movzbl 67(%r13), %esi
.L70:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl 8(%rsp), %r14d
movl %r14d, %esi
movq %rbp, %rdi
call _Z8printMasPdi
movq (%rsp), %r13
movq %r13, %rcx
movq %rbp, %rdx
movl %r14d, %esi
movq %rbx, %rdi
call _Z16iterationManagerPdiS_S_
movl %r14d, %esi
movq %r13, %rdi
call _Z8printMasPdi
addl $1, %r15d
cmpl $10, %r15d
je .L79
movq %rbx, %rax
movq (%rsp), %rbx
movq %rax, (%rsp)
.L71:
movl $14, %edx
leaq .LC13(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r15d, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r14
testq %r14, %r14
je .L80
cmpb $0, 56(%r14)
je .L64
movzbl 67(%r14), %esi
.L65:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
cmpl $2, 8(%rsp)
jle .L66
movl 12(%rsp), %edx
movl $1, %eax
.L67:
movsd (%rbx,%rax,8), %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
addq $1, %rax
cmpq %rdx, %rax
jne .L67
.L66:
movl $7, %edx
leaq .LC14(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .L81
cmpb $0, 56(%r13)
jne .L82
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L70
.L79:
testq %rbx, %rbx
je .L72
movq %rbx, %rdi
call _ZdaPv@PLT
.L72:
movq %rbp, %rdi
call _ZdaPv@PLT
movq (%rsp), %rax
testq %rax, %rax
je .L58
movq %rax, %rdi
call _ZdaPv@PLT
.L58:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3902:
.size _Z5modeli, .-_Z5modeli
.globl _Z10initializePfj
.type _Z10initializePfj, @function
_Z10initializePfj:
.LFB3904:
.cfi_startproc
endbr64
testl %esi, %esi
je .L83
movq %rdi, %rax
movl %esi, %esi
leaq (%rdi,%rsi,4), %rdx
.L85:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L85
.L83:
ret
.cfi_endproc
.LFE3904:
.size _Z10initializePfj, .-_Z10initializePfj
.globl _Z12cpuIterationPfS_j
.type _Z12cpuIterationPfS_j, @function
_Z12cpuIterationPfS_j:
.LFB3905:
.cfi_startproc
endbr64
movq %rdi, %rcx
testl %edx, %edx
je .L87
movl %edx, %edi
movl $0, %eax
subl $1, %edx
movsd .LC16(%rip), %xmm3
movsd .LC17(%rip), %xmm2
movapd %xmm3, %xmm4
jmp .L92
.L94:
pxor %xmm0, %xmm0
cvtss2sd (%rcx,%rax,4), %xmm0
addsd %xmm4, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsi,%rax,4)
jmp .L90
.L95:
movl $0x00000000, (%rsi)
.L90:
addq $1, %rax
cmpq %rdi, %rax
je .L87
.L92:
cmpl %eax, %edx
je .L94
testl %eax, %eax
je .L95
movss (%rcx,%rax,4), %xmm1
movaps %xmm1, %xmm5
addss %xmm1, %xmm5
movss -4(%rcx,%rax,4), %xmm0
subss %xmm5, %xmm0
addss 4(%rcx,%rax,4), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm3, %xmm0
mulsd %xmm2, %xmm0
cvtss2sd %xmm1, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsi,%rax,4)
jmp .L90
.L87:
ret
.cfi_endproc
.LFE3905:
.size _Z12cpuIterationPfS_j, .-_Z12cpuIterationPfS_j
.section .rodata.str1.1
.LC20:
.string "CPU time : %.3f ms\n"
.text
.globl _Z13cpuReciprocalPfj
.type _Z13cpuReciprocalPfj, @function
_Z13cpuReciprocalPfj:
.LFB3906:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movl %esi, %ebp
movl %esi, %ebx
salq $2, %rbx
movq %rbx, %rdi
call _Znam@PLT
movq %rax, %r13
movq %rbx, %rdi
call _Znam@PLT
movq %rax, %r12
movl $0, %ebx
movl $0x00000000, 8(%rsp)
jmp .L99
.L97:
movl %ebp, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z12cpuIterationPfS_j
.L98:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
subss 12(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC18(%rip), %xmm0
divsd .LC19(%rip), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 8(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm4, %xmm4
cvtsd2ss %xmm0, %xmm4
movss %xmm4, 8(%rsp)
addl $1, %ebx
cmpl $100000, %ebx
je .L102
.L99:
call clock@PLT
pxor %xmm2, %xmm2
cvtsi2ssq %rax, %xmm2
movss %xmm2, 12(%rsp)
testb $1, %bl
jne .L97
movl %ebp, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z12cpuIterationPfS_j
jmp .L98
.L102:
pxor %xmm0, %xmm0
cvtss2sd %xmm4, %xmm0
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3906:
.size _Z13cpuReciprocalPfj, .-_Z13cpuReciprocalPfj
.globl _Z14checkShodimostv
.type _Z14checkShodimostv, @function
_Z14checkShodimostv:
.LFB3907:
.cfi_startproc
endbr64
movl $1, %eax
ret
.cfi_endproc
.LFE3907:
.size _Z14checkShodimostv, .-_Z14checkShodimostv
.globl main
.type main, @function
main:
.LFB3908:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $5, %edi
call _Z5modeli
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3908:
.size main, .-main
.globl _Z39__device_stub__Z16reciprocalKernelPfS_jPfS_j
.type _Z39__device_stub__Z16reciprocalKernelPfS_jPfS_j, @function
_Z39__device_stub__Z16reciprocalKernelPfS_jPfS_j:
.LFB3934:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L110
.L106:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L111
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L110:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16reciprocalKernelPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L106
.L111:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3934:
.size _Z39__device_stub__Z16reciprocalKernelPfS_jPfS_j, .-_Z39__device_stub__Z16reciprocalKernelPfS_jPfS_j
.globl _Z16reciprocalKernelPfS_j
.type _Z16reciprocalKernelPfS_j, @function
_Z16reciprocalKernelPfS_j:
.LFB3935:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16reciprocalKernelPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3935:
.size _Z16reciprocalKernelPfS_j, .-_Z16reciprocalKernelPfS_j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC21:
.string "cudaMalloc((void **)&gpuOldData, sizeof(float)*size)"
.align 8
.LC22:
.string "/home/ubuntu/Datasets/stackv2/train-structured/neikila/Cuda/master/LAB2.cu"
.align 8
.LC23:
.string "cudaMalloc((void **)&gpuNewData, sizeof(float)*size)"
.align 8
.LC24:
.string "cudaMemcpy(gpuOldData, data, sizeof(float)*size, cudaMemcpyHostToDevice)"
.align 8
.LC25:
.string "cudaMemcpy(rc, gpuNewData, sizeof(float)*size, cudaMemcpyDeviceToHost)"
.align 8
.LC26:
.string "cudaMemcpy(rc, gpuOldData, sizeof(float)*size, cudaMemcpyDeviceToHost)"
.section .rodata.str1.1
.LC27:
.string "GPU time : %.3f ms\n"
.LC28:
.string "cudaFree(gpuOldData)"
.LC29:
.string "cudaFree(gpuNewData)"
.text
.globl _Z13gpuReciprocalPfj
.type _Z13gpuReciprocalPfj, @function
_Z13gpuReciprocalPfj:
.LFB3903:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r13
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %esi, %ebp
salq $2, %rbp
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %r12
leaq 32(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC21(%rip), %rdx
movl $164, %esi
leaq .LC22(%rip), %rbx
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq 40(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %ecx
leaq .LC23(%rip), %rdx
movl $165, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC24(%rip), %rdx
movl $166, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %ebx
movl $0x00000000, 8(%rsp)
leaq .LC26(%rip), %r15
leaq .LC22(%rip), %r14
leaq 60(%rsp), %r13
jmp .L119
.L116:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
leaq .LC25(%rip), %rdx
movl $178, %esi
movq %r14, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
.L117:
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaEventElapsedTime@PLT
movss 8(%rsp), %xmm1
addss 60(%rsp), %xmm1
movss %xmm1, 8(%rsp)
addl $1, %ebx
cmpl $100000, %ebx
je .L123
.L119:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
testb $1, %bl
jne .L115
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1000, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L116
movl 12(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z39__device_stub__Z16reciprocalKernelPfS_jPfS_j
jmp .L116
.L115:
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1000, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L124
.L118:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %ecx
movq %r15, %rdx
movl $182, %esi
movq %r14, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
jmp .L117
.L124:
movl 12(%rsp), %edx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z39__device_stub__Z16reciprocalKernelPfS_jPfS_j
jmp .L118
.L123:
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ecx
leaq .LC28(%rip), %rdx
movl $198, %esi
leaq .LC22(%rip), %rbx
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ecx
leaq .LC29(%rip), %rdx
movl $199, %esi
movq %rbx, %rdi
call _ZL17CheckCudaErrorAuxPKcjS0_9cudaError
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L125
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L125:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3903:
.size _Z13gpuReciprocalPfj, .-_Z13gpuReciprocalPfj
.section .rodata.str1.1
.LC30:
.string "_Z16reciprocalKernelPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3937:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _Z16reciprocalKernelPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3937:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long -350469331
.long -1086703902
.align 8
.LC6:
.long -597859448
.long 1072694086
.align 8
.LC7:
.long -350469331
.long 1060779746
.align 8
.LC8:
.long 0
.long 1072693248
.align 8
.LC9:
.long 0
.long 1073741824
.section .rodata.cst16
.align 16
.LC11:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC12:
.long -755914244
.long 1062232653
.align 8
.LC16:
.long -350469331
.long 1058682594
.align 8
.LC17:
.long 0
.long 1074790400
.align 8
.LC18:
.long 0
.long 1083129856
.align 8
.LC19:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
============================================================================
Name : LAB3.cu
Author : Kineibe
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <string>
#include <fstream>
#include <sstream>
using namespace std;
static void CheckCudaErrorAux (const char *, unsigned, const char *, cudaError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
#define H_T 0.0001
#define H_X 0.5
#define TOTAL_TIME 10
#define EPSILON 0.001
#define RIGHT_COND 1
#define LEFT_COND 0
#define BLOCK_SIZE_AMOUNT 256
const double A = H_T / (H_X * H_X);
const double B = 2 * A + 1;
double countSum(int k, double* t, int size) {
if (k == 0) {
return t[k] * 1;
} else if (k == size - 1) {
return -1 * t[k - 1] / H_X + t[k] / H_X;
} else {
return -1 * A * t[k - 1] + t[k] / B - A * t[k + 1];
}
}
double iterationPart(double prev, double multiplier, double f, double sum) {
return prev + (f - sum) / multiplier;
}
void iteration(double* t_prev, int size, double* f, double* t_result) {
for (int i = 0; i < size; ++i) {
double a;
if (i == 0)
a = 1;
else if (i == size - 1)
a = 1 / H_X;
else
a = B;
double sum = countSum(i, t_prev, size);
double newT = iterationPart(t_prev[i], a, f[i], sum);
t_result[i] = newT;
}
}
bool condition(double* t_prev, double* t_result, int size) {
double result = 0;
for (int i = 0; i < size; ++i) {
result += abs(t_prev[i] - t_result[i]);
}
return result < EPSILON;
}
void iterationManager(double* t_prev, int size, double* f, double* t_target) {
bool check = true;
double* t_result = new double[size];
do {
iteration(t_prev, size, f, t_result);
check = condition(t_prev, t_result, size);
double* temp = t_result;
t_result = t_prev;
t_prev = temp;
} while(!check);
for (int i = 0; i < size; ++i) {
t_target[i] = t_prev[i];
}
delete[] t_result;
}
void printMas(double* arr, int size) {
for (int i = 0; i < size; ++i) {
cout << arr[i] << ' ';
}
cout << endl;
}
void model(int size) {
double* t = new double[size];
for (int i = 0; i < size; ++i) {
t[i] = 0;
}
double* t_next = new double[size];
double* f = new double[size];
f[0] = LEFT_COND;
f[size - 1] = RIGHT_COND;
// int iterationAmount = TOTAL_TIME / H_T;
int iterationAmount = 10;
for (int i = 0; i < iterationAmount; ++i) {
cout << "Iteration num " << i << endl;
for (int i = 1; i < size - 1; ++i) {
f[i] = t[i];
}
cout << "F array" << endl;
printMas(f, size);
iterationManager(t, size, f, t_next);
printMas(t_next, size);
double* temp = t_next;
t_next = t;
t = temp;
}
delete[] t_next;
delete[] f;
delete[] t;
}
/**
* CUDA kernel that computes reciprocal values for a given vector
*/
__global__ void reciprocalKernel(float *data, float *newData, unsigned vectorSize) {
unsigned idx = blockIdx.x*blockDim.x+threadIdx.x;
if (idx < vectorSize) {
if (idx == vectorSize - 1) {
newData[idx] = RIGHT_COND * H_T + data[idx];
} else if (idx == 0) {
newData[idx] = LEFT_COND;
} else {
newData[idx] = data[idx] + (data[idx - 1] - 2 * data[idx] + data[idx + 1]) * H_T / (H_X * H_X);
}
}
}
/**
* Host function that copies the data and launches the work on GPU
*/
void gpuReciprocal(float *data, unsigned size)
{
cudaEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
float *rc = new float[size];
float *gpuOldData;
float *gpuNewData;
int iterationAmount = TOTAL_TIME / H_T;
static const int BLOCK_SIZE = BLOCK_SIZE_AMOUNT;
const int blockCount = 1000;
CUDA_CHECK_RETURN(cudaMalloc((void **)&gpuOldData, sizeof(float)*size));
CUDA_CHECK_RETURN(cudaMalloc((void **)&gpuNewData, sizeof(float)*size));
CUDA_CHECK_RETURN(cudaMemcpy(gpuOldData, data, sizeof(float)*size, cudaMemcpyHostToDevice));
cudaEventCreate(&GPUstart);
cudaEventCreate(&GPUstop);
for (int i = 0; i < iterationAmount; ++i) {
cudaEventRecord(GPUstart, 0);
if (i % 2 == 0) {
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuOldData, gpuNewData, size);
cudaEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(cudaMemcpy(rc, gpuNewData, sizeof(float)*size, cudaMemcpyDeviceToHost));
} else {
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuNewData, gpuOldData, size);
cudaEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(cudaMemcpy(rc, gpuOldData, sizeof(float)*size, cudaMemcpyDeviceToHost));
}
cudaEventSynchronize(GPUstop);
float temp;
cudaEventElapsedTime(&temp, GPUstart, GPUstop);
GPUtime += temp;
//
// for (int i = 0; i < size; ++i) {
// std::cout << "t[" << i << "] = " << rc[i] << std::endl;
// }
// std::cout << std::endl;
}
printf("GPU time : %.3f ms\n", GPUtime);
CUDA_CHECK_RETURN(cudaFree(gpuOldData));
CUDA_CHECK_RETURN(cudaFree(gpuNewData));
}
void initialize(float *data, unsigned size)
{
for (unsigned i = 0; i < size; ++i)
data[i] = 0;
}
void cpuIteration(float *data, float *newData, unsigned vectorSize) {
for (int idx = 0; idx < vectorSize; ++idx) {
if (idx == vectorSize - 1) {
newData[idx] = RIGHT_COND * H_T + data[idx];
} else if (idx == 0) {
newData[idx] = LEFT_COND;
} else {
newData[idx] = data[idx] + (data[idx - 1] - 2 * data[idx] + data[idx + 1]) * H_T / (H_X * H_X);
}
}
}
void cpuReciprocal(float *data, unsigned size)
{
float *rc = new float[size];
float *oldData = new float[size];
float* result;
float CPUstart, CPUstop;
float CPUtime = 0.0f;
int iterationAmount = TOTAL_TIME / H_T;
for (int i = 0; i < iterationAmount; ++i) {
CPUstart = clock();
if (i % 2 == 0) {
cpuIteration(oldData, rc, size);
result = rc;
} else {
cpuIteration(rc, oldData, size);
result = oldData;
}
CPUstop = clock();
CPUtime += 1000.*(CPUstop - CPUstart) / CLOCKS_PER_SEC;
//
// for (int i = 0; i < size; ++i) {
// std::cout << "t[" << i << "] = " << result[i] << std::endl;
// }
// std::cout << std::endl;
}
printf("CPU time : %.3f ms\n", CPUtime);
}
bool checkShodimost() {
return true;
}
int main(void)
{
static const int WORK_SIZE = 256000;
float *data = new float[WORK_SIZE];
model(5);
/* Free memory */
delete[] data;
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, cudaError_t err)
{
if (err == cudaSuccess)
return;
std::cerr << statement<<" returned " << cudaGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} | /*
============================================================================
Name : LAB3.cu
Author : Kineibe
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <string>
#include <fstream>
#include <sstream>
using namespace std;
static void CheckCudaErrorAux (const char *, unsigned, const char *, hipError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
#define H_T 0.0001
#define H_X 0.5
#define TOTAL_TIME 10
#define EPSILON 0.001
#define RIGHT_COND 1
#define LEFT_COND 0
#define BLOCK_SIZE_AMOUNT 256
const double A = H_T / (H_X * H_X);
const double B = 2 * A + 1;
double countSum(int k, double* t, int size) {
if (k == 0) {
return t[k] * 1;
} else if (k == size - 1) {
return -1 * t[k - 1] / H_X + t[k] / H_X;
} else {
return -1 * A * t[k - 1] + t[k] / B - A * t[k + 1];
}
}
double iterationPart(double prev, double multiplier, double f, double sum) {
return prev + (f - sum) / multiplier;
}
void iteration(double* t_prev, int size, double* f, double* t_result) {
for (int i = 0; i < size; ++i) {
double a;
if (i == 0)
a = 1;
else if (i == size - 1)
a = 1 / H_X;
else
a = B;
double sum = countSum(i, t_prev, size);
double newT = iterationPart(t_prev[i], a, f[i], sum);
t_result[i] = newT;
}
}
bool condition(double* t_prev, double* t_result, int size) {
double result = 0;
for (int i = 0; i < size; ++i) {
result += abs(t_prev[i] - t_result[i]);
}
return result < EPSILON;
}
void iterationManager(double* t_prev, int size, double* f, double* t_target) {
bool check = true;
double* t_result = new double[size];
do {
iteration(t_prev, size, f, t_result);
check = condition(t_prev, t_result, size);
double* temp = t_result;
t_result = t_prev;
t_prev = temp;
} while(!check);
for (int i = 0; i < size; ++i) {
t_target[i] = t_prev[i];
}
delete[] t_result;
}
void printMas(double* arr, int size) {
for (int i = 0; i < size; ++i) {
cout << arr[i] << ' ';
}
cout << endl;
}
void model(int size) {
double* t = new double[size];
for (int i = 0; i < size; ++i) {
t[i] = 0;
}
double* t_next = new double[size];
double* f = new double[size];
f[0] = LEFT_COND;
f[size - 1] = RIGHT_COND;
// int iterationAmount = TOTAL_TIME / H_T;
int iterationAmount = 10;
for (int i = 0; i < iterationAmount; ++i) {
cout << "Iteration num " << i << endl;
for (int i = 1; i < size - 1; ++i) {
f[i] = t[i];
}
cout << "F array" << endl;
printMas(f, size);
iterationManager(t, size, f, t_next);
printMas(t_next, size);
double* temp = t_next;
t_next = t;
t = temp;
}
delete[] t_next;
delete[] f;
delete[] t;
}
/**
* CUDA kernel that computes reciprocal values for a given vector
*/
__global__ void reciprocalKernel(float *data, float *newData, unsigned vectorSize) {
unsigned idx = blockIdx.x*blockDim.x+threadIdx.x;
if (idx < vectorSize) {
if (idx == vectorSize - 1) {
newData[idx] = RIGHT_COND * H_T + data[idx];
} else if (idx == 0) {
newData[idx] = LEFT_COND;
} else {
newData[idx] = data[idx] + (data[idx - 1] - 2 * data[idx] + data[idx + 1]) * H_T / (H_X * H_X);
}
}
}
/**
* Host function that copies the data and launches the work on GPU
*/
void gpuReciprocal(float *data, unsigned size)
{
hipEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
float *rc = new float[size];
float *gpuOldData;
float *gpuNewData;
int iterationAmount = TOTAL_TIME / H_T;
static const int BLOCK_SIZE = BLOCK_SIZE_AMOUNT;
const int blockCount = 1000;
CUDA_CHECK_RETURN(hipMalloc((void **)&gpuOldData, sizeof(float)*size));
CUDA_CHECK_RETURN(hipMalloc((void **)&gpuNewData, sizeof(float)*size));
CUDA_CHECK_RETURN(hipMemcpy(gpuOldData, data, sizeof(float)*size, hipMemcpyHostToDevice));
hipEventCreate(&GPUstart);
hipEventCreate(&GPUstop);
for (int i = 0; i < iterationAmount; ++i) {
hipEventRecord(GPUstart, 0);
if (i % 2 == 0) {
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuOldData, gpuNewData, size);
hipEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(hipMemcpy(rc, gpuNewData, sizeof(float)*size, hipMemcpyDeviceToHost));
} else {
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuNewData, gpuOldData, size);
hipEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(hipMemcpy(rc, gpuOldData, sizeof(float)*size, hipMemcpyDeviceToHost));
}
hipEventSynchronize(GPUstop);
float temp;
hipEventElapsedTime(&temp, GPUstart, GPUstop);
GPUtime += temp;
//
// for (int i = 0; i < size; ++i) {
// std::cout << "t[" << i << "] = " << rc[i] << std::endl;
// }
// std::cout << std::endl;
}
printf("GPU time : %.3f ms\n", GPUtime);
CUDA_CHECK_RETURN(hipFree(gpuOldData));
CUDA_CHECK_RETURN(hipFree(gpuNewData));
}
void initialize(float *data, unsigned size)
{
for (unsigned i = 0; i < size; ++i)
data[i] = 0;
}
void cpuIteration(float *data, float *newData, unsigned vectorSize) {
for (int idx = 0; idx < vectorSize; ++idx) {
if (idx == vectorSize - 1) {
newData[idx] = RIGHT_COND * H_T + data[idx];
} else if (idx == 0) {
newData[idx] = LEFT_COND;
} else {
newData[idx] = data[idx] + (data[idx - 1] - 2 * data[idx] + data[idx + 1]) * H_T / (H_X * H_X);
}
}
}
void cpuReciprocal(float *data, unsigned size)
{
float *rc = new float[size];
float *oldData = new float[size];
float* result;
float CPUstart, CPUstop;
float CPUtime = 0.0f;
int iterationAmount = TOTAL_TIME / H_T;
for (int i = 0; i < iterationAmount; ++i) {
CPUstart = clock();
if (i % 2 == 0) {
cpuIteration(oldData, rc, size);
result = rc;
} else {
cpuIteration(rc, oldData, size);
result = oldData;
}
CPUstop = clock();
CPUtime += 1000.*(CPUstop - CPUstart) / CLOCKS_PER_SEC;
//
// for (int i = 0; i < size; ++i) {
// std::cout << "t[" << i << "] = " << result[i] << std::endl;
// }
// std::cout << std::endl;
}
printf("CPU time : %.3f ms\n", CPUtime);
}
bool checkShodimost() {
return true;
}
int main(void)
{
static const int WORK_SIZE = 256000;
float *data = new float[WORK_SIZE];
model(5);
/* Free memory */
delete[] data;
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err)
{
if (err == hipSuccess)
return;
std::cerr << statement<<" returned " << hipGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
============================================================================
Name : LAB3.cu
Author : Kineibe
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <string>
#include <fstream>
#include <sstream>
using namespace std;
static void CheckCudaErrorAux (const char *, unsigned, const char *, hipError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
#define H_T 0.0001
#define H_X 0.5
#define TOTAL_TIME 10
#define EPSILON 0.001
#define RIGHT_COND 1
#define LEFT_COND 0
#define BLOCK_SIZE_AMOUNT 256
const double A = H_T / (H_X * H_X);
const double B = 2 * A + 1;
double countSum(int k, double* t, int size) {
if (k == 0) {
return t[k] * 1;
} else if (k == size - 1) {
return -1 * t[k - 1] / H_X + t[k] / H_X;
} else {
return -1 * A * t[k - 1] + t[k] / B - A * t[k + 1];
}
}
double iterationPart(double prev, double multiplier, double f, double sum) {
return prev + (f - sum) / multiplier;
}
void iteration(double* t_prev, int size, double* f, double* t_result) {
for (int i = 0; i < size; ++i) {
double a;
if (i == 0)
a = 1;
else if (i == size - 1)
a = 1 / H_X;
else
a = B;
double sum = countSum(i, t_prev, size);
double newT = iterationPart(t_prev[i], a, f[i], sum);
t_result[i] = newT;
}
}
bool condition(double* t_prev, double* t_result, int size) {
double result = 0;
for (int i = 0; i < size; ++i) {
result += abs(t_prev[i] - t_result[i]);
}
return result < EPSILON;
}
void iterationManager(double* t_prev, int size, double* f, double* t_target) {
bool check = true;
double* t_result = new double[size];
do {
iteration(t_prev, size, f, t_result);
check = condition(t_prev, t_result, size);
double* temp = t_result;
t_result = t_prev;
t_prev = temp;
} while(!check);
for (int i = 0; i < size; ++i) {
t_target[i] = t_prev[i];
}
delete[] t_result;
}
void printMas(double* arr, int size) {
for (int i = 0; i < size; ++i) {
cout << arr[i] << ' ';
}
cout << endl;
}
void model(int size) {
double* t = new double[size];
for (int i = 0; i < size; ++i) {
t[i] = 0;
}
double* t_next = new double[size];
double* f = new double[size];
f[0] = LEFT_COND;
f[size - 1] = RIGHT_COND;
// int iterationAmount = TOTAL_TIME / H_T;
int iterationAmount = 10;
for (int i = 0; i < iterationAmount; ++i) {
cout << "Iteration num " << i << endl;
for (int i = 1; i < size - 1; ++i) {
f[i] = t[i];
}
cout << "F array" << endl;
printMas(f, size);
iterationManager(t, size, f, t_next);
printMas(t_next, size);
double* temp = t_next;
t_next = t;
t = temp;
}
delete[] t_next;
delete[] f;
delete[] t;
}
/**
* CUDA kernel that computes reciprocal values for a given vector
*/
__global__ void reciprocalKernel(float *data, float *newData, unsigned vectorSize) {
unsigned idx = blockIdx.x*blockDim.x+threadIdx.x;
if (idx < vectorSize) {
if (idx == vectorSize - 1) {
newData[idx] = RIGHT_COND * H_T + data[idx];
} else if (idx == 0) {
newData[idx] = LEFT_COND;
} else {
newData[idx] = data[idx] + (data[idx - 1] - 2 * data[idx] + data[idx + 1]) * H_T / (H_X * H_X);
}
}
}
/**
* Host function that copies the data and launches the work on GPU
*/
void gpuReciprocal(float *data, unsigned size)
{
hipEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
float *rc = new float[size];
float *gpuOldData;
float *gpuNewData;
int iterationAmount = TOTAL_TIME / H_T;
static const int BLOCK_SIZE = BLOCK_SIZE_AMOUNT;
const int blockCount = 1000;
CUDA_CHECK_RETURN(hipMalloc((void **)&gpuOldData, sizeof(float)*size));
CUDA_CHECK_RETURN(hipMalloc((void **)&gpuNewData, sizeof(float)*size));
CUDA_CHECK_RETURN(hipMemcpy(gpuOldData, data, sizeof(float)*size, hipMemcpyHostToDevice));
hipEventCreate(&GPUstart);
hipEventCreate(&GPUstop);
for (int i = 0; i < iterationAmount; ++i) {
hipEventRecord(GPUstart, 0);
if (i % 2 == 0) {
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuOldData, gpuNewData, size);
hipEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(hipMemcpy(rc, gpuNewData, sizeof(float)*size, hipMemcpyDeviceToHost));
} else {
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuNewData, gpuOldData, size);
hipEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(hipMemcpy(rc, gpuOldData, sizeof(float)*size, hipMemcpyDeviceToHost));
}
hipEventSynchronize(GPUstop);
float temp;
hipEventElapsedTime(&temp, GPUstart, GPUstop);
GPUtime += temp;
//
// for (int i = 0; i < size; ++i) {
// std::cout << "t[" << i << "] = " << rc[i] << std::endl;
// }
// std::cout << std::endl;
}
printf("GPU time : %.3f ms\n", GPUtime);
CUDA_CHECK_RETURN(hipFree(gpuOldData));
CUDA_CHECK_RETURN(hipFree(gpuNewData));
}
void initialize(float *data, unsigned size)
{
for (unsigned i = 0; i < size; ++i)
data[i] = 0;
}
void cpuIteration(float *data, float *newData, unsigned vectorSize) {
for (int idx = 0; idx < vectorSize; ++idx) {
if (idx == vectorSize - 1) {
newData[idx] = RIGHT_COND * H_T + data[idx];
} else if (idx == 0) {
newData[idx] = LEFT_COND;
} else {
newData[idx] = data[idx] + (data[idx - 1] - 2 * data[idx] + data[idx + 1]) * H_T / (H_X * H_X);
}
}
}
void cpuReciprocal(float *data, unsigned size)
{
float *rc = new float[size];
float *oldData = new float[size];
float* result;
float CPUstart, CPUstop;
float CPUtime = 0.0f;
int iterationAmount = TOTAL_TIME / H_T;
for (int i = 0; i < iterationAmount; ++i) {
CPUstart = clock();
if (i % 2 == 0) {
cpuIteration(oldData, rc, size);
result = rc;
} else {
cpuIteration(rc, oldData, size);
result = oldData;
}
CPUstop = clock();
CPUtime += 1000.*(CPUstop - CPUstart) / CLOCKS_PER_SEC;
//
// for (int i = 0; i < size; ++i) {
// std::cout << "t[" << i << "] = " << result[i] << std::endl;
// }
// std::cout << std::endl;
}
printf("CPU time : %.3f ms\n", CPUtime);
}
bool checkShodimost() {
return true;
}
int main(void)
{
static const int WORK_SIZE = 256000;
float *data = new float[WORK_SIZE];
model(5);
/* Free memory */
delete[] data;
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err)
{
if (err == hipSuccess)
return;
std::cerr << statement<<" returned " << hipGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16reciprocalKernelPfS_j
.globl _Z16reciprocalKernelPfS_j
.p2align 8
.type _Z16reciprocalKernelPfS_j,@function
_Z16reciprocalKernelPfS_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_9
s_load_b128 s[0:3], s[0:1], 0x0
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_7
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, -1, v1
s_mov_b32 s7, 0x3f1a36e2
s_mov_b32 s6, 0xeb1c432d
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mov_b32_e32 v4, v2
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_nc_u32_e32 v1, 1, v1
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x2
global_load_b32 v4, v[7:8], off
global_load_b32 v2, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v2, -2.0, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v0, v2, v0
v_cvt_f64_f32_e32 v[2:3], v4
v_cvt_f64_f32_e32 v[0:1], v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], s[6:7]
v_fma_f64 v[0:1], v[0:1], 4.0, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v6, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v0, s[2:3]
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_7:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0x3f1a36e2
s_mov_b32 s0, 0xeb1c432d
v_add_co_u32 v0, vcc_lo, s2, v0
global_load_b32 v2, v[2:3], off
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], s[0:1]
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16reciprocalKernelPfS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16reciprocalKernelPfS_j, .Lfunc_end0-_Z16reciprocalKernelPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16reciprocalKernelPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16reciprocalKernelPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
============================================================================
Name : LAB3.cu
Author : Kineibe
Version :
Copyright : Your copyright notice
Description : CUDA compute reciprocals
============================================================================
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
#include <string>
#include <fstream>
#include <sstream>
using namespace std;
static void CheckCudaErrorAux (const char *, unsigned, const char *, hipError_t);
#define CUDA_CHECK_RETURN(value) CheckCudaErrorAux(__FILE__,__LINE__, #value, value)
#define H_T 0.0001
#define H_X 0.5
#define TOTAL_TIME 10
#define EPSILON 0.001
#define RIGHT_COND 1
#define LEFT_COND 0
#define BLOCK_SIZE_AMOUNT 256
const double A = H_T / (H_X * H_X);
const double B = 2 * A + 1;
double countSum(int k, double* t, int size) {
if (k == 0) {
return t[k] * 1;
} else if (k == size - 1) {
return -1 * t[k - 1] / H_X + t[k] / H_X;
} else {
return -1 * A * t[k - 1] + t[k] / B - A * t[k + 1];
}
}
double iterationPart(double prev, double multiplier, double f, double sum) {
return prev + (f - sum) / multiplier;
}
void iteration(double* t_prev, int size, double* f, double* t_result) {
for (int i = 0; i < size; ++i) {
double a;
if (i == 0)
a = 1;
else if (i == size - 1)
a = 1 / H_X;
else
a = B;
double sum = countSum(i, t_prev, size);
double newT = iterationPart(t_prev[i], a, f[i], sum);
t_result[i] = newT;
}
}
bool condition(double* t_prev, double* t_result, int size) {
double result = 0;
for (int i = 0; i < size; ++i) {
result += abs(t_prev[i] - t_result[i]);
}
return result < EPSILON;
}
void iterationManager(double* t_prev, int size, double* f, double* t_target) {
bool check = true;
double* t_result = new double[size];
do {
iteration(t_prev, size, f, t_result);
check = condition(t_prev, t_result, size);
double* temp = t_result;
t_result = t_prev;
t_prev = temp;
} while(!check);
for (int i = 0; i < size; ++i) {
t_target[i] = t_prev[i];
}
delete[] t_result;
}
void printMas(double* arr, int size) {
for (int i = 0; i < size; ++i) {
cout << arr[i] << ' ';
}
cout << endl;
}
void model(int size) {
double* t = new double[size];
for (int i = 0; i < size; ++i) {
t[i] = 0;
}
double* t_next = new double[size];
double* f = new double[size];
f[0] = LEFT_COND;
f[size - 1] = RIGHT_COND;
// int iterationAmount = TOTAL_TIME / H_T;
int iterationAmount = 10;
for (int i = 0; i < iterationAmount; ++i) {
cout << "Iteration num " << i << endl;
for (int i = 1; i < size - 1; ++i) {
f[i] = t[i];
}
cout << "F array" << endl;
printMas(f, size);
iterationManager(t, size, f, t_next);
printMas(t_next, size);
double* temp = t_next;
t_next = t;
t = temp;
}
delete[] t_next;
delete[] f;
delete[] t;
}
/**
* CUDA kernel that computes reciprocal values for a given vector
*/
__global__ void reciprocalKernel(float *data, float *newData, unsigned vectorSize) {
unsigned idx = blockIdx.x*blockDim.x+threadIdx.x;
if (idx < vectorSize) {
if (idx == vectorSize - 1) {
newData[idx] = RIGHT_COND * H_T + data[idx];
} else if (idx == 0) {
newData[idx] = LEFT_COND;
} else {
newData[idx] = data[idx] + (data[idx - 1] - 2 * data[idx] + data[idx + 1]) * H_T / (H_X * H_X);
}
}
}
/**
* Host function that copies the data and launches the work on GPU
*/
void gpuReciprocal(float *data, unsigned size)
{
hipEvent_t GPUstart, GPUstop;
float GPUtime = 0.0f;
float *rc = new float[size];
float *gpuOldData;
float *gpuNewData;
int iterationAmount = TOTAL_TIME / H_T;
static const int BLOCK_SIZE = BLOCK_SIZE_AMOUNT;
const int blockCount = 1000;
CUDA_CHECK_RETURN(hipMalloc((void **)&gpuOldData, sizeof(float)*size));
CUDA_CHECK_RETURN(hipMalloc((void **)&gpuNewData, sizeof(float)*size));
CUDA_CHECK_RETURN(hipMemcpy(gpuOldData, data, sizeof(float)*size, hipMemcpyHostToDevice));
hipEventCreate(&GPUstart);
hipEventCreate(&GPUstop);
for (int i = 0; i < iterationAmount; ++i) {
hipEventRecord(GPUstart, 0);
if (i % 2 == 0) {
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuOldData, gpuNewData, size);
hipEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(hipMemcpy(rc, gpuNewData, sizeof(float)*size, hipMemcpyDeviceToHost));
} else {
reciprocalKernel<<<blockCount, BLOCK_SIZE>>> (gpuNewData, gpuOldData, size);
hipEventRecord(GPUstop, 0);
CUDA_CHECK_RETURN(hipMemcpy(rc, gpuOldData, sizeof(float)*size, hipMemcpyDeviceToHost));
}
hipEventSynchronize(GPUstop);
float temp;
hipEventElapsedTime(&temp, GPUstart, GPUstop);
GPUtime += temp;
//
// for (int i = 0; i < size; ++i) {
// std::cout << "t[" << i << "] = " << rc[i] << std::endl;
// }
// std::cout << std::endl;
}
printf("GPU time : %.3f ms\n", GPUtime);
CUDA_CHECK_RETURN(hipFree(gpuOldData));
CUDA_CHECK_RETURN(hipFree(gpuNewData));
}
void initialize(float *data, unsigned size)
{
for (unsigned i = 0; i < size; ++i)
data[i] = 0;
}
void cpuIteration(float *data, float *newData, unsigned vectorSize) {
for (int idx = 0; idx < vectorSize; ++idx) {
if (idx == vectorSize - 1) {
newData[idx] = RIGHT_COND * H_T + data[idx];
} else if (idx == 0) {
newData[idx] = LEFT_COND;
} else {
newData[idx] = data[idx] + (data[idx - 1] - 2 * data[idx] + data[idx + 1]) * H_T / (H_X * H_X);
}
}
}
void cpuReciprocal(float *data, unsigned size)
{
float *rc = new float[size];
float *oldData = new float[size];
float* result;
float CPUstart, CPUstop;
float CPUtime = 0.0f;
int iterationAmount = TOTAL_TIME / H_T;
for (int i = 0; i < iterationAmount; ++i) {
CPUstart = clock();
if (i % 2 == 0) {
cpuIteration(oldData, rc, size);
result = rc;
} else {
cpuIteration(rc, oldData, size);
result = oldData;
}
CPUstop = clock();
CPUtime += 1000.*(CPUstop - CPUstart) / CLOCKS_PER_SEC;
//
// for (int i = 0; i < size; ++i) {
// std::cout << "t[" << i << "] = " << result[i] << std::endl;
// }
// std::cout << std::endl;
}
printf("CPU time : %.3f ms\n", CPUtime);
}
bool checkShodimost() {
return true;
}
int main(void)
{
static const int WORK_SIZE = 256000;
float *data = new float[WORK_SIZE];
model(5);
/* Free memory */
delete[] data;
return 0;
}
/**
* Check the return value of the CUDA runtime API call and exit
* the application if the call has failed.
*/
static void CheckCudaErrorAux (const char *file, unsigned line, const char *statement, hipError_t err)
{
if (err == hipSuccess)
return;
std::cerr << statement<<" returned " << hipGetErrorString(err) << "("<<err<< ") at "<<file<<":"<<line << std::endl;
exit (1);
} | .text
.file "LAB2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8countSumiPdi
.LCPI0_0:
.quad 0x3f3a36e2eb1c432d # double 4.0000000000000002E-4
.LCPI0_1:
.quad 0x3ff00346dc5d6388 # double 1.0007999999999999
.text
.globl _Z8countSumiPdi
.p2align 4, 0x90
.type _Z8countSumiPdi,@function
_Z8countSumiPdi: # @_Z8countSumiPdi
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB0_1
# %bb.2:
decl %edx
movslq %edi, %rax
movsd -8(%rsi,%rax,8), %xmm1 # xmm1 = mem[0],zero
movsd (%rsi,%rax,8), %xmm0 # xmm0 = mem[0],zero
cmpl %edi, %edx
jne .LBB0_5
# %bb.3:
addsd %xmm1, %xmm1
addsd %xmm0, %xmm0
subsd %xmm1, %xmm0
retq
.LBB0_1:
movsd (%rsi), %xmm0 # xmm0 = mem[0],zero
retq
.LBB0_5:
movsd .LCPI0_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
divsd .LCPI0_1(%rip), %xmm0
subsd %xmm1, %xmm0
mulsd 8(%rsi,%rax,8), %xmm2
subsd %xmm2, %xmm0
retq
.Lfunc_end0:
.size _Z8countSumiPdi, .Lfunc_end0-_Z8countSumiPdi
.cfi_endproc
# -- End function
.globl _Z13iterationPartdddd # -- Begin function _Z13iterationPartdddd
.p2align 4, 0x90
.type _Z13iterationPartdddd,@function
_Z13iterationPartdddd: # @_Z13iterationPartdddd
.cfi_startproc
# %bb.0:
subsd %xmm3, %xmm2
divsd %xmm1, %xmm2
addsd %xmm2, %xmm0
retq
.Lfunc_end1:
.size _Z13iterationPartdddd, .Lfunc_end1-_Z13iterationPartdddd
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 3, 0x0 # -- Begin function _Z9iterationPdiS_S_
.LCPI2_0:
.quad 0x3ff00346dc5d6388 # double 1.0007999999999999
.quad 0x4000000000000000 # double 2
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x3ff0000000000000 # double 1
.LCPI2_2:
.quad 0x3f3a36e2eb1c432d # double 4.0000000000000002E-4
.LCPI2_3:
.quad 0x3ff00346dc5d6388 # double 1.0007999999999999
.text
.globl _Z9iterationPdiS_S_
.p2align 4, 0x90
.type _Z9iterationPdiS_S_,@function
_Z9iterationPdiS_S_: # @_Z9iterationPdiS_S_
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
testl %esi, %esi
jle .LBB2_11
# %bb.1: # %.lr.ph
leal -1(%rsi), %eax
movl %esi, %esi
shlq $3, %rax
shlq $3, %rsi
xorl %r8d, %r8d
movsd .LCPI2_1(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI2_2(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI2_3(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_2 Depth=1
movsd (%rdi), %xmm4 # xmm4 = mem[0],zero
.LBB2_10: # %_Z8countSumiPdi.exit
# in Loop: Header=BB2_2 Depth=1
movsd (%rdx,%r8), %xmm5 # xmm5 = mem[0],zero
subsd %xmm4, %xmm5
divsd %xmm3, %xmm5
addsd (%rdi,%r8), %xmm5
movsd %xmm5, (%rcx,%r8)
addq $8, %r8
cmpq %r8, %rsi
je .LBB2_11
.LBB2_2: # =>This Inner Loop Header: Depth=1
xorl %r9d, %r9d
cmpq %r8, %rax
sete %r10b
movapd %xmm0, %xmm3
testq %r8, %r8
je .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movb %r10b, %r9b
movsd .LCPI2_0(,%r9,8), %xmm3 # xmm3 = mem[0],zero
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
je .LBB2_5
# %bb.6: # in Loop: Header=BB2_2 Depth=1
movsd -8(%rdi,%r8), %xmm5 # xmm5 = mem[0],zero
movsd (%rdi,%r8), %xmm4 # xmm4 = mem[0],zero
cmpq %r8, %rax
jne .LBB2_8
# %bb.7: # in Loop: Header=BB2_2 Depth=1
addsd %xmm5, %xmm5
addsd %xmm4, %xmm4
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_8: # in Loop: Header=BB2_2 Depth=1
mulsd %xmm1, %xmm5
divsd %xmm2, %xmm4
subsd %xmm5, %xmm4
movsd 8(%rdi,%r8), %xmm5 # xmm5 = mem[0],zero
mulsd %xmm1, %xmm5
.LBB2_9: # %_Z8countSumiPdi.exit
# in Loop: Header=BB2_2 Depth=1
subsd %xmm5, %xmm4
jmp .LBB2_10
.LBB2_11: # %._crit_edge
retq
.Lfunc_end2:
.size _Z9iterationPdiS_S_, .Lfunc_end2-_Z9iterationPdiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z9conditionPdS_i
.LCPI3_0:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.text
.globl _Z9conditionPdS_i
.p2align 4, 0x90
.type _Z9conditionPdS_i,@function
_Z9conditionPdS_i: # @_Z9conditionPdS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB3_1
# %bb.4: # %.lr.ph.preheader
movl %edx, %eax
xorpd %xmm0, %xmm0
xorl %ecx, %ecx
movapd .LCPI3_0(%rip), %xmm1 # xmm1 = [NaN,NaN]
.p2align 4, 0x90
.LBB3_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%rcx,8), %xmm2 # xmm2 = mem[0],zero
subsd (%rsi,%rcx,8), %xmm2
andpd %xmm1, %xmm2
addsd %xmm2, %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB3_5
# %bb.2: # %._crit_edge.loopexit
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
seta %al
retq
.LBB3_1:
movb $1, %al
retq
.Lfunc_end3:
.size _Z9conditionPdS_i, .Lfunc_end3-_Z9conditionPdS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z16iterationManagerPdiS_S_
.LCPI4_0:
.quad 0x3ff00346dc5d6388 # double 1.0007999999999999
.quad 0x4000000000000000 # double 2
.LCPI4_4:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3ff0000000000000 # double 1
.LCPI4_2:
.quad 0x3f3a36e2eb1c432d # double 4.0000000000000002E-4
.LCPI4_3:
.quad 0x3ff00346dc5d6388 # double 1.0007999999999999
.LCPI4_5:
.quad 0x3f50624dd2f1a9fc # double 0.001
.text
.globl _Z16iterationManagerPdiS_S_
.p2align 4, 0x90
.type _Z16iterationManagerPdiS_S_,@function
_Z16iterationManagerPdiS_S_: # @_Z16iterationManagerPdiS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r15
movl %esi, %ebp
movq %rdi, %r14
movslq %esi, %r12
leaq (,%r12,8), %rax
testl %r12d, %r12d
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
leal -1(%r12), %esi
movl %r12d, %ecx
leaq (,%rcx,8), %r8
shlq $3, %rsi
movsd .LCPI4_1(%rip), %xmm0 # xmm0 = mem[0],zero
movapd .LCPI4_4(%rip), %xmm1 # xmm1 = [NaN,NaN]
movsd .LCPI4_5(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI4_2(%rip), %xmm3 # xmm3 = mem[0],zero
movsd .LCPI4_3(%rip), %xmm4 # xmm4 = mem[0],zero
movq %rax, %r9
movq %r14, %rdx
.p2align 4, 0x90
.LBB4_1: # =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
# Child Loop BB4_15 Depth 2
testl %ebp, %ebp
jle .LBB4_2
# %bb.3: # %.lr.ph.i.preheader
# in Loop: Header=BB4_1 Depth=1
movq %rdx, %rdi
movq %r9, %rdx
xorl %r9d, %r9d
jmp .LBB4_4
.p2align 4, 0x90
.LBB4_7: # in Loop: Header=BB4_4 Depth=2
movsd (%rdi), %xmm6 # xmm6 = mem[0],zero
.LBB4_12: # %_Z8countSumiPdi.exit.i
# in Loop: Header=BB4_4 Depth=2
movsd (%r15,%r9), %xmm7 # xmm7 = mem[0],zero
subsd %xmm6, %xmm7
divsd %xmm5, %xmm7
addsd (%rdi,%r9), %xmm7
movsd %xmm7, (%rdx,%r9)
addq $8, %r9
cmpq %r9, %r8
je .LBB4_13
.LBB4_4: # %.lr.ph.i
# Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
xorl %r10d, %r10d
cmpq %r9, %rsi
sete %r11b
movapd %xmm0, %xmm5
testq %r9, %r9
je .LBB4_6
# %bb.5: # %.lr.ph.i
# in Loop: Header=BB4_4 Depth=2
movb %r11b, %r10b
movsd .LCPI4_0(,%r10,8), %xmm5 # xmm5 = mem[0],zero
.LBB4_6: # %.lr.ph.i
# in Loop: Header=BB4_4 Depth=2
je .LBB4_7
# %bb.8: # in Loop: Header=BB4_4 Depth=2
movsd -8(%rdi,%r9), %xmm7 # xmm7 = mem[0],zero
movsd (%rdi,%r9), %xmm6 # xmm6 = mem[0],zero
cmpq %r9, %rsi
jne .LBB4_10
# %bb.9: # in Loop: Header=BB4_4 Depth=2
addsd %xmm7, %xmm7
addsd %xmm6, %xmm6
jmp .LBB4_11
.p2align 4, 0x90
.LBB4_10: # in Loop: Header=BB4_4 Depth=2
mulsd %xmm3, %xmm7
divsd %xmm4, %xmm6
subsd %xmm7, %xmm6
movsd 8(%rdi,%r9), %xmm7 # xmm7 = mem[0],zero
mulsd %xmm3, %xmm7
.LBB4_11: # %_Z8countSumiPdi.exit.i
# in Loop: Header=BB4_4 Depth=2
subsd %xmm7, %xmm6
jmp .LBB4_12
.p2align 4, 0x90
.LBB4_13: # %_Z9iterationPdiS_S_.exit
# in Loop: Header=BB4_1 Depth=1
testl %ebp, %ebp
jle .LBB4_2
# %bb.14: # %.lr.ph.i22.preheader
# in Loop: Header=BB4_1 Depth=1
xorpd %xmm5, %xmm5
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB4_15: # %.lr.ph.i22
# Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rdi,%r9,8), %xmm6 # xmm6 = mem[0],zero
subsd (%rdx,%r9,8), %xmm6
andpd %xmm1, %xmm6
addsd %xmm6, %xmm5
incq %r9
cmpq %r9, %rcx
jne .LBB4_15
# %bb.16: # %._crit_edge.loopexit.i
# in Loop: Header=BB4_1 Depth=1
ucomisd %xmm5, %xmm2
movq %rdi, %r9
jbe .LBB4_1
# %bb.17: # %.preheader
testl %ebp, %ebp
jg .LBB4_18
jmp .LBB4_20
.LBB4_2:
movq %rax, %rdx
movq %r14, %rdi
testl %ebp, %ebp
jle .LBB4_20
.LBB4_18: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_19: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rdx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rbx,%rax,8)
incq %rax
cmpq %rax, %rcx
jne .LBB4_19
.LBB4_20: # %._crit_edge
testq %rdi, %rdi
je .LBB4_21
# %bb.22:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZdaPv # TAILCALL
.LBB4_21:
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z16iterationManagerPdiS_S_, .Lfunc_end4-_Z16iterationManagerPdiS_S_
.cfi_endproc
# -- End function
.globl _Z8printMasPdi # -- Begin function _Z8printMasPdi
.p2align 4, 0x90
.type _Z8printMasPdi,@function
_Z8printMasPdi: # @_Z8printMasPdi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %esi, %esi
jle .LBB5_4
# %bb.1: # %.lr.ph.preheader
movq %rdi, %rbx
movl %esi, %r15d
xorl %r12d, %r12d
leaq 7(%rsp), %r14
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_9: # in Loop: Header=BB5_2 Depth=1
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB5_10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB5_2 Depth=1
incq %r12
cmpq %r12, %r15
je .LBB5_4
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $32, 7(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB5_9
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB5_10
.LBB5_4: # %._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_11
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB5_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB5_8
.LBB5_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB5_11:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size _Z8printMasPdi, .Lfunc_end5-_Z8printMasPdi
.cfi_endproc
# -- End function
.globl _Z5modeli # -- Begin function _Z5modeli
.p2align 4, 0x90
.type _Z5modeli,@function
_Z5modeli: # @_Z5modeli
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movslq %edi, %r12
leaq (,%r12,8), %rax
testl %r12d, %r12d
movq $-1, %r14
cmovnsq %rax, %r14
movq %r14, %rdi
callq _Znam
movq %rax, %r13
testl %r12d, %r12d
jle .LBB6_2
# %bb.1: # %.lr.ph.preheader
movl %ebx, %edx
shlq $3, %rdx
movq %r13, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB6_2: # %._crit_edge
movq %r14, %rdi
callq _Znam
movq %rax, %r15
movq %r14, %rdi
callq _Znam
movq %rax, %r14
movq $0, (%rax)
movq %rbx, 8(%rsp) # 8-byte Spill
decl %ebx
movabsq $4607182418800017408, %rax # imm = 0x3FF0000000000000
movq %rax, -8(%r14,%r12,8)
xorl %ebp, %ebp
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_13: # in Loop: Header=BB6_3 Depth=1
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB6_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit44
# in Loop: Header=BB6_3 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r14, %rdi
movq 8(%rsp), %r13 # 8-byte Reload
movl %r13d, %esi
callq _Z8printMasPdi
movq %r15, %rdi
movl %r13d, %esi
movq %r14, %rdx
movq %r12, %rcx
callq _Z16iterationManagerPdiS_S_
movq %r12, %rdi
movl %r13d, %esi
callq _Z8printMasPdi
incl %ebp
movq %r12, %r13
cmpl $10, %ebp
je .LBB6_15
.LBB6_3: # =>This Loop Header: Depth=1
# Child Loop BB6_9 Depth 2
movq %r15, %r12
movq %r13, %r15
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB6_19
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB6_3 Depth=1
cmpb $0, 56(%r13)
je .LBB6_6
# %bb.5: # in Loop: Header=BB6_3 Depth=1
movzbl 67(%r13), %ecx
jmp .LBB6_7
.p2align 4, 0x90
.LBB6_6: # in Loop: Header=BB6_3 Depth=1
movq %r13, %rdi
movq %rax, 16(%rsp) # 8-byte Spill
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq 16(%rsp), %rax # 8-byte Reload
.LBB6_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB6_3 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $3, 8(%rsp) # 4-byte Folded Reload
jl .LBB6_10
# %bb.8: # %.lr.ph51.preheader
# in Loop: Header=BB6_3 Depth=1
movl $1, %eax
.p2align 4, 0x90
.LBB6_9: # %.lr.ph51
# Parent Loop BB6_3 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r14,%rax,8)
incq %rax
cmpq %rax, %rbx
jne .LBB6_9
.LBB6_10: # %._crit_edge52
# in Loop: Header=BB6_3 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB6_19
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i41
# in Loop: Header=BB6_3 Depth=1
cmpb $0, 56(%r13)
je .LBB6_13
# %bb.12: # in Loop: Header=BB6_3 Depth=1
movzbl 67(%r13), %eax
jmp .LBB6_14
.LBB6_15:
testq %r15, %r15
je .LBB6_17
# %bb.16:
movq %r15, %rdi
callq _ZdaPv
.LBB6_17:
movq %r14, %rdi
callq _ZdaPv
testq %r12, %r12
je .LBB6_18
# %bb.20:
movq %r12, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZdaPv # TAILCALL
.LBB6_18:
.cfi_def_cfa_offset 80
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_19:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end6:
.size _Z5modeli, .Lfunc_end6-_Z5modeli
.cfi_endproc
# -- End function
.globl _Z31__device_stub__reciprocalKernelPfS_j # -- Begin function _Z31__device_stub__reciprocalKernelPfS_j
.p2align 4, 0x90
.type _Z31__device_stub__reciprocalKernelPfS_j,@function
_Z31__device_stub__reciprocalKernelPfS_j: # @_Z31__device_stub__reciprocalKernelPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16reciprocalKernelPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end7:
.size _Z31__device_stub__reciprocalKernelPfS_j, .Lfunc_end7-_Z31__device_stub__reciprocalKernelPfS_j
.cfi_endproc
# -- End function
.globl _Z13gpuReciprocalPfj # -- Begin function _Z13gpuReciprocalPfj
.p2align 4, 0x90
.type _Z13gpuReciprocalPfj,@function
_Z13gpuReciprocalPfj: # @_Z13gpuReciprocalPfj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %r13
movabsq $4294967552, %r14 # imm = 0x100000100
movl %esi, 28(%rsp) # 4-byte Spill
movl %esi, %r15d
shlq $2, %r15
movq %r15, %rdi
callq _Znam
movq %rax, %r12
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movl $.L.str.3, %esi
movl $166, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movl $.L.str.4, %esi
movl $167, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str.5, %esi
movl $168, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
leaq 120(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
xorl %ebx, %ebx
xorps %xmm0, %xmm0
leaq 744(%r14), %r13
leaq 128(%rsp), %rbp
jmp .LBB8_1
.p2align 4, 0x90
.LBB8_5: # in Loop: Header=BB8_1 Depth=1
testl %eax, %eax
je .LBB8_6
.LBB8_7: # in Loop: Header=BB8_1 Depth=1
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq %r12, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.7, %esi
movl $184, %edi
.LBB8_8: # in Loop: Header=BB8_1 Depth=1
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 120(%rsp), %rsi
movq 40(%rsp), %rdx
movq %rbp, %rdi
callq hipEventElapsedTime
movss 116(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss 128(%rsp), %xmm0
incl %ebx
cmpl $100000, %ebx # imm = 0x186A0
je .LBB8_9
.LBB8_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, 116(%rsp) # 4-byte Spill
movq 120(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r13, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testb $1, %bl
jne .LBB8_5
# %bb.2: # in Loop: Header=BB8_1 Depth=1
testl %eax, %eax
jne .LBB8_4
# %bb.3: # in Loop: Header=BB8_1 Depth=1
movq 16(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z16reciprocalKernelPfS_j, %edi
movq %rbp, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_4: # in Loop: Header=BB8_1 Depth=1
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rsi
movq %r12, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.6, %esi
movl $180, %edi
jmp .LBB8_8
.LBB8_6: # in Loop: Header=BB8_1 Depth=1
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z16reciprocalKernelPfS_j, %edi
movq %rbp, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB8_7
.LBB8_9:
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movl $.L.str.9, %esi
movl $200, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
movq 32(%rsp), %rdi
callq hipFree
movl $.L.str.10, %esi
movl $201, %edi
movl %eax, %edx
callq _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z13gpuReciprocalPfj, .Lfunc_end8-_Z13gpuReciprocalPfj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.type _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t,@function
_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t: # @_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_startproc
# %bb.0:
testl %edx, %edx
jne .LBB9_2
# %bb.1:
retq
.LBB9_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl %edx, %ebp
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.12, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebp, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.13, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.14, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.15, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEj
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end9:
.size _ZL17CheckCudaErrorAuxPKcjS0_10hipError_t, .Lfunc_end9-_ZL17CheckCudaErrorAuxPKcjS0_10hipError_t
.cfi_endproc
# -- End function
.globl _Z10initializePfj # -- Begin function _Z10initializePfj
.p2align 4, 0x90
.type _Z10initializePfj,@function
_Z10initializePfj: # @_Z10initializePfj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB10_1
# %bb.2: # %.lr.ph.preheader
movl %esi, %edx
shlq $2, %rdx
xorl %esi, %esi
jmp memset@PLT # TAILCALL
.LBB10_1: # %._crit_edge
retq
.Lfunc_end10:
.size _Z10initializePfj, .Lfunc_end10-_Z10initializePfj
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12cpuIterationPfS_j
.LCPI11_0:
.quad 0x3f1a36e2eb1c432d # double 1.0E-4
.LCPI11_1:
.quad 0x4010000000000000 # double 4
.text
.globl _Z12cpuIterationPfS_j
.p2align 4, 0x90
.type _Z12cpuIterationPfS_j,@function
_Z12cpuIterationPfS_j: # @_Z12cpuIterationPfS_j
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
testl %edx, %edx
je .LBB11_9
# %bb.1: # %.lr.ph
leal -1(%rdx), %eax
movl %edx, %ecx
xorl %edx, %edx
movsd .LCPI11_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI11_1(%rip), %xmm1 # xmm1 = mem[0],zero
jmp .LBB11_2
.p2align 4, 0x90
.LBB11_3: # in Loop: Header=BB11_2 Depth=1
movss (%rdi,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
addsd %xmm0, %xmm2
.LBB11_7: # in Loop: Header=BB11_2 Depth=1
cvtsd2ss %xmm2, %xmm2
movss %xmm2, (%rsi,%rdx,4)
.LBB11_8: # in Loop: Header=BB11_2 Depth=1
incq %rdx
cmpq %rdx, %rcx
je .LBB11_9
.LBB11_2: # =>This Inner Loop Header: Depth=1
cmpq %rdx, %rax
je .LBB11_3
# %bb.4: # in Loop: Header=BB11_2 Depth=1
testq %rdx, %rdx
je .LBB11_5
# %bb.6: # in Loop: Header=BB11_2 Depth=1
movss -4(%rdi,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%rdi,%rdx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
xorps %xmm4, %xmm4
cvtss2sd %xmm3, %xmm4
addss %xmm3, %xmm3
subss %xmm3, %xmm2
addss 4(%rdi,%rdx,4), %xmm2
cvtss2sd %xmm2, %xmm2
mulsd %xmm0, %xmm2
mulsd %xmm1, %xmm2
addsd %xmm4, %xmm2
jmp .LBB11_7
.LBB11_5: # in Loop: Header=BB11_2 Depth=1
movl $0, (%rsi)
jmp .LBB11_8
.LBB11_9: # %._crit_edge
retq
.Lfunc_end11:
.size _Z12cpuIterationPfS_j, .Lfunc_end11-_Z12cpuIterationPfS_j
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13cpuReciprocalPfj
.LCPI12_0:
.quad 0x3f1a36e2eb1c432d # double 1.0E-4
.LCPI12_1:
.quad 0x4010000000000000 # double 4
.LCPI12_2:
.quad 0x408f400000000000 # double 1000
.LCPI12_3:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z13cpuReciprocalPfj
.p2align 4, 0x90
.type _Z13cpuReciprocalPfj,@function
_Z13cpuReciprocalPfj: # @_Z13cpuReciprocalPfj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %esi, %r12d
leaq (,%r12,4), %r15
movq %r15, %rdi
callq _Znam
movq %rax, %r14
movq %r15, %rdi
callq _Znam
movq %rax, %r15
leal -1(%rbx), %r13d
xorps %xmm0, %xmm0
xorl %ebp, %ebp
jmp .LBB12_1
.p2align 4, 0x90
.LBB12_20: # %_Z12cpuIterationPfS_j.exit
# in Loop: Header=BB12_1 Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
subss (%rsp), %xmm0 # 4-byte Folded Reload
cvtss2sd %xmm0, %xmm0
mulsd .LCPI12_2(%rip), %xmm0
divsd .LCPI12_3(%rip), %xmm0
movss 4(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
incl %ebp
cmpl $100000, %ebp # imm = 0x186A0
je .LBB12_21
.LBB12_1: # =>This Loop Header: Depth=1
# Child Loop BB12_13 Depth 2
# Child Loop BB12_4 Depth 2
movss %xmm0, 4(%rsp) # 4-byte Spill
callq clock
testb $1, %bpl
jne .LBB12_11
# %bb.2: # in Loop: Header=BB12_1 Depth=1
testl %ebx, %ebx
movsd .LCPI12_0(%rip), %xmm3 # xmm3 = mem[0],zero
movsd .LCPI12_1(%rip), %xmm4 # xmm4 = mem[0],zero
je .LBB12_20
# %bb.3: # %.lr.ph.i.preheader
# in Loop: Header=BB12_1 Depth=1
xorl %ecx, %ecx
jmp .LBB12_4
.p2align 4, 0x90
.LBB12_5: # in Loop: Header=BB12_4 Depth=2
movss (%r15,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
addsd %xmm3, %xmm0
.LBB12_9: # in Loop: Header=BB12_4 Depth=2
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%rcx,4)
.LBB12_10: # in Loop: Header=BB12_4 Depth=2
incq %rcx
cmpq %rcx, %r12
je .LBB12_20
.LBB12_4: # %.lr.ph.i
# Parent Loop BB12_1 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rcx, %r13
je .LBB12_5
# %bb.6: # in Loop: Header=BB12_4 Depth=2
testq %rcx, %rcx
je .LBB12_7
# %bb.8: # in Loop: Header=BB12_4 Depth=2
movss -4(%r15,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r15,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
cvtss2sd %xmm1, %xmm2
addss %xmm1, %xmm1
subss %xmm1, %xmm0
addss 4(%r15,%rcx,4), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm3, %xmm0
mulsd %xmm4, %xmm0
addsd %xmm2, %xmm0
jmp .LBB12_9
.LBB12_7: # in Loop: Header=BB12_4 Depth=2
movl $0, (%r14)
jmp .LBB12_10
.p2align 4, 0x90
.LBB12_11: # in Loop: Header=BB12_1 Depth=1
testl %ebx, %ebx
movsd .LCPI12_0(%rip), %xmm3 # xmm3 = mem[0],zero
movsd .LCPI12_1(%rip), %xmm4 # xmm4 = mem[0],zero
je .LBB12_20
# %bb.12: # %.lr.ph.i19.preheader
# in Loop: Header=BB12_1 Depth=1
xorl %ecx, %ecx
jmp .LBB12_13
.p2align 4, 0x90
.LBB12_14: # in Loop: Header=BB12_13 Depth=2
movss (%r14,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
addsd %xmm3, %xmm0
.LBB12_18: # in Loop: Header=BB12_13 Depth=2
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%rcx,4)
.LBB12_19: # in Loop: Header=BB12_13 Depth=2
incq %rcx
cmpq %rcx, %r12
je .LBB12_20
.LBB12_13: # %.lr.ph.i19
# Parent Loop BB12_1 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rcx, %r13
je .LBB12_14
# %bb.15: # in Loop: Header=BB12_13 Depth=2
testq %rcx, %rcx
je .LBB12_16
# %bb.17: # in Loop: Header=BB12_13 Depth=2
movss -4(%r14,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r14,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
cvtss2sd %xmm1, %xmm2
addss %xmm1, %xmm1
subss %xmm1, %xmm0
addss 4(%r14,%rcx,4), %xmm0
cvtss2sd %xmm0, %xmm0
mulsd %xmm3, %xmm0
mulsd %xmm4, %xmm0
addsd %xmm2, %xmm0
jmp .LBB12_18
.LBB12_16: # in Loop: Header=BB12_13 Depth=2
movl $0, (%r15)
jmp .LBB12_19
.LBB12_21:
cvtss2sd %xmm0, %xmm0
movl $.L.str.11, %edi
movb $1, %al
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end12:
.size _Z13cpuReciprocalPfj, .Lfunc_end12-_Z13cpuReciprocalPfj
.cfi_endproc
# -- End function
.globl _Z14checkShodimostv # -- Begin function _Z14checkShodimostv
.p2align 4, 0x90
.type _Z14checkShodimostv,@function
_Z14checkShodimostv: # @_Z14checkShodimostv
.cfi_startproc
# %bb.0:
movb $1, %al
retq
.Lfunc_end13:
.size _Z14checkShodimostv, .Lfunc_end13-_Z14checkShodimostv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $5, %edi
callq _Z5modeli
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end14:
.size main, .Lfunc_end14-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB15_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB15_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16reciprocalKernelPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end15:
.size __hip_module_ctor, .Lfunc_end15-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB16_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB16_2:
retq
.Lfunc_end16:
.size __hip_module_dtor, .Lfunc_end16-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Iteration num "
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "F array"
.size .L.str.1, 8
.type _Z16reciprocalKernelPfS_j,@object # @_Z16reciprocalKernelPfS_j
.section .rodata,"a",@progbits
.globl _Z16reciprocalKernelPfS_j
.p2align 3, 0x0
_Z16reciprocalKernelPfS_j:
.quad _Z31__device_stub__reciprocalKernelPfS_j
.size _Z16reciprocalKernelPfS_j, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/neikila/Cuda/master/LAB2.hip"
.size .L.str.2, 86
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc((void **)&gpuOldData, sizeof(float)*size)"
.size .L.str.3, 52
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc((void **)&gpuNewData, sizeof(float)*size)"
.size .L.str.4, 52
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy(gpuOldData, data, sizeof(float)*size, hipMemcpyHostToDevice)"
.size .L.str.5, 71
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMemcpy(rc, gpuNewData, sizeof(float)*size, hipMemcpyDeviceToHost)"
.size .L.str.6, 69
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy(rc, gpuOldData, sizeof(float)*size, hipMemcpyDeviceToHost)"
.size .L.str.7, 69
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU time : %.3f ms\n"
.size .L.str.8, 20
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipFree(gpuOldData)"
.size .L.str.9, 20
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipFree(gpuNewData)"
.size .L.str.10, 20
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "CPU time : %.3f ms\n"
.size .L.str.11, 20
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " returned "
.size .L.str.12, 11
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "("
.size .L.str.13, 2
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz ") at "
.size .L.str.14, 6
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz ":"
.size .L.str.15, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16reciprocalKernelPfS_j"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__reciprocalKernelPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z16reciprocalKernelPfS_j
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16reciprocalKernelPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0070*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0080*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fcc000fffe03f */
/*0090*/ ISETP.NE.AND P0, PT, R0.reuse, UR4, PT ; /* 0x0000000400007c0c */
/* 0x040fe2000bf05270 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ IMAD.WIDE.U32 R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e000b */
/*00c0*/ IMAD.WIDE.U32 R2, R0, R11, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e000b */
/*00d0*/ @!P0 BRA 0x230 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*00f0*/ @!P0 BRA 0x210 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R8, R0.reuse, -0x1, RZ ; /* 0xffffffff00087810 */
/* 0x040fe20007ffe0ff */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R10, R0, 0x1, RZ ; /* 0x00000001000a7810 */
/* 0x000fc60007ffe0ff */
/*0130*/ IMAD.WIDE.U32 R8, R8, R11, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e000b */
/*0140*/ IMAD.WIDE.U32 R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fe400078e000b */
/*0150*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1900 */
/*0160*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f22000c1e1900 */
/*0170*/ FADD R7, R4, R4 ; /* 0x0000000404077221 */
/* 0x004fc80000000000 */
/*0180*/ FADD R7, R8, -R7 ; /* 0x8000000708077221 */
/* 0x008fc80000000000 */
/*0190*/ FADD R0, R7, R10 ; /* 0x0000000a07007221 */
/* 0x010fc80000000000 */
/*01a0*/ F2F.F64.F32 R12, R0 ; /* 0x00000000000c7310 */
/* 0x000e300000201800 */
/*01b0*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */
/* 0x000e620000201800 */
/*01c0*/ DMUL R12, R12, c[0x2][0x0] ; /* 0x008000000c0c7a28 */
/* 0x001e4c0000000000 */
/*01d0*/ DFMA R6, R12, 4, R6 ; /* 0x401000000c06782b */
/* 0x002e140000000006 */
/*01e0*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*01f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0240*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */
/* 0x004e240000201800 */
/*0250*/ DADD R6, R6, c[0x2][0x0] ; /* 0x0080000006067629 */
/* 0x001e140000000000 */
/*0260*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*0270*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16reciprocalKernelPfS_j
.globl _Z16reciprocalKernelPfS_j
.p2align 8
.type _Z16reciprocalKernelPfS_j,@function
_Z16reciprocalKernelPfS_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s4, v1
s_cbranch_execz .LBB0_9
s_load_b128 s[0:3], s[0:1], 0x0
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_7
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, -1, v1
s_mov_b32 s7, 0x3f1a36e2
s_mov_b32 s6, 0xeb1c432d
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mov_b32_e32 v4, v2
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_nc_u32_e32 v1, 1, v1
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x2
global_load_b32 v4, v[7:8], off
global_load_b32 v2, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(1)
v_fmac_f32_e32 v2, -2.0, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v0, v2, v0
v_cvt_f64_f32_e32 v[2:3], v4
v_cvt_f64_f32_e32 v[0:1], v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], s[6:7]
v_fma_f64 v[0:1], v[0:1], 4.0, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v6, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v0, s[2:3]
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_7:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0x3f1a36e2
s_mov_b32 s0, 0xeb1c432d
v_add_co_u32 v0, vcc_lo, s2, v0
global_load_b32 v2, v[2:3], off
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], s[0:1]
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16reciprocalKernelPfS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16reciprocalKernelPfS_j, .Lfunc_end0-_Z16reciprocalKernelPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16reciprocalKernelPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16reciprocalKernelPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
//think about inlining this
__device__ double* three_dim_indexGPU(double* matrix, int i, int j, int k, double m, int b){
int m_int = (int)m;
double* p;
//specify index layout here
p=&matrix[(m_int)*b*(k)+(m_int)*(j)+(i)];
return p;
}
__device__ double* two_dim_indexGPU(double* vector, int i, int j, double m, int b){
//int m_int= (int)m;
double* p;
//specify index layout here
p=&vector[b*(i)+(j)];
return p;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
//think about inlining this
__device__ double* three_dim_indexGPU(double* matrix, int i, int j, int k, double m, int b){
int m_int = (int)m;
double* p;
//specify index layout here
p=&matrix[(m_int)*b*(k)+(m_int)*(j)+(i)];
return p;
}
__device__ double* two_dim_indexGPU(double* vector, int i, int j, double m, int b){
//int m_int= (int)m;
double* p;
//specify index layout here
p=&vector[b*(i)+(j)];
return p;
} | .file "tmpxft_00108632_00000000-6_cuda_index.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18three_dim_indexGPUPdiiidi
.type _Z18three_dim_indexGPUPdiiidi, @function
_Z18three_dim_indexGPUPdiiidi:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z18three_dim_indexGPUPdiiidi, .-_Z18three_dim_indexGPUPdiiidi
.globl _Z16two_dim_indexGPUPdiidi
.type _Z16two_dim_indexGPUPdiidi, @function
_Z16two_dim_indexGPUPdiidi:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z16two_dim_indexGPUPdiidi, .-_Z16two_dim_indexGPUPdiidi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
//think about inlining this
__device__ double* three_dim_indexGPU(double* matrix, int i, int j, int k, double m, int b){
int m_int = (int)m;
double* p;
//specify index layout here
p=&matrix[(m_int)*b*(k)+(m_int)*(j)+(i)];
return p;
}
__device__ double* two_dim_indexGPU(double* vector, int i, int j, double m, int b){
//int m_int= (int)m;
double* p;
//specify index layout here
p=&vector[b*(i)+(j)];
return p;
} | #include <hip/hip_runtime.h>
#include<iostream>
//think about inlining this
__device__ double* three_dim_indexGPU(double* matrix, int i, int j, int k, double m, int b){
int m_int = (int)m;
double* p;
//specify index layout here
p=&matrix[(m_int)*b*(k)+(m_int)*(j)+(i)];
return p;
}
__device__ double* two_dim_indexGPU(double* vector, int i, int j, double m, int b){
//int m_int= (int)m;
double* p;
//specify index layout here
p=&vector[b*(i)+(j)];
return p;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
//think about inlining this
__device__ double* three_dim_indexGPU(double* matrix, int i, int j, int k, double m, int b){
int m_int = (int)m;
double* p;
//specify index layout here
p=&matrix[(m_int)*b*(k)+(m_int)*(j)+(i)];
return p;
}
__device__ double* two_dim_indexGPU(double* vector, int i, int j, double m, int b){
//int m_int= (int)m;
double* p;
//specify index layout here
p=&vector[b*(i)+(j)];
return p;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
//think about inlining this
__device__ double* three_dim_indexGPU(double* matrix, int i, int j, int k, double m, int b){
int m_int = (int)m;
double* p;
//specify index layout here
p=&matrix[(m_int)*b*(k)+(m_int)*(j)+(i)];
return p;
}
__device__ double* two_dim_indexGPU(double* vector, int i, int j, double m, int b){
//int m_int= (int)m;
double* p;
//specify index layout here
p=&vector[b*(i)+(j)];
return p;
} | .text
.file "cuda_index.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00108632_00000000-6_cuda_index.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18three_dim_indexGPUPdiiidi
.type _Z18three_dim_indexGPUPdiiidi, @function
_Z18three_dim_indexGPUPdiiidi:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z18three_dim_indexGPUPdiiidi, .-_Z18three_dim_indexGPUPdiiidi
.globl _Z16two_dim_indexGPUPdiidi
.type _Z16two_dim_indexGPUPdiidi, @function
_Z16two_dim_indexGPUPdiidi:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z16two_dim_indexGPUPdiidi, .-_Z16two_dim_indexGPUPdiidi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_index.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cudaUpdateActivity_kernel(int * inputs, char * activity, unsigned int * firingRate, unsigned int * exampleFiringRate, int * totalOutput, unsigned long long int * firstEventTime, unsigned long long int * lastEventTime, unsigned int inputsDimX, unsigned int inputsDimY, unsigned int inputsDimZ, unsigned int long long timestamp)
{
const unsigned int inputSize = inputsDimZ * inputsDimX * inputsDimY;
// One batch per block z dimension
const unsigned int batchInputOffset = blockIdx.z * inputSize;
for (unsigned int channel = blockIdx.x; channel < inputsDimZ; channel += gridDim.x) {
for (unsigned int y = threadIdx.y; y < inputsDimY; y += blockDim.y) {
for (unsigned int x = threadIdx.x; x < inputsDimX; x += blockDim.x) {
const unsigned int inputsIdx =
x + y*inputsDimX + channel*inputsDimX*inputsDimY;
int act = inputs[inputsIdx + batchInputOffset];
unsigned int actAbs = abs(act);
char spike = act == 0 ? 0 : act/abs(act);
activity[inputsIdx + batchInputOffset] = spike;
firingRate[inputsIdx + batchInputOffset] += actAbs;
exampleFiringRate[inputsIdx + batchInputOffset] += actAbs;
totalOutput[inputsIdx + batchInputOffset] += act;
}
}
}
} | code for sm_80
Function : _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x1a0], PT ; /* 0x000068000a007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e680000002100 */
/*0070*/ S2R R9, SR_CTAID.Z ; /* 0x0000000000097919 */
/* 0x000ea40000002700 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x19c], PT ; /* 0x0000670000007a0c */
/* 0x001fe20003f06070 */
/*0090*/ BSSY B0, 0x500 ; /* 0x0000046000007945 */
/* 0x000fd80003800000 */
/*00a0*/ @P0 BRA 0x4f0 ; /* 0x0000044000000947 */
/* 0x006fea0003800000 */
/*00b0*/ IMAD R11, R9, c[0x0][0x1a0], R10 ; /* 0x00006800090b7a24 */
/* 0x004fe400078e020a */
/*00c0*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0000 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x198], PT ; /* 0x0000660008007a0c */
/* 0x002fe20003f06070 */
/*00e0*/ BSSY B1, 0x4c0 ; /* 0x000003d000017945 */
/* 0x000fd80003800000 */
/*00f0*/ @P0 BRA 0x4b0 ; /* 0x000003b000000947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD R3, R11, c[0x0][0x19c], R12 ; /* 0x000067000b037a24 */
/* 0x000fe400078e020c */
/*0110*/ IMAD.MOV.U32 R13, RZ, RZ, R8.reuse ; /* 0x000000ffff0d7224 */
/* 0x100fe400078e0008 */
/*0120*/ IMAD R14, R3, c[0x0][0x198], R8 ; /* 0x00006600030e7a24 */
/* 0x000fe400078e0208 */
/*0130*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x002fc800078e00ff */
/*0140*/ IMAD.WIDE.U32 R18, R14, R19, c[0x0][0x160] ; /* 0x000058000e127625 */
/* 0x000fcc00078e0013 */
/*0150*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea2000c1e1900 */
/*0160*/ IMAD.SHL.U32 R17, R14.reuse, 0x4, RZ ; /* 0x000000040e117824 */
/* 0x040fe200078e00ff */
/*0170*/ IADD3 R4, P1, R14, c[0x0][0x168], RZ ; /* 0x00005a000e047a10 */
/* 0x000fe20007f3e0ff */
/*0180*/ BSSY B2, 0x390 ; /* 0x0000020000027945 */
/* 0x000fe20003800000 */
/*0190*/ SHF.R.U32.HI R16, RZ, 0x1e, R14 ; /* 0x0000001eff107819 */
/* 0x000fe2000001160e */
/*01a0*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*01b0*/ IADD3 R2, P2, R17, c[0x0][0x170], RZ ; /* 0x00005c0011027a10 */
/* 0x000fe20007f5e0ff */
/*01c0*/ IMAD.X R5, RZ, RZ, c[0x0][0x16c], P1 ; /* 0x00005b00ff057624 */
/* 0x000fc600008e06ff */
/*01d0*/ IADD3.X R3, R16, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0010037a10 */
/* 0x000fe400017fe4ff */
/*01e0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x004fe40003f05270 */
/*01f0*/ IABS R15, R18 ; /* 0x00000012000f7213 */
/* 0x000fd60000000000 */
/*0200*/ @!P0 BRA 0x380 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0210*/ I2F.RP R19, R15 ; /* 0x0000000f00137306 */
/* 0x000e220000209400 */
/*0220*/ IABS R22, R18 ; /* 0x0000001200167213 */
/* 0x000fca0000000000 */
/*0230*/ IMAD.MOV R22, RZ, RZ, -R22 ; /* 0x000000ffff167224 */
/* 0x000fe400078e0a16 */
/*0240*/ MUFU.RCP R19, R19 ; /* 0x0000001300137308 */
/* 0x001e240000001000 */
/*0250*/ IADD3 R6, R19, 0xffffffe, RZ ; /* 0x0ffffffe13067810 */
/* 0x001fcc0007ffe0ff */
/*0260*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0270*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0280*/ IMAD.MOV R20, RZ, RZ, -R7 ; /* 0x000000ffff147224 */
/* 0x002fc800078e0a07 */
/*0290*/ IMAD R21, R20, R15, RZ ; /* 0x0000000f14157224 */
/* 0x000fc800078e02ff */
/*02a0*/ IMAD.HI.U32 R20, R7, R21, R6 ; /* 0x0000001507147227 */
/* 0x000fe200078e0006 */
/*02b0*/ LOP3.LUT R6, R18, R15, RZ, 0x3c, !PT ; /* 0x0000000f12067212 */
/* 0x000fc800078e3cff */
/*02c0*/ ISETP.GE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f26270 */
/*02d0*/ IMAD.HI.U32 R20, R20, R15, RZ ; /* 0x0000000f14147227 */
/* 0x000fc800078e00ff */
/*02e0*/ IMAD R22, R20, R22, R15 ; /* 0x0000001614167224 */
/* 0x000fca00078e020f */
/*02f0*/ ISETP.GT.U32.AND P2, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fda0003f44070 */
/*0300*/ @!P2 IMAD.IADD R22, R22, 0x1, -R15 ; /* 0x000000011616a824 */
/* 0x000fe200078e0a0f */
/*0310*/ @!P2 IADD3 R20, R20, 0x1, RZ ; /* 0x000000011414a810 */
/* 0x000fe40007ffe0ff */
/*0320*/ ISETP.NE.AND P2, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe40003f45270 */
/*0330*/ ISETP.GE.U32.AND P0, PT, R22, R15, PT ; /* 0x0000000f1600720c */
/* 0x000fda0003f06070 */
/*0340*/ @P0 IADD3 R20, R20, 0x1, RZ ; /* 0x0000000114140810 */
/* 0x000fca0007ffe0ff */
/*0350*/ @!P1 IMAD.MOV R20, RZ, RZ, -R20 ; /* 0x000000ffff149224 */
/* 0x000fe200078e0a14 */
/*0360*/ @!P2 LOP3.LUT R20, RZ, R15, RZ, 0x33, !PT ; /* 0x0000000fff14a212 */
/* 0x000fca00078e33ff */
/*0370*/ IMAD.MOV.U32 R23, RZ, RZ, R20 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0014 */
/*0380*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0390*/ STG.E.U8 [R4.64], R23 ; /* 0x0000001704007986 */
/* 0x0001e8000c101104 */
/*03a0*/ LDG.E R20, [R2.64] ; /* 0x0000000402147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IADD3 R6, P0, R17, c[0x0][0x178], RZ ; /* 0x00005e0011067a10 */
/* 0x000fc80007f1e0ff */
/*03c0*/ IADD3.X R7, R16, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0010077a10 */
/* 0x000fe200007fe4ff */
/*03d0*/ IMAD.IADD R19, R20, 0x1, R15 ; /* 0x0000000114137824 */
/* 0x004fca00078e020f */
/*03e0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*03f0*/ LDG.E R22, [R6.64] ; /* 0x0000000406167981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IADD3 R20, P0, R17, c[0x0][0x180], RZ ; /* 0x0000600011147a10 */
/* 0x000fc80007f1e0ff */
/*0410*/ IADD3.X R21, R16, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610010157a10 */
/* 0x000fe200007fe4ff */
/*0420*/ IMAD.IADD R15, R22, 0x1, R15 ; /* 0x00000001160f7824 */
/* 0x004fca00078e020f */
/*0430*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0003e8000c101904 */
/*0440*/ LDG.E R5, [R20.64] ; /* 0x0000000414057981 */
/* 0x001ea2000c1e1900 */
/*0450*/ IADD3 R13, R13, c[0x0][0x0], RZ ; /* 0x000000000d0d7a10 */
/* 0x000fe40007ffe0ff */
/*0460*/ IADD3 R14, R14, c[0x0][0x0], RZ ; /* 0x000000000e0e7a10 */
/* 0x000fe40007ffe0ff */
/*0470*/ ISETP.GE.U32.AND P0, PT, R13, c[0x0][0x198], PT ; /* 0x000066000d007a0c */
/* 0x000fe20003f06070 */
/*0480*/ IMAD.IADD R5, R18, 0x1, R5 ; /* 0x0000000112057824 */
/* 0x004fca00078e0205 */
/*0490*/ STG.E [R20.64], R5 ; /* 0x0000000514007986 */
/* 0x0003ee000c101904 */
/*04a0*/ @!P0 BRA 0x130 ; /* 0xfffffc8000008947 */
/* 0x000fea000383ffff */
/*04b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R12, R12, c[0x0][0x4], RZ ; /* 0x000001000c0c7a10 */
/* 0x000fc80007ffe0ff */
/*04d0*/ ISETP.GE.U32.AND P0, PT, R12, c[0x0][0x19c], PT ; /* 0x000067000c007a0c */
/* 0x000fda0003f06070 */
/*04e0*/ @!P0 BRA 0xd0 ; /* 0xfffffbe000008947 */
/* 0x000fea000383ffff */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ IADD3 R10, R10, c[0x0][0xc], RZ ; /* 0x000003000a0a7a10 */
/* 0x000fc80007ffe0ff */
/*0510*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x1a0], PT ; /* 0x000068000a007a0c */
/* 0x000fda0003f06070 */
/*0520*/ @!P0 BRA 0x80 ; /* 0xfffffb5000008947 */
/* 0x000fea000383ffff */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cudaUpdateActivity_kernel(int * inputs, char * activity, unsigned int * firingRate, unsigned int * exampleFiringRate, int * totalOutput, unsigned long long int * firstEventTime, unsigned long long int * lastEventTime, unsigned int inputsDimX, unsigned int inputsDimY, unsigned int inputsDimZ, unsigned int long long timestamp)
{
const unsigned int inputSize = inputsDimZ * inputsDimX * inputsDimY;
// One batch per block z dimension
const unsigned int batchInputOffset = blockIdx.z * inputSize;
for (unsigned int channel = blockIdx.x; channel < inputsDimZ; channel += gridDim.x) {
for (unsigned int y = threadIdx.y; y < inputsDimY; y += blockDim.y) {
for (unsigned int x = threadIdx.x; x < inputsDimX; x += blockDim.x) {
const unsigned int inputsIdx =
x + y*inputsDimX + channel*inputsDimX*inputsDimY;
int act = inputs[inputsIdx + batchInputOffset];
unsigned int actAbs = abs(act);
char spike = act == 0 ? 0 : act/abs(act);
activity[inputsIdx + batchInputOffset] = spike;
firingRate[inputsIdx + batchInputOffset] += actAbs;
exampleFiringRate[inputsIdx + batchInputOffset] += actAbs;
totalOutput[inputsIdx + batchInputOffset] += act;
}
}
}
} | .file "tmpxft_00152f89_00000000-6_cudaUpdateActivity_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z63__device_stub__Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjyPiPcPjS1_S_PyS2_jjjy
.type _Z63__device_stub__Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjyPiPcPjS1_S_PyS2_jjjy, @function
_Z63__device_stub__Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjyPiPcPjS1_S_PyS2_jjjy:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 272(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z63__device_stub__Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjyPiPcPjS1_S_PyS2_jjjy, .-_Z63__device_stub__Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjyPiPcPjS1_S_PyS2_jjjy
.globl _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.type _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy, @function
_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z63__device_stub__Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjyPiPcPjS1_S_PyS2_jjjy
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy, .-_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cudaUpdateActivity_kernel(int * inputs, char * activity, unsigned int * firingRate, unsigned int * exampleFiringRate, int * totalOutput, unsigned long long int * firstEventTime, unsigned long long int * lastEventTime, unsigned int inputsDimX, unsigned int inputsDimY, unsigned int inputsDimZ, unsigned int long long timestamp)
{
const unsigned int inputSize = inputsDimZ * inputsDimX * inputsDimY;
// One batch per block z dimension
const unsigned int batchInputOffset = blockIdx.z * inputSize;
for (unsigned int channel = blockIdx.x; channel < inputsDimZ; channel += gridDim.x) {
for (unsigned int y = threadIdx.y; y < inputsDimY; y += blockDim.y) {
for (unsigned int x = threadIdx.x; x < inputsDimX; x += blockDim.x) {
const unsigned int inputsIdx =
x + y*inputsDimX + channel*inputsDimX*inputsDimY;
int act = inputs[inputsIdx + batchInputOffset];
unsigned int actAbs = abs(act);
char spike = act == 0 ? 0 : act/abs(act);
activity[inputsIdx + batchInputOffset] = spike;
firingRate[inputsIdx + batchInputOffset] += actAbs;
exampleFiringRate[inputsIdx + batchInputOffset] += actAbs;
totalOutput[inputsIdx + batchInputOffset] += act;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaUpdateActivity_kernel(int * inputs, char * activity, unsigned int * firingRate, unsigned int * exampleFiringRate, int * totalOutput, unsigned long long int * firstEventTime, unsigned long long int * lastEventTime, unsigned int inputsDimX, unsigned int inputsDimY, unsigned int inputsDimZ, unsigned int long long timestamp)
{
const unsigned int inputSize = inputsDimZ * inputsDimX * inputsDimY;
// One batch per block z dimension
const unsigned int batchInputOffset = blockIdx.z * inputSize;
for (unsigned int channel = blockIdx.x; channel < inputsDimZ; channel += gridDim.x) {
for (unsigned int y = threadIdx.y; y < inputsDimY; y += blockDim.y) {
for (unsigned int x = threadIdx.x; x < inputsDimX; x += blockDim.x) {
const unsigned int inputsIdx =
x + y*inputsDimX + channel*inputsDimX*inputsDimY;
int act = inputs[inputsIdx + batchInputOffset];
unsigned int actAbs = abs(act);
char spike = act == 0 ? 0 : act/abs(act);
activity[inputsIdx + batchInputOffset] = spike;
firingRate[inputsIdx + batchInputOffset] += actAbs;
exampleFiringRate[inputsIdx + batchInputOffset] += actAbs;
totalOutput[inputsIdx + batchInputOffset] += act;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaUpdateActivity_kernel(int * inputs, char * activity, unsigned int * firingRate, unsigned int * exampleFiringRate, int * totalOutput, unsigned long long int * firstEventTime, unsigned long long int * lastEventTime, unsigned int inputsDimX, unsigned int inputsDimY, unsigned int inputsDimZ, unsigned int long long timestamp)
{
const unsigned int inputSize = inputsDimZ * inputsDimX * inputsDimY;
// One batch per block z dimension
const unsigned int batchInputOffset = blockIdx.z * inputSize;
for (unsigned int channel = blockIdx.x; channel < inputsDimZ; channel += gridDim.x) {
for (unsigned int y = threadIdx.y; y < inputsDimY; y += blockDim.y) {
for (unsigned int x = threadIdx.x; x < inputsDimX; x += blockDim.x) {
const unsigned int inputsIdx =
x + y*inputsDimX + channel*inputsDimX*inputsDimY;
int act = inputs[inputsIdx + batchInputOffset];
unsigned int actAbs = abs(act);
char spike = act == 0 ? 0 : act/abs(act);
activity[inputsIdx + batchInputOffset] = spike;
firingRate[inputsIdx + batchInputOffset] += actAbs;
exampleFiringRate[inputsIdx + batchInputOffset] += actAbs;
totalOutput[inputsIdx + batchInputOffset] += act;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.globl _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.p2align 8
.type _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy,@function
_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy:
s_load_b32 s18, s[0:1], 0x40
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s14, s18
s_cbranch_scc1 .LBB0_11
s_clause 0x3
s_load_b64 s[2:3], s[0:1], 0x38
s_load_b64 s[12:13], s[0:1], 0x20
s_load_b32 s19, s[0:1], 0x50
s_load_b256 s[4:11], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
s_mul_i32 s15, s15, s18
s_add_u32 s16, s0, 0x50
s_addc_u32 s17, s1, 0
s_add_i32 s0, s14, s15
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s3, s0, v[1:2]
v_mov_b32_e32 v3, 0
v_cmp_gt_u32_e32 vcc_lo, s3, v1
v_cmp_gt_u32_e64 s0, s2, v0
s_mul_i32 s15, s19, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
s_mul_i32 s15, s15, s2
v_mul_lo_u32 v6, s2, v2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v6, s15, v6
s_add_i32 s14, s19, s14
s_cmp_ge_u32 s14, s18
s_cbranch_scc1 .LBB0_11
.LBB0_3:
s_and_saveexec_b32 s20, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s1, s[16:17], 0xc
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v1
s_mov_b32 s23, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s21, s1, 16
s_mul_i32 s22, s2, s21
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s24
v_add_nc_u32_e32 v8, s21, v8
v_add_nc_u32_e32 v7, s22, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s1, s3, v8
s_or_b32 s23, s1, s23
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execz .LBB0_2
.LBB0_6:
s_and_saveexec_b32 s24, s0
s_cbranch_execz .LBB0_5
s_load_b32 s1, s[16:17], 0xc
v_mov_b32_e32 v9, v0
s_mov_b32 s26, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s25, s1, 0xffff
s_branch .LBB0_9
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s27
v_add_co_u32 v13, s1, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s1, s7, v3, s1
v_add_co_u32 v15, s1, s8, v4
v_add_co_ci_u32_e64 v16, s1, s9, v5, s1
global_store_b8 v[13:14], v12, off
v_add_co_u32 v12, s1, s10, v4
global_load_b32 v2, v[15:16], off
v_add_co_ci_u32_e64 v13, s1, s11, v5, s1
v_add_co_u32 v4, s1, s12, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s1, s13, v5, s1
v_add_nc_u32_e32 v9, s25, v9
v_cmp_le_u32_e64 s1, s2, v9
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s26, s1, s26
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v11
global_store_b32 v[15:16], v2, off
global_load_b32 v2, v[12:13], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v11
global_store_b32 v[12:13], v2, off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v10
global_store_b32 v[4:5], v2, off
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execz .LBB0_5
.LBB0_9:
v_add_nc_u32_e32 v2, v7, v9
v_mov_b32_e32 v12, 0
s_mov_b32 s27, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_co_u32 v10, s1, s4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s1, s5, v5, s1
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v11, 0, v10
v_max_i32_e32 v11, v10, v11
v_cmpx_ne_u32_e32 0, v10
s_cbranch_execz .LBB0_8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_f32_u32_e32 v12, v11
v_ashrrev_i32_e32 v14, 31, v10
v_sub_nc_u32_e32 v13, 0, v11
v_rcp_iflag_f32_e32 v12, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v15, v10, v14
v_xor_b32_e32 v15, v15, v14
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, 0x4f7ffffe, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v12, v12
v_mul_lo_u32 v13, v13, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v13, v12, v13
v_add_nc_u32_e32 v12, v12, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v12, v15, v12
v_mul_lo_u32 v13, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v13, v15, v13
v_add_nc_u32_e32 v15, 1, v12
v_sub_nc_u32_e32 v16, v13, v11
v_cmp_ge_u32_e64 s1, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v12, v12, v15, s1
v_cndmask_b32_e64 v13, v13, v16, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, 1, v12
v_cmp_ge_u32_e64 s1, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v12, v12, v15, s1
v_xor_b32_e32 v12, v12, v14
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v12, v12, v14
s_branch .LBB0_8
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 336
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 28
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy, .Lfunc_end0-_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 8
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: hidden_block_count_x
- .offset: 84
.size: 4
.value_kind: hidden_block_count_y
- .offset: 88
.size: 4
.value_kind: hidden_block_count_z
- .offset: 92
.size: 2
.value_kind: hidden_group_size_x
- .offset: 94
.size: 2
.value_kind: hidden_group_size_y
- .offset: 96
.size: 2
.value_kind: hidden_group_size_z
- .offset: 98
.size: 2
.value_kind: hidden_remainder_x
- .offset: 100
.size: 2
.value_kind: hidden_remainder_y
- .offset: 102
.size: 2
.value_kind: hidden_remainder_z
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 144
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 336
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.private_segment_fixed_size: 0
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaUpdateActivity_kernel(int * inputs, char * activity, unsigned int * firingRate, unsigned int * exampleFiringRate, int * totalOutput, unsigned long long int * firstEventTime, unsigned long long int * lastEventTime, unsigned int inputsDimX, unsigned int inputsDimY, unsigned int inputsDimZ, unsigned int long long timestamp)
{
const unsigned int inputSize = inputsDimZ * inputsDimX * inputsDimY;
// One batch per block z dimension
const unsigned int batchInputOffset = blockIdx.z * inputSize;
for (unsigned int channel = blockIdx.x; channel < inputsDimZ; channel += gridDim.x) {
for (unsigned int y = threadIdx.y; y < inputsDimY; y += blockDim.y) {
for (unsigned int x = threadIdx.x; x < inputsDimX; x += blockDim.x) {
const unsigned int inputsIdx =
x + y*inputsDimX + channel*inputsDimX*inputsDimY;
int act = inputs[inputsIdx + batchInputOffset];
unsigned int actAbs = abs(act);
char spike = act == 0 ? 0 : act/abs(act);
activity[inputsIdx + batchInputOffset] = spike;
firingRate[inputsIdx + batchInputOffset] += actAbs;
exampleFiringRate[inputsIdx + batchInputOffset] += actAbs;
totalOutput[inputsIdx + batchInputOffset] += act;
}
}
}
} | .text
.file "cudaUpdateActivity_kernel.hip"
.globl _Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy # -- Begin function _Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.p2align 4, 0x90
.type _Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy,@function
_Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy: # @_Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy, .Lfunc_end0-_Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy,@object # @_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.section .rodata,"a",@progbits
.globl _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.p2align 3, 0x0
_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy:
.quad _Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.size _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x1a0], PT ; /* 0x000068000a007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e680000002100 */
/*0070*/ S2R R9, SR_CTAID.Z ; /* 0x0000000000097919 */
/* 0x000ea40000002700 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x19c], PT ; /* 0x0000670000007a0c */
/* 0x001fe20003f06070 */
/*0090*/ BSSY B0, 0x500 ; /* 0x0000046000007945 */
/* 0x000fd80003800000 */
/*00a0*/ @P0 BRA 0x4f0 ; /* 0x0000044000000947 */
/* 0x006fea0003800000 */
/*00b0*/ IMAD R11, R9, c[0x0][0x1a0], R10 ; /* 0x00006800090b7a24 */
/* 0x004fe400078e020a */
/*00c0*/ IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0000 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x198], PT ; /* 0x0000660008007a0c */
/* 0x002fe20003f06070 */
/*00e0*/ BSSY B1, 0x4c0 ; /* 0x000003d000017945 */
/* 0x000fd80003800000 */
/*00f0*/ @P0 BRA 0x4b0 ; /* 0x000003b000000947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD R3, R11, c[0x0][0x19c], R12 ; /* 0x000067000b037a24 */
/* 0x000fe400078e020c */
/*0110*/ IMAD.MOV.U32 R13, RZ, RZ, R8.reuse ; /* 0x000000ffff0d7224 */
/* 0x100fe400078e0008 */
/*0120*/ IMAD R14, R3, c[0x0][0x198], R8 ; /* 0x00006600030e7a24 */
/* 0x000fe400078e0208 */
/*0130*/ IMAD.MOV.U32 R19, RZ, RZ, 0x4 ; /* 0x00000004ff137424 */
/* 0x002fc800078e00ff */
/*0140*/ IMAD.WIDE.U32 R18, R14, R19, c[0x0][0x160] ; /* 0x000058000e127625 */
/* 0x000fcc00078e0013 */
/*0150*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea2000c1e1900 */
/*0160*/ IMAD.SHL.U32 R17, R14.reuse, 0x4, RZ ; /* 0x000000040e117824 */
/* 0x040fe200078e00ff */
/*0170*/ IADD3 R4, P1, R14, c[0x0][0x168], RZ ; /* 0x00005a000e047a10 */
/* 0x000fe20007f3e0ff */
/*0180*/ BSSY B2, 0x390 ; /* 0x0000020000027945 */
/* 0x000fe20003800000 */
/*0190*/ SHF.R.U32.HI R16, RZ, 0x1e, R14 ; /* 0x0000001eff107819 */
/* 0x000fe2000001160e */
/*01a0*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*01b0*/ IADD3 R2, P2, R17, c[0x0][0x170], RZ ; /* 0x00005c0011027a10 */
/* 0x000fe20007f5e0ff */
/*01c0*/ IMAD.X R5, RZ, RZ, c[0x0][0x16c], P1 ; /* 0x00005b00ff057624 */
/* 0x000fc600008e06ff */
/*01d0*/ IADD3.X R3, R16, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0010037a10 */
/* 0x000fe400017fe4ff */
/*01e0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x004fe40003f05270 */
/*01f0*/ IABS R15, R18 ; /* 0x00000012000f7213 */
/* 0x000fd60000000000 */
/*0200*/ @!P0 BRA 0x380 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0210*/ I2F.RP R19, R15 ; /* 0x0000000f00137306 */
/* 0x000e220000209400 */
/*0220*/ IABS R22, R18 ; /* 0x0000001200167213 */
/* 0x000fca0000000000 */
/*0230*/ IMAD.MOV R22, RZ, RZ, -R22 ; /* 0x000000ffff167224 */
/* 0x000fe400078e0a16 */
/*0240*/ MUFU.RCP R19, R19 ; /* 0x0000001300137308 */
/* 0x001e240000001000 */
/*0250*/ IADD3 R6, R19, 0xffffffe, RZ ; /* 0x0ffffffe13067810 */
/* 0x001fcc0007ffe0ff */
/*0260*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0270*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0280*/ IMAD.MOV R20, RZ, RZ, -R7 ; /* 0x000000ffff147224 */
/* 0x002fc800078e0a07 */
/*0290*/ IMAD R21, R20, R15, RZ ; /* 0x0000000f14157224 */
/* 0x000fc800078e02ff */
/*02a0*/ IMAD.HI.U32 R20, R7, R21, R6 ; /* 0x0000001507147227 */
/* 0x000fe200078e0006 */
/*02b0*/ LOP3.LUT R6, R18, R15, RZ, 0x3c, !PT ; /* 0x0000000f12067212 */
/* 0x000fc800078e3cff */
/*02c0*/ ISETP.GE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f26270 */
/*02d0*/ IMAD.HI.U32 R20, R20, R15, RZ ; /* 0x0000000f14147227 */
/* 0x000fc800078e00ff */
/*02e0*/ IMAD R22, R20, R22, R15 ; /* 0x0000001614167224 */
/* 0x000fca00078e020f */
/*02f0*/ ISETP.GT.U32.AND P2, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fda0003f44070 */
/*0300*/ @!P2 IMAD.IADD R22, R22, 0x1, -R15 ; /* 0x000000011616a824 */
/* 0x000fe200078e0a0f */
/*0310*/ @!P2 IADD3 R20, R20, 0x1, RZ ; /* 0x000000011414a810 */
/* 0x000fe40007ffe0ff */
/*0320*/ ISETP.NE.AND P2, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe40003f45270 */
/*0330*/ ISETP.GE.U32.AND P0, PT, R22, R15, PT ; /* 0x0000000f1600720c */
/* 0x000fda0003f06070 */
/*0340*/ @P0 IADD3 R20, R20, 0x1, RZ ; /* 0x0000000114140810 */
/* 0x000fca0007ffe0ff */
/*0350*/ @!P1 IMAD.MOV R20, RZ, RZ, -R20 ; /* 0x000000ffff149224 */
/* 0x000fe200078e0a14 */
/*0360*/ @!P2 LOP3.LUT R20, RZ, R15, RZ, 0x33, !PT ; /* 0x0000000fff14a212 */
/* 0x000fca00078e33ff */
/*0370*/ IMAD.MOV.U32 R23, RZ, RZ, R20 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0014 */
/*0380*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0390*/ STG.E.U8 [R4.64], R23 ; /* 0x0000001704007986 */
/* 0x0001e8000c101104 */
/*03a0*/ LDG.E R20, [R2.64] ; /* 0x0000000402147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IADD3 R6, P0, R17, c[0x0][0x178], RZ ; /* 0x00005e0011067a10 */
/* 0x000fc80007f1e0ff */
/*03c0*/ IADD3.X R7, R16, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0010077a10 */
/* 0x000fe200007fe4ff */
/*03d0*/ IMAD.IADD R19, R20, 0x1, R15 ; /* 0x0000000114137824 */
/* 0x004fca00078e020f */
/*03e0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*03f0*/ LDG.E R22, [R6.64] ; /* 0x0000000406167981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IADD3 R20, P0, R17, c[0x0][0x180], RZ ; /* 0x0000600011147a10 */
/* 0x000fc80007f1e0ff */
/*0410*/ IADD3.X R21, R16, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610010157a10 */
/* 0x000fe200007fe4ff */
/*0420*/ IMAD.IADD R15, R22, 0x1, R15 ; /* 0x00000001160f7824 */
/* 0x004fca00078e020f */
/*0430*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0003e8000c101904 */
/*0440*/ LDG.E R5, [R20.64] ; /* 0x0000000414057981 */
/* 0x001ea2000c1e1900 */
/*0450*/ IADD3 R13, R13, c[0x0][0x0], RZ ; /* 0x000000000d0d7a10 */
/* 0x000fe40007ffe0ff */
/*0460*/ IADD3 R14, R14, c[0x0][0x0], RZ ; /* 0x000000000e0e7a10 */
/* 0x000fe40007ffe0ff */
/*0470*/ ISETP.GE.U32.AND P0, PT, R13, c[0x0][0x198], PT ; /* 0x000066000d007a0c */
/* 0x000fe20003f06070 */
/*0480*/ IMAD.IADD R5, R18, 0x1, R5 ; /* 0x0000000112057824 */
/* 0x004fca00078e0205 */
/*0490*/ STG.E [R20.64], R5 ; /* 0x0000000514007986 */
/* 0x0003ee000c101904 */
/*04a0*/ @!P0 BRA 0x130 ; /* 0xfffffc8000008947 */
/* 0x000fea000383ffff */
/*04b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R12, R12, c[0x0][0x4], RZ ; /* 0x000001000c0c7a10 */
/* 0x000fc80007ffe0ff */
/*04d0*/ ISETP.GE.U32.AND P0, PT, R12, c[0x0][0x19c], PT ; /* 0x000067000c007a0c */
/* 0x000fda0003f06070 */
/*04e0*/ @!P0 BRA 0xd0 ; /* 0xfffffbe000008947 */
/* 0x000fea000383ffff */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ IADD3 R10, R10, c[0x0][0xc], RZ ; /* 0x000003000a0a7a10 */
/* 0x000fc80007ffe0ff */
/*0510*/ ISETP.GE.U32.AND P0, PT, R10, c[0x0][0x1a0], PT ; /* 0x000068000a007a0c */
/* 0x000fda0003f06070 */
/*0520*/ @!P0 BRA 0x80 ; /* 0xfffffb5000008947 */
/* 0x000fea000383ffff */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.globl _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.p2align 8
.type _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy,@function
_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy:
s_load_b32 s18, s[0:1], 0x40
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s14, s18
s_cbranch_scc1 .LBB0_11
s_clause 0x3
s_load_b64 s[2:3], s[0:1], 0x38
s_load_b64 s[12:13], s[0:1], 0x20
s_load_b32 s19, s[0:1], 0x50
s_load_b256 s[4:11], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
s_mul_i32 s15, s15, s18
s_add_u32 s16, s0, 0x50
s_addc_u32 s17, s1, 0
s_add_i32 s0, s14, s15
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s3, s0, v[1:2]
v_mov_b32_e32 v3, 0
v_cmp_gt_u32_e32 vcc_lo, s3, v1
v_cmp_gt_u32_e64 s0, s2, v0
s_mul_i32 s15, s19, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
s_mul_i32 s15, s15, s2
v_mul_lo_u32 v6, s2, v2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v6, s15, v6
s_add_i32 s14, s19, s14
s_cmp_ge_u32 s14, s18
s_cbranch_scc1 .LBB0_11
.LBB0_3:
s_and_saveexec_b32 s20, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s1, s[16:17], 0xc
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v8, v1
s_mov_b32 s23, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s21, s1, 16
s_mul_i32 s22, s2, s21
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s24
v_add_nc_u32_e32 v8, s21, v8
v_add_nc_u32_e32 v7, s22, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s1, s3, v8
s_or_b32 s23, s1, s23
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execz .LBB0_2
.LBB0_6:
s_and_saveexec_b32 s24, s0
s_cbranch_execz .LBB0_5
s_load_b32 s1, s[16:17], 0xc
v_mov_b32_e32 v9, v0
s_mov_b32 s26, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s25, s1, 0xffff
s_branch .LBB0_9
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s27
v_add_co_u32 v13, s1, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s1, s7, v3, s1
v_add_co_u32 v15, s1, s8, v4
v_add_co_ci_u32_e64 v16, s1, s9, v5, s1
global_store_b8 v[13:14], v12, off
v_add_co_u32 v12, s1, s10, v4
global_load_b32 v2, v[15:16], off
v_add_co_ci_u32_e64 v13, s1, s11, v5, s1
v_add_co_u32 v4, s1, s12, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s1, s13, v5, s1
v_add_nc_u32_e32 v9, s25, v9
v_cmp_le_u32_e64 s1, s2, v9
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s26, s1, s26
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v11
global_store_b32 v[15:16], v2, off
global_load_b32 v2, v[12:13], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v11
global_store_b32 v[12:13], v2, off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v10
global_store_b32 v[4:5], v2, off
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execz .LBB0_5
.LBB0_9:
v_add_nc_u32_e32 v2, v7, v9
v_mov_b32_e32 v12, 0
s_mov_b32 s27, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_co_u32 v10, s1, s4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s1, s5, v5, s1
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v11, 0, v10
v_max_i32_e32 v11, v10, v11
v_cmpx_ne_u32_e32 0, v10
s_cbranch_execz .LBB0_8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_f32_u32_e32 v12, v11
v_ashrrev_i32_e32 v14, 31, v10
v_sub_nc_u32_e32 v13, 0, v11
v_rcp_iflag_f32_e32 v12, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v15, v10, v14
v_xor_b32_e32 v15, v15, v14
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, 0x4f7ffffe, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v12, v12
v_mul_lo_u32 v13, v13, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v13, v12, v13
v_add_nc_u32_e32 v12, v12, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v12, v15, v12
v_mul_lo_u32 v13, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v13, v15, v13
v_add_nc_u32_e32 v15, 1, v12
v_sub_nc_u32_e32 v16, v13, v11
v_cmp_ge_u32_e64 s1, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v12, v12, v15, s1
v_cndmask_b32_e64 v13, v13, v16, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, 1, v12
v_cmp_ge_u32_e64 s1, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v12, v12, v15, s1
v_xor_b32_e32 v12, v12, v14
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v12, v12, v14
s_branch .LBB0_8
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 336
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 28
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy, .Lfunc_end0-_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 72
.size: 8
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: hidden_block_count_x
- .offset: 84
.size: 4
.value_kind: hidden_block_count_y
- .offset: 88
.size: 4
.value_kind: hidden_block_count_z
- .offset: 92
.size: 2
.value_kind: hidden_group_size_x
- .offset: 94
.size: 2
.value_kind: hidden_group_size_y
- .offset: 96
.size: 2
.value_kind: hidden_group_size_z
- .offset: 98
.size: 2
.value_kind: hidden_remainder_x
- .offset: 100
.size: 2
.value_kind: hidden_remainder_y
- .offset: 102
.size: 2
.value_kind: hidden_remainder_z
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 144
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 336
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.private_segment_fixed_size: 0
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00152f89_00000000-6_cudaUpdateActivity_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z63__device_stub__Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjyPiPcPjS1_S_PyS2_jjjy
.type _Z63__device_stub__Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjyPiPcPjS1_S_PyS2_jjjy, @function
_Z63__device_stub__Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjyPiPcPjS1_S_PyS2_jjjy:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 272(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z63__device_stub__Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjyPiPcPjS1_S_PyS2_jjjy, .-_Z63__device_stub__Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjyPiPcPjS1_S_PyS2_jjjy
.globl _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.type _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy, @function
_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z63__device_stub__Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjyPiPcPjS1_S_PyS2_jjjy
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy, .-_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaUpdateActivity_kernel.hip"
.globl _Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy # -- Begin function _Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.p2align 4, 0x90
.type _Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy,@function
_Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy: # @_Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy, .Lfunc_end0-_Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy,@object # @_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.section .rodata,"a",@progbits
.globl _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.p2align 3, 0x0
_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy:
.quad _Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.size _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25cudaUpdateActivity_kernelPiPcPjS1_S_PyS2_jjjy
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #pragma unmanaged
#include <iostream>
#include <cuda_runtime.h>
// Define this to turn on error checking
//#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__, deviceID )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__, deviceID )
__host__ inline void __cudaSafeCall(cudaError err, const char *file, const int line, int deviceID)
{
#ifdef CUDA_ERROR_CHECK
if (cudaSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error in file '" << file
<< "' in line " << line
<< " : " << cudaGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
#endif
return;
}
__host__ inline void __cudaCheckError(const char *file, const int line, int deviceID)
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if (cudaSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error in file '" << file
<< "' in line " << line
<< " : " << cudaGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if (cudaSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error after sync in file '" << file
<< "' in line " << line
<< " : " << cudaGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
#endif
return;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #pragma unmanaged
#include <iostream>
#include <cuda_runtime.h>
// Define this to turn on error checking
//#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__, deviceID )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__, deviceID )
__host__ inline void __cudaSafeCall(cudaError err, const char *file, const int line, int deviceID)
{
#ifdef CUDA_ERROR_CHECK
if (cudaSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error in file '" << file
<< "' in line " << line
<< " : " << cudaGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
#endif
return;
}
__host__ inline void __cudaCheckError(const char *file, const int line, int deviceID)
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if (cudaSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error in file '" << file
<< "' in line " << line
<< " : " << cudaGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if (cudaSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error after sync in file '" << file
<< "' in line " << line
<< " : " << cudaGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
#endif
return;
} | .file "tmpxft_00027cec_00000000-6_cudaErrorCheck.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #pragma unmanaged
#include <iostream>
#include <cuda_runtime.h>
// Define this to turn on error checking
//#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__, deviceID )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__, deviceID )
__host__ inline void __cudaSafeCall(cudaError err, const char *file, const int line, int deviceID)
{
#ifdef CUDA_ERROR_CHECK
if (cudaSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error in file '" << file
<< "' in line " << line
<< " : " << cudaGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
#endif
return;
}
__host__ inline void __cudaCheckError(const char *file, const int line, int deviceID)
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if (cudaSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error in file '" << file
<< "' in line " << line
<< " : " << cudaGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if (cudaSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error after sync in file '" << file
<< "' in line " << line
<< " : " << cudaGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
#endif
return;
} | #pragma unmanaged
#include <iostream>
#include <hip/hip_runtime.h>
// Define this to turn on error checking
//#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__, deviceID )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__, deviceID )
__host__ inline void __cudaSafeCall(hipError_t err, const char *file, const int line, int deviceID)
{
#ifdef CUDA_ERROR_CHECK
if (hipSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error in file '" << file
<< "' in line " << line
<< " : " << hipGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
#endif
return;
}
__host__ inline void __cudaCheckError(const char *file, const int line, int deviceID)
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if (hipSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error in file '" << file
<< "' in line " << line
<< " : " << hipGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if (hipSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error after sync in file '" << file
<< "' in line " << line
<< " : " << hipGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
#endif
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma unmanaged
#include <iostream>
#include <hip/hip_runtime.h>
// Define this to turn on error checking
//#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__, deviceID )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__, deviceID )
__host__ inline void __cudaSafeCall(hipError_t err, const char *file, const int line, int deviceID)
{
#ifdef CUDA_ERROR_CHECK
if (hipSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error in file '" << file
<< "' in line " << line
<< " : " << hipGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
#endif
return;
}
__host__ inline void __cudaCheckError(const char *file, const int line, int deviceID)
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if (hipSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error in file '" << file
<< "' in line " << line
<< " : " << hipGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if (hipSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error after sync in file '" << file
<< "' in line " << line
<< " : " << hipGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
#endif
return;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma unmanaged
#include <iostream>
#include <hip/hip_runtime.h>
// Define this to turn on error checking
//#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__, deviceID )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__, deviceID )
__host__ inline void __cudaSafeCall(hipError_t err, const char *file, const int line, int deviceID)
{
#ifdef CUDA_ERROR_CHECK
if (hipSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error in file '" << file
<< "' in line " << line
<< " : " << hipGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
#endif
return;
}
__host__ inline void __cudaCheckError(const char *file, const int line, int deviceID)
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if (hipSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error in file '" << file
<< "' in line " << line
<< " : " << hipGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if (hipSuccess != err)
{
std::cerr << "\nCUDA device ID: " << deviceID
<< " encountered an error after sync in file '" << file
<< "' in line " << line
<< " : " << hipGetErrorString(err) << ".\n";
exit(EXIT_FAILURE);
}
#endif
return;
} | .text
.file "cudaErrorCheck.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00027cec_00000000-6_cudaErrorCheck.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaErrorCheck.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <iostream>
#include <stdio.h>
#define N 1024
int a[N][N],b[N][N],c[N][N];
using namespace std;
__global__ void addMatrix(int a[][N], int b[][N], int c[][N], int n){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row<n && col<n)
c[row][col] = a[row][col] + b[row][col];
}
void random_int(int a[][N], int n)
{
int i,j;
for (i = 0; i < n; ++i)
for (j = 0; j < n; ++j)
a[i][j] = rand() % 101;
}
int main(void)
{
int (*pA)[N], (*pB)[N], (*pC)[N];
random_int(a,N);
random_int(b,N);
cudaMalloc((void**)&pA, (N*N)*sizeof(int));
cudaMalloc((void**)&pB, (N*N)*sizeof(int));
cudaMalloc((void**)&pC, (N*N)*sizeof(int));
cudaMemcpy(pA, a, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(pB, b, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(pC, c, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
dim3 dimBlock(64, 64);
dim3 dimGrid(N/dimBlock.x, N/dimBlock.y);
addMatrix<<<dimGrid,dimBlock>>>(pA,pB,pC,N);
cudaMemcpy(c, pC, (N*N)*sizeof(int), cudaMemcpyDeviceToHost);
int i, j;
/*
printf("C = \n");
for(i=0;i<N;i++){
for(j=0;j<N;j++){
printf("%d ", c[i][j]);
}
printf("\n");
}
*/
cudaFree(pA);
cudaFree(pB);
cudaFree(pC);
printf("\n");
return 0;
} | code for sm_80
Function : _Z9addMatrixPA1024_iS0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x178], PT ; /* 0x00005e0009007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R6, R6, c[0x0][0x4], R3 ; /* 0x0000010006067a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x178], P0 ; /* 0x00005e0006007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0.00048828125 ; /* 0x00001000ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00c0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R9, 0x4, R2 ; /* 0x0000000409027825 */
/* 0x000fc800078e0202 */
/*00f0*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe400078e0204 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fcc00078e0207 */
/*0130*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fe200078e0206 */
/*0140*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <iostream>
#include <stdio.h>
#define N 1024
int a[N][N],b[N][N],c[N][N];
using namespace std;
__global__ void addMatrix(int a[][N], int b[][N], int c[][N], int n){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row<n && col<n)
c[row][col] = a[row][col] + b[row][col];
}
void random_int(int a[][N], int n)
{
int i,j;
for (i = 0; i < n; ++i)
for (j = 0; j < n; ++j)
a[i][j] = rand() % 101;
}
int main(void)
{
int (*pA)[N], (*pB)[N], (*pC)[N];
random_int(a,N);
random_int(b,N);
cudaMalloc((void**)&pA, (N*N)*sizeof(int));
cudaMalloc((void**)&pB, (N*N)*sizeof(int));
cudaMalloc((void**)&pC, (N*N)*sizeof(int));
cudaMemcpy(pA, a, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(pB, b, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(pC, c, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
dim3 dimBlock(64, 64);
dim3 dimGrid(N/dimBlock.x, N/dimBlock.y);
addMatrix<<<dimGrid,dimBlock>>>(pA,pB,pC,N);
cudaMemcpy(c, pC, (N*N)*sizeof(int), cudaMemcpyDeviceToHost);
int i, j;
/*
printf("C = \n");
for(i=0;i<N;i++){
for(j=0;j<N;j++){
printf("%d ", c[i][j]);
}
printf("\n");
}
*/
cudaFree(pA);
cudaFree(pB);
cudaFree(pC);
printf("\n");
return 0;
} | .file "tmpxft_0003c9f9_00000000-6_q4.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10random_intPA1024_ii
.type _Z10random_intPA1024_ii, @function
_Z10random_intPA1024_ii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L9
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movslq %esi, %r12
leaq (%rdi,%r12,4), %rbp
movq %r12, %rax
salq $10, %rax
addq %r12, %rax
leaq (%rdi,%rax,4), %r13
negq %r12
salq $2, %r12
.L5:
leaq 0(%rbp,%r12), %rbx
.L6:
call rand@PLT
movslq %eax, %rdx
imulq $680390859, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $101, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
addq $4096, %rbp
cmpq %r13, %rbp
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE3669:
.size _Z10random_intPA1024_ii, .-_Z10random_intPA1024_ii
.globl _Z41__device_stub__Z9addMatrixPA1024_iS0_S0_iPA1024_iS0_S0_i
.type _Z41__device_stub__Z9addMatrixPA1024_iS0_S0_iPA1024_iS0_S0_i, @function
_Z41__device_stub__Z9addMatrixPA1024_iS0_S0_iPA1024_iS0_S0_i:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addMatrixPA1024_iS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z41__device_stub__Z9addMatrixPA1024_iS0_S0_iPA1024_iS0_S0_i, .-_Z41__device_stub__Z9addMatrixPA1024_iS0_S0_iPA1024_iS0_S0_i
.globl _Z9addMatrixPA1024_iS0_S0_i
.type _Z9addMatrixPA1024_iS0_S0_i, @function
_Z9addMatrixPA1024_iS0_S0_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z9addMatrixPA1024_iS0_S0_iPA1024_iS0_S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9addMatrixPA1024_iS0_S0_i, .-_Z9addMatrixPA1024_iS0_S0_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1024, %esi
leaq a(%rip), %rbp
movq %rbp, %rdi
call _Z10random_intPA1024_ii
movl $1024, %esi
leaq b(%rip), %rbx
movq %rbx, %rdi
call _Z10random_intPA1024_ii
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
leaq c(%rip), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $64, 32(%rsp)
movl $64, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
leaq c(%rip), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z41__device_stub__Z9addMatrixPA1024_iS0_S0_iPA1024_iS0_S0_i
jmp .L21
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9addMatrixPA1024_iS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addMatrixPA1024_iS0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl c
.bss
.align 32
.type c, @object
.size c, 4194304
c:
.zero 4194304
.globl b
.align 32
.type b, @object
.size b, 4194304
b:
.zero 4194304
.globl a
.align 32
.type a, @object
.size a, 4194304
a:
.zero 4194304
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <iostream>
#include <stdio.h>
#define N 1024
int a[N][N],b[N][N],c[N][N];
using namespace std;
__global__ void addMatrix(int a[][N], int b[][N], int c[][N], int n){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row<n && col<n)
c[row][col] = a[row][col] + b[row][col];
}
void random_int(int a[][N], int n)
{
int i,j;
for (i = 0; i < n; ++i)
for (j = 0; j < n; ++j)
a[i][j] = rand() % 101;
}
int main(void)
{
int (*pA)[N], (*pB)[N], (*pC)[N];
random_int(a,N);
random_int(b,N);
cudaMalloc((void**)&pA, (N*N)*sizeof(int));
cudaMalloc((void**)&pB, (N*N)*sizeof(int));
cudaMalloc((void**)&pC, (N*N)*sizeof(int));
cudaMemcpy(pA, a, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(pB, b, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(pC, c, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
dim3 dimBlock(64, 64);
dim3 dimGrid(N/dimBlock.x, N/dimBlock.y);
addMatrix<<<dimGrid,dimBlock>>>(pA,pB,pC,N);
cudaMemcpy(c, pC, (N*N)*sizeof(int), cudaMemcpyDeviceToHost);
int i, j;
/*
printf("C = \n");
for(i=0;i<N;i++){
for(j=0;j<N;j++){
printf("%d ", c[i][j]);
}
printf("\n");
}
*/
cudaFree(pA);
cudaFree(pB);
cudaFree(pC);
printf("\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#define N 1024
int a[N][N],b[N][N],c[N][N];
using namespace std;
__global__ void addMatrix(int a[][N], int b[][N], int c[][N], int n){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row<n && col<n)
c[row][col] = a[row][col] + b[row][col];
}
void random_int(int a[][N], int n)
{
int i,j;
for (i = 0; i < n; ++i)
for (j = 0; j < n; ++j)
a[i][j] = rand() % 101;
}
int main(void)
{
int (*pA)[N], (*pB)[N], (*pC)[N];
random_int(a,N);
random_int(b,N);
hipMalloc((void**)&pA, (N*N)*sizeof(int));
hipMalloc((void**)&pB, (N*N)*sizeof(int));
hipMalloc((void**)&pC, (N*N)*sizeof(int));
hipMemcpy(pA, a, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(pB, b, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(pC, c, (N*N)*sizeof(int), hipMemcpyHostToDevice);
dim3 dimBlock(64, 64);
dim3 dimGrid(N/dimBlock.x, N/dimBlock.y);
addMatrix<<<dimGrid,dimBlock>>>(pA,pB,pC,N);
hipMemcpy(c, pC, (N*N)*sizeof(int), hipMemcpyDeviceToHost);
int i, j;
/*
printf("C = \n");
for(i=0;i<N;i++){
for(j=0;j<N;j++){
printf("%d ", c[i][j]);
}
printf("\n");
}
*/
hipFree(pA);
hipFree(pB);
hipFree(pC);
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#define N 1024
int a[N][N],b[N][N],c[N][N];
using namespace std;
__global__ void addMatrix(int a[][N], int b[][N], int c[][N], int n){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row<n && col<n)
c[row][col] = a[row][col] + b[row][col];
}
void random_int(int a[][N], int n)
{
int i,j;
for (i = 0; i < n; ++i)
for (j = 0; j < n; ++j)
a[i][j] = rand() % 101;
}
int main(void)
{
int (*pA)[N], (*pB)[N], (*pC)[N];
random_int(a,N);
random_int(b,N);
hipMalloc((void**)&pA, (N*N)*sizeof(int));
hipMalloc((void**)&pB, (N*N)*sizeof(int));
hipMalloc((void**)&pC, (N*N)*sizeof(int));
hipMemcpy(pA, a, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(pB, b, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(pC, c, (N*N)*sizeof(int), hipMemcpyHostToDevice);
dim3 dimBlock(64, 64);
dim3 dimGrid(N/dimBlock.x, N/dimBlock.y);
addMatrix<<<dimGrid,dimBlock>>>(pA,pB,pC,N);
hipMemcpy(c, pC, (N*N)*sizeof(int), hipMemcpyDeviceToHost);
int i, j;
/*
printf("C = \n");
for(i=0;i<N;i++){
for(j=0;j<N;j++){
printf("%d ", c[i][j]);
}
printf("\n");
}
*/
hipFree(pA);
hipFree(pB);
hipFree(pC);
printf("\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addMatrixPA1024_iS0_S0_i
.globl _Z9addMatrixPA1024_iS0_S0_i
.p2align 8
.type _Z9addMatrixPA1024_iS0_S0_i,@function
_Z9addMatrixPA1024_iS0_S0_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v0, v2
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 12, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, v4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, v6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addMatrixPA1024_iS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addMatrixPA1024_iS0_S0_i, .Lfunc_end0-_Z9addMatrixPA1024_iS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addMatrixPA1024_iS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addMatrixPA1024_iS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#define N 1024
int a[N][N],b[N][N],c[N][N];
using namespace std;
__global__ void addMatrix(int a[][N], int b[][N], int c[][N], int n){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row<n && col<n)
c[row][col] = a[row][col] + b[row][col];
}
void random_int(int a[][N], int n)
{
int i,j;
for (i = 0; i < n; ++i)
for (j = 0; j < n; ++j)
a[i][j] = rand() % 101;
}
int main(void)
{
int (*pA)[N], (*pB)[N], (*pC)[N];
random_int(a,N);
random_int(b,N);
hipMalloc((void**)&pA, (N*N)*sizeof(int));
hipMalloc((void**)&pB, (N*N)*sizeof(int));
hipMalloc((void**)&pC, (N*N)*sizeof(int));
hipMemcpy(pA, a, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(pB, b, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(pC, c, (N*N)*sizeof(int), hipMemcpyHostToDevice);
dim3 dimBlock(64, 64);
dim3 dimGrid(N/dimBlock.x, N/dimBlock.y);
addMatrix<<<dimGrid,dimBlock>>>(pA,pB,pC,N);
hipMemcpy(c, pC, (N*N)*sizeof(int), hipMemcpyDeviceToHost);
int i, j;
/*
printf("C = \n");
for(i=0;i<N;i++){
for(j=0;j<N;j++){
printf("%d ", c[i][j]);
}
printf("\n");
}
*/
hipFree(pA);
hipFree(pB);
hipFree(pC);
printf("\n");
return 0;
} | .text
.file "q4.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__addMatrixPA1024_iS0_S0_i # -- Begin function _Z24__device_stub__addMatrixPA1024_iS0_S0_i
.p2align 4, 0x90
.type _Z24__device_stub__addMatrixPA1024_iS0_S0_i,@function
_Z24__device_stub__addMatrixPA1024_iS0_S0_i: # @_Z24__device_stub__addMatrixPA1024_iS0_S0_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addMatrixPA1024_iS0_S0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__addMatrixPA1024_iS0_S0_i, .Lfunc_end0-_Z24__device_stub__addMatrixPA1024_iS0_S0_i
.cfi_endproc
# -- End function
.globl _Z10random_intPA1024_ii # -- Begin function _Z10random_intPA1024_ii
.p2align 4, 0x90
.type _Z10random_intPA1024_ii,@function
_Z10random_intPA1024_ii: # @_Z10random_intPA1024_ii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $680390859, %rax, %rcx # imm = 0x288DF0CB
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $101, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq %r12, %r14
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r15
addq $4096, %rbx # imm = 0x1000
cmpq %r14, %r15
jne .LBB1_2
# %bb.5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_6: # %._crit_edge12
retq
.Lfunc_end1:
.size _Z10random_intPA1024_ii, .Lfunc_end1-_Z10random_intPA1024_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $a, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $680390859, %rax, %rcx # imm = 0x288DF0CB
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $101, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB2_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB2_1 Depth=1
incq %r14
addq $4096, %rbx # imm = 0x1000
cmpq $1024, %r14 # imm = 0x400
jne .LBB2_1
# %bb.4: # %.preheader.i7.preheader
movl $b, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_5: # %.preheader.i7
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $680390859, %rax, %rcx # imm = 0x288DF0CB
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $101, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB2_6
# %bb.7: # %._crit_edge.i12
# in Loop: Header=BB2_5 Depth=1
incq %r14
addq $4096, %rbx # imm = 0x1000
cmpq $1024, %r14 # imm = 0x400
jne .LBB2_5
# %bb.8: # %_Z10random_intPA1024_ii.exit15
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 24(%rsp), %rdi
movl $a, %esi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $b, %esi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $c, %esi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
movabsq $68719476752, %rdi # imm = 0x1000000010
movabsq $274877907008, %rdx # imm = 0x4000000040
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 36(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9addMatrixPA1024_iS0_S0_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq 8(%rsp), %rsi
movl $c, %edi
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addMatrixPA1024_iS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type a,@object # @a
.bss
.globl a
.p2align 4, 0x0
a:
.zero 4194304
.size a, 4194304
.type b,@object # @b
.globl b
.p2align 4, 0x0
b:
.zero 4194304
.size b, 4194304
.type c,@object # @c
.globl c
.p2align 4, 0x0
c:
.zero 4194304
.size c, 4194304
.type _Z9addMatrixPA1024_iS0_S0_i,@object # @_Z9addMatrixPA1024_iS0_S0_i
.section .rodata,"a",@progbits
.globl _Z9addMatrixPA1024_iS0_S0_i
.p2align 3, 0x0
_Z9addMatrixPA1024_iS0_S0_i:
.quad _Z24__device_stub__addMatrixPA1024_iS0_S0_i
.size _Z9addMatrixPA1024_iS0_S0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9addMatrixPA1024_iS0_S0_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addMatrixPA1024_iS0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym a
.addrsig_sym b
.addrsig_sym c
.addrsig_sym _Z9addMatrixPA1024_iS0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addMatrixPA1024_iS0_S0_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x178], PT ; /* 0x00005e0009007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R6, R6, c[0x0][0x4], R3 ; /* 0x0000010006067a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x178], P0 ; /* 0x00005e0006007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0.00048828125 ; /* 0x00001000ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00c0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R9, 0x4, R2 ; /* 0x0000000409027825 */
/* 0x000fc800078e0202 */
/*00f0*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe400078e0204 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fcc00078e0207 */
/*0130*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fe200078e0206 */
/*0140*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addMatrixPA1024_iS0_S0_i
.globl _Z9addMatrixPA1024_iS0_S0_i
.p2align 8
.type _Z9addMatrixPA1024_iS0_S0_i,@function
_Z9addMatrixPA1024_iS0_S0_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v0, v2
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 12, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, v4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, v6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addMatrixPA1024_iS0_S0_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addMatrixPA1024_iS0_S0_i, .Lfunc_end0-_Z9addMatrixPA1024_iS0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addMatrixPA1024_iS0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addMatrixPA1024_iS0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003c9f9_00000000-6_q4.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10random_intPA1024_ii
.type _Z10random_intPA1024_ii, @function
_Z10random_intPA1024_ii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L9
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movslq %esi, %r12
leaq (%rdi,%r12,4), %rbp
movq %r12, %rax
salq $10, %rax
addq %r12, %rax
leaq (%rdi,%rax,4), %r13
negq %r12
salq $2, %r12
.L5:
leaq 0(%rbp,%r12), %rbx
.L6:
call rand@PLT
movslq %eax, %rdx
imulq $680390859, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $101, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
addq $4096, %rbp
cmpq %r13, %rbp
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE3669:
.size _Z10random_intPA1024_ii, .-_Z10random_intPA1024_ii
.globl _Z41__device_stub__Z9addMatrixPA1024_iS0_S0_iPA1024_iS0_S0_i
.type _Z41__device_stub__Z9addMatrixPA1024_iS0_S0_iPA1024_iS0_S0_i, @function
_Z41__device_stub__Z9addMatrixPA1024_iS0_S0_iPA1024_iS0_S0_i:
.LFB3695:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addMatrixPA1024_iS0_S0_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z41__device_stub__Z9addMatrixPA1024_iS0_S0_iPA1024_iS0_S0_i, .-_Z41__device_stub__Z9addMatrixPA1024_iS0_S0_iPA1024_iS0_S0_i
.globl _Z9addMatrixPA1024_iS0_S0_i
.type _Z9addMatrixPA1024_iS0_S0_i, @function
_Z9addMatrixPA1024_iS0_S0_i:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z9addMatrixPA1024_iS0_S0_iPA1024_iS0_S0_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9addMatrixPA1024_iS0_S0_i, .-_Z9addMatrixPA1024_iS0_S0_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1024, %esi
leaq a(%rip), %rbp
movq %rbp, %rdi
call _Z10random_intPA1024_ii
movl $1024, %esi
leaq b(%rip), %rbx
movq %rbx, %rdi
call _Z10random_intPA1024_ii
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
leaq c(%rip), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $64, 32(%rsp)
movl $64, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
leaq c(%rip), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z41__device_stub__Z9addMatrixPA1024_iS0_S0_iPA1024_iS0_S0_i
jmp .L21
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9addMatrixPA1024_iS0_S0_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addMatrixPA1024_iS0_S0_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl c
.bss
.align 32
.type c, @object
.size c, 4194304
c:
.zero 4194304
.globl b
.align 32
.type b, @object
.size b, 4194304
b:
.zero 4194304
.globl a
.align 32
.type a, @object
.size a, 4194304
a:
.zero 4194304
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q4.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__addMatrixPA1024_iS0_S0_i # -- Begin function _Z24__device_stub__addMatrixPA1024_iS0_S0_i
.p2align 4, 0x90
.type _Z24__device_stub__addMatrixPA1024_iS0_S0_i,@function
_Z24__device_stub__addMatrixPA1024_iS0_S0_i: # @_Z24__device_stub__addMatrixPA1024_iS0_S0_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addMatrixPA1024_iS0_S0_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__addMatrixPA1024_iS0_S0_i, .Lfunc_end0-_Z24__device_stub__addMatrixPA1024_iS0_S0_i
.cfi_endproc
# -- End function
.globl _Z10random_intPA1024_ii # -- Begin function _Z10random_intPA1024_ii
.p2align 4, 0x90
.type _Z10random_intPA1024_ii,@function
_Z10random_intPA1024_ii: # @_Z10random_intPA1024_ii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $680390859, %rax, %rcx # imm = 0x288DF0CB
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $101, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq %r12, %r14
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r15
addq $4096, %rbx # imm = 0x1000
cmpq %r14, %r15
jne .LBB1_2
# %bb.5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_6: # %._crit_edge12
retq
.Lfunc_end1:
.size _Z10random_intPA1024_ii, .Lfunc_end1-_Z10random_intPA1024_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $a, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $680390859, %rax, %rcx # imm = 0x288DF0CB
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $101, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB2_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB2_1 Depth=1
incq %r14
addq $4096, %rbx # imm = 0x1000
cmpq $1024, %r14 # imm = 0x400
jne .LBB2_1
# %bb.4: # %.preheader.i7.preheader
movl $b, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_5: # %.preheader.i7
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $680390859, %rax, %rcx # imm = 0x288DF0CB
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $101, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB2_6
# %bb.7: # %._crit_edge.i12
# in Loop: Header=BB2_5 Depth=1
incq %r14
addq $4096, %rbx # imm = 0x1000
cmpq $1024, %r14 # imm = 0x400
jne .LBB2_5
# %bb.8: # %_Z10random_intPA1024_ii.exit15
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 24(%rsp), %rdi
movl $a, %esi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $b, %esi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $c, %esi
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpy
movabsq $68719476752, %rdi # imm = 0x1000000010
movabsq $274877907008, %rdx # imm = 0x4000000040
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 36(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9addMatrixPA1024_iS0_S0_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq 8(%rsp), %rsi
movl $c, %edi
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addMatrixPA1024_iS0_S0_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type a,@object # @a
.bss
.globl a
.p2align 4, 0x0
a:
.zero 4194304
.size a, 4194304
.type b,@object # @b
.globl b
.p2align 4, 0x0
b:
.zero 4194304
.size b, 4194304
.type c,@object # @c
.globl c
.p2align 4, 0x0
c:
.zero 4194304
.size c, 4194304
.type _Z9addMatrixPA1024_iS0_S0_i,@object # @_Z9addMatrixPA1024_iS0_S0_i
.section .rodata,"a",@progbits
.globl _Z9addMatrixPA1024_iS0_S0_i
.p2align 3, 0x0
_Z9addMatrixPA1024_iS0_S0_i:
.quad _Z24__device_stub__addMatrixPA1024_iS0_S0_i
.size _Z9addMatrixPA1024_iS0_S0_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9addMatrixPA1024_iS0_S0_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addMatrixPA1024_iS0_S0_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym a
.addrsig_sym b
.addrsig_sym c
.addrsig_sym _Z9addMatrixPA1024_iS0_S0_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include <cuda.h>
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; ++i)
a[i] = rand()%20000;
}
void add_array(int* a, int N)
{
for (int i = 0; i < N; ++i)
a[i] =i;
}
__global__ void binary_search(int* a, int* b, bool* c, int sizeofa) //kernal function
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
printf(" %d\n", index);
int key = b[index];
int min = 0, max = sizeofa;
int mid = sizeofa / 2;
while (min != mid)
{
if (key == a[mid])
{
break;
}
else if (key < a[mid])
{
min = min;
max = mid;
}
else {
min = mid;
max = max;
}
mid = (min + max) / 2;
}
if (key == a[mid])
c[index] = true;
else
c[index] = false;
printf(" %d %d %d %d\n", index, key, a[mid],c[index]);
}
int main()
{
int N = 10000; //size of given array
int M = 1000; //Number of searching element
size_t size = N * sizeof(int);
size_t size2 = M * sizeof(int);
//allocate memory for host array
int* vector1 = (int*)malloc(size);
int* vector2 = (int*)malloc(size2);
bool* vector3 = (bool*)malloc(M * sizeof(bool));
//insert number into array
add_array(vector1,N);
//insert random elements to search
random_ints(vector2,M);
//create device array pointer
int *d_vector1;
int *d_vector2;
bool *d_vector3;
//allocate device memory for vector
cudaMalloc(& d_vector1, size);
cudaMalloc(& d_vector2, size2);
cudaMalloc(& d_vector3, M*sizeof(bool));
//copy vectors from host memory to dvice memory
cudaMemcpy(d_vector1,vector1, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_vector2,vector2, size2, cudaMemcpyHostToDevice);
//call kernal
binary_search<<<M,1>>>(d_vector1, d_vector2, d_vector3,N);
cudaMemcpy(vector3,d_vector3, M * sizeof(bool), cudaMemcpyDeviceToHost);
for (int i = 0; i < M; i++)
{
if(vector3[i]==true)
printf("%d is present in array\n",vector2[i]);
else if(vector3[i] == 0)
printf("%d is not present in array\n", vector2[i]);
}
} | code for sm_80
Function : _Z13binary_searchPiS_Pbi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R16, SR_CTAID.X ; /* 0x0000000000107919 */
/* 0x000e220000002500 */
/*0020*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0080*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0090*/ IADD3 R22, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001167a10 */
/* 0x000fe20007f1e0ff */
/*00a0*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff127624 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.X R2, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff027624 */
/* 0x000fe400000e06ff */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, R22 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0016 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0002 */
/*00e0*/ IMAD R16, R16, c[0x0][0x0], R3 ; /* 0x0000000010107a24 */
/* 0x001fca00078e0203 */
/*00f0*/ STL [R1], R16 ; /* 0x0000001001007387 */
/* 0x0001e40000100800 */
/*0100*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe20000000000 */
/*0110*/ MOV R3, 0x180 ; /* 0x0000018000037802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R20, 0x100 ; /* 0x0000010000147802 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0150*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0160*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0170*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x001fea0003c00000 */
/*0180*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE R4, R16, R11, c[0x0][0x168] ; /* 0x00005a0010047625 */
/* 0x000fca00078e020b */
/*01a0*/ LDG.E R17, [R4.64] ; /* 0x0000002404117981 */
/* 0x000162000c1e1900 */
/*01b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff037624 */
/* 0x000fca00078e00ff */
/*01c0*/ IADD3 R0, R3, 0x1, RZ ; /* 0x0000000103007810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*01e0*/ LEA.HI R0, R3, c[0x0][0x178], RZ, 0x1 ; /* 0x00005e0003007a11 */
/* 0x000fc800078f08ff */
/*01f0*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fce0000011400 */
/*0200*/ @!P0 BRA 0x320 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0210*/ BSSY B0, 0x320 ; /* 0x0000010000007945 */
/* 0x001fe20003800000 */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*0230*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD.WIDE R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e020b */
/*0250*/ LDG.E R4, [R4.64] ; /* 0x0000002404047981 */
/* 0x000ea4000c1e1900 */
/*0260*/ ISETP.NE.AND P0, PT, R17, R4, PT ; /* 0x000000041100720c */
/* 0x024fda0003f05270 */
/*0270*/ @!P0 BRA 0x310 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0280*/ ISETP.GE.AND P0, PT, R17, R4, PT ; /* 0x000000041100720c */
/* 0x000fc80003f06270 */
/*0290*/ SEL R3, R3, R0, !P0 ; /* 0x0000000003037207 */
/* 0x000fe40004000000 */
/*02a0*/ SEL R18, R0, R18, !P0 ; /* 0x0000001200127207 */
/* 0x000fca0004000000 */
/*02b0*/ IMAD.IADD R0, R3, 0x1, R18 ; /* 0x0000000103007824 */
/* 0x000fca00078e0212 */
/*02c0*/ LEA.HI R0, R0, R0, RZ, 0x1 ; /* 0x0000000000007211 */
/* 0x000fc800078f08ff */
/*02d0*/ SHF.R.S32.HI R0, RZ, 0x1, R0 ; /* 0x00000001ff007819 */
/* 0x000fc80000011400 */
/*02e0*/ ISETP.NE.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fda0003f05270 */
/*02f0*/ @P0 BRA 0x230 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0300*/ IMAD.MOV.U32 R0, RZ, RZ, R3 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0003 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ IMAD.WIDE R10, R0, R11, c[0x0][0x160] ; /* 0x00005800000a7625 */
/* 0x001fca00078e020b */
/*0330*/ LDG.E R0, [R10.64] ; /* 0x000000240a007981 */
/* 0x000ea2000c1e1900 */
/*0340*/ IADD3 R12, P1, R16, c[0x0][0x170], RZ ; /* 0x00005c00100c7a10 */
/* 0x000fc80007f3e0ff */
/*0350*/ LEA.HI.X.SX32 R13, R16, c[0x0][0x174], 0x1, P1 ; /* 0x00005d00100d7a11 */
/* 0x000fe400008f0eff */
/*0360*/ ISETP.NE.AND P0, PT, R17, R0, PT ; /* 0x000000001100720c */
/* 0x024fc80003f05270 */
/*0370*/ SEL R19, RZ, 0x1, P0 ; /* 0x00000001ff137807 */
/* 0x000fca0000000000 */
/*0380*/ STG.E.U8 [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0001e8000c101124 */
/*0390*/ LDG.E R18, [R10.64] ; /* 0x000000240a127981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*03b0*/ IMAD.MOV.U32 R6, RZ, RZ, R22 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0016 */
/*03c0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0002 */
/*03d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*03e0*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*03f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0400*/ STL.128 [R1], R16 ; /* 0x0000001001007387 */
/* 0x0041ec0000100c00 */
/*0410*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fe20000000000 */
/*0420*/ MOV R11, 0x490 ; /* 0x00000490000b7802 */
/* 0x000fc40000000f00 */
/*0430*/ MOV R20, 0x410 ; /* 0x0000041000147802 */
/* 0x000fe40000000f00 */
/*0440*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0450*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0460*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0470*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0480*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x001fea0003c00000 */
/*0490*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04a0*/ BRA 0x4a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include <cuda.h>
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; ++i)
a[i] = rand()%20000;
}
void add_array(int* a, int N)
{
for (int i = 0; i < N; ++i)
a[i] =i;
}
__global__ void binary_search(int* a, int* b, bool* c, int sizeofa) //kernal function
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
printf(" %d\n", index);
int key = b[index];
int min = 0, max = sizeofa;
int mid = sizeofa / 2;
while (min != mid)
{
if (key == a[mid])
{
break;
}
else if (key < a[mid])
{
min = min;
max = mid;
}
else {
min = mid;
max = max;
}
mid = (min + max) / 2;
}
if (key == a[mid])
c[index] = true;
else
c[index] = false;
printf(" %d %d %d %d\n", index, key, a[mid],c[index]);
}
int main()
{
int N = 10000; //size of given array
int M = 1000; //Number of searching element
size_t size = N * sizeof(int);
size_t size2 = M * sizeof(int);
//allocate memory for host array
int* vector1 = (int*)malloc(size);
int* vector2 = (int*)malloc(size2);
bool* vector3 = (bool*)malloc(M * sizeof(bool));
//insert number into array
add_array(vector1,N);
//insert random elements to search
random_ints(vector2,M);
//create device array pointer
int *d_vector1;
int *d_vector2;
bool *d_vector3;
//allocate device memory for vector
cudaMalloc(& d_vector1, size);
cudaMalloc(& d_vector2, size2);
cudaMalloc(& d_vector3, M*sizeof(bool));
//copy vectors from host memory to dvice memory
cudaMemcpy(d_vector1,vector1, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_vector2,vector2, size2, cudaMemcpyHostToDevice);
//call kernal
binary_search<<<M,1>>>(d_vector1, d_vector2, d_vector3,N);
cudaMemcpy(vector3,d_vector3, M * sizeof(bool), cudaMemcpyDeviceToHost);
for (int i = 0; i < M; i++)
{
if(vector3[i]==true)
printf("%d is present in array\n",vector2[i]);
else if(vector3[i] == 0)
printf("%d is not present in array\n", vector2[i]);
}
} | .file "tmpxft_0002c1c4_00000000-6_binary.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $45, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $20000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z9add_arrayPii
.type _Z9add_arrayPii, @function
_Z9add_arrayPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L11
movslq %esi, %rsi
movl $0, %eax
.L13:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L13
.L11:
ret
.cfi_endproc
.LFE2058:
.size _Z9add_arrayPii, .-_Z9add_arrayPii
.globl _Z38__device_stub__Z13binary_searchPiS_PbiPiS_Pbi
.type _Z38__device_stub__Z13binary_searchPiS_PbiPiS_Pbi, @function
_Z38__device_stub__Z13binary_searchPiS_PbiPiS_Pbi:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13binary_searchPiS_Pbi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z13binary_searchPiS_PbiPiS_Pbi, .-_Z38__device_stub__Z13binary_searchPiS_PbiPiS_Pbi
.globl _Z13binary_searchPiS_Pbi
.type _Z13binary_searchPiS_Pbi, @function
_Z13binary_searchPiS_Pbi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13binary_searchPiS_PbiPiS_Pbi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13binary_searchPiS_Pbi, .-_Z13binary_searchPiS_Pbi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d is present in array\n"
.LC1:
.string "%d is not present in array\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40000, %edi
call malloc@PLT
movq %rax, %rbx
movl $4000, %edi
call malloc@PLT
movq %rax, %rbp
movl $1000, %edi
call malloc@PLT
movq %rax, %r12
movl $10000, %esi
movq %rbx, %rdi
call _Z9add_arrayPii
movl $1000, %esi
movq %rbp, %rdi
call _Z11random_intsPii
leaq 8(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1000, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L24:
movl $2, %ecx
movl $1000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC1(%rip), %r14
leaq .LC0(%rip), %r13
jmp .L27
.L31:
movl $10000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z13binary_searchPiS_PbiPiS_Pbi
jmp .L24
.L25:
movl 0(%rbp,%rbx,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L26:
addq $1, %rbx
cmpq $1000, %rbx
je .L32
.L27:
cmpb $0, (%r12,%rbx)
je .L25
movl 0(%rbp,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L32:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13binary_searchPiS_Pbi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13binary_searchPiS_Pbi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include <cuda.h>
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; ++i)
a[i] = rand()%20000;
}
void add_array(int* a, int N)
{
for (int i = 0; i < N; ++i)
a[i] =i;
}
__global__ void binary_search(int* a, int* b, bool* c, int sizeofa) //kernal function
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
printf(" %d\n", index);
int key = b[index];
int min = 0, max = sizeofa;
int mid = sizeofa / 2;
while (min != mid)
{
if (key == a[mid])
{
break;
}
else if (key < a[mid])
{
min = min;
max = mid;
}
else {
min = mid;
max = max;
}
mid = (min + max) / 2;
}
if (key == a[mid])
c[index] = true;
else
c[index] = false;
printf(" %d %d %d %d\n", index, key, a[mid],c[index]);
}
int main()
{
int N = 10000; //size of given array
int M = 1000; //Number of searching element
size_t size = N * sizeof(int);
size_t size2 = M * sizeof(int);
//allocate memory for host array
int* vector1 = (int*)malloc(size);
int* vector2 = (int*)malloc(size2);
bool* vector3 = (bool*)malloc(M * sizeof(bool));
//insert number into array
add_array(vector1,N);
//insert random elements to search
random_ints(vector2,M);
//create device array pointer
int *d_vector1;
int *d_vector2;
bool *d_vector3;
//allocate device memory for vector
cudaMalloc(& d_vector1, size);
cudaMalloc(& d_vector2, size2);
cudaMalloc(& d_vector3, M*sizeof(bool));
//copy vectors from host memory to dvice memory
cudaMemcpy(d_vector1,vector1, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_vector2,vector2, size2, cudaMemcpyHostToDevice);
//call kernal
binary_search<<<M,1>>>(d_vector1, d_vector2, d_vector3,N);
cudaMemcpy(vector3,d_vector3, M * sizeof(bool), cudaMemcpyDeviceToHost);
for (int i = 0; i < M; i++)
{
if(vector3[i]==true)
printf("%d is present in array\n",vector2[i]);
else if(vector3[i] == 0)
printf("%d is not present in array\n", vector2[i]);
}
} | #include<stdio.h>
#include <hip/hip_runtime.h>
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; ++i)
a[i] = rand()%20000;
}
void add_array(int* a, int N)
{
for (int i = 0; i < N; ++i)
a[i] =i;
}
__global__ void binary_search(int* a, int* b, bool* c, int sizeofa) //kernal function
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
printf(" %d\n", index);
int key = b[index];
int min = 0, max = sizeofa;
int mid = sizeofa / 2;
while (min != mid)
{
if (key == a[mid])
{
break;
}
else if (key < a[mid])
{
min = min;
max = mid;
}
else {
min = mid;
max = max;
}
mid = (min + max) / 2;
}
if (key == a[mid])
c[index] = true;
else
c[index] = false;
printf(" %d %d %d %d\n", index, key, a[mid],c[index]);
}
int main()
{
int N = 10000; //size of given array
int M = 1000; //Number of searching element
size_t size = N * sizeof(int);
size_t size2 = M * sizeof(int);
//allocate memory for host array
int* vector1 = (int*)malloc(size);
int* vector2 = (int*)malloc(size2);
bool* vector3 = (bool*)malloc(M * sizeof(bool));
//insert number into array
add_array(vector1,N);
//insert random elements to search
random_ints(vector2,M);
//create device array pointer
int *d_vector1;
int *d_vector2;
bool *d_vector3;
//allocate device memory for vector
hipMalloc(& d_vector1, size);
hipMalloc(& d_vector2, size2);
hipMalloc(& d_vector3, M*sizeof(bool));
//copy vectors from host memory to dvice memory
hipMemcpy(d_vector1,vector1, size, hipMemcpyHostToDevice);
hipMemcpy(d_vector2,vector2, size2, hipMemcpyHostToDevice);
//call kernal
binary_search<<<M,1>>>(d_vector1, d_vector2, d_vector3,N);
hipMemcpy(vector3,d_vector3, M * sizeof(bool), hipMemcpyDeviceToHost);
for (int i = 0; i < M; i++)
{
if(vector3[i]==true)
printf("%d is present in array\n",vector2[i]);
else if(vector3[i] == 0)
printf("%d is not present in array\n", vector2[i]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include <hip/hip_runtime.h>
void random_ints(int* a, int N)
{
int i;
for (i = 0; i < N; ++i)
a[i] = rand()%20000;
}
void add_array(int* a, int N)
{
for (int i = 0; i < N; ++i)
a[i] =i;
}
__global__ void binary_search(int* a, int* b, bool* c, int sizeofa) //kernal function
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
printf(" %d\n", index);
int key = b[index];
int min = 0, max = sizeofa;
int mid = sizeofa / 2;
while (min != mid)
{
if (key == a[mid])
{
break;
}
else if (key < a[mid])
{
min = min;
max = mid;
}
else {
min = mid;
max = max;
}
mid = (min + max) / 2;
}
if (key == a[mid])
c[index] = true;
else
c[index] = false;
printf(" %d %d %d %d\n", index, key, a[mid],c[index]);
}
int main()
{
int N = 10000; //size of given array
int M = 1000; //Number of searching element
size_t size = N * sizeof(int);
size_t size2 = M * sizeof(int);
//allocate memory for host array
int* vector1 = (int*)malloc(size);
int* vector2 = (int*)malloc(size2);
bool* vector3 = (bool*)malloc(M * sizeof(bool));
//insert number into array
add_array(vector1,N);
//insert random elements to search
random_ints(vector2,M);
//create device array pointer
int *d_vector1;
int *d_vector2;
bool *d_vector3;
//allocate device memory for vector
hipMalloc(& d_vector1, size);
hipMalloc(& d_vector2, size2);
hipMalloc(& d_vector3, M*sizeof(bool));
//copy vectors from host memory to dvice memory
hipMemcpy(d_vector1,vector1, size, hipMemcpyHostToDevice);
hipMemcpy(d_vector2,vector2, size2, hipMemcpyHostToDevice);
//call kernal
binary_search<<<M,1>>>(d_vector1, d_vector2, d_vector3,N);
hipMemcpy(vector3,d_vector3, M * sizeof(bool), hipMemcpyDeviceToHost);
for (int i = 0; i < M; i++)
{
if(vector3[i]==true)
printf("%d is present in array\n",vector2[i]);
else if(vector3[i] == 0)
printf("%d is not present in array\n", vector2[i]);
}
} | .text
.file "binary.hip"
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $45, %rcx
addl %edx, %ecx
imull $20000, %ecx, %ecx # imm = 0x4E20
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z11random_intsPii, .Lfunc_end0-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl _Z9add_arrayPii # -- Begin function _Z9add_arrayPii
.p2align 4, 0x90
.type _Z9add_arrayPii,@function
_Z9add_arrayPii: # @_Z9add_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z9add_arrayPii, .Lfunc_end1-_Z9add_arrayPii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__binary_searchPiS_Pbi # -- Begin function _Z28__device_stub__binary_searchPiS_Pbi
.p2align 4, 0x90
.type _Z28__device_stub__binary_searchPiS_Pbi,@function
_Z28__device_stub__binary_searchPiS_Pbi: # @_Z28__device_stub__binary_searchPiS_Pbi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13binary_searchPiS_Pbi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z28__device_stub__binary_searchPiS_Pbi, .Lfunc_end2-_Z28__device_stub__binary_searchPiS_Pbi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r15
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %rbx
movl $1000, %edi # imm = 0x3E8
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %eax, (%r15,%rax,4)
incq %rax
cmpq $10000, %rax # imm = 0x2710
jne .LBB3_1
# %bb.2: # %.lr.ph.i34.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i34
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $45, %rcx
addl %edx, %ecx
imull $20000, %ecx, %ecx # imm = 0x4E20
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB3_3
# %bb.4: # %_Z11random_intsPii.exit
leaq 32(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1000, %esi # imm = 0x3E8
callq hipMalloc
movq 32(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 999(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10000, 12(%rsp) # imm = 0x2710
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13binary_searchPiS_Pbi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq 16(%rsp), %rsi
movl $1000, %edx # imm = 0x3E8
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.1, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
cmpb $0, (%r14,%r12)
movl (%rbx,%r12,4), %esi
movl $.L.str, %edi
cmoveq %r15, %rdi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB3_7
# %bb.8:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13binary_searchPiS_Pbi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13binary_searchPiS_Pbi,@object # @_Z13binary_searchPiS_Pbi
.section .rodata,"a",@progbits
.globl _Z13binary_searchPiS_Pbi
.p2align 3, 0x0
_Z13binary_searchPiS_Pbi:
.quad _Z28__device_stub__binary_searchPiS_Pbi
.size _Z13binary_searchPiS_Pbi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d is present in array\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d is not present in array\n"
.size .L.str.1, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13binary_searchPiS_Pbi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__binary_searchPiS_Pbi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13binary_searchPiS_Pbi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002c1c4_00000000-6_binary.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $45, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $20000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z9add_arrayPii
.type _Z9add_arrayPii, @function
_Z9add_arrayPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L11
movslq %esi, %rsi
movl $0, %eax
.L13:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L13
.L11:
ret
.cfi_endproc
.LFE2058:
.size _Z9add_arrayPii, .-_Z9add_arrayPii
.globl _Z38__device_stub__Z13binary_searchPiS_PbiPiS_Pbi
.type _Z38__device_stub__Z13binary_searchPiS_PbiPiS_Pbi, @function
_Z38__device_stub__Z13binary_searchPiS_PbiPiS_Pbi:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13binary_searchPiS_Pbi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z13binary_searchPiS_PbiPiS_Pbi, .-_Z38__device_stub__Z13binary_searchPiS_PbiPiS_Pbi
.globl _Z13binary_searchPiS_Pbi
.type _Z13binary_searchPiS_Pbi, @function
_Z13binary_searchPiS_Pbi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13binary_searchPiS_PbiPiS_Pbi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13binary_searchPiS_Pbi, .-_Z13binary_searchPiS_Pbi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d is present in array\n"
.LC1:
.string "%d is not present in array\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $40000, %edi
call malloc@PLT
movq %rax, %rbx
movl $4000, %edi
call malloc@PLT
movq %rax, %rbp
movl $1000, %edi
call malloc@PLT
movq %rax, %r12
movl $10000, %esi
movq %rbx, %rdi
call _Z9add_arrayPii
movl $1000, %esi
movq %rbp, %rdi
call _Z11random_intsPii
leaq 8(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $1000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1000, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L24:
movl $2, %ecx
movl $1000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC1(%rip), %r14
leaq .LC0(%rip), %r13
jmp .L27
.L31:
movl $10000, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z13binary_searchPiS_PbiPiS_Pbi
jmp .L24
.L25:
movl 0(%rbp,%rbx,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L26:
addq $1, %rbx
cmpq $1000, %rbx
je .L32
.L27:
cmpb $0, (%r12,%rbx)
je .L25
movl 0(%rbp,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L32:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13binary_searchPiS_Pbi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13binary_searchPiS_Pbi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "binary.hip"
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $45, %rcx
addl %edx, %ecx
imull $20000, %ecx, %ecx # imm = 0x4E20
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z11random_intsPii, .Lfunc_end0-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl _Z9add_arrayPii # -- Begin function _Z9add_arrayPii
.p2align 4, 0x90
.type _Z9add_arrayPii,@function
_Z9add_arrayPii: # @_Z9add_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z9add_arrayPii, .Lfunc_end1-_Z9add_arrayPii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__binary_searchPiS_Pbi # -- Begin function _Z28__device_stub__binary_searchPiS_Pbi
.p2align 4, 0x90
.type _Z28__device_stub__binary_searchPiS_Pbi,@function
_Z28__device_stub__binary_searchPiS_Pbi: # @_Z28__device_stub__binary_searchPiS_Pbi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13binary_searchPiS_Pbi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z28__device_stub__binary_searchPiS_Pbi, .Lfunc_end2-_Z28__device_stub__binary_searchPiS_Pbi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r15
movl $4000, %edi # imm = 0xFA0
callq malloc
movq %rax, %rbx
movl $1000, %edi # imm = 0x3E8
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %eax, (%r15,%rax,4)
incq %rax
cmpq $10000, %rax # imm = 0x2710
jne .LBB3_1
# %bb.2: # %.lr.ph.i34.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i34
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $45, %rcx
addl %edx, %ecx
imull $20000, %ecx, %ecx # imm = 0x4E20
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB3_3
# %bb.4: # %_Z11random_intsPii.exit
leaq 32(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1000, %esi # imm = 0x3E8
callq hipMalloc
movq 32(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 999(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $10000, 12(%rsp) # imm = 0x2710
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13binary_searchPiS_Pbi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
movq 16(%rsp), %rsi
movl $1000, %edx # imm = 0x3E8
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.1, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
cmpb $0, (%r14,%r12)
movl (%rbx,%r12,4), %esi
movl $.L.str, %edi
cmoveq %r15, %rdi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB3_7
# %bb.8:
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13binary_searchPiS_Pbi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13binary_searchPiS_Pbi,@object # @_Z13binary_searchPiS_Pbi
.section .rodata,"a",@progbits
.globl _Z13binary_searchPiS_Pbi
.p2align 3, 0x0
_Z13binary_searchPiS_Pbi:
.quad _Z28__device_stub__binary_searchPiS_Pbi
.size _Z13binary_searchPiS_Pbi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d is present in array\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d is not present in array\n"
.size .L.str.1, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13binary_searchPiS_Pbi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__binary_searchPiS_Pbi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13binary_searchPiS_Pbi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
__global__ void maxi(int *d_a,int n){
int strid=(n/2);
int idx=threadIdx.x;
while(strid>0){
if(idx<strid)
if(d_a[idx]<d_a[idx+strid])
d_a[idx]=d_a[idx+strid];
strid=(strid/2);
}
}
int main(){
int n=512;
int *a;
a=(int*)malloc(n*sizeof(int));
for(int i=0; i<n; i++)
a[i]=i*i*i;
int *d_a;
cudaMalloc((void**)&d_a,n*sizeof(int));
cudaMemcpy(d_a,a,n*sizeof(int),cudaMemcpyHostToDevice);
dim3 blockD(n,1,1);
dim3 gridD(1,1,1);
maxi<<<gridD,blockD>>>(d_a,n);
int *b;
b=(int*)malloc(n*sizeof(int));
cudaMemcpy(b,d_a,n*sizeof(int),cudaMemcpyDeviceToHost);
printf("%d\n",b[0]);
} | code for sm_80
Function : _Z4maxiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff077624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0203 */
/*0090*/ LEA.HI R0, R7, R7.reuse, RZ, 0x1 ; /* 0x0000000707007211 */
/* 0x080fe200078f08ff */
/*00a0*/ BSSY B0, 0x160 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*00b0*/ MOV R4, R7 ; /* 0x0000000700047202 */
/* 0x000fe40000000f00 */
/*00c0*/ SHF.R.S32.HI R7, RZ, 0x1, R0 ; /* 0x00000001ff077819 */
/* 0x000fe40000011400 */
/*00d0*/ ISETP.GT.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f04270 */
/*00e0*/ ISETP.GE.AND P1, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fda0003f26270 */
/*00f0*/ @P1 BRA 0x150 ; /* 0x0000005000001947 */
/* 0x001fea0003800000 */
/*0100*/ IMAD.WIDE R4, R7, 0x4, R2 ; /* 0x0000000407047825 */
/* 0x000fe200078e0202 */
/*0110*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000eaa000c1e1900 */
/*0120*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0130*/ ISETP.GE.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f26270 */
/*0140*/ @!P1 STG.E [R2.64], R5 ; /* 0x0000000502009986 */
/* 0x0001e4000c101904 */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ @P0 BRA 0x90 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
__global__ void maxi(int *d_a,int n){
int strid=(n/2);
int idx=threadIdx.x;
while(strid>0){
if(idx<strid)
if(d_a[idx]<d_a[idx+strid])
d_a[idx]=d_a[idx+strid];
strid=(strid/2);
}
}
int main(){
int n=512;
int *a;
a=(int*)malloc(n*sizeof(int));
for(int i=0; i<n; i++)
a[i]=i*i*i;
int *d_a;
cudaMalloc((void**)&d_a,n*sizeof(int));
cudaMemcpy(d_a,a,n*sizeof(int),cudaMemcpyHostToDevice);
dim3 blockD(n,1,1);
dim3 gridD(1,1,1);
maxi<<<gridD,blockD>>>(d_a,n);
int *b;
b=(int*)malloc(n*sizeof(int));
cudaMemcpy(b,d_a,n*sizeof(int),cudaMemcpyDeviceToHost);
printf("%d\n",b[0]);
} | .file "tmpxft_001107d9_00000000-6_maxinum_bhanu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z4maxiPiiPii
.type _Z24__device_stub__Z4maxiPiiPii, @function
_Z24__device_stub__Z4maxiPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4maxiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z4maxiPiiPii, .-_Z24__device_stub__Z4maxiPiiPii
.globl _Z4maxiPii
.type _Z4maxiPii, @function
_Z4maxiPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4maxiPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4maxiPii, .-_Z4maxiPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $2048, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L12:
movl %eax, %edx
imull %eax, %edx
imull %eax, %edx
movl %edx, (%rbx,%rax,4)
addq $1, %rax
cmpq $512, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $2048, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2048, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $2048, %edx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl (%rbx), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $512, %esi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z4maxiPiiPii
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z4maxiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4maxiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
__global__ void maxi(int *d_a,int n){
int strid=(n/2);
int idx=threadIdx.x;
while(strid>0){
if(idx<strid)
if(d_a[idx]<d_a[idx+strid])
d_a[idx]=d_a[idx+strid];
strid=(strid/2);
}
}
int main(){
int n=512;
int *a;
a=(int*)malloc(n*sizeof(int));
for(int i=0; i<n; i++)
a[i]=i*i*i;
int *d_a;
cudaMalloc((void**)&d_a,n*sizeof(int));
cudaMemcpy(d_a,a,n*sizeof(int),cudaMemcpyHostToDevice);
dim3 blockD(n,1,1);
dim3 gridD(1,1,1);
maxi<<<gridD,blockD>>>(d_a,n);
int *b;
b=(int*)malloc(n*sizeof(int));
cudaMemcpy(b,d_a,n*sizeof(int),cudaMemcpyDeviceToHost);
printf("%d\n",b[0]);
} | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void maxi(int *d_a,int n){
int strid=(n/2);
int idx=threadIdx.x;
while(strid>0){
if(idx<strid)
if(d_a[idx]<d_a[idx+strid])
d_a[idx]=d_a[idx+strid];
strid=(strid/2);
}
}
int main(){
int n=512;
int *a;
a=(int*)malloc(n*sizeof(int));
for(int i=0; i<n; i++)
a[i]=i*i*i;
int *d_a;
hipMalloc((void**)&d_a,n*sizeof(int));
hipMemcpy(d_a,a,n*sizeof(int),hipMemcpyHostToDevice);
dim3 blockD(n,1,1);
dim3 gridD(1,1,1);
maxi<<<gridD,blockD>>>(d_a,n);
int *b;
b=(int*)malloc(n*sizeof(int));
hipMemcpy(b,d_a,n*sizeof(int),hipMemcpyDeviceToHost);
printf("%d\n",b[0]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void maxi(int *d_a,int n){
int strid=(n/2);
int idx=threadIdx.x;
while(strid>0){
if(idx<strid)
if(d_a[idx]<d_a[idx+strid])
d_a[idx]=d_a[idx+strid];
strid=(strid/2);
}
}
int main(){
int n=512;
int *a;
a=(int*)malloc(n*sizeof(int));
for(int i=0; i<n; i++)
a[i]=i*i*i;
int *d_a;
hipMalloc((void**)&d_a,n*sizeof(int));
hipMemcpy(d_a,a,n*sizeof(int),hipMemcpyHostToDevice);
dim3 blockD(n,1,1);
dim3 gridD(1,1,1);
maxi<<<gridD,blockD>>>(d_a,n);
int *b;
b=(int*)malloc(n*sizeof(int));
hipMemcpy(b,d_a,n*sizeof(int),hipMemcpyDeviceToHost);
printf("%d\n",b[0]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4maxiPii
.globl _Z4maxiPii
.p2align 8
.type _Z4maxiPii,@function
_Z4maxiPii:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s3, s0, v1
v_add_co_ci_u32_e64 v4, null, s1, 0, s3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_gt_u32 s3, 3
s_cbranch_scc0 .LBB0_6
.LBB0_3:
s_mov_b32 s3, s2
s_lshr_b32 s2, s2, 1
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_clause 0x1
global_load_b32 v7, v[3:4], off
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v7, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
global_store_b32 v[3:4], v1, off
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4maxiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4maxiPii, .Lfunc_end0-_Z4maxiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4maxiPii
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z4maxiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void maxi(int *d_a,int n){
int strid=(n/2);
int idx=threadIdx.x;
while(strid>0){
if(idx<strid)
if(d_a[idx]<d_a[idx+strid])
d_a[idx]=d_a[idx+strid];
strid=(strid/2);
}
}
int main(){
int n=512;
int *a;
a=(int*)malloc(n*sizeof(int));
for(int i=0; i<n; i++)
a[i]=i*i*i;
int *d_a;
hipMalloc((void**)&d_a,n*sizeof(int));
hipMemcpy(d_a,a,n*sizeof(int),hipMemcpyHostToDevice);
dim3 blockD(n,1,1);
dim3 gridD(1,1,1);
maxi<<<gridD,blockD>>>(d_a,n);
int *b;
b=(int*)malloc(n*sizeof(int));
hipMemcpy(b,d_a,n*sizeof(int),hipMemcpyDeviceToHost);
printf("%d\n",b[0]);
} | .text
.file "maxinum_bhanu.hip"
.globl _Z19__device_stub__maxiPii # -- Begin function _Z19__device_stub__maxiPii
.p2align 4, 0x90
.type _Z19__device_stub__maxiPii,@function
_Z19__device_stub__maxiPii: # @_Z19__device_stub__maxiPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4maxiPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__maxiPii, .Lfunc_end0-_Z19__device_stub__maxiPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
imull %eax, %ecx
imull %eax, %ecx
movl %ecx, (%rbx,%rax,4)
incq %rax
cmpq $512, %rax # imm = 0x200
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $512, 20(%rsp) # imm = 0x200
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4maxiPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4maxiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4maxiPii,@object # @_Z4maxiPii
.section .rodata,"a",@progbits
.globl _Z4maxiPii
.p2align 3, 0x0
_Z4maxiPii:
.quad _Z19__device_stub__maxiPii
.size _Z4maxiPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4maxiPii"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__maxiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4maxiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4maxiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff077624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0203 */
/*0090*/ LEA.HI R0, R7, R7.reuse, RZ, 0x1 ; /* 0x0000000707007211 */
/* 0x080fe200078f08ff */
/*00a0*/ BSSY B0, 0x160 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*00b0*/ MOV R4, R7 ; /* 0x0000000700047202 */
/* 0x000fe40000000f00 */
/*00c0*/ SHF.R.S32.HI R7, RZ, 0x1, R0 ; /* 0x00000001ff077819 */
/* 0x000fe40000011400 */
/*00d0*/ ISETP.GT.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f04270 */
/*00e0*/ ISETP.GE.AND P1, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fda0003f26270 */
/*00f0*/ @P1 BRA 0x150 ; /* 0x0000005000001947 */
/* 0x001fea0003800000 */
/*0100*/ IMAD.WIDE R4, R7, 0x4, R2 ; /* 0x0000000407047825 */
/* 0x000fe200078e0202 */
/*0110*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000eaa000c1e1900 */
/*0120*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0130*/ ISETP.GE.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f26270 */
/*0140*/ @!P1 STG.E [R2.64], R5 ; /* 0x0000000502009986 */
/* 0x0001e4000c101904 */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ @P0 BRA 0x90 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4maxiPii
.globl _Z4maxiPii
.p2align 8
.type _Z4maxiPii,@function
_Z4maxiPii:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s3, s0, v1
v_add_co_ci_u32_e64 v4, null, s1, 0, s3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_gt_u32 s3, 3
s_cbranch_scc0 .LBB0_6
.LBB0_3:
s_mov_b32 s3, s2
s_lshr_b32 s2, s2, 1
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_clause 0x1
global_load_b32 v7, v[3:4], off
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v7, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
global_store_b32 v[3:4], v1, off
s_branch .LBB0_2
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4maxiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4maxiPii, .Lfunc_end0-_Z4maxiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4maxiPii
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z4maxiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001107d9_00000000-6_maxinum_bhanu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z4maxiPiiPii
.type _Z24__device_stub__Z4maxiPiiPii, @function
_Z24__device_stub__Z4maxiPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4maxiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z4maxiPiiPii, .-_Z24__device_stub__Z4maxiPiiPii
.globl _Z4maxiPii
.type _Z4maxiPii, @function
_Z4maxiPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z4maxiPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4maxiPii, .-_Z4maxiPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $2048, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L12:
movl %eax, %edx
imull %eax, %edx
imull %eax, %edx
movl %edx, (%rbx,%rax,4)
addq $1, %rax
cmpq $512, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $2048, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2048, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $2048, %edx
movq 8(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl (%rbx), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $512, %esi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z4maxiPiiPii
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z4maxiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4maxiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "maxinum_bhanu.hip"
.globl _Z19__device_stub__maxiPii # -- Begin function _Z19__device_stub__maxiPii
.p2align 4, 0x90
.type _Z19__device_stub__maxiPii,@function
_Z19__device_stub__maxiPii: # @_Z19__device_stub__maxiPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4maxiPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__maxiPii, .Lfunc_end0-_Z19__device_stub__maxiPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $96, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -16
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
imull %eax, %ecx
imull %eax, %ecx
movl %ecx, (%rbx,%rax,4)
incq %rax
cmpq $512, %rax # imm = 0x200
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $512, 20(%rsp) # imm = 0x200
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4maxiPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4maxiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4maxiPii,@object # @_Z4maxiPii
.section .rodata,"a",@progbits
.globl _Z4maxiPii
.p2align 3, 0x0
_Z4maxiPii:
.quad _Z19__device_stub__maxiPii
.size _Z4maxiPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4maxiPii"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__maxiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4maxiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void PIDControllerKernel(float* input, float* goal, float* output, float* previousError, float* integral)
{
int id = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (id < D_COUNT)
{
float error = input[id] - goal[id];
integral[id] = D_INTEGRAL_DECAY * integral[id] + error;
float derivative = error - previousError[id];
previousError[id] = error;
float out = D_OFFSET + D_PROPORTIONAL_GAIN * error + D_INTEGRAL_GAIN * integral[id] + D_DERIVATIVE_GAIN * derivative;
if (out > D_MAX_OUTPUT)
out = D_MAX_OUTPUT;
if (out < D_MIN_OUTPUT)
out = D_MIN_OUTPUT;
output[id] = out;
}
} | code for sm_80
Function : _Z19PIDControllerKernelPfS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x3][0x1c], PT ; /* 0x00c0070000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R0, R17, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0211 */
/*00b0*/ IMAD.WIDE R2, R0.reuse, R17.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0211 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R0, R17, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x000fe400078e0211 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ee2000c1e1900 */
/*0100*/ FADD R11, -R4, R3 ; /* 0x00000003040b7221 */
/* 0x004fc80000000100 */
/*0110*/ FFMA R13, R8, c[0x3][0xc], R11 ; /* 0x00c00300080d7a23 */
/* 0x008fe4000000000b */
/*0120*/ IMAD.WIDE R8, R0, R17, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc600078e0211 */
/*0130*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe8000c101904 */
/*0140*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea8000c1e1900 */
/*0150*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe8000c101904 */
/*0160*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ee2000c1e1900 */
/*0170*/ MOV R12, c[0x3][0x0] ; /* 0x00c00000000c7a02 */
/* 0x000fca0000000f00 */
/*0180*/ FFMA R4, R11, R12, c[0x3][0x10] ; /* 0x00c004000b047623 */
/* 0x000fe4000000000c */
/*0190*/ IMAD.WIDE R2, R0, R17, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0211 */
/*01a0*/ FADD R10, R11, -R10 ; /* 0x8000000a0b0a7221 */
/* 0x004fe40000000000 */
/*01b0*/ FFMA R15, R15, c[0x3][0x4], R4 ; /* 0x00c001000f0f7a23 */
/* 0x008fc80000000004 */
/*01c0*/ FFMA R10, R10, c[0x3][0x8], R15 ; /* 0x00c002000a0a7a23 */
/* 0x000fca000000000f */
/*01d0*/ FSETP.GT.AND P0, PT, R10, c[0x3][0x18], PT ; /* 0x00c006000a007a0b */
/* 0x000fc80003f04000 */
/*01e0*/ FSEL R10, R10, c[0x3][0x18], !P0 ; /* 0x00c006000a0a7a08 */
/* 0x000fc80004000000 */
/*01f0*/ FSETP.GEU.AND P0, PT, R10, c[0x3][0x14], PT ; /* 0x00c005000a007a0b */
/* 0x000fc80003f0e000 */
/*0200*/ FSEL R5, R10, c[0x3][0x14], P0 ; /* 0x00c005000a057a08 */
/* 0x000fca0000000000 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void PIDControllerKernel(float* input, float* goal, float* output, float* previousError, float* integral)
{
int id = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (id < D_COUNT)
{
float error = input[id] - goal[id];
integral[id] = D_INTEGRAL_DECAY * integral[id] + error;
float derivative = error - previousError[id];
previousError[id] = error;
float out = D_OFFSET + D_PROPORTIONAL_GAIN * error + D_INTEGRAL_GAIN * integral[id] + D_DERIVATIVE_GAIN * derivative;
if (out > D_MAX_OUTPUT)
out = D_MAX_OUTPUT;
if (out < D_MIN_OUTPUT)
out = D_MIN_OUTPUT;
output[id] = out;
}
} | .file "tmpxft_00145fb3_00000000-6_PIDControllerKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z19PIDControllerKernelPfS_S_S_S_PfS_S_S_S_
.type _Z47__device_stub__Z19PIDControllerKernelPfS_S_S_S_PfS_S_S_S_, @function
_Z47__device_stub__Z19PIDControllerKernelPfS_S_S_S_PfS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19PIDControllerKernelPfS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z19PIDControllerKernelPfS_S_S_S_PfS_S_S_S_, .-_Z47__device_stub__Z19PIDControllerKernelPfS_S_S_S_PfS_S_S_S_
.globl _Z19PIDControllerKernelPfS_S_S_S_
.type _Z19PIDControllerKernelPfS_S_S_S_, @function
_Z19PIDControllerKernelPfS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z19PIDControllerKernelPfS_S_S_S_PfS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19PIDControllerKernelPfS_S_S_S_, .-_Z19PIDControllerKernelPfS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19PIDControllerKernelPfS_S_S_S_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "D_PROPORTIONAL_GAIN"
.LC2:
.string "D_INTEGRAL_GAIN"
.LC3:
.string "D_DERIVATIVE_GAIN"
.LC4:
.string "D_INTEGRAL_DECAY"
.LC5:
.string "D_OFFSET"
.LC6:
.string "D_MIN_OUTPUT"
.LC7:
.string "D_MAX_OUTPUT"
.LC8:
.string "D_COUNT"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19PIDControllerKernelPfS_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL19D_PROPORTIONAL_GAIN(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15D_INTEGRAL_GAIN(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17D_DERIVATIVE_GAIN(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16D_INTEGRAL_DECAY(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8D_OFFSET(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12D_MIN_OUTPUT(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12D_MAX_OUTPUT(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7D_COUNT(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7D_COUNT
.comm _ZL7D_COUNT,4,4
.local _ZL12D_MAX_OUTPUT
.comm _ZL12D_MAX_OUTPUT,4,4
.local _ZL12D_MIN_OUTPUT
.comm _ZL12D_MIN_OUTPUT,4,4
.local _ZL8D_OFFSET
.comm _ZL8D_OFFSET,4,4
.local _ZL16D_INTEGRAL_DECAY
.comm _ZL16D_INTEGRAL_DECAY,4,4
.local _ZL17D_DERIVATIVE_GAIN
.comm _ZL17D_DERIVATIVE_GAIN,4,4
.local _ZL15D_INTEGRAL_GAIN
.comm _ZL15D_INTEGRAL_GAIN,4,4
.local _ZL19D_PROPORTIONAL_GAIN
.comm _ZL19D_PROPORTIONAL_GAIN,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void PIDControllerKernel(float* input, float* goal, float* output, float* previousError, float* integral)
{
int id = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (id < D_COUNT)
{
float error = input[id] - goal[id];
integral[id] = D_INTEGRAL_DECAY * integral[id] + error;
float derivative = error - previousError[id];
previousError[id] = error;
float out = D_OFFSET + D_PROPORTIONAL_GAIN * error + D_INTEGRAL_GAIN * integral[id] + D_DERIVATIVE_GAIN * derivative;
if (out > D_MAX_OUTPUT)
out = D_MAX_OUTPUT;
if (out < D_MIN_OUTPUT)
out = D_MIN_OUTPUT;
output[id] = out;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PIDControllerKernel(float* input, float* goal, float* output, float* previousError, float* integral)
{
int id = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (id < D_COUNT)
{
float error = input[id] - goal[id];
integral[id] = D_INTEGRAL_DECAY * integral[id] + error;
float derivative = error - previousError[id];
previousError[id] = error;
float out = D_OFFSET + D_PROPORTIONAL_GAIN * error + D_INTEGRAL_GAIN * integral[id] + D_DERIVATIVE_GAIN * derivative;
if (out > D_MAX_OUTPUT)
out = D_MAX_OUTPUT;
if (out < D_MIN_OUTPUT)
out = D_MIN_OUTPUT;
output[id] = out;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PIDControllerKernel(float* input, float* goal, float* output, float* previousError, float* integral)
{
int id = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (id < D_COUNT)
{
float error = input[id] - goal[id];
integral[id] = D_INTEGRAL_DECAY * integral[id] + error;
float derivative = error - previousError[id];
previousError[id] = error;
float out = D_OFFSET + D_PROPORTIONAL_GAIN * error + D_INTEGRAL_GAIN * integral[id] + D_DERIVATIVE_GAIN * derivative;
if (out > D_MAX_OUTPUT)
out = D_MAX_OUTPUT;
if (out < D_MIN_OUTPUT)
out = D_MIN_OUTPUT;
output[id] = out;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19PIDControllerKernelPfS_S_S_S_
.globl _Z19PIDControllerKernelPfS_S_S_S_
.p2align 8
.type _Z19PIDControllerKernelPfS_S_S_S_,@function
_Z19PIDControllerKernelPfS_S_S_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x28
s_load_b32 s5, s[0:1], 0x34
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, D_COUNT@rel32@lo+4
s_addc_u32 s3, s3, D_COUNT@rel32@hi+12
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s4, s15
s_and_b32 s4, s5, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
global_load_b32 v4, v[6:7], off
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_INTEGRAL_DECAY@rel32@lo+4
s_addc_u32 s1, s1, D_INTEGRAL_DECAY@rel32@hi+12
s_load_b32 s0, s[0:1], 0x0
s_waitcnt vmcnt(1)
v_sub_f32_e32 v5, v2, v3
v_add_co_u32 v2, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_fma_f32 v4, s0, v4, v5
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_OFFSET@rel32@lo+4
s_addc_u32 s1, s1, D_OFFSET@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, D_PROPORTIONAL_GAIN@rel32@lo+4
s_addc_u32 s3, s3, D_PROPORTIONAL_GAIN@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, D_INTEGRAL_GAIN@rel32@lo+4
s_addc_u32 s5, s5, D_INTEGRAL_GAIN@rel32@hi+12
global_store_b32 v[6:7], v4, off
global_load_b32 v4, v[2:3], off
global_store_b32 v[2:3], v5, off
global_load_b32 v2, v[6:7], off
s_load_b32 s6, s[0:1], 0x0
s_load_b32 s7, s[2:3], 0x0
s_load_b32 s4, s[4:5], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_DERIVATIVE_GAIN@rel32@lo+4
s_addc_u32 s1, s1, D_DERIVATIVE_GAIN@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, D_MAX_OUTPUT@rel32@lo+4
s_addc_u32 s3, s3, D_MAX_OUTPUT@rel32@hi+12
s_load_b32 s5, s[0:1], 0x0
s_load_b32 s2, s[2:3], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_MIN_OUTPUT@rel32@lo+4
s_addc_u32 s1, s1, D_MIN_OUTPUT@rel32@hi+12
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_fma_f32 v3, v5, s7, s6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v4, v5, v4 :: v_dual_fmac_f32 v3, s4, v2
v_fmac_f32_e32 v3, s5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, s2, v3
v_cndmask_b32_e64 v2, v3, s2, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, s0, v2
v_cndmask_b32_e64 v2, v2, s0, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19PIDControllerKernelPfS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19PIDControllerKernelPfS_S_S_S_, .Lfunc_end0-_Z19PIDControllerKernelPfS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected D_PROPORTIONAL_GAIN
.type D_PROPORTIONAL_GAIN,@object
.section .bss,"aw",@nobits
.globl D_PROPORTIONAL_GAIN
.p2align 2, 0x0
D_PROPORTIONAL_GAIN:
.long 0x00000000
.size D_PROPORTIONAL_GAIN, 4
.protected D_INTEGRAL_GAIN
.type D_INTEGRAL_GAIN,@object
.globl D_INTEGRAL_GAIN
.p2align 2, 0x0
D_INTEGRAL_GAIN:
.long 0x00000000
.size D_INTEGRAL_GAIN, 4
.protected D_DERIVATIVE_GAIN
.type D_DERIVATIVE_GAIN,@object
.globl D_DERIVATIVE_GAIN
.p2align 2, 0x0
D_DERIVATIVE_GAIN:
.long 0x00000000
.size D_DERIVATIVE_GAIN, 4
.protected D_INTEGRAL_DECAY
.type D_INTEGRAL_DECAY,@object
.globl D_INTEGRAL_DECAY
.p2align 2, 0x0
D_INTEGRAL_DECAY:
.long 0x00000000
.size D_INTEGRAL_DECAY, 4
.protected D_OFFSET
.type D_OFFSET,@object
.globl D_OFFSET
.p2align 2, 0x0
D_OFFSET:
.long 0x00000000
.size D_OFFSET, 4
.protected D_MIN_OUTPUT
.type D_MIN_OUTPUT,@object
.globl D_MIN_OUTPUT
.p2align 2, 0x0
D_MIN_OUTPUT:
.long 0x00000000
.size D_MIN_OUTPUT, 4
.protected D_MAX_OUTPUT
.type D_MAX_OUTPUT,@object
.globl D_MAX_OUTPUT
.p2align 2, 0x0
D_MAX_OUTPUT:
.long 0x00000000
.size D_MAX_OUTPUT, 4
.protected D_COUNT
.type D_COUNT,@object
.globl D_COUNT
.p2align 2, 0x0
D_COUNT:
.long 0
.size D_COUNT, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym D_PROPORTIONAL_GAIN
.addrsig_sym D_INTEGRAL_GAIN
.addrsig_sym D_DERIVATIVE_GAIN
.addrsig_sym D_INTEGRAL_DECAY
.addrsig_sym D_OFFSET
.addrsig_sym D_MIN_OUTPUT
.addrsig_sym D_MAX_OUTPUT
.addrsig_sym D_COUNT
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19PIDControllerKernelPfS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19PIDControllerKernelPfS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PIDControllerKernel(float* input, float* goal, float* output, float* previousError, float* integral)
{
int id = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if (id < D_COUNT)
{
float error = input[id] - goal[id];
integral[id] = D_INTEGRAL_DECAY * integral[id] + error;
float derivative = error - previousError[id];
previousError[id] = error;
float out = D_OFFSET + D_PROPORTIONAL_GAIN * error + D_INTEGRAL_GAIN * integral[id] + D_DERIVATIVE_GAIN * derivative;
if (out > D_MAX_OUTPUT)
out = D_MAX_OUTPUT;
if (out < D_MIN_OUTPUT)
out = D_MIN_OUTPUT;
output[id] = out;
}
} | .text
.file "PIDControllerKernel.hip"
.globl _Z34__device_stub__PIDControllerKernelPfS_S_S_S_ # -- Begin function _Z34__device_stub__PIDControllerKernelPfS_S_S_S_
.p2align 4, 0x90
.type _Z34__device_stub__PIDControllerKernelPfS_S_S_S_,@function
_Z34__device_stub__PIDControllerKernelPfS_S_S_S_: # @_Z34__device_stub__PIDControllerKernelPfS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19PIDControllerKernelPfS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z34__device_stub__PIDControllerKernelPfS_S_S_S_, .Lfunc_end0-_Z34__device_stub__PIDControllerKernelPfS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19PIDControllerKernelPfS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $D_PROPORTIONAL_GAIN, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_INTEGRAL_GAIN, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_DERIVATIVE_GAIN, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_INTEGRAL_DECAY, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_OFFSET, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_MIN_OUTPUT, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_MAX_OUTPUT, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_COUNT, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type D_PROPORTIONAL_GAIN,@object # @D_PROPORTIONAL_GAIN
.local D_PROPORTIONAL_GAIN
.comm D_PROPORTIONAL_GAIN,4,4
.type D_INTEGRAL_GAIN,@object # @D_INTEGRAL_GAIN
.local D_INTEGRAL_GAIN
.comm D_INTEGRAL_GAIN,4,4
.type D_DERIVATIVE_GAIN,@object # @D_DERIVATIVE_GAIN
.local D_DERIVATIVE_GAIN
.comm D_DERIVATIVE_GAIN,4,4
.type D_INTEGRAL_DECAY,@object # @D_INTEGRAL_DECAY
.local D_INTEGRAL_DECAY
.comm D_INTEGRAL_DECAY,4,4
.type D_OFFSET,@object # @D_OFFSET
.local D_OFFSET
.comm D_OFFSET,4,4
.type D_MIN_OUTPUT,@object # @D_MIN_OUTPUT
.local D_MIN_OUTPUT
.comm D_MIN_OUTPUT,4,4
.type D_MAX_OUTPUT,@object # @D_MAX_OUTPUT
.local D_MAX_OUTPUT
.comm D_MAX_OUTPUT,4,4
.type D_COUNT,@object # @D_COUNT
.local D_COUNT
.comm D_COUNT,4,4
.type _Z19PIDControllerKernelPfS_S_S_S_,@object # @_Z19PIDControllerKernelPfS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z19PIDControllerKernelPfS_S_S_S_
.p2align 3, 0x0
_Z19PIDControllerKernelPfS_S_S_S_:
.quad _Z34__device_stub__PIDControllerKernelPfS_S_S_S_
.size _Z19PIDControllerKernelPfS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19PIDControllerKernelPfS_S_S_S_"
.size .L__unnamed_1, 34
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "D_PROPORTIONAL_GAIN"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "D_INTEGRAL_GAIN"
.size .L__unnamed_3, 16
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "D_DERIVATIVE_GAIN"
.size .L__unnamed_4, 18
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "D_INTEGRAL_DECAY"
.size .L__unnamed_5, 17
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "D_OFFSET"
.size .L__unnamed_6, 9
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "D_MIN_OUTPUT"
.size .L__unnamed_7, 13
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "D_MAX_OUTPUT"
.size .L__unnamed_8, 13
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "D_COUNT"
.size .L__unnamed_9, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__PIDControllerKernelPfS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym D_PROPORTIONAL_GAIN
.addrsig_sym D_INTEGRAL_GAIN
.addrsig_sym D_DERIVATIVE_GAIN
.addrsig_sym D_INTEGRAL_DECAY
.addrsig_sym D_OFFSET
.addrsig_sym D_MIN_OUTPUT
.addrsig_sym D_MAX_OUTPUT
.addrsig_sym D_COUNT
.addrsig_sym _Z19PIDControllerKernelPfS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19PIDControllerKernelPfS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x3][0x1c], PT ; /* 0x00c0070000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R0, R17, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0211 */
/*00b0*/ IMAD.WIDE R2, R0.reuse, R17.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0211 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R0, R17, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x000fe400078e0211 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ee2000c1e1900 */
/*0100*/ FADD R11, -R4, R3 ; /* 0x00000003040b7221 */
/* 0x004fc80000000100 */
/*0110*/ FFMA R13, R8, c[0x3][0xc], R11 ; /* 0x00c00300080d7a23 */
/* 0x008fe4000000000b */
/*0120*/ IMAD.WIDE R8, R0, R17, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc600078e0211 */
/*0130*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe8000c101904 */
/*0140*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea8000c1e1900 */
/*0150*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe8000c101904 */
/*0160*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ee2000c1e1900 */
/*0170*/ MOV R12, c[0x3][0x0] ; /* 0x00c00000000c7a02 */
/* 0x000fca0000000f00 */
/*0180*/ FFMA R4, R11, R12, c[0x3][0x10] ; /* 0x00c004000b047623 */
/* 0x000fe4000000000c */
/*0190*/ IMAD.WIDE R2, R0, R17, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fc800078e0211 */
/*01a0*/ FADD R10, R11, -R10 ; /* 0x8000000a0b0a7221 */
/* 0x004fe40000000000 */
/*01b0*/ FFMA R15, R15, c[0x3][0x4], R4 ; /* 0x00c001000f0f7a23 */
/* 0x008fc80000000004 */
/*01c0*/ FFMA R10, R10, c[0x3][0x8], R15 ; /* 0x00c002000a0a7a23 */
/* 0x000fca000000000f */
/*01d0*/ FSETP.GT.AND P0, PT, R10, c[0x3][0x18], PT ; /* 0x00c006000a007a0b */
/* 0x000fc80003f04000 */
/*01e0*/ FSEL R10, R10, c[0x3][0x18], !P0 ; /* 0x00c006000a0a7a08 */
/* 0x000fc80004000000 */
/*01f0*/ FSETP.GEU.AND P0, PT, R10, c[0x3][0x14], PT ; /* 0x00c005000a007a0b */
/* 0x000fc80003f0e000 */
/*0200*/ FSEL R5, R10, c[0x3][0x14], P0 ; /* 0x00c005000a057a08 */
/* 0x000fca0000000000 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19PIDControllerKernelPfS_S_S_S_
.globl _Z19PIDControllerKernelPfS_S_S_S_
.p2align 8
.type _Z19PIDControllerKernelPfS_S_S_S_,@function
_Z19PIDControllerKernelPfS_S_S_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x28
s_load_b32 s5, s[0:1], 0x34
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, D_COUNT@rel32@lo+4
s_addc_u32 s3, s3, D_COUNT@rel32@hi+12
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s4, s15
s_and_b32 s4, s5, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
global_load_b32 v4, v[6:7], off
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_INTEGRAL_DECAY@rel32@lo+4
s_addc_u32 s1, s1, D_INTEGRAL_DECAY@rel32@hi+12
s_load_b32 s0, s[0:1], 0x0
s_waitcnt vmcnt(1)
v_sub_f32_e32 v5, v2, v3
v_add_co_u32 v2, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_fma_f32 v4, s0, v4, v5
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_OFFSET@rel32@lo+4
s_addc_u32 s1, s1, D_OFFSET@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, D_PROPORTIONAL_GAIN@rel32@lo+4
s_addc_u32 s3, s3, D_PROPORTIONAL_GAIN@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, D_INTEGRAL_GAIN@rel32@lo+4
s_addc_u32 s5, s5, D_INTEGRAL_GAIN@rel32@hi+12
global_store_b32 v[6:7], v4, off
global_load_b32 v4, v[2:3], off
global_store_b32 v[2:3], v5, off
global_load_b32 v2, v[6:7], off
s_load_b32 s6, s[0:1], 0x0
s_load_b32 s7, s[2:3], 0x0
s_load_b32 s4, s[4:5], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_DERIVATIVE_GAIN@rel32@lo+4
s_addc_u32 s1, s1, D_DERIVATIVE_GAIN@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, D_MAX_OUTPUT@rel32@lo+4
s_addc_u32 s3, s3, D_MAX_OUTPUT@rel32@hi+12
s_load_b32 s5, s[0:1], 0x0
s_load_b32 s2, s[2:3], 0x0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, D_MIN_OUTPUT@rel32@lo+4
s_addc_u32 s1, s1, D_MIN_OUTPUT@rel32@hi+12
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_fma_f32 v3, v5, s7, s6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v4, v5, v4 :: v_dual_fmac_f32 v3, s4, v2
v_fmac_f32_e32 v3, s5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, s2, v3
v_cndmask_b32_e64 v2, v3, s2, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, s0, v2
v_cndmask_b32_e64 v2, v2, s0, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19PIDControllerKernelPfS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19PIDControllerKernelPfS_S_S_S_, .Lfunc_end0-_Z19PIDControllerKernelPfS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected D_PROPORTIONAL_GAIN
.type D_PROPORTIONAL_GAIN,@object
.section .bss,"aw",@nobits
.globl D_PROPORTIONAL_GAIN
.p2align 2, 0x0
D_PROPORTIONAL_GAIN:
.long 0x00000000
.size D_PROPORTIONAL_GAIN, 4
.protected D_INTEGRAL_GAIN
.type D_INTEGRAL_GAIN,@object
.globl D_INTEGRAL_GAIN
.p2align 2, 0x0
D_INTEGRAL_GAIN:
.long 0x00000000
.size D_INTEGRAL_GAIN, 4
.protected D_DERIVATIVE_GAIN
.type D_DERIVATIVE_GAIN,@object
.globl D_DERIVATIVE_GAIN
.p2align 2, 0x0
D_DERIVATIVE_GAIN:
.long 0x00000000
.size D_DERIVATIVE_GAIN, 4
.protected D_INTEGRAL_DECAY
.type D_INTEGRAL_DECAY,@object
.globl D_INTEGRAL_DECAY
.p2align 2, 0x0
D_INTEGRAL_DECAY:
.long 0x00000000
.size D_INTEGRAL_DECAY, 4
.protected D_OFFSET
.type D_OFFSET,@object
.globl D_OFFSET
.p2align 2, 0x0
D_OFFSET:
.long 0x00000000
.size D_OFFSET, 4
.protected D_MIN_OUTPUT
.type D_MIN_OUTPUT,@object
.globl D_MIN_OUTPUT
.p2align 2, 0x0
D_MIN_OUTPUT:
.long 0x00000000
.size D_MIN_OUTPUT, 4
.protected D_MAX_OUTPUT
.type D_MAX_OUTPUT,@object
.globl D_MAX_OUTPUT
.p2align 2, 0x0
D_MAX_OUTPUT:
.long 0x00000000
.size D_MAX_OUTPUT, 4
.protected D_COUNT
.type D_COUNT,@object
.globl D_COUNT
.p2align 2, 0x0
D_COUNT:
.long 0
.size D_COUNT, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym D_PROPORTIONAL_GAIN
.addrsig_sym D_INTEGRAL_GAIN
.addrsig_sym D_DERIVATIVE_GAIN
.addrsig_sym D_INTEGRAL_DECAY
.addrsig_sym D_OFFSET
.addrsig_sym D_MIN_OUTPUT
.addrsig_sym D_MAX_OUTPUT
.addrsig_sym D_COUNT
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19PIDControllerKernelPfS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19PIDControllerKernelPfS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00145fb3_00000000-6_PIDControllerKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z19PIDControllerKernelPfS_S_S_S_PfS_S_S_S_
.type _Z47__device_stub__Z19PIDControllerKernelPfS_S_S_S_PfS_S_S_S_, @function
_Z47__device_stub__Z19PIDControllerKernelPfS_S_S_S_PfS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19PIDControllerKernelPfS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z19PIDControllerKernelPfS_S_S_S_PfS_S_S_S_, .-_Z47__device_stub__Z19PIDControllerKernelPfS_S_S_S_PfS_S_S_S_
.globl _Z19PIDControllerKernelPfS_S_S_S_
.type _Z19PIDControllerKernelPfS_S_S_S_, @function
_Z19PIDControllerKernelPfS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z19PIDControllerKernelPfS_S_S_S_PfS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19PIDControllerKernelPfS_S_S_S_, .-_Z19PIDControllerKernelPfS_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19PIDControllerKernelPfS_S_S_S_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "D_PROPORTIONAL_GAIN"
.LC2:
.string "D_INTEGRAL_GAIN"
.LC3:
.string "D_DERIVATIVE_GAIN"
.LC4:
.string "D_INTEGRAL_DECAY"
.LC5:
.string "D_OFFSET"
.LC6:
.string "D_MIN_OUTPUT"
.LC7:
.string "D_MAX_OUTPUT"
.LC8:
.string "D_COUNT"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19PIDControllerKernelPfS_S_S_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL19D_PROPORTIONAL_GAIN(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL15D_INTEGRAL_GAIN(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17D_DERIVATIVE_GAIN(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16D_INTEGRAL_DECAY(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8D_OFFSET(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12D_MIN_OUTPUT(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL12D_MAX_OUTPUT(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7D_COUNT(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7D_COUNT
.comm _ZL7D_COUNT,4,4
.local _ZL12D_MAX_OUTPUT
.comm _ZL12D_MAX_OUTPUT,4,4
.local _ZL12D_MIN_OUTPUT
.comm _ZL12D_MIN_OUTPUT,4,4
.local _ZL8D_OFFSET
.comm _ZL8D_OFFSET,4,4
.local _ZL16D_INTEGRAL_DECAY
.comm _ZL16D_INTEGRAL_DECAY,4,4
.local _ZL17D_DERIVATIVE_GAIN
.comm _ZL17D_DERIVATIVE_GAIN,4,4
.local _ZL15D_INTEGRAL_GAIN
.comm _ZL15D_INTEGRAL_GAIN,4,4
.local _ZL19D_PROPORTIONAL_GAIN
.comm _ZL19D_PROPORTIONAL_GAIN,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "PIDControllerKernel.hip"
.globl _Z34__device_stub__PIDControllerKernelPfS_S_S_S_ # -- Begin function _Z34__device_stub__PIDControllerKernelPfS_S_S_S_
.p2align 4, 0x90
.type _Z34__device_stub__PIDControllerKernelPfS_S_S_S_,@function
_Z34__device_stub__PIDControllerKernelPfS_S_S_S_: # @_Z34__device_stub__PIDControllerKernelPfS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19PIDControllerKernelPfS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z34__device_stub__PIDControllerKernelPfS_S_S_S_, .Lfunc_end0-_Z34__device_stub__PIDControllerKernelPfS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19PIDControllerKernelPfS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $D_PROPORTIONAL_GAIN, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_INTEGRAL_GAIN, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_DERIVATIVE_GAIN, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_INTEGRAL_DECAY, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_OFFSET, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_MIN_OUTPUT, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_MAX_OUTPUT, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $D_COUNT, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type D_PROPORTIONAL_GAIN,@object # @D_PROPORTIONAL_GAIN
.local D_PROPORTIONAL_GAIN
.comm D_PROPORTIONAL_GAIN,4,4
.type D_INTEGRAL_GAIN,@object # @D_INTEGRAL_GAIN
.local D_INTEGRAL_GAIN
.comm D_INTEGRAL_GAIN,4,4
.type D_DERIVATIVE_GAIN,@object # @D_DERIVATIVE_GAIN
.local D_DERIVATIVE_GAIN
.comm D_DERIVATIVE_GAIN,4,4
.type D_INTEGRAL_DECAY,@object # @D_INTEGRAL_DECAY
.local D_INTEGRAL_DECAY
.comm D_INTEGRAL_DECAY,4,4
.type D_OFFSET,@object # @D_OFFSET
.local D_OFFSET
.comm D_OFFSET,4,4
.type D_MIN_OUTPUT,@object # @D_MIN_OUTPUT
.local D_MIN_OUTPUT
.comm D_MIN_OUTPUT,4,4
.type D_MAX_OUTPUT,@object # @D_MAX_OUTPUT
.local D_MAX_OUTPUT
.comm D_MAX_OUTPUT,4,4
.type D_COUNT,@object # @D_COUNT
.local D_COUNT
.comm D_COUNT,4,4
.type _Z19PIDControllerKernelPfS_S_S_S_,@object # @_Z19PIDControllerKernelPfS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z19PIDControllerKernelPfS_S_S_S_
.p2align 3, 0x0
_Z19PIDControllerKernelPfS_S_S_S_:
.quad _Z34__device_stub__PIDControllerKernelPfS_S_S_S_
.size _Z19PIDControllerKernelPfS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19PIDControllerKernelPfS_S_S_S_"
.size .L__unnamed_1, 34
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "D_PROPORTIONAL_GAIN"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "D_INTEGRAL_GAIN"
.size .L__unnamed_3, 16
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "D_DERIVATIVE_GAIN"
.size .L__unnamed_4, 18
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "D_INTEGRAL_DECAY"
.size .L__unnamed_5, 17
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "D_OFFSET"
.size .L__unnamed_6, 9
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "D_MIN_OUTPUT"
.size .L__unnamed_7, 13
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "D_MAX_OUTPUT"
.size .L__unnamed_8, 13
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "D_COUNT"
.size .L__unnamed_9, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__PIDControllerKernelPfS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym D_PROPORTIONAL_GAIN
.addrsig_sym D_INTEGRAL_GAIN
.addrsig_sym D_DERIVATIVE_GAIN
.addrsig_sym D_INTEGRAL_DECAY
.addrsig_sym D_OFFSET
.addrsig_sym D_MIN_OUTPUT
.addrsig_sym D_MAX_OUTPUT
.addrsig_sym D_COUNT
.addrsig_sym _Z19PIDControllerKernelPfS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | # define _XOPEN_SOURCE 600
# include <stdio.h>
# include <stdlib.h>
# include <unistd.h>
# include <math.h>
# include <float.h>
# include <string.h>
# include <limits.h>
# include <sys/time.h>
# include <time.h>
//# include "mpi.h"
//# include <omp.h>
//N is Total Mem to be used and the size when only one vector
//is used in a kernel
#ifndef N
#define N 2048
#endif
#define DATA_TYPE float
//N2 for kernels with two vectors
#define N2 N/2
//N3 for kernels with three vectors
#define N3 N/3
#ifndef NTIMES
#define NTIMES 10
#endif
#define NBENCH 16
#define SCALAR 0.42
# ifndef MIN
# define MIN(x,y) ((x)<(y)?(x):(y))
# endif
# ifndef MAX
# define MAX(x,y) ((x)>(y)?(x):(y))
# endif
// Some compilers require an extra keyword to recognize the "restrict" qualifier.
DATA_TYPE * __restrict__ a1, * __restrict__ b2, * __restrict__ c2, * __restrict__ d3, * __restrict__ e3, * __restrict__ f3, * __restrict__ vxmo, * __restrict__ vxmi, * __restrict__ mat_atax;
DATA_TYPE * d_a1, * d_b2, * d_c2, * d_d3, * d_e3, * d_f3;
DATA_TYPE * __restrict__ rand_list;
DATA_TYPE red_var = 0.0f;
size_t array_elements, array_elements2, array_elements3, array_bytes, array_bytes2, array_bytes3, array_bytes_vxm, array_bytes_mat_atax, array_alignment, sq_array_elements, cb_array_elements, sq_array_elements3, n_vxm;
static double avgtime[NBENCH], maxtime[NBENCH],
mintime[NBENCH];
static char *label[NBENCH] = {"Copy", "Scale",
"Add", "Triad", "Reduction", "2PStencil", "2D4PStencil", "MatxVec",
"MatMult", "Stride2", "Stride4", "Stride16", "Stride64", "Rows", "MatMultNoOpt", "Stencil"};
//Se puede eliminar o corregir
static long int bytes[NBENCH] = {
2 * sizeof(DATA_TYPE) * N,
2 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
1 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
5 * sizeof(DATA_TYPE) * N,
2 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
2 * sizeof(DATA_TYPE) * N,
8 * sizeof(DATA_TYPE) * N,
8 * sizeof(DATA_TYPE) * N,
};
/*#ifdef _OPENMP
extern int omp_get_num_threads();
#endif*/
double times[NBENCH][NTIMES];
int rank = -1;
__global__ void Kernel_Copy_CUDA ( float *b2, float *c2 )
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N2) c2[i] = b2[i];
}
void __attribute__((noinline)) Kernel_Copy( int k )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 1: Copy
Kernel_Copy_CUDA<<<(N2+32-1)/32, 32>>>(d_b2, d_c2);
/*
for (j=0; j<N2; j++)
c2[j] = b2[j];
*/
end_t = clock();
times[0][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
/*FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[0]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
fclose(logFile);*/
}
__global__ void Kernel_Scale_CUDA ( float *b2, float *c2, DATA_TYPE scalar )
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N2) c2[i] = b2[i] * scalar;
}
void __attribute__((noinline)) Kernel_Scale( int k, DATA_TYPE scalar )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 2: Scale
Kernel_Scale_CUDA<<<(N2+32-1)/32, 32>>>(d_b2, d_c2, scalar);
/*for (j=0; j<N2; j++)
c2[j] = scalar*b2[j];*/
end_t = clock();
times[1][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
/*FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[1]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
fclose(logFile);*/
}
__global__ void Kernel_Add_CUDA ( float *d3, float *e3, float *f3)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N3) f3[i] = d3[i]+e3[i];
}
void __attribute__((noinline)) Kernel_Add( int k )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 3: Add
Kernel_Add_CUDA<<<(N3+32-1)/32, 32, 32>>>(d_d3, d_e3, d_f3);
/*for (j=0; j<N3; j++)
f3[j] = d3[j]+e3[j];*/
end_t = clock();
times[2][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
/*FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N3)--F\n[",label[2]);
for(j=0; j<N3; j++)
fprintf(logFile,",%f",f3[j]);
fprintf(logFile,"]\n");
fclose(logFile);*/
}
void __attribute__((noinline)) Kernel_Triad( int k, double scalar )
{
clock_t start_t, end_t;
int j;
// kernel 4: Triad
start_t = clock();
for (j=0; j<N3; j++)
f3[j] = d3[j]+scalar*e3[j];
end_t = clock();
times[3][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N3)--F\n[",label[3]);
for(j=0; j<N3; j++)
fprintf(logFile,",%f",f3[j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//TODO hauria de funcionar
void __attribute__((noinline)) Kernel_Reduction( int k )
{
clock_t start_t, end_t;
int j;
double reduc = 0.0f;
// kernel 5: Reduction
start_t = clock();
for (j=0; j<N; j++)
reduc +=a1[j];
red_var = fmod(reduc+red_var, FLT_MAX );
end_t = clock();
times[4][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N)--reduc\n[",label[4]);
for(j=0; j<N; j++)
fprintf(logFile,",%f",reduc);
fprintf(logFile,"]\n");
fclose(logFile);
}
void __attribute__((noinline)) Kernel_2PStencil( int k )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 6: 2PStencil
for (j=1; j<N2-1; j++)
c2[j] = (b2[j-1]+b2[j+1])*0.5;
end_t = clock();
times[5][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N2-1)--C\n[",label[5]);
for(j=1; j<N2-1; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
void __attribute__((noinline)) Kernel_2D4PStencil( int k )
{
clock_t start_t, end_t;
int n = sq_array_elements;
int j, i;
start_t = clock();
// kernel 7: 2D4PStencil
for ( j=1; j < n-1; j++ )
for ( i=1; i < n-1; i++ )
c2[j*n+i] = (b2[j*n+i-1]+b2[j*n+i+1]+b2[(j-1)*n+i]+b2[(j+1)*n+i])*0.25f;
end_t = clock();
times[6][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j1<n-1)(i1<n-1)--C\n[",label[6]);
for(j=1; j<n-1; j++)
for(i=1; i<n-1; i++)
fprintf(logFile,",%f",c2[j*n+i]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//atax_1 -- from polybench
void __attribute__((noinline)) Kernel_MatxVec( int k )
{
clock_t start_t, end_t;
int i, j;
int n = n_vxm;
// kernel 9: Scatter
start_t = clock();
for (i = 0; i < n; i++)
{
vxmo[i] = 0.0;
for (j = 0; j < n; j++)
vxmo[i] = vxmo[i] + mat_atax[i*n+j] * vxmi[j];
}
end_t = clock();
times[7][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
//fprintf(logFile,"\n%d\n",n);
fprintf(logFile,"-----%s---(i<n)--vxmo\n[",label[7]);
for(i=0; i<n; i++)
fprintf(logFile,",%f",vxmo[i]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//matrixmult -- read correctly
void __attribute__((noinline)) Kernel_MatMult( int k )
{
clock_t start_t, end_t;
int i, j, z;
int n = sq_array_elements3;
// kernel 9: Scatter
start_t = clock();
for (i = 0; i < n; i++)
for (j = 0; j < n; j++)
{
d3[i*n+j] = 0.0;
for (z = 0; z < n; ++z)
d3[i*n+j] += e3[i*n+z] * f3[j*n+z];
}
end_t = clock();
times[8][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(i<n)(j<n)--D\n[",label[8]);
for(i=0; i<n; i++)
for(j=0; j<n; j++)
fprintf(logFile,",%f",d3[i*n+j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//Stride 2
void __attribute__((noinline)) Kernel_Stride2( int k )
{
clock_t start_t, end_t;
int j, i;
// kernel 10: Stride2
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*2;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[9][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[9]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
//fprintf(logFile,"Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Stride4( int k )
{
clock_t start_t, end_t;
int j, i;
// kernel 11: Stride
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*4;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[10][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[10]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");//Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Stride16( int k )
{
clock_t start_t, end_t;
int j, i;
// kernel 12: Stride16
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*16;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[11][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[11]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");//Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Stride64( int k )
{
clock_t start_t, end_t;
int n = sq_array_elements;
int j, i;
// kernel 13: Stride64
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*64;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[12][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[12]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");//Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Rows( int k )
{
clock_t start_t, end_t;
int n = sq_array_elements;
int j, i;
// kernel 14: Rows
start_t = clock();
for ( j=0; j < n; j++ )
for ( i=0; i < n; i++ )
c2[i*n+j] = b2[i*n+j];
end_t = clock();
times[13][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<n)(i<n)--C\n[",label[13]);
for(j=0; j<n; j++)
for(i=0;i<n;i++)
fprintf(logFile,",%f",c2[i*n+j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//mm_fc -- polybench
void __attribute__((noinline)) Kernel_MatMultNoOpt( int k )
{
clock_t start_t, end_t;
int i, j, z;
int n = sq_array_elements3;
// kernel 16: mm_fc
start_t = clock();
for (i = 0; i < n; i++)
for (j = 0; j < n; j++)
{
d3[i*n+j] = 0.0;
for (z = 0; z < n; ++z)
d3[i*n+j] += e3[i*n+z] * f3[z*n+j];
}
end_t = clock();
times[14][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(i<n)(j<n)--D\n[",label[14]);
for(i=0;i<n;i++)
for(j=0; j<n; j++)
fprintf(logFile,",%f",d3[i*n+j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//stencil
void __attribute__((noinline)) Kernel_Stencil( int k )
{
clock_t start_t, end_t;
int i, j, z;
int n = cb_array_elements;
int n2 = n*n;
// kernel 15: Test
start_t = clock();
for (i = 1; i < n-1; i++) {
for (j = 1; j < n-1; j++) {
for (z = 1; z < n-1; z++) {
c2[i*n2+j*n+z] = 0.125 * (b2[(i+1)*n2+j*n+z] - 2.0 * b2[i*n2+j*n+z] + b2[(i-1)*n2+j*n+z])
+ 0.125 * (b2[i*n2+(j+1)*n+z] - 2.0 * b2[i*n2+j*n+z] + b2[i*n2+(j-1)*n+z])
+ 0.125 * (b2[i*n2+j*n+(z+1)] - 2.0 * b2[i*n2+j*n+z] + b2[i*n2+j*n+(z-1)])
+ b2[i*n2+j*n+z];
}
}
}
end_t = clock();
times[15][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(i1<n-1)(j1<n-1)(z1<n-1)--C\n[",label[15]);
for(i=1; i<n-1; i++)
for(j=1; j<n-1; j++)
for(z=1; z<n-1; z++)
fprintf(logFile,",%f",c2[i*n2+j*n+z]);
fprintf(logFile,"]\n");
}
int
main(int argc, char *argv[])
{
int BytesPerWord;
int i,k;
ssize_t j;
DATA_TYPE scalar;
double t;
double *TimesByRank;
int rc, numranks = 1, myrank;
char* affinity=NULL;
affinity = argv[1];
/* --- SETUP --- call MPI_Init() before anything else! --- */
//size_matmul = sqrt(N);
// if either of these fail there is something really screwed up!
/* --- NEW FEATURE --- distribute requested storage across MPI ranks --- */
array_elements = N / numranks; // don't worry about rounding vs truncation
array_elements2 = N2 / numranks; // don't worry about rounding vs truncation
array_elements3 = N3 / numranks; // don't worry about rounding vs truncation
sq_array_elements = sqrt(N2);
sq_array_elements3 = sqrt(N3);
cb_array_elements = cbrt(N2);
n_vxm = sqrt(N+1)-1;
printf("n_vxm: %ld\n", n_vxm);
array_alignment = 64; // Can be modified -- provides partial support for adjusting relative alignment
// Dynamically allocate the three arrays using "posix_memalign()"
// NOTE that the OFFSET parameter is not used in this version of the code!
array_bytes = array_elements * sizeof(DATA_TYPE);
array_bytes2 = array_elements2 * sizeof(DATA_TYPE);
array_bytes3 = array_elements3 * sizeof(DATA_TYPE);
array_bytes_vxm = n_vxm * sizeof(DATA_TYPE);
array_bytes_mat_atax = n_vxm * n_vxm * sizeof(DATA_TYPE);
k = posix_memalign((void **)&a1, array_alignment, array_bytes);
if (k != 0) {
printf("Rank %d: Allocation of array a failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&b2, array_alignment, array_bytes2);
if (k != 0) {
printf("Rank %d: Allocation of array b2 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&c2, array_alignment, array_bytes2);
if (k != 0) {
printf("Rank %d: Allocation of array c2 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&d3, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array d3 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&e3, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array e3 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&f3, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array f3 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&rand_list, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&vxmo, array_alignment, array_bytes_vxm);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&vxmi, array_alignment, array_bytes_vxm);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&mat_atax, array_alignment, array_bytes_mat_atax);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
cudaMalloc(&d_b2, array_elements2 * sizeof(DATA_TYPE));
cudaMalloc(&d_c2, array_elements2 * sizeof(DATA_TYPE));
cudaMalloc(&d_d3, array_elements3 * sizeof(DATA_TYPE));
cudaMalloc(&d_e3, array_elements3 * sizeof(DATA_TYPE));
cudaMalloc(&d_f3, array_elements3 * sizeof(DATA_TYPE));
/* --- SETUP --- initialize arrays and estimate precision of timer --- */
for (j=0; j<N; j++) {
a1[j] = 1.0;
}
cudaMemcpy(d_a1, a1, array_bytes, cudaMemcpyHostToDevice);
for (j=0; j<N2; j++) {
b2[j] = 1.0;
c2[j] = 0.0;
}
for (j=0; j<N3; j++) {
d3[j] = 1.0;
e3[j] = 1.0;
f3[j] = 0.0;
}
for (j=0; j<n_vxm; j++){
vxmi[j] = 1.0;
vxmo[j] = 0.0;
}
for(j=0; j<n_vxm*n_vxm; j++){
mat_atax[j] = 1.0;
}
srand(0);
for (j = 0; j < N3; j++)
rand_list[j] = ((float)rand()/RAND_MAX)*N3;
//printf(" \n");
/* --- MAIN LOOP --- repeat test cases NTIMES times --- */
// This code has more barriers and timing calls than are actually needed, but
// this should not cause a problem for arrays that are large enough to satisfy
// the STREAM run rules.
// MAJOR FIX!!! Version 1.7 had the start timer for each loop *after* the
// MPI_Barrier(), when it should have been *before* the MPI_Barrier().
//
cudaMemcpy(d_b2, b2, array_bytes2, cudaMemcpyHostToDevice);
cudaMemcpy(d_c2, c2, array_bytes2, cudaMemcpyHostToDevice);
cudaMemcpy(d_d3, d3, array_bytes3, cudaMemcpyHostToDevice);
cudaMemcpy(d_e3, e3, array_bytes3, cudaMemcpyHostToDevice);
cudaMemcpy(d_f3, f3, array_bytes3, cudaMemcpyHostToDevice);
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"--------------------------------------------\n\n\n");
fclose(logFile);
scalar = SCALAR;
sleep(1);
for (k=0; k<NTIMES; k++)
Kernel_Copy( k );
for (k=0; k<NTIMES; k++)
Kernel_Scale( k, scalar );
cudaMemcpy(c2, d_c2, array_bytes2, cudaMemcpyDeviceToHost);
for (k=0; k<NTIMES; k++)
Kernel_Add( k );
cudaMemcpy(f3, d_f3, array_bytes3, cudaMemcpyDeviceToHost);
float sum =0.0;
for(k=0;k<array_elements3; k++)
{
sum+=f3[k];
}
printf("DEBUG: Final result add %f \n",sum);
for (k=0; k<NTIMES; k++)
Kernel_Triad( k, scalar );
for (k=0; k<NTIMES; k++)
Kernel_Reduction( k );
for (k=0; k<NTIMES; k++)
Kernel_2PStencil( k );
for (k=0; k<NTIMES; k++)
Kernel_2D4PStencil( k );
for (k=0; k<NTIMES; k++)
Kernel_MatxVec( k );
for (k=0; k<NTIMES; k++)
Kernel_MatMult( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride2( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride4( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride16( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride64( k );
for (k=0; k<NTIMES; k++)
Kernel_Rows( k );
for (k=0; k<NTIMES; k++)
Kernel_MatMultNoOpt( k );
for (k=0; k<NTIMES; k++)
Kernel_Stencil( k );
for(int y = 0; y < NBENCH ; y++)
{
float m = 0.0;
for(int z = 0; z <NTIMES ; z++)
{
m += times[y][z];
}
printf("DEBUG: Final Timing %s: %f seconds\n",label[y],m);
}
// --- SUMMARY ---
printf("red_var %f\n", red_var);
// Rank 0 processes all timing data
free(a1);
cudaFree(d_a1);
free(b2);
free(c2);
free(d3);
free(e3);
free(f3);
free(rand_list);
/*if (myrank == 0) {
free(TimesByRank);
}*/
//MPI_Finalize();
return(0);
} | code for sm_80
Function : _Z15Kernel_Add_CUDAPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x2a9, PT ; /* 0x000002a90600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z17Kernel_Scale_CUDAPfS_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R4, 0x3ff, PT ; /* 0x000003ff0400780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ FMUL R7, R2, c[0x0][0x170] ; /* 0x00005c0002077a20 */
/* 0x004fca0000400000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16Kernel_Copy_CUDAPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R4, 0x3ff, PT ; /* 0x000003ff0400780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | # define _XOPEN_SOURCE 600
# include <stdio.h>
# include <stdlib.h>
# include <unistd.h>
# include <math.h>
# include <float.h>
# include <string.h>
# include <limits.h>
# include <sys/time.h>
# include <time.h>
//# include "mpi.h"
//# include <omp.h>
//N is Total Mem to be used and the size when only one vector
//is used in a kernel
#ifndef N
#define N 2048
#endif
#define DATA_TYPE float
//N2 for kernels with two vectors
#define N2 N/2
//N3 for kernels with three vectors
#define N3 N/3
#ifndef NTIMES
#define NTIMES 10
#endif
#define NBENCH 16
#define SCALAR 0.42
# ifndef MIN
# define MIN(x,y) ((x)<(y)?(x):(y))
# endif
# ifndef MAX
# define MAX(x,y) ((x)>(y)?(x):(y))
# endif
// Some compilers require an extra keyword to recognize the "restrict" qualifier.
DATA_TYPE * __restrict__ a1, * __restrict__ b2, * __restrict__ c2, * __restrict__ d3, * __restrict__ e3, * __restrict__ f3, * __restrict__ vxmo, * __restrict__ vxmi, * __restrict__ mat_atax;
DATA_TYPE * d_a1, * d_b2, * d_c2, * d_d3, * d_e3, * d_f3;
DATA_TYPE * __restrict__ rand_list;
DATA_TYPE red_var = 0.0f;
size_t array_elements, array_elements2, array_elements3, array_bytes, array_bytes2, array_bytes3, array_bytes_vxm, array_bytes_mat_atax, array_alignment, sq_array_elements, cb_array_elements, sq_array_elements3, n_vxm;
static double avgtime[NBENCH], maxtime[NBENCH],
mintime[NBENCH];
static char *label[NBENCH] = {"Copy", "Scale",
"Add", "Triad", "Reduction", "2PStencil", "2D4PStencil", "MatxVec",
"MatMult", "Stride2", "Stride4", "Stride16", "Stride64", "Rows", "MatMultNoOpt", "Stencil"};
//Se puede eliminar o corregir
static long int bytes[NBENCH] = {
2 * sizeof(DATA_TYPE) * N,
2 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
1 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
5 * sizeof(DATA_TYPE) * N,
2 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
2 * sizeof(DATA_TYPE) * N,
8 * sizeof(DATA_TYPE) * N,
8 * sizeof(DATA_TYPE) * N,
};
/*#ifdef _OPENMP
extern int omp_get_num_threads();
#endif*/
double times[NBENCH][NTIMES];
int rank = -1;
__global__ void Kernel_Copy_CUDA ( float *b2, float *c2 )
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N2) c2[i] = b2[i];
}
void __attribute__((noinline)) Kernel_Copy( int k )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 1: Copy
Kernel_Copy_CUDA<<<(N2+32-1)/32, 32>>>(d_b2, d_c2);
/*
for (j=0; j<N2; j++)
c2[j] = b2[j];
*/
end_t = clock();
times[0][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
/*FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[0]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
fclose(logFile);*/
}
__global__ void Kernel_Scale_CUDA ( float *b2, float *c2, DATA_TYPE scalar )
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N2) c2[i] = b2[i] * scalar;
}
void __attribute__((noinline)) Kernel_Scale( int k, DATA_TYPE scalar )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 2: Scale
Kernel_Scale_CUDA<<<(N2+32-1)/32, 32>>>(d_b2, d_c2, scalar);
/*for (j=0; j<N2; j++)
c2[j] = scalar*b2[j];*/
end_t = clock();
times[1][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
/*FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[1]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
fclose(logFile);*/
}
__global__ void Kernel_Add_CUDA ( float *d3, float *e3, float *f3)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N3) f3[i] = d3[i]+e3[i];
}
void __attribute__((noinline)) Kernel_Add( int k )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 3: Add
Kernel_Add_CUDA<<<(N3+32-1)/32, 32, 32>>>(d_d3, d_e3, d_f3);
/*for (j=0; j<N3; j++)
f3[j] = d3[j]+e3[j];*/
end_t = clock();
times[2][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
/*FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N3)--F\n[",label[2]);
for(j=0; j<N3; j++)
fprintf(logFile,",%f",f3[j]);
fprintf(logFile,"]\n");
fclose(logFile);*/
}
void __attribute__((noinline)) Kernel_Triad( int k, double scalar )
{
clock_t start_t, end_t;
int j;
// kernel 4: Triad
start_t = clock();
for (j=0; j<N3; j++)
f3[j] = d3[j]+scalar*e3[j];
end_t = clock();
times[3][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N3)--F\n[",label[3]);
for(j=0; j<N3; j++)
fprintf(logFile,",%f",f3[j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//TODO hauria de funcionar
void __attribute__((noinline)) Kernel_Reduction( int k )
{
clock_t start_t, end_t;
int j;
double reduc = 0.0f;
// kernel 5: Reduction
start_t = clock();
for (j=0; j<N; j++)
reduc +=a1[j];
red_var = fmod(reduc+red_var, FLT_MAX );
end_t = clock();
times[4][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N)--reduc\n[",label[4]);
for(j=0; j<N; j++)
fprintf(logFile,",%f",reduc);
fprintf(logFile,"]\n");
fclose(logFile);
}
void __attribute__((noinline)) Kernel_2PStencil( int k )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 6: 2PStencil
for (j=1; j<N2-1; j++)
c2[j] = (b2[j-1]+b2[j+1])*0.5;
end_t = clock();
times[5][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N2-1)--C\n[",label[5]);
for(j=1; j<N2-1; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
void __attribute__((noinline)) Kernel_2D4PStencil( int k )
{
clock_t start_t, end_t;
int n = sq_array_elements;
int j, i;
start_t = clock();
// kernel 7: 2D4PStencil
for ( j=1; j < n-1; j++ )
for ( i=1; i < n-1; i++ )
c2[j*n+i] = (b2[j*n+i-1]+b2[j*n+i+1]+b2[(j-1)*n+i]+b2[(j+1)*n+i])*0.25f;
end_t = clock();
times[6][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j1<n-1)(i1<n-1)--C\n[",label[6]);
for(j=1; j<n-1; j++)
for(i=1; i<n-1; i++)
fprintf(logFile,",%f",c2[j*n+i]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//atax_1 -- from polybench
void __attribute__((noinline)) Kernel_MatxVec( int k )
{
clock_t start_t, end_t;
int i, j;
int n = n_vxm;
// kernel 9: Scatter
start_t = clock();
for (i = 0; i < n; i++)
{
vxmo[i] = 0.0;
for (j = 0; j < n; j++)
vxmo[i] = vxmo[i] + mat_atax[i*n+j] * vxmi[j];
}
end_t = clock();
times[7][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
//fprintf(logFile,"\n%d\n",n);
fprintf(logFile,"-----%s---(i<n)--vxmo\n[",label[7]);
for(i=0; i<n; i++)
fprintf(logFile,",%f",vxmo[i]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//matrixmult -- read correctly
void __attribute__((noinline)) Kernel_MatMult( int k )
{
clock_t start_t, end_t;
int i, j, z;
int n = sq_array_elements3;
// kernel 9: Scatter
start_t = clock();
for (i = 0; i < n; i++)
for (j = 0; j < n; j++)
{
d3[i*n+j] = 0.0;
for (z = 0; z < n; ++z)
d3[i*n+j] += e3[i*n+z] * f3[j*n+z];
}
end_t = clock();
times[8][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(i<n)(j<n)--D\n[",label[8]);
for(i=0; i<n; i++)
for(j=0; j<n; j++)
fprintf(logFile,",%f",d3[i*n+j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//Stride 2
void __attribute__((noinline)) Kernel_Stride2( int k )
{
clock_t start_t, end_t;
int j, i;
// kernel 10: Stride2
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*2;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[9][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[9]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
//fprintf(logFile,"Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Stride4( int k )
{
clock_t start_t, end_t;
int j, i;
// kernel 11: Stride
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*4;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[10][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[10]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");//Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Stride16( int k )
{
clock_t start_t, end_t;
int j, i;
// kernel 12: Stride16
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*16;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[11][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[11]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");//Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Stride64( int k )
{
clock_t start_t, end_t;
int n = sq_array_elements;
int j, i;
// kernel 13: Stride64
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*64;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[12][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[12]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");//Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Rows( int k )
{
clock_t start_t, end_t;
int n = sq_array_elements;
int j, i;
// kernel 14: Rows
start_t = clock();
for ( j=0; j < n; j++ )
for ( i=0; i < n; i++ )
c2[i*n+j] = b2[i*n+j];
end_t = clock();
times[13][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<n)(i<n)--C\n[",label[13]);
for(j=0; j<n; j++)
for(i=0;i<n;i++)
fprintf(logFile,",%f",c2[i*n+j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//mm_fc -- polybench
void __attribute__((noinline)) Kernel_MatMultNoOpt( int k )
{
clock_t start_t, end_t;
int i, j, z;
int n = sq_array_elements3;
// kernel 16: mm_fc
start_t = clock();
for (i = 0; i < n; i++)
for (j = 0; j < n; j++)
{
d3[i*n+j] = 0.0;
for (z = 0; z < n; ++z)
d3[i*n+j] += e3[i*n+z] * f3[z*n+j];
}
end_t = clock();
times[14][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(i<n)(j<n)--D\n[",label[14]);
for(i=0;i<n;i++)
for(j=0; j<n; j++)
fprintf(logFile,",%f",d3[i*n+j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//stencil
void __attribute__((noinline)) Kernel_Stencil( int k )
{
clock_t start_t, end_t;
int i, j, z;
int n = cb_array_elements;
int n2 = n*n;
// kernel 15: Test
start_t = clock();
for (i = 1; i < n-1; i++) {
for (j = 1; j < n-1; j++) {
for (z = 1; z < n-1; z++) {
c2[i*n2+j*n+z] = 0.125 * (b2[(i+1)*n2+j*n+z] - 2.0 * b2[i*n2+j*n+z] + b2[(i-1)*n2+j*n+z])
+ 0.125 * (b2[i*n2+(j+1)*n+z] - 2.0 * b2[i*n2+j*n+z] + b2[i*n2+(j-1)*n+z])
+ 0.125 * (b2[i*n2+j*n+(z+1)] - 2.0 * b2[i*n2+j*n+z] + b2[i*n2+j*n+(z-1)])
+ b2[i*n2+j*n+z];
}
}
}
end_t = clock();
times[15][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(i1<n-1)(j1<n-1)(z1<n-1)--C\n[",label[15]);
for(i=1; i<n-1; i++)
for(j=1; j<n-1; j++)
for(z=1; z<n-1; z++)
fprintf(logFile,",%f",c2[i*n2+j*n+z]);
fprintf(logFile,"]\n");
}
int
main(int argc, char *argv[])
{
int BytesPerWord;
int i,k;
ssize_t j;
DATA_TYPE scalar;
double t;
double *TimesByRank;
int rc, numranks = 1, myrank;
char* affinity=NULL;
affinity = argv[1];
/* --- SETUP --- call MPI_Init() before anything else! --- */
//size_matmul = sqrt(N);
// if either of these fail there is something really screwed up!
/* --- NEW FEATURE --- distribute requested storage across MPI ranks --- */
array_elements = N / numranks; // don't worry about rounding vs truncation
array_elements2 = N2 / numranks; // don't worry about rounding vs truncation
array_elements3 = N3 / numranks; // don't worry about rounding vs truncation
sq_array_elements = sqrt(N2);
sq_array_elements3 = sqrt(N3);
cb_array_elements = cbrt(N2);
n_vxm = sqrt(N+1)-1;
printf("n_vxm: %ld\n", n_vxm);
array_alignment = 64; // Can be modified -- provides partial support for adjusting relative alignment
// Dynamically allocate the three arrays using "posix_memalign()"
// NOTE that the OFFSET parameter is not used in this version of the code!
array_bytes = array_elements * sizeof(DATA_TYPE);
array_bytes2 = array_elements2 * sizeof(DATA_TYPE);
array_bytes3 = array_elements3 * sizeof(DATA_TYPE);
array_bytes_vxm = n_vxm * sizeof(DATA_TYPE);
array_bytes_mat_atax = n_vxm * n_vxm * sizeof(DATA_TYPE);
k = posix_memalign((void **)&a1, array_alignment, array_bytes);
if (k != 0) {
printf("Rank %d: Allocation of array a failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&b2, array_alignment, array_bytes2);
if (k != 0) {
printf("Rank %d: Allocation of array b2 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&c2, array_alignment, array_bytes2);
if (k != 0) {
printf("Rank %d: Allocation of array c2 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&d3, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array d3 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&e3, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array e3 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&f3, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array f3 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&rand_list, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&vxmo, array_alignment, array_bytes_vxm);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&vxmi, array_alignment, array_bytes_vxm);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&mat_atax, array_alignment, array_bytes_mat_atax);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
cudaMalloc(&d_b2, array_elements2 * sizeof(DATA_TYPE));
cudaMalloc(&d_c2, array_elements2 * sizeof(DATA_TYPE));
cudaMalloc(&d_d3, array_elements3 * sizeof(DATA_TYPE));
cudaMalloc(&d_e3, array_elements3 * sizeof(DATA_TYPE));
cudaMalloc(&d_f3, array_elements3 * sizeof(DATA_TYPE));
/* --- SETUP --- initialize arrays and estimate precision of timer --- */
for (j=0; j<N; j++) {
a1[j] = 1.0;
}
cudaMemcpy(d_a1, a1, array_bytes, cudaMemcpyHostToDevice);
for (j=0; j<N2; j++) {
b2[j] = 1.0;
c2[j] = 0.0;
}
for (j=0; j<N3; j++) {
d3[j] = 1.0;
e3[j] = 1.0;
f3[j] = 0.0;
}
for (j=0; j<n_vxm; j++){
vxmi[j] = 1.0;
vxmo[j] = 0.0;
}
for(j=0; j<n_vxm*n_vxm; j++){
mat_atax[j] = 1.0;
}
srand(0);
for (j = 0; j < N3; j++)
rand_list[j] = ((float)rand()/RAND_MAX)*N3;
//printf(" \n");
/* --- MAIN LOOP --- repeat test cases NTIMES times --- */
// This code has more barriers and timing calls than are actually needed, but
// this should not cause a problem for arrays that are large enough to satisfy
// the STREAM run rules.
// MAJOR FIX!!! Version 1.7 had the start timer for each loop *after* the
// MPI_Barrier(), when it should have been *before* the MPI_Barrier().
//
cudaMemcpy(d_b2, b2, array_bytes2, cudaMemcpyHostToDevice);
cudaMemcpy(d_c2, c2, array_bytes2, cudaMemcpyHostToDevice);
cudaMemcpy(d_d3, d3, array_bytes3, cudaMemcpyHostToDevice);
cudaMemcpy(d_e3, e3, array_bytes3, cudaMemcpyHostToDevice);
cudaMemcpy(d_f3, f3, array_bytes3, cudaMemcpyHostToDevice);
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"--------------------------------------------\n\n\n");
fclose(logFile);
scalar = SCALAR;
sleep(1);
for (k=0; k<NTIMES; k++)
Kernel_Copy( k );
for (k=0; k<NTIMES; k++)
Kernel_Scale( k, scalar );
cudaMemcpy(c2, d_c2, array_bytes2, cudaMemcpyDeviceToHost);
for (k=0; k<NTIMES; k++)
Kernel_Add( k );
cudaMemcpy(f3, d_f3, array_bytes3, cudaMemcpyDeviceToHost);
float sum =0.0;
for(k=0;k<array_elements3; k++)
{
sum+=f3[k];
}
printf("DEBUG: Final result add %f \n",sum);
for (k=0; k<NTIMES; k++)
Kernel_Triad( k, scalar );
for (k=0; k<NTIMES; k++)
Kernel_Reduction( k );
for (k=0; k<NTIMES; k++)
Kernel_2PStencil( k );
for (k=0; k<NTIMES; k++)
Kernel_2D4PStencil( k );
for (k=0; k<NTIMES; k++)
Kernel_MatxVec( k );
for (k=0; k<NTIMES; k++)
Kernel_MatMult( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride2( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride4( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride16( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride64( k );
for (k=0; k<NTIMES; k++)
Kernel_Rows( k );
for (k=0; k<NTIMES; k++)
Kernel_MatMultNoOpt( k );
for (k=0; k<NTIMES; k++)
Kernel_Stencil( k );
for(int y = 0; y < NBENCH ; y++)
{
float m = 0.0;
for(int z = 0; z <NTIMES ; z++)
{
m += times[y][z];
}
printf("DEBUG: Final Timing %s: %f seconds\n",label[y],m);
}
// --- SUMMARY ---
printf("red_var %f\n", red_var);
// Rank 0 processes all timing data
free(a1);
cudaFree(d_a1);
free(b2);
free(c2);
free(d3);
free(e3);
free(f3);
free(rand_list);
/*if (myrank == 0) {
free(TimesByRank);
}*/
//MPI_Finalize();
return(0);
} | # define _XOPEN_SOURCE 600
#include <hip/hip_runtime.h>
# include <stdio.h>
# include <stdlib.h>
# include <unistd.h>
# include <math.h>
# include <float.h>
# include <string.h>
# include <limits.h>
# include <sys/time.h>
# include <time.h>
//# include "mpi.h"
//# include <omp.h>
//N is Total Mem to be used and the size when only one vector
//is used in a kernel
#ifndef N
#define N 2048
#endif
#define DATA_TYPE float
//N2 for kernels with two vectors
#define N2 N/2
//N3 for kernels with three vectors
#define N3 N/3
#ifndef NTIMES
#define NTIMES 10
#endif
#define NBENCH 16
#define SCALAR 0.42
# ifndef MIN
# define MIN(x,y) ((x)<(y)?(x):(y))
# endif
# ifndef MAX
# define MAX(x,y) ((x)>(y)?(x):(y))
# endif
// Some compilers require an extra keyword to recognize the "restrict" qualifier.
DATA_TYPE * __restrict__ a1, * __restrict__ b2, * __restrict__ c2, * __restrict__ d3, * __restrict__ e3, * __restrict__ f3, * __restrict__ vxmo, * __restrict__ vxmi, * __restrict__ mat_atax;
DATA_TYPE * d_a1, * d_b2, * d_c2, * d_d3, * d_e3, * d_f3;
DATA_TYPE * __restrict__ rand_list;
DATA_TYPE red_var = 0.0f;
size_t array_elements, array_elements2, array_elements3, array_bytes, array_bytes2, array_bytes3, array_bytes_vxm, array_bytes_mat_atax, array_alignment, sq_array_elements, cb_array_elements, sq_array_elements3, n_vxm;
static double avgtime[NBENCH], maxtime[NBENCH],
mintime[NBENCH];
static char *label[NBENCH] = {"Copy", "Scale",
"Add", "Triad", "Reduction", "2PStencil", "2D4PStencil", "MatxVec",
"MatMult", "Stride2", "Stride4", "Stride16", "Stride64", "Rows", "MatMultNoOpt", "Stencil"};
//Se puede eliminar o corregir
static long int bytes[NBENCH] = {
2 * sizeof(DATA_TYPE) * N,
2 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
1 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
5 * sizeof(DATA_TYPE) * N,
2 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
2 * sizeof(DATA_TYPE) * N,
8 * sizeof(DATA_TYPE) * N,
8 * sizeof(DATA_TYPE) * N,
};
/*#ifdef _OPENMP
extern int omp_get_num_threads();
#endif*/
double times[NBENCH][NTIMES];
int rank = -1;
__global__ void Kernel_Copy_CUDA ( float *b2, float *c2 )
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N2) c2[i] = b2[i];
}
void __attribute__((noinline)) Kernel_Copy( int k )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 1: Copy
Kernel_Copy_CUDA<<<(N2+32-1)/32, 32>>>(d_b2, d_c2);
/*
for (j=0; j<N2; j++)
c2[j] = b2[j];
*/
end_t = clock();
times[0][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
/*FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[0]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
fclose(logFile);*/
}
__global__ void Kernel_Scale_CUDA ( float *b2, float *c2, DATA_TYPE scalar )
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N2) c2[i] = b2[i] * scalar;
}
void __attribute__((noinline)) Kernel_Scale( int k, DATA_TYPE scalar )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 2: Scale
Kernel_Scale_CUDA<<<(N2+32-1)/32, 32>>>(d_b2, d_c2, scalar);
/*for (j=0; j<N2; j++)
c2[j] = scalar*b2[j];*/
end_t = clock();
times[1][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
/*FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[1]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
fclose(logFile);*/
}
__global__ void Kernel_Add_CUDA ( float *d3, float *e3, float *f3)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N3) f3[i] = d3[i]+e3[i];
}
void __attribute__((noinline)) Kernel_Add( int k )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 3: Add
Kernel_Add_CUDA<<<(N3+32-1)/32, 32, 32>>>(d_d3, d_e3, d_f3);
/*for (j=0; j<N3; j++)
f3[j] = d3[j]+e3[j];*/
end_t = clock();
times[2][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
/*FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N3)--F\n[",label[2]);
for(j=0; j<N3; j++)
fprintf(logFile,",%f",f3[j]);
fprintf(logFile,"]\n");
fclose(logFile);*/
}
void __attribute__((noinline)) Kernel_Triad( int k, double scalar )
{
clock_t start_t, end_t;
int j;
// kernel 4: Triad
start_t = clock();
for (j=0; j<N3; j++)
f3[j] = d3[j]+scalar*e3[j];
end_t = clock();
times[3][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N3)--F\n[",label[3]);
for(j=0; j<N3; j++)
fprintf(logFile,",%f",f3[j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//TODO hauria de funcionar
void __attribute__((noinline)) Kernel_Reduction( int k )
{
clock_t start_t, end_t;
int j;
double reduc = 0.0f;
// kernel 5: Reduction
start_t = clock();
for (j=0; j<N; j++)
reduc +=a1[j];
red_var = fmod(reduc+red_var, FLT_MAX );
end_t = clock();
times[4][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N)--reduc\n[",label[4]);
for(j=0; j<N; j++)
fprintf(logFile,",%f",reduc);
fprintf(logFile,"]\n");
fclose(logFile);
}
void __attribute__((noinline)) Kernel_2PStencil( int k )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 6: 2PStencil
for (j=1; j<N2-1; j++)
c2[j] = (b2[j-1]+b2[j+1])*0.5;
end_t = clock();
times[5][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N2-1)--C\n[",label[5]);
for(j=1; j<N2-1; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
void __attribute__((noinline)) Kernel_2D4PStencil( int k )
{
clock_t start_t, end_t;
int n = sq_array_elements;
int j, i;
start_t = clock();
// kernel 7: 2D4PStencil
for ( j=1; j < n-1; j++ )
for ( i=1; i < n-1; i++ )
c2[j*n+i] = (b2[j*n+i-1]+b2[j*n+i+1]+b2[(j-1)*n+i]+b2[(j+1)*n+i])*0.25f;
end_t = clock();
times[6][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j1<n-1)(i1<n-1)--C\n[",label[6]);
for(j=1; j<n-1; j++)
for(i=1; i<n-1; i++)
fprintf(logFile,",%f",c2[j*n+i]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//atax_1 -- from polybench
void __attribute__((noinline)) Kernel_MatxVec( int k )
{
clock_t start_t, end_t;
int i, j;
int n = n_vxm;
// kernel 9: Scatter
start_t = clock();
for (i = 0; i < n; i++)
{
vxmo[i] = 0.0;
for (j = 0; j < n; j++)
vxmo[i] = vxmo[i] + mat_atax[i*n+j] * vxmi[j];
}
end_t = clock();
times[7][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
//fprintf(logFile,"\n%d\n",n);
fprintf(logFile,"-----%s---(i<n)--vxmo\n[",label[7]);
for(i=0; i<n; i++)
fprintf(logFile,",%f",vxmo[i]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//matrixmult -- read correctly
void __attribute__((noinline)) Kernel_MatMult( int k )
{
clock_t start_t, end_t;
int i, j, z;
int n = sq_array_elements3;
// kernel 9: Scatter
start_t = clock();
for (i = 0; i < n; i++)
for (j = 0; j < n; j++)
{
d3[i*n+j] = 0.0;
for (z = 0; z < n; ++z)
d3[i*n+j] += e3[i*n+z] * f3[j*n+z];
}
end_t = clock();
times[8][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(i<n)(j<n)--D\n[",label[8]);
for(i=0; i<n; i++)
for(j=0; j<n; j++)
fprintf(logFile,",%f",d3[i*n+j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//Stride 2
void __attribute__((noinline)) Kernel_Stride2( int k )
{
clock_t start_t, end_t;
int j, i;
// kernel 10: Stride2
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*2;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[9][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[9]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
//fprintf(logFile,"Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Stride4( int k )
{
clock_t start_t, end_t;
int j, i;
// kernel 11: Stride
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*4;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[10][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[10]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");//Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Stride16( int k )
{
clock_t start_t, end_t;
int j, i;
// kernel 12: Stride16
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*16;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[11][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[11]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");//Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Stride64( int k )
{
clock_t start_t, end_t;
int n = sq_array_elements;
int j, i;
// kernel 13: Stride64
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*64;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[12][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[12]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");//Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Rows( int k )
{
clock_t start_t, end_t;
int n = sq_array_elements;
int j, i;
// kernel 14: Rows
start_t = clock();
for ( j=0; j < n; j++ )
for ( i=0; i < n; i++ )
c2[i*n+j] = b2[i*n+j];
end_t = clock();
times[13][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<n)(i<n)--C\n[",label[13]);
for(j=0; j<n; j++)
for(i=0;i<n;i++)
fprintf(logFile,",%f",c2[i*n+j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//mm_fc -- polybench
void __attribute__((noinline)) Kernel_MatMultNoOpt( int k )
{
clock_t start_t, end_t;
int i, j, z;
int n = sq_array_elements3;
// kernel 16: mm_fc
start_t = clock();
for (i = 0; i < n; i++)
for (j = 0; j < n; j++)
{
d3[i*n+j] = 0.0;
for (z = 0; z < n; ++z)
d3[i*n+j] += e3[i*n+z] * f3[z*n+j];
}
end_t = clock();
times[14][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(i<n)(j<n)--D\n[",label[14]);
for(i=0;i<n;i++)
for(j=0; j<n; j++)
fprintf(logFile,",%f",d3[i*n+j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//stencil
void __attribute__((noinline)) Kernel_Stencil( int k )
{
clock_t start_t, end_t;
int i, j, z;
int n = cb_array_elements;
int n2 = n*n;
// kernel 15: Test
start_t = clock();
for (i = 1; i < n-1; i++) {
for (j = 1; j < n-1; j++) {
for (z = 1; z < n-1; z++) {
c2[i*n2+j*n+z] = 0.125 * (b2[(i+1)*n2+j*n+z] - 2.0 * b2[i*n2+j*n+z] + b2[(i-1)*n2+j*n+z])
+ 0.125 * (b2[i*n2+(j+1)*n+z] - 2.0 * b2[i*n2+j*n+z] + b2[i*n2+(j-1)*n+z])
+ 0.125 * (b2[i*n2+j*n+(z+1)] - 2.0 * b2[i*n2+j*n+z] + b2[i*n2+j*n+(z-1)])
+ b2[i*n2+j*n+z];
}
}
}
end_t = clock();
times[15][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(i1<n-1)(j1<n-1)(z1<n-1)--C\n[",label[15]);
for(i=1; i<n-1; i++)
for(j=1; j<n-1; j++)
for(z=1; z<n-1; z++)
fprintf(logFile,",%f",c2[i*n2+j*n+z]);
fprintf(logFile,"]\n");
}
int
main(int argc, char *argv[])
{
int BytesPerWord;
int i,k;
ssize_t j;
DATA_TYPE scalar;
double t;
double *TimesByRank;
int rc, numranks = 1, myrank;
char* affinity=NULL;
affinity = argv[1];
/* --- SETUP --- call MPI_Init() before anything else! --- */
//size_matmul = sqrt(N);
// if either of these fail there is something really screwed up!
/* --- NEW FEATURE --- distribute requested storage across MPI ranks --- */
array_elements = N / numranks; // don't worry about rounding vs truncation
array_elements2 = N2 / numranks; // don't worry about rounding vs truncation
array_elements3 = N3 / numranks; // don't worry about rounding vs truncation
sq_array_elements = sqrt(N2);
sq_array_elements3 = sqrt(N3);
cb_array_elements = cbrt(N2);
n_vxm = sqrt(N+1)-1;
printf("n_vxm: %ld\n", n_vxm);
array_alignment = 64; // Can be modified -- provides partial support for adjusting relative alignment
// Dynamically allocate the three arrays using "posix_memalign()"
// NOTE that the OFFSET parameter is not used in this version of the code!
array_bytes = array_elements * sizeof(DATA_TYPE);
array_bytes2 = array_elements2 * sizeof(DATA_TYPE);
array_bytes3 = array_elements3 * sizeof(DATA_TYPE);
array_bytes_vxm = n_vxm * sizeof(DATA_TYPE);
array_bytes_mat_atax = n_vxm * n_vxm * sizeof(DATA_TYPE);
k = posix_memalign((void **)&a1, array_alignment, array_bytes);
if (k != 0) {
printf("Rank %d: Allocation of array a failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&b2, array_alignment, array_bytes2);
if (k != 0) {
printf("Rank %d: Allocation of array b2 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&c2, array_alignment, array_bytes2);
if (k != 0) {
printf("Rank %d: Allocation of array c2 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&d3, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array d3 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&e3, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array e3 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&f3, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array f3 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&rand_list, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&vxmo, array_alignment, array_bytes_vxm);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&vxmi, array_alignment, array_bytes_vxm);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&mat_atax, array_alignment, array_bytes_mat_atax);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
hipMalloc(&d_b2, array_elements2 * sizeof(DATA_TYPE));
hipMalloc(&d_c2, array_elements2 * sizeof(DATA_TYPE));
hipMalloc(&d_d3, array_elements3 * sizeof(DATA_TYPE));
hipMalloc(&d_e3, array_elements3 * sizeof(DATA_TYPE));
hipMalloc(&d_f3, array_elements3 * sizeof(DATA_TYPE));
/* --- SETUP --- initialize arrays and estimate precision of timer --- */
for (j=0; j<N; j++) {
a1[j] = 1.0;
}
hipMemcpy(d_a1, a1, array_bytes, hipMemcpyHostToDevice);
for (j=0; j<N2; j++) {
b2[j] = 1.0;
c2[j] = 0.0;
}
for (j=0; j<N3; j++) {
d3[j] = 1.0;
e3[j] = 1.0;
f3[j] = 0.0;
}
for (j=0; j<n_vxm; j++){
vxmi[j] = 1.0;
vxmo[j] = 0.0;
}
for(j=0; j<n_vxm*n_vxm; j++){
mat_atax[j] = 1.0;
}
srand(0);
for (j = 0; j < N3; j++)
rand_list[j] = ((float)rand()/RAND_MAX)*N3;
//printf(" \n");
/* --- MAIN LOOP --- repeat test cases NTIMES times --- */
// This code has more barriers and timing calls than are actually needed, but
// this should not cause a problem for arrays that are large enough to satisfy
// the STREAM run rules.
// MAJOR FIX!!! Version 1.7 had the start timer for each loop *after* the
// MPI_Barrier(), when it should have been *before* the MPI_Barrier().
//
hipMemcpy(d_b2, b2, array_bytes2, hipMemcpyHostToDevice);
hipMemcpy(d_c2, c2, array_bytes2, hipMemcpyHostToDevice);
hipMemcpy(d_d3, d3, array_bytes3, hipMemcpyHostToDevice);
hipMemcpy(d_e3, e3, array_bytes3, hipMemcpyHostToDevice);
hipMemcpy(d_f3, f3, array_bytes3, hipMemcpyHostToDevice);
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"--------------------------------------------\n\n\n");
fclose(logFile);
scalar = SCALAR;
sleep(1);
for (k=0; k<NTIMES; k++)
Kernel_Copy( k );
for (k=0; k<NTIMES; k++)
Kernel_Scale( k, scalar );
hipMemcpy(c2, d_c2, array_bytes2, hipMemcpyDeviceToHost);
for (k=0; k<NTIMES; k++)
Kernel_Add( k );
hipMemcpy(f3, d_f3, array_bytes3, hipMemcpyDeviceToHost);
float sum =0.0;
for(k=0;k<array_elements3; k++)
{
sum+=f3[k];
}
printf("DEBUG: Final result add %f \n",sum);
for (k=0; k<NTIMES; k++)
Kernel_Triad( k, scalar );
for (k=0; k<NTIMES; k++)
Kernel_Reduction( k );
for (k=0; k<NTIMES; k++)
Kernel_2PStencil( k );
for (k=0; k<NTIMES; k++)
Kernel_2D4PStencil( k );
for (k=0; k<NTIMES; k++)
Kernel_MatxVec( k );
for (k=0; k<NTIMES; k++)
Kernel_MatMult( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride2( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride4( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride16( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride64( k );
for (k=0; k<NTIMES; k++)
Kernel_Rows( k );
for (k=0; k<NTIMES; k++)
Kernel_MatMultNoOpt( k );
for (k=0; k<NTIMES; k++)
Kernel_Stencil( k );
for(int y = 0; y < NBENCH ; y++)
{
float m = 0.0;
for(int z = 0; z <NTIMES ; z++)
{
m += times[y][z];
}
printf("DEBUG: Final Timing %s: %f seconds\n",label[y],m);
}
// --- SUMMARY ---
printf("red_var %f\n", red_var);
// Rank 0 processes all timing data
free(a1);
hipFree(d_a1);
free(b2);
free(c2);
free(d3);
free(e3);
free(f3);
free(rand_list);
/*if (myrank == 0) {
free(TimesByRank);
}*/
//MPI_Finalize();
return(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | # define _XOPEN_SOURCE 600
#include <hip/hip_runtime.h>
# include <stdio.h>
# include <stdlib.h>
# include <unistd.h>
# include <math.h>
# include <float.h>
# include <string.h>
# include <limits.h>
# include <sys/time.h>
# include <time.h>
//# include "mpi.h"
//# include <omp.h>
//N is Total Mem to be used and the size when only one vector
//is used in a kernel
#ifndef N
#define N 2048
#endif
#define DATA_TYPE float
//N2 for kernels with two vectors
#define N2 N/2
//N3 for kernels with three vectors
#define N3 N/3
#ifndef NTIMES
#define NTIMES 10
#endif
#define NBENCH 16
#define SCALAR 0.42
# ifndef MIN
# define MIN(x,y) ((x)<(y)?(x):(y))
# endif
# ifndef MAX
# define MAX(x,y) ((x)>(y)?(x):(y))
# endif
// Some compilers require an extra keyword to recognize the "restrict" qualifier.
DATA_TYPE * __restrict__ a1, * __restrict__ b2, * __restrict__ c2, * __restrict__ d3, * __restrict__ e3, * __restrict__ f3, * __restrict__ vxmo, * __restrict__ vxmi, * __restrict__ mat_atax;
DATA_TYPE * d_a1, * d_b2, * d_c2, * d_d3, * d_e3, * d_f3;
DATA_TYPE * __restrict__ rand_list;
DATA_TYPE red_var = 0.0f;
size_t array_elements, array_elements2, array_elements3, array_bytes, array_bytes2, array_bytes3, array_bytes_vxm, array_bytes_mat_atax, array_alignment, sq_array_elements, cb_array_elements, sq_array_elements3, n_vxm;
static double avgtime[NBENCH], maxtime[NBENCH],
mintime[NBENCH];
static char *label[NBENCH] = {"Copy", "Scale",
"Add", "Triad", "Reduction", "2PStencil", "2D4PStencil", "MatxVec",
"MatMult", "Stride2", "Stride4", "Stride16", "Stride64", "Rows", "MatMultNoOpt", "Stencil"};
//Se puede eliminar o corregir
static long int bytes[NBENCH] = {
2 * sizeof(DATA_TYPE) * N,
2 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
1 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
5 * sizeof(DATA_TYPE) * N,
2 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
3 * sizeof(DATA_TYPE) * N,
2 * sizeof(DATA_TYPE) * N,
8 * sizeof(DATA_TYPE) * N,
8 * sizeof(DATA_TYPE) * N,
};
/*#ifdef _OPENMP
extern int omp_get_num_threads();
#endif*/
double times[NBENCH][NTIMES];
int rank = -1;
__global__ void Kernel_Copy_CUDA ( float *b2, float *c2 )
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N2) c2[i] = b2[i];
}
void __attribute__((noinline)) Kernel_Copy( int k )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 1: Copy
Kernel_Copy_CUDA<<<(N2+32-1)/32, 32>>>(d_b2, d_c2);
/*
for (j=0; j<N2; j++)
c2[j] = b2[j];
*/
end_t = clock();
times[0][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
/*FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[0]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
fclose(logFile);*/
}
__global__ void Kernel_Scale_CUDA ( float *b2, float *c2, DATA_TYPE scalar )
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N2) c2[i] = b2[i] * scalar;
}
void __attribute__((noinline)) Kernel_Scale( int k, DATA_TYPE scalar )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 2: Scale
Kernel_Scale_CUDA<<<(N2+32-1)/32, 32>>>(d_b2, d_c2, scalar);
/*for (j=0; j<N2; j++)
c2[j] = scalar*b2[j];*/
end_t = clock();
times[1][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
/*FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[1]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
fclose(logFile);*/
}
__global__ void Kernel_Add_CUDA ( float *d3, float *e3, float *f3)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N3) f3[i] = d3[i]+e3[i];
}
void __attribute__((noinline)) Kernel_Add( int k )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 3: Add
Kernel_Add_CUDA<<<(N3+32-1)/32, 32, 32>>>(d_d3, d_e3, d_f3);
/*for (j=0; j<N3; j++)
f3[j] = d3[j]+e3[j];*/
end_t = clock();
times[2][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
/*FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N3)--F\n[",label[2]);
for(j=0; j<N3; j++)
fprintf(logFile,",%f",f3[j]);
fprintf(logFile,"]\n");
fclose(logFile);*/
}
void __attribute__((noinline)) Kernel_Triad( int k, double scalar )
{
clock_t start_t, end_t;
int j;
// kernel 4: Triad
start_t = clock();
for (j=0; j<N3; j++)
f3[j] = d3[j]+scalar*e3[j];
end_t = clock();
times[3][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N3)--F\n[",label[3]);
for(j=0; j<N3; j++)
fprintf(logFile,",%f",f3[j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//TODO hauria de funcionar
void __attribute__((noinline)) Kernel_Reduction( int k )
{
clock_t start_t, end_t;
int j;
double reduc = 0.0f;
// kernel 5: Reduction
start_t = clock();
for (j=0; j<N; j++)
reduc +=a1[j];
red_var = fmod(reduc+red_var, FLT_MAX );
end_t = clock();
times[4][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N)--reduc\n[",label[4]);
for(j=0; j<N; j++)
fprintf(logFile,",%f",reduc);
fprintf(logFile,"]\n");
fclose(logFile);
}
void __attribute__((noinline)) Kernel_2PStencil( int k )
{
clock_t start_t, end_t;
int j;
start_t = clock();
// kernel 6: 2PStencil
for (j=1; j<N2-1; j++)
c2[j] = (b2[j-1]+b2[j+1])*0.5;
end_t = clock();
times[5][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<N2-1)--C\n[",label[5]);
for(j=1; j<N2-1; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
void __attribute__((noinline)) Kernel_2D4PStencil( int k )
{
clock_t start_t, end_t;
int n = sq_array_elements;
int j, i;
start_t = clock();
// kernel 7: 2D4PStencil
for ( j=1; j < n-1; j++ )
for ( i=1; i < n-1; i++ )
c2[j*n+i] = (b2[j*n+i-1]+b2[j*n+i+1]+b2[(j-1)*n+i]+b2[(j+1)*n+i])*0.25f;
end_t = clock();
times[6][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j1<n-1)(i1<n-1)--C\n[",label[6]);
for(j=1; j<n-1; j++)
for(i=1; i<n-1; i++)
fprintf(logFile,",%f",c2[j*n+i]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//atax_1 -- from polybench
void __attribute__((noinline)) Kernel_MatxVec( int k )
{
clock_t start_t, end_t;
int i, j;
int n = n_vxm;
// kernel 9: Scatter
start_t = clock();
for (i = 0; i < n; i++)
{
vxmo[i] = 0.0;
for (j = 0; j < n; j++)
vxmo[i] = vxmo[i] + mat_atax[i*n+j] * vxmi[j];
}
end_t = clock();
times[7][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
//fprintf(logFile,"\n%d\n",n);
fprintf(logFile,"-----%s---(i<n)--vxmo\n[",label[7]);
for(i=0; i<n; i++)
fprintf(logFile,",%f",vxmo[i]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//matrixmult -- read correctly
void __attribute__((noinline)) Kernel_MatMult( int k )
{
clock_t start_t, end_t;
int i, j, z;
int n = sq_array_elements3;
// kernel 9: Scatter
start_t = clock();
for (i = 0; i < n; i++)
for (j = 0; j < n; j++)
{
d3[i*n+j] = 0.0;
for (z = 0; z < n; ++z)
d3[i*n+j] += e3[i*n+z] * f3[j*n+z];
}
end_t = clock();
times[8][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(i<n)(j<n)--D\n[",label[8]);
for(i=0; i<n; i++)
for(j=0; j<n; j++)
fprintf(logFile,",%f",d3[i*n+j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//Stride 2
void __attribute__((noinline)) Kernel_Stride2( int k )
{
clock_t start_t, end_t;
int j, i;
// kernel 10: Stride2
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*2;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[9][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[9]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");
//fprintf(logFile,"Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Stride4( int k )
{
clock_t start_t, end_t;
int j, i;
// kernel 11: Stride
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*4;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[10][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[10]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");//Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Stride16( int k )
{
clock_t start_t, end_t;
int j, i;
// kernel 12: Stride16
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*16;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[11][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[11]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");//Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Stride64( int k )
{
clock_t start_t, end_t;
int n = sq_array_elements;
int j, i;
// kernel 13: Stride64
start_t = clock();
for ( j=0; j < N2; j++ )
{
unsigned long int index = j*64;
index = (index+(unsigned long int)(index/N2))%N2;
c2[index] = b2[index];
}
end_t = clock();
times[12][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s-----C\n[",label[12]);
for(j=0; j<N2; j++)
fprintf(logFile,",%f",c2[j]);
fprintf(logFile,"]\n");//Index[%d]\n",index);
fclose(logFile);
}
void __attribute__((noinline)) Kernel_Rows( int k )
{
clock_t start_t, end_t;
int n = sq_array_elements;
int j, i;
// kernel 14: Rows
start_t = clock();
for ( j=0; j < n; j++ )
for ( i=0; i < n; i++ )
c2[i*n+j] = b2[i*n+j];
end_t = clock();
times[13][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(j<n)(i<n)--C\n[",label[13]);
for(j=0; j<n; j++)
for(i=0;i<n;i++)
fprintf(logFile,",%f",c2[i*n+j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//mm_fc -- polybench
void __attribute__((noinline)) Kernel_MatMultNoOpt( int k )
{
clock_t start_t, end_t;
int i, j, z;
int n = sq_array_elements3;
// kernel 16: mm_fc
start_t = clock();
for (i = 0; i < n; i++)
for (j = 0; j < n; j++)
{
d3[i*n+j] = 0.0;
for (z = 0; z < n; ++z)
d3[i*n+j] += e3[i*n+z] * f3[z*n+j];
}
end_t = clock();
times[14][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(i<n)(j<n)--D\n[",label[14]);
for(i=0;i<n;i++)
for(j=0; j<n; j++)
fprintf(logFile,",%f",d3[i*n+j]);
fprintf(logFile,"]\n");
fclose(logFile);
}
//stencil
void __attribute__((noinline)) Kernel_Stencil( int k )
{
clock_t start_t, end_t;
int i, j, z;
int n = cb_array_elements;
int n2 = n*n;
// kernel 15: Test
start_t = clock();
for (i = 1; i < n-1; i++) {
for (j = 1; j < n-1; j++) {
for (z = 1; z < n-1; z++) {
c2[i*n2+j*n+z] = 0.125 * (b2[(i+1)*n2+j*n+z] - 2.0 * b2[i*n2+j*n+z] + b2[(i-1)*n2+j*n+z])
+ 0.125 * (b2[i*n2+(j+1)*n+z] - 2.0 * b2[i*n2+j*n+z] + b2[i*n2+(j-1)*n+z])
+ 0.125 * (b2[i*n2+j*n+(z+1)] - 2.0 * b2[i*n2+j*n+z] + b2[i*n2+j*n+(z-1)])
+ b2[i*n2+j*n+z];
}
}
}
end_t = clock();
times[15][k] = (double)(end_t - start_t) / CLOCKS_PER_SEC;
//Out
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"-----%s---(i1<n-1)(j1<n-1)(z1<n-1)--C\n[",label[15]);
for(i=1; i<n-1; i++)
for(j=1; j<n-1; j++)
for(z=1; z<n-1; z++)
fprintf(logFile,",%f",c2[i*n2+j*n+z]);
fprintf(logFile,"]\n");
}
int
main(int argc, char *argv[])
{
int BytesPerWord;
int i,k;
ssize_t j;
DATA_TYPE scalar;
double t;
double *TimesByRank;
int rc, numranks = 1, myrank;
char* affinity=NULL;
affinity = argv[1];
/* --- SETUP --- call MPI_Init() before anything else! --- */
//size_matmul = sqrt(N);
// if either of these fail there is something really screwed up!
/* --- NEW FEATURE --- distribute requested storage across MPI ranks --- */
array_elements = N / numranks; // don't worry about rounding vs truncation
array_elements2 = N2 / numranks; // don't worry about rounding vs truncation
array_elements3 = N3 / numranks; // don't worry about rounding vs truncation
sq_array_elements = sqrt(N2);
sq_array_elements3 = sqrt(N3);
cb_array_elements = cbrt(N2);
n_vxm = sqrt(N+1)-1;
printf("n_vxm: %ld\n", n_vxm);
array_alignment = 64; // Can be modified -- provides partial support for adjusting relative alignment
// Dynamically allocate the three arrays using "posix_memalign()"
// NOTE that the OFFSET parameter is not used in this version of the code!
array_bytes = array_elements * sizeof(DATA_TYPE);
array_bytes2 = array_elements2 * sizeof(DATA_TYPE);
array_bytes3 = array_elements3 * sizeof(DATA_TYPE);
array_bytes_vxm = n_vxm * sizeof(DATA_TYPE);
array_bytes_mat_atax = n_vxm * n_vxm * sizeof(DATA_TYPE);
k = posix_memalign((void **)&a1, array_alignment, array_bytes);
if (k != 0) {
printf("Rank %d: Allocation of array a failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&b2, array_alignment, array_bytes2);
if (k != 0) {
printf("Rank %d: Allocation of array b2 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&c2, array_alignment, array_bytes2);
if (k != 0) {
printf("Rank %d: Allocation of array c2 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&d3, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array d3 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&e3, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array e3 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&f3, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array f3 failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&rand_list, array_alignment, array_bytes3);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&vxmo, array_alignment, array_bytes_vxm);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&vxmi, array_alignment, array_bytes_vxm);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
k = posix_memalign((void **)&mat_atax, array_alignment, array_bytes_mat_atax);
if (k != 0) {
printf("Rank %d: Allocation of array rand_list failed, return code is %d\n",myrank,k);
exit(1);
}
hipMalloc(&d_b2, array_elements2 * sizeof(DATA_TYPE));
hipMalloc(&d_c2, array_elements2 * sizeof(DATA_TYPE));
hipMalloc(&d_d3, array_elements3 * sizeof(DATA_TYPE));
hipMalloc(&d_e3, array_elements3 * sizeof(DATA_TYPE));
hipMalloc(&d_f3, array_elements3 * sizeof(DATA_TYPE));
/* --- SETUP --- initialize arrays and estimate precision of timer --- */
for (j=0; j<N; j++) {
a1[j] = 1.0;
}
hipMemcpy(d_a1, a1, array_bytes, hipMemcpyHostToDevice);
for (j=0; j<N2; j++) {
b2[j] = 1.0;
c2[j] = 0.0;
}
for (j=0; j<N3; j++) {
d3[j] = 1.0;
e3[j] = 1.0;
f3[j] = 0.0;
}
for (j=0; j<n_vxm; j++){
vxmi[j] = 1.0;
vxmo[j] = 0.0;
}
for(j=0; j<n_vxm*n_vxm; j++){
mat_atax[j] = 1.0;
}
srand(0);
for (j = 0; j < N3; j++)
rand_list[j] = ((float)rand()/RAND_MAX)*N3;
//printf(" \n");
/* --- MAIN LOOP --- repeat test cases NTIMES times --- */
// This code has more barriers and timing calls than are actually needed, but
// this should not cause a problem for arrays that are large enough to satisfy
// the STREAM run rules.
// MAJOR FIX!!! Version 1.7 had the start timer for each loop *after* the
// MPI_Barrier(), when it should have been *before* the MPI_Barrier().
//
hipMemcpy(d_b2, b2, array_bytes2, hipMemcpyHostToDevice);
hipMemcpy(d_c2, c2, array_bytes2, hipMemcpyHostToDevice);
hipMemcpy(d_d3, d3, array_bytes3, hipMemcpyHostToDevice);
hipMemcpy(d_e3, e3, array_bytes3, hipMemcpyHostToDevice);
hipMemcpy(d_f3, f3, array_bytes3, hipMemcpyHostToDevice);
FILE *logFile = fopen("results.txt","a");
fprintf(logFile,"--------------------------------------------\n\n\n");
fclose(logFile);
scalar = SCALAR;
sleep(1);
for (k=0; k<NTIMES; k++)
Kernel_Copy( k );
for (k=0; k<NTIMES; k++)
Kernel_Scale( k, scalar );
hipMemcpy(c2, d_c2, array_bytes2, hipMemcpyDeviceToHost);
for (k=0; k<NTIMES; k++)
Kernel_Add( k );
hipMemcpy(f3, d_f3, array_bytes3, hipMemcpyDeviceToHost);
float sum =0.0;
for(k=0;k<array_elements3; k++)
{
sum+=f3[k];
}
printf("DEBUG: Final result add %f \n",sum);
for (k=0; k<NTIMES; k++)
Kernel_Triad( k, scalar );
for (k=0; k<NTIMES; k++)
Kernel_Reduction( k );
for (k=0; k<NTIMES; k++)
Kernel_2PStencil( k );
for (k=0; k<NTIMES; k++)
Kernel_2D4PStencil( k );
for (k=0; k<NTIMES; k++)
Kernel_MatxVec( k );
for (k=0; k<NTIMES; k++)
Kernel_MatMult( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride2( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride4( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride16( k );
for (k=0; k<NTIMES; k++)
Kernel_Stride64( k );
for (k=0; k<NTIMES; k++)
Kernel_Rows( k );
for (k=0; k<NTIMES; k++)
Kernel_MatMultNoOpt( k );
for (k=0; k<NTIMES; k++)
Kernel_Stencil( k );
for(int y = 0; y < NBENCH ; y++)
{
float m = 0.0;
for(int z = 0; z <NTIMES ; z++)
{
m += times[y][z];
}
printf("DEBUG: Final Timing %s: %f seconds\n",label[y],m);
}
// --- SUMMARY ---
printf("red_var %f\n", red_var);
// Rank 0 processes all timing data
free(a1);
hipFree(d_a1);
free(b2);
free(c2);
free(d3);
free(e3);
free(f3);
free(rand_list);
/*if (myrank == 0) {
free(TimesByRank);
}*/
//MPI_Finalize();
return(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16Kernel_Copy_CUDAPfS_
.globl _Z16Kernel_Copy_CUDAPfS_
.p2align 8
.type _Z16Kernel_Copy_CUDAPfS_,@function
_Z16Kernel_Copy_CUDAPfS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x400, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16Kernel_Copy_CUDAPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16Kernel_Copy_CUDAPfS_, .Lfunc_end0-_Z16Kernel_Copy_CUDAPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17Kernel_Scale_CUDAPfS_f
.globl _Z17Kernel_Scale_CUDAPfS_f
.p2align 8
.type _Z17Kernel_Scale_CUDAPfS_f,@function
_Z17Kernel_Scale_CUDAPfS_f:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x400, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17Kernel_Scale_CUDAPfS_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17Kernel_Scale_CUDAPfS_f, .Lfunc_end1-_Z17Kernel_Scale_CUDAPfS_f
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15Kernel_Add_CUDAPfS_S_
.globl _Z15Kernel_Add_CUDAPfS_S_
.p2align 8
.type _Z15Kernel_Add_CUDAPfS_S_,@function
_Z15Kernel_Add_CUDAPfS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x2aa, v1
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15Kernel_Add_CUDAPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15Kernel_Add_CUDAPfS_S_, .Lfunc_end2-_Z15Kernel_Add_CUDAPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16Kernel_Copy_CUDAPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16Kernel_Copy_CUDAPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17Kernel_Scale_CUDAPfS_f
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17Kernel_Scale_CUDAPfS_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15Kernel_Add_CUDAPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15Kernel_Add_CUDAPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15Kernel_Add_CUDAPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x2a9, PT ; /* 0x000002a90600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z17Kernel_Scale_CUDAPfS_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R4, 0x3ff, PT ; /* 0x000003ff0400780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*00b0*/ FMUL R7, R2, c[0x0][0x170] ; /* 0x00005c0002077a20 */
/* 0x004fca0000400000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16Kernel_Copy_CUDAPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R4, 0x3ff, PT ; /* 0x000003ff0400780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16Kernel_Copy_CUDAPfS_
.globl _Z16Kernel_Copy_CUDAPfS_
.p2align 8
.type _Z16Kernel_Copy_CUDAPfS_,@function
_Z16Kernel_Copy_CUDAPfS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x400, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16Kernel_Copy_CUDAPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16Kernel_Copy_CUDAPfS_, .Lfunc_end0-_Z16Kernel_Copy_CUDAPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17Kernel_Scale_CUDAPfS_f
.globl _Z17Kernel_Scale_CUDAPfS_f
.p2align 8
.type _Z17Kernel_Scale_CUDAPfS_f,@function
_Z17Kernel_Scale_CUDAPfS_f:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x400, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17Kernel_Scale_CUDAPfS_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17Kernel_Scale_CUDAPfS_f, .Lfunc_end1-_Z17Kernel_Scale_CUDAPfS_f
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15Kernel_Add_CUDAPfS_S_
.globl _Z15Kernel_Add_CUDAPfS_S_
.p2align 8
.type _Z15Kernel_Add_CUDAPfS_S_,@function
_Z15Kernel_Add_CUDAPfS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x2aa, v1
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15Kernel_Add_CUDAPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15Kernel_Add_CUDAPfS_S_, .Lfunc_end2-_Z15Kernel_Add_CUDAPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16Kernel_Copy_CUDAPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16Kernel_Copy_CUDAPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17Kernel_Scale_CUDAPfS_f
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17Kernel_Scale_CUDAPfS_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15Kernel_Add_CUDAPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15Kernel_Add_CUDAPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void NewNodeConnectionKernel( int f, int q, int r, int *activityFlag, int *connection, int *age, float *localError, float alfa, int maxCells, float errorFraction )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < 1)
{
activityFlag[r] = 1;
connection[q * maxCells + f] = 0;
age[q * maxCells + f] = 0;
connection[f * maxCells + q] = 0;
age[f * maxCells + q] = 0;
connection[q * maxCells + r] = 1;
age[q * maxCells + r] = 0;
connection[r * maxCells + q] = 1;
age[r * maxCells + q] = 0;
connection[f * maxCells + r] = 1;
age[f * maxCells + r] = 0;
connection[r * maxCells + f] = 1;
age[r * maxCells + f] = 0;
localError[q] -= alfa * localError[q];
localError[f] -= alfa * localError[f];
localError[r] = errorFraction * (localError[q] + localError[f]);
}
} | code for sm_80
Function : _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f04270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R5, c[0x0][0x194] ; /* 0x0000650000057a02 */
/* 0x000fe20000000f00 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff027435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R4, c[0x0][0x164] ; /* 0x0000590000047a02 */
/* 0x000fe20000000f00 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ MOV R0, c[0x0][0x168] ; /* 0x00005a0000007a02 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD R12, R5, R4, c[0x0][0x160] ; /* 0x00005800050c7624 */
/* 0x000fe400078e0204 */
/*0100*/ IMAD.WIDE R8, R3, R0, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e0200 */
/*0110*/ IMAD R16, R5, c[0x0][0x160], R4 ; /* 0x0000580005107a24 */
/* 0x000fe200078e0204 */
/*0120*/ STG.E [R8.64], R2 ; /* 0x0000000208007986 */
/* 0x0001e2000c101904 */
/*0130*/ IMAD.WIDE R10, R12, R3, c[0x0][0x178] ; /* 0x00005e000c0a7625 */
/* 0x000fc800078e0203 */
/*0140*/ IMAD R20, R5, R4, c[0x0][0x168] ; /* 0x00005a0005147624 */
/* 0x000fe200078e0204 */
/*0150*/ STG.E [R10.64], RZ ; /* 0x000000ff0a007986 */
/* 0x0003e2000c101904 */
/*0160*/ IMAD.WIDE R12, R12, R3, c[0x0][0x180] ; /* 0x000060000c0c7625 */
/* 0x000fc800078e0203 */
/*0170*/ IMAD R22, R5, c[0x0][0x168], R4 ; /* 0x00005a0005167a24 */
/* 0x000fe200078e0204 */
/*0180*/ STG.E [R12.64], RZ ; /* 0x000000ff0c007986 */
/* 0x0005e2000c101904 */
/*0190*/ IMAD.WIDE R14, R16, R3, c[0x0][0x178] ; /* 0x00005e00100e7625 */
/* 0x000fc800078e0203 */
/*01a0*/ IMAD.WIDE R16, R16, R3.reuse, c[0x0][0x180] ; /* 0x0000600010107625 */
/* 0x080fe200078e0203 */
/*01b0*/ STG.E [R14.64], RZ ; /* 0x000000ff0e007986 */
/* 0x0007e6000c101904 */
/*01c0*/ IMAD.WIDE R18, R20.reuse, R3.reuse, c[0x0][0x178] ; /* 0x00005e0014127625 */
/* 0x0c0fe200078e0203 */
/*01d0*/ STG.E [R16.64], RZ ; /* 0x000000ff10007986 */
/* 0x0009e6000c101904 */
/*01e0*/ IMAD.WIDE R8, R20, R3.reuse, c[0x0][0x180] ; /* 0x0000600014087625 */
/* 0x081fe200078e0203 */
/*01f0*/ STG.E [R18.64], R2 ; /* 0x0000000212007986 */
/* 0x000fe6000c101904 */
/*0200*/ IMAD R24, R5, R6, c[0x0][0x168] ; /* 0x00005a0005187624 */
/* 0x000fe200078e0206 */
/*0210*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x0001e2000c101904 */
/*0220*/ IMAD.WIDE R20, R22, R3, c[0x0][0x178] ; /* 0x00005e0016147625 */
/* 0x000fc800078e0203 */
/*0230*/ IMAD.WIDE R10, R22, R3.reuse, c[0x0][0x180] ; /* 0x00006000160a7625 */
/* 0x082fe200078e0203 */
/*0240*/ STG.E [R20.64], R2 ; /* 0x0000000214007986 */
/* 0x000fe6000c101904 */
/*0250*/ IMAD R22, R5, c[0x0][0x168], R6 ; /* 0x00005a0005167a24 */
/* 0x000fe200078e0206 */
/*0260*/ STG.E [R10.64], RZ ; /* 0x000000ff0a007986 */
/* 0x0003e2000c101904 */
/*0270*/ IMAD.WIDE R12, R24, R3, c[0x0][0x178] ; /* 0x00005e00180c7625 */
/* 0x004fc800078e0203 */
/*0280*/ IMAD.WIDE R14, R24, R3.reuse, c[0x0][0x180] ; /* 0x00006000180e7625 */
/* 0x088fe200078e0203 */
/*0290*/ STG.E [R12.64], R2 ; /* 0x000000020c007986 */
/* 0x000fe6000c101904 */
/*02a0*/ IMAD.WIDE R16, R22.reuse, R3.reuse, c[0x0][0x178] ; /* 0x00005e0016107625 */
/* 0x0d0fe200078e0203 */
/*02b0*/ STG.E [R14.64], RZ ; /* 0x000000ff0e007986 */
/* 0x000fe6000c101904 */
/*02c0*/ IMAD.WIDE R22, R22, R3, c[0x0][0x180] ; /* 0x0000600016167625 */
/* 0x000fe200078e0203 */
/*02d0*/ STG.E [R16.64], R2 ; /* 0x0000000210007986 */
/* 0x0005e6000c101904 */
/*02e0*/ IMAD.WIDE R4, R3, R4, c[0x0][0x188] ; /* 0x0000620003047625 */
/* 0x000fe200078e0204 */
/*02f0*/ STG.E [R22.64], RZ ; /* 0x000000ff16007986 */
/* 0x000fe8000c101904 */
/*0300*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000e24000c1e1900 */
/*0310*/ FFMA R9, -R7, c[0x0][0x190], R7 ; /* 0x0000640007097a23 */
/* 0x001fc40000000107 */
/*0320*/ IMAD.WIDE R6, R3, R6, c[0x0][0x188] ; /* 0x0000620003067625 */
/* 0x000fc600078e0206 */
/*0330*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101904 */
/*0340*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000e64000c1e1900 */
/*0350*/ FFMA R11, -R8, c[0x0][0x190], R8 ; /* 0x00006400080b7a23 */
/* 0x002fca0000000108 */
/*0360*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101904 */
/*0370*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee2000c1e1900 */
/*0380*/ IMAD.WIDE R2, R3, R0, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x004fc800078e0200 */
/*0390*/ FADD R8, R11, R8 ; /* 0x000000080b087221 */
/* 0x008fc80000000000 */
/*03a0*/ FMUL R13, R8, c[0x0][0x198] ; /* 0x00006600080d7a20 */
/* 0x000fca0000400000 */
/*03b0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void NewNodeConnectionKernel( int f, int q, int r, int *activityFlag, int *connection, int *age, float *localError, float alfa, int maxCells, float errorFraction )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < 1)
{
activityFlag[r] = 1;
connection[q * maxCells + f] = 0;
age[q * maxCells + f] = 0;
connection[f * maxCells + q] = 0;
age[f * maxCells + q] = 0;
connection[q * maxCells + r] = 1;
age[q * maxCells + r] = 0;
connection[r * maxCells + q] = 1;
age[r * maxCells + q] = 0;
connection[f * maxCells + r] = 1;
age[f * maxCells + r] = 0;
connection[r * maxCells + f] = 1;
age[r * maxCells + f] = 0;
localError[q] -= alfa * localError[q];
localError[f] -= alfa * localError[f];
localError[r] = errorFraction * (localError[q] + localError[f]);
}
} | .file "tmpxft_001b5244_00000000-6_NewNodeConnectionKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z23NewNodeConnectionKerneliiiPiS_S_PffifiiiPiS_S_Pffif
.type _Z55__device_stub__Z23NewNodeConnectionKerneliiiPiS_S_PffifiiiPiS_S_Pffif, @function
_Z55__device_stub__Z23NewNodeConnectionKerneliiiPiS_S_PffifiiiPiS_S_Pffif:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movq %rcx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movss %xmm0, 48(%rsp)
movss %xmm1, 12(%rsp)
movq 240(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z23NewNodeConnectionKerneliiiPiS_S_Pffif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z23NewNodeConnectionKerneliiiPiS_S_PffifiiiPiS_S_Pffif, .-_Z55__device_stub__Z23NewNodeConnectionKerneliiiPiS_S_PffifiiiPiS_S_Pffif
.globl _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.type _Z23NewNodeConnectionKerneliiiPiS_S_Pffif, @function
_Z23NewNodeConnectionKerneliiiPiS_S_Pffif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z23NewNodeConnectionKerneliiiPiS_S_PffifiiiPiS_S_Pffif
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23NewNodeConnectionKerneliiiPiS_S_Pffif, .-_Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23NewNodeConnectionKerneliiiPiS_S_Pffif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23NewNodeConnectionKerneliiiPiS_S_Pffif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void NewNodeConnectionKernel( int f, int q, int r, int *activityFlag, int *connection, int *age, float *localError, float alfa, int maxCells, float errorFraction )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < 1)
{
activityFlag[r] = 1;
connection[q * maxCells + f] = 0;
age[q * maxCells + f] = 0;
connection[f * maxCells + q] = 0;
age[f * maxCells + q] = 0;
connection[q * maxCells + r] = 1;
age[q * maxCells + r] = 0;
connection[r * maxCells + q] = 1;
age[r * maxCells + q] = 0;
connection[f * maxCells + r] = 1;
age[f * maxCells + r] = 0;
connection[r * maxCells + f] = 1;
age[r * maxCells + f] = 0;
localError[q] -= alfa * localError[q];
localError[f] -= alfa * localError[f];
localError[r] = errorFraction * (localError[q] + localError[f]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NewNodeConnectionKernel( int f, int q, int r, int *activityFlag, int *connection, int *age, float *localError, float alfa, int maxCells, float errorFraction )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < 1)
{
activityFlag[r] = 1;
connection[q * maxCells + f] = 0;
age[q * maxCells + f] = 0;
connection[f * maxCells + q] = 0;
age[f * maxCells + q] = 0;
connection[q * maxCells + r] = 1;
age[q * maxCells + r] = 0;
connection[r * maxCells + q] = 1;
age[r * maxCells + q] = 0;
connection[f * maxCells + r] = 1;
age[f * maxCells + r] = 0;
connection[r * maxCells + f] = 1;
age[r * maxCells + f] = 0;
localError[q] -= alfa * localError[q];
localError[f] -= alfa * localError[f];
localError[r] = errorFraction * (localError[q] + localError[f]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NewNodeConnectionKernel( int f, int q, int r, int *activityFlag, int *connection, int *age, float *localError, float alfa, int maxCells, float errorFraction )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < 1)
{
activityFlag[r] = 1;
connection[q * maxCells + f] = 0;
age[q * maxCells + f] = 0;
connection[f * maxCells + q] = 0;
age[f * maxCells + q] = 0;
connection[q * maxCells + r] = 1;
age[q * maxCells + r] = 0;
connection[r * maxCells + q] = 1;
age[r * maxCells + q] = 0;
connection[f * maxCells + r] = 1;
age[f * maxCells + r] = 0;
connection[r * maxCells + f] = 1;
age[r * maxCells + f] = 0;
localError[q] -= alfa * localError[q];
localError[f] -= alfa * localError[f];
localError[r] = errorFraction * (localError[q] + localError[f]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.globl _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.p2align 8
.type _Z23NewNodeConnectionKerneliiiPiS_S_Pffif,@function
_Z23NewNodeConnectionKerneliiiPiS_S_Pffif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x40
s_load_b32 s3, s[0:1], 0x4c
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 1, v1
s_cbranch_execz .LBB0_2
s_clause 0x4
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s24, s[0:1], 0x8
s_load_b64 s[12:13], s[0:1], 0x30
s_load_b256 s[4:11], s[0:1], 0x10
s_load_b32 s33, s[0:1], 0x38
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, 1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s15, s2, 31
s_ashr_i32 s25, s24, 31
s_ashr_i32 s17, s3, 31
s_lshl_b64 s[0:1], s[24:25], 2
s_mul_i32 s14, s13, s3
s_add_u32 s4, s4, s0
s_addc_u32 s5, s5, s1
s_add_i32 s18, s14, s2
s_mul_i32 s16, s13, s2
s_ashr_i32 s19, s18, 31
s_mul_i32 s13, s13, s24
s_lshl_b64 s[18:19], s[18:19], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s20, s6, s18
s_addc_u32 s21, s7, s19
s_add_u32 s18, s8, s18
s_addc_u32 s19, s9, s19
s_add_i32 s22, s16, s3
s_ashr_i32 s23, s22, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[26:27], s[22:23], 2
s_add_u32 s22, s6, s26
s_addc_u32 s23, s7, s27
s_add_u32 s26, s8, s26
s_addc_u32 s27, s9, s27
s_add_i32 s28, s14, s24
s_mov_b32 s14, s2
s_ashr_i32 s29, s28, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[28:29], s[28:29], 2
s_add_u32 s30, s6, s28
s_addc_u32 s31, s7, s29
s_add_u32 s28, s8, s28
s_addc_u32 s29, s9, s29
s_add_i32 s34, s13, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s35, s34, 31
s_lshl_b64 s[34:35], s[34:35], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s36, s6, s34
s_addc_u32 s37, s7, s35
s_add_u32 s34, s8, s34
s_addc_u32 s35, s9, s35
s_add_i32 s24, s16, s24
s_mov_b32 s16, s3
s_ashr_i32 s25, s24, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[24:25], s[24:25], 2
s_add_u32 s38, s6, s24
s_addc_u32 s39, s7, s25
s_add_u32 s24, s8, s24
s_addc_u32 s25, s9, s25
s_add_i32 s40, s13, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s41, s40, 31
s_lshl_b64 s[40:41], s[40:41], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s6, s6, s40
s_addc_u32 s7, s7, s41
s_add_u32 s8, s8, s40
s_addc_u32 s9, s9, s41
s_lshl_b64 s[16:17], s[16:17], 2
s_add_u32 s16, s10, s16
s_addc_u32 s17, s11, s17
s_load_b32 s3, s[16:17], 0x0
s_waitcnt lgkmcnt(0)
v_fma_f32 v1, -s3, s12, s3
s_lshl_b64 s[2:3], s[14:15], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s10, s2
s_addc_u32 s3, s11, s3
global_store_b32 v0, v1, s[16:17]
global_load_b32 v1, v0, s[2:3]
s_add_u32 s0, s10, s0
s_addc_u32 s1, s11, s1
s_waitcnt vmcnt(0)
v_fma_f32 v1, -v1, s12, v1
global_store_b32 v0, v1, s[2:3]
global_load_b32 v2, v0, s[16:17]
s_clause 0x1
global_store_b32 v0, v3, s[4:5]
global_store_b32 v0, v0, s[20:21]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, s33, v1
s_clause 0xb
global_store_b32 v0, v0, s[18:19]
global_store_b32 v0, v0, s[22:23]
global_store_b32 v0, v0, s[26:27]
global_store_b32 v0, v3, s[30:31]
global_store_b32 v0, v0, s[28:29]
global_store_b32 v0, v3, s[36:37]
global_store_b32 v0, v0, s[34:35]
global_store_b32 v0, v3, s[38:39]
global_store_b32 v0, v0, s[24:25]
global_store_b32 v0, v3, s[6:7]
global_store_b32 v0, v0, s[8:9]
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 42
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23NewNodeConnectionKerneliiiPiS_S_Pffif, .Lfunc_end0-_Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.private_segment_fixed_size: 0
.sgpr_count: 42
.sgpr_spill_count: 0
.symbol: _Z23NewNodeConnectionKerneliiiPiS_S_Pffif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NewNodeConnectionKernel( int f, int q, int r, int *activityFlag, int *connection, int *age, float *localError, float alfa, int maxCells, float errorFraction )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < 1)
{
activityFlag[r] = 1;
connection[q * maxCells + f] = 0;
age[q * maxCells + f] = 0;
connection[f * maxCells + q] = 0;
age[f * maxCells + q] = 0;
connection[q * maxCells + r] = 1;
age[q * maxCells + r] = 0;
connection[r * maxCells + q] = 1;
age[r * maxCells + q] = 0;
connection[f * maxCells + r] = 1;
age[f * maxCells + r] = 0;
connection[r * maxCells + f] = 1;
age[r * maxCells + f] = 0;
localError[q] -= alfa * localError[q];
localError[f] -= alfa * localError[f];
localError[r] = errorFraction * (localError[q] + localError[f]);
}
} | .text
.file "NewNodeConnectionKernel.hip"
.globl _Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif # -- Begin function _Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif
.p2align 4, 0x90
.type _Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif,@function
_Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif: # @_Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 200(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23NewNodeConnectionKerneliiiPiS_S_Pffif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif, .Lfunc_end0-_Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23NewNodeConnectionKerneliiiPiS_S_Pffif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23NewNodeConnectionKerneliiiPiS_S_Pffif,@object # @_Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.section .rodata,"a",@progbits
.globl _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.p2align 3, 0x0
_Z23NewNodeConnectionKerneliiiPiS_S_Pffif:
.quad _Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif
.size _Z23NewNodeConnectionKerneliiiPiS_S_Pffif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23NewNodeConnectionKerneliiiPiS_S_Pffif"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f04270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R5, c[0x0][0x194] ; /* 0x0000650000057a02 */
/* 0x000fe20000000f00 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff027435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R4, c[0x0][0x164] ; /* 0x0000590000047a02 */
/* 0x000fe20000000f00 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ MOV R0, c[0x0][0x168] ; /* 0x00005a0000007a02 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R6, c[0x0][0x160] ; /* 0x0000580000067a02 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD R12, R5, R4, c[0x0][0x160] ; /* 0x00005800050c7624 */
/* 0x000fe400078e0204 */
/*0100*/ IMAD.WIDE R8, R3, R0, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e0200 */
/*0110*/ IMAD R16, R5, c[0x0][0x160], R4 ; /* 0x0000580005107a24 */
/* 0x000fe200078e0204 */
/*0120*/ STG.E [R8.64], R2 ; /* 0x0000000208007986 */
/* 0x0001e2000c101904 */
/*0130*/ IMAD.WIDE R10, R12, R3, c[0x0][0x178] ; /* 0x00005e000c0a7625 */
/* 0x000fc800078e0203 */
/*0140*/ IMAD R20, R5, R4, c[0x0][0x168] ; /* 0x00005a0005147624 */
/* 0x000fe200078e0204 */
/*0150*/ STG.E [R10.64], RZ ; /* 0x000000ff0a007986 */
/* 0x0003e2000c101904 */
/*0160*/ IMAD.WIDE R12, R12, R3, c[0x0][0x180] ; /* 0x000060000c0c7625 */
/* 0x000fc800078e0203 */
/*0170*/ IMAD R22, R5, c[0x0][0x168], R4 ; /* 0x00005a0005167a24 */
/* 0x000fe200078e0204 */
/*0180*/ STG.E [R12.64], RZ ; /* 0x000000ff0c007986 */
/* 0x0005e2000c101904 */
/*0190*/ IMAD.WIDE R14, R16, R3, c[0x0][0x178] ; /* 0x00005e00100e7625 */
/* 0x000fc800078e0203 */
/*01a0*/ IMAD.WIDE R16, R16, R3.reuse, c[0x0][0x180] ; /* 0x0000600010107625 */
/* 0x080fe200078e0203 */
/*01b0*/ STG.E [R14.64], RZ ; /* 0x000000ff0e007986 */
/* 0x0007e6000c101904 */
/*01c0*/ IMAD.WIDE R18, R20.reuse, R3.reuse, c[0x0][0x178] ; /* 0x00005e0014127625 */
/* 0x0c0fe200078e0203 */
/*01d0*/ STG.E [R16.64], RZ ; /* 0x000000ff10007986 */
/* 0x0009e6000c101904 */
/*01e0*/ IMAD.WIDE R8, R20, R3.reuse, c[0x0][0x180] ; /* 0x0000600014087625 */
/* 0x081fe200078e0203 */
/*01f0*/ STG.E [R18.64], R2 ; /* 0x0000000212007986 */
/* 0x000fe6000c101904 */
/*0200*/ IMAD R24, R5, R6, c[0x0][0x168] ; /* 0x00005a0005187624 */
/* 0x000fe200078e0206 */
/*0210*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x0001e2000c101904 */
/*0220*/ IMAD.WIDE R20, R22, R3, c[0x0][0x178] ; /* 0x00005e0016147625 */
/* 0x000fc800078e0203 */
/*0230*/ IMAD.WIDE R10, R22, R3.reuse, c[0x0][0x180] ; /* 0x00006000160a7625 */
/* 0x082fe200078e0203 */
/*0240*/ STG.E [R20.64], R2 ; /* 0x0000000214007986 */
/* 0x000fe6000c101904 */
/*0250*/ IMAD R22, R5, c[0x0][0x168], R6 ; /* 0x00005a0005167a24 */
/* 0x000fe200078e0206 */
/*0260*/ STG.E [R10.64], RZ ; /* 0x000000ff0a007986 */
/* 0x0003e2000c101904 */
/*0270*/ IMAD.WIDE R12, R24, R3, c[0x0][0x178] ; /* 0x00005e00180c7625 */
/* 0x004fc800078e0203 */
/*0280*/ IMAD.WIDE R14, R24, R3.reuse, c[0x0][0x180] ; /* 0x00006000180e7625 */
/* 0x088fe200078e0203 */
/*0290*/ STG.E [R12.64], R2 ; /* 0x000000020c007986 */
/* 0x000fe6000c101904 */
/*02a0*/ IMAD.WIDE R16, R22.reuse, R3.reuse, c[0x0][0x178] ; /* 0x00005e0016107625 */
/* 0x0d0fe200078e0203 */
/*02b0*/ STG.E [R14.64], RZ ; /* 0x000000ff0e007986 */
/* 0x000fe6000c101904 */
/*02c0*/ IMAD.WIDE R22, R22, R3, c[0x0][0x180] ; /* 0x0000600016167625 */
/* 0x000fe200078e0203 */
/*02d0*/ STG.E [R16.64], R2 ; /* 0x0000000210007986 */
/* 0x0005e6000c101904 */
/*02e0*/ IMAD.WIDE R4, R3, R4, c[0x0][0x188] ; /* 0x0000620003047625 */
/* 0x000fe200078e0204 */
/*02f0*/ STG.E [R22.64], RZ ; /* 0x000000ff16007986 */
/* 0x000fe8000c101904 */
/*0300*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000e24000c1e1900 */
/*0310*/ FFMA R9, -R7, c[0x0][0x190], R7 ; /* 0x0000640007097a23 */
/* 0x001fc40000000107 */
/*0320*/ IMAD.WIDE R6, R3, R6, c[0x0][0x188] ; /* 0x0000620003067625 */
/* 0x000fc600078e0206 */
/*0330*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101904 */
/*0340*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000e64000c1e1900 */
/*0350*/ FFMA R11, -R8, c[0x0][0x190], R8 ; /* 0x00006400080b7a23 */
/* 0x002fca0000000108 */
/*0360*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101904 */
/*0370*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee2000c1e1900 */
/*0380*/ IMAD.WIDE R2, R3, R0, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x004fc800078e0200 */
/*0390*/ FADD R8, R11, R8 ; /* 0x000000080b087221 */
/* 0x008fc80000000000 */
/*03a0*/ FMUL R13, R8, c[0x0][0x198] ; /* 0x00006600080d7a20 */
/* 0x000fca0000400000 */
/*03b0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.globl _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.p2align 8
.type _Z23NewNodeConnectionKerneliiiPiS_S_Pffif,@function
_Z23NewNodeConnectionKerneliiiPiS_S_Pffif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x40
s_load_b32 s3, s[0:1], 0x4c
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 1, v1
s_cbranch_execz .LBB0_2
s_clause 0x4
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s24, s[0:1], 0x8
s_load_b64 s[12:13], s[0:1], 0x30
s_load_b256 s[4:11], s[0:1], 0x10
s_load_b32 s33, s[0:1], 0x38
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, 1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s15, s2, 31
s_ashr_i32 s25, s24, 31
s_ashr_i32 s17, s3, 31
s_lshl_b64 s[0:1], s[24:25], 2
s_mul_i32 s14, s13, s3
s_add_u32 s4, s4, s0
s_addc_u32 s5, s5, s1
s_add_i32 s18, s14, s2
s_mul_i32 s16, s13, s2
s_ashr_i32 s19, s18, 31
s_mul_i32 s13, s13, s24
s_lshl_b64 s[18:19], s[18:19], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s20, s6, s18
s_addc_u32 s21, s7, s19
s_add_u32 s18, s8, s18
s_addc_u32 s19, s9, s19
s_add_i32 s22, s16, s3
s_ashr_i32 s23, s22, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[26:27], s[22:23], 2
s_add_u32 s22, s6, s26
s_addc_u32 s23, s7, s27
s_add_u32 s26, s8, s26
s_addc_u32 s27, s9, s27
s_add_i32 s28, s14, s24
s_mov_b32 s14, s2
s_ashr_i32 s29, s28, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[28:29], s[28:29], 2
s_add_u32 s30, s6, s28
s_addc_u32 s31, s7, s29
s_add_u32 s28, s8, s28
s_addc_u32 s29, s9, s29
s_add_i32 s34, s13, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s35, s34, 31
s_lshl_b64 s[34:35], s[34:35], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s36, s6, s34
s_addc_u32 s37, s7, s35
s_add_u32 s34, s8, s34
s_addc_u32 s35, s9, s35
s_add_i32 s24, s16, s24
s_mov_b32 s16, s3
s_ashr_i32 s25, s24, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[24:25], s[24:25], 2
s_add_u32 s38, s6, s24
s_addc_u32 s39, s7, s25
s_add_u32 s24, s8, s24
s_addc_u32 s25, s9, s25
s_add_i32 s40, s13, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s41, s40, 31
s_lshl_b64 s[40:41], s[40:41], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_u32 s6, s6, s40
s_addc_u32 s7, s7, s41
s_add_u32 s8, s8, s40
s_addc_u32 s9, s9, s41
s_lshl_b64 s[16:17], s[16:17], 2
s_add_u32 s16, s10, s16
s_addc_u32 s17, s11, s17
s_load_b32 s3, s[16:17], 0x0
s_waitcnt lgkmcnt(0)
v_fma_f32 v1, -s3, s12, s3
s_lshl_b64 s[2:3], s[14:15], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s10, s2
s_addc_u32 s3, s11, s3
global_store_b32 v0, v1, s[16:17]
global_load_b32 v1, v0, s[2:3]
s_add_u32 s0, s10, s0
s_addc_u32 s1, s11, s1
s_waitcnt vmcnt(0)
v_fma_f32 v1, -v1, s12, v1
global_store_b32 v0, v1, s[2:3]
global_load_b32 v2, v0, s[16:17]
s_clause 0x1
global_store_b32 v0, v3, s[4:5]
global_store_b32 v0, v0, s[20:21]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, s33, v1
s_clause 0xb
global_store_b32 v0, v0, s[18:19]
global_store_b32 v0, v0, s[22:23]
global_store_b32 v0, v0, s[26:27]
global_store_b32 v0, v3, s[30:31]
global_store_b32 v0, v0, s[28:29]
global_store_b32 v0, v3, s[36:37]
global_store_b32 v0, v0, s[34:35]
global_store_b32 v0, v3, s[38:39]
global_store_b32 v0, v0, s[24:25]
global_store_b32 v0, v3, s[6:7]
global_store_b32 v0, v0, s[8:9]
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 42
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23NewNodeConnectionKerneliiiPiS_S_Pffif, .Lfunc_end0-_Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.private_segment_fixed_size: 0
.sgpr_count: 42
.sgpr_spill_count: 0
.symbol: _Z23NewNodeConnectionKerneliiiPiS_S_Pffif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b5244_00000000-6_NewNodeConnectionKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z23NewNodeConnectionKerneliiiPiS_S_PffifiiiPiS_S_Pffif
.type _Z55__device_stub__Z23NewNodeConnectionKerneliiiPiS_S_PffifiiiPiS_S_Pffif, @function
_Z55__device_stub__Z23NewNodeConnectionKerneliiiPiS_S_PffifiiiPiS_S_Pffif:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movq %rcx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movss %xmm0, 48(%rsp)
movss %xmm1, 12(%rsp)
movq 240(%rsp), %rax
movq %rax, 16(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z23NewNodeConnectionKerneliiiPiS_S_Pffif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z23NewNodeConnectionKerneliiiPiS_S_PffifiiiPiS_S_Pffif, .-_Z55__device_stub__Z23NewNodeConnectionKerneliiiPiS_S_PffifiiiPiS_S_Pffif
.globl _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.type _Z23NewNodeConnectionKerneliiiPiS_S_Pffif, @function
_Z23NewNodeConnectionKerneliiiPiS_S_Pffif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z23NewNodeConnectionKerneliiiPiS_S_PffifiiiPiS_S_Pffif
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23NewNodeConnectionKerneliiiPiS_S_Pffif, .-_Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23NewNodeConnectionKerneliiiPiS_S_Pffif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23NewNodeConnectionKerneliiiPiS_S_Pffif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "NewNodeConnectionKernel.hip"
.globl _Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif # -- Begin function _Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif
.p2align 4, 0x90
.type _Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif,@function
_Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif: # @_Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 200(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23NewNodeConnectionKerneliiiPiS_S_Pffif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif, .Lfunc_end0-_Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23NewNodeConnectionKerneliiiPiS_S_Pffif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23NewNodeConnectionKerneliiiPiS_S_Pffif,@object # @_Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.section .rodata,"a",@progbits
.globl _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.p2align 3, 0x0
_Z23NewNodeConnectionKerneliiiPiS_S_Pffif:
.quad _Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif
.size _Z23NewNodeConnectionKerneliiiPiS_S_Pffif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23NewNodeConnectionKerneliiiPiS_S_Pffif"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__NewNodeConnectionKerneliiiPiS_S_Pffif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23NewNodeConnectionKerneliiiPiS_S_Pffif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include "driver.cu"
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cufft.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <sys/types.h>
#include <fcntl.h>
#include <unistd.h>
#include <float.h>
#include <getopt.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#define NUM_EL 64
#define CHANNELS 25
#define PFB_CHANNELS 5
#define SAMPLES 4000
#define DEF_CUDA_DEVICE 0
#define checkCudaErrors(err) __checkCudaErrors(err, __FILE__, __LINE__)
char* g_inputData = NULL;
char2* g_outputData = NULL;
char* g_inputData_d = NULL;
char2* g_outputData_d = NULL;
int loadData(char* f){
int ret = EXIT_SUCCESS;
int file = 0;
int readSize = NUM_EL * CHANNELS * SAMPLES * (2*sizeof(char));
g_inputData = (char*) malloc(readSize);
if(NULL == g_inputData) {
(void) fprintf(stderr, "ERROR: Memory allocation failed! %s.\n", strerror(errno));
return EXIT_FAILURE;
}
file = open(f, O_RDONLY);
if (file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: failed to open data file. %s\n", strerror(errno));
return EXIT_FAILURE;
}
ret = read(file, g_inputData, readSize);
if (ret < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: failed to read data file. %s\n", strerror(errno));
(void) close(file);
return EXIT_FAILURE;
}
(void) close(file);
return EXIT_SUCCESS;
}
void __checkCudaErrors(cudaError_t err, const char* file, const int line) {
if (err != cudaSuccess) {
(void) fprintf(stderr, "ERROR: file <%s>, Line %d: %s\n",
file,
line,
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
return;
}
int init(){
int cudaDevice = DEF_CUDA_DEVICE;
checkCudaErrors(cudaSetDevice(cudaDevice));
int inputSize = NUM_EL * CHANNELS * SAMPLES * (2*sizeof(char));
int outputSize = SAMPLES * PFB_CHANNELS * NUM_EL * (2*sizeof(char));
// allocate memory for input and output data on the device.
checkCudaErrors(cudaMalloc((void **) &g_inputData_d, inputSize));
checkCudaErrors(cudaMemset((void *) g_inputData_d, 0, inputSize));
checkCudaErrors(cudaMalloc((void **) &g_outputData_d, outputSize));
checkCudaErrors(cudaMemset((void *) g_outputData_d, 0, outputSize));
// copy data to the device.
checkCudaErrors(cudaMemcpy(g_inputData_d, g_inputData, inputSize, cudaMemcpyHostToDevice));
return EXIT_SUCCESS;
}
__global__ void map(char* dataIn,
char2* dataOut,
int channelSelect) {
// select the channel range
int channelMin = PFB_CHANNELS*channelSelect;
int absIdx = 2 * blockDim.y*(blockIdx.x*CHANNELS + (channelMin+blockIdx.y)) + 2 * threadIdx.y; // times 2 because we are mapping a sequence of values to char2 array.
int mapIdx = blockDim.y*(blockIdx.x*gridDim.y + blockIdx.y) + threadIdx.y;
dataOut[mapIdx].x = dataIn[absIdx];
dataOut[mapIdx].y = dataIn[absIdx+1];
return;
}
int main(int argc, char *argv[]) {
int ret = EXIT_SUCCESS;
if(argc < 2) {
(void) fprintf(stderr, "ERROR: Data filename not specified.\n");
return EXIT_FAILURE;
}
char filename[256] = {0};
(void) strncpy(filename, argv[1], 256);
filename[255] = '\0';
ret = loadData(filename);
if (ret == EXIT_FAILURE) {
return EXIT_FAILURE;
}
ret = init();
// run map
int select = 0;
dim3 gridSize(SAMPLES,PFB_CHANNELS,1);
dim3 blockSize(1, NUM_EL, 1);
map<<<gridSize, blockSize>>>(g_inputData_d, g_outputData_d, select);
checkCudaErrors(cudaGetLastError());
int outputSize = SAMPLES * PFB_CHANNELS * NUM_EL * (2*sizeof(char));
g_outputData = (char2*) malloc(outputSize);
checkCudaErrors(cudaMemcpy(g_outputData, g_outputData_d, outputSize, cudaMemcpyDeviceToHost));
//output the true data as a check.
/*int file = 0;
char outfileFull[256] = "outfileFull.dat\0";
file = open(outfile,
O_CREAT | O_TRUNC | O_WRONLY,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
if(file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: writing outfile failed\n");
return EXIT_FAILURE;
}
(void) write(file, g_inputData, SAMPLES*CHANNELS*NUM_EL*2*sizeof(char));
(void) close(file); */
// output the mapped data.
int file = 0;
char outfile[256] = "outfile.dat\0";
file = open(outfile,
O_CREAT | O_TRUNC | O_WRONLY,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
if(file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: writing outfile failed\n");
return EXIT_FAILURE;
}
(void) write(file, g_outputData, outputSize);
(void) close(file);
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z3mapPcP5char2i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC UR4, c[0x0][0x4] ; /* 0x0000010000047ab9 */
/* 0x000fe40000000800 */
/*0040*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0050*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fc6000800063f */
/*0060*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R4, 0x19, R5 ; /* 0x0000001904007824 */
/* 0x001fe200078e0205 */
/*0080*/ SHF.L.U32 R3, R9, 0x1, RZ ; /* 0x0000000109037819 */
/* 0x002fc600000006ff */
/*0090*/ IMAD R0, R7, 0x5, R0 ; /* 0x0000000507007824 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x000fe2000f8e0203 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*00e0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ IMAD R0, R4, c[0x0][0x10], R5 ; /* 0x0000040004007a24 */
/* 0x000fe200078e0205 */
/*0100*/ HFMA2.MMA R5, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff057435 */
/* 0x000fc600000001ff */
/*0110*/ IMAD R0, R0, c[0x0][0x4], R9 ; /* 0x0000010000007a24 */
/* 0x000fce00078e0209 */
/*0120*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*0130*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe8000c101104 */
/*0140*/ LDG.E.U8 R9, [R2.64+0x1] ; /* 0x0000010402097981 */
/* 0x000ea8000c1e1100 */
/*0150*/ STG.E.U8 [R4.64+0x1], R9 ; /* 0x0000010904007986 */
/* 0x004fe2000c101104 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include "driver.cu"
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cufft.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <sys/types.h>
#include <fcntl.h>
#include <unistd.h>
#include <float.h>
#include <getopt.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#define NUM_EL 64
#define CHANNELS 25
#define PFB_CHANNELS 5
#define SAMPLES 4000
#define DEF_CUDA_DEVICE 0
#define checkCudaErrors(err) __checkCudaErrors(err, __FILE__, __LINE__)
char* g_inputData = NULL;
char2* g_outputData = NULL;
char* g_inputData_d = NULL;
char2* g_outputData_d = NULL;
int loadData(char* f){
int ret = EXIT_SUCCESS;
int file = 0;
int readSize = NUM_EL * CHANNELS * SAMPLES * (2*sizeof(char));
g_inputData = (char*) malloc(readSize);
if(NULL == g_inputData) {
(void) fprintf(stderr, "ERROR: Memory allocation failed! %s.\n", strerror(errno));
return EXIT_FAILURE;
}
file = open(f, O_RDONLY);
if (file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: failed to open data file. %s\n", strerror(errno));
return EXIT_FAILURE;
}
ret = read(file, g_inputData, readSize);
if (ret < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: failed to read data file. %s\n", strerror(errno));
(void) close(file);
return EXIT_FAILURE;
}
(void) close(file);
return EXIT_SUCCESS;
}
void __checkCudaErrors(cudaError_t err, const char* file, const int line) {
if (err != cudaSuccess) {
(void) fprintf(stderr, "ERROR: file <%s>, Line %d: %s\n",
file,
line,
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
return;
}
int init(){
int cudaDevice = DEF_CUDA_DEVICE;
checkCudaErrors(cudaSetDevice(cudaDevice));
int inputSize = NUM_EL * CHANNELS * SAMPLES * (2*sizeof(char));
int outputSize = SAMPLES * PFB_CHANNELS * NUM_EL * (2*sizeof(char));
// allocate memory for input and output data on the device.
checkCudaErrors(cudaMalloc((void **) &g_inputData_d, inputSize));
checkCudaErrors(cudaMemset((void *) g_inputData_d, 0, inputSize));
checkCudaErrors(cudaMalloc((void **) &g_outputData_d, outputSize));
checkCudaErrors(cudaMemset((void *) g_outputData_d, 0, outputSize));
// copy data to the device.
checkCudaErrors(cudaMemcpy(g_inputData_d, g_inputData, inputSize, cudaMemcpyHostToDevice));
return EXIT_SUCCESS;
}
__global__ void map(char* dataIn,
char2* dataOut,
int channelSelect) {
// select the channel range
int channelMin = PFB_CHANNELS*channelSelect;
int absIdx = 2 * blockDim.y*(blockIdx.x*CHANNELS + (channelMin+blockIdx.y)) + 2 * threadIdx.y; // times 2 because we are mapping a sequence of values to char2 array.
int mapIdx = blockDim.y*(blockIdx.x*gridDim.y + blockIdx.y) + threadIdx.y;
dataOut[mapIdx].x = dataIn[absIdx];
dataOut[mapIdx].y = dataIn[absIdx+1];
return;
}
int main(int argc, char *argv[]) {
int ret = EXIT_SUCCESS;
if(argc < 2) {
(void) fprintf(stderr, "ERROR: Data filename not specified.\n");
return EXIT_FAILURE;
}
char filename[256] = {0};
(void) strncpy(filename, argv[1], 256);
filename[255] = '\0';
ret = loadData(filename);
if (ret == EXIT_FAILURE) {
return EXIT_FAILURE;
}
ret = init();
// run map
int select = 0;
dim3 gridSize(SAMPLES,PFB_CHANNELS,1);
dim3 blockSize(1, NUM_EL, 1);
map<<<gridSize, blockSize>>>(g_inputData_d, g_outputData_d, select);
checkCudaErrors(cudaGetLastError());
int outputSize = SAMPLES * PFB_CHANNELS * NUM_EL * (2*sizeof(char));
g_outputData = (char2*) malloc(outputSize);
checkCudaErrors(cudaMemcpy(g_outputData, g_outputData_d, outputSize, cudaMemcpyDeviceToHost));
//output the true data as a check.
/*int file = 0;
char outfileFull[256] = "outfileFull.dat\0";
file = open(outfile,
O_CREAT | O_TRUNC | O_WRONLY,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
if(file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: writing outfile failed\n");
return EXIT_FAILURE;
}
(void) write(file, g_inputData, SAMPLES*CHANNELS*NUM_EL*2*sizeof(char));
(void) close(file); */
// output the mapped data.
int file = 0;
char outfile[256] = "outfile.dat\0";
file = open(outfile,
O_CREAT | O_TRUNC | O_WRONLY,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
if(file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: writing outfile failed\n");
return EXIT_FAILURE;
}
(void) write(file, g_outputData, outputSize);
(void) close(file);
return EXIT_SUCCESS;
} | .file "tmpxft_0015df50_00000000-6_driver.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2103:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "ERROR: Memory allocation failed! %s.\n"
.align 8
.LC1:
.string "ERROR: failed to open data file. %s\n"
.align 8
.LC2:
.string "ERROR: failed to read data file. %s\n"
.text
.globl _Z8loadDataPc
.type _Z8loadDataPc, @function
_Z8loadDataPc:
.LFB2097:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl $12800000, %edi
call malloc@PLT
movq %rax, g_inputData(%rip)
testq %rax, %rax
je .L9
movl $0, %esi
movq %rbx, %rdi
call __open_2@PLT
movl %eax, %ebx
testl %eax, %eax
js .L10
movq $-1, %rcx
movl $12800000, %edx
movq g_inputData(%rip), %rsi
movl %eax, %edi
call __read_chk@PLT
testl %eax, %eax
js .L11
movl %ebx, %edi
call close@PLT
movl $0, %eax
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __errno_location@PLT
movl (%rax), %edi
call strerror@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L3
.L10:
call __errno_location@PLT
movl (%rax), %edi
call strerror@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L3
.L11:
call __errno_location@PLT
movl (%rax), %edi
call strerror@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call close@PLT
movl $1, %eax
jmp .L3
.cfi_endproc
.LFE2097:
.size _Z8loadDataPc, .-_Z8loadDataPc
.section .rodata.str1.8
.align 8
.LC3:
.string "ERROR: file <%s>, Line %d: %s\n"
.text
.globl _Z17__checkCudaErrors9cudaErrorPKci
.type _Z17__checkCudaErrors9cudaErrorPKci, @function
_Z17__checkCudaErrors9cudaErrorPKci:
.LFB2098:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L17
ret
.L17:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %r9
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2098:
.size _Z17__checkCudaErrors9cudaErrorPKci, .-_Z17__checkCudaErrors9cudaErrorPKci
.section .rodata.str1.8
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mitchburnett/grating/release/src/pfb/sandbox/driver.cu"
.text
.globl _Z4initv
.type _Z4initv, @function
_Z4initv:
.LFB2099:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $79, %edx
leaq .LC4(%rip), %rbx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $12800000, %esi
leaq g_inputData_d(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $85, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $12800000, %edx
movl $0, %esi
movq g_inputData_d(%rip), %rdi
call cudaMemset@PLT
movl %eax, %edi
movl $86, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $2560000, %esi
leaq g_outputData_d(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $87, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $2560000, %edx
movl $0, %esi
movq g_outputData_d(%rip), %rdi
call cudaMemset@PLT
movl %eax, %edi
movl $88, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $1, %ecx
movl $12800000, %edx
movq g_inputData(%rip), %rsi
movq g_inputData_d(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $91, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z4initv, .-_Z4initv
.globl _Z30__device_stub__Z3mapPcP5char2iPcP5char2i
.type _Z30__device_stub__Z3mapPcP5char2iPcP5char2i, @function
_Z30__device_stub__Z3mapPcP5char2iPcP5char2i:
.LFB2125:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3mapPcP5char2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2125:
.size _Z30__device_stub__Z3mapPcP5char2iPcP5char2i, .-_Z30__device_stub__Z3mapPcP5char2iPcP5char2i
.globl _Z3mapPcP5char2i
.type _Z3mapPcP5char2i, @function
_Z3mapPcP5char2i:
.LFB2126:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z3mapPcP5char2iPcP5char2i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2126:
.size _Z3mapPcP5char2i, .-_Z3mapPcP5char2i
.section .rodata.str1.8
.align 8
.LC5:
.string "ERROR: Data filename not specified.\n"
.align 8
.LC6:
.string "ERROR: writing outfile failed\n"
.text
.globl main
.type main, @function
main:
.LFB2100:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $560, %rsp
.cfi_def_cfa_offset 576
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L35
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movq $0, 136(%rsp)
movq $0, 144(%rsp)
movq $0, 152(%rsp)
movq $0, 160(%rsp)
movq $0, 168(%rsp)
movq $0, 176(%rsp)
movq $0, 184(%rsp)
movq $0, 192(%rsp)
movq $0, 200(%rsp)
movq $0, 208(%rsp)
movq $0, 216(%rsp)
movq $0, 224(%rsp)
movq $0, 232(%rsp)
movq $0, 240(%rsp)
movq $0, 248(%rsp)
movq $0, 256(%rsp)
movq $0, 264(%rsp)
movq $0, 272(%rsp)
movq $0, 280(%rsp)
movq 8(%rsi), %rsi
leaq 32(%rsp), %rbx
movl $255, %edx
movq %rbx, %rdi
call strncpy@PLT
movq %rbx, %rdi
call _Z8loadDataPc
cmpl $1, %eax
je .L28
call _Z4initv
movl $4000, 8(%rsp)
movl $5, 12(%rsp)
movl $1, 20(%rsp)
movl $64, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L31:
call cudaGetLastError@PLT
movl %eax, %edi
movl $135, %edx
leaq .LC4(%rip), %rbx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $2560000, %edi
call malloc@PLT
movq %rax, %rdi
movq %rax, g_outputData(%rip)
movl $2, %ecx
movl $2560000, %edx
movq g_outputData_d(%rip), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $141, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movabsq $3343197498338735471, %rax
movl $7627108, %edx
movq %rax, 288(%rsp)
movq %rdx, 296(%rsp)
leaq 304(%rsp), %rdi
movl $60, %ecx
movl $0, %eax
rep stosl
leaq 288(%rsp), %rdi
movl $420, %edx
movl $577, %esi
call open@PLT
movl %eax, %ebx
testl %eax, %eax
js .L37
movl $2560000, %edx
movq g_outputData(%rip), %rsi
movl %eax, %edi
call write@PLT
movl %ebx, %edi
call close@PLT
movl $0, %eax
.L28:
movq 552(%rsp), %rdx
subq %fs:40, %rdx
jne .L38
addq $560, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L28
.L36:
movl $0, %edx
movq g_outputData_d(%rip), %rsi
movq g_inputData_d(%rip), %rdi
call _Z30__device_stub__Z3mapPcP5char2iPcP5char2i
jmp .L31
.L37:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L28
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "_Z3mapPcP5char2i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2128:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mapPcP5char2i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2128:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl g_outputData_d
.bss
.align 8
.type g_outputData_d, @object
.size g_outputData_d, 8
g_outputData_d:
.zero 8
.globl g_inputData_d
.align 8
.type g_inputData_d, @object
.size g_inputData_d, 8
g_inputData_d:
.zero 8
.globl g_outputData
.align 8
.type g_outputData, @object
.size g_outputData, 8
g_outputData:
.zero 8
.globl g_inputData
.align 8
.type g_inputData, @object
.size g_inputData, 8
g_inputData:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include "driver.cu"
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cufft.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <sys/types.h>
#include <fcntl.h>
#include <unistd.h>
#include <float.h>
#include <getopt.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#define NUM_EL 64
#define CHANNELS 25
#define PFB_CHANNELS 5
#define SAMPLES 4000
#define DEF_CUDA_DEVICE 0
#define checkCudaErrors(err) __checkCudaErrors(err, __FILE__, __LINE__)
char* g_inputData = NULL;
char2* g_outputData = NULL;
char* g_inputData_d = NULL;
char2* g_outputData_d = NULL;
int loadData(char* f){
int ret = EXIT_SUCCESS;
int file = 0;
int readSize = NUM_EL * CHANNELS * SAMPLES * (2*sizeof(char));
g_inputData = (char*) malloc(readSize);
if(NULL == g_inputData) {
(void) fprintf(stderr, "ERROR: Memory allocation failed! %s.\n", strerror(errno));
return EXIT_FAILURE;
}
file = open(f, O_RDONLY);
if (file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: failed to open data file. %s\n", strerror(errno));
return EXIT_FAILURE;
}
ret = read(file, g_inputData, readSize);
if (ret < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: failed to read data file. %s\n", strerror(errno));
(void) close(file);
return EXIT_FAILURE;
}
(void) close(file);
return EXIT_SUCCESS;
}
void __checkCudaErrors(cudaError_t err, const char* file, const int line) {
if (err != cudaSuccess) {
(void) fprintf(stderr, "ERROR: file <%s>, Line %d: %s\n",
file,
line,
cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
return;
}
int init(){
int cudaDevice = DEF_CUDA_DEVICE;
checkCudaErrors(cudaSetDevice(cudaDevice));
int inputSize = NUM_EL * CHANNELS * SAMPLES * (2*sizeof(char));
int outputSize = SAMPLES * PFB_CHANNELS * NUM_EL * (2*sizeof(char));
// allocate memory for input and output data on the device.
checkCudaErrors(cudaMalloc((void **) &g_inputData_d, inputSize));
checkCudaErrors(cudaMemset((void *) g_inputData_d, 0, inputSize));
checkCudaErrors(cudaMalloc((void **) &g_outputData_d, outputSize));
checkCudaErrors(cudaMemset((void *) g_outputData_d, 0, outputSize));
// copy data to the device.
checkCudaErrors(cudaMemcpy(g_inputData_d, g_inputData, inputSize, cudaMemcpyHostToDevice));
return EXIT_SUCCESS;
}
__global__ void map(char* dataIn,
char2* dataOut,
int channelSelect) {
// select the channel range
int channelMin = PFB_CHANNELS*channelSelect;
int absIdx = 2 * blockDim.y*(blockIdx.x*CHANNELS + (channelMin+blockIdx.y)) + 2 * threadIdx.y; // times 2 because we are mapping a sequence of values to char2 array.
int mapIdx = blockDim.y*(blockIdx.x*gridDim.y + blockIdx.y) + threadIdx.y;
dataOut[mapIdx].x = dataIn[absIdx];
dataOut[mapIdx].y = dataIn[absIdx+1];
return;
}
int main(int argc, char *argv[]) {
int ret = EXIT_SUCCESS;
if(argc < 2) {
(void) fprintf(stderr, "ERROR: Data filename not specified.\n");
return EXIT_FAILURE;
}
char filename[256] = {0};
(void) strncpy(filename, argv[1], 256);
filename[255] = '\0';
ret = loadData(filename);
if (ret == EXIT_FAILURE) {
return EXIT_FAILURE;
}
ret = init();
// run map
int select = 0;
dim3 gridSize(SAMPLES,PFB_CHANNELS,1);
dim3 blockSize(1, NUM_EL, 1);
map<<<gridSize, blockSize>>>(g_inputData_d, g_outputData_d, select);
checkCudaErrors(cudaGetLastError());
int outputSize = SAMPLES * PFB_CHANNELS * NUM_EL * (2*sizeof(char));
g_outputData = (char2*) malloc(outputSize);
checkCudaErrors(cudaMemcpy(g_outputData, g_outputData_d, outputSize, cudaMemcpyDeviceToHost));
//output the true data as a check.
/*int file = 0;
char outfileFull[256] = "outfileFull.dat\0";
file = open(outfile,
O_CREAT | O_TRUNC | O_WRONLY,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
if(file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: writing outfile failed\n");
return EXIT_FAILURE;
}
(void) write(file, g_inputData, SAMPLES*CHANNELS*NUM_EL*2*sizeof(char));
(void) close(file); */
// output the mapped data.
int file = 0;
char outfile[256] = "outfile.dat\0";
file = open(outfile,
O_CREAT | O_TRUNC | O_WRONLY,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
if(file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: writing outfile failed\n");
return EXIT_FAILURE;
}
(void) write(file, g_outputData, outputSize);
(void) close(file);
return EXIT_SUCCESS;
} | //#include "driver.cu"
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <sys/types.h>
#include <fcntl.h>
#include <unistd.h>
#include <float.h>
#include <getopt.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#define NUM_EL 64
#define CHANNELS 25
#define PFB_CHANNELS 5
#define SAMPLES 4000
#define DEF_CUDA_DEVICE 0
#define checkCudaErrors(err) __checkCudaErrors(err, __FILE__, __LINE__)
char* g_inputData = NULL;
char2* g_outputData = NULL;
char* g_inputData_d = NULL;
char2* g_outputData_d = NULL;
int loadData(char* f){
int ret = EXIT_SUCCESS;
int file = 0;
int readSize = NUM_EL * CHANNELS * SAMPLES * (2*sizeof(char));
g_inputData = (char*) malloc(readSize);
if(NULL == g_inputData) {
(void) fprintf(stderr, "ERROR: Memory allocation failed! %s.\n", strerror(errno));
return EXIT_FAILURE;
}
file = open(f, O_RDONLY);
if (file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: failed to open data file. %s\n", strerror(errno));
return EXIT_FAILURE;
}
ret = read(file, g_inputData, readSize);
if (ret < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: failed to read data file. %s\n", strerror(errno));
(void) close(file);
return EXIT_FAILURE;
}
(void) close(file);
return EXIT_SUCCESS;
}
void __checkCudaErrors(hipError_t err, const char* file, const int line) {
if (err != hipSuccess) {
(void) fprintf(stderr, "ERROR: file <%s>, Line %d: %s\n",
file,
line,
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
return;
}
int init(){
int cudaDevice = DEF_CUDA_DEVICE;
checkCudaErrors(hipSetDevice(cudaDevice));
int inputSize = NUM_EL * CHANNELS * SAMPLES * (2*sizeof(char));
int outputSize = SAMPLES * PFB_CHANNELS * NUM_EL * (2*sizeof(char));
// allocate memory for input and output data on the device.
checkCudaErrors(hipMalloc((void **) &g_inputData_d, inputSize));
checkCudaErrors(hipMemset((void *) g_inputData_d, 0, inputSize));
checkCudaErrors(hipMalloc((void **) &g_outputData_d, outputSize));
checkCudaErrors(hipMemset((void *) g_outputData_d, 0, outputSize));
// copy data to the device.
checkCudaErrors(hipMemcpy(g_inputData_d, g_inputData, inputSize, hipMemcpyHostToDevice));
return EXIT_SUCCESS;
}
__global__ void map(char* dataIn,
char2* dataOut,
int channelSelect) {
// select the channel range
int channelMin = PFB_CHANNELS*channelSelect;
int absIdx = 2 * blockDim.y*(blockIdx.x*CHANNELS + (channelMin+blockIdx.y)) + 2 * threadIdx.y; // times 2 because we are mapping a sequence of values to char2 array.
int mapIdx = blockDim.y*(blockIdx.x*gridDim.y + blockIdx.y) + threadIdx.y;
dataOut[mapIdx].x = dataIn[absIdx];
dataOut[mapIdx].y = dataIn[absIdx+1];
return;
}
int main(int argc, char *argv[]) {
int ret = EXIT_SUCCESS;
if(argc < 2) {
(void) fprintf(stderr, "ERROR: Data filename not specified.\n");
return EXIT_FAILURE;
}
char filename[256] = {0};
(void) strncpy(filename, argv[1], 256);
filename[255] = '\0';
ret = loadData(filename);
if (ret == EXIT_FAILURE) {
return EXIT_FAILURE;
}
ret = init();
// run map
int select = 0;
dim3 gridSize(SAMPLES,PFB_CHANNELS,1);
dim3 blockSize(1, NUM_EL, 1);
map<<<gridSize, blockSize>>>(g_inputData_d, g_outputData_d, select);
checkCudaErrors(hipGetLastError());
int outputSize = SAMPLES * PFB_CHANNELS * NUM_EL * (2*sizeof(char));
g_outputData = (char2*) malloc(outputSize);
checkCudaErrors(hipMemcpy(g_outputData, g_outputData_d, outputSize, hipMemcpyDeviceToHost));
//output the true data as a check.
/*int file = 0;
char outfileFull[256] = "outfileFull.dat\0";
file = open(outfile,
O_CREAT | O_TRUNC | O_WRONLY,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
if(file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: writing outfile failed\n");
return EXIT_FAILURE;
}
(void) write(file, g_inputData, SAMPLES*CHANNELS*NUM_EL*2*sizeof(char));
(void) close(file); */
// output the mapped data.
int file = 0;
char outfile[256] = "outfile.dat\0";
file = open(outfile,
O_CREAT | O_TRUNC | O_WRONLY,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
if(file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: writing outfile failed\n");
return EXIT_FAILURE;
}
(void) write(file, g_outputData, outputSize);
(void) close(file);
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //#include "driver.cu"
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <sys/types.h>
#include <fcntl.h>
#include <unistd.h>
#include <float.h>
#include <getopt.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#define NUM_EL 64
#define CHANNELS 25
#define PFB_CHANNELS 5
#define SAMPLES 4000
#define DEF_CUDA_DEVICE 0
#define checkCudaErrors(err) __checkCudaErrors(err, __FILE__, __LINE__)
char* g_inputData = NULL;
char2* g_outputData = NULL;
char* g_inputData_d = NULL;
char2* g_outputData_d = NULL;
int loadData(char* f){
int ret = EXIT_SUCCESS;
int file = 0;
int readSize = NUM_EL * CHANNELS * SAMPLES * (2*sizeof(char));
g_inputData = (char*) malloc(readSize);
if(NULL == g_inputData) {
(void) fprintf(stderr, "ERROR: Memory allocation failed! %s.\n", strerror(errno));
return EXIT_FAILURE;
}
file = open(f, O_RDONLY);
if (file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: failed to open data file. %s\n", strerror(errno));
return EXIT_FAILURE;
}
ret = read(file, g_inputData, readSize);
if (ret < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: failed to read data file. %s\n", strerror(errno));
(void) close(file);
return EXIT_FAILURE;
}
(void) close(file);
return EXIT_SUCCESS;
}
void __checkCudaErrors(hipError_t err, const char* file, const int line) {
if (err != hipSuccess) {
(void) fprintf(stderr, "ERROR: file <%s>, Line %d: %s\n",
file,
line,
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
return;
}
int init(){
int cudaDevice = DEF_CUDA_DEVICE;
checkCudaErrors(hipSetDevice(cudaDevice));
int inputSize = NUM_EL * CHANNELS * SAMPLES * (2*sizeof(char));
int outputSize = SAMPLES * PFB_CHANNELS * NUM_EL * (2*sizeof(char));
// allocate memory for input and output data on the device.
checkCudaErrors(hipMalloc((void **) &g_inputData_d, inputSize));
checkCudaErrors(hipMemset((void *) g_inputData_d, 0, inputSize));
checkCudaErrors(hipMalloc((void **) &g_outputData_d, outputSize));
checkCudaErrors(hipMemset((void *) g_outputData_d, 0, outputSize));
// copy data to the device.
checkCudaErrors(hipMemcpy(g_inputData_d, g_inputData, inputSize, hipMemcpyHostToDevice));
return EXIT_SUCCESS;
}
__global__ void map(char* dataIn,
char2* dataOut,
int channelSelect) {
// select the channel range
int channelMin = PFB_CHANNELS*channelSelect;
int absIdx = 2 * blockDim.y*(blockIdx.x*CHANNELS + (channelMin+blockIdx.y)) + 2 * threadIdx.y; // times 2 because we are mapping a sequence of values to char2 array.
int mapIdx = blockDim.y*(blockIdx.x*gridDim.y + blockIdx.y) + threadIdx.y;
dataOut[mapIdx].x = dataIn[absIdx];
dataOut[mapIdx].y = dataIn[absIdx+1];
return;
}
int main(int argc, char *argv[]) {
int ret = EXIT_SUCCESS;
if(argc < 2) {
(void) fprintf(stderr, "ERROR: Data filename not specified.\n");
return EXIT_FAILURE;
}
char filename[256] = {0};
(void) strncpy(filename, argv[1], 256);
filename[255] = '\0';
ret = loadData(filename);
if (ret == EXIT_FAILURE) {
return EXIT_FAILURE;
}
ret = init();
// run map
int select = 0;
dim3 gridSize(SAMPLES,PFB_CHANNELS,1);
dim3 blockSize(1, NUM_EL, 1);
map<<<gridSize, blockSize>>>(g_inputData_d, g_outputData_d, select);
checkCudaErrors(hipGetLastError());
int outputSize = SAMPLES * PFB_CHANNELS * NUM_EL * (2*sizeof(char));
g_outputData = (char2*) malloc(outputSize);
checkCudaErrors(hipMemcpy(g_outputData, g_outputData_d, outputSize, hipMemcpyDeviceToHost));
//output the true data as a check.
/*int file = 0;
char outfileFull[256] = "outfileFull.dat\0";
file = open(outfile,
O_CREAT | O_TRUNC | O_WRONLY,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
if(file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: writing outfile failed\n");
return EXIT_FAILURE;
}
(void) write(file, g_inputData, SAMPLES*CHANNELS*NUM_EL*2*sizeof(char));
(void) close(file); */
// output the mapped data.
int file = 0;
char outfile[256] = "outfile.dat\0";
file = open(outfile,
O_CREAT | O_TRUNC | O_WRONLY,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
if(file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: writing outfile failed\n");
return EXIT_FAILURE;
}
(void) write(file, g_outputData, outputSize);
(void) close(file);
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mapPcP15HIP_vector_typeIcLj2EEi
.globl _Z3mapPcP15HIP_vector_typeIcLj2EEi
.p2align 8
.type _Z3mapPcP15HIP_vector_typeIcLj2EEi,@function
_Z3mapPcP15HIP_vector_typeIcLj2EEi:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x1c
v_bfe_u32 v0, v0, 10, 10
s_mul_i32 s1, s14, 25
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s1, s1, s15
v_lshlrev_b32_e32 v1, 1, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, 5
s_lshr_b32 s3, s3, 16
s_add_i32 s1, s1, s2
s_mul_i32 s0, s0, s14
s_mul_i32 s1, s1, s3
s_add_i32 s0, s0, s15
v_lshl_add_u32 v3, s1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v3
v_add_co_u32 v1, vcc_lo, s4, v3
v_or_b32_e32 v3, 1, v3
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v3
global_load_u8 v4, v[1:2], off
v_mad_u64_u32 v[1:2], null, s0, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v4, off
global_load_u8 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v2, off offset:1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mapPcP15HIP_vector_typeIcLj2EEi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mapPcP15HIP_vector_typeIcLj2EEi, .Lfunc_end0-_Z3mapPcP15HIP_vector_typeIcLj2EEi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mapPcP15HIP_vector_typeIcLj2EEi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3mapPcP15HIP_vector_typeIcLj2EEi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //#include "driver.cu"
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include <sys/types.h>
#include <fcntl.h>
#include <unistd.h>
#include <float.h>
#include <getopt.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#define NUM_EL 64
#define CHANNELS 25
#define PFB_CHANNELS 5
#define SAMPLES 4000
#define DEF_CUDA_DEVICE 0
#define checkCudaErrors(err) __checkCudaErrors(err, __FILE__, __LINE__)
char* g_inputData = NULL;
char2* g_outputData = NULL;
char* g_inputData_d = NULL;
char2* g_outputData_d = NULL;
int loadData(char* f){
int ret = EXIT_SUCCESS;
int file = 0;
int readSize = NUM_EL * CHANNELS * SAMPLES * (2*sizeof(char));
g_inputData = (char*) malloc(readSize);
if(NULL == g_inputData) {
(void) fprintf(stderr, "ERROR: Memory allocation failed! %s.\n", strerror(errno));
return EXIT_FAILURE;
}
file = open(f, O_RDONLY);
if (file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: failed to open data file. %s\n", strerror(errno));
return EXIT_FAILURE;
}
ret = read(file, g_inputData, readSize);
if (ret < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: failed to read data file. %s\n", strerror(errno));
(void) close(file);
return EXIT_FAILURE;
}
(void) close(file);
return EXIT_SUCCESS;
}
void __checkCudaErrors(hipError_t err, const char* file, const int line) {
if (err != hipSuccess) {
(void) fprintf(stderr, "ERROR: file <%s>, Line %d: %s\n",
file,
line,
hipGetErrorString(err));
exit(EXIT_FAILURE);
}
return;
}
int init(){
int cudaDevice = DEF_CUDA_DEVICE;
checkCudaErrors(hipSetDevice(cudaDevice));
int inputSize = NUM_EL * CHANNELS * SAMPLES * (2*sizeof(char));
int outputSize = SAMPLES * PFB_CHANNELS * NUM_EL * (2*sizeof(char));
// allocate memory for input and output data on the device.
checkCudaErrors(hipMalloc((void **) &g_inputData_d, inputSize));
checkCudaErrors(hipMemset((void *) g_inputData_d, 0, inputSize));
checkCudaErrors(hipMalloc((void **) &g_outputData_d, outputSize));
checkCudaErrors(hipMemset((void *) g_outputData_d, 0, outputSize));
// copy data to the device.
checkCudaErrors(hipMemcpy(g_inputData_d, g_inputData, inputSize, hipMemcpyHostToDevice));
return EXIT_SUCCESS;
}
__global__ void map(char* dataIn,
char2* dataOut,
int channelSelect) {
// select the channel range
int channelMin = PFB_CHANNELS*channelSelect;
int absIdx = 2 * blockDim.y*(blockIdx.x*CHANNELS + (channelMin+blockIdx.y)) + 2 * threadIdx.y; // times 2 because we are mapping a sequence of values to char2 array.
int mapIdx = blockDim.y*(blockIdx.x*gridDim.y + blockIdx.y) + threadIdx.y;
dataOut[mapIdx].x = dataIn[absIdx];
dataOut[mapIdx].y = dataIn[absIdx+1];
return;
}
int main(int argc, char *argv[]) {
int ret = EXIT_SUCCESS;
if(argc < 2) {
(void) fprintf(stderr, "ERROR: Data filename not specified.\n");
return EXIT_FAILURE;
}
char filename[256] = {0};
(void) strncpy(filename, argv[1], 256);
filename[255] = '\0';
ret = loadData(filename);
if (ret == EXIT_FAILURE) {
return EXIT_FAILURE;
}
ret = init();
// run map
int select = 0;
dim3 gridSize(SAMPLES,PFB_CHANNELS,1);
dim3 blockSize(1, NUM_EL, 1);
map<<<gridSize, blockSize>>>(g_inputData_d, g_outputData_d, select);
checkCudaErrors(hipGetLastError());
int outputSize = SAMPLES * PFB_CHANNELS * NUM_EL * (2*sizeof(char));
g_outputData = (char2*) malloc(outputSize);
checkCudaErrors(hipMemcpy(g_outputData, g_outputData_d, outputSize, hipMemcpyDeviceToHost));
//output the true data as a check.
/*int file = 0;
char outfileFull[256] = "outfileFull.dat\0";
file = open(outfile,
O_CREAT | O_TRUNC | O_WRONLY,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
if(file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: writing outfile failed\n");
return EXIT_FAILURE;
}
(void) write(file, g_inputData, SAMPLES*CHANNELS*NUM_EL*2*sizeof(char));
(void) close(file); */
// output the mapped data.
int file = 0;
char outfile[256] = "outfile.dat\0";
file = open(outfile,
O_CREAT | O_TRUNC | O_WRONLY,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
if(file < EXIT_SUCCESS) {
(void) fprintf(stderr, "ERROR: writing outfile failed\n");
return EXIT_FAILURE;
}
(void) write(file, g_outputData, outputSize);
(void) close(file);
return EXIT_SUCCESS;
} | .text
.file "driver.hip"
.globl _Z8loadDataPc # -- Begin function _Z8loadDataPc
.p2align 4, 0x90
.type _Z8loadDataPc,@function
_Z8loadDataPc: # @_Z8loadDataPc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl $12800000, %edi # imm = 0xC35000
callq malloc
movq %rax, g_inputData(%rip)
testq %rax, %rax
je .LBB0_1
# %bb.3:
movq %rbx, %rdi
xorl %esi, %esi
xorl %eax, %eax
callq open
testl %eax, %eax
js .LBB0_4
# %bb.5:
movl %eax, %ebx
movq g_inputData(%rip), %rsi
movl $12800000, %edx # imm = 0xC35000
movl %eax, %edi
callq read
testl %eax, %eax
js .LBB0_6
# %bb.7:
movl %ebx, %edi
callq close
xorl %eax, %eax
.LBB0_8:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
callq __errno_location
movl (%rax), %edi
callq strerror
movl $.L.str, %esi
jmp .LBB0_2
.LBB0_4:
movq stderr(%rip), %rbx
callq __errno_location
movl (%rax), %edi
callq strerror
movl $.L.str.1, %esi
.LBB0_2:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %eax
jmp .LBB0_8
.LBB0_6:
movq stderr(%rip), %r14
callq __errno_location
movl (%rax), %edi
callq strerror
movl $.L.str.2, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl %ebx, %edi
callq close
movl $1, %eax
jmp .LBB0_8
.Lfunc_end0:
.size _Z8loadDataPc, .Lfunc_end0-_Z8loadDataPc
.cfi_endproc
# -- End function
.globl _Z17__checkCudaErrors10hipError_tPKci # -- Begin function _Z17__checkCudaErrors10hipError_tPKci
.p2align 4, 0x90
.type _Z17__checkCudaErrors10hipError_tPKci,@function
_Z17__checkCudaErrors10hipError_tPKci: # @_Z17__checkCudaErrors10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq stderr(%rip), %rbx
movl %edx, %ebp
movq %rsi, %r14
callq hipGetErrorString
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %r14, %rdx
movl %ebp, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z17__checkCudaErrors10hipError_tPKci, .Lfunc_end1-_Z17__checkCudaErrors10hipError_tPKci
.cfi_endproc
# -- End function
.globl _Z4initv # -- Begin function _Z4initv
.p2align 4, 0x90
.type _Z4initv,@function
_Z4initv: # @_Z4initv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z17__checkCudaErrors10hipError_tPKci.exit
movl $g_inputData_d, %edi
movl $12800000, %esi # imm = 0xC35000
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z17__checkCudaErrors10hipError_tPKci.exit7
movq g_inputData_d(%rip), %rdi
movl $12800000, %edx # imm = 0xC35000
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB2_6
# %bb.7: # %_Z17__checkCudaErrors10hipError_tPKci.exit9
movl $g_outputData_d, %edi
movl $2560000, %esi # imm = 0x271000
callq hipMalloc
testl %eax, %eax
jne .LBB2_8
# %bb.9: # %_Z17__checkCudaErrors10hipError_tPKci.exit11
movq g_outputData_d(%rip), %rdi
movl $2560000, %edx # imm = 0x271000
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB2_10
# %bb.11: # %_Z17__checkCudaErrors10hipError_tPKci.exit13
movq g_inputData_d(%rip), %rdi
movq g_inputData(%rip), %rsi
movl $12800000, %edx # imm = 0xC35000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_12
# %bb.13: # %_Z17__checkCudaErrors10hipError_tPKci.exit15
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $79, %ecx
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $85, %ecx
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $86, %ecx
jmp .LBB2_2
.LBB2_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $87, %ecx
jmp .LBB2_2
.LBB2_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $88, %ecx
jmp .LBB2_2
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $91, %ecx
.LBB2_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z4initv, .Lfunc_end2-_Z4initv
.cfi_endproc
# -- End function
.globl _Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi # -- Begin function _Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi
.p2align 4, 0x90
.type _Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi,@function
_Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi: # @_Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mapPcP15HIP_vector_typeIcLj2EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi, .Lfunc_end3-_Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $368, %rsp # imm = 0x170
.cfi_def_cfa_offset 384
.cfi_offset %rbx, -16
cmpl $1, %edi
jle .LBB4_1
# %bb.3:
xorps %xmm0, %xmm0
movaps %xmm0, 352(%rsp)
movaps %xmm0, 336(%rsp)
movaps %xmm0, 320(%rsp)
movaps %xmm0, 304(%rsp)
movaps %xmm0, 288(%rsp)
movaps %xmm0, 272(%rsp)
movaps %xmm0, 256(%rsp)
movaps %xmm0, 240(%rsp)
movaps %xmm0, 224(%rsp)
movaps %xmm0, 208(%rsp)
movaps %xmm0, 192(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 144(%rsp)
movaps %xmm0, 128(%rsp)
movaps %xmm0, 112(%rsp)
movq 8(%rsi), %rsi
leaq 112(%rsp), %rbx
movl $256, %edx # imm = 0x100
movq %rbx, %rdi
callq strncpy
movb $0, 367(%rsp)
movq %rbx, %rdi
callq _Z8loadDataPc
movl %eax, %ecx
movl $1, %eax
testl %ecx, %ecx
jne .LBB4_14
# %bb.4:
callq _Z4initv
movabsq $21474840480, %rdi # imm = 0x500000FA0
movabsq $274877906945, %rdx # imm = 0x4000000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq g_inputData_d(%rip), %rax
movq g_outputData_d(%rip), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl $0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mapPcP15HIP_vector_typeIcLj2EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_7
# %bb.9: # %_Z17__checkCudaErrors10hipError_tPKci.exit
movl $2560000, %edi # imm = 0x271000
callq malloc
movq %rax, g_outputData(%rip)
movq g_outputData_d(%rip), %rsi
movl $2560000, %edx # imm = 0x271000
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_10
# %bb.11: # %_Z17__checkCudaErrors10hipError_tPKci.exit19
movl $.L__const.main.outfile, %edi
movl $577, %esi # imm = 0x241
movl $420, %edx # imm = 0x1A4
xorl %eax, %eax
callq open
testl %eax, %eax
js .LBB4_12
# %bb.13:
movl %eax, %ebx
movq g_outputData(%rip), %rsi
movl $2560000, %edx # imm = 0x271000
movl %eax, %edi
callq write
movl %ebx, %edi
callq close
xorl %eax, %eax
.LBB4_14:
addq $368, %rsp # imm = 0x170
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 384
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $36, %esi
jmp .LBB4_2
.LBB4_12:
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $30, %esi
.LBB4_2:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB4_14
.LBB4_7:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $135, %ecx
jmp .LBB4_8
.LBB4_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $141, %ecx
.LBB4_8:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mapPcP15HIP_vector_typeIcLj2EEi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type g_inputData,@object # @g_inputData
.bss
.globl g_inputData
.p2align 3, 0x0
g_inputData:
.quad 0
.size g_inputData, 8
.type g_outputData,@object # @g_outputData
.globl g_outputData
.p2align 3, 0x0
g_outputData:
.quad 0
.size g_outputData, 8
.type g_inputData_d,@object # @g_inputData_d
.globl g_inputData_d
.p2align 3, 0x0
g_inputData_d:
.quad 0
.size g_inputData_d, 8
.type g_outputData_d,@object # @g_outputData_d
.globl g_outputData_d
.p2align 3, 0x0
g_outputData_d:
.quad 0
.size g_outputData_d, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR: Memory allocation failed! %s.\n"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ERROR: failed to open data file. %s\n"
.size .L.str.1, 37
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR: failed to read data file. %s\n"
.size .L.str.2, 37
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ERROR: file <%s>, Line %d: %s\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/mitchburnett/grating/release/src/pfb/sandbox/driver.hip"
.size .L.str.4, 113
.type _Z3mapPcP15HIP_vector_typeIcLj2EEi,@object # @_Z3mapPcP15HIP_vector_typeIcLj2EEi
.section .rodata,"a",@progbits
.globl _Z3mapPcP15HIP_vector_typeIcLj2EEi
.p2align 3, 0x0
_Z3mapPcP15HIP_vector_typeIcLj2EEi:
.quad _Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi
.size _Z3mapPcP15HIP_vector_typeIcLj2EEi, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "ERROR: Data filename not specified.\n"
.size .L.str.5, 37
.type .L__const.main.outfile,@object # @__const.main.outfile
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.outfile:
.asciz "outfile.dat\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000"
.size .L__const.main.outfile, 256
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "ERROR: writing outfile failed\n"
.size .L.str.6, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3mapPcP15HIP_vector_typeIcLj2EEi"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym g_inputData_d
.addrsig_sym g_outputData_d
.addrsig_sym _Z3mapPcP15HIP_vector_typeIcLj2EEi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3mapPcP5char2i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC UR4, c[0x0][0x4] ; /* 0x0000010000047ab9 */
/* 0x000fe40000000800 */
/*0040*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0050*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fc6000800063f */
/*0060*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R4, 0x19, R5 ; /* 0x0000001904007824 */
/* 0x001fe200078e0205 */
/*0080*/ SHF.L.U32 R3, R9, 0x1, RZ ; /* 0x0000000109037819 */
/* 0x002fc600000006ff */
/*0090*/ IMAD R0, R7, 0x5, R0 ; /* 0x0000000507007824 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x000fe2000f8e0203 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00d0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f0eff */
/*00e0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ IMAD R0, R4, c[0x0][0x10], R5 ; /* 0x0000040004007a24 */
/* 0x000fe200078e0205 */
/*0100*/ HFMA2.MMA R5, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff057435 */
/* 0x000fc600000001ff */
/*0110*/ IMAD R0, R0, c[0x0][0x4], R9 ; /* 0x0000010000007a24 */
/* 0x000fce00078e0209 */
/*0120*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*0130*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe8000c101104 */
/*0140*/ LDG.E.U8 R9, [R2.64+0x1] ; /* 0x0000010402097981 */
/* 0x000ea8000c1e1100 */
/*0150*/ STG.E.U8 [R4.64+0x1], R9 ; /* 0x0000010904007986 */
/* 0x004fe2000c101104 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mapPcP15HIP_vector_typeIcLj2EEi
.globl _Z3mapPcP15HIP_vector_typeIcLj2EEi
.p2align 8
.type _Z3mapPcP15HIP_vector_typeIcLj2EEi,@function
_Z3mapPcP15HIP_vector_typeIcLj2EEi:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x1c
v_bfe_u32 v0, v0, 10, 10
s_mul_i32 s1, s14, 25
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s1, s1, s15
v_lshlrev_b32_e32 v1, 1, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, 5
s_lshr_b32 s3, s3, 16
s_add_i32 s1, s1, s2
s_mul_i32 s0, s0, s14
s_mul_i32 s1, s1, s3
s_add_i32 s0, s0, s15
v_lshl_add_u32 v3, s1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v3
v_add_co_u32 v1, vcc_lo, s4, v3
v_or_b32_e32 v3, 1, v3
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v3
global_load_u8 v4, v[1:2], off
v_mad_u64_u32 v[1:2], null, s0, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 1, v[1:2]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v4, off
global_load_u8 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v2, off offset:1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mapPcP15HIP_vector_typeIcLj2EEi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mapPcP15HIP_vector_typeIcLj2EEi, .Lfunc_end0-_Z3mapPcP15HIP_vector_typeIcLj2EEi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mapPcP15HIP_vector_typeIcLj2EEi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3mapPcP15HIP_vector_typeIcLj2EEi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015df50_00000000-6_driver.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2103:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "ERROR: Memory allocation failed! %s.\n"
.align 8
.LC1:
.string "ERROR: failed to open data file. %s\n"
.align 8
.LC2:
.string "ERROR: failed to read data file. %s\n"
.text
.globl _Z8loadDataPc
.type _Z8loadDataPc, @function
_Z8loadDataPc:
.LFB2097:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl $12800000, %edi
call malloc@PLT
movq %rax, g_inputData(%rip)
testq %rax, %rax
je .L9
movl $0, %esi
movq %rbx, %rdi
call __open_2@PLT
movl %eax, %ebx
testl %eax, %eax
js .L10
movq $-1, %rcx
movl $12800000, %edx
movq g_inputData(%rip), %rsi
movl %eax, %edi
call __read_chk@PLT
testl %eax, %eax
js .L11
movl %ebx, %edi
call close@PLT
movl $0, %eax
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __errno_location@PLT
movl (%rax), %edi
call strerror@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L3
.L10:
call __errno_location@PLT
movl (%rax), %edi
call strerror@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L3
.L11:
call __errno_location@PLT
movl (%rax), %edi
call strerror@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call close@PLT
movl $1, %eax
jmp .L3
.cfi_endproc
.LFE2097:
.size _Z8loadDataPc, .-_Z8loadDataPc
.section .rodata.str1.8
.align 8
.LC3:
.string "ERROR: file <%s>, Line %d: %s\n"
.text
.globl _Z17__checkCudaErrors9cudaErrorPKci
.type _Z17__checkCudaErrors9cudaErrorPKci, @function
_Z17__checkCudaErrors9cudaErrorPKci:
.LFB2098:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L17
ret
.L17:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %r9
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2098:
.size _Z17__checkCudaErrors9cudaErrorPKci, .-_Z17__checkCudaErrors9cudaErrorPKci
.section .rodata.str1.8
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mitchburnett/grating/release/src/pfb/sandbox/driver.cu"
.text
.globl _Z4initv
.type _Z4initv, @function
_Z4initv:
.LFB2099:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $0, %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $79, %edx
leaq .LC4(%rip), %rbx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $12800000, %esi
leaq g_inputData_d(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $85, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $12800000, %edx
movl $0, %esi
movq g_inputData_d(%rip), %rdi
call cudaMemset@PLT
movl %eax, %edi
movl $86, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $2560000, %esi
leaq g_outputData_d(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edi
movl $87, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $2560000, %edx
movl $0, %esi
movq g_outputData_d(%rip), %rdi
call cudaMemset@PLT
movl %eax, %edi
movl $88, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $1, %ecx
movl $12800000, %edx
movq g_inputData(%rip), %rsi
movq g_inputData_d(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $91, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z4initv, .-_Z4initv
.globl _Z30__device_stub__Z3mapPcP5char2iPcP5char2i
.type _Z30__device_stub__Z3mapPcP5char2iPcP5char2i, @function
_Z30__device_stub__Z3mapPcP5char2iPcP5char2i:
.LFB2125:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3mapPcP5char2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2125:
.size _Z30__device_stub__Z3mapPcP5char2iPcP5char2i, .-_Z30__device_stub__Z3mapPcP5char2iPcP5char2i
.globl _Z3mapPcP5char2i
.type _Z3mapPcP5char2i, @function
_Z3mapPcP5char2i:
.LFB2126:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z3mapPcP5char2iPcP5char2i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2126:
.size _Z3mapPcP5char2i, .-_Z3mapPcP5char2i
.section .rodata.str1.8
.align 8
.LC5:
.string "ERROR: Data filename not specified.\n"
.align 8
.LC6:
.string "ERROR: writing outfile failed\n"
.text
.globl main
.type main, @function
main:
.LFB2100:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $560, %rsp
.cfi_def_cfa_offset 576
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L35
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movq $0, 136(%rsp)
movq $0, 144(%rsp)
movq $0, 152(%rsp)
movq $0, 160(%rsp)
movq $0, 168(%rsp)
movq $0, 176(%rsp)
movq $0, 184(%rsp)
movq $0, 192(%rsp)
movq $0, 200(%rsp)
movq $0, 208(%rsp)
movq $0, 216(%rsp)
movq $0, 224(%rsp)
movq $0, 232(%rsp)
movq $0, 240(%rsp)
movq $0, 248(%rsp)
movq $0, 256(%rsp)
movq $0, 264(%rsp)
movq $0, 272(%rsp)
movq $0, 280(%rsp)
movq 8(%rsi), %rsi
leaq 32(%rsp), %rbx
movl $255, %edx
movq %rbx, %rdi
call strncpy@PLT
movq %rbx, %rdi
call _Z8loadDataPc
cmpl $1, %eax
je .L28
call _Z4initv
movl $4000, 8(%rsp)
movl $5, 12(%rsp)
movl $1, 20(%rsp)
movl $64, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L31:
call cudaGetLastError@PLT
movl %eax, %edi
movl $135, %edx
leaq .LC4(%rip), %rbx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movl $2560000, %edi
call malloc@PLT
movq %rax, %rdi
movq %rax, g_outputData(%rip)
movl $2, %ecx
movl $2560000, %edx
movq g_outputData_d(%rip), %rsi
call cudaMemcpy@PLT
movl %eax, %edi
movl $141, %edx
movq %rbx, %rsi
call _Z17__checkCudaErrors9cudaErrorPKci
movabsq $3343197498338735471, %rax
movl $7627108, %edx
movq %rax, 288(%rsp)
movq %rdx, 296(%rsp)
leaq 304(%rsp), %rdi
movl $60, %ecx
movl $0, %eax
rep stosl
leaq 288(%rsp), %rdi
movl $420, %edx
movl $577, %esi
call open@PLT
movl %eax, %ebx
testl %eax, %eax
js .L37
movl $2560000, %edx
movq g_outputData(%rip), %rsi
movl %eax, %edi
call write@PLT
movl %ebx, %edi
call close@PLT
movl $0, %eax
.L28:
movq 552(%rsp), %rdx
subq %fs:40, %rdx
jne .L38
addq $560, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L28
.L36:
movl $0, %edx
movq g_outputData_d(%rip), %rsi
movq g_inputData_d(%rip), %rdi
call _Z30__device_stub__Z3mapPcP5char2iPcP5char2i
jmp .L31
.L37:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L28
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "_Z3mapPcP5char2i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2128:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mapPcP5char2i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2128:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl g_outputData_d
.bss
.align 8
.type g_outputData_d, @object
.size g_outputData_d, 8
g_outputData_d:
.zero 8
.globl g_inputData_d
.align 8
.type g_inputData_d, @object
.size g_inputData_d, 8
g_inputData_d:
.zero 8
.globl g_outputData
.align 8
.type g_outputData, @object
.size g_outputData, 8
g_outputData:
.zero 8
.globl g_inputData
.align 8
.type g_inputData, @object
.size g_inputData, 8
g_inputData:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "driver.hip"
.globl _Z8loadDataPc # -- Begin function _Z8loadDataPc
.p2align 4, 0x90
.type _Z8loadDataPc,@function
_Z8loadDataPc: # @_Z8loadDataPc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl $12800000, %edi # imm = 0xC35000
callq malloc
movq %rax, g_inputData(%rip)
testq %rax, %rax
je .LBB0_1
# %bb.3:
movq %rbx, %rdi
xorl %esi, %esi
xorl %eax, %eax
callq open
testl %eax, %eax
js .LBB0_4
# %bb.5:
movl %eax, %ebx
movq g_inputData(%rip), %rsi
movl $12800000, %edx # imm = 0xC35000
movl %eax, %edi
callq read
testl %eax, %eax
js .LBB0_6
# %bb.7:
movl %ebx, %edi
callq close
xorl %eax, %eax
.LBB0_8:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
callq __errno_location
movl (%rax), %edi
callq strerror
movl $.L.str, %esi
jmp .LBB0_2
.LBB0_4:
movq stderr(%rip), %rbx
callq __errno_location
movl (%rax), %edi
callq strerror
movl $.L.str.1, %esi
.LBB0_2:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %eax
jmp .LBB0_8
.LBB0_6:
movq stderr(%rip), %r14
callq __errno_location
movl (%rax), %edi
callq strerror
movl $.L.str.2, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl %ebx, %edi
callq close
movl $1, %eax
jmp .LBB0_8
.Lfunc_end0:
.size _Z8loadDataPc, .Lfunc_end0-_Z8loadDataPc
.cfi_endproc
# -- End function
.globl _Z17__checkCudaErrors10hipError_tPKci # -- Begin function _Z17__checkCudaErrors10hipError_tPKci
.p2align 4, 0x90
.type _Z17__checkCudaErrors10hipError_tPKci,@function
_Z17__checkCudaErrors10hipError_tPKci: # @_Z17__checkCudaErrors10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq stderr(%rip), %rbx
movl %edx, %ebp
movq %rsi, %r14
callq hipGetErrorString
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %r14, %rdx
movl %ebp, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z17__checkCudaErrors10hipError_tPKci, .Lfunc_end1-_Z17__checkCudaErrors10hipError_tPKci
.cfi_endproc
# -- End function
.globl _Z4initv # -- Begin function _Z4initv
.p2align 4, 0x90
.type _Z4initv,@function
_Z4initv: # @_Z4initv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z17__checkCudaErrors10hipError_tPKci.exit
movl $g_inputData_d, %edi
movl $12800000, %esi # imm = 0xC35000
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z17__checkCudaErrors10hipError_tPKci.exit7
movq g_inputData_d(%rip), %rdi
movl $12800000, %edx # imm = 0xC35000
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB2_6
# %bb.7: # %_Z17__checkCudaErrors10hipError_tPKci.exit9
movl $g_outputData_d, %edi
movl $2560000, %esi # imm = 0x271000
callq hipMalloc
testl %eax, %eax
jne .LBB2_8
# %bb.9: # %_Z17__checkCudaErrors10hipError_tPKci.exit11
movq g_outputData_d(%rip), %rdi
movl $2560000, %edx # imm = 0x271000
xorl %esi, %esi
callq hipMemset
testl %eax, %eax
jne .LBB2_10
# %bb.11: # %_Z17__checkCudaErrors10hipError_tPKci.exit13
movq g_inputData_d(%rip), %rdi
movq g_inputData(%rip), %rsi
movl $12800000, %edx # imm = 0xC35000
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_12
# %bb.13: # %_Z17__checkCudaErrors10hipError_tPKci.exit15
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $79, %ecx
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $85, %ecx
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $86, %ecx
jmp .LBB2_2
.LBB2_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $87, %ecx
jmp .LBB2_2
.LBB2_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $88, %ecx
jmp .LBB2_2
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $91, %ecx
.LBB2_2:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z4initv, .Lfunc_end2-_Z4initv
.cfi_endproc
# -- End function
.globl _Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi # -- Begin function _Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi
.p2align 4, 0x90
.type _Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi,@function
_Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi: # @_Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mapPcP15HIP_vector_typeIcLj2EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi, .Lfunc_end3-_Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $368, %rsp # imm = 0x170
.cfi_def_cfa_offset 384
.cfi_offset %rbx, -16
cmpl $1, %edi
jle .LBB4_1
# %bb.3:
xorps %xmm0, %xmm0
movaps %xmm0, 352(%rsp)
movaps %xmm0, 336(%rsp)
movaps %xmm0, 320(%rsp)
movaps %xmm0, 304(%rsp)
movaps %xmm0, 288(%rsp)
movaps %xmm0, 272(%rsp)
movaps %xmm0, 256(%rsp)
movaps %xmm0, 240(%rsp)
movaps %xmm0, 224(%rsp)
movaps %xmm0, 208(%rsp)
movaps %xmm0, 192(%rsp)
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 144(%rsp)
movaps %xmm0, 128(%rsp)
movaps %xmm0, 112(%rsp)
movq 8(%rsi), %rsi
leaq 112(%rsp), %rbx
movl $256, %edx # imm = 0x100
movq %rbx, %rdi
callq strncpy
movb $0, 367(%rsp)
movq %rbx, %rdi
callq _Z8loadDataPc
movl %eax, %ecx
movl $1, %eax
testl %ecx, %ecx
jne .LBB4_14
# %bb.4:
callq _Z4initv
movabsq $21474840480, %rdi # imm = 0x500000FA0
movabsq $274877906945, %rdx # imm = 0x4000000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq g_inputData_d(%rip), %rax
movq g_outputData_d(%rip), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movl $0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mapPcP15HIP_vector_typeIcLj2EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq hipGetLastError
testl %eax, %eax
jne .LBB4_7
# %bb.9: # %_Z17__checkCudaErrors10hipError_tPKci.exit
movl $2560000, %edi # imm = 0x271000
callq malloc
movq %rax, g_outputData(%rip)
movq g_outputData_d(%rip), %rsi
movl $2560000, %edx # imm = 0x271000
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_10
# %bb.11: # %_Z17__checkCudaErrors10hipError_tPKci.exit19
movl $.L__const.main.outfile, %edi
movl $577, %esi # imm = 0x241
movl $420, %edx # imm = 0x1A4
xorl %eax, %eax
callq open
testl %eax, %eax
js .LBB4_12
# %bb.13:
movl %eax, %ebx
movq g_outputData(%rip), %rsi
movl $2560000, %edx # imm = 0x271000
movl %eax, %edi
callq write
movl %ebx, %edi
callq close
xorl %eax, %eax
.LBB4_14:
addq $368, %rsp # imm = 0x170
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 384
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $36, %esi
jmp .LBB4_2
.LBB4_12:
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $30, %esi
.LBB4_2:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB4_14
.LBB4_7:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $135, %ecx
jmp .LBB4_8
.LBB4_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $141, %ecx
.LBB4_8:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mapPcP15HIP_vector_typeIcLj2EEi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type g_inputData,@object # @g_inputData
.bss
.globl g_inputData
.p2align 3, 0x0
g_inputData:
.quad 0
.size g_inputData, 8
.type g_outputData,@object # @g_outputData
.globl g_outputData
.p2align 3, 0x0
g_outputData:
.quad 0
.size g_outputData, 8
.type g_inputData_d,@object # @g_inputData_d
.globl g_inputData_d
.p2align 3, 0x0
g_inputData_d:
.quad 0
.size g_inputData_d, 8
.type g_outputData_d,@object # @g_outputData_d
.globl g_outputData_d
.p2align 3, 0x0
g_outputData_d:
.quad 0
.size g_outputData_d, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR: Memory allocation failed! %s.\n"
.size .L.str, 38
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ERROR: failed to open data file. %s\n"
.size .L.str.1, 37
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR: failed to read data file. %s\n"
.size .L.str.2, 37
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ERROR: file <%s>, Line %d: %s\n"
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/mitchburnett/grating/release/src/pfb/sandbox/driver.hip"
.size .L.str.4, 113
.type _Z3mapPcP15HIP_vector_typeIcLj2EEi,@object # @_Z3mapPcP15HIP_vector_typeIcLj2EEi
.section .rodata,"a",@progbits
.globl _Z3mapPcP15HIP_vector_typeIcLj2EEi
.p2align 3, 0x0
_Z3mapPcP15HIP_vector_typeIcLj2EEi:
.quad _Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi
.size _Z3mapPcP15HIP_vector_typeIcLj2EEi, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "ERROR: Data filename not specified.\n"
.size .L.str.5, 37
.type .L__const.main.outfile,@object # @__const.main.outfile
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.outfile:
.asciz "outfile.dat\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000\000"
.size .L__const.main.outfile, 256
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "ERROR: writing outfile failed\n"
.size .L.str.6, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3mapPcP15HIP_vector_typeIcLj2EEi"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mapPcP15HIP_vector_typeIcLj2EEi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym g_inputData_d
.addrsig_sym g_outputData_d
.addrsig_sym _Z3mapPcP15HIP_vector_typeIcLj2EEi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda_runtime.h>
#include<cmath>
const double NEWTON_G = 6.67384e-11;
const double SOFTENING = 1e-9f;
__constant__ double NEWTON_GG = 6.67384e-11;
__constant__ double SOFTENINGG = 1e-9f;
void writeSoA(double** f, int B, int size, const char *filename){
FILE* file;
file=fopen(filename, "w");
fprintf(file, "%d\n", B);
for (int i = 0; i < 5; i++){
for (int j = 0; j < size/5; j++){
fprintf(file, "%lf ", ((*f)[j + i*(size/5)]));
}
fprintf(file, "\n");
}
fclose(file);
}
void ReadSoA(double** f, int* B, const char *filename) {
FILE *fp;
fp = fopen(filename, "r");
fscanf(fp, "%d", B);
int size = (*B) * 5; // 5 atributos: masa, pos_x, pos_y, vel_x, vel_y
double* F = new double[size];
int i;
for (i = 0; i < size; i++) {
fscanf(fp, "%lf ", &(F[i]));
}
*f = F;
fclose(fp);
}
void printArray(int size, double *arr) {
printf("[");
for (int i = 0; i < size; i++) {
printf("%lf ", arr[i]);
}
printf("]\n");
}
void N_body_CPU(int size, double delta_t, double *f, double *fout, int T){
//printf("N_body_CPU\n");
for (int body_i = 0; body_i < size/5; body_i++){ // para cada cuerpo
//printf("body %d ", body_i);
//if (body_i == 95 && T == 0) printf("(%lf, %lf, %lf, %lf, %lf)\n", f[body_i], f[body_i + (size/5)], f[body_i + (size/5)*2], f[body_i + (size/5)*3], f[body_i + (size/5)*4]);
double mass1 = f[body_i];
double x1 = f[body_i + (size/5)];
double y1 = f[body_i + (size/5)*2];
double vx1 = f[body_i + (size/5)*3];
double vy1 = f[body_i + (size/5)*4];
double Fx = 0;
double Fy = 0;
for (int j = 0; j < size/5; j++){ // comparar con otros cuerpos
if (j == body_i) continue; // creo que puedo obviarlo pues el radio seria cero (aunque nos da division por cero)
double mass2 = f[j];
double x2 = f[j + (size/5)];
double y2 = f[j + (size/5)*2];
double distance = sqrt( pow(x2-x1, 2) + pow(y2-y1, 2) + pow(SOFTENING, 2) );
//if (body_i == 0) printf("distance: %lf\n", distance);
double angle = atan((y2-y1)/(x2-x1));
Fx += NEWTON_G*mass1*mass2/(pow(distance, 2)) * cos(angle);
Fy += NEWTON_G*mass1*mass2/(pow(distance, 2)) * sin(angle);
}
double new_vx1 = vx1 + Fx*delta_t/mass1;
double new_vy1 = vy1 + Fy*delta_t/mass1;
// a futuro, usar otro arreglo para la masa, pues no cambia
fout[body_i] = mass1;
fout[body_i + (size/5)] = x1 + new_vx1*delta_t; //new x
fout[body_i + (size/5)*2] = y1 + new_vy1*delta_t ; //new y
fout[body_i + (size/5)*3] = new_vx1; //new vx
fout[body_i + (size/5)*4] = new_vy1; //new vy
}
}
__global__ void N_body_GPU(int size, double delta_t, double *f, double *fout){
int body_i= threadIdx.x + blockDim.x*blockIdx.x;
if (body_i < size/5){
double mass1 = f[body_i];
double x1 = f[body_i + (size/5)];
double y1 = f[body_i + (size/5)*2];
double vx1 = f[body_i + (size/5)*3];
double vy1 = f[body_i + (size/5)*4];
double mass2,x2,y2,distance,angle,new_vx1,new_vy1;
double Fx = 0;
double Fy = 0;
for (int j = 0; j < size/5; j++){ // comparar con otros cuerpos
if (j != body_i){
mass2 = f[j];
x2 = f[j + (size/5)];
y2 = f[j + (size/5)*2];
distance = sqrt( (x2-x1)*(x2-x1) + (y2-y1)*(y2-y1) + SOFTENINGG);
//printf("distance: %lf\n", distance);
angle = atan((y2-y1)/(x2-x1));
Fx += NEWTON_GG*mass2/(pow(distance, 2)) * cos(angle);
Fy += NEWTON_GG*mass2/(pow(distance, 2)) * sin(angle);
}
}
//printf("F: %lf\n", F);
new_vx1 = vx1 + Fx*delta_t;
new_vy1 = vy1 + Fy*delta_t;
//printf("F*delta_t/mass1: %lf\n", F*delta_t/mass1);
//printf("new_vx1: %lf\n", new_vx1);
//printf("new_vy1: %lf\n", new_vy1);
// a futuro, usar otro arreglo para la masa, pues no cambia
fout[body_i] = mass1;
fout[body_i + (size/5)] = x1 + new_vx1*delta_t; //new x
fout[body_i + (size/5)*2] = y1 + new_vy1*delta_t ; //new y
fout[body_i + (size/5)*3] = new_vx1; //new vx
fout[body_i + (size/5)*4] = new_vy1; //new vy
}
}
__global__ void N_body_GPU_F(int size, double delta_t, double *f, double *fout,int T){
int body_i= threadIdx.x + blockDim.x*blockIdx.x;
if (body_i<size/5){
extern __shared__ double datos[];
// 5 atributos: masa
datos[body_i ]= f[body_i];
datos[body_i+ (size/5) ]= f[body_i + (size/5)];
datos[body_i+ (size/5)*2]= f[body_i + (size/5)*2];
double autx,auty,rx,ry,vx,vy;
vx=f[body_i+ (size/5)*3];
vy=f[body_i+ (size/5)*4];
double angle;
double Ax,Ay;
fout[body_i]=datos[body_i];
for (int t = 0; t < T; ++t){
__syncthreads();
Ax=0.0,Ay=0.0;
autx=datos[body_i+ (size/5) ];
auty=datos[body_i+ (size/5)*2];
auty=datos[body_i+ (size/5)*2];
for (int i = 0; i < size/5; ++i){
if (i!=body_i){
rx=autx-datos[i+ (size/5) ];
ry=auty-datos[i+ (size/5)*2];
angle=atan(ry/rx);
rx=datos[i]/sqrt(rx*rx+ry*ry+SOFTENINGG);
Ax += rx*cos(angle);
Ay += rx*sin(angle);
}
}
Ax*=NEWTON_GG*delta_t;
Ay*=NEWTON_GG*delta_t;
datos[body_i+ (size/5) ]=autx+vx*delta_t+Ax*delta_t;
datos[body_i+ (size/5)*2]=auty+vy*delta_t+Ay*delta_t;
vx=Ax+vx;
vy=Ay+vy;
}
fout[body_i+ (size/5) ]=autx+vx*delta_t+Ax*delta_t;
fout[body_i+ (size/5)*2]=auty+vy*delta_t+Ay*delta_t;
fout[body_i+ (size/5)*3]=Ax+vx;
fout[body_i+ (size/5)*4]=Ay+vy;
}
}
int main() {
cudaEvent_t ct1, ct2, ct3, ct4;
clock_t t1, t2;
double ms;
char filename[] = "input.txt";
char filename_out[] = "-CPU-Resultado.txt";
char filename_aux[30];
char final[] = "final";
char directory[] = "data/";
char directory_aux[30];
float dt,dt2;
//int iterator=2;
int B;
double *f, *fout, *fhost, *fhostout, *faux,*ff;
int grid_size, block_size = 256;
ReadSoA(&fhost, &B, filename);
int size = B*5;
cudaMalloc((void**)&f, size* sizeof(double));
cudaMalloc((void**)&ff, size* sizeof(double));
cudaMalloc((void**)&fout, size* sizeof(double));
cudaMemcpy(f, fhost, size* sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(ff, fhost, size* sizeof(double), cudaMemcpyHostToDevice);
int debug = 0;
if (debug){
printf("B: %d\n", B );
printf("size: %d\n", size);
printArray(size, fhost);
}
double delta_t = 0.01;
fhostout = new double[size];
if (debug){
printArray(size, fhost);
}
long T = 10000;
char integer_string[32];
char integer_string2[32];
/*** CPU ***/
int cpu = 1;
if (cpu){
t1 = clock();
for (long t = 0; t < T; t++){
N_body_CPU(size, delta_t, fhost, fhostout, t);
faux=fhost;
fhost = fhostout;
fhostout=faux;
if (t % 1000 == 0 || t == T-1){
sprintf(integer_string, "%d", t);
sprintf(integer_string2, "-%d", T);
strcpy(filename_aux, filename_out);
strcpy(directory_aux, directory);
writeSoA(&fhostout, B, size,
strcat(directory_aux, strcat(integer_string, strcat(integer_string2, filename_aux) ) ));
}
//printArray(size, fhostout);
//std::cout << "-----------------------" << std::endl;
}
t2 = clock();
if (debug){
printArray(size, fhost);
}
ms = 1000.0 * (double)(t2 - t1) / CLOCKS_PER_SEC;
std::cout << "Tiempo CPU : " << ms << "[ms]" << std::endl;
//writeSoA(&fhostout, B, size, strcat(final, filename_out) );
}
int long_simulation = 0;
if (long_simulation){
T = 20000*20;
}
/*** GPU ***/
int gpu1 = 1;
if (gpu1){
char filename_outGPU[] = "-GPU-Resultado.txt";
grid_size = (int)ceil((float) B / block_size);
cudaEventCreate(&ct1);
cudaEventCreate(&ct2);
cudaEventRecord(ct1);
for (long t = 0; t < T; t++){
N_body_GPU<<<grid_size, block_size>>>(size, delta_t, f, fout);
faux = fout;
fout = f;
f = faux;
if (t % 1000 == 0 || t == T-1){
sprintf(integer_string, "%d", t);
sprintf(integer_string2, "-%d", T);
strcpy(filename_aux, filename_outGPU);
strcpy(directory_aux, directory);
cudaMemcpy(fhostout, f, size* sizeof(double), cudaMemcpyDeviceToHost);
writeSoA(&fhostout, B, size,
strcat(directory_aux, strcat(integer_string, strcat(integer_string2, filename_aux))) );
}
}
cudaEventRecord(ct2);
cudaEventSynchronize(ct2);
cudaEventElapsedTime(&dt, ct1, ct2);
std::cout << "Tiempo GPU : " << dt << "[ms]" << std::endl;
cudaMemcpy(fhostout, f, size* sizeof(double), cudaMemcpyDeviceToHost);
//strcpy(filename_out, "GPU-Resultado.txt");
//writeSoA(&fhostout, B, size, filename_outGPU);
}
/*** GPU Fast ***/
char filename_outFPU[] = "data/FPU-Resultado.txt";
grid_size = (int)ceil((float) B / block_size);
cudaEventCreate(&ct3);
cudaEventCreate(&ct4);
cudaEventRecord(ct3);
N_body_GPU_F<<<grid_size, block_size,B*3* sizeof(double)>>>(size, delta_t, ff, fout,T);
cudaEventRecord(ct4);
cudaEventSynchronize(ct4);
cudaEventElapsedTime(&dt2, ct3, ct4);
std::cout << "Tiempo GPU-F: " << dt2 << "[ms]" << std::endl;
cudaMemcpy(fhostout, fout, size* sizeof(double), cudaMemcpyDeviceToHost);
writeSoA(&fhostout, B, size, filename_outFPU);
delete[] fhostout;
} | .file "tmpxft_001084d1_00000000-6_n_body.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "w"
.LC1:
.string "%d\n"
.LC2:
.string "%lf "
.LC3:
.string "\n"
.text
.globl _Z8writeSoAPPdiiPKc
.type _Z8writeSoAPPdiiPKc, @function
_Z8writeSoAPPdiiPKc:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r14
movl %esi, %ebx
movl %edx, %r15d
movl %edx, 12(%rsp)
movq %rcx, %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %r13
movl %ebx, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movslq %r15d, %r12
imulq $1717986919, %r12, %r12
sarq $33, %r12
sarl $31, %r15d
subl %r15d, %r12d
movl $0, 4(%rsp)
movl $5, 8(%rsp)
leaq .LC2(%rip), %r15
.L4:
movslq 4(%rsp), %rbx
salq $3, %rbx
movl $0, %ebp
cmpl $4, 12(%rsp)
jle .L8
.L5:
movq (%r14), %rax
movsd (%rax,%rbx), %xmm0
movq %r15, %rdx
movl $2, %esi
movq %r13, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addl $1, %ebp
addq $8, %rbx
cmpl %r12d, %ebp
jl .L5
.L8:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl %r12d, 4(%rsp)
subl $1, 8(%rsp)
jne .L4
movq %r13, %rdi
call fclose@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z8writeSoAPPdiiPKc, .-_Z8writeSoAPPdiiPKc
.section .rodata.str1.1
.LC4:
.string "r"
.LC5:
.string "%d"
.text
.globl _Z7ReadSoAPPdPiPKc
.type _Z7ReadSoAPPdPiPKc, @function
_Z7ReadSoAPPdPiPKc:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r15
movq %rsi, %rbx
movq %rdx, %rdi
leaq .LC4(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movq %rbx, %rdx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl (%rbx), %r12d
leal (%r12,%r12,4), %ebx
movslq %ebx, %rdi
movq %rdi, %rax
shrq $60, %rax
jne .L13
salq $3, %rdi
call _Znam@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L15
movq %rax, %rbx
leal -1(%r12,%r12,4), %eax
leaq 8(%r14,%rax,8), %r13
leaq .LC2(%rip), %r12
.L16:
movq %rbx, %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $8, %rbx
cmpq %r13, %rbx
jne .L16
.L15:
movq %r14, (%r15)
movq %rbp, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE3670:
.size _Z7ReadSoAPPdPiPKc, .-_Z7ReadSoAPPdPiPKc
.section .rodata.str1.1
.LC6:
.string "["
.LC7:
.string "]\n"
.text
.globl _Z10printArrayiPd
.type _Z10printArrayiPd, @function
_Z10printArrayiPd:
.LFB3671:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebp
movq %rsi, %r12
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L20
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,8), %r12
leaq .LC2(%rip), %rbp
.L21:
movsd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L21
.L20:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z10printArrayiPd, .-_Z10printArrayiPd
.globl _Z10N_body_CPUidPdS_i
.type _Z10N_body_CPUidPdS_i, @function
_Z10N_body_CPUidPdS_i:
.LFB3672:
.cfi_startproc
endbr64
movq %rdx, %r8
movslq %edi, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %edi, %edx
sarl $31, %edx
subl %edx, %eax
cmpl $4, %edi
jle .L32
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movapd %xmm0, %xmm1
movq %rsi, %rbp
movl %eax, %r14d
movslq %eax, %rcx
salq $3, %rcx
leal (%rax,%rax), %r12d
movslq %r12d, %rdx
salq $3, %rdx
leaq (%rsi,%rdx), %r9
leaq (%r8,%rdx), %rax
movl $0, %r15d
leaq 136(%rsp), %rsi
movq %rsi, 56(%rsp)
movq %r15, %r13
movl %r12d, %r15d
jmp .L28
.L36:
movsd 0(%rbp,%rbx,8), %xmm5
movsd %xmm5, 16(%rsp)
leal (%r14,%rbx), %eax
cltq
movsd 0(%rbp,%rax,8), %xmm1
subsd 32(%rsp), %xmm1
leal (%r15,%rbx), %eax
cltq
movsd 0(%rbp,%rax,8), %xmm0
subsd 40(%rsp), %xmm0
movapd %xmm1, %xmm2
mulsd %xmm1, %xmm2
movapd %xmm0, %xmm4
mulsd %xmm0, %xmm4
addsd %xmm4, %xmm2
addsd .LC9(%rip), %xmm2
sqrtsd %xmm2, %xmm2
movsd %xmm2, 24(%rsp)
divsd %xmm1, %xmm0
call atan@PLT
movq %r12, %rsi
movq 56(%rsp), %rdi
call sincos@PLT
movsd 48(%rsp), %xmm0
mulsd .LC10(%rip), %xmm0
mulsd 16(%rsp), %xmm0
movsd 24(%rsp), %xmm1
mulsd %xmm1, %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm2
mulsd 128(%rsp), %xmm2
addsd (%rsp), %xmm2
movsd %xmm2, (%rsp)
mulsd 136(%rsp), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
.L26:
addq $1, %rbx
cmpl %ebx, %r14d
jle .L35
.L27:
cmpl %r13d, %ebx
jne .L36
jmp .L26
.L35:
movq 80(%rsp), %rcx
movsd 48(%rsp), %xmm3
movq 88(%rsp), %rdx
movq 96(%rsp), %r9
movq 104(%rsp), %rax
movsd 112(%rsp), %xmm1
movq 120(%rsp), %r8
movsd (%rsp), %xmm2
mulsd %xmm1, %xmm2
divsd %xmm3, %xmm2
addsd 64(%rsp), %xmm2
movsd 8(%rsp), %xmm0
mulsd %xmm1, %xmm0
divsd %xmm3, %xmm0
addsd 72(%rsp), %xmm0
movsd %xmm3, (%r8,%r13,8)
movapd %xmm1, %xmm3
mulsd %xmm2, %xmm3
addsd 32(%rsp), %xmm3
movsd %xmm3, (%r8,%rcx)
movapd %xmm1, %xmm3
mulsd %xmm0, %xmm3
addsd 40(%rsp), %xmm3
movsd %xmm3, (%r8,%rdx)
movsd %xmm2, (%rax,%rcx)
movsd %xmm0, (%rax,%rdx)
addq $1, %r13
addq $8, %rcx
addq $8, %rdx
cmpl %r13d, %r14d
jle .L37
.L28:
movsd 0(%rbp,%r13,8), %xmm3
movsd 0(%rbp,%rcx), %xmm5
movsd %xmm5, 32(%rsp)
movsd 0(%rbp,%rdx), %xmm6
movsd %xmm6, 40(%rsp)
movsd (%r9,%rcx), %xmm7
movsd %xmm7, 64(%rsp)
movsd (%r9,%rdx), %xmm5
movsd %xmm5, 72(%rsp)
movl $0, %ebx
movq $0x000000000, 8(%rsp)
movq $0x000000000, (%rsp)
leaq 128(%rsp), %r12
movq %rcx, 80(%rsp)
movsd %xmm3, 48(%rsp)
movq %rdx, 88(%rsp)
movq %r9, 96(%rsp)
movq %rax, 104(%rsp)
movsd %xmm1, 112(%rsp)
movq %r8, 120(%rsp)
jmp .L27
.L37:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE3672:
.size _Z10N_body_CPUidPdS_i, .-_Z10N_body_CPUidPdS_i
.globl _Z34__device_stub__Z10N_body_GPUidPdS_idPdS_
.type _Z34__device_stub__Z10N_body_GPUidPdS_idPdS_, @function
_Z34__device_stub__Z10N_body_GPUidPdS_idPdS_:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movsd %xmm0, 16(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L42
.L38:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10N_body_GPUidPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L38
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z34__device_stub__Z10N_body_GPUidPdS_idPdS_, .-_Z34__device_stub__Z10N_body_GPUidPdS_idPdS_
.globl _Z10N_body_GPUidPdS_
.type _Z10N_body_GPUidPdS_, @function
_Z10N_body_GPUidPdS_:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10N_body_GPUidPdS_idPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z10N_body_GPUidPdS_, .-_Z10N_body_GPUidPdS_
.globl _Z37__device_stub__Z12N_body_GPU_FidPdS_iidPdS_i
.type _Z37__device_stub__Z12N_body_GPU_FidPdS_iidPdS_i, @function
_Z37__device_stub__Z12N_body_GPU_FidPdS_iidPdS_i:
.LFB3701:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movsd %xmm0, 16(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L50
.L46:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12N_body_GPU_FidPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L46
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z37__device_stub__Z12N_body_GPU_FidPdS_iidPdS_i, .-_Z37__device_stub__Z12N_body_GPU_FidPdS_iidPdS_i
.globl _Z12N_body_GPU_FidPdS_i
.type _Z12N_body_GPU_FidPdS_i, @function
_Z12N_body_GPU_FidPdS_i:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12N_body_GPU_FidPdS_iidPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z12N_body_GPU_FidPdS_i, .-_Z12N_body_GPU_FidPdS_i
.section .rodata.str1.1
.LC12:
.string "-%d"
.LC15:
.string "Tiempo CPU : "
.LC16:
.string "[ms]"
.LC21:
.string "Tiempo GPU : "
.LC22:
.string "Tiempo GPU-F: "
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $376, %rsp
.cfi_def_cfa_offset 432
movq %fs:40, %rax
movq %rax, 360(%rsp)
xorl %eax, %eax
movabsq $8679613459571175017, %rax
movq %rax, 150(%rsp)
movw $116, 158(%rsp)
movabsq $8315142641667818285, %rax
movabsq $8371751234250763381, %rdx
movq %rax, 160(%rsp)
movq %rdx, 168(%rsp)
movl $7633012, 175(%rsp)
movl $1635017060, 144(%rsp)
movw $47, 148(%rsp)
leaq 150(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 96(%rsp), %rdi
call _Z7ReadSoAPPdPiPKc
movl 44(%rsp), %eax
leal (%rax,%rax,4), %r14d
movslq %r14d, %rbx
leaq 0(,%rbx,8), %r15
movq %r15, 24(%rsp)
leaq 80(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movq 96(%rsp), %rbp
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
shrq $60, %rbx
jne .L55
movq %r15, %rdi
call _Znam@PLT
movq %rax, 104(%rsp)
call clock@PLT
movl $0, %ebx
movq %rax, 16(%rsp)
jmp .L56
.L55:
movq 360(%rsp), %rax
subq %fs:40, %rax
je .L57
call __stack_chk_fail@PLT
.L57:
call __cxa_throw_bad_array_new_length@PLT
.L76:
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movsd .LC11(%rip), %xmm0
movl %r14d, %edi
call _Z34__device_stub__Z10N_body_GPUidPdS_idPdS_
jmp .L62
.L77:
movl $10000, %ecx
movq 88(%rsp), %rdx
movq 112(%rsp), %rsi
movsd .LC11(%rip), %xmm0
movl %r14d, %edi
call _Z37__device_stub__Z12N_body_GPU_FidPdS_iidPdS_i
jmp .L68
.L63:
addq $1, %rbx
.L66:
movl $256, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl 8(%rsp), %eax
movl %eax, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movl $1, %ecx
movq 120(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L76
.L62:
movq 88(%rsp), %rax
movq 80(%rsp), %rdx
movq %rdx, 88(%rsp)
movq %rax, 80(%rsp)
movabsq $2361183241434822607, %rax
imulq %rbx
sarq $7, %rdx
movq %rbx, %rax
sarq $63, %rax
subq %rax, %rdx
imulq $1000, %rdx, %rdx
cmpq %rdx, %rbx
je .L73
cmpq $9999, %rbx
jne .L63
.L73:
leaq 288(%rsp), %rax
movq %rbx, %r8
leaq .LC5(%rip), %rcx
movl $32, %edx
movl $2, %esi
movq %rax, 16(%rsp)
movq %rax, %rdi
movl $0, %eax
call __sprintf_chk@PLT
leaq 320(%rsp), %r13
movl $10000, %r8d
leaq .LC12(%rip), %rcx
movl $32, %edx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __sprintf_chk@PLT
leaq 192(%rsp), %rsi
leaq 224(%rsp), %r15
movl $30, %edx
movq %r15, %rdi
call __strcpy_chk@PLT
leaq 144(%rsp), %rsi
leaq 256(%rsp), %r12
movl $30, %edx
movq %r12, %rdi
call __strcpy_chk@PLT
movl $2, %ecx
movq 24(%rsp), %rdx
movq 80(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $32, %edx
movq %r15, %rsi
movq %r13, %rdi
call __strcat_chk@PLT
movq %r13, %rsi
movl $32, %edx
movq 16(%rsp), %rdi
call __strcat_chk@PLT
movq %rax, %rsi
movl $30, %edx
movq %r12, %rdi
call __strcat_chk@PLT
movq %r12, %rcx
leaq 104(%rsp), %rdi
movl %r14d, %edx
movl 44(%rsp), %esi
call _Z8writeSoAPPdiiPKc
addq $1, %rbx
cmpq $10000, %rbx
jne .L66
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 40(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC21(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 40(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC16(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movq 24(%rsp), %rdx
movq 80(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movabsq $6147490660673151332, %rax
movabsq $7022356970680439341, %rdx
movq %rax, 192(%rsp)
movq %rdx, 200(%rsp)
movabsq $32783537689027681, %rax
movq %rax, 207(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl 44(%rsp), %xmm0
mulss .LC17(%rip), %xmm0
movss %xmm0, 8(%rsp)
movss .LC23(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC18(%rip), %xmm3
ucomiss %xmm1, %xmm3
jbe .L67
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movaps %xmm0, %xmm3
cmpnless %xmm1, %xmm3
movss .LC20(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm3, %xmm1
andnps %xmm0, %xmm2
orps %xmm2, %xmm1
movss %xmm1, 8(%rsp)
.L67:
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl 44(%rsp), %eax
leal (%rax,%rax,2), %eax
cltq
movl $256, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
cvttss2sil 8(%rsp), %edx
movl %edx, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $0, %r9d
leaq 0(,%rax,8), %r8
movq 132(%rsp), %rdx
movl $1, %ecx
movq 120(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L77
.L68:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 132(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 132(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC16(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movq 24(%rsp), %rdx
movq 88(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 192(%rsp), %rcx
leaq 104(%rsp), %rdi
movl %r14d, %edx
movl 44(%rsp), %esi
call _Z8writeSoAPPdiiPKc
testq %rbp, %rbp
je .L69
movq %rbp, %rdi
call _ZdaPv@PLT
.L69:
movq 360(%rsp), %rax
subq %fs:40, %rax
jne .L78
movl $0, %eax
addq $376, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
addq $1, %rbx
.L56:
movq 104(%rsp), %r12
movq 96(%rsp), %rbp
movl %ebx, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movsd .LC11(%rip), %xmm0
movl %r14d, %edi
call _Z10N_body_CPUidPdS_i
movq %r12, 96(%rsp)
movq %rbp, 104(%rsp)
movabsq $2361183241434822607, %rax
imulq %rbx
sarq $7, %rdx
movq %rbx, %rax
sarq $63, %rax
subq %rax, %rdx
imulq $1000, %rdx, %rdx
cmpq %rdx, %rbx
je .L72
cmpq $9999, %rbx
jne .L58
.L72:
leaq 288(%rsp), %r13
movq %rbx, %r8
leaq .LC5(%rip), %rcx
movl $32, %edx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __sprintf_chk@PLT
leaq 320(%rsp), %rax
movl $10000, %r8d
leaq .LC12(%rip), %rcx
movl $32, %edx
movl $2, %esi
movq %rax, 8(%rsp)
movq %rax, %rdi
movl $0, %eax
call __sprintf_chk@PLT
leaq 160(%rsp), %rsi
leaq 224(%rsp), %r15
movl $30, %edx
movq %r15, %rdi
call __strcpy_chk@PLT
leaq 144(%rsp), %rsi
leaq 256(%rsp), %r12
movl $30, %edx
movq %r12, %rdi
call __strcpy_chk@PLT
movl $32, %edx
movq %r15, %rsi
movq 8(%rsp), %rdi
call __strcat_chk@PLT
movq %rax, %rsi
movl $32, %edx
movq %r13, %rdi
call __strcat_chk@PLT
movq %r13, %rsi
movl $30, %edx
movq %r12, %rdi
call __strcat_chk@PLT
movq %r12, %rcx
leaq 104(%rsp), %rdi
movl %r14d, %edx
movl 44(%rsp), %esi
call _Z8writeSoAPPdiiPKc
addq $1, %rbx
cmpq $10000, %rbx
jne .L56
movq 16(%rsp), %r13
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC13(%rip), %xmm0
divsd .LC14(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC16(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movabsq $8315142641667819309, %rax
movabsq $8371751234250763381, %rdx
movq %rax, 192(%rsp)
movq %rdx, 200(%rsp)
movl $7633012, 207(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl 44(%rsp), %xmm0
mulss .LC17(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC23(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC18(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L61
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC20(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L61:
cvttss2sil %xmm3, %eax
movl %eax, 8(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
jmp .L66
.L78:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.1
.LC24:
.string "_Z12N_body_GPU_FidPdS_i"
.LC25:
.string "_Z10N_body_GPUidPdS_"
.LC26:
.string "NEWTON_GG"
.LC27:
.string "SOFTENINGG"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3704:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z12N_body_GPU_FidPdS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z10N_body_GPUidPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9NEWTON_GG(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10SOFTENINGG(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL10SOFTENINGG
.comm _ZL10SOFTENINGG,8,8
.local _ZL9NEWTON_GG
.comm _ZL9NEWTON_GG,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long -1068445632
.long 1009939037
.align 8
.LC10:
.long 573314622
.long 1037195340
.align 8
.LC11:
.long 1202590843
.long 1065646817
.align 8
.LC13:
.long 0
.long 1083129856
.align 8
.LC14:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC17:
.long 998244352
.align 4
.LC18:
.long 1258291200
.align 4
.LC20:
.long 1065353216
.align 4
.LC23:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda_runtime.h>
#include<cmath>
const double NEWTON_G = 6.67384e-11;
const double SOFTENING = 1e-9f;
__constant__ double NEWTON_GG = 6.67384e-11;
__constant__ double SOFTENINGG = 1e-9f;
void writeSoA(double** f, int B, int size, const char *filename){
FILE* file;
file=fopen(filename, "w");
fprintf(file, "%d\n", B);
for (int i = 0; i < 5; i++){
for (int j = 0; j < size/5; j++){
fprintf(file, "%lf ", ((*f)[j + i*(size/5)]));
}
fprintf(file, "\n");
}
fclose(file);
}
void ReadSoA(double** f, int* B, const char *filename) {
FILE *fp;
fp = fopen(filename, "r");
fscanf(fp, "%d", B);
int size = (*B) * 5; // 5 atributos: masa, pos_x, pos_y, vel_x, vel_y
double* F = new double[size];
int i;
for (i = 0; i < size; i++) {
fscanf(fp, "%lf ", &(F[i]));
}
*f = F;
fclose(fp);
}
void printArray(int size, double *arr) {
printf("[");
for (int i = 0; i < size; i++) {
printf("%lf ", arr[i]);
}
printf("]\n");
}
void N_body_CPU(int size, double delta_t, double *f, double *fout, int T){
//printf("N_body_CPU\n");
for (int body_i = 0; body_i < size/5; body_i++){ // para cada cuerpo
//printf("body %d ", body_i);
//if (body_i == 95 && T == 0) printf("(%lf, %lf, %lf, %lf, %lf)\n", f[body_i], f[body_i + (size/5)], f[body_i + (size/5)*2], f[body_i + (size/5)*3], f[body_i + (size/5)*4]);
double mass1 = f[body_i];
double x1 = f[body_i + (size/5)];
double y1 = f[body_i + (size/5)*2];
double vx1 = f[body_i + (size/5)*3];
double vy1 = f[body_i + (size/5)*4];
double Fx = 0;
double Fy = 0;
for (int j = 0; j < size/5; j++){ // comparar con otros cuerpos
if (j == body_i) continue; // creo que puedo obviarlo pues el radio seria cero (aunque nos da division por cero)
double mass2 = f[j];
double x2 = f[j + (size/5)];
double y2 = f[j + (size/5)*2];
double distance = sqrt( pow(x2-x1, 2) + pow(y2-y1, 2) + pow(SOFTENING, 2) );
//if (body_i == 0) printf("distance: %lf\n", distance);
double angle = atan((y2-y1)/(x2-x1));
Fx += NEWTON_G*mass1*mass2/(pow(distance, 2)) * cos(angle);
Fy += NEWTON_G*mass1*mass2/(pow(distance, 2)) * sin(angle);
}
double new_vx1 = vx1 + Fx*delta_t/mass1;
double new_vy1 = vy1 + Fy*delta_t/mass1;
// a futuro, usar otro arreglo para la masa, pues no cambia
fout[body_i] = mass1;
fout[body_i + (size/5)] = x1 + new_vx1*delta_t; //new x
fout[body_i + (size/5)*2] = y1 + new_vy1*delta_t ; //new y
fout[body_i + (size/5)*3] = new_vx1; //new vx
fout[body_i + (size/5)*4] = new_vy1; //new vy
}
}
__global__ void N_body_GPU(int size, double delta_t, double *f, double *fout){
int body_i= threadIdx.x + blockDim.x*blockIdx.x;
if (body_i < size/5){
double mass1 = f[body_i];
double x1 = f[body_i + (size/5)];
double y1 = f[body_i + (size/5)*2];
double vx1 = f[body_i + (size/5)*3];
double vy1 = f[body_i + (size/5)*4];
double mass2,x2,y2,distance,angle,new_vx1,new_vy1;
double Fx = 0;
double Fy = 0;
for (int j = 0; j < size/5; j++){ // comparar con otros cuerpos
if (j != body_i){
mass2 = f[j];
x2 = f[j + (size/5)];
y2 = f[j + (size/5)*2];
distance = sqrt( (x2-x1)*(x2-x1) + (y2-y1)*(y2-y1) + SOFTENINGG);
//printf("distance: %lf\n", distance);
angle = atan((y2-y1)/(x2-x1));
Fx += NEWTON_GG*mass2/(pow(distance, 2)) * cos(angle);
Fy += NEWTON_GG*mass2/(pow(distance, 2)) * sin(angle);
}
}
//printf("F: %lf\n", F);
new_vx1 = vx1 + Fx*delta_t;
new_vy1 = vy1 + Fy*delta_t;
//printf("F*delta_t/mass1: %lf\n", F*delta_t/mass1);
//printf("new_vx1: %lf\n", new_vx1);
//printf("new_vy1: %lf\n", new_vy1);
// a futuro, usar otro arreglo para la masa, pues no cambia
fout[body_i] = mass1;
fout[body_i + (size/5)] = x1 + new_vx1*delta_t; //new x
fout[body_i + (size/5)*2] = y1 + new_vy1*delta_t ; //new y
fout[body_i + (size/5)*3] = new_vx1; //new vx
fout[body_i + (size/5)*4] = new_vy1; //new vy
}
}
__global__ void N_body_GPU_F(int size, double delta_t, double *f, double *fout,int T){
int body_i= threadIdx.x + blockDim.x*blockIdx.x;
if (body_i<size/5){
extern __shared__ double datos[];
// 5 atributos: masa
datos[body_i ]= f[body_i];
datos[body_i+ (size/5) ]= f[body_i + (size/5)];
datos[body_i+ (size/5)*2]= f[body_i + (size/5)*2];
double autx,auty,rx,ry,vx,vy;
vx=f[body_i+ (size/5)*3];
vy=f[body_i+ (size/5)*4];
double angle;
double Ax,Ay;
fout[body_i]=datos[body_i];
for (int t = 0; t < T; ++t){
__syncthreads();
Ax=0.0,Ay=0.0;
autx=datos[body_i+ (size/5) ];
auty=datos[body_i+ (size/5)*2];
auty=datos[body_i+ (size/5)*2];
for (int i = 0; i < size/5; ++i){
if (i!=body_i){
rx=autx-datos[i+ (size/5) ];
ry=auty-datos[i+ (size/5)*2];
angle=atan(ry/rx);
rx=datos[i]/sqrt(rx*rx+ry*ry+SOFTENINGG);
Ax += rx*cos(angle);
Ay += rx*sin(angle);
}
}
Ax*=NEWTON_GG*delta_t;
Ay*=NEWTON_GG*delta_t;
datos[body_i+ (size/5) ]=autx+vx*delta_t+Ax*delta_t;
datos[body_i+ (size/5)*2]=auty+vy*delta_t+Ay*delta_t;
vx=Ax+vx;
vy=Ay+vy;
}
fout[body_i+ (size/5) ]=autx+vx*delta_t+Ax*delta_t;
fout[body_i+ (size/5)*2]=auty+vy*delta_t+Ay*delta_t;
fout[body_i+ (size/5)*3]=Ax+vx;
fout[body_i+ (size/5)*4]=Ay+vy;
}
}
int main() {
cudaEvent_t ct1, ct2, ct3, ct4;
clock_t t1, t2;
double ms;
char filename[] = "input.txt";
char filename_out[] = "-CPU-Resultado.txt";
char filename_aux[30];
char final[] = "final";
char directory[] = "data/";
char directory_aux[30];
float dt,dt2;
//int iterator=2;
int B;
double *f, *fout, *fhost, *fhostout, *faux,*ff;
int grid_size, block_size = 256;
ReadSoA(&fhost, &B, filename);
int size = B*5;
cudaMalloc((void**)&f, size* sizeof(double));
cudaMalloc((void**)&ff, size* sizeof(double));
cudaMalloc((void**)&fout, size* sizeof(double));
cudaMemcpy(f, fhost, size* sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy(ff, fhost, size* sizeof(double), cudaMemcpyHostToDevice);
int debug = 0;
if (debug){
printf("B: %d\n", B );
printf("size: %d\n", size);
printArray(size, fhost);
}
double delta_t = 0.01;
fhostout = new double[size];
if (debug){
printArray(size, fhost);
}
long T = 10000;
char integer_string[32];
char integer_string2[32];
/*** CPU ***/
int cpu = 1;
if (cpu){
t1 = clock();
for (long t = 0; t < T; t++){
N_body_CPU(size, delta_t, fhost, fhostout, t);
faux=fhost;
fhost = fhostout;
fhostout=faux;
if (t % 1000 == 0 || t == T-1){
sprintf(integer_string, "%d", t);
sprintf(integer_string2, "-%d", T);
strcpy(filename_aux, filename_out);
strcpy(directory_aux, directory);
writeSoA(&fhostout, B, size,
strcat(directory_aux, strcat(integer_string, strcat(integer_string2, filename_aux) ) ));
}
//printArray(size, fhostout);
//std::cout << "-----------------------" << std::endl;
}
t2 = clock();
if (debug){
printArray(size, fhost);
}
ms = 1000.0 * (double)(t2 - t1) / CLOCKS_PER_SEC;
std::cout << "Tiempo CPU : " << ms << "[ms]" << std::endl;
//writeSoA(&fhostout, B, size, strcat(final, filename_out) );
}
int long_simulation = 0;
if (long_simulation){
T = 20000*20;
}
/*** GPU ***/
int gpu1 = 1;
if (gpu1){
char filename_outGPU[] = "-GPU-Resultado.txt";
grid_size = (int)ceil((float) B / block_size);
cudaEventCreate(&ct1);
cudaEventCreate(&ct2);
cudaEventRecord(ct1);
for (long t = 0; t < T; t++){
N_body_GPU<<<grid_size, block_size>>>(size, delta_t, f, fout);
faux = fout;
fout = f;
f = faux;
if (t % 1000 == 0 || t == T-1){
sprintf(integer_string, "%d", t);
sprintf(integer_string2, "-%d", T);
strcpy(filename_aux, filename_outGPU);
strcpy(directory_aux, directory);
cudaMemcpy(fhostout, f, size* sizeof(double), cudaMemcpyDeviceToHost);
writeSoA(&fhostout, B, size,
strcat(directory_aux, strcat(integer_string, strcat(integer_string2, filename_aux))) );
}
}
cudaEventRecord(ct2);
cudaEventSynchronize(ct2);
cudaEventElapsedTime(&dt, ct1, ct2);
std::cout << "Tiempo GPU : " << dt << "[ms]" << std::endl;
cudaMemcpy(fhostout, f, size* sizeof(double), cudaMemcpyDeviceToHost);
//strcpy(filename_out, "GPU-Resultado.txt");
//writeSoA(&fhostout, B, size, filename_outGPU);
}
/*** GPU Fast ***/
char filename_outFPU[] = "data/FPU-Resultado.txt";
grid_size = (int)ceil((float) B / block_size);
cudaEventCreate(&ct3);
cudaEventCreate(&ct4);
cudaEventRecord(ct3);
N_body_GPU_F<<<grid_size, block_size,B*3* sizeof(double)>>>(size, delta_t, ff, fout,T);
cudaEventRecord(ct4);
cudaEventSynchronize(ct4);
cudaEventElapsedTime(&dt2, ct3, ct4);
std::cout << "Tiempo GPU-F: " << dt2 << "[ms]" << std::endl;
cudaMemcpy(fhostout, fout, size* sizeof(double), cudaMemcpyDeviceToHost);
writeSoA(&fhostout, B, size, filename_outFPU);
delete[] fhostout;
} | #include <iostream>
#include <hip/hip_runtime.h>
#include<cmath>
const double NEWTON_G = 6.67384e-11;
const double SOFTENING = 1e-9f;
__constant__ double NEWTON_GG = 6.67384e-11;
__constant__ double SOFTENINGG = 1e-9f;
void writeSoA(double** f, int B, int size, const char *filename){
FILE* file;
file=fopen(filename, "w");
fprintf(file, "%d\n", B);
for (int i = 0; i < 5; i++){
for (int j = 0; j < size/5; j++){
fprintf(file, "%lf ", ((*f)[j + i*(size/5)]));
}
fprintf(file, "\n");
}
fclose(file);
}
void ReadSoA(double** f, int* B, const char *filename) {
FILE *fp;
fp = fopen(filename, "r");
fscanf(fp, "%d", B);
int size = (*B) * 5; // 5 atributos: masa, pos_x, pos_y, vel_x, vel_y
double* F = new double[size];
int i;
for (i = 0; i < size; i++) {
fscanf(fp, "%lf ", &(F[i]));
}
*f = F;
fclose(fp);
}
void printArray(int size, double *arr) {
printf("[");
for (int i = 0; i < size; i++) {
printf("%lf ", arr[i]);
}
printf("]\n");
}
void N_body_CPU(int size, double delta_t, double *f, double *fout, int T){
//printf("N_body_CPU\n");
for (int body_i = 0; body_i < size/5; body_i++){ // para cada cuerpo
//printf("body %d ", body_i);
//if (body_i == 95 && T == 0) printf("(%lf, %lf, %lf, %lf, %lf)\n", f[body_i], f[body_i + (size/5)], f[body_i + (size/5)*2], f[body_i + (size/5)*3], f[body_i + (size/5)*4]);
double mass1 = f[body_i];
double x1 = f[body_i + (size/5)];
double y1 = f[body_i + (size/5)*2];
double vx1 = f[body_i + (size/5)*3];
double vy1 = f[body_i + (size/5)*4];
double Fx = 0;
double Fy = 0;
for (int j = 0; j < size/5; j++){ // comparar con otros cuerpos
if (j == body_i) continue; // creo que puedo obviarlo pues el radio seria cero (aunque nos da division por cero)
double mass2 = f[j];
double x2 = f[j + (size/5)];
double y2 = f[j + (size/5)*2];
double distance = sqrt( pow(x2-x1, 2) + pow(y2-y1, 2) + pow(SOFTENING, 2) );
//if (body_i == 0) printf("distance: %lf\n", distance);
double angle = atan((y2-y1)/(x2-x1));
Fx += NEWTON_G*mass1*mass2/(pow(distance, 2)) * cos(angle);
Fy += NEWTON_G*mass1*mass2/(pow(distance, 2)) * sin(angle);
}
double new_vx1 = vx1 + Fx*delta_t/mass1;
double new_vy1 = vy1 + Fy*delta_t/mass1;
// a futuro, usar otro arreglo para la masa, pues no cambia
fout[body_i] = mass1;
fout[body_i + (size/5)] = x1 + new_vx1*delta_t; //new x
fout[body_i + (size/5)*2] = y1 + new_vy1*delta_t ; //new y
fout[body_i + (size/5)*3] = new_vx1; //new vx
fout[body_i + (size/5)*4] = new_vy1; //new vy
}
}
__global__ void N_body_GPU(int size, double delta_t, double *f, double *fout){
int body_i= threadIdx.x + blockDim.x*blockIdx.x;
if (body_i < size/5){
double mass1 = f[body_i];
double x1 = f[body_i + (size/5)];
double y1 = f[body_i + (size/5)*2];
double vx1 = f[body_i + (size/5)*3];
double vy1 = f[body_i + (size/5)*4];
double mass2,x2,y2,distance,angle,new_vx1,new_vy1;
double Fx = 0;
double Fy = 0;
for (int j = 0; j < size/5; j++){ // comparar con otros cuerpos
if (j != body_i){
mass2 = f[j];
x2 = f[j + (size/5)];
y2 = f[j + (size/5)*2];
distance = sqrt( (x2-x1)*(x2-x1) + (y2-y1)*(y2-y1) + SOFTENINGG);
//printf("distance: %lf\n", distance);
angle = atan((y2-y1)/(x2-x1));
Fx += NEWTON_GG*mass2/(pow(distance, 2)) * cos(angle);
Fy += NEWTON_GG*mass2/(pow(distance, 2)) * sin(angle);
}
}
//printf("F: %lf\n", F);
new_vx1 = vx1 + Fx*delta_t;
new_vy1 = vy1 + Fy*delta_t;
//printf("F*delta_t/mass1: %lf\n", F*delta_t/mass1);
//printf("new_vx1: %lf\n", new_vx1);
//printf("new_vy1: %lf\n", new_vy1);
// a futuro, usar otro arreglo para la masa, pues no cambia
fout[body_i] = mass1;
fout[body_i + (size/5)] = x1 + new_vx1*delta_t; //new x
fout[body_i + (size/5)*2] = y1 + new_vy1*delta_t ; //new y
fout[body_i + (size/5)*3] = new_vx1; //new vx
fout[body_i + (size/5)*4] = new_vy1; //new vy
}
}
__global__ void N_body_GPU_F(int size, double delta_t, double *f, double *fout,int T){
int body_i= threadIdx.x + blockDim.x*blockIdx.x;
if (body_i<size/5){
extern __shared__ double datos[];
// 5 atributos: masa
datos[body_i ]= f[body_i];
datos[body_i+ (size/5) ]= f[body_i + (size/5)];
datos[body_i+ (size/5)*2]= f[body_i + (size/5)*2];
double autx,auty,rx,ry,vx,vy;
vx=f[body_i+ (size/5)*3];
vy=f[body_i+ (size/5)*4];
double angle;
double Ax,Ay;
fout[body_i]=datos[body_i];
for (int t = 0; t < T; ++t){
__syncthreads();
Ax=0.0,Ay=0.0;
autx=datos[body_i+ (size/5) ];
auty=datos[body_i+ (size/5)*2];
auty=datos[body_i+ (size/5)*2];
for (int i = 0; i < size/5; ++i){
if (i!=body_i){
rx=autx-datos[i+ (size/5) ];
ry=auty-datos[i+ (size/5)*2];
angle=atan(ry/rx);
rx=datos[i]/sqrt(rx*rx+ry*ry+SOFTENINGG);
Ax += rx*cos(angle);
Ay += rx*sin(angle);
}
}
Ax*=NEWTON_GG*delta_t;
Ay*=NEWTON_GG*delta_t;
datos[body_i+ (size/5) ]=autx+vx*delta_t+Ax*delta_t;
datos[body_i+ (size/5)*2]=auty+vy*delta_t+Ay*delta_t;
vx=Ax+vx;
vy=Ay+vy;
}
fout[body_i+ (size/5) ]=autx+vx*delta_t+Ax*delta_t;
fout[body_i+ (size/5)*2]=auty+vy*delta_t+Ay*delta_t;
fout[body_i+ (size/5)*3]=Ax+vx;
fout[body_i+ (size/5)*4]=Ay+vy;
}
}
int main() {
hipEvent_t ct1, ct2, ct3, ct4;
clock_t t1, t2;
double ms;
char filename[] = "input.txt";
char filename_out[] = "-CPU-Resultado.txt";
char filename_aux[30];
char final[] = "final";
char directory[] = "data/";
char directory_aux[30];
float dt,dt2;
//int iterator=2;
int B;
double *f, *fout, *fhost, *fhostout, *faux,*ff;
int grid_size, block_size = 256;
ReadSoA(&fhost, &B, filename);
int size = B*5;
hipMalloc((void**)&f, size* sizeof(double));
hipMalloc((void**)&ff, size* sizeof(double));
hipMalloc((void**)&fout, size* sizeof(double));
hipMemcpy(f, fhost, size* sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(ff, fhost, size* sizeof(double), hipMemcpyHostToDevice);
int debug = 0;
if (debug){
printf("B: %d\n", B );
printf("size: %d\n", size);
printArray(size, fhost);
}
double delta_t = 0.01;
fhostout = new double[size];
if (debug){
printArray(size, fhost);
}
long T = 10000;
char integer_string[32];
char integer_string2[32];
/*** CPU ***/
int cpu = 1;
if (cpu){
t1 = clock();
for (long t = 0; t < T; t++){
N_body_CPU(size, delta_t, fhost, fhostout, t);
faux=fhost;
fhost = fhostout;
fhostout=faux;
if (t % 1000 == 0 || t == T-1){
sprintf(integer_string, "%d", t);
sprintf(integer_string2, "-%d", T);
strcpy(filename_aux, filename_out);
strcpy(directory_aux, directory);
writeSoA(&fhostout, B, size,
strcat(directory_aux, strcat(integer_string, strcat(integer_string2, filename_aux) ) ));
}
//printArray(size, fhostout);
//std::cout << "-----------------------" << std::endl;
}
t2 = clock();
if (debug){
printArray(size, fhost);
}
ms = 1000.0 * (double)(t2 - t1) / CLOCKS_PER_SEC;
std::cout << "Tiempo CPU : " << ms << "[ms]" << std::endl;
//writeSoA(&fhostout, B, size, strcat(final, filename_out) );
}
int long_simulation = 0;
if (long_simulation){
T = 20000*20;
}
/*** GPU ***/
int gpu1 = 1;
if (gpu1){
char filename_outGPU[] = "-GPU-Resultado.txt";
grid_size = (int)ceil((float) B / block_size);
hipEventCreate(&ct1);
hipEventCreate(&ct2);
hipEventRecord(ct1);
for (long t = 0; t < T; t++){
N_body_GPU<<<grid_size, block_size>>>(size, delta_t, f, fout);
faux = fout;
fout = f;
f = faux;
if (t % 1000 == 0 || t == T-1){
sprintf(integer_string, "%d", t);
sprintf(integer_string2, "-%d", T);
strcpy(filename_aux, filename_outGPU);
strcpy(directory_aux, directory);
hipMemcpy(fhostout, f, size* sizeof(double), hipMemcpyDeviceToHost);
writeSoA(&fhostout, B, size,
strcat(directory_aux, strcat(integer_string, strcat(integer_string2, filename_aux))) );
}
}
hipEventRecord(ct2);
hipEventSynchronize(ct2);
hipEventElapsedTime(&dt, ct1, ct2);
std::cout << "Tiempo GPU : " << dt << "[ms]" << std::endl;
hipMemcpy(fhostout, f, size* sizeof(double), hipMemcpyDeviceToHost);
//strcpy(filename_out, "GPU-Resultado.txt");
//writeSoA(&fhostout, B, size, filename_outGPU);
}
/*** GPU Fast ***/
char filename_outFPU[] = "data/FPU-Resultado.txt";
grid_size = (int)ceil((float) B / block_size);
hipEventCreate(&ct3);
hipEventCreate(&ct4);
hipEventRecord(ct3);
N_body_GPU_F<<<grid_size, block_size,B*3* sizeof(double)>>>(size, delta_t, ff, fout,T);
hipEventRecord(ct4);
hipEventSynchronize(ct4);
hipEventElapsedTime(&dt2, ct3, ct4);
std::cout << "Tiempo GPU-F: " << dt2 << "[ms]" << std::endl;
hipMemcpy(fhostout, fout, size* sizeof(double), hipMemcpyDeviceToHost);
writeSoA(&fhostout, B, size, filename_outFPU);
delete[] fhostout;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#include<cmath>
const double NEWTON_G = 6.67384e-11;
const double SOFTENING = 1e-9f;
__constant__ double NEWTON_GG = 6.67384e-11;
__constant__ double SOFTENINGG = 1e-9f;
void writeSoA(double** f, int B, int size, const char *filename){
FILE* file;
file=fopen(filename, "w");
fprintf(file, "%d\n", B);
for (int i = 0; i < 5; i++){
for (int j = 0; j < size/5; j++){
fprintf(file, "%lf ", ((*f)[j + i*(size/5)]));
}
fprintf(file, "\n");
}
fclose(file);
}
void ReadSoA(double** f, int* B, const char *filename) {
FILE *fp;
fp = fopen(filename, "r");
fscanf(fp, "%d", B);
int size = (*B) * 5; // 5 atributos: masa, pos_x, pos_y, vel_x, vel_y
double* F = new double[size];
int i;
for (i = 0; i < size; i++) {
fscanf(fp, "%lf ", &(F[i]));
}
*f = F;
fclose(fp);
}
void printArray(int size, double *arr) {
printf("[");
for (int i = 0; i < size; i++) {
printf("%lf ", arr[i]);
}
printf("]\n");
}
void N_body_CPU(int size, double delta_t, double *f, double *fout, int T){
//printf("N_body_CPU\n");
for (int body_i = 0; body_i < size/5; body_i++){ // para cada cuerpo
//printf("body %d ", body_i);
//if (body_i == 95 && T == 0) printf("(%lf, %lf, %lf, %lf, %lf)\n", f[body_i], f[body_i + (size/5)], f[body_i + (size/5)*2], f[body_i + (size/5)*3], f[body_i + (size/5)*4]);
double mass1 = f[body_i];
double x1 = f[body_i + (size/5)];
double y1 = f[body_i + (size/5)*2];
double vx1 = f[body_i + (size/5)*3];
double vy1 = f[body_i + (size/5)*4];
double Fx = 0;
double Fy = 0;
for (int j = 0; j < size/5; j++){ // comparar con otros cuerpos
if (j == body_i) continue; // creo que puedo obviarlo pues el radio seria cero (aunque nos da division por cero)
double mass2 = f[j];
double x2 = f[j + (size/5)];
double y2 = f[j + (size/5)*2];
double distance = sqrt( pow(x2-x1, 2) + pow(y2-y1, 2) + pow(SOFTENING, 2) );
//if (body_i == 0) printf("distance: %lf\n", distance);
double angle = atan((y2-y1)/(x2-x1));
Fx += NEWTON_G*mass1*mass2/(pow(distance, 2)) * cos(angle);
Fy += NEWTON_G*mass1*mass2/(pow(distance, 2)) * sin(angle);
}
double new_vx1 = vx1 + Fx*delta_t/mass1;
double new_vy1 = vy1 + Fy*delta_t/mass1;
// a futuro, usar otro arreglo para la masa, pues no cambia
fout[body_i] = mass1;
fout[body_i + (size/5)] = x1 + new_vx1*delta_t; //new x
fout[body_i + (size/5)*2] = y1 + new_vy1*delta_t ; //new y
fout[body_i + (size/5)*3] = new_vx1; //new vx
fout[body_i + (size/5)*4] = new_vy1; //new vy
}
}
__global__ void N_body_GPU(int size, double delta_t, double *f, double *fout){
int body_i= threadIdx.x + blockDim.x*blockIdx.x;
if (body_i < size/5){
double mass1 = f[body_i];
double x1 = f[body_i + (size/5)];
double y1 = f[body_i + (size/5)*2];
double vx1 = f[body_i + (size/5)*3];
double vy1 = f[body_i + (size/5)*4];
double mass2,x2,y2,distance,angle,new_vx1,new_vy1;
double Fx = 0;
double Fy = 0;
for (int j = 0; j < size/5; j++){ // comparar con otros cuerpos
if (j != body_i){
mass2 = f[j];
x2 = f[j + (size/5)];
y2 = f[j + (size/5)*2];
distance = sqrt( (x2-x1)*(x2-x1) + (y2-y1)*(y2-y1) + SOFTENINGG);
//printf("distance: %lf\n", distance);
angle = atan((y2-y1)/(x2-x1));
Fx += NEWTON_GG*mass2/(pow(distance, 2)) * cos(angle);
Fy += NEWTON_GG*mass2/(pow(distance, 2)) * sin(angle);
}
}
//printf("F: %lf\n", F);
new_vx1 = vx1 + Fx*delta_t;
new_vy1 = vy1 + Fy*delta_t;
//printf("F*delta_t/mass1: %lf\n", F*delta_t/mass1);
//printf("new_vx1: %lf\n", new_vx1);
//printf("new_vy1: %lf\n", new_vy1);
// a futuro, usar otro arreglo para la masa, pues no cambia
fout[body_i] = mass1;
fout[body_i + (size/5)] = x1 + new_vx1*delta_t; //new x
fout[body_i + (size/5)*2] = y1 + new_vy1*delta_t ; //new y
fout[body_i + (size/5)*3] = new_vx1; //new vx
fout[body_i + (size/5)*4] = new_vy1; //new vy
}
}
__global__ void N_body_GPU_F(int size, double delta_t, double *f, double *fout,int T){
int body_i= threadIdx.x + blockDim.x*blockIdx.x;
if (body_i<size/5){
extern __shared__ double datos[];
// 5 atributos: masa
datos[body_i ]= f[body_i];
datos[body_i+ (size/5) ]= f[body_i + (size/5)];
datos[body_i+ (size/5)*2]= f[body_i + (size/5)*2];
double autx,auty,rx,ry,vx,vy;
vx=f[body_i+ (size/5)*3];
vy=f[body_i+ (size/5)*4];
double angle;
double Ax,Ay;
fout[body_i]=datos[body_i];
for (int t = 0; t < T; ++t){
__syncthreads();
Ax=0.0,Ay=0.0;
autx=datos[body_i+ (size/5) ];
auty=datos[body_i+ (size/5)*2];
auty=datos[body_i+ (size/5)*2];
for (int i = 0; i < size/5; ++i){
if (i!=body_i){
rx=autx-datos[i+ (size/5) ];
ry=auty-datos[i+ (size/5)*2];
angle=atan(ry/rx);
rx=datos[i]/sqrt(rx*rx+ry*ry+SOFTENINGG);
Ax += rx*cos(angle);
Ay += rx*sin(angle);
}
}
Ax*=NEWTON_GG*delta_t;
Ay*=NEWTON_GG*delta_t;
datos[body_i+ (size/5) ]=autx+vx*delta_t+Ax*delta_t;
datos[body_i+ (size/5)*2]=auty+vy*delta_t+Ay*delta_t;
vx=Ax+vx;
vy=Ay+vy;
}
fout[body_i+ (size/5) ]=autx+vx*delta_t+Ax*delta_t;
fout[body_i+ (size/5)*2]=auty+vy*delta_t+Ay*delta_t;
fout[body_i+ (size/5)*3]=Ax+vx;
fout[body_i+ (size/5)*4]=Ay+vy;
}
}
int main() {
hipEvent_t ct1, ct2, ct3, ct4;
clock_t t1, t2;
double ms;
char filename[] = "input.txt";
char filename_out[] = "-CPU-Resultado.txt";
char filename_aux[30];
char final[] = "final";
char directory[] = "data/";
char directory_aux[30];
float dt,dt2;
//int iterator=2;
int B;
double *f, *fout, *fhost, *fhostout, *faux,*ff;
int grid_size, block_size = 256;
ReadSoA(&fhost, &B, filename);
int size = B*5;
hipMalloc((void**)&f, size* sizeof(double));
hipMalloc((void**)&ff, size* sizeof(double));
hipMalloc((void**)&fout, size* sizeof(double));
hipMemcpy(f, fhost, size* sizeof(double), hipMemcpyHostToDevice);
hipMemcpy(ff, fhost, size* sizeof(double), hipMemcpyHostToDevice);
int debug = 0;
if (debug){
printf("B: %d\n", B );
printf("size: %d\n", size);
printArray(size, fhost);
}
double delta_t = 0.01;
fhostout = new double[size];
if (debug){
printArray(size, fhost);
}
long T = 10000;
char integer_string[32];
char integer_string2[32];
/*** CPU ***/
int cpu = 1;
if (cpu){
t1 = clock();
for (long t = 0; t < T; t++){
N_body_CPU(size, delta_t, fhost, fhostout, t);
faux=fhost;
fhost = fhostout;
fhostout=faux;
if (t % 1000 == 0 || t == T-1){
sprintf(integer_string, "%d", t);
sprintf(integer_string2, "-%d", T);
strcpy(filename_aux, filename_out);
strcpy(directory_aux, directory);
writeSoA(&fhostout, B, size,
strcat(directory_aux, strcat(integer_string, strcat(integer_string2, filename_aux) ) ));
}
//printArray(size, fhostout);
//std::cout << "-----------------------" << std::endl;
}
t2 = clock();
if (debug){
printArray(size, fhost);
}
ms = 1000.0 * (double)(t2 - t1) / CLOCKS_PER_SEC;
std::cout << "Tiempo CPU : " << ms << "[ms]" << std::endl;
//writeSoA(&fhostout, B, size, strcat(final, filename_out) );
}
int long_simulation = 0;
if (long_simulation){
T = 20000*20;
}
/*** GPU ***/
int gpu1 = 1;
if (gpu1){
char filename_outGPU[] = "-GPU-Resultado.txt";
grid_size = (int)ceil((float) B / block_size);
hipEventCreate(&ct1);
hipEventCreate(&ct2);
hipEventRecord(ct1);
for (long t = 0; t < T; t++){
N_body_GPU<<<grid_size, block_size>>>(size, delta_t, f, fout);
faux = fout;
fout = f;
f = faux;
if (t % 1000 == 0 || t == T-1){
sprintf(integer_string, "%d", t);
sprintf(integer_string2, "-%d", T);
strcpy(filename_aux, filename_outGPU);
strcpy(directory_aux, directory);
hipMemcpy(fhostout, f, size* sizeof(double), hipMemcpyDeviceToHost);
writeSoA(&fhostout, B, size,
strcat(directory_aux, strcat(integer_string, strcat(integer_string2, filename_aux))) );
}
}
hipEventRecord(ct2);
hipEventSynchronize(ct2);
hipEventElapsedTime(&dt, ct1, ct2);
std::cout << "Tiempo GPU : " << dt << "[ms]" << std::endl;
hipMemcpy(fhostout, f, size* sizeof(double), hipMemcpyDeviceToHost);
//strcpy(filename_out, "GPU-Resultado.txt");
//writeSoA(&fhostout, B, size, filename_outGPU);
}
/*** GPU Fast ***/
char filename_outFPU[] = "data/FPU-Resultado.txt";
grid_size = (int)ceil((float) B / block_size);
hipEventCreate(&ct3);
hipEventCreate(&ct4);
hipEventRecord(ct3);
N_body_GPU_F<<<grid_size, block_size,B*3* sizeof(double)>>>(size, delta_t, ff, fout,T);
hipEventRecord(ct4);
hipEventSynchronize(ct4);
hipEventElapsedTime(&dt2, ct3, ct4);
std::cout << "Tiempo GPU-F: " << dt2 << "[ms]" << std::endl;
hipMemcpy(fhostout, fout, size* sizeof(double), hipMemcpyDeviceToHost);
writeSoA(&fhostout, B, size, filename_outFPU);
delete[] fhostout;
} | .text
.file "n_body.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z8writeSoAPPdiiPKc # -- Begin function _Z8writeSoAPPdiiPKc
.p2align 4, 0x90
.type _Z8writeSoAPPdiiPKc,@function
_Z8writeSoAPPdiiPKc: # @_Z8writeSoAPPdiiPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r12d
movl %esi, %ebp
movq %rdi, %r14
movl $.L.str, %esi
movq %rcx, %rdi
callq fopen
movq %rax, %r15
xorl %ebx, %ebx
movl $.L.str.1, %esi
movq %rax, %rdi
movl %ebp, %edx
xorl %eax, %eax
callq fprintf
movl %r12d, 12(%rsp) # 4-byte Spill
movslq %r12d, %rax
imulq $1717986919, %rax, %r13 # imm = 0x66666667
movq %r13, %rax
shrq $63, %rax
sarq $33, %r13
addl %eax, %r13d
xorl %ebp, %ebp
movq %r13, 16(%rsp) # 8-byte Spill
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_2: # %._crit_edge
# in Loop: Header=BB0_1 Depth=1
movl $10, %edi
movq %r15, %rsi
callq fputc@PLT
incq %rbp
movq 16(%rsp), %r13 # 8-byte Reload
addl %r13d, %ebx
cmpq $5, %rbp
je .LBB0_3
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
movl %ebx, %ebx
movq %rbx, %r12
cmpl $5, 12(%rsp) # 4-byte Folded Reload
jl .LBB0_2
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r14), %rax
movsd (%rax,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
incq %r12
decq %r13
jne .LBB0_4
jmp .LBB0_2
.LBB0_3:
movq %r15, %rdi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end0:
.size _Z8writeSoAPPdiiPKc, .Lfunc_end0-_Z8writeSoAPPdiiPKc
.cfi_endproc
# -- End function
.globl _Z7ReadSoAPPdPiPKc # -- Begin function _Z7ReadSoAPPdPiPKc
.p2align 4, 0x90
.type _Z7ReadSoAPPdPiPKc,@function
_Z7ReadSoAPPdPiPKc: # @_Z7ReadSoAPPdPiPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq %rdi, %rbx
movl $.L.str.4, %esi
movq %rdx, %rdi
callq fopen
movq %rax, %r14
movl $.L.str.5, %esi
movq %rax, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl (%r15), %r12d
leal (%r12,%r12,4), %ebp
movslq %ebp, %rax
shlq $3, %rax
testl %r12d, %r12d
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movq %rax, %r15
testl %r12d, %r12d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
cmpl $2, %ebp
movl $1, %r13d
cmovgel %ebp, %r13d
movq %r15, %r12
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $8, %r12
decq %r13
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq %r15, (%rbx)
movq %r14, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z7ReadSoAPPdPiPKc, .Lfunc_end1-_Z7ReadSoAPPdPiPKc
.cfi_endproc
# -- End function
.globl _Z10printArrayiPd # -- Begin function _Z10printArrayiPd
.p2align 4, 0x90
.type _Z10printArrayiPd,@function
_Z10printArrayiPd: # @_Z10printArrayiPd
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $91, %edi
callq putchar@PLT
testl %ebp, %ebp
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_2
.LBB2_3: # %._crit_edge
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end2:
.size _Z10printArrayiPd, .Lfunc_end2-_Z10printArrayiPd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10N_body_CPUidPdS_i
.LCPI3_0:
.quad 0x3dd2584c222c163e # double 6.6738400000000001E-11
.LCPI3_1:
.quad 0x3c32725dc050d040 # double 9.9999994343613787E-19
.LCPI3_2:
.quad 0x0000000000000000 # double 0
.text
.globl _Z10N_body_CPUidPdS_i
.p2align 4, 0x90
.type _Z10N_body_CPUidPdS_i,@function
_Z10N_body_CPUidPdS_i: # @_Z10N_body_CPUidPdS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 80(%rsp) # 8-byte Spill
movsd %xmm0, 72(%rsp) # 8-byte Spill
cmpl $5, %edi
jl .LBB3_7
# %bb.1: # %.lr.ph92
movq %rsi, %r14
movslq %edi, %rax
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rax
shrq $63, %rax
sarq $33, %rcx
addl %eax, %ecx
leal (%rcx,%rcx), %eax
leal (%rcx,%rcx,2), %edx
movq %rdx, 48(%rsp) # 8-byte Spill
movl %ecx, %ebp
shll $2, %ecx
movq %rcx, 64(%rsp) # 8-byte Spill
leaq (%rsi,%rbp,8), %r13
movq %rax, 56(%rsp) # 8-byte Spill
leaq (%rsi,%rax,8), %r12
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_6: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movsd 72(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movsd 16(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
mulsd %xmm1, %xmm3
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm0, %xmm3
movsd 112(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
addsd %xmm3, %xmm2
mulsd %xmm1, %xmm4
divsd %xmm0, %xmm4
movsd 96(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
addsd %xmm4, %xmm3
movq 80(%rsp), %rax # 8-byte Reload
movsd %xmm0, (%rax,%r15,8)
movapd %xmm2, %xmm0
mulsd %xmm1, %xmm0
movsd 24(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
addsd %xmm0, %xmm4
movq 104(%rsp), %rcx # 8-byte Reload
movsd %xmm4, (%rax,%rcx,8)
movapd %xmm3, %xmm0
mulsd %xmm1, %xmm0
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movq 136(%rsp), %rcx # 8-byte Reload
movsd %xmm1, (%rax,%rcx,8)
movq 128(%rsp), %rcx # 8-byte Reload
movsd %xmm2, (%rax,%rcx,8)
movq 120(%rsp), %rcx # 8-byte Reload
movsd %xmm3, (%rax,%rcx,8)
incq %r15
cmpq %rbp, %r15
je .LBB3_7
.LBB3_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movsd (%r14,%r15,8), %xmm1 # xmm1 = mem[0],zero
leaq (%r15,%rbp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 24(%rsp) # 8-byte Spill
movq 56(%rsp), %rax # 8-byte Reload
addq %r15, %rax
movq %rax, 136(%rsp) # 8-byte Spill
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 32(%rsp) # 8-byte Spill
movq 48(%rsp), %rax # 8-byte Reload
leaq (%r15,%rax), %rax
movq %rax, 128(%rsp) # 8-byte Spill
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 64(%rsp), %rax # 8-byte Reload
addq %r15, %rax
movq %rax, 120(%rsp) # 8-byte Spill
movsd (%r14,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 96(%rsp) # 8-byte Spill
movsd %xmm1, 88(%rsp) # 8-byte Spill
mulsd .LCPI3_0(%rip), %xmm1
movsd %xmm1, 152(%rsp) # 8-byte Spill
xorl %ebx, %ebx
xorpd %xmm0, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
xorpd %xmm4, %xmm4
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_8: # %call.sqrt
# in Loop: Header=BB3_3 Depth=2
movsd %xmm2, 8(%rsp) # 8-byte Spill
movsd %xmm3, 144(%rsp) # 8-byte Spill
callq sqrt
movsd 144(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
.LBB3_9: # %.split
# in Loop: Header=BB3_3 Depth=2
movsd %xmm0, 40(%rsp) # 8-byte Spill
divsd %xmm3, %xmm2
movapd %xmm2, %xmm0
callq atan
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd (%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
mulsd 152(%rsp), %xmm2 # 8-byte Folded Reload
movsd 40(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm1, %xmm1
divsd %xmm1, %xmm2
movsd %xmm2, (%rsp) # 8-byte Spill
callq cos
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd (%rsp), %xmm0 # 8-byte Folded Reload
movsd 160(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
addsd %xmm0, %xmm4
.LBB3_10: # in Loop: Header=BB3_3 Depth=2
incq %rbx
cmpq %rbx, %rbp
je .LBB3_6
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rbx, %r15
je .LBB3_10
# %bb.4: # in Loop: Header=BB3_3 Depth=2
movsd %xmm4, 160(%rsp) # 8-byte Spill
movsd (%r14,%rbx,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rsp) # 8-byte Spill
movsd (%r13,%rbx,8), %xmm3 # xmm3 = mem[0],zero
movsd (%r12,%rbx,8), %xmm2 # xmm2 = mem[0],zero
subsd 24(%rsp), %xmm3 # 8-byte Folded Reload
movapd %xmm3, %xmm1
mulsd %xmm3, %xmm1
subsd 32(%rsp), %xmm2 # 8-byte Folded Reload
movapd %xmm2, %xmm0
mulsd %xmm2, %xmm0
addsd %xmm1, %xmm0
addsd .LCPI3_1(%rip), %xmm0
ucomisd .LCPI3_2(%rip), %xmm0
jb .LBB3_8
# %bb.5: # in Loop: Header=BB3_3 Depth=2
sqrtsd %xmm0, %xmm0
jmp .LBB3_9
.LBB3_7: # %._crit_edge93
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10N_body_CPUidPdS_i, .Lfunc_end3-_Z10N_body_CPUidPdS_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__N_body_GPUidPdS_ # -- Begin function _Z25__device_stub__N_body_GPUidPdS_
.p2align 4, 0x90
.type _Z25__device_stub__N_body_GPUidPdS_,@function
_Z25__device_stub__N_body_GPUidPdS_: # @_Z25__device_stub__N_body_GPUidPdS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movsd %xmm0, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10N_body_GPUidPdS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z25__device_stub__N_body_GPUidPdS_, .Lfunc_end4-_Z25__device_stub__N_body_GPUidPdS_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__N_body_GPU_FidPdS_i # -- Begin function _Z27__device_stub__N_body_GPU_FidPdS_i
.p2align 4, 0x90
.type _Z27__device_stub__N_body_GPU_FidPdS_i,@function
_Z27__device_stub__N_body_GPU_FidPdS_i: # @_Z27__device_stub__N_body_GPU_FidPdS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movsd %xmm0, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12N_body_GPU_FidPdS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z27__device_stub__N_body_GPU_FidPdS_i, .Lfunc_end5-_Z27__device_stub__N_body_GPU_FidPdS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI6_0:
.byte 45 # 0x2d
.byte 67 # 0x43
.byte 80 # 0x50
.byte 85 # 0x55
.byte 45 # 0x2d
.byte 82 # 0x52
.byte 101 # 0x65
.byte 115 # 0x73
.byte 117 # 0x75
.byte 108 # 0x6c
.byte 116 # 0x74
.byte 97 # 0x61
.byte 100 # 0x64
.byte 111 # 0x6f
.byte 46 # 0x2e
.byte 116 # 0x74
.LCPI6_4:
.byte 45 # 0x2d
.byte 71 # 0x47
.byte 80 # 0x50
.byte 85 # 0x55
.byte 45 # 0x2d
.byte 82 # 0x52
.byte 101 # 0x65
.byte 115 # 0x73
.byte 117 # 0x75
.byte 108 # 0x6c
.byte 116 # 0x74
.byte 97 # 0x61
.byte 100 # 0x64
.byte 111 # 0x6f
.byte 46 # 0x2e
.byte 116 # 0x74
.LCPI6_6:
.byte 100 # 0x64
.byte 97 # 0x61
.byte 116 # 0x74
.byte 97 # 0x61
.byte 47 # 0x2f
.byte 70 # 0x46
.byte 80 # 0x50
.byte 85 # 0x55
.byte 45 # 0x2d
.byte 82 # 0x52
.byte 101 # 0x65
.byte 115 # 0x73
.byte 117 # 0x75
.byte 108 # 0x6c
.byte 116 # 0x74
.byte 97 # 0x61
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI6_1:
.quad 0x3f847ae147ae147b # double 0.01
.LCPI6_2:
.quad 0x408f400000000000 # double 1000
.LCPI6_3:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI6_5:
.long 0x3b800000 # float 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $472, %rsp # imm = 0x1D8
.cfi_def_cfa_offset 528
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $8679613459571175017, %rax # imm = 0x78742E7475706E69
movq %rax, 286(%rsp)
movw $116, 294(%rsp)
movaps .LCPI6_0(%rip), %xmm0 # xmm0 = [45,67,80,85,45,82,101,115,117,108,116,97,100,111,46,116]
movaps %xmm0, 304(%rsp)
movw $29816, 320(%rsp) # imm = 0x7478
movb $0, 322(%rsp)
movl $1635017060, 42(%rsp) # imm = 0x61746164
movw $47, 46(%rsp)
leaq 286(%rsp), %rdi
movl $.L.str.4, %esi
callq fopen
movq %rax, %r14
leaq 4(%rsp), %rdx
movl $.L.str.5, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %r12d
leal (%r12,%r12,4), %ebp
movslq %ebp, %rdi
shlq $3, %rdi
testl %r12d, %r12d
movq $-1, %rbx
cmovsq %rbx, %rdi
callq _Znam
movq %rax, %r15
testl %r12d, %r12d
jle .LBB6_3
# %bb.1: # %.lr.ph.preheader.i
cmpl $2, %ebp
movl $1, %r13d
cmovgel %ebp, %r13d
movq %r15, %r12
.p2align 4, 0x90
.LBB6_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $8, %r12
decq %r13
jne .LBB6_2
.LBB6_3: # %_Z7ReadSoAPPdPiPKc.exit
movq %r14, %rdi
callq fclose
movslq 4(%rsp), %r14
leaq (%r14,%r14,4), %rax
movq %rax, 80(%rsp) # 8-byte Spill
leaq (,%rax,8), %r12
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 224(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 224(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
testq %r14, %r14
movl %r14d, %r13d
movq %r12, 56(%rsp) # 8-byte Spill
cmovnsq %r12, %rbx
movq %rbx, %rdi
callq _Znam
movq %rax, %r14
callq clock
movq %rax, 296(%rsp) # 8-byte Spill
xorl %ebp, %ebp
movabsq $2361183241434822607, %r12 # imm = 0x20C49BA5E353F7CF
jmp .LBB6_4
.p2align 4, 0x90
.LBB6_11: # %_Z8writeSoAPPdiiPKc.exit
# in Loop: Header=BB6_4 Depth=1
movq %r15, %rdi
callq fclose
movq 8(%rsp), %rbx # 8-byte Reload
movabsq $2361183241434822607, %r12 # imm = 0x20C49BA5E353F7CF
movq 24(%rsp), %r14 # 8-byte Reload
movq 72(%rsp), %rbp # 8-byte Reload
.LBB6_12: # in Loop: Header=BB6_4 Depth=1
incq %rbp
movq %r14, %r15
movq %rbx, %r14
cmpq $10000, %rbp # imm = 0x2710
je .LBB6_13
.LBB6_4: # =>This Loop Header: Depth=1
# Child Loop BB6_7 Depth 2
# Child Loop BB6_9 Depth 3
movq %r15, %rbx
movq 80(%rsp), %rdi # 8-byte Reload
# kill: def $edi killed $edi killed $rdi
movsd .LCPI6_1(%rip), %xmm0 # xmm0 = mem[0],zero
movq %r15, %rsi
movq %r14, %rdx
callq _Z10N_body_CPUidPdS_i
movq %rbp, %rax
shrq $3, %rax
mulq %r12
cmpq $9999, %rbp # imm = 0x270F
movq %r15, 8(%rsp) # 8-byte Spill
je .LBB6_6
# %bb.5: # in Loop: Header=BB6_4 Depth=1
shrq $4, %rdx
imulq $1000, %rdx, %rax # imm = 0x3E8
movq %rbp, %rcx
subq %rax, %rcx
jne .LBB6_12
.LBB6_6: # in Loop: Header=BB6_4 Depth=1
movq %r14, 24(%rsp) # 8-byte Spill
movq %rbp, %rdx
xorl %ebp, %ebp
movl $.L.str.5, %esi
leaq 336(%rsp), %rbx
movq %rbx, %rdi
movq %rdx, 72(%rsp) # 8-byte Spill
xorl %eax, %eax
callq sprintf
movl $.L.str.10, %esi
movl $10000, %edx # imm = 0x2710
leaq 432(%rsp), %r14
movq %r14, %rdi
xorl %eax, %eax
callq sprintf
leaq 400(%rsp), %r15
movq %r15, %rdi
leaq 304(%rsp), %rsi
callq strcpy
leaq 368(%rsp), %r12
movq %r12, %rdi
leaq 42(%rsp), %rsi
callq strcpy
movl 4(%rsp), %eax
movl %eax, 64(%rsp) # 4-byte Spill
movq %r14, %rdi
movq %r15, %rsi
callq strcat
movq %rbx, %rdi
movq %r14, %rsi
callq strcat
movq %r12, %rdi
movq %rbx, %rsi
callq strcat
movl $.L.str, %esi
movq %r12, %rdi
callq fopen
movq %rax, %r15
movl $.L.str.1, %esi
movq %rax, %rdi
movl 64(%rsp), %edx # 4-byte Reload
xorl %eax, %eax
callq fprintf
xorl %r14d, %r14d
jmp .LBB6_7
.p2align 4, 0x90
.LBB6_10: # %._crit_edge.i
# in Loop: Header=BB6_7 Depth=2
movl $10, %edi
movq %r15, %rsi
callq fputc@PLT
incq %r14
addl %r13d, %ebp
cmpq $5, %r14
je .LBB6_11
.LBB6_7: # %.preheader.i
# Parent Loop BB6_4 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_9 Depth 3
testl %r13d, %r13d
jle .LBB6_10
# %bb.8: # %.lr.ph.i69
# in Loop: Header=BB6_7 Depth=2
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB6_9: # Parent Loop BB6_4 Depth=1
# Parent Loop BB6_7 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %esi
movq %r15, %rdi
movb $1, %al
callq fprintf
incq %r12
cmpq %r12, %r13
jne .LBB6_9
jmp .LBB6_10
.LBB6_13:
callq clock
subq 296(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
mulsd .LCPI6_2(%rip), %xmm0
divsd .LCPI6_3(%rip), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.12, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB6_47
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB6_16
# %bb.15:
movzbl 67(%r15), %eax
jmp .LBB6_17
.LBB6_16:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB6_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movabsq $4294967296, %r15 # imm = 0x100000000
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movaps .LCPI6_4(%rip), %xmm0 # xmm0 = [45,71,80,85,45,82,101,115,117,108,116,97,100,111,46,116]
movaps %xmm0, 192(%rsp)
xorps %xmm0, %xmm0
cvtsi2ssl 4(%rsp), %xmm0
movw $29816, 208(%rsp) # imm = 0x7478
movb $0, 210(%rsp)
mulss .LCPI6_5(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r14d
leaq 232(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
movq 232(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq %r15, %r14
leaq 256(%r15), %rbp
xorl %r15d, %r15d
movq %rbp, 72(%rsp) # 8-byte Spill
movq %r14, 64(%rsp) # 8-byte Spill
jmp .LBB6_18
.p2align 4, 0x90
.LBB6_27: # %_Z8writeSoAPPdiiPKc.exit85
# in Loop: Header=BB6_18 Depth=1
movq %r14, %rdi
callq fclose
movq 8(%rsp), %rbx # 8-byte Reload
movabsq $2361183241434822607, %r12 # imm = 0x20C49BA5E353F7CF
movq 72(%rsp), %rbp # 8-byte Reload
movq 64(%rsp), %r14 # 8-byte Reload
movq 24(%rsp), %r15 # 8-byte Reload
.LBB6_28: # in Loop: Header=BB6_18 Depth=1
incq %r15
cmpq $10000, %r15 # imm = 0x2710
je .LBB6_29
.LBB6_18: # =>This Loop Header: Depth=1
# Child Loop BB6_23 Depth 2
# Child Loop BB6_25 Depth 3
movq %r14, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_20
# %bb.19: # in Loop: Header=BB6_18 Depth=1
movq 16(%rsp), %rax
movq 32(%rsp), %rcx
movq 80(%rsp), %rdx # 8-byte Reload
movl %edx, 48(%rsp)
movabsq $4576918229304087675, %rdx # imm = 0x3F847AE147AE147B
movq %rdx, 168(%rsp)
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 240(%rsp)
leaq 168(%rsp), %rax
movq %rax, 248(%rsp)
leaq 160(%rsp), %rax
movq %rax, 256(%rsp)
leaq 152(%rsp), %rax
movq %rax, 264(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
movl $_Z10N_body_GPUidPdS_, %edi
leaq 240(%rsp), %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_20: # in Loop: Header=BB6_18 Depth=1
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movq %rcx, 32(%rsp)
movq %rax, 16(%rsp)
movq %r15, %rax
shrq $3, %rax
mulq %r12
cmpq $9999, %r15 # imm = 0x270F
je .LBB6_22
# %bb.21: # in Loop: Header=BB6_18 Depth=1
shrq $4, %rdx
imulq $1000, %rdx, %rax # imm = 0x3E8
movq %r15, %rcx
subq %rax, %rcx
jne .LBB6_28
.LBB6_22: # in Loop: Header=BB6_18 Depth=1
xorl %r12d, %r12d
movl $.L.str.5, %esi
leaq 336(%rsp), %rdi
movq %r15, 24(%rsp) # 8-byte Spill
movq %r15, %rdx
xorl %eax, %eax
callq sprintf
movl $.L.str.10, %esi
movl $10000, %edx # imm = 0x2710
leaq 432(%rsp), %rbp
movq %rbp, %rdi
xorl %eax, %eax
callq sprintf
movq %rbx, %r15
leaq 400(%rsp), %rbx
movq %rbx, %rdi
leaq 192(%rsp), %rsi
callq strcpy
leaq 368(%rsp), %r14
movq %r14, %rdi
leaq 42(%rsp), %rsi
callq strcpy
movq 16(%rsp), %rsi
movq %r15, %rdi
movq 56(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl 4(%rsp), %r15d
movq %rbp, %rdi
movq %rbx, %rsi
callq strcat
leaq 336(%rsp), %rbx
movq %rbx, %rdi
movq %rbp, %rsi
callq strcat
movq %r14, %rdi
movq %rbx, %rsi
callq strcat
movl $.L.str, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r14
movl $.L.str.1, %esi
movq %rax, %rdi
movl %r15d, %edx
xorl %eax, %eax
callq fprintf
xorl %r15d, %r15d
jmp .LBB6_23
.p2align 4, 0x90
.LBB6_26: # %._crit_edge.i76
# in Loop: Header=BB6_23 Depth=2
movl $10, %edi
movq %r14, %rsi
callq fputc@PLT
incq %r15
addl %r13d, %r12d
cmpq $5, %r15
je .LBB6_27
.LBB6_23: # %.preheader.i74
# Parent Loop BB6_18 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_25 Depth 3
testl %r13d, %r13d
jle .LBB6_26
# %bb.24: # %.lr.ph.i80
# in Loop: Header=BB6_23 Depth=2
movl %r12d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB6_25: # Parent Loop BB6_18 Depth=1
# Parent Loop BB6_23 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rbx,%rbp,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incq %rbp
cmpq %rbp, %r13
jne .LBB6_25
jmp .LBB6_26
.LBB6_29:
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 96(%rsp), %rdi
callq hipEventSynchronize
movq 232(%rsp), %rsi
movq 96(%rsp), %rdx
leaq 180(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 180(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.12, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB6_47
# %bb.30: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i105
cmpb $0, 56(%r15)
je .LBB6_32
# %bb.31:
movzbl 67(%r15), %eax
jmp .LBB6_33
.LBB6_32:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB6_33: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit108
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq 56(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movaps .LCPI6_6(%rip), %xmm0 # xmm0 = [100,97,116,97,47,70,80,85,45,82,101,115,117,108,116,97]
movaps %xmm0, 192(%rsp)
movl $1949200228, 208(%rsp) # imm = 0x742E6F64
xorps %xmm0, %xmm0
cvtsi2ssl 4(%rsp), %xmm0
movw $29816, 212(%rsp) # imm = 0x7478
movb $0, 214(%rsp)
mulss .LCPI6_5(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r14d
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movslq 4(%rsp), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %r8
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r14
movq %r14, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_35
# %bb.34:
movq 224(%rsp), %rax
movq 32(%rsp), %rcx
movq 80(%rsp), %rdx # 8-byte Reload
movl %edx, 188(%rsp)
movabsq $4576918229304087675, %rdx # imm = 0x3F847AE147AE147B
movq %rdx, 168(%rsp)
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movl $10000, 184(%rsp) # imm = 0x2710
leaq 188(%rsp), %rax
movq %rax, 240(%rsp)
leaq 168(%rsp), %rax
movq %rax, 248(%rsp)
leaq 160(%rsp), %rax
movq %rax, 256(%rsp)
leaq 152(%rsp), %rax
movq %rax, 264(%rsp)
leaq 184(%rsp), %rax
movq %rax, 272(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z12N_body_GPU_FidPdS_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_35:
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 88(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 88(%rsp), %rdx
leaq 240(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 240(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.12, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB6_47
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i110
cmpb $0, 56(%r15)
je .LBB6_38
# %bb.37:
movzbl 67(%r15), %eax
jmp .LBB6_39
.LBB6_38:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB6_39: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit113
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 32(%rsp), %rsi
movq %rbx, %rdi
movq 56(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl 4(%rsp), %ebp
leaq 192(%rsp), %rdi
movl $.L.str, %esi
callq fopen
movq %rax, %r14
xorl %r15d, %r15d
movl $.L.str.1, %esi
movq %rax, %rdi
movl %ebp, %edx
xorl %eax, %eax
callq fprintf
xorl %r12d, %r12d
jmp .LBB6_40
.p2align 4, 0x90
.LBB6_43: # %._crit_edge.i94
# in Loop: Header=BB6_40 Depth=1
movl $10, %edi
movq %r14, %rsi
callq fputc@PLT
incq %r12
addl %r13d, %r15d
cmpq $5, %r12
je .LBB6_44
.LBB6_40: # %.preheader.i92
# =>This Loop Header: Depth=1
# Child Loop BB6_42 Depth 2
testl %r13d, %r13d
jle .LBB6_43
# %bb.41: # %.lr.ph.i98
# in Loop: Header=BB6_40 Depth=1
movl %r15d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB6_42: # Parent Loop BB6_40 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%rbp,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %esi
movq %r14, %rdi
movb $1, %al
callq fprintf
incq %rbp
cmpq %rbp, %r13
jne .LBB6_42
jmp .LBB6_43
.LBB6_44: # %_Z8writeSoAPPdiiPKc.exit103
movq %r14, %rdi
callq fclose
movq 8(%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB6_46
# %bb.45:
callq _ZdaPv
.LBB6_46:
xorl %eax, %eax
addq $472, %rsp # imm = 0x1D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_47:
.cfi_def_cfa_offset 528
callq _ZSt16__throw_bad_castv
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10N_body_GPUidPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12N_body_GPU_FidPdS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $NEWTON_GG, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $SOFTENINGG, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type NEWTON_GG,@object # @NEWTON_GG
.local NEWTON_GG
.comm NEWTON_GG,8,8
.type SOFTENINGG,@object # @SOFTENINGG
.local SOFTENINGG
.comm SOFTENINGG,8,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "w"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%lf "
.size .L.str.2, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d"
.size .L.str.5, 3
.type _Z10N_body_GPUidPdS_,@object # @_Z10N_body_GPUidPdS_
.section .rodata,"a",@progbits
.globl _Z10N_body_GPUidPdS_
.p2align 3, 0x0
_Z10N_body_GPUidPdS_:
.quad _Z25__device_stub__N_body_GPUidPdS_
.size _Z10N_body_GPUidPdS_, 8
.type _Z12N_body_GPU_FidPdS_i,@object # @_Z12N_body_GPU_FidPdS_i
.globl _Z12N_body_GPU_FidPdS_i
.p2align 3, 0x0
_Z12N_body_GPU_FidPdS_i:
.quad _Z27__device_stub__N_body_GPU_FidPdS_i
.size _Z12N_body_GPU_FidPdS_i, 8
.type .L.str.10,@object # @.str.10
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.10:
.asciz "-%d"
.size .L.str.10, 4
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Tiempo CPU : "
.size .L.str.11, 15
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "[ms]"
.size .L.str.12, 5
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Tiempo GPU : "
.size .L.str.13, 15
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Tiempo GPU-F: "
.size .L.str.14, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10N_body_GPUidPdS_"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12N_body_GPU_FidPdS_i"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "NEWTON_GG"
.size .L__unnamed_3, 10
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "SOFTENINGG"
.size .L__unnamed_4, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "]"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__N_body_GPUidPdS_
.addrsig_sym _Z27__device_stub__N_body_GPU_FidPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym NEWTON_GG
.addrsig_sym SOFTENINGG
.addrsig_sym _Z10N_body_GPUidPdS_
.addrsig_sym _Z12N_body_GPU_FidPdS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrixAddKernel1(float* ans, float* M, float* N, int size) {
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
if((row < size) && (col < size)) {
ans[row*size + col] = M[row*size + col] + N[row*size + col];
}
} | code for sm_80
Function : _Z16matrixAddKernel1PfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
Subsets and Splits